4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
112 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
113 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
114 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
116 #define I40E_FLOW_TYPES ( \
117 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
122 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
127 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
129 /* Additional timesync values. */
130 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
131 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
132 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
133 #define I40E_PRTTSYN_TSYNENA 0x80000000
134 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
135 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
137 #define I40E_MAX_PERCENT 100
138 #define I40E_DEFAULT_DCB_APP_NUM 1
139 #define I40E_DEFAULT_DCB_APP_PRIO 3
141 #define I40E_INSET_NONE 0x00000000000000000ULL
144 #define I40E_INSET_DMAC 0x0000000000000001ULL
145 #define I40E_INSET_SMAC 0x0000000000000002ULL
146 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
147 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
148 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
151 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
152 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
153 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
154 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
155 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
156 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
157 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
159 /* bit 16 ~ bit 31 */
160 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
161 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
162 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
163 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
164 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
165 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
166 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
167 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
169 /* bit 32 ~ bit 47, tunnel fields */
170 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
171 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
172 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
173 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
174 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
175 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
177 /* bit 48 ~ bit 55 */
178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
180 /* bit 56 ~ bit 63, Flex Payload */
181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD \
190 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
191 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
192 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
193 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
196 * Below are values for writing un-exposed registers suggested
199 /* Destination MAC address */
200 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
201 /* Source MAC address */
202 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
206 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
207 /* Single VLAN tag in the inner L2 header */
208 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
209 /* Source IPv4 address */
210 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
211 /* Destination IPv4 address */
212 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
213 /* Source IPv4 address for X722 */
214 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
215 /* Destination IPv4 address for X722 */
216 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
217 /* IPv4 Protocol for X722 */
218 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
219 /* IPv4 Time to Live for X722 */
220 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
221 /* IPv4 Type of Service (TOS) */
222 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
224 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
225 /* IPv4 Time to Live */
226 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
227 /* Source IPv6 address */
228 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
229 /* Destination IPv6 address */
230 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
231 /* IPv6 Traffic Class (TC) */
232 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
233 /* IPv6 Next Header */
234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
238 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
239 /* Destination L4 port */
240 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
241 /* SCTP verification tag */
242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
245 /* Source port of tunneling UDP */
246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
247 /* Destination port of tunneling UDP */
248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
249 /* UDP Tunneling ID, NVGRE/GRE key */
250 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
251 /* Last ether type */
252 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
253 /* Tunneling outer destination IPv4 address */
254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
255 /* Tunneling outer destination IPv6 address */
256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
257 /* 1st word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
259 /* 2nd word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
261 /* 3rd word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
263 /* 4th word of flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
265 /* 5th word of flex payload */
266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
267 /* 6th word of flex payload */
268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
269 /* 7th word of flex payload */
270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
271 /* 8th word of flex payload */
272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
273 /* all 8 words flex payload */
274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
275 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
277 #define I40E_TRANSLATE_INSET 0
278 #define I40E_TRANSLATE_REG 1
280 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
281 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
282 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
283 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
285 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
287 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
290 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
292 /* PCI offset for querying capability */
293 #define PCI_DEV_CAP_REG 0xA4
294 /* PCI offset for enabling/disabling Extended Tag */
295 #define PCI_DEV_CTRL_REG 0xA8
296 /* Bit mask of Extended Tag capability */
297 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
298 /* Bit shift of Extended Tag enable/disable */
299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
300 /* Bit mask of Extended Tag enable/disable */
301 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
305 static int i40e_dev_configure(struct rte_eth_dev *dev);
306 static int i40e_dev_start(struct rte_eth_dev *dev);
307 static void i40e_dev_stop(struct rte_eth_dev *dev);
308 static void i40e_dev_close(struct rte_eth_dev *dev);
309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
316 struct rte_eth_stats *stats);
317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
318 struct rte_eth_xstat *xstats, unsigned n);
319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
320 struct rte_eth_xstat_name *xstats_names,
322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
328 struct rte_eth_dev_info *dev_info);
329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
333 enum rte_vlan_type vlan_type,
335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
343 struct rte_eth_fc_conf *fc_conf);
344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
345 struct rte_eth_fc_conf *fc_conf);
346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
347 struct rte_eth_pfc_conf *pfc_conf);
348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
349 struct ether_addr *mac_addr,
352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
354 struct rte_eth_rss_reta_entry64 *reta_conf,
356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
357 struct rte_eth_rss_reta_entry64 *reta_conf,
360 static int i40e_get_cap(struct i40e_hw *hw);
361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
362 static int i40e_pf_setup(struct i40e_pf *pf);
363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
368 bool offset_loaded, uint64_t *offset, uint64_t *stat);
369 static void i40e_stat_update_48(struct i40e_hw *hw,
375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
376 static void i40e_dev_interrupt_handler(
377 __rte_unused struct rte_intr_handle *handle, void *param);
378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
379 uint32_t base, uint32_t num);
380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
386 static int i40e_veb_release(struct i40e_veb *veb);
387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
388 struct i40e_vsi *vsi);
389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
392 struct i40e_macvlan_filter *mv_f,
394 struct ether_addr *addr);
395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
396 struct i40e_macvlan_filter *mv_f,
399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
401 struct rte_eth_rss_conf *rss_conf);
402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
403 struct rte_eth_rss_conf *rss_conf);
404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
405 struct rte_eth_udp_tunnel *udp_tunnel);
406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
407 struct rte_eth_udp_tunnel *udp_tunnel);
408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
410 struct rte_eth_ethertype_filter *filter,
412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
413 enum rte_filter_op filter_op,
415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
416 enum rte_filter_type filter_type,
417 enum rte_filter_op filter_op,
419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
420 struct rte_eth_dcb_info *dcb_info);
421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
422 static void i40e_configure_registers(struct i40e_hw *hw);
423 static void i40e_hw_init(struct rte_eth_dev *dev);
424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
426 struct rte_eth_mirror_conf *mirror_conf,
427 uint8_t sw_id, uint8_t on);
428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
433 struct timespec *timestamp,
435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
436 struct timespec *timestamp);
437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
442 struct timespec *timestamp);
443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
444 const struct timespec *timestamp);
446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
451 static int i40e_get_regs(struct rte_eth_dev *dev,
452 struct rte_dev_reg_info *regs);
454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
457 struct rte_dev_eeprom_info *eeprom);
459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
460 struct ether_addr *mac_addr);
462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
464 static const struct rte_pci_id pci_id_i40e_map[] = {
465 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
466 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
467 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
468 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
469 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
470 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
471 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
472 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
473 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
474 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
475 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
476 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
477 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
478 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
479 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
480 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
481 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
482 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
483 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
484 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
485 { .vendor_id = 0, /* sentinel */ },
488 static const struct eth_dev_ops i40e_eth_dev_ops = {
489 .dev_configure = i40e_dev_configure,
490 .dev_start = i40e_dev_start,
491 .dev_stop = i40e_dev_stop,
492 .dev_close = i40e_dev_close,
493 .promiscuous_enable = i40e_dev_promiscuous_enable,
494 .promiscuous_disable = i40e_dev_promiscuous_disable,
495 .allmulticast_enable = i40e_dev_allmulticast_enable,
496 .allmulticast_disable = i40e_dev_allmulticast_disable,
497 .dev_set_link_up = i40e_dev_set_link_up,
498 .dev_set_link_down = i40e_dev_set_link_down,
499 .link_update = i40e_dev_link_update,
500 .stats_get = i40e_dev_stats_get,
501 .xstats_get = i40e_dev_xstats_get,
502 .xstats_get_names = i40e_dev_xstats_get_names,
503 .stats_reset = i40e_dev_stats_reset,
504 .xstats_reset = i40e_dev_stats_reset,
505 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
506 .dev_infos_get = i40e_dev_info_get,
507 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
508 .vlan_filter_set = i40e_vlan_filter_set,
509 .vlan_tpid_set = i40e_vlan_tpid_set,
510 .vlan_offload_set = i40e_vlan_offload_set,
511 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
512 .vlan_pvid_set = i40e_vlan_pvid_set,
513 .rx_queue_start = i40e_dev_rx_queue_start,
514 .rx_queue_stop = i40e_dev_rx_queue_stop,
515 .tx_queue_start = i40e_dev_tx_queue_start,
516 .tx_queue_stop = i40e_dev_tx_queue_stop,
517 .rx_queue_setup = i40e_dev_rx_queue_setup,
518 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
519 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
520 .rx_queue_release = i40e_dev_rx_queue_release,
521 .rx_queue_count = i40e_dev_rx_queue_count,
522 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
523 .tx_queue_setup = i40e_dev_tx_queue_setup,
524 .tx_queue_release = i40e_dev_tx_queue_release,
525 .dev_led_on = i40e_dev_led_on,
526 .dev_led_off = i40e_dev_led_off,
527 .flow_ctrl_get = i40e_flow_ctrl_get,
528 .flow_ctrl_set = i40e_flow_ctrl_set,
529 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
530 .mac_addr_add = i40e_macaddr_add,
531 .mac_addr_remove = i40e_macaddr_remove,
532 .reta_update = i40e_dev_rss_reta_update,
533 .reta_query = i40e_dev_rss_reta_query,
534 .rss_hash_update = i40e_dev_rss_hash_update,
535 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
536 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
537 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
538 .filter_ctrl = i40e_dev_filter_ctrl,
539 .rxq_info_get = i40e_rxq_info_get,
540 .txq_info_get = i40e_txq_info_get,
541 .mirror_rule_set = i40e_mirror_rule_set,
542 .mirror_rule_reset = i40e_mirror_rule_reset,
543 .timesync_enable = i40e_timesync_enable,
544 .timesync_disable = i40e_timesync_disable,
545 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
546 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
547 .get_dcb_info = i40e_dev_get_dcb_info,
548 .timesync_adjust_time = i40e_timesync_adjust_time,
549 .timesync_read_time = i40e_timesync_read_time,
550 .timesync_write_time = i40e_timesync_write_time,
551 .get_reg = i40e_get_regs,
552 .get_eeprom_length = i40e_get_eeprom_length,
553 .get_eeprom = i40e_get_eeprom,
554 .mac_addr_set = i40e_set_default_mac_addr,
555 .mtu_set = i40e_dev_mtu_set,
558 /* store statistics names and its offset in stats structure */
559 struct rte_i40e_xstats_name_off {
560 char name[RTE_ETH_XSTATS_NAME_SIZE];
564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
565 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
566 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
567 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
568 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
569 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
570 rx_unknown_protocol)},
571 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
572 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
573 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
574 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
578 sizeof(rte_i40e_stats_strings[0]))
580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
581 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
582 tx_dropped_link_down)},
583 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
584 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
587 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
589 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
591 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
593 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
594 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
595 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
596 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
597 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
598 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
600 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
602 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
604 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
606 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
608 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
610 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
612 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
614 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
615 mac_short_packet_dropped)},
616 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
618 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
619 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
620 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
622 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
624 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
626 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
628 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
630 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
632 {"rx_flow_director_atr_match_packets",
633 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
634 {"rx_flow_director_sb_match_packets",
635 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
636 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
638 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
640 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
642 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
647 sizeof(rte_i40e_hw_port_strings[0]))
649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
650 {"xon_packets", offsetof(struct i40e_hw_port_stats,
652 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
657 sizeof(rte_i40e_rxq_prio_strings[0]))
659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
660 {"xon_packets", offsetof(struct i40e_hw_port_stats,
662 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
664 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
665 priority_xon_2_xoff)},
668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
669 sizeof(rte_i40e_txq_prio_strings[0]))
671 static struct eth_driver rte_i40e_pmd = {
673 .id_table = pci_id_i40e_map,
674 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
675 RTE_PCI_DRV_DETACHABLE,
676 .probe = rte_eth_dev_pci_probe,
677 .remove = rte_eth_dev_pci_remove,
679 .eth_dev_init = eth_i40e_dev_init,
680 .eth_dev_uninit = eth_i40e_dev_uninit,
681 .dev_private_size = sizeof(struct i40e_adapter),
685 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
686 struct rte_eth_link *link)
688 struct rte_eth_link *dst = link;
689 struct rte_eth_link *src = &(dev->data->dev_link);
691 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
692 *(uint64_t *)src) == 0)
699 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
700 struct rte_eth_link *link)
702 struct rte_eth_link *dst = &(dev->data->dev_link);
703 struct rte_eth_link *src = link;
705 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
706 *(uint64_t *)src) == 0)
712 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
715 #ifndef I40E_GLQF_ORT
716 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
718 #ifndef I40E_GLQF_PIT
719 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
722 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
725 * Initialize registers for flexible payload, which should be set by NVM.
726 * This should be removed from code once it is fixed in NVM.
728 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
730 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
731 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
732 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
733 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
734 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
735 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
736 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
737 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
738 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
739 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
741 /* Initialize registers for parsing packet type of QinQ */
742 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
743 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
746 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
749 * Add a ethertype filter to drop all flow control frames transmitted
753 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
755 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
756 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
757 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
758 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
761 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
762 I40E_FLOW_CONTROL_ETHERTYPE, flags,
763 pf->main_vsi_seid, 0,
766 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
767 " frames from VSIs.");
771 floating_veb_list_handler(__rte_unused const char *key,
772 const char *floating_veb_value,
776 unsigned int count = 0;
779 bool *vf_floating_veb = opaque;
781 while (isblank(*floating_veb_value))
782 floating_veb_value++;
784 /* Reset floating VEB configuration for VFs */
785 for (idx = 0; idx < I40E_MAX_VF; idx++)
786 vf_floating_veb[idx] = false;
790 while (isblank(*floating_veb_value))
791 floating_veb_value++;
792 if (*floating_veb_value == '\0')
795 idx = strtoul(floating_veb_value, &end, 10);
796 if (errno || end == NULL)
798 while (isblank(*end))
802 } else if ((*end == ';') || (*end == '\0')) {
804 if (min == I40E_MAX_VF)
806 if (max >= I40E_MAX_VF)
807 max = I40E_MAX_VF - 1;
808 for (idx = min; idx <= max; idx++) {
809 vf_floating_veb[idx] = true;
816 floating_veb_value = end + 1;
817 } while (*end != '\0');
826 config_vf_floating_veb(struct rte_devargs *devargs,
827 uint16_t floating_veb,
828 bool *vf_floating_veb)
830 struct rte_kvargs *kvlist;
832 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
836 /* All the VFs attach to the floating VEB by default
837 * when the floating VEB is enabled.
839 for (i = 0; i < I40E_MAX_VF; i++)
840 vf_floating_veb[i] = true;
845 kvlist = rte_kvargs_parse(devargs->args, NULL);
849 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
850 rte_kvargs_free(kvlist);
853 /* When the floating_veb_list parameter exists, all the VFs
854 * will attach to the legacy VEB firstly, then configure VFs
855 * to the floating VEB according to the floating_veb_list.
857 if (rte_kvargs_process(kvlist, floating_veb_list,
858 floating_veb_list_handler,
859 vf_floating_veb) < 0) {
860 rte_kvargs_free(kvlist);
863 rte_kvargs_free(kvlist);
867 i40e_check_floating_handler(__rte_unused const char *key,
869 __rte_unused void *opaque)
871 if (strcmp(value, "1"))
878 is_floating_veb_supported(struct rte_devargs *devargs)
880 struct rte_kvargs *kvlist;
881 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
886 kvlist = rte_kvargs_parse(devargs->args, NULL);
890 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
891 rte_kvargs_free(kvlist);
894 /* Floating VEB is enabled when there's key-value:
895 * enable_floating_veb=1
897 if (rte_kvargs_process(kvlist, floating_veb_key,
898 i40e_check_floating_handler, NULL) < 0) {
899 rte_kvargs_free(kvlist);
902 rte_kvargs_free(kvlist);
908 config_floating_veb(struct rte_eth_dev *dev)
910 struct rte_pci_device *pci_dev = dev->pci_dev;
911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
914 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
916 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
918 is_floating_veb_supported(pci_dev->device.devargs);
919 config_vf_floating_veb(pci_dev->device.devargs,
921 pf->floating_veb_list);
923 pf->floating_veb = false;
927 #define I40E_L2_TAGS_S_TAG_SHIFT 1
928 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
931 eth_i40e_dev_init(struct rte_eth_dev *dev)
933 struct rte_pci_device *pci_dev;
934 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 struct i40e_vsi *vsi;
941 PMD_INIT_FUNC_TRACE();
943 dev->dev_ops = &i40e_eth_dev_ops;
944 dev->rx_pkt_burst = i40e_recv_pkts;
945 dev->tx_pkt_burst = i40e_xmit_pkts;
947 /* for secondary processes, we don't initialise any further as primary
948 * has already done this work. Only check we don't need a different
950 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
951 i40e_set_rx_function(dev);
952 i40e_set_tx_function(dev);
955 pci_dev = dev->pci_dev;
957 rte_eth_copy_pci_info(dev, pci_dev);
959 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
960 pf->adapter->eth_dev = dev;
961 pf->dev_data = dev->data;
963 hw->back = I40E_PF_TO_ADAPTER(pf);
964 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
966 PMD_INIT_LOG(ERR, "Hardware is not available, "
967 "as address is NULL");
971 hw->vendor_id = pci_dev->id.vendor_id;
972 hw->device_id = pci_dev->id.device_id;
973 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
974 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
975 hw->bus.device = pci_dev->addr.devid;
976 hw->bus.func = pci_dev->addr.function;
977 hw->adapter_stopped = 0;
979 /* Make sure all is clean before doing PF reset */
982 /* Initialize the hardware */
985 /* Reset here to make sure all is clean for each PF */
986 ret = i40e_pf_reset(hw);
988 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
992 /* Initialize the shared code (base driver) */
993 ret = i40e_init_shared_code(hw);
995 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1000 * To work around the NVM issue, initialize registers
1001 * for flexible payload and packet type of QinQ by
1002 * software. It should be removed once issues are fixed
1005 i40e_GLQF_reg_init(hw);
1007 /* Initialize the input set for filters (hash and fd) to default value */
1008 i40e_filter_input_set_init(pf);
1010 /* Initialize the parameters for adminq */
1011 i40e_init_adminq_parameter(hw);
1012 ret = i40e_init_adminq(hw);
1013 if (ret != I40E_SUCCESS) {
1014 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1017 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1018 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1019 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1020 ((hw->nvm.version >> 12) & 0xf),
1021 ((hw->nvm.version >> 4) & 0xff),
1022 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1024 /* Need the special FW version to support floating VEB */
1025 config_floating_veb(dev);
1026 /* Clear PXE mode */
1027 i40e_clear_pxe_mode(hw);
1028 ret = i40e_dev_sync_phy_type(hw);
1030 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1031 goto err_sync_phy_type;
1034 * On X710, performance number is far from the expectation on recent
1035 * firmware versions. The fix for this issue may not be integrated in
1036 * the following firmware version. So the workaround in software driver
1037 * is needed. It needs to modify the initial values of 3 internal only
1038 * registers. Note that the workaround can be removed when it is fixed
1039 * in firmware in the future.
1041 i40e_configure_registers(hw);
1043 /* Get hw capabilities */
1044 ret = i40e_get_cap(hw);
1045 if (ret != I40E_SUCCESS) {
1046 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1047 goto err_get_capabilities;
1050 /* Initialize parameters for PF */
1051 ret = i40e_pf_parameter_init(dev);
1053 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1054 goto err_parameter_init;
1057 /* Initialize the queue management */
1058 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1060 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1061 goto err_qp_pool_init;
1063 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1064 hw->func_caps.num_msix_vectors - 1);
1066 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1067 goto err_msix_pool_init;
1070 /* Initialize lan hmc */
1071 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1072 hw->func_caps.num_rx_qp, 0, 0);
1073 if (ret != I40E_SUCCESS) {
1074 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1075 goto err_init_lan_hmc;
1078 /* Configure lan hmc */
1079 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1080 if (ret != I40E_SUCCESS) {
1081 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1082 goto err_configure_lan_hmc;
1085 /* Get and check the mac address */
1086 i40e_get_mac_addr(hw, hw->mac.addr);
1087 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1088 PMD_INIT_LOG(ERR, "mac address is not valid");
1090 goto err_get_mac_addr;
1092 /* Copy the permanent MAC address */
1093 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1094 (struct ether_addr *) hw->mac.perm_addr);
1096 /* Disable flow control */
1097 hw->fc.requested_mode = I40E_FC_NONE;
1098 i40e_set_fc(hw, &aq_fail, TRUE);
1100 /* Set the global registers with default ether type value */
1101 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1102 if (ret != I40E_SUCCESS) {
1103 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1105 goto err_setup_pf_switch;
1108 /* PF setup, which includes VSI setup */
1109 ret = i40e_pf_setup(pf);
1111 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1112 goto err_setup_pf_switch;
1115 /* reset all stats of the device, including pf and main vsi */
1116 i40e_dev_stats_reset(dev);
1120 /* Disable double vlan by default */
1121 i40e_vsi_config_double_vlan(vsi, FALSE);
1123 /* Disable S-TAG identification when floating_veb is disabled */
1124 if (!pf->floating_veb) {
1125 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1126 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1127 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1128 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1132 if (!vsi->max_macaddrs)
1133 len = ETHER_ADDR_LEN;
1135 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1137 /* Should be after VSI initialized */
1138 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1139 if (!dev->data->mac_addrs) {
1140 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1141 "for storing mac address");
1144 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1145 &dev->data->mac_addrs[0]);
1147 /* initialize pf host driver to setup SRIOV resource if applicable */
1148 i40e_pf_host_init(dev);
1150 /* register callback func to eal lib */
1151 rte_intr_callback_register(&(pci_dev->intr_handle),
1152 i40e_dev_interrupt_handler, (void *)dev);
1154 /* configure and enable device interrupt */
1155 i40e_pf_config_irq0(hw, TRUE);
1156 i40e_pf_enable_irq0(hw);
1158 /* enable uio intr after callback register */
1159 rte_intr_enable(&(pci_dev->intr_handle));
1161 * Add an ethertype filter to drop all flow control frames transmitted
1162 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1165 i40e_add_tx_flow_control_drop_filter(pf);
1167 /* Set the max frame size to 0x2600 by default,
1168 * in case other drivers changed the default value.
1170 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1172 /* initialize mirror rule list */
1173 TAILQ_INIT(&pf->mirror_list);
1175 /* Init dcb to sw mode by default */
1176 ret = i40e_dcb_init_configure(dev, TRUE);
1177 if (ret != I40E_SUCCESS) {
1178 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1179 pf->flags &= ~I40E_FLAG_DCB;
1185 i40e_vsi_release(pf->main_vsi);
1186 err_setup_pf_switch:
1188 err_configure_lan_hmc:
1189 (void)i40e_shutdown_lan_hmc(hw);
1191 i40e_res_pool_destroy(&pf->msix_pool);
1193 i40e_res_pool_destroy(&pf->qp_pool);
1196 err_get_capabilities:
1198 (void)i40e_shutdown_adminq(hw);
1204 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1206 struct rte_pci_device *pci_dev;
1208 struct i40e_filter_control_settings settings;
1210 uint8_t aq_fail = 0;
1212 PMD_INIT_FUNC_TRACE();
1214 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1217 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218 pci_dev = dev->pci_dev;
1220 if (hw->adapter_stopped == 0)
1221 i40e_dev_close(dev);
1223 dev->dev_ops = NULL;
1224 dev->rx_pkt_burst = NULL;
1225 dev->tx_pkt_burst = NULL;
1227 /* Clear PXE mode */
1228 i40e_clear_pxe_mode(hw);
1230 /* Unconfigure filter control */
1231 memset(&settings, 0, sizeof(settings));
1232 ret = i40e_set_filter_control(hw, &settings);
1234 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1237 /* Disable flow control */
1238 hw->fc.requested_mode = I40E_FC_NONE;
1239 i40e_set_fc(hw, &aq_fail, TRUE);
1241 /* uninitialize pf host driver */
1242 i40e_pf_host_uninit(dev);
1244 rte_free(dev->data->mac_addrs);
1245 dev->data->mac_addrs = NULL;
1247 /* disable uio intr before callback unregister */
1248 rte_intr_disable(&(pci_dev->intr_handle));
1250 /* register callback func to eal lib */
1251 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1252 i40e_dev_interrupt_handler, (void *)dev);
1258 i40e_dev_configure(struct rte_eth_dev *dev)
1260 struct i40e_adapter *ad =
1261 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1262 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1263 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1266 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1267 * bulk allocation or vector Rx preconditions we will reset it.
1269 ad->rx_bulk_alloc_allowed = true;
1270 ad->rx_vec_allowed = true;
1271 ad->tx_simple_allowed = true;
1272 ad->tx_vec_allowed = true;
1274 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1275 ret = i40e_fdir_setup(pf);
1276 if (ret != I40E_SUCCESS) {
1277 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1280 ret = i40e_fdir_configure(dev);
1282 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1286 i40e_fdir_teardown(pf);
1288 ret = i40e_dev_init_vlan(dev);
1293 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1294 * RSS setting have different requirements.
1295 * General PMD driver call sequence are NIC init, configure,
1296 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1297 * will try to lookup the VSI that specific queue belongs to if VMDQ
1298 * applicable. So, VMDQ setting has to be done before
1299 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1300 * For RSS setting, it will try to calculate actual configured RX queue
1301 * number, which will be available after rx_queue_setup(). dev_start()
1302 * function is good to place RSS setup.
1304 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1305 ret = i40e_vmdq_setup(dev);
1310 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1311 ret = i40e_dcb_setup(dev);
1313 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1321 /* need to release vmdq resource if exists */
1322 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1323 i40e_vsi_release(pf->vmdq[i].vsi);
1324 pf->vmdq[i].vsi = NULL;
1329 /* need to release fdir resource if exists */
1330 i40e_fdir_teardown(pf);
1335 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1337 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1338 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1339 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1340 uint16_t msix_vect = vsi->msix_intr;
1343 for (i = 0; i < vsi->nb_qps; i++) {
1344 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1345 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1349 if (vsi->type != I40E_VSI_SRIOV) {
1350 if (!rte_intr_allow_others(intr_handle)) {
1351 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1352 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1354 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1357 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1358 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1360 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1365 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1366 vsi->user_param + (msix_vect - 1);
1368 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1369 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1371 I40E_WRITE_FLUSH(hw);
1375 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1376 int base_queue, int nb_queue)
1380 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1382 /* Bind all RX queues to allocated MSIX interrupt */
1383 for (i = 0; i < nb_queue; i++) {
1384 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1385 I40E_QINT_RQCTL_ITR_INDX_MASK |
1386 ((base_queue + i + 1) <<
1387 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1388 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1389 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1391 if (i == nb_queue - 1)
1392 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1393 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1396 /* Write first RX queue to Link list register as the head element */
1397 if (vsi->type != I40E_VSI_SRIOV) {
1399 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1401 if (msix_vect == I40E_MISC_VEC_ID) {
1402 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1404 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1406 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1408 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1411 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1413 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1415 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1417 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1424 if (msix_vect == I40E_MISC_VEC_ID) {
1426 I40E_VPINT_LNKLST0(vsi->user_param),
1428 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1430 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1432 /* num_msix_vectors_vf needs to minus irq0 */
1433 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1434 vsi->user_param + (msix_vect - 1);
1436 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1438 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1440 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1444 I40E_WRITE_FLUSH(hw);
1448 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1450 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1451 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1452 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1453 uint16_t msix_vect = vsi->msix_intr;
1454 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1455 uint16_t queue_idx = 0;
1460 for (i = 0; i < vsi->nb_qps; i++) {
1461 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1462 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1465 /* INTENA flag is not auto-cleared for interrupt */
1466 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1467 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1468 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1469 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1470 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1472 /* VF bind interrupt */
1473 if (vsi->type == I40E_VSI_SRIOV) {
1474 __vsi_queues_bind_intr(vsi, msix_vect,
1475 vsi->base_queue, vsi->nb_qps);
1479 /* PF & VMDq bind interrupt */
1480 if (rte_intr_dp_is_en(intr_handle)) {
1481 if (vsi->type == I40E_VSI_MAIN) {
1484 } else if (vsi->type == I40E_VSI_VMDQ2) {
1485 struct i40e_vsi *main_vsi =
1486 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1487 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1492 for (i = 0; i < vsi->nb_used_qps; i++) {
1494 if (!rte_intr_allow_others(intr_handle))
1495 /* allow to share MISC_VEC_ID */
1496 msix_vect = I40E_MISC_VEC_ID;
1498 /* no enough msix_vect, map all to one */
1499 __vsi_queues_bind_intr(vsi, msix_vect,
1500 vsi->base_queue + i,
1501 vsi->nb_used_qps - i);
1502 for (; !!record && i < vsi->nb_used_qps; i++)
1503 intr_handle->intr_vec[queue_idx + i] =
1507 /* 1:1 queue/msix_vect mapping */
1508 __vsi_queues_bind_intr(vsi, msix_vect,
1509 vsi->base_queue + i, 1);
1511 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1519 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1521 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1523 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1524 uint16_t interval = i40e_calc_itr_interval(\
1525 RTE_LIBRTE_I40E_ITR_INTERVAL);
1526 uint16_t msix_intr, i;
1528 if (rte_intr_allow_others(intr_handle))
1529 for (i = 0; i < vsi->nb_msix; i++) {
1530 msix_intr = vsi->msix_intr + i;
1531 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1532 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1533 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1534 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1536 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1539 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1540 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1541 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1542 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1544 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1546 I40E_WRITE_FLUSH(hw);
1550 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1552 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1553 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1554 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1555 uint16_t msix_intr, i;
1557 if (rte_intr_allow_others(intr_handle))
1558 for (i = 0; i < vsi->nb_msix; i++) {
1559 msix_intr = vsi->msix_intr + i;
1560 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1564 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1566 I40E_WRITE_FLUSH(hw);
1569 static inline uint8_t
1570 i40e_parse_link_speeds(uint16_t link_speeds)
1572 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1574 if (link_speeds & ETH_LINK_SPEED_40G)
1575 link_speed |= I40E_LINK_SPEED_40GB;
1576 if (link_speeds & ETH_LINK_SPEED_25G)
1577 link_speed |= I40E_LINK_SPEED_25GB;
1578 if (link_speeds & ETH_LINK_SPEED_20G)
1579 link_speed |= I40E_LINK_SPEED_20GB;
1580 if (link_speeds & ETH_LINK_SPEED_10G)
1581 link_speed |= I40E_LINK_SPEED_10GB;
1582 if (link_speeds & ETH_LINK_SPEED_1G)
1583 link_speed |= I40E_LINK_SPEED_1GB;
1584 if (link_speeds & ETH_LINK_SPEED_100M)
1585 link_speed |= I40E_LINK_SPEED_100MB;
1591 i40e_phy_conf_link(struct i40e_hw *hw,
1593 uint8_t force_speed)
1595 enum i40e_status_code status;
1596 struct i40e_aq_get_phy_abilities_resp phy_ab;
1597 struct i40e_aq_set_phy_config phy_conf;
1598 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1599 I40E_AQ_PHY_FLAG_PAUSE_RX |
1600 I40E_AQ_PHY_FLAG_PAUSE_RX |
1601 I40E_AQ_PHY_FLAG_LOW_POWER;
1602 const uint8_t advt = I40E_LINK_SPEED_40GB |
1603 I40E_LINK_SPEED_25GB |
1604 I40E_LINK_SPEED_10GB |
1605 I40E_LINK_SPEED_1GB |
1606 I40E_LINK_SPEED_100MB;
1610 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1615 memset(&phy_conf, 0, sizeof(phy_conf));
1617 /* bits 0-2 use the values from get_phy_abilities_resp */
1619 abilities |= phy_ab.abilities & mask;
1621 /* update ablities and speed */
1622 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1623 phy_conf.link_speed = advt;
1625 phy_conf.link_speed = force_speed;
1627 phy_conf.abilities = abilities;
1629 /* use get_phy_abilities_resp value for the rest */
1630 phy_conf.phy_type = phy_ab.phy_type;
1631 phy_conf.eee_capability = phy_ab.eee_capability;
1632 phy_conf.eeer = phy_ab.eeer_val;
1633 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1635 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1636 phy_ab.abilities, phy_ab.link_speed);
1637 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1638 phy_conf.abilities, phy_conf.link_speed);
1640 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1644 return I40E_SUCCESS;
1648 i40e_apply_link_speed(struct rte_eth_dev *dev)
1651 uint8_t abilities = 0;
1652 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653 struct rte_eth_conf *conf = &dev->data->dev_conf;
1655 speed = i40e_parse_link_speeds(conf->link_speeds);
1656 if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1657 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1658 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1659 abilities |= I40E_AQ_PHY_AN_ENABLED;
1660 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1662 /* Skip changing speed on 40G interfaces, FW does not support */
1663 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1664 speed = I40E_LINK_SPEED_UNKNOWN;
1665 abilities |= I40E_AQ_PHY_AN_ENABLED;
1668 return i40e_phy_conf_link(hw, abilities, speed);
1672 i40e_dev_start(struct rte_eth_dev *dev)
1674 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676 struct i40e_vsi *main_vsi = pf->main_vsi;
1678 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1679 uint32_t intr_vector = 0;
1681 hw->adapter_stopped = 0;
1683 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1684 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1685 dev->data->port_id);
1689 rte_intr_disable(intr_handle);
1691 if ((rte_intr_cap_multiple(intr_handle) ||
1692 !RTE_ETH_DEV_SRIOV(dev).active) &&
1693 dev->data->dev_conf.intr_conf.rxq != 0) {
1694 intr_vector = dev->data->nb_rx_queues;
1695 if (rte_intr_efd_enable(intr_handle, intr_vector))
1699 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1700 intr_handle->intr_vec =
1701 rte_zmalloc("intr_vec",
1702 dev->data->nb_rx_queues * sizeof(int),
1704 if (!intr_handle->intr_vec) {
1705 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1706 " intr_vec\n", dev->data->nb_rx_queues);
1711 /* Initialize VSI */
1712 ret = i40e_dev_rxtx_init(pf);
1713 if (ret != I40E_SUCCESS) {
1714 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1718 /* Map queues with MSIX interrupt */
1719 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1720 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1721 i40e_vsi_queues_bind_intr(main_vsi);
1722 i40e_vsi_enable_queues_intr(main_vsi);
1724 /* Map VMDQ VSI queues with MSIX interrupt */
1725 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1726 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1727 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1728 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1731 /* enable FDIR MSIX interrupt */
1732 if (pf->fdir.fdir_vsi) {
1733 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1734 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1737 /* Enable all queues which have been configured */
1738 ret = i40e_dev_switch_queues(pf, TRUE);
1739 if (ret != I40E_SUCCESS) {
1740 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1744 /* Enable receiving broadcast packets */
1745 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1746 if (ret != I40E_SUCCESS)
1747 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1749 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1750 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1752 if (ret != I40E_SUCCESS)
1753 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1756 /* Apply link configure */
1757 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1758 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1759 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1760 ETH_LINK_SPEED_40G)) {
1761 PMD_DRV_LOG(ERR, "Invalid link setting");
1764 ret = i40e_apply_link_speed(dev);
1765 if (I40E_SUCCESS != ret) {
1766 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1770 if (!rte_intr_allow_others(intr_handle)) {
1771 rte_intr_callback_unregister(intr_handle,
1772 i40e_dev_interrupt_handler,
1774 /* configure and enable device interrupt */
1775 i40e_pf_config_irq0(hw, FALSE);
1776 i40e_pf_enable_irq0(hw);
1778 if (dev->data->dev_conf.intr_conf.lsc != 0)
1779 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1780 " no intr multiplex\n");
1781 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1782 ret = i40e_aq_set_phy_int_mask(hw,
1783 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1784 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1785 I40E_AQ_EVENT_MEDIA_NA), NULL);
1786 if (ret != I40E_SUCCESS)
1787 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1789 /* Call get_link_info aq commond to enable LSE */
1790 i40e_dev_link_update(dev, 0);
1793 /* enable uio intr after callback register */
1794 rte_intr_enable(intr_handle);
1796 return I40E_SUCCESS;
1799 i40e_dev_switch_queues(pf, FALSE);
1800 i40e_dev_clear_queues(dev);
1806 i40e_dev_stop(struct rte_eth_dev *dev)
1808 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1809 struct i40e_vsi *main_vsi = pf->main_vsi;
1810 struct i40e_mirror_rule *p_mirror;
1811 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1814 /* Disable all queues */
1815 i40e_dev_switch_queues(pf, FALSE);
1817 /* un-map queues with interrupt registers */
1818 i40e_vsi_disable_queues_intr(main_vsi);
1819 i40e_vsi_queues_unbind_intr(main_vsi);
1821 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1822 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1823 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1826 if (pf->fdir.fdir_vsi) {
1827 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1828 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1830 /* Clear all queues and release memory */
1831 i40e_dev_clear_queues(dev);
1834 i40e_dev_set_link_down(dev);
1836 /* Remove all mirror rules */
1837 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1838 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1841 pf->nb_mirror_rule = 0;
1843 if (!rte_intr_allow_others(intr_handle))
1844 /* resume to the default handler */
1845 rte_intr_callback_register(intr_handle,
1846 i40e_dev_interrupt_handler,
1849 /* Clean datapath event and queue/vec mapping */
1850 rte_intr_efd_disable(intr_handle);
1851 if (intr_handle->intr_vec) {
1852 rte_free(intr_handle->intr_vec);
1853 intr_handle->intr_vec = NULL;
1858 i40e_dev_close(struct rte_eth_dev *dev)
1860 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1861 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865 PMD_INIT_FUNC_TRACE();
1868 hw->adapter_stopped = 1;
1869 i40e_dev_free_queues(dev);
1871 /* Disable interrupt */
1872 i40e_pf_disable_irq0(hw);
1873 rte_intr_disable(&(dev->pci_dev->intr_handle));
1875 /* shutdown and destroy the HMC */
1876 i40e_shutdown_lan_hmc(hw);
1878 /* release all the existing VSIs and VEBs */
1879 i40e_fdir_teardown(pf);
1880 i40e_vsi_release(pf->main_vsi);
1882 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1883 i40e_vsi_release(pf->vmdq[i].vsi);
1884 pf->vmdq[i].vsi = NULL;
1890 /* shutdown the adminq */
1891 i40e_aq_queue_shutdown(hw, true);
1892 i40e_shutdown_adminq(hw);
1894 i40e_res_pool_destroy(&pf->qp_pool);
1895 i40e_res_pool_destroy(&pf->msix_pool);
1897 /* force a PF reset to clean anything leftover */
1898 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1899 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1900 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1901 I40E_WRITE_FLUSH(hw);
1905 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1907 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909 struct i40e_vsi *vsi = pf->main_vsi;
1912 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1914 if (status != I40E_SUCCESS)
1915 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1917 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1919 if (status != I40E_SUCCESS)
1920 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1925 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1927 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929 struct i40e_vsi *vsi = pf->main_vsi;
1932 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1934 if (status != I40E_SUCCESS)
1935 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1937 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1939 if (status != I40E_SUCCESS)
1940 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1944 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1946 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1947 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948 struct i40e_vsi *vsi = pf->main_vsi;
1951 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1952 if (ret != I40E_SUCCESS)
1953 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1957 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961 struct i40e_vsi *vsi = pf->main_vsi;
1964 if (dev->data->promiscuous == 1)
1965 return; /* must remain in all_multicast mode */
1967 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1968 vsi->seid, FALSE, NULL);
1969 if (ret != I40E_SUCCESS)
1970 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1974 * Set device link up.
1977 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1979 /* re-apply link speed setting */
1980 return i40e_apply_link_speed(dev);
1984 * Set device link down.
1987 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1989 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1990 uint8_t abilities = 0;
1991 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993 if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1994 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1995 return i40e_phy_conf_link(hw, abilities, speed);
1999 i40e_dev_link_update(struct rte_eth_dev *dev,
2000 int wait_to_complete)
2002 #define CHECK_INTERVAL 100 /* 100ms */
2003 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2004 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005 struct i40e_link_status link_status;
2006 struct rte_eth_link link, old;
2008 unsigned rep_cnt = MAX_REPEAT_TIME;
2009 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2011 memset(&link, 0, sizeof(link));
2012 memset(&old, 0, sizeof(old));
2013 memset(&link_status, 0, sizeof(link_status));
2014 rte_i40e_dev_atomic_read_link_status(dev, &old);
2017 /* Get link status information from hardware */
2018 status = i40e_aq_get_link_info(hw, enable_lse,
2019 &link_status, NULL);
2020 if (status != I40E_SUCCESS) {
2021 link.link_speed = ETH_SPEED_NUM_100M;
2022 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2023 PMD_DRV_LOG(ERR, "Failed to get link info");
2027 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2028 if (!wait_to_complete)
2031 rte_delay_ms(CHECK_INTERVAL);
2032 } while (!link.link_status && rep_cnt--);
2034 if (!link.link_status)
2037 /* i40e uses full duplex only */
2038 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2040 /* Parse the link status */
2041 switch (link_status.link_speed) {
2042 case I40E_LINK_SPEED_100MB:
2043 link.link_speed = ETH_SPEED_NUM_100M;
2045 case I40E_LINK_SPEED_1GB:
2046 link.link_speed = ETH_SPEED_NUM_1G;
2048 case I40E_LINK_SPEED_10GB:
2049 link.link_speed = ETH_SPEED_NUM_10G;
2051 case I40E_LINK_SPEED_20GB:
2052 link.link_speed = ETH_SPEED_NUM_20G;
2054 case I40E_LINK_SPEED_25GB:
2055 link.link_speed = ETH_SPEED_NUM_25G;
2057 case I40E_LINK_SPEED_40GB:
2058 link.link_speed = ETH_SPEED_NUM_40G;
2061 link.link_speed = ETH_SPEED_NUM_100M;
2065 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2066 ETH_LINK_SPEED_FIXED);
2069 rte_i40e_dev_atomic_write_link_status(dev, &link);
2070 if (link.link_status == old.link_status)
2076 /* Get all the statistics of a VSI */
2078 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2080 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2081 struct i40e_eth_stats *nes = &vsi->eth_stats;
2082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2085 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2086 vsi->offset_loaded, &oes->rx_bytes,
2088 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2089 vsi->offset_loaded, &oes->rx_unicast,
2091 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2092 vsi->offset_loaded, &oes->rx_multicast,
2093 &nes->rx_multicast);
2094 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2095 vsi->offset_loaded, &oes->rx_broadcast,
2096 &nes->rx_broadcast);
2097 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2098 &oes->rx_discards, &nes->rx_discards);
2099 /* GLV_REPC not supported */
2100 /* GLV_RMPC not supported */
2101 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2102 &oes->rx_unknown_protocol,
2103 &nes->rx_unknown_protocol);
2104 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2105 vsi->offset_loaded, &oes->tx_bytes,
2107 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2108 vsi->offset_loaded, &oes->tx_unicast,
2110 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2111 vsi->offset_loaded, &oes->tx_multicast,
2112 &nes->tx_multicast);
2113 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2114 vsi->offset_loaded, &oes->tx_broadcast,
2115 &nes->tx_broadcast);
2116 /* GLV_TDPC not supported */
2117 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2118 &oes->tx_errors, &nes->tx_errors);
2119 vsi->offset_loaded = true;
2121 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2123 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2124 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2125 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2126 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2127 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2128 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2129 nes->rx_unknown_protocol);
2130 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2131 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2132 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2133 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2134 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2135 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2136 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2141 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2144 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2145 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2147 /* Get statistics of struct i40e_eth_stats */
2148 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2149 I40E_GLPRT_GORCL(hw->port),
2150 pf->offset_loaded, &os->eth.rx_bytes,
2152 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2153 I40E_GLPRT_UPRCL(hw->port),
2154 pf->offset_loaded, &os->eth.rx_unicast,
2155 &ns->eth.rx_unicast);
2156 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2157 I40E_GLPRT_MPRCL(hw->port),
2158 pf->offset_loaded, &os->eth.rx_multicast,
2159 &ns->eth.rx_multicast);
2160 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2161 I40E_GLPRT_BPRCL(hw->port),
2162 pf->offset_loaded, &os->eth.rx_broadcast,
2163 &ns->eth.rx_broadcast);
2164 /* Workaround: CRC size should not be included in byte statistics,
2165 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2167 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2168 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2170 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2171 pf->offset_loaded, &os->eth.rx_discards,
2172 &ns->eth.rx_discards);
2173 /* GLPRT_REPC not supported */
2174 /* GLPRT_RMPC not supported */
2175 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2177 &os->eth.rx_unknown_protocol,
2178 &ns->eth.rx_unknown_protocol);
2179 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2180 I40E_GLPRT_GOTCL(hw->port),
2181 pf->offset_loaded, &os->eth.tx_bytes,
2183 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2184 I40E_GLPRT_UPTCL(hw->port),
2185 pf->offset_loaded, &os->eth.tx_unicast,
2186 &ns->eth.tx_unicast);
2187 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2188 I40E_GLPRT_MPTCL(hw->port),
2189 pf->offset_loaded, &os->eth.tx_multicast,
2190 &ns->eth.tx_multicast);
2191 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2192 I40E_GLPRT_BPTCL(hw->port),
2193 pf->offset_loaded, &os->eth.tx_broadcast,
2194 &ns->eth.tx_broadcast);
2195 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2196 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2197 /* GLPRT_TEPC not supported */
2199 /* additional port specific stats */
2200 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2201 pf->offset_loaded, &os->tx_dropped_link_down,
2202 &ns->tx_dropped_link_down);
2203 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2204 pf->offset_loaded, &os->crc_errors,
2206 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2207 pf->offset_loaded, &os->illegal_bytes,
2208 &ns->illegal_bytes);
2209 /* GLPRT_ERRBC not supported */
2210 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2211 pf->offset_loaded, &os->mac_local_faults,
2212 &ns->mac_local_faults);
2213 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2214 pf->offset_loaded, &os->mac_remote_faults,
2215 &ns->mac_remote_faults);
2216 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2217 pf->offset_loaded, &os->rx_length_errors,
2218 &ns->rx_length_errors);
2219 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2220 pf->offset_loaded, &os->link_xon_rx,
2222 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2223 pf->offset_loaded, &os->link_xoff_rx,
2225 for (i = 0; i < 8; i++) {
2226 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2228 &os->priority_xon_rx[i],
2229 &ns->priority_xon_rx[i]);
2230 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2232 &os->priority_xoff_rx[i],
2233 &ns->priority_xoff_rx[i]);
2235 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2236 pf->offset_loaded, &os->link_xon_tx,
2238 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2239 pf->offset_loaded, &os->link_xoff_tx,
2241 for (i = 0; i < 8; i++) {
2242 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2244 &os->priority_xon_tx[i],
2245 &ns->priority_xon_tx[i]);
2246 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2248 &os->priority_xoff_tx[i],
2249 &ns->priority_xoff_tx[i]);
2250 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2252 &os->priority_xon_2_xoff[i],
2253 &ns->priority_xon_2_xoff[i]);
2255 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2256 I40E_GLPRT_PRC64L(hw->port),
2257 pf->offset_loaded, &os->rx_size_64,
2259 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2260 I40E_GLPRT_PRC127L(hw->port),
2261 pf->offset_loaded, &os->rx_size_127,
2263 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2264 I40E_GLPRT_PRC255L(hw->port),
2265 pf->offset_loaded, &os->rx_size_255,
2267 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2268 I40E_GLPRT_PRC511L(hw->port),
2269 pf->offset_loaded, &os->rx_size_511,
2271 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2272 I40E_GLPRT_PRC1023L(hw->port),
2273 pf->offset_loaded, &os->rx_size_1023,
2275 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2276 I40E_GLPRT_PRC1522L(hw->port),
2277 pf->offset_loaded, &os->rx_size_1522,
2279 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2280 I40E_GLPRT_PRC9522L(hw->port),
2281 pf->offset_loaded, &os->rx_size_big,
2283 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2284 pf->offset_loaded, &os->rx_undersize,
2286 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2287 pf->offset_loaded, &os->rx_fragments,
2289 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2290 pf->offset_loaded, &os->rx_oversize,
2292 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2293 pf->offset_loaded, &os->rx_jabber,
2295 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2296 I40E_GLPRT_PTC64L(hw->port),
2297 pf->offset_loaded, &os->tx_size_64,
2299 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2300 I40E_GLPRT_PTC127L(hw->port),
2301 pf->offset_loaded, &os->tx_size_127,
2303 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2304 I40E_GLPRT_PTC255L(hw->port),
2305 pf->offset_loaded, &os->tx_size_255,
2307 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2308 I40E_GLPRT_PTC511L(hw->port),
2309 pf->offset_loaded, &os->tx_size_511,
2311 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2312 I40E_GLPRT_PTC1023L(hw->port),
2313 pf->offset_loaded, &os->tx_size_1023,
2315 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2316 I40E_GLPRT_PTC1522L(hw->port),
2317 pf->offset_loaded, &os->tx_size_1522,
2319 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2320 I40E_GLPRT_PTC9522L(hw->port),
2321 pf->offset_loaded, &os->tx_size_big,
2323 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2325 &os->fd_sb_match, &ns->fd_sb_match);
2326 /* GLPRT_MSPDC not supported */
2327 /* GLPRT_XEC not supported */
2329 pf->offset_loaded = true;
2332 i40e_update_vsi_stats(pf->main_vsi);
2335 /* Get all statistics of a port */
2337 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2339 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2340 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2344 /* call read registers - updates values, now write them to struct */
2345 i40e_read_stats_registers(pf, hw);
2347 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2348 pf->main_vsi->eth_stats.rx_multicast +
2349 pf->main_vsi->eth_stats.rx_broadcast -
2350 pf->main_vsi->eth_stats.rx_discards;
2351 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2352 pf->main_vsi->eth_stats.tx_multicast +
2353 pf->main_vsi->eth_stats.tx_broadcast;
2354 stats->ibytes = ns->eth.rx_bytes;
2355 stats->obytes = ns->eth.tx_bytes;
2356 stats->oerrors = ns->eth.tx_errors +
2357 pf->main_vsi->eth_stats.tx_errors;
2360 stats->imissed = ns->eth.rx_discards +
2361 pf->main_vsi->eth_stats.rx_discards;
2362 stats->ierrors = ns->crc_errors +
2363 ns->rx_length_errors + ns->rx_undersize +
2364 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2366 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2367 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2368 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2369 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2370 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2371 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2372 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2373 ns->eth.rx_unknown_protocol);
2374 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2375 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2376 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2377 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2378 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2379 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2381 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2382 ns->tx_dropped_link_down);
2383 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2384 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2386 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2387 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2388 ns->mac_local_faults);
2389 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2390 ns->mac_remote_faults);
2391 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2392 ns->rx_length_errors);
2393 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2394 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2395 for (i = 0; i < 8; i++) {
2396 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2397 i, ns->priority_xon_rx[i]);
2398 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2399 i, ns->priority_xoff_rx[i]);
2401 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2402 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2403 for (i = 0; i < 8; i++) {
2404 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2405 i, ns->priority_xon_tx[i]);
2406 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2407 i, ns->priority_xoff_tx[i]);
2408 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2409 i, ns->priority_xon_2_xoff[i]);
2411 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2412 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2413 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2414 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2415 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2416 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2417 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2418 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2419 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2420 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2421 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2422 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2423 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2424 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2425 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2426 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2427 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2428 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2429 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2430 ns->mac_short_packet_dropped);
2431 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2432 ns->checksum_error);
2433 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2434 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2437 /* Reset the statistics */
2439 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2441 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444 /* Mark PF and VSI stats to update the offset, aka "reset" */
2445 pf->offset_loaded = false;
2447 pf->main_vsi->offset_loaded = false;
2449 /* read the stats, reading current register values into offset */
2450 i40e_read_stats_registers(pf, hw);
2454 i40e_xstats_calc_num(void)
2456 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2457 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2458 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2461 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2462 struct rte_eth_xstat_name *xstats_names,
2463 __rte_unused unsigned limit)
2468 if (xstats_names == NULL)
2469 return i40e_xstats_calc_num();
2471 /* Note: limit checked in rte_eth_xstats_names() */
2473 /* Get stats from i40e_eth_stats struct */
2474 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2475 snprintf(xstats_names[count].name,
2476 sizeof(xstats_names[count].name),
2477 "%s", rte_i40e_stats_strings[i].name);
2481 /* Get individiual stats from i40e_hw_port struct */
2482 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2483 snprintf(xstats_names[count].name,
2484 sizeof(xstats_names[count].name),
2485 "%s", rte_i40e_hw_port_strings[i].name);
2489 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2490 for (prio = 0; prio < 8; prio++) {
2491 snprintf(xstats_names[count].name,
2492 sizeof(xstats_names[count].name),
2493 "rx_priority%u_%s", prio,
2494 rte_i40e_rxq_prio_strings[i].name);
2499 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2500 for (prio = 0; prio < 8; prio++) {
2501 snprintf(xstats_names[count].name,
2502 sizeof(xstats_names[count].name),
2503 "tx_priority%u_%s", prio,
2504 rte_i40e_txq_prio_strings[i].name);
2512 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2515 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2516 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2517 unsigned i, count, prio;
2518 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2520 count = i40e_xstats_calc_num();
2524 i40e_read_stats_registers(pf, hw);
2531 /* Get stats from i40e_eth_stats struct */
2532 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2533 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2534 rte_i40e_stats_strings[i].offset);
2538 /* Get individiual stats from i40e_hw_port struct */
2539 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2540 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2541 rte_i40e_hw_port_strings[i].offset);
2545 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2546 for (prio = 0; prio < 8; prio++) {
2547 xstats[count].value =
2548 *(uint64_t *)(((char *)hw_stats) +
2549 rte_i40e_rxq_prio_strings[i].offset +
2550 (sizeof(uint64_t) * prio));
2555 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2556 for (prio = 0; prio < 8; prio++) {
2557 xstats[count].value =
2558 *(uint64_t *)(((char *)hw_stats) +
2559 rte_i40e_txq_prio_strings[i].offset +
2560 (sizeof(uint64_t) * prio));
2569 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2570 __rte_unused uint16_t queue_id,
2571 __rte_unused uint8_t stat_idx,
2572 __rte_unused uint8_t is_rx)
2574 PMD_INIT_FUNC_TRACE();
2580 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2582 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2583 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584 struct i40e_vsi *vsi = pf->main_vsi;
2586 dev_info->max_rx_queues = vsi->nb_qps;
2587 dev_info->max_tx_queues = vsi->nb_qps;
2588 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2589 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2590 dev_info->max_mac_addrs = vsi->max_macaddrs;
2591 dev_info->max_vfs = dev->pci_dev->max_vfs;
2592 dev_info->rx_offload_capa =
2593 DEV_RX_OFFLOAD_VLAN_STRIP |
2594 DEV_RX_OFFLOAD_QINQ_STRIP |
2595 DEV_RX_OFFLOAD_IPV4_CKSUM |
2596 DEV_RX_OFFLOAD_UDP_CKSUM |
2597 DEV_RX_OFFLOAD_TCP_CKSUM;
2598 dev_info->tx_offload_capa =
2599 DEV_TX_OFFLOAD_VLAN_INSERT |
2600 DEV_TX_OFFLOAD_QINQ_INSERT |
2601 DEV_TX_OFFLOAD_IPV4_CKSUM |
2602 DEV_TX_OFFLOAD_UDP_CKSUM |
2603 DEV_TX_OFFLOAD_TCP_CKSUM |
2604 DEV_TX_OFFLOAD_SCTP_CKSUM |
2605 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2606 DEV_TX_OFFLOAD_TCP_TSO |
2607 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2608 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2609 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2610 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2611 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2613 dev_info->reta_size = pf->hash_lut_size;
2614 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2616 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2618 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2619 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2620 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2622 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2626 dev_info->default_txconf = (struct rte_eth_txconf) {
2628 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2629 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2630 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2632 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2633 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2634 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2635 ETH_TXQ_FLAGS_NOOFFLOADS,
2638 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2639 .nb_max = I40E_MAX_RING_DESC,
2640 .nb_min = I40E_MIN_RING_DESC,
2641 .nb_align = I40E_ALIGN_RING_DESC,
2644 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2645 .nb_max = I40E_MAX_RING_DESC,
2646 .nb_min = I40E_MIN_RING_DESC,
2647 .nb_align = I40E_ALIGN_RING_DESC,
2650 if (pf->flags & I40E_FLAG_VMDQ) {
2651 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2652 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2653 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2654 pf->max_nb_vmdq_vsi;
2655 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2656 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2657 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2660 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2662 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2663 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2665 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2668 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2672 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2674 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2675 struct i40e_vsi *vsi = pf->main_vsi;
2676 PMD_INIT_FUNC_TRACE();
2679 return i40e_vsi_add_vlan(vsi, vlan_id);
2681 return i40e_vsi_delete_vlan(vsi, vlan_id);
2685 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2686 enum rte_vlan_type vlan_type,
2689 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690 uint64_t reg_r = 0, reg_w = 0;
2691 uint16_t reg_id = 0;
2693 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2695 switch (vlan_type) {
2696 case ETH_VLAN_TYPE_OUTER:
2702 case ETH_VLAN_TYPE_INNER:
2708 "Unsupported vlan type in single vlan.\n");
2714 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2717 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2719 if (ret != I40E_SUCCESS) {
2720 PMD_DRV_LOG(ERR, "Fail to debug read from "
2721 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2725 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2726 "0x%08"PRIx64"", reg_id, reg_r);
2728 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2729 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2730 if (reg_r == reg_w) {
2732 PMD_DRV_LOG(DEBUG, "No need to write");
2736 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2738 if (ret != I40E_SUCCESS) {
2740 PMD_DRV_LOG(ERR, "Fail to debug write to "
2741 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2744 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2745 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2751 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2753 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2754 struct i40e_vsi *vsi = pf->main_vsi;
2756 if (mask & ETH_VLAN_FILTER_MASK) {
2757 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2758 i40e_vsi_config_vlan_filter(vsi, TRUE);
2760 i40e_vsi_config_vlan_filter(vsi, FALSE);
2763 if (mask & ETH_VLAN_STRIP_MASK) {
2764 /* Enable or disable VLAN stripping */
2765 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2766 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2768 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2771 if (mask & ETH_VLAN_EXTEND_MASK) {
2772 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2773 i40e_vsi_config_double_vlan(vsi, TRUE);
2774 /* Set global registers with default ether type value */
2775 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2777 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2781 i40e_vsi_config_double_vlan(vsi, FALSE);
2786 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2787 __rte_unused uint16_t queue,
2788 __rte_unused int on)
2790 PMD_INIT_FUNC_TRACE();
2794 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2797 struct i40e_vsi *vsi = pf->main_vsi;
2798 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2799 struct i40e_vsi_vlan_pvid_info info;
2801 memset(&info, 0, sizeof(info));
2804 info.config.pvid = pvid;
2806 info.config.reject.tagged =
2807 data->dev_conf.txmode.hw_vlan_reject_tagged;
2808 info.config.reject.untagged =
2809 data->dev_conf.txmode.hw_vlan_reject_untagged;
2812 return i40e_vsi_vlan_pvid_set(vsi, &info);
2816 i40e_dev_led_on(struct rte_eth_dev *dev)
2818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819 uint32_t mode = i40e_led_get(hw);
2822 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2828 i40e_dev_led_off(struct rte_eth_dev *dev)
2830 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831 uint32_t mode = i40e_led_get(hw);
2834 i40e_led_set(hw, 0, false);
2840 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2845 fc_conf->pause_time = pf->fc_conf.pause_time;
2846 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2847 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2849 /* Return current mode according to actual setting*/
2850 switch (hw->fc.current_mode) {
2852 fc_conf->mode = RTE_FC_FULL;
2854 case I40E_FC_TX_PAUSE:
2855 fc_conf->mode = RTE_FC_TX_PAUSE;
2857 case I40E_FC_RX_PAUSE:
2858 fc_conf->mode = RTE_FC_RX_PAUSE;
2862 fc_conf->mode = RTE_FC_NONE;
2869 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2871 uint32_t mflcn_reg, fctrl_reg, reg;
2872 uint32_t max_high_water;
2873 uint8_t i, aq_failure;
2877 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2878 [RTE_FC_NONE] = I40E_FC_NONE,
2879 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2880 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2881 [RTE_FC_FULL] = I40E_FC_FULL
2884 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2886 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2887 if ((fc_conf->high_water > max_high_water) ||
2888 (fc_conf->high_water < fc_conf->low_water)) {
2889 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2890 "High_water must <= %d.", max_high_water);
2894 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2896 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2898 pf->fc_conf.pause_time = fc_conf->pause_time;
2899 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2900 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2902 PMD_INIT_FUNC_TRACE();
2904 /* All the link flow control related enable/disable register
2905 * configuration is handle by the F/W
2907 err = i40e_set_fc(hw, &aq_failure, true);
2911 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2912 /* Configure flow control refresh threshold,
2913 * the value for stat_tx_pause_refresh_timer[8]
2914 * is used for global pause operation.
2918 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2919 pf->fc_conf.pause_time);
2921 /* configure the timer value included in transmitted pause
2923 * the value for stat_tx_pause_quanta[8] is used for global
2926 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2927 pf->fc_conf.pause_time);
2929 fctrl_reg = I40E_READ_REG(hw,
2930 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2932 if (fc_conf->mac_ctrl_frame_fwd != 0)
2933 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2935 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2937 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2940 /* Configure pause time (2 TCs per register) */
2941 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2942 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2943 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2945 /* Configure flow control refresh threshold value */
2946 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2947 pf->fc_conf.pause_time / 2);
2949 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2951 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2952 *depending on configuration
2954 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2955 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2956 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2958 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2959 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2962 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2965 /* config the water marker both based on the packets and bytes */
2966 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2967 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2968 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2969 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2970 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2971 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2972 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2973 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2975 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2976 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2979 I40E_WRITE_FLUSH(hw);
2985 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2986 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2988 PMD_INIT_FUNC_TRACE();
2993 /* Add a MAC address, and update filters */
2995 i40e_macaddr_add(struct rte_eth_dev *dev,
2996 struct ether_addr *mac_addr,
2997 __rte_unused uint32_t index,
3000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3001 struct i40e_mac_filter_info mac_filter;
3002 struct i40e_vsi *vsi;
3005 /* If VMDQ not enabled or configured, return */
3006 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3007 !pf->nb_cfg_vmdq_vsi)) {
3008 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3009 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3014 if (pool > pf->nb_cfg_vmdq_vsi) {
3015 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3016 pool, pf->nb_cfg_vmdq_vsi);
3020 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3021 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3022 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3024 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3029 vsi = pf->vmdq[pool - 1].vsi;
3031 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3032 if (ret != I40E_SUCCESS) {
3033 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3038 /* Remove a MAC address, and update filters */
3040 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3042 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3043 struct i40e_vsi *vsi;
3044 struct rte_eth_dev_data *data = dev->data;
3045 struct ether_addr *macaddr;
3050 macaddr = &(data->mac_addrs[index]);
3052 pool_sel = dev->data->mac_pool_sel[index];
3054 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3055 if (pool_sel & (1ULL << i)) {
3059 /* No VMDQ pool enabled or configured */
3060 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3061 (i > pf->nb_cfg_vmdq_vsi)) {
3062 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3066 vsi = pf->vmdq[i - 1].vsi;
3068 ret = i40e_vsi_delete_mac(vsi, macaddr);
3071 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3078 /* Set perfect match or hash match of MAC and VLAN for a VF */
3080 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3081 struct rte_eth_mac_filter *filter,
3085 struct i40e_mac_filter_info mac_filter;
3086 struct ether_addr old_mac;
3087 struct ether_addr *new_mac;
3088 struct i40e_pf_vf *vf = NULL;
3093 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3096 hw = I40E_PF_TO_HW(pf);
3098 if (filter == NULL) {
3099 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3103 new_mac = &filter->mac_addr;
3105 if (is_zero_ether_addr(new_mac)) {
3106 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3110 vf_id = filter->dst_id;
3112 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3113 PMD_DRV_LOG(ERR, "Invalid argument.");
3116 vf = &pf->vfs[vf_id];
3118 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3119 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3124 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3125 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3127 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3130 mac_filter.filter_type = filter->filter_type;
3131 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3132 if (ret != I40E_SUCCESS) {
3133 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3136 ether_addr_copy(new_mac, &pf->dev_addr);
3138 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3140 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3141 if (ret != I40E_SUCCESS) {
3142 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3146 /* Clear device address as it has been removed */
3147 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3148 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3154 /* MAC filter handle */
3156 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3159 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3160 struct rte_eth_mac_filter *filter;
3161 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3162 int ret = I40E_NOT_SUPPORTED;
3164 filter = (struct rte_eth_mac_filter *)(arg);
3166 switch (filter_op) {
3167 case RTE_ETH_FILTER_NOP:
3170 case RTE_ETH_FILTER_ADD:
3171 i40e_pf_disable_irq0(hw);
3173 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3174 i40e_pf_enable_irq0(hw);
3176 case RTE_ETH_FILTER_DELETE:
3177 i40e_pf_disable_irq0(hw);
3179 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3180 i40e_pf_enable_irq0(hw);
3183 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3184 ret = I40E_ERR_PARAM;
3192 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3194 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3195 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3201 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3202 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3205 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3209 uint32_t *lut_dw = (uint32_t *)lut;
3210 uint16_t i, lut_size_dw = lut_size / 4;
3212 for (i = 0; i < lut_size_dw; i++)
3213 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3220 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3229 pf = I40E_VSI_TO_PF(vsi);
3230 hw = I40E_VSI_TO_HW(vsi);
3232 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3233 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3236 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3240 uint32_t *lut_dw = (uint32_t *)lut;
3241 uint16_t i, lut_size_dw = lut_size / 4;
3243 for (i = 0; i < lut_size_dw; i++)
3244 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3245 I40E_WRITE_FLUSH(hw);
3252 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3253 struct rte_eth_rss_reta_entry64 *reta_conf,
3256 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3257 uint16_t i, lut_size = pf->hash_lut_size;
3258 uint16_t idx, shift;
3262 if (reta_size != lut_size ||
3263 reta_size > ETH_RSS_RETA_SIZE_512) {
3264 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3265 "(%d) doesn't match the number hardware can supported "
3266 "(%d)\n", reta_size, lut_size);
3270 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3272 PMD_DRV_LOG(ERR, "No memory can be allocated");
3275 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3278 for (i = 0; i < reta_size; i++) {
3279 idx = i / RTE_RETA_GROUP_SIZE;
3280 shift = i % RTE_RETA_GROUP_SIZE;
3281 if (reta_conf[idx].mask & (1ULL << shift))
3282 lut[i] = reta_conf[idx].reta[shift];
3284 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3293 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3294 struct rte_eth_rss_reta_entry64 *reta_conf,
3297 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3298 uint16_t i, lut_size = pf->hash_lut_size;
3299 uint16_t idx, shift;
3303 if (reta_size != lut_size ||
3304 reta_size > ETH_RSS_RETA_SIZE_512) {
3305 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3306 "(%d) doesn't match the number hardware can supported "
3307 "(%d)\n", reta_size, lut_size);
3311 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3313 PMD_DRV_LOG(ERR, "No memory can be allocated");
3317 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3320 for (i = 0; i < reta_size; i++) {
3321 idx = i / RTE_RETA_GROUP_SIZE;
3322 shift = i % RTE_RETA_GROUP_SIZE;
3323 if (reta_conf[idx].mask & (1ULL << shift))
3324 reta_conf[idx].reta[shift] = lut[i];
3334 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3335 * @hw: pointer to the HW structure
3336 * @mem: pointer to mem struct to fill out
3337 * @size: size of memory requested
3338 * @alignment: what to align the allocation to
3340 enum i40e_status_code
3341 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3342 struct i40e_dma_mem *mem,
3346 const struct rte_memzone *mz = NULL;
3347 char z_name[RTE_MEMZONE_NAMESIZE];
3350 return I40E_ERR_PARAM;
3352 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3353 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3354 alignment, RTE_PGSIZE_2M);
3356 return I40E_ERR_NO_MEMORY;
3360 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3361 mem->zone = (const void *)mz;
3362 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3363 "%"PRIu64, mz->name, mem->pa);
3365 return I40E_SUCCESS;
3369 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3370 * @hw: pointer to the HW structure
3371 * @mem: ptr to mem struct to free
3373 enum i40e_status_code
3374 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3375 struct i40e_dma_mem *mem)
3378 return I40E_ERR_PARAM;
3380 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3381 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3383 rte_memzone_free((const struct rte_memzone *)mem->zone);
3388 return I40E_SUCCESS;
3392 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3393 * @hw: pointer to the HW structure
3394 * @mem: pointer to mem struct to fill out
3395 * @size: size of memory requested
3397 enum i40e_status_code
3398 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3399 struct i40e_virt_mem *mem,
3403 return I40E_ERR_PARAM;
3406 mem->va = rte_zmalloc("i40e", size, 0);
3409 return I40E_SUCCESS;
3411 return I40E_ERR_NO_MEMORY;
3415 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3416 * @hw: pointer to the HW structure
3417 * @mem: pointer to mem struct to free
3419 enum i40e_status_code
3420 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3421 struct i40e_virt_mem *mem)
3424 return I40E_ERR_PARAM;
3429 return I40E_SUCCESS;
3433 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3435 rte_spinlock_init(&sp->spinlock);
3439 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3441 rte_spinlock_lock(&sp->spinlock);
3445 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3447 rte_spinlock_unlock(&sp->spinlock);
3451 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3457 * Get the hardware capabilities, which will be parsed
3458 * and saved into struct i40e_hw.
3461 i40e_get_cap(struct i40e_hw *hw)
3463 struct i40e_aqc_list_capabilities_element_resp *buf;
3464 uint16_t len, size = 0;
3467 /* Calculate a huge enough buff for saving response data temporarily */
3468 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3469 I40E_MAX_CAP_ELE_NUM;
3470 buf = rte_zmalloc("i40e", len, 0);
3472 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3473 return I40E_ERR_NO_MEMORY;
3476 /* Get, parse the capabilities and save it to hw */
3477 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3478 i40e_aqc_opc_list_func_capabilities, NULL);
3479 if (ret != I40E_SUCCESS)
3480 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3482 /* Free the temporary buffer after being used */
3489 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3491 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3492 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3493 uint16_t qp_count = 0, vsi_count = 0;
3495 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3496 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3499 /* Add the parameter init for LFC */
3500 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3501 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3502 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3504 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3505 pf->max_num_vsi = hw->func_caps.num_vsis;
3506 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3507 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3508 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3510 /* FDir queue/VSI allocation */
3511 pf->fdir_qp_offset = 0;
3512 if (hw->func_caps.fd) {
3513 pf->flags |= I40E_FLAG_FDIR;
3514 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3516 pf->fdir_nb_qps = 0;
3518 qp_count += pf->fdir_nb_qps;
3521 /* LAN queue/VSI allocation */
3522 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3523 if (!hw->func_caps.rss) {
3526 pf->flags |= I40E_FLAG_RSS;
3527 if (hw->mac.type == I40E_MAC_X722)
3528 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3529 pf->lan_nb_qps = pf->lan_nb_qp_max;
3531 qp_count += pf->lan_nb_qps;
3534 /* VF queue/VSI allocation */
3535 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3536 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3537 pf->flags |= I40E_FLAG_SRIOV;
3538 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3539 pf->vf_num = dev->pci_dev->max_vfs;
3540 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3541 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3542 pf->vf_nb_qps * pf->vf_num);
3547 qp_count += pf->vf_nb_qps * pf->vf_num;
3548 vsi_count += pf->vf_num;
3550 /* VMDq queue/VSI allocation */
3551 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3552 pf->vmdq_nb_qps = 0;
3553 pf->max_nb_vmdq_vsi = 0;
3554 if (hw->func_caps.vmdq) {
3555 if (qp_count < hw->func_caps.num_tx_qp &&
3556 vsi_count < hw->func_caps.num_vsis) {
3557 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3558 qp_count) / pf->vmdq_nb_qp_max;
3560 /* Limit the maximum number of VMDq vsi to the maximum
3561 * ethdev can support
3563 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3564 hw->func_caps.num_vsis - vsi_count);
3565 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3567 if (pf->max_nb_vmdq_vsi) {
3568 pf->flags |= I40E_FLAG_VMDQ;
3569 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3570 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3571 "per VMDQ VSI, in total %u queues",
3572 pf->max_nb_vmdq_vsi,
3573 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3574 pf->max_nb_vmdq_vsi);
3576 PMD_DRV_LOG(INFO, "No enough queues left for "
3580 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3583 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3584 vsi_count += pf->max_nb_vmdq_vsi;
3586 if (hw->func_caps.dcb)
3587 pf->flags |= I40E_FLAG_DCB;
3589 if (qp_count > hw->func_caps.num_tx_qp) {
3590 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3591 "the hardware maximum %u", qp_count,
3592 hw->func_caps.num_tx_qp);
3595 if (vsi_count > hw->func_caps.num_vsis) {
3596 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3597 "the hardware maximum %u", vsi_count,
3598 hw->func_caps.num_vsis);
3606 i40e_pf_get_switch_config(struct i40e_pf *pf)
3608 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3609 struct i40e_aqc_get_switch_config_resp *switch_config;
3610 struct i40e_aqc_switch_config_element_resp *element;
3611 uint16_t start_seid = 0, num_reported;
3614 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3615 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3616 if (!switch_config) {
3617 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3621 /* Get the switch configurations */
3622 ret = i40e_aq_get_switch_config(hw, switch_config,
3623 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3624 if (ret != I40E_SUCCESS) {
3625 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3628 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3629 if (num_reported != 1) { /* The number should be 1 */
3630 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3634 /* Parse the switch configuration elements */
3635 element = &(switch_config->element[0]);
3636 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3637 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3638 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3640 PMD_DRV_LOG(INFO, "Unknown element type");
3643 rte_free(switch_config);
3649 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3652 struct pool_entry *entry;
3654 if (pool == NULL || num == 0)
3657 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3658 if (entry == NULL) {
3659 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3663 /* queue heap initialize */
3664 pool->num_free = num;
3665 pool->num_alloc = 0;
3667 LIST_INIT(&pool->alloc_list);
3668 LIST_INIT(&pool->free_list);
3670 /* Initialize element */
3674 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3679 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3681 struct pool_entry *entry, *next_entry;
3686 for (entry = LIST_FIRST(&pool->alloc_list);
3687 entry && (next_entry = LIST_NEXT(entry, next), 1);
3688 entry = next_entry) {
3689 LIST_REMOVE(entry, next);
3693 for (entry = LIST_FIRST(&pool->free_list);
3694 entry && (next_entry = LIST_NEXT(entry, next), 1);
3695 entry = next_entry) {
3696 LIST_REMOVE(entry, next);
3701 pool->num_alloc = 0;
3703 LIST_INIT(&pool->alloc_list);
3704 LIST_INIT(&pool->free_list);
3708 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3711 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3712 uint32_t pool_offset;
3716 PMD_DRV_LOG(ERR, "Invalid parameter");
3720 pool_offset = base - pool->base;
3721 /* Lookup in alloc list */
3722 LIST_FOREACH(entry, &pool->alloc_list, next) {
3723 if (entry->base == pool_offset) {
3724 valid_entry = entry;
3725 LIST_REMOVE(entry, next);
3730 /* Not find, return */
3731 if (valid_entry == NULL) {
3732 PMD_DRV_LOG(ERR, "Failed to find entry");
3737 * Found it, move it to free list and try to merge.
3738 * In order to make merge easier, always sort it by qbase.
3739 * Find adjacent prev and last entries.
3742 LIST_FOREACH(entry, &pool->free_list, next) {
3743 if (entry->base > valid_entry->base) {
3751 /* Try to merge with next one*/
3753 /* Merge with next one */
3754 if (valid_entry->base + valid_entry->len == next->base) {
3755 next->base = valid_entry->base;
3756 next->len += valid_entry->len;
3757 rte_free(valid_entry);
3764 /* Merge with previous one */
3765 if (prev->base + prev->len == valid_entry->base) {
3766 prev->len += valid_entry->len;
3767 /* If it merge with next one, remove next node */
3769 LIST_REMOVE(valid_entry, next);
3770 rte_free(valid_entry);
3772 rte_free(valid_entry);
3778 /* Not find any entry to merge, insert */
3781 LIST_INSERT_AFTER(prev, valid_entry, next);
3782 else if (next != NULL)
3783 LIST_INSERT_BEFORE(next, valid_entry, next);
3784 else /* It's empty list, insert to head */
3785 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3788 pool->num_free += valid_entry->len;
3789 pool->num_alloc -= valid_entry->len;
3795 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3798 struct pool_entry *entry, *valid_entry;
3800 if (pool == NULL || num == 0) {
3801 PMD_DRV_LOG(ERR, "Invalid parameter");
3805 if (pool->num_free < num) {
3806 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3807 num, pool->num_free);
3812 /* Lookup in free list and find most fit one */
3813 LIST_FOREACH(entry, &pool->free_list, next) {
3814 if (entry->len >= num) {
3816 if (entry->len == num) {
3817 valid_entry = entry;
3820 if (valid_entry == NULL || valid_entry->len > entry->len)
3821 valid_entry = entry;
3825 /* Not find one to satisfy the request, return */
3826 if (valid_entry == NULL) {
3827 PMD_DRV_LOG(ERR, "No valid entry found");
3831 * The entry have equal queue number as requested,
3832 * remove it from alloc_list.
3834 if (valid_entry->len == num) {
3835 LIST_REMOVE(valid_entry, next);
3838 * The entry have more numbers than requested,
3839 * create a new entry for alloc_list and minus its
3840 * queue base and number in free_list.
3842 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3843 if (entry == NULL) {
3844 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3848 entry->base = valid_entry->base;
3850 valid_entry->base += num;
3851 valid_entry->len -= num;
3852 valid_entry = entry;
3855 /* Insert it into alloc list, not sorted */
3856 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3858 pool->num_free -= valid_entry->len;
3859 pool->num_alloc += valid_entry->len;
3861 return valid_entry->base + pool->base;
3865 * bitmap_is_subset - Check whether src2 is subset of src1
3868 bitmap_is_subset(uint8_t src1, uint8_t src2)
3870 return !((src1 ^ src2) & src2);
3873 static enum i40e_status_code
3874 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3876 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3878 /* If DCB is not supported, only default TC is supported */
3879 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3880 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3881 return I40E_NOT_SUPPORTED;
3884 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3885 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3886 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3888 return I40E_NOT_SUPPORTED;
3890 return I40E_SUCCESS;
3894 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3895 struct i40e_vsi_vlan_pvid_info *info)
3898 struct i40e_vsi_context ctxt;
3899 uint8_t vlan_flags = 0;
3902 if (vsi == NULL || info == NULL) {
3903 PMD_DRV_LOG(ERR, "invalid parameters");
3904 return I40E_ERR_PARAM;
3908 vsi->info.pvid = info->config.pvid;
3910 * If insert pvid is enabled, only tagged pkts are
3911 * allowed to be sent out.
3913 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3914 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3917 if (info->config.reject.tagged == 0)
3918 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3920 if (info->config.reject.untagged == 0)
3921 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3923 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3924 I40E_AQ_VSI_PVLAN_MODE_MASK);
3925 vsi->info.port_vlan_flags |= vlan_flags;
3926 vsi->info.valid_sections =
3927 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3928 memset(&ctxt, 0, sizeof(ctxt));
3929 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3930 ctxt.seid = vsi->seid;
3932 hw = I40E_VSI_TO_HW(vsi);
3933 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3934 if (ret != I40E_SUCCESS)
3935 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3941 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3943 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3945 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3947 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3948 if (ret != I40E_SUCCESS)
3952 PMD_DRV_LOG(ERR, "seid not valid");
3956 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3957 tc_bw_data.tc_valid_bits = enabled_tcmap;
3958 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3959 tc_bw_data.tc_bw_credits[i] =
3960 (enabled_tcmap & (1 << i)) ? 1 : 0;
3962 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3963 if (ret != I40E_SUCCESS) {
3964 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3968 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3969 sizeof(vsi->info.qs_handle));
3970 return I40E_SUCCESS;
3973 static enum i40e_status_code
3974 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3975 struct i40e_aqc_vsi_properties_data *info,
3976 uint8_t enabled_tcmap)
3978 enum i40e_status_code ret;
3979 int i, total_tc = 0;
3980 uint16_t qpnum_per_tc, bsf, qp_idx;
3982 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3983 if (ret != I40E_SUCCESS)
3986 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3987 if (enabled_tcmap & (1 << i))
3989 vsi->enabled_tc = enabled_tcmap;
3991 /* Number of queues per enabled TC */
3992 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3993 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3994 bsf = rte_bsf32(qpnum_per_tc);
3996 /* Adjust the queue number to actual queues that can be applied */
3997 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3998 vsi->nb_qps = qpnum_per_tc * total_tc;
4001 * Configure TC and queue mapping parameters, for enabled TC,
4002 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4003 * default queue will serve it.
4006 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4007 if (vsi->enabled_tc & (1 << i)) {
4008 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4009 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4010 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4011 qp_idx += qpnum_per_tc;
4013 info->tc_mapping[i] = 0;
4016 /* Associate queue number with VSI */
4017 if (vsi->type == I40E_VSI_SRIOV) {
4018 info->mapping_flags |=
4019 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4020 for (i = 0; i < vsi->nb_qps; i++)
4021 info->queue_mapping[i] =
4022 rte_cpu_to_le_16(vsi->base_queue + i);
4024 info->mapping_flags |=
4025 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4026 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4028 info->valid_sections |=
4029 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4031 return I40E_SUCCESS;
4035 i40e_veb_release(struct i40e_veb *veb)
4037 struct i40e_vsi *vsi;
4043 if (!TAILQ_EMPTY(&veb->head)) {
4044 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4047 /* associate_vsi field is NULL for floating VEB */
4048 if (veb->associate_vsi != NULL) {
4049 vsi = veb->associate_vsi;
4050 hw = I40E_VSI_TO_HW(vsi);
4052 vsi->uplink_seid = veb->uplink_seid;
4055 veb->associate_pf->main_vsi->floating_veb = NULL;
4056 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4059 i40e_aq_delete_element(hw, veb->seid, NULL);
4061 return I40E_SUCCESS;
4065 static struct i40e_veb *
4066 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4068 struct i40e_veb *veb;
4074 "veb setup failed, associated PF shouldn't null");
4077 hw = I40E_PF_TO_HW(pf);
4079 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4081 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4085 veb->associate_vsi = vsi;
4086 veb->associate_pf = pf;
4087 TAILQ_INIT(&veb->head);
4088 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4090 /* create floating veb if vsi is NULL */
4092 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4093 I40E_DEFAULT_TCMAP, false,
4094 &veb->seid, false, NULL);
4096 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4097 true, &veb->seid, false, NULL);
4100 if (ret != I40E_SUCCESS) {
4101 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4102 hw->aq.asq_last_status);
4106 /* get statistics index */
4107 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4108 &veb->stats_idx, NULL, NULL, NULL);
4109 if (ret != I40E_SUCCESS) {
4110 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4111 hw->aq.asq_last_status);
4114 /* Get VEB bandwidth, to be implemented */
4115 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4117 vsi->uplink_seid = veb->seid;
4126 i40e_vsi_release(struct i40e_vsi *vsi)
4130 struct i40e_vsi_list *vsi_list;
4133 struct i40e_mac_filter *f;
4134 uint16_t user_param;
4137 return I40E_SUCCESS;
4139 user_param = vsi->user_param;
4141 pf = I40E_VSI_TO_PF(vsi);
4142 hw = I40E_VSI_TO_HW(vsi);
4144 /* VSI has child to attach, release child first */
4146 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4147 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4150 i40e_veb_release(vsi->veb);
4153 if (vsi->floating_veb) {
4154 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4155 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4160 /* Remove all macvlan filters of the VSI */
4161 i40e_vsi_remove_all_macvlan_filter(vsi);
4162 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4165 if (vsi->type != I40E_VSI_MAIN &&
4166 ((vsi->type != I40E_VSI_SRIOV) ||
4167 !pf->floating_veb_list[user_param])) {
4168 /* Remove vsi from parent's sibling list */
4169 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4170 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4171 return I40E_ERR_PARAM;
4173 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4174 &vsi->sib_vsi_list, list);
4176 /* Remove all switch element of the VSI */
4177 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4178 if (ret != I40E_SUCCESS)
4179 PMD_DRV_LOG(ERR, "Failed to delete element");
4182 if ((vsi->type == I40E_VSI_SRIOV) &&
4183 pf->floating_veb_list[user_param]) {
4184 /* Remove vsi from parent's sibling list */
4185 if (vsi->parent_vsi == NULL ||
4186 vsi->parent_vsi->floating_veb == NULL) {
4187 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4188 return I40E_ERR_PARAM;
4190 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4191 &vsi->sib_vsi_list, list);
4193 /* Remove all switch element of the VSI */
4194 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4195 if (ret != I40E_SUCCESS)
4196 PMD_DRV_LOG(ERR, "Failed to delete element");
4199 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4201 if (vsi->type != I40E_VSI_SRIOV)
4202 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4205 return I40E_SUCCESS;
4209 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4211 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4212 struct i40e_aqc_remove_macvlan_element_data def_filter;
4213 struct i40e_mac_filter_info filter;
4216 if (vsi->type != I40E_VSI_MAIN)
4217 return I40E_ERR_CONFIG;
4218 memset(&def_filter, 0, sizeof(def_filter));
4219 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4221 def_filter.vlan_tag = 0;
4222 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4223 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4224 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4225 if (ret != I40E_SUCCESS) {
4226 struct i40e_mac_filter *f;
4227 struct ether_addr *mac;
4229 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4231 /* It needs to add the permanent mac into mac list */
4232 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4234 PMD_DRV_LOG(ERR, "failed to allocate memory");
4235 return I40E_ERR_NO_MEMORY;
4237 mac = &f->mac_info.mac_addr;
4238 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4240 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4241 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4246 (void)rte_memcpy(&filter.mac_addr,
4247 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4248 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4249 return i40e_vsi_add_mac(vsi, &filter);
4253 * i40e_vsi_get_bw_config - Query VSI BW Information
4254 * @vsi: the VSI to be queried
4256 * Returns 0 on success, negative value on failure
4258 static enum i40e_status_code
4259 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4261 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4262 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4263 struct i40e_hw *hw = &vsi->adapter->hw;
4268 memset(&bw_config, 0, sizeof(bw_config));
4269 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4270 if (ret != I40E_SUCCESS) {
4271 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4272 hw->aq.asq_last_status);
4276 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4277 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4278 &ets_sla_config, NULL);
4279 if (ret != I40E_SUCCESS) {
4280 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4281 "configuration %u", hw->aq.asq_last_status);
4285 /* store and print out BW info */
4286 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4287 vsi->bw_info.bw_max = bw_config.max_bw;
4288 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4289 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4290 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4291 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4293 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4294 vsi->bw_info.bw_ets_share_credits[i] =
4295 ets_sla_config.share_credits[i];
4296 vsi->bw_info.bw_ets_credits[i] =
4297 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4298 /* 4 bits per TC, 4th bit is reserved */
4299 vsi->bw_info.bw_ets_max[i] =
4300 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4301 RTE_LEN2MASK(3, uint8_t));
4302 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4303 vsi->bw_info.bw_ets_share_credits[i]);
4304 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4305 vsi->bw_info.bw_ets_credits[i]);
4306 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4307 vsi->bw_info.bw_ets_max[i]);
4310 return I40E_SUCCESS;
4313 /* i40e_enable_pf_lb
4314 * @pf: pointer to the pf structure
4316 * allow loopback on pf
4319 i40e_enable_pf_lb(struct i40e_pf *pf)
4321 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4322 struct i40e_vsi_context ctxt;
4325 /* Use the FW API if FW >= v5.0 */
4326 if (hw->aq.fw_maj_ver < 5) {
4327 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4331 memset(&ctxt, 0, sizeof(ctxt));
4332 ctxt.seid = pf->main_vsi_seid;
4333 ctxt.pf_num = hw->pf_id;
4334 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4336 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4337 ret, hw->aq.asq_last_status);
4340 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4341 ctxt.info.valid_sections =
4342 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4343 ctxt.info.switch_id |=
4344 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4346 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4348 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4349 hw->aq.asq_last_status);
4354 i40e_vsi_setup(struct i40e_pf *pf,
4355 enum i40e_vsi_type type,
4356 struct i40e_vsi *uplink_vsi,
4357 uint16_t user_param)
4359 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4360 struct i40e_vsi *vsi;
4361 struct i40e_mac_filter_info filter;
4363 struct i40e_vsi_context ctxt;
4364 struct ether_addr broadcast =
4365 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4367 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4368 uplink_vsi == NULL) {
4369 PMD_DRV_LOG(ERR, "VSI setup failed, "
4370 "VSI link shouldn't be NULL");
4374 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4375 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4376 "uplink VSI should be NULL");
4381 * 1.type is not MAIN and uplink vsi is not NULL
4382 * If uplink vsi didn't setup VEB, create one first under veb field
4383 * 2.type is SRIOV and the uplink is NULL
4384 * If floating VEB is NULL, create one veb under floating veb field
4387 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4388 uplink_vsi->veb == NULL) {
4389 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4391 if (uplink_vsi->veb == NULL) {
4392 PMD_DRV_LOG(ERR, "VEB setup failed");
4395 /* set ALLOWLOOPBACk on pf, when veb is created */
4396 i40e_enable_pf_lb(pf);
4399 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4400 pf->main_vsi->floating_veb == NULL) {
4401 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4403 if (pf->main_vsi->floating_veb == NULL) {
4404 PMD_DRV_LOG(ERR, "VEB setup failed");
4409 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4411 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4414 TAILQ_INIT(&vsi->mac_list);
4416 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4417 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4418 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4419 vsi->user_param = user_param;
4420 /* Allocate queues */
4421 switch (vsi->type) {
4422 case I40E_VSI_MAIN :
4423 vsi->nb_qps = pf->lan_nb_qps;
4425 case I40E_VSI_SRIOV :
4426 vsi->nb_qps = pf->vf_nb_qps;
4428 case I40E_VSI_VMDQ2:
4429 vsi->nb_qps = pf->vmdq_nb_qps;
4432 vsi->nb_qps = pf->fdir_nb_qps;
4438 * The filter status descriptor is reported in rx queue 0,
4439 * while the tx queue for fdir filter programming has no
4440 * such constraints, can be non-zero queues.
4441 * To simplify it, choose FDIR vsi use queue 0 pair.
4442 * To make sure it will use queue 0 pair, queue allocation
4443 * need be done before this function is called
4445 if (type != I40E_VSI_FDIR) {
4446 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4448 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4452 vsi->base_queue = ret;
4454 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4456 /* VF has MSIX interrupt in VF range, don't allocate here */
4457 if (type == I40E_VSI_MAIN) {
4458 ret = i40e_res_pool_alloc(&pf->msix_pool,
4459 RTE_MIN(vsi->nb_qps,
4460 RTE_MAX_RXTX_INTR_VEC_ID));
4462 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4464 goto fail_queue_alloc;
4466 vsi->msix_intr = ret;
4467 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4468 } else if (type != I40E_VSI_SRIOV) {
4469 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4471 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4472 goto fail_queue_alloc;
4474 vsi->msix_intr = ret;
4482 if (type == I40E_VSI_MAIN) {
4483 /* For main VSI, no need to add since it's default one */
4484 vsi->uplink_seid = pf->mac_seid;
4485 vsi->seid = pf->main_vsi_seid;
4486 /* Bind queues with specific MSIX interrupt */
4488 * Needs 2 interrupt at least, one for misc cause which will
4489 * enabled from OS side, Another for queues binding the
4490 * interrupt from device side only.
4493 /* Get default VSI parameters from hardware */
4494 memset(&ctxt, 0, sizeof(ctxt));
4495 ctxt.seid = vsi->seid;
4496 ctxt.pf_num = hw->pf_id;
4497 ctxt.uplink_seid = vsi->uplink_seid;
4499 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4500 if (ret != I40E_SUCCESS) {
4501 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4502 goto fail_msix_alloc;
4504 (void)rte_memcpy(&vsi->info, &ctxt.info,
4505 sizeof(struct i40e_aqc_vsi_properties_data));
4506 vsi->vsi_id = ctxt.vsi_number;
4507 vsi->info.valid_sections = 0;
4509 /* Configure tc, enabled TC0 only */
4510 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4512 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4513 goto fail_msix_alloc;
4516 /* TC, queue mapping */
4517 memset(&ctxt, 0, sizeof(ctxt));
4518 vsi->info.valid_sections |=
4519 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4520 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4521 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4522 (void)rte_memcpy(&ctxt.info, &vsi->info,
4523 sizeof(struct i40e_aqc_vsi_properties_data));
4524 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4525 I40E_DEFAULT_TCMAP);
4526 if (ret != I40E_SUCCESS) {
4527 PMD_DRV_LOG(ERR, "Failed to configure "
4528 "TC queue mapping");
4529 goto fail_msix_alloc;
4531 ctxt.seid = vsi->seid;
4532 ctxt.pf_num = hw->pf_id;
4533 ctxt.uplink_seid = vsi->uplink_seid;
4536 /* Update VSI parameters */
4537 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4538 if (ret != I40E_SUCCESS) {
4539 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4540 goto fail_msix_alloc;
4543 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4544 sizeof(vsi->info.tc_mapping));
4545 (void)rte_memcpy(&vsi->info.queue_mapping,
4546 &ctxt.info.queue_mapping,
4547 sizeof(vsi->info.queue_mapping));
4548 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4549 vsi->info.valid_sections = 0;
4551 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4555 * Updating default filter settings are necessary to prevent
4556 * reception of tagged packets.
4557 * Some old firmware configurations load a default macvlan
4558 * filter which accepts both tagged and untagged packets.
4559 * The updating is to use a normal filter instead if needed.
4560 * For NVM 4.2.2 or after, the updating is not needed anymore.
4561 * The firmware with correct configurations load the default
4562 * macvlan filter which is expected and cannot be removed.
4564 i40e_update_default_filter_setting(vsi);
4565 i40e_config_qinq(hw, vsi);
4566 } else if (type == I40E_VSI_SRIOV) {
4567 memset(&ctxt, 0, sizeof(ctxt));
4569 * For other VSI, the uplink_seid equals to uplink VSI's
4570 * uplink_seid since they share same VEB
4572 if (uplink_vsi == NULL)
4573 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4575 vsi->uplink_seid = uplink_vsi->uplink_seid;
4576 ctxt.pf_num = hw->pf_id;
4577 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4578 ctxt.uplink_seid = vsi->uplink_seid;
4579 ctxt.connection_type = 0x1;
4580 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4582 /* Use the VEB configuration if FW >= v5.0 */
4583 if (hw->aq.fw_maj_ver >= 5) {
4584 /* Configure switch ID */
4585 ctxt.info.valid_sections |=
4586 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4587 ctxt.info.switch_id =
4588 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4591 /* Configure port/vlan */
4592 ctxt.info.valid_sections |=
4593 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4594 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4595 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4596 I40E_DEFAULT_TCMAP);
4597 if (ret != I40E_SUCCESS) {
4598 PMD_DRV_LOG(ERR, "Failed to configure "
4599 "TC queue mapping");
4600 goto fail_msix_alloc;
4602 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4603 ctxt.info.valid_sections |=
4604 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4606 * Since VSI is not created yet, only configure parameter,
4607 * will add vsi below.
4610 i40e_config_qinq(hw, vsi);
4611 } else if (type == I40E_VSI_VMDQ2) {
4612 memset(&ctxt, 0, sizeof(ctxt));
4614 * For other VSI, the uplink_seid equals to uplink VSI's
4615 * uplink_seid since they share same VEB
4617 vsi->uplink_seid = uplink_vsi->uplink_seid;
4618 ctxt.pf_num = hw->pf_id;
4620 ctxt.uplink_seid = vsi->uplink_seid;
4621 ctxt.connection_type = 0x1;
4622 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4624 ctxt.info.valid_sections |=
4625 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4626 /* user_param carries flag to enable loop back */
4628 ctxt.info.switch_id =
4629 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4630 ctxt.info.switch_id |=
4631 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4634 /* Configure port/vlan */
4635 ctxt.info.valid_sections |=
4636 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4637 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4638 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4639 I40E_DEFAULT_TCMAP);
4640 if (ret != I40E_SUCCESS) {
4641 PMD_DRV_LOG(ERR, "Failed to configure "
4642 "TC queue mapping");
4643 goto fail_msix_alloc;
4645 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4646 ctxt.info.valid_sections |=
4647 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4648 } else if (type == I40E_VSI_FDIR) {
4649 memset(&ctxt, 0, sizeof(ctxt));
4650 vsi->uplink_seid = uplink_vsi->uplink_seid;
4651 ctxt.pf_num = hw->pf_id;
4653 ctxt.uplink_seid = vsi->uplink_seid;
4654 ctxt.connection_type = 0x1; /* regular data port */
4655 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4656 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4657 I40E_DEFAULT_TCMAP);
4658 if (ret != I40E_SUCCESS) {
4659 PMD_DRV_LOG(ERR, "Failed to configure "
4660 "TC queue mapping.");
4661 goto fail_msix_alloc;
4663 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4664 ctxt.info.valid_sections |=
4665 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4667 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4668 goto fail_msix_alloc;
4671 if (vsi->type != I40E_VSI_MAIN) {
4672 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4673 if (ret != I40E_SUCCESS) {
4674 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4675 hw->aq.asq_last_status);
4676 goto fail_msix_alloc;
4678 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4679 vsi->info.valid_sections = 0;
4680 vsi->seid = ctxt.seid;
4681 vsi->vsi_id = ctxt.vsi_number;
4682 vsi->sib_vsi_list.vsi = vsi;
4683 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4684 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4685 &vsi->sib_vsi_list, list);
4687 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4688 &vsi->sib_vsi_list, list);
4692 /* MAC/VLAN configuration */
4693 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4694 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4696 ret = i40e_vsi_add_mac(vsi, &filter);
4697 if (ret != I40E_SUCCESS) {
4698 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4699 goto fail_msix_alloc;
4702 /* Get VSI BW information */
4703 i40e_vsi_get_bw_config(vsi);
4706 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4708 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4714 /* Configure vlan filter on or off */
4716 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4719 struct i40e_mac_filter *f;
4721 struct i40e_mac_filter_info *mac_filter;
4722 enum rte_mac_filter_type desired_filter;
4723 int ret = I40E_SUCCESS;
4726 /* Filter to match MAC and VLAN */
4727 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4729 /* Filter to match only MAC */
4730 desired_filter = RTE_MAC_PERFECT_MATCH;
4735 mac_filter = rte_zmalloc("mac_filter_info_data",
4736 num * sizeof(*mac_filter), 0);
4737 if (mac_filter == NULL) {
4738 PMD_DRV_LOG(ERR, "failed to allocate memory");
4739 return I40E_ERR_NO_MEMORY;
4744 /* Remove all existing mac */
4745 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4746 mac_filter[i] = f->mac_info;
4747 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4749 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4750 on ? "enable" : "disable");
4756 /* Override with new filter */
4757 for (i = 0; i < num; i++) {
4758 mac_filter[i].filter_type = desired_filter;
4759 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4761 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4762 on ? "enable" : "disable");
4768 rte_free(mac_filter);
4772 /* Configure vlan stripping on or off */
4774 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4776 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4777 struct i40e_vsi_context ctxt;
4779 int ret = I40E_SUCCESS;
4781 /* Check if it has been already on or off */
4782 if (vsi->info.valid_sections &
4783 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4785 if ((vsi->info.port_vlan_flags &
4786 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4787 return 0; /* already on */
4789 if ((vsi->info.port_vlan_flags &
4790 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4791 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4792 return 0; /* already off */
4797 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4799 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4800 vsi->info.valid_sections =
4801 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4802 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4803 vsi->info.port_vlan_flags |= vlan_flags;
4804 ctxt.seid = vsi->seid;
4805 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4806 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4808 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4809 on ? "enable" : "disable");
4815 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4817 struct rte_eth_dev_data *data = dev->data;
4821 /* Apply vlan offload setting */
4822 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4823 i40e_vlan_offload_set(dev, mask);
4825 /* Apply double-vlan setting, not implemented yet */
4827 /* Apply pvid setting */
4828 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4829 data->dev_conf.txmode.hw_vlan_insert_pvid);
4831 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4837 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4839 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4841 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4845 i40e_update_flow_control(struct i40e_hw *hw)
4847 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4848 struct i40e_link_status link_status;
4849 uint32_t rxfc = 0, txfc = 0, reg;
4853 memset(&link_status, 0, sizeof(link_status));
4854 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4855 if (ret != I40E_SUCCESS) {
4856 PMD_DRV_LOG(ERR, "Failed to get link status information");
4857 goto write_reg; /* Disable flow control */
4860 an_info = hw->phy.link_info.an_info;
4861 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4862 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4863 ret = I40E_ERR_NOT_READY;
4864 goto write_reg; /* Disable flow control */
4867 * If link auto negotiation is enabled, flow control needs to
4868 * be configured according to it
4870 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4871 case I40E_LINK_PAUSE_RXTX:
4874 hw->fc.current_mode = I40E_FC_FULL;
4876 case I40E_AQ_LINK_PAUSE_RX:
4878 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4880 case I40E_AQ_LINK_PAUSE_TX:
4882 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4885 hw->fc.current_mode = I40E_FC_NONE;
4890 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4891 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4892 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4893 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4894 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4895 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4902 i40e_pf_setup(struct i40e_pf *pf)
4904 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4905 struct i40e_filter_control_settings settings;
4906 struct i40e_vsi *vsi;
4909 /* Clear all stats counters */
4910 pf->offset_loaded = FALSE;
4911 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4912 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4914 ret = i40e_pf_get_switch_config(pf);
4915 if (ret != I40E_SUCCESS) {
4916 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4919 if (pf->flags & I40E_FLAG_FDIR) {
4920 /* make queue allocated first, let FDIR use queue pair 0*/
4921 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4922 if (ret != I40E_FDIR_QUEUE_ID) {
4923 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4925 pf->flags &= ~I40E_FLAG_FDIR;
4928 /* main VSI setup */
4929 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4931 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4932 return I40E_ERR_NOT_READY;
4936 /* Configure filter control */
4937 memset(&settings, 0, sizeof(settings));
4938 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4939 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4940 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4941 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4943 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4944 hw->func_caps.rss_table_size);
4945 return I40E_ERR_PARAM;
4947 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4948 "size: %u\n", hw->func_caps.rss_table_size);
4949 pf->hash_lut_size = hw->func_caps.rss_table_size;
4951 /* Enable ethtype and macvlan filters */
4952 settings.enable_ethtype = TRUE;
4953 settings.enable_macvlan = TRUE;
4954 ret = i40e_set_filter_control(hw, &settings);
4956 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4959 /* Update flow control according to the auto negotiation */
4960 i40e_update_flow_control(hw);
4962 return I40E_SUCCESS;
4966 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4972 * Set or clear TX Queue Disable flags,
4973 * which is required by hardware.
4975 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4976 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4978 /* Wait until the request is finished */
4979 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4980 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4981 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4982 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4983 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4989 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4990 return I40E_SUCCESS; /* already on, skip next steps */
4992 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4993 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4995 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4996 return I40E_SUCCESS; /* already off, skip next steps */
4997 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4999 /* Write the register */
5000 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5001 /* Check the result */
5002 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5003 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5004 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5006 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5007 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5010 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5011 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5015 /* Check if it is timeout */
5016 if (j >= I40E_CHK_Q_ENA_COUNT) {
5017 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5018 (on ? "enable" : "disable"), q_idx);
5019 return I40E_ERR_TIMEOUT;
5022 return I40E_SUCCESS;
5025 /* Swith on or off the tx queues */
5027 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5029 struct rte_eth_dev_data *dev_data = pf->dev_data;
5030 struct i40e_tx_queue *txq;
5031 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5035 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5036 txq = dev_data->tx_queues[i];
5037 /* Don't operate the queue if not configured or
5038 * if starting only per queue */
5039 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5042 ret = i40e_dev_tx_queue_start(dev, i);
5044 ret = i40e_dev_tx_queue_stop(dev, i);
5045 if ( ret != I40E_SUCCESS)
5049 return I40E_SUCCESS;
5053 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5058 /* Wait until the request is finished */
5059 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5060 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5061 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5062 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5063 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5068 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5069 return I40E_SUCCESS; /* Already on, skip next steps */
5070 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5072 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5073 return I40E_SUCCESS; /* Already off, skip next steps */
5074 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5077 /* Write the register */
5078 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5079 /* Check the result */
5080 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5081 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5082 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5084 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5085 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5088 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5089 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5094 /* Check if it is timeout */
5095 if (j >= I40E_CHK_Q_ENA_COUNT) {
5096 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5097 (on ? "enable" : "disable"), q_idx);
5098 return I40E_ERR_TIMEOUT;
5101 return I40E_SUCCESS;
5103 /* Switch on or off the rx queues */
5105 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5107 struct rte_eth_dev_data *dev_data = pf->dev_data;
5108 struct i40e_rx_queue *rxq;
5109 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5113 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5114 rxq = dev_data->rx_queues[i];
5115 /* Don't operate the queue if not configured or
5116 * if starting only per queue */
5117 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5120 ret = i40e_dev_rx_queue_start(dev, i);
5122 ret = i40e_dev_rx_queue_stop(dev, i);
5123 if (ret != I40E_SUCCESS)
5127 return I40E_SUCCESS;
5130 /* Switch on or off all the rx/tx queues */
5132 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5137 /* enable rx queues before enabling tx queues */
5138 ret = i40e_dev_switch_rx_queues(pf, on);
5140 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5143 ret = i40e_dev_switch_tx_queues(pf, on);
5145 /* Stop tx queues before stopping rx queues */
5146 ret = i40e_dev_switch_tx_queues(pf, on);
5148 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5151 ret = i40e_dev_switch_rx_queues(pf, on);
5157 /* Initialize VSI for TX */
5159 i40e_dev_tx_init(struct i40e_pf *pf)
5161 struct rte_eth_dev_data *data = pf->dev_data;
5163 uint32_t ret = I40E_SUCCESS;
5164 struct i40e_tx_queue *txq;
5166 for (i = 0; i < data->nb_tx_queues; i++) {
5167 txq = data->tx_queues[i];
5168 if (!txq || !txq->q_set)
5170 ret = i40e_tx_queue_init(txq);
5171 if (ret != I40E_SUCCESS)
5174 if (ret == I40E_SUCCESS)
5175 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5181 /* Initialize VSI for RX */
5183 i40e_dev_rx_init(struct i40e_pf *pf)
5185 struct rte_eth_dev_data *data = pf->dev_data;
5186 int ret = I40E_SUCCESS;
5188 struct i40e_rx_queue *rxq;
5190 i40e_pf_config_mq_rx(pf);
5191 for (i = 0; i < data->nb_rx_queues; i++) {
5192 rxq = data->rx_queues[i];
5193 if (!rxq || !rxq->q_set)
5196 ret = i40e_rx_queue_init(rxq);
5197 if (ret != I40E_SUCCESS) {
5198 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5203 if (ret == I40E_SUCCESS)
5204 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5211 i40e_dev_rxtx_init(struct i40e_pf *pf)
5215 err = i40e_dev_tx_init(pf);
5217 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5220 err = i40e_dev_rx_init(pf);
5222 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5230 i40e_vmdq_setup(struct rte_eth_dev *dev)
5232 struct rte_eth_conf *conf = &dev->data->dev_conf;
5233 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5234 int i, err, conf_vsis, j, loop;
5235 struct i40e_vsi *vsi;
5236 struct i40e_vmdq_info *vmdq_info;
5237 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5238 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5241 * Disable interrupt to avoid message from VF. Furthermore, it will
5242 * avoid race condition in VSI creation/destroy.
5244 i40e_pf_disable_irq0(hw);
5246 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5247 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5251 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5252 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5253 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5254 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5255 pf->max_nb_vmdq_vsi);
5259 if (pf->vmdq != NULL) {
5260 PMD_INIT_LOG(INFO, "VMDQ already configured");
5264 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5265 sizeof(*vmdq_info) * conf_vsis, 0);
5267 if (pf->vmdq == NULL) {
5268 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5272 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5274 /* Create VMDQ VSI */
5275 for (i = 0; i < conf_vsis; i++) {
5276 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5277 vmdq_conf->enable_loop_back);
5279 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5283 vmdq_info = &pf->vmdq[i];
5285 vmdq_info->vsi = vsi;
5287 pf->nb_cfg_vmdq_vsi = conf_vsis;
5289 /* Configure Vlan */
5290 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5291 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5292 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5293 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5294 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5295 vmdq_conf->pool_map[i].vlan_id, j);
5297 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5298 vmdq_conf->pool_map[i].vlan_id);
5300 PMD_INIT_LOG(ERR, "Failed to add vlan");
5308 i40e_pf_enable_irq0(hw);
5313 for (i = 0; i < conf_vsis; i++)
5314 if (pf->vmdq[i].vsi == NULL)
5317 i40e_vsi_release(pf->vmdq[i].vsi);
5321 i40e_pf_enable_irq0(hw);
5326 i40e_stat_update_32(struct i40e_hw *hw,
5334 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5338 if (new_data >= *offset)
5339 *stat = (uint64_t)(new_data - *offset);
5341 *stat = (uint64_t)((new_data +
5342 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5346 i40e_stat_update_48(struct i40e_hw *hw,
5355 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5356 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5357 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5362 if (new_data >= *offset)
5363 *stat = new_data - *offset;
5365 *stat = (uint64_t)((new_data +
5366 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5368 *stat &= I40E_48_BIT_MASK;
5373 i40e_pf_disable_irq0(struct i40e_hw *hw)
5375 /* Disable all interrupt types */
5376 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5377 I40E_WRITE_FLUSH(hw);
5382 i40e_pf_enable_irq0(struct i40e_hw *hw)
5384 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5385 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5386 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5387 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5388 I40E_WRITE_FLUSH(hw);
5392 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5394 /* read pending request and disable first */
5395 i40e_pf_disable_irq0(hw);
5396 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5397 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5398 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5401 /* Link no queues with irq0 */
5402 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5403 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5407 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5409 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5410 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5413 uint32_t index, offset, val;
5418 * Try to find which VF trigger a reset, use absolute VF id to access
5419 * since the reg is global register.
5421 for (i = 0; i < pf->vf_num; i++) {
5422 abs_vf_id = hw->func_caps.vf_base_id + i;
5423 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5424 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5425 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5426 /* VFR event occured */
5427 if (val & (0x1 << offset)) {
5430 /* Clear the event first */
5431 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5433 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5435 * Only notify a VF reset event occured,
5436 * don't trigger another SW reset
5438 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5439 if (ret != I40E_SUCCESS)
5440 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5446 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5448 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5449 struct i40e_arq_event_info info;
5450 uint16_t pending, opcode;
5453 info.buf_len = I40E_AQ_BUF_SZ;
5454 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5455 if (!info.msg_buf) {
5456 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5462 ret = i40e_clean_arq_element(hw, &info, &pending);
5464 if (ret != I40E_SUCCESS) {
5465 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5466 "aq_err: %u", hw->aq.asq_last_status);
5469 opcode = rte_le_to_cpu_16(info.desc.opcode);
5472 case i40e_aqc_opc_send_msg_to_pf:
5473 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5474 i40e_pf_host_handle_vf_msg(dev,
5475 rte_le_to_cpu_16(info.desc.retval),
5476 rte_le_to_cpu_32(info.desc.cookie_high),
5477 rte_le_to_cpu_32(info.desc.cookie_low),
5481 case i40e_aqc_opc_get_link_status:
5482 ret = i40e_dev_link_update(dev, 0);
5484 _rte_eth_dev_callback_process(dev,
5485 RTE_ETH_EVENT_INTR_LSC, NULL);
5488 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5493 rte_free(info.msg_buf);
5497 * Interrupt handler triggered by NIC for handling
5498 * specific interrupt.
5501 * Pointer to interrupt handle.
5503 * The address of parameter (struct rte_eth_dev *) regsitered before.
5509 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5512 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5513 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5516 /* Disable interrupt */
5517 i40e_pf_disable_irq0(hw);
5519 /* read out interrupt causes */
5520 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5522 /* No interrupt event indicated */
5523 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5524 PMD_DRV_LOG(INFO, "No interrupt event");
5527 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5528 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5529 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5530 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5531 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5532 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5533 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5534 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5535 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5536 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5537 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5538 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5539 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5540 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5541 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5542 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5544 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5545 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5546 i40e_dev_handle_vfr_event(dev);
5548 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5549 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5550 i40e_dev_handle_aq_msg(dev);
5554 /* Enable interrupt */
5555 i40e_pf_enable_irq0(hw);
5556 rte_intr_enable(&(dev->pci_dev->intr_handle));
5560 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5561 struct i40e_macvlan_filter *filter,
5564 int ele_num, ele_buff_size;
5565 int num, actual_num, i;
5567 int ret = I40E_SUCCESS;
5568 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5569 struct i40e_aqc_add_macvlan_element_data *req_list;
5571 if (filter == NULL || total == 0)
5572 return I40E_ERR_PARAM;
5573 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5574 ele_buff_size = hw->aq.asq_buf_size;
5576 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5577 if (req_list == NULL) {
5578 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5579 return I40E_ERR_NO_MEMORY;
5584 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5585 memset(req_list, 0, ele_buff_size);
5587 for (i = 0; i < actual_num; i++) {
5588 (void)rte_memcpy(req_list[i].mac_addr,
5589 &filter[num + i].macaddr, ETH_ADDR_LEN);
5590 req_list[i].vlan_tag =
5591 rte_cpu_to_le_16(filter[num + i].vlan_id);
5593 switch (filter[num + i].filter_type) {
5594 case RTE_MAC_PERFECT_MATCH:
5595 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5596 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5598 case RTE_MACVLAN_PERFECT_MATCH:
5599 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5601 case RTE_MAC_HASH_MATCH:
5602 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5603 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5605 case RTE_MACVLAN_HASH_MATCH:
5606 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5609 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5610 ret = I40E_ERR_PARAM;
5614 req_list[i].queue_number = 0;
5616 req_list[i].flags = rte_cpu_to_le_16(flags);
5619 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5621 if (ret != I40E_SUCCESS) {
5622 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5626 } while (num < total);
5634 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5635 struct i40e_macvlan_filter *filter,
5638 int ele_num, ele_buff_size;
5639 int num, actual_num, i;
5641 int ret = I40E_SUCCESS;
5642 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5643 struct i40e_aqc_remove_macvlan_element_data *req_list;
5645 if (filter == NULL || total == 0)
5646 return I40E_ERR_PARAM;
5648 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5649 ele_buff_size = hw->aq.asq_buf_size;
5651 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5652 if (req_list == NULL) {
5653 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5654 return I40E_ERR_NO_MEMORY;
5659 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5660 memset(req_list, 0, ele_buff_size);
5662 for (i = 0; i < actual_num; i++) {
5663 (void)rte_memcpy(req_list[i].mac_addr,
5664 &filter[num + i].macaddr, ETH_ADDR_LEN);
5665 req_list[i].vlan_tag =
5666 rte_cpu_to_le_16(filter[num + i].vlan_id);
5668 switch (filter[num + i].filter_type) {
5669 case RTE_MAC_PERFECT_MATCH:
5670 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5671 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5673 case RTE_MACVLAN_PERFECT_MATCH:
5674 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5676 case RTE_MAC_HASH_MATCH:
5677 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5678 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5680 case RTE_MACVLAN_HASH_MATCH:
5681 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5684 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5685 ret = I40E_ERR_PARAM;
5688 req_list[i].flags = rte_cpu_to_le_16(flags);
5691 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5693 if (ret != I40E_SUCCESS) {
5694 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5698 } while (num < total);
5705 /* Find out specific MAC filter */
5706 static struct i40e_mac_filter *
5707 i40e_find_mac_filter(struct i40e_vsi *vsi,
5708 struct ether_addr *macaddr)
5710 struct i40e_mac_filter *f;
5712 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5713 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5721 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5724 uint32_t vid_idx, vid_bit;
5726 if (vlan_id > ETH_VLAN_ID_MAX)
5729 vid_idx = I40E_VFTA_IDX(vlan_id);
5730 vid_bit = I40E_VFTA_BIT(vlan_id);
5732 if (vsi->vfta[vid_idx] & vid_bit)
5739 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5740 uint16_t vlan_id, bool on)
5742 uint32_t vid_idx, vid_bit;
5744 if (vlan_id > ETH_VLAN_ID_MAX)
5747 vid_idx = I40E_VFTA_IDX(vlan_id);
5748 vid_bit = I40E_VFTA_BIT(vlan_id);
5751 vsi->vfta[vid_idx] |= vid_bit;
5753 vsi->vfta[vid_idx] &= ~vid_bit;
5757 * Find all vlan options for specific mac addr,
5758 * return with actual vlan found.
5761 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5762 struct i40e_macvlan_filter *mv_f,
5763 int num, struct ether_addr *addr)
5769 * Not to use i40e_find_vlan_filter to decrease the loop time,
5770 * although the code looks complex.
5772 if (num < vsi->vlan_num)
5773 return I40E_ERR_PARAM;
5776 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5778 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5779 if (vsi->vfta[j] & (1 << k)) {
5781 PMD_DRV_LOG(ERR, "vlan number "
5783 return I40E_ERR_PARAM;
5785 (void)rte_memcpy(&mv_f[i].macaddr,
5786 addr, ETH_ADDR_LEN);
5788 j * I40E_UINT32_BIT_SIZE + k;
5794 return I40E_SUCCESS;
5798 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5799 struct i40e_macvlan_filter *mv_f,
5804 struct i40e_mac_filter *f;
5806 if (num < vsi->mac_num)
5807 return I40E_ERR_PARAM;
5809 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5811 PMD_DRV_LOG(ERR, "buffer number not match");
5812 return I40E_ERR_PARAM;
5814 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5816 mv_f[i].vlan_id = vlan;
5817 mv_f[i].filter_type = f->mac_info.filter_type;
5821 return I40E_SUCCESS;
5825 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5828 struct i40e_mac_filter *f;
5829 struct i40e_macvlan_filter *mv_f;
5830 int ret = I40E_SUCCESS;
5832 if (vsi == NULL || vsi->mac_num == 0)
5833 return I40E_ERR_PARAM;
5835 /* Case that no vlan is set */
5836 if (vsi->vlan_num == 0)
5839 num = vsi->mac_num * vsi->vlan_num;
5841 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5843 PMD_DRV_LOG(ERR, "failed to allocate memory");
5844 return I40E_ERR_NO_MEMORY;
5848 if (vsi->vlan_num == 0) {
5849 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5850 (void)rte_memcpy(&mv_f[i].macaddr,
5851 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5852 mv_f[i].vlan_id = 0;
5856 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5857 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5858 vsi->vlan_num, &f->mac_info.mac_addr);
5859 if (ret != I40E_SUCCESS)
5865 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5873 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5875 struct i40e_macvlan_filter *mv_f;
5877 int ret = I40E_SUCCESS;
5879 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5880 return I40E_ERR_PARAM;
5882 /* If it's already set, just return */
5883 if (i40e_find_vlan_filter(vsi,vlan))
5884 return I40E_SUCCESS;
5886 mac_num = vsi->mac_num;
5889 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5890 return I40E_ERR_PARAM;
5893 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5896 PMD_DRV_LOG(ERR, "failed to allocate memory");
5897 return I40E_ERR_NO_MEMORY;
5900 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5902 if (ret != I40E_SUCCESS)
5905 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5907 if (ret != I40E_SUCCESS)
5910 i40e_set_vlan_filter(vsi, vlan, 1);
5920 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5922 struct i40e_macvlan_filter *mv_f;
5924 int ret = I40E_SUCCESS;
5927 * Vlan 0 is the generic filter for untagged packets
5928 * and can't be removed.
5930 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5931 return I40E_ERR_PARAM;
5933 /* If can't find it, just return */
5934 if (!i40e_find_vlan_filter(vsi, vlan))
5935 return I40E_ERR_PARAM;
5937 mac_num = vsi->mac_num;
5940 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5941 return I40E_ERR_PARAM;
5944 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5947 PMD_DRV_LOG(ERR, "failed to allocate memory");
5948 return I40E_ERR_NO_MEMORY;
5951 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5953 if (ret != I40E_SUCCESS)
5956 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5958 if (ret != I40E_SUCCESS)
5961 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5962 if (vsi->vlan_num == 1) {
5963 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5964 if (ret != I40E_SUCCESS)
5967 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5968 if (ret != I40E_SUCCESS)
5972 i40e_set_vlan_filter(vsi, vlan, 0);
5982 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5984 struct i40e_mac_filter *f;
5985 struct i40e_macvlan_filter *mv_f;
5986 int i, vlan_num = 0;
5987 int ret = I40E_SUCCESS;
5989 /* If it's add and we've config it, return */
5990 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5992 return I40E_SUCCESS;
5993 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5994 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5997 * If vlan_num is 0, that's the first time to add mac,
5998 * set mask for vlan_id 0.
6000 if (vsi->vlan_num == 0) {
6001 i40e_set_vlan_filter(vsi, 0, 1);
6004 vlan_num = vsi->vlan_num;
6005 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6006 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6009 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6011 PMD_DRV_LOG(ERR, "failed to allocate memory");
6012 return I40E_ERR_NO_MEMORY;
6015 for (i = 0; i < vlan_num; i++) {
6016 mv_f[i].filter_type = mac_filter->filter_type;
6017 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6021 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6022 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6023 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6024 &mac_filter->mac_addr);
6025 if (ret != I40E_SUCCESS)
6029 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6030 if (ret != I40E_SUCCESS)
6033 /* Add the mac addr into mac list */
6034 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6036 PMD_DRV_LOG(ERR, "failed to allocate memory");
6037 ret = I40E_ERR_NO_MEMORY;
6040 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6042 f->mac_info.filter_type = mac_filter->filter_type;
6043 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6054 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6056 struct i40e_mac_filter *f;
6057 struct i40e_macvlan_filter *mv_f;
6059 enum rte_mac_filter_type filter_type;
6060 int ret = I40E_SUCCESS;
6062 /* Can't find it, return an error */
6063 f = i40e_find_mac_filter(vsi, addr);
6065 return I40E_ERR_PARAM;
6067 vlan_num = vsi->vlan_num;
6068 filter_type = f->mac_info.filter_type;
6069 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6070 filter_type == RTE_MACVLAN_HASH_MATCH) {
6071 if (vlan_num == 0) {
6072 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6073 return I40E_ERR_PARAM;
6075 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6076 filter_type == RTE_MAC_HASH_MATCH)
6079 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6081 PMD_DRV_LOG(ERR, "failed to allocate memory");
6082 return I40E_ERR_NO_MEMORY;
6085 for (i = 0; i < vlan_num; i++) {
6086 mv_f[i].filter_type = filter_type;
6087 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6090 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6091 filter_type == RTE_MACVLAN_HASH_MATCH) {
6092 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6093 if (ret != I40E_SUCCESS)
6097 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6098 if (ret != I40E_SUCCESS)
6101 /* Remove the mac addr into mac list */
6102 TAILQ_REMOVE(&vsi->mac_list, f, next);
6112 /* Configure hash enable flags for RSS */
6114 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6121 if (flags & ETH_RSS_FRAG_IPV4)
6122 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6123 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6124 if (type == I40E_MAC_X722) {
6125 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6126 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6128 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6130 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6131 if (type == I40E_MAC_X722) {
6132 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6133 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6134 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6136 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6138 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6139 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6140 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6141 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6142 if (flags & ETH_RSS_FRAG_IPV6)
6143 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6144 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6145 if (type == I40E_MAC_X722) {
6146 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6149 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6151 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6152 if (type == I40E_MAC_X722) {
6153 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6154 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6155 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6157 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6159 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6160 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6161 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6162 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6163 if (flags & ETH_RSS_L2_PAYLOAD)
6164 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6169 /* Parse the hash enable flags */
6171 i40e_parse_hena(uint64_t flags)
6173 uint64_t rss_hf = 0;
6177 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6178 rss_hf |= ETH_RSS_FRAG_IPV4;
6179 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6180 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6182 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6183 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6185 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6186 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6188 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6189 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6190 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6191 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6193 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6194 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6195 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6196 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6197 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6198 rss_hf |= ETH_RSS_FRAG_IPV6;
6199 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6200 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6202 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6203 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6205 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6206 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6208 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6209 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6210 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6211 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6213 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6214 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6215 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6216 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6217 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6218 rss_hf |= ETH_RSS_L2_PAYLOAD;
6225 i40e_pf_disable_rss(struct i40e_pf *pf)
6227 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6230 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6231 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6232 if (hw->mac.type == I40E_MAC_X722)
6233 hena &= ~I40E_RSS_HENA_ALL_X722;
6235 hena &= ~I40E_RSS_HENA_ALL;
6236 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6237 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6238 I40E_WRITE_FLUSH(hw);
6242 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6244 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6245 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6248 if (!key || key_len == 0) {
6249 PMD_DRV_LOG(DEBUG, "No key to be configured");
6251 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6253 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6257 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6258 struct i40e_aqc_get_set_rss_key_data *key_dw =
6259 (struct i40e_aqc_get_set_rss_key_data *)key;
6261 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6263 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6266 uint32_t *hash_key = (uint32_t *)key;
6269 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6270 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6271 I40E_WRITE_FLUSH(hw);
6278 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6280 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6281 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6284 if (!key || !key_len)
6287 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6288 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6289 (struct i40e_aqc_get_set_rss_key_data *)key);
6291 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6295 uint32_t *key_dw = (uint32_t *)key;
6298 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6299 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6301 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6307 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6309 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6314 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6315 rss_conf->rss_key_len);
6319 rss_hf = rss_conf->rss_hf;
6320 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6321 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6322 if (hw->mac.type == I40E_MAC_X722)
6323 hena &= ~I40E_RSS_HENA_ALL_X722;
6325 hena &= ~I40E_RSS_HENA_ALL;
6326 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6327 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6328 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6329 I40E_WRITE_FLUSH(hw);
6335 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6336 struct rte_eth_rss_conf *rss_conf)
6338 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6340 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6343 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6344 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6345 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6346 ? I40E_RSS_HENA_ALL_X722
6347 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6348 if (rss_hf != 0) /* Enable RSS */
6350 return 0; /* Nothing to do */
6353 if (rss_hf == 0) /* Disable RSS */
6356 return i40e_hw_rss_hash_set(pf, rss_conf);
6360 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6361 struct rte_eth_rss_conf *rss_conf)
6363 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6364 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6367 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6368 &rss_conf->rss_key_len);
6370 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6371 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6372 rss_conf->rss_hf = i40e_parse_hena(hena);
6378 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6380 switch (filter_type) {
6381 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6382 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6384 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6385 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6387 case RTE_TUNNEL_FILTER_IMAC_TENID:
6388 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6390 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6391 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6393 case ETH_TUNNEL_FILTER_IMAC:
6394 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6396 case ETH_TUNNEL_FILTER_OIP:
6397 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6399 case ETH_TUNNEL_FILTER_IIP:
6400 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6403 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6411 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6412 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6417 uint8_t i, tun_type = 0;
6418 /* internal varialbe to convert ipv6 byte order */
6419 uint32_t convert_ipv6[4];
6421 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6422 struct i40e_vsi *vsi = pf->main_vsi;
6423 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6424 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6426 cld_filter = rte_zmalloc("tunnel_filter",
6427 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6430 if (NULL == cld_filter) {
6431 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6434 pfilter = cld_filter;
6436 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6437 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6439 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6440 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6441 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6442 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6443 rte_memcpy(&pfilter->ipaddr.v4.data,
6444 &rte_cpu_to_le_32(ipv4_addr),
6445 sizeof(pfilter->ipaddr.v4.data));
6447 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6448 for (i = 0; i < 4; i++) {
6450 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6452 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6453 sizeof(pfilter->ipaddr.v6.data));
6456 /* check tunneled type */
6457 switch (tunnel_filter->tunnel_type) {
6458 case RTE_TUNNEL_TYPE_VXLAN:
6459 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6461 case RTE_TUNNEL_TYPE_NVGRE:
6462 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6464 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6465 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6468 /* Other tunnel types is not supported. */
6469 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6470 rte_free(cld_filter);
6474 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6477 rte_free(cld_filter);
6481 pfilter->flags |= rte_cpu_to_le_16(
6482 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6483 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6484 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6485 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6488 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6490 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6493 rte_free(cld_filter);
6498 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6502 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6503 if (pf->vxlan_ports[i] == port)
6511 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6515 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6517 idx = i40e_get_vxlan_port_idx(pf, port);
6519 /* Check if port already exists */
6521 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6525 /* Now check if there is space to add the new port */
6526 idx = i40e_get_vxlan_port_idx(pf, 0);
6528 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6529 "not adding port %d", port);
6533 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6536 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6540 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6543 /* New port: add it and mark its index in the bitmap */
6544 pf->vxlan_ports[idx] = port;
6545 pf->vxlan_bitmap |= (1 << idx);
6547 if (!(pf->flags & I40E_FLAG_VXLAN))
6548 pf->flags |= I40E_FLAG_VXLAN;
6554 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6557 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6559 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6560 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6564 idx = i40e_get_vxlan_port_idx(pf, port);
6567 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6571 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6572 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6576 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6579 pf->vxlan_ports[idx] = 0;
6580 pf->vxlan_bitmap &= ~(1 << idx);
6582 if (!pf->vxlan_bitmap)
6583 pf->flags &= ~I40E_FLAG_VXLAN;
6588 /* Add UDP tunneling port */
6590 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6591 struct rte_eth_udp_tunnel *udp_tunnel)
6594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6596 if (udp_tunnel == NULL)
6599 switch (udp_tunnel->prot_type) {
6600 case RTE_TUNNEL_TYPE_VXLAN:
6601 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6604 case RTE_TUNNEL_TYPE_GENEVE:
6605 case RTE_TUNNEL_TYPE_TEREDO:
6606 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6611 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6619 /* Remove UDP tunneling port */
6621 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6622 struct rte_eth_udp_tunnel *udp_tunnel)
6625 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6627 if (udp_tunnel == NULL)
6630 switch (udp_tunnel->prot_type) {
6631 case RTE_TUNNEL_TYPE_VXLAN:
6632 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6634 case RTE_TUNNEL_TYPE_GENEVE:
6635 case RTE_TUNNEL_TYPE_TEREDO:
6636 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6640 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6648 /* Calculate the maximum number of contiguous PF queues that are configured */
6650 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6652 struct rte_eth_dev_data *data = pf->dev_data;
6654 struct i40e_rx_queue *rxq;
6657 for (i = 0; i < pf->lan_nb_qps; i++) {
6658 rxq = data->rx_queues[i];
6659 if (rxq && rxq->q_set)
6670 i40e_pf_config_rss(struct i40e_pf *pf)
6672 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6673 struct rte_eth_rss_conf rss_conf;
6674 uint32_t i, lut = 0;
6678 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6679 * It's necessary to calulate the actual PF queues that are configured.
6681 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6682 num = i40e_pf_calc_configured_queues_num(pf);
6684 num = pf->dev_data->nb_rx_queues;
6686 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6687 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6691 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6695 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6698 lut = (lut << 8) | (j & ((0x1 <<
6699 hw->func_caps.rss_table_entry_width) - 1));
6701 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6704 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6705 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6706 i40e_pf_disable_rss(pf);
6709 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6710 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6711 /* Random default keys */
6712 static uint32_t rss_key_default[] = {0x6b793944,
6713 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6714 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6715 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6717 rss_conf.rss_key = (uint8_t *)rss_key_default;
6718 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6722 return i40e_hw_rss_hash_set(pf, &rss_conf);
6726 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6727 struct rte_eth_tunnel_filter_conf *filter)
6729 if (pf == NULL || filter == NULL) {
6730 PMD_DRV_LOG(ERR, "Invalid parameter");
6734 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6735 PMD_DRV_LOG(ERR, "Invalid queue ID");
6739 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6740 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6744 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6745 (is_zero_ether_addr(&filter->outer_mac))) {
6746 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6750 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6751 (is_zero_ether_addr(&filter->inner_mac))) {
6752 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6759 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6760 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6762 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6767 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6768 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6771 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6772 } else if (len == 4) {
6773 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6775 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6780 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6787 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6788 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6794 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6801 switch (cfg->cfg_type) {
6802 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6803 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6806 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6814 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6815 enum rte_filter_op filter_op,
6818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6819 int ret = I40E_ERR_PARAM;
6821 switch (filter_op) {
6822 case RTE_ETH_FILTER_SET:
6823 ret = i40e_dev_global_config_set(hw,
6824 (struct rte_eth_global_cfg *)arg);
6827 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6835 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6836 enum rte_filter_op filter_op,
6839 struct rte_eth_tunnel_filter_conf *filter;
6840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6841 int ret = I40E_SUCCESS;
6843 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6845 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6846 return I40E_ERR_PARAM;
6848 switch (filter_op) {
6849 case RTE_ETH_FILTER_NOP:
6850 if (!(pf->flags & I40E_FLAG_VXLAN))
6851 ret = I40E_NOT_SUPPORTED;
6853 case RTE_ETH_FILTER_ADD:
6854 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6856 case RTE_ETH_FILTER_DELETE:
6857 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6860 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6861 ret = I40E_ERR_PARAM;
6869 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6872 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6875 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6876 ret = i40e_pf_config_rss(pf);
6878 i40e_pf_disable_rss(pf);
6883 /* Get the symmetric hash enable configurations per port */
6885 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6887 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6889 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6892 /* Set the symmetric hash enable configurations per port */
6894 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6896 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6899 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6900 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6904 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6906 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6907 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6911 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6913 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6914 I40E_WRITE_FLUSH(hw);
6918 * Get global configurations of hash function type and symmetric hash enable
6919 * per flow type (pctype). Note that global configuration means it affects all
6920 * the ports on the same NIC.
6923 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6924 struct rte_eth_hash_global_conf *g_cfg)
6926 uint32_t reg, mask = I40E_FLOW_TYPES;
6928 enum i40e_filter_pctype pctype;
6930 memset(g_cfg, 0, sizeof(*g_cfg));
6931 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6932 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6933 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6935 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6936 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6937 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6939 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6940 if (!(mask & (1UL << i)))
6942 mask &= ~(1UL << i);
6943 /* Bit set indicats the coresponding flow type is supported */
6944 g_cfg->valid_bit_mask[0] |= (1UL << i);
6945 /* if flowtype is invalid, continue */
6946 if (!I40E_VALID_FLOW(i))
6948 pctype = i40e_flowtype_to_pctype(i);
6949 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6950 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6951 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6958 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6961 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6963 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6964 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6965 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6966 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6972 * As i40e supports less than 32 flow types, only first 32 bits need to
6975 mask0 = g_cfg->valid_bit_mask[0];
6976 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6978 /* Check if any unsupported flow type configured */
6979 if ((mask0 | i40e_mask) ^ i40e_mask)
6982 if (g_cfg->valid_bit_mask[i])
6990 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6996 * Set global configurations of hash function type and symmetric hash enable
6997 * per flow type (pctype). Note any modifying global configuration will affect
6998 * all the ports on the same NIC.
7001 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7002 struct rte_eth_hash_global_conf *g_cfg)
7007 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7008 enum i40e_filter_pctype pctype;
7010 /* Check the input parameters */
7011 ret = i40e_hash_global_config_check(g_cfg);
7015 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7016 if (!(mask0 & (1UL << i)))
7018 mask0 &= ~(1UL << i);
7019 /* if flowtype is invalid, continue */
7020 if (!I40E_VALID_FLOW(i))
7022 pctype = i40e_flowtype_to_pctype(i);
7023 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7024 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7025 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7028 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7029 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7031 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7032 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7036 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7037 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7039 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7040 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7044 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7046 /* Use the default, and keep it as it is */
7049 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7052 I40E_WRITE_FLUSH(hw);
7058 * Valid input sets for hash and flow director filters per PCTYPE
7061 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7062 enum rte_filter_type filter)
7066 static const uint64_t valid_hash_inset_table[] = {
7067 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7068 I40E_INSET_DMAC | I40E_INSET_SMAC |
7069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7070 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7071 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7072 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7073 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7074 I40E_INSET_FLEX_PAYLOAD,
7075 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7076 I40E_INSET_DMAC | I40E_INSET_SMAC |
7077 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7078 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7079 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7080 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7081 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7082 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7083 I40E_INSET_FLEX_PAYLOAD,
7085 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7086 I40E_INSET_DMAC | I40E_INSET_SMAC |
7087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7088 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7089 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7090 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7091 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7092 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7093 I40E_INSET_FLEX_PAYLOAD,
7094 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7095 I40E_INSET_DMAC | I40E_INSET_SMAC |
7096 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7097 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7098 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7099 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7100 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7101 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7102 I40E_INSET_FLEX_PAYLOAD,
7104 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7105 I40E_INSET_DMAC | I40E_INSET_SMAC |
7106 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7107 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7108 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7109 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7110 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7111 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7112 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7114 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7115 I40E_INSET_DMAC | I40E_INSET_SMAC |
7116 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7117 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7118 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7119 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7120 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7121 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7122 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7124 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7125 I40E_INSET_DMAC | I40E_INSET_SMAC |
7126 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7127 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7128 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7129 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7130 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7131 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7132 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7133 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7134 I40E_INSET_DMAC | I40E_INSET_SMAC |
7135 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7137 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7138 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7139 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7140 I40E_INSET_FLEX_PAYLOAD,
7141 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7142 I40E_INSET_DMAC | I40E_INSET_SMAC |
7143 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7144 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7145 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7146 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7147 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7148 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7149 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7150 I40E_INSET_DMAC | I40E_INSET_SMAC |
7151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7152 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7153 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7154 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7155 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7156 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7158 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7159 I40E_INSET_DMAC | I40E_INSET_SMAC |
7160 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7161 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7162 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7163 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7164 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7165 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7166 I40E_INSET_FLEX_PAYLOAD,
7167 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7168 I40E_INSET_DMAC | I40E_INSET_SMAC |
7169 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7170 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7171 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7172 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7173 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7174 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7175 I40E_INSET_FLEX_PAYLOAD,
7177 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7178 I40E_INSET_DMAC | I40E_INSET_SMAC |
7179 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7180 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7181 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7182 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7183 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7184 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7185 I40E_INSET_FLEX_PAYLOAD,
7187 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7188 I40E_INSET_DMAC | I40E_INSET_SMAC |
7189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7190 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7191 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7192 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7193 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7194 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7195 I40E_INSET_FLEX_PAYLOAD,
7197 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7198 I40E_INSET_DMAC | I40E_INSET_SMAC |
7199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7200 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7201 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7202 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7203 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7204 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7205 I40E_INSET_FLEX_PAYLOAD,
7206 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7207 I40E_INSET_DMAC | I40E_INSET_SMAC |
7208 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7209 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7210 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7211 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7212 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7213 I40E_INSET_FLEX_PAYLOAD,
7214 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7215 I40E_INSET_DMAC | I40E_INSET_SMAC |
7216 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7217 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7218 I40E_INSET_FLEX_PAYLOAD,
7222 * Flow director supports only fields defined in
7223 * union rte_eth_fdir_flow.
7225 static const uint64_t valid_fdir_inset_table[] = {
7226 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7227 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7228 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7229 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7230 I40E_INSET_IPV4_TTL,
7231 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7232 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7233 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7234 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7235 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7237 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7238 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7239 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7240 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7241 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7242 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7243 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7244 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7245 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7246 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7248 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7249 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7250 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7251 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7252 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7254 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7255 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7256 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7257 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7258 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7260 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7261 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7262 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7263 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7264 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7266 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7267 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7268 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7269 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7270 I40E_INSET_IPV4_TTL,
7271 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7272 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7273 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7274 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7275 I40E_INSET_IPV6_HOP_LIMIT,
7276 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7277 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7278 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7279 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7280 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7282 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7283 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7284 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7285 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7286 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7287 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7288 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7289 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7290 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7291 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7293 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7294 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7295 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7296 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7297 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7299 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7300 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7301 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7302 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7303 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7305 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7306 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7307 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7308 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7309 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7311 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7312 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7314 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7315 I40E_INSET_IPV6_HOP_LIMIT,
7316 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7317 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7318 I40E_INSET_LAST_ETHER_TYPE,
7321 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7323 if (filter == RTE_ETH_FILTER_HASH)
7324 valid = valid_hash_inset_table[pctype];
7326 valid = valid_fdir_inset_table[pctype];
7332 * Validate if the input set is allowed for a specific PCTYPE
7335 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7336 enum rte_filter_type filter, uint64_t inset)
7340 valid = i40e_get_valid_input_set(pctype, filter);
7341 if (inset & (~valid))
7347 /* default input set fields combination per pctype */
7349 i40e_get_default_input_set(uint16_t pctype)
7351 static const uint64_t default_inset_table[] = {
7352 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7353 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7354 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7355 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7356 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7358 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7359 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7360 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7361 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7362 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7363 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7365 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7366 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7367 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7369 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7370 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7371 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7373 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7374 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7375 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7377 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7378 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7379 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7380 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7381 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7382 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7383 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7385 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7386 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7387 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7388 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7389 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7390 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7392 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7393 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7394 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7396 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7397 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7398 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7400 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7401 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7402 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7404 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7405 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7406 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7407 I40E_INSET_LAST_ETHER_TYPE,
7410 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7413 return default_inset_table[pctype];
7417 * Parse the input set from index to logical bit masks
7420 i40e_parse_input_set(uint64_t *inset,
7421 enum i40e_filter_pctype pctype,
7422 enum rte_eth_input_set_field *field,
7428 static const struct {
7429 enum rte_eth_input_set_field field;
7431 } inset_convert_table[] = {
7432 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7433 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7434 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7435 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7436 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7437 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7438 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7439 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7440 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7441 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7442 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7443 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7444 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7445 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7446 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7447 I40E_INSET_IPV6_NEXT_HDR},
7448 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7449 I40E_INSET_IPV6_HOP_LIMIT},
7450 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7451 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7452 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7453 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7454 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7455 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7456 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7457 I40E_INSET_SCTP_VT},
7458 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7459 I40E_INSET_TUNNEL_DMAC},
7460 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7461 I40E_INSET_VLAN_TUNNEL},
7462 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7463 I40E_INSET_TUNNEL_ID},
7464 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7465 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7466 I40E_INSET_FLEX_PAYLOAD_W1},
7467 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7468 I40E_INSET_FLEX_PAYLOAD_W2},
7469 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7470 I40E_INSET_FLEX_PAYLOAD_W3},
7471 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7472 I40E_INSET_FLEX_PAYLOAD_W4},
7473 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7474 I40E_INSET_FLEX_PAYLOAD_W5},
7475 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7476 I40E_INSET_FLEX_PAYLOAD_W6},
7477 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7478 I40E_INSET_FLEX_PAYLOAD_W7},
7479 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7480 I40E_INSET_FLEX_PAYLOAD_W8},
7483 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7486 /* Only one item allowed for default or all */
7488 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7489 *inset = i40e_get_default_input_set(pctype);
7491 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7492 *inset = I40E_INSET_NONE;
7497 for (i = 0, *inset = 0; i < size; i++) {
7498 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7499 if (field[i] == inset_convert_table[j].field) {
7500 *inset |= inset_convert_table[j].inset;
7505 /* It contains unsupported input set, return immediately */
7506 if (j == RTE_DIM(inset_convert_table))
7514 * Translate the input set from bit masks to register aware bit masks
7518 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7528 static const struct inset_map inset_map_common[] = {
7529 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7530 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7531 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7532 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7533 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7534 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7535 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7536 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7537 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7538 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7539 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7540 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7541 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7542 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7543 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7544 {I40E_INSET_TUNNEL_DMAC,
7545 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7546 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7547 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7548 {I40E_INSET_TUNNEL_SRC_PORT,
7549 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7550 {I40E_INSET_TUNNEL_DST_PORT,
7551 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7552 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7553 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7554 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7555 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7556 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7557 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7558 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7559 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7560 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7563 /* some different registers map in x722*/
7564 static const struct inset_map inset_map_diff_x722[] = {
7565 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7566 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7567 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7568 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7571 static const struct inset_map inset_map_diff_not_x722[] = {
7572 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7573 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7574 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7575 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7581 /* Translate input set to register aware inset */
7582 if (type == I40E_MAC_X722) {
7583 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7584 if (input & inset_map_diff_x722[i].inset)
7585 val |= inset_map_diff_x722[i].inset_reg;
7588 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7589 if (input & inset_map_diff_not_x722[i].inset)
7590 val |= inset_map_diff_not_x722[i].inset_reg;
7594 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7595 if (input & inset_map_common[i].inset)
7596 val |= inset_map_common[i].inset_reg;
7603 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7606 uint64_t inset_need_mask = inset;
7608 static const struct {
7611 } inset_mask_map[] = {
7612 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7613 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7614 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7615 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7616 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7617 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7618 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7619 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7622 if (!inset || !mask || !nb_elem)
7625 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7626 /* Clear the inset bit, if no MASK is required,
7627 * for example proto + ttl
7629 if ((inset & inset_mask_map[i].inset) ==
7630 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7631 inset_need_mask &= ~inset_mask_map[i].inset;
7632 if (!inset_need_mask)
7635 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7636 if ((inset_need_mask & inset_mask_map[i].inset) ==
7637 inset_mask_map[i].inset) {
7638 if (idx >= nb_elem) {
7639 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7642 mask[idx] = inset_mask_map[i].mask;
7651 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7653 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7655 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7657 i40e_write_rx_ctl(hw, addr, val);
7658 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7659 (uint32_t)i40e_read_rx_ctl(hw, addr));
7663 i40e_filter_input_set_init(struct i40e_pf *pf)
7665 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7666 enum i40e_filter_pctype pctype;
7667 uint64_t input_set, inset_reg;
7668 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7671 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7672 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7673 if (hw->mac.type == I40E_MAC_X722) {
7674 if (!I40E_VALID_PCTYPE_X722(pctype))
7677 if (!I40E_VALID_PCTYPE(pctype))
7681 input_set = i40e_get_default_input_set(pctype);
7683 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7684 I40E_INSET_MASK_NUM_REG);
7687 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7690 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7691 (uint32_t)(inset_reg & UINT32_MAX));
7692 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7693 (uint32_t)((inset_reg >>
7694 I40E_32_BIT_WIDTH) & UINT32_MAX));
7695 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7696 (uint32_t)(inset_reg & UINT32_MAX));
7697 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7698 (uint32_t)((inset_reg >>
7699 I40E_32_BIT_WIDTH) & UINT32_MAX));
7701 for (i = 0; i < num; i++) {
7702 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7704 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7707 /*clear unused mask registers of the pctype */
7708 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7709 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7711 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7714 I40E_WRITE_FLUSH(hw);
7716 /* store the default input set */
7717 pf->hash_input_set[pctype] = input_set;
7718 pf->fdir.input_set[pctype] = input_set;
7723 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7724 struct rte_eth_input_set_conf *conf)
7726 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7727 enum i40e_filter_pctype pctype;
7728 uint64_t input_set, inset_reg = 0;
7729 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7733 PMD_DRV_LOG(ERR, "Invalid pointer");
7736 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7737 conf->op != RTE_ETH_INPUT_SET_ADD) {
7738 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7742 if (!I40E_VALID_FLOW(conf->flow_type)) {
7743 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7747 if (hw->mac.type == I40E_MAC_X722) {
7748 /* get translated pctype value in fd pctype register */
7749 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7750 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7753 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7755 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7758 PMD_DRV_LOG(ERR, "Failed to parse input set");
7761 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7763 PMD_DRV_LOG(ERR, "Invalid input set");
7766 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7767 /* get inset value in register */
7768 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7769 inset_reg <<= I40E_32_BIT_WIDTH;
7770 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7771 input_set |= pf->hash_input_set[pctype];
7773 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7774 I40E_INSET_MASK_NUM_REG);
7778 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7780 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7781 (uint32_t)(inset_reg & UINT32_MAX));
7782 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7783 (uint32_t)((inset_reg >>
7784 I40E_32_BIT_WIDTH) & UINT32_MAX));
7786 for (i = 0; i < num; i++)
7787 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7789 /*clear unused mask registers of the pctype */
7790 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7791 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7793 I40E_WRITE_FLUSH(hw);
7795 pf->hash_input_set[pctype] = input_set;
7800 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7801 struct rte_eth_input_set_conf *conf)
7803 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7804 enum i40e_filter_pctype pctype;
7805 uint64_t input_set, inset_reg = 0;
7806 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7810 PMD_DRV_LOG(ERR, "Invalid pointer");
7813 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7814 conf->op != RTE_ETH_INPUT_SET_ADD) {
7815 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7819 if (!I40E_VALID_FLOW(conf->flow_type)) {
7820 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7824 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7826 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7829 PMD_DRV_LOG(ERR, "Failed to parse input set");
7832 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7834 PMD_DRV_LOG(ERR, "Invalid input set");
7838 /* get inset value in register */
7839 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7840 inset_reg <<= I40E_32_BIT_WIDTH;
7841 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7843 /* Can not change the inset reg for flex payload for fdir,
7844 * it is done by writing I40E_PRTQF_FD_FLXINSET
7845 * in i40e_set_flex_mask_on_pctype.
7847 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7848 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7850 input_set |= pf->fdir.input_set[pctype];
7851 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7852 I40E_INSET_MASK_NUM_REG);
7856 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7858 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7859 (uint32_t)(inset_reg & UINT32_MAX));
7860 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7861 (uint32_t)((inset_reg >>
7862 I40E_32_BIT_WIDTH) & UINT32_MAX));
7864 for (i = 0; i < num; i++)
7865 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7867 /*clear unused mask registers of the pctype */
7868 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7869 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7871 I40E_WRITE_FLUSH(hw);
7873 pf->fdir.input_set[pctype] = input_set;
7878 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7883 PMD_DRV_LOG(ERR, "Invalid pointer");
7887 switch (info->info_type) {
7888 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7889 i40e_get_symmetric_hash_enable_per_port(hw,
7890 &(info->info.enable));
7892 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7893 ret = i40e_get_hash_filter_global_config(hw,
7894 &(info->info.global_conf));
7897 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7907 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7912 PMD_DRV_LOG(ERR, "Invalid pointer");
7916 switch (info->info_type) {
7917 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7918 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7920 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7921 ret = i40e_set_hash_filter_global_config(hw,
7922 &(info->info.global_conf));
7924 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7925 ret = i40e_hash_filter_inset_select(hw,
7926 &(info->info.input_set_conf));
7930 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7939 /* Operations for hash function */
7941 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7942 enum rte_filter_op filter_op,
7945 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7948 switch (filter_op) {
7949 case RTE_ETH_FILTER_NOP:
7951 case RTE_ETH_FILTER_GET:
7952 ret = i40e_hash_filter_get(hw,
7953 (struct rte_eth_hash_filter_info *)arg);
7955 case RTE_ETH_FILTER_SET:
7956 ret = i40e_hash_filter_set(hw,
7957 (struct rte_eth_hash_filter_info *)arg);
7960 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7970 * Configure ethertype filter, which can director packet by filtering
7971 * with mac address and ether_type or only ether_type
7974 i40e_ethertype_filter_set(struct i40e_pf *pf,
7975 struct rte_eth_ethertype_filter *filter,
7978 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7979 struct i40e_control_filter_stats stats;
7983 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7984 PMD_DRV_LOG(ERR, "Invalid queue ID");
7987 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7988 filter->ether_type == ETHER_TYPE_IPv6) {
7989 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7990 " control packet filter.", filter->ether_type);
7993 if (filter->ether_type == ETHER_TYPE_VLAN)
7994 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7997 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7998 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7999 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8000 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8001 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8003 memset(&stats, 0, sizeof(stats));
8004 ret = i40e_aq_add_rem_control_packet_filter(hw,
8005 filter->mac_addr.addr_bytes,
8006 filter->ether_type, flags,
8008 filter->queue, add, &stats, NULL);
8010 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8011 " mac_etype_used = %u, etype_used = %u,"
8012 " mac_etype_free = %u, etype_free = %u\n",
8013 ret, stats.mac_etype_used, stats.etype_used,
8014 stats.mac_etype_free, stats.etype_free);
8021 * Handle operations for ethertype filter.
8024 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8025 enum rte_filter_op filter_op,
8028 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8031 if (filter_op == RTE_ETH_FILTER_NOP)
8035 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8040 switch (filter_op) {
8041 case RTE_ETH_FILTER_ADD:
8042 ret = i40e_ethertype_filter_set(pf,
8043 (struct rte_eth_ethertype_filter *)arg,
8046 case RTE_ETH_FILTER_DELETE:
8047 ret = i40e_ethertype_filter_set(pf,
8048 (struct rte_eth_ethertype_filter *)arg,
8052 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8060 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8061 enum rte_filter_type filter_type,
8062 enum rte_filter_op filter_op,
8070 switch (filter_type) {
8071 case RTE_ETH_FILTER_NONE:
8072 /* For global configuration */
8073 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8075 case RTE_ETH_FILTER_HASH:
8076 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8078 case RTE_ETH_FILTER_MACVLAN:
8079 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8081 case RTE_ETH_FILTER_ETHERTYPE:
8082 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8084 case RTE_ETH_FILTER_TUNNEL:
8085 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8087 case RTE_ETH_FILTER_FDIR:
8088 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8091 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8101 * Check and enable Extended Tag.
8102 * Enabling Extended Tag is important for 40G performance.
8105 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8110 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8113 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8117 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8118 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8123 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8126 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8130 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8131 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8134 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8135 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8138 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8145 * As some registers wouldn't be reset unless a global hardware reset,
8146 * hardware initialization is needed to put those registers into an
8147 * expected initial state.
8150 i40e_hw_init(struct rte_eth_dev *dev)
8152 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8154 i40e_enable_extended_tag(dev);
8156 /* clear the PF Queue Filter control register */
8157 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8159 /* Disable symmetric hash per port */
8160 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8163 enum i40e_filter_pctype
8164 i40e_flowtype_to_pctype(uint16_t flow_type)
8166 static const enum i40e_filter_pctype pctype_table[] = {
8167 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8168 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8169 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8170 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8171 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8172 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8173 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8174 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8175 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8176 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8177 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8178 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8179 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8180 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8181 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8182 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8183 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8184 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8185 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8188 return pctype_table[flow_type];
8192 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8194 static const uint16_t flowtype_table[] = {
8195 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8196 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8197 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8199 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8200 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8201 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8202 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8204 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8205 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8207 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8208 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8210 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8211 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8212 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8213 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8214 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8215 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8216 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8218 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8219 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8220 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8221 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8223 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8224 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8226 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8227 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8229 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8230 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8231 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8232 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8233 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8236 return flowtype_table[pctype];
8240 * On X710, performance number is far from the expectation on recent firmware
8241 * versions; on XL710, performance number is also far from the expectation on
8242 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8243 * mode is enabled and port MAC address is equal to the packet destination MAC
8244 * address. The fix for this issue may not be integrated in the following
8245 * firmware version. So the workaround in software driver is needed. It needs
8246 * to modify the initial values of 3 internal only registers for both X710 and
8247 * XL710. Note that the values for X710 or XL710 could be different, and the
8248 * workaround can be removed when it is fixed in firmware in the future.
8251 /* For both X710 and XL710 */
8252 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8253 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8255 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8256 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8259 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8261 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8262 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8265 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8267 enum i40e_status_code status;
8268 struct i40e_aq_get_phy_abilities_resp phy_ab;
8271 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8282 i40e_configure_registers(struct i40e_hw *hw)
8288 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8289 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8290 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8296 for (i = 0; i < RTE_DIM(reg_table); i++) {
8297 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8298 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8299 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8301 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8304 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8307 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8310 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8314 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8315 reg_table[i].addr, reg);
8316 if (reg == reg_table[i].val)
8319 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8320 reg_table[i].val, NULL);
8322 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8323 "address of 0x%"PRIx32, reg_table[i].val,
8327 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8328 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8332 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8333 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8334 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8335 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8337 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8342 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8343 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8347 /* Configure for double VLAN RX stripping */
8348 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8349 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8350 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8351 ret = i40e_aq_debug_write_register(hw,
8352 I40E_VSI_TSR(vsi->vsi_id),
8355 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8357 return I40E_ERR_CONFIG;
8361 /* Configure for double VLAN TX insertion */
8362 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8363 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8364 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8365 ret = i40e_aq_debug_write_register(hw,
8366 I40E_VSI_L2TAGSTXVALID(
8367 vsi->vsi_id), reg, NULL);
8369 PMD_DRV_LOG(ERR, "Failed to update "
8370 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8371 return I40E_ERR_CONFIG;
8379 * i40e_aq_add_mirror_rule
8380 * @hw: pointer to the hardware structure
8381 * @seid: VEB seid to add mirror rule to
8382 * @dst_id: destination vsi seid
8383 * @entries: Buffer which contains the entities to be mirrored
8384 * @count: number of entities contained in the buffer
8385 * @rule_id:the rule_id of the rule to be added
8387 * Add a mirror rule for a given veb.
8390 static enum i40e_status_code
8391 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8392 uint16_t seid, uint16_t dst_id,
8393 uint16_t rule_type, uint16_t *entries,
8394 uint16_t count, uint16_t *rule_id)
8396 struct i40e_aq_desc desc;
8397 struct i40e_aqc_add_delete_mirror_rule cmd;
8398 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8399 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8402 enum i40e_status_code status;
8404 i40e_fill_default_direct_cmd_desc(&desc,
8405 i40e_aqc_opc_add_mirror_rule);
8406 memset(&cmd, 0, sizeof(cmd));
8408 buff_len = sizeof(uint16_t) * count;
8409 desc.datalen = rte_cpu_to_le_16(buff_len);
8411 desc.flags |= rte_cpu_to_le_16(
8412 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8413 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8414 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8415 cmd.num_entries = rte_cpu_to_le_16(count);
8416 cmd.seid = rte_cpu_to_le_16(seid);
8417 cmd.destination = rte_cpu_to_le_16(dst_id);
8419 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8420 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8421 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8423 " mirror_rules_used = %u, mirror_rules_free = %u,",
8424 hw->aq.asq_last_status, resp->rule_id,
8425 resp->mirror_rules_used, resp->mirror_rules_free);
8426 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8432 * i40e_aq_del_mirror_rule
8433 * @hw: pointer to the hardware structure
8434 * @seid: VEB seid to add mirror rule to
8435 * @entries: Buffer which contains the entities to be mirrored
8436 * @count: number of entities contained in the buffer
8437 * @rule_id:the rule_id of the rule to be delete
8439 * Delete a mirror rule for a given veb.
8442 static enum i40e_status_code
8443 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8444 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8445 uint16_t count, uint16_t rule_id)
8447 struct i40e_aq_desc desc;
8448 struct i40e_aqc_add_delete_mirror_rule cmd;
8449 uint16_t buff_len = 0;
8450 enum i40e_status_code status;
8453 i40e_fill_default_direct_cmd_desc(&desc,
8454 i40e_aqc_opc_delete_mirror_rule);
8455 memset(&cmd, 0, sizeof(cmd));
8456 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8457 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8459 cmd.num_entries = count;
8460 buff_len = sizeof(uint16_t) * count;
8461 desc.datalen = rte_cpu_to_le_16(buff_len);
8462 buff = (void *)entries;
8464 /* rule id is filled in destination field for deleting mirror rule */
8465 cmd.destination = rte_cpu_to_le_16(rule_id);
8467 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8468 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8469 cmd.seid = rte_cpu_to_le_16(seid);
8471 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8472 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8478 * i40e_mirror_rule_set
8479 * @dev: pointer to the hardware structure
8480 * @mirror_conf: mirror rule info
8481 * @sw_id: mirror rule's sw_id
8482 * @on: enable/disable
8484 * set a mirror rule.
8488 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8489 struct rte_eth_mirror_conf *mirror_conf,
8490 uint8_t sw_id, uint8_t on)
8492 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8493 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8494 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8495 struct i40e_mirror_rule *parent = NULL;
8496 uint16_t seid, dst_seid, rule_id;
8500 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8502 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8503 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8504 " without veb or vfs.");
8507 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8508 PMD_DRV_LOG(ERR, "mirror table is full.");
8511 if (mirror_conf->dst_pool > pf->vf_num) {
8512 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8513 mirror_conf->dst_pool);
8517 seid = pf->main_vsi->veb->seid;
8519 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8520 if (sw_id <= it->index) {
8526 if (mirr_rule && sw_id == mirr_rule->index) {
8528 PMD_DRV_LOG(ERR, "mirror rule exists.");
8531 ret = i40e_aq_del_mirror_rule(hw, seid,
8532 mirr_rule->rule_type,
8534 mirr_rule->num_entries, mirr_rule->id);
8536 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8537 " ret = %d, aq_err = %d.",
8538 ret, hw->aq.asq_last_status);
8541 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8542 rte_free(mirr_rule);
8543 pf->nb_mirror_rule--;
8547 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8551 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8552 sizeof(struct i40e_mirror_rule) , 0);
8554 PMD_DRV_LOG(ERR, "failed to allocate memory");
8555 return I40E_ERR_NO_MEMORY;
8557 switch (mirror_conf->rule_type) {
8558 case ETH_MIRROR_VLAN:
8559 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8560 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8561 mirr_rule->entries[j] =
8562 mirror_conf->vlan.vlan_id[i];
8567 PMD_DRV_LOG(ERR, "vlan is not specified.");
8568 rte_free(mirr_rule);
8571 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8573 case ETH_MIRROR_VIRTUAL_POOL_UP:
8574 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8575 /* check if the specified pool bit is out of range */
8576 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8577 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8578 rte_free(mirr_rule);
8581 for (i = 0, j = 0; i < pf->vf_num; i++) {
8582 if (mirror_conf->pool_mask & (1ULL << i)) {
8583 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8587 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8588 /* add pf vsi to entries */
8589 mirr_rule->entries[j] = pf->main_vsi_seid;
8593 PMD_DRV_LOG(ERR, "pool is not specified.");
8594 rte_free(mirr_rule);
8597 /* egress and ingress in aq commands means from switch but not port */
8598 mirr_rule->rule_type =
8599 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8600 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8601 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8603 case ETH_MIRROR_UPLINK_PORT:
8604 /* egress and ingress in aq commands means from switch but not port*/
8605 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8607 case ETH_MIRROR_DOWNLINK_PORT:
8608 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8611 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8612 mirror_conf->rule_type);
8613 rte_free(mirr_rule);
8617 /* If the dst_pool is equal to vf_num, consider it as PF */
8618 if (mirror_conf->dst_pool == pf->vf_num)
8619 dst_seid = pf->main_vsi_seid;
8621 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8623 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8624 mirr_rule->rule_type, mirr_rule->entries,
8627 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8628 " ret = %d, aq_err = %d.",
8629 ret, hw->aq.asq_last_status);
8630 rte_free(mirr_rule);
8634 mirr_rule->index = sw_id;
8635 mirr_rule->num_entries = j;
8636 mirr_rule->id = rule_id;
8637 mirr_rule->dst_vsi_seid = dst_seid;
8640 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8642 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8644 pf->nb_mirror_rule++;
8649 * i40e_mirror_rule_reset
8650 * @dev: pointer to the device
8651 * @sw_id: mirror rule's sw_id
8653 * reset a mirror rule.
8657 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8659 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8661 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8665 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8667 seid = pf->main_vsi->veb->seid;
8669 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8670 if (sw_id == it->index) {
8676 ret = i40e_aq_del_mirror_rule(hw, seid,
8677 mirr_rule->rule_type,
8679 mirr_rule->num_entries, mirr_rule->id);
8681 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8682 " status = %d, aq_err = %d.",
8683 ret, hw->aq.asq_last_status);
8686 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8687 rte_free(mirr_rule);
8688 pf->nb_mirror_rule--;
8690 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8697 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8699 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8700 uint64_t systim_cycles;
8702 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8703 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8706 return systim_cycles;
8710 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8715 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8716 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8723 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8725 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8728 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8729 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8736 i40e_start_timecounters(struct rte_eth_dev *dev)
8738 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8739 struct i40e_adapter *adapter =
8740 (struct i40e_adapter *)dev->data->dev_private;
8741 struct rte_eth_link link;
8742 uint32_t tsync_inc_l;
8743 uint32_t tsync_inc_h;
8745 /* Get current link speed. */
8746 memset(&link, 0, sizeof(link));
8747 i40e_dev_link_update(dev, 1);
8748 rte_i40e_dev_atomic_read_link_status(dev, &link);
8750 switch (link.link_speed) {
8751 case ETH_SPEED_NUM_40G:
8752 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8753 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8755 case ETH_SPEED_NUM_10G:
8756 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8757 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8759 case ETH_SPEED_NUM_1G:
8760 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8761 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8768 /* Set the timesync increment value. */
8769 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8770 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8772 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8773 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8774 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8776 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8777 adapter->systime_tc.cc_shift = 0;
8778 adapter->systime_tc.nsec_mask = 0;
8780 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8781 adapter->rx_tstamp_tc.cc_shift = 0;
8782 adapter->rx_tstamp_tc.nsec_mask = 0;
8784 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8785 adapter->tx_tstamp_tc.cc_shift = 0;
8786 adapter->tx_tstamp_tc.nsec_mask = 0;
8790 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8792 struct i40e_adapter *adapter =
8793 (struct i40e_adapter *)dev->data->dev_private;
8795 adapter->systime_tc.nsec += delta;
8796 adapter->rx_tstamp_tc.nsec += delta;
8797 adapter->tx_tstamp_tc.nsec += delta;
8803 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8806 struct i40e_adapter *adapter =
8807 (struct i40e_adapter *)dev->data->dev_private;
8809 ns = rte_timespec_to_ns(ts);
8811 /* Set the timecounters to a new value. */
8812 adapter->systime_tc.nsec = ns;
8813 adapter->rx_tstamp_tc.nsec = ns;
8814 adapter->tx_tstamp_tc.nsec = ns;
8820 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8822 uint64_t ns, systime_cycles;
8823 struct i40e_adapter *adapter =
8824 (struct i40e_adapter *)dev->data->dev_private;
8826 systime_cycles = i40e_read_systime_cyclecounter(dev);
8827 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8828 *ts = rte_ns_to_timespec(ns);
8834 i40e_timesync_enable(struct rte_eth_dev *dev)
8836 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8837 uint32_t tsync_ctl_l;
8838 uint32_t tsync_ctl_h;
8840 /* Stop the timesync system time. */
8841 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8842 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8843 /* Reset the timesync system time value. */
8844 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8845 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8847 i40e_start_timecounters(dev);
8849 /* Clear timesync registers. */
8850 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8851 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8852 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8853 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8854 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8855 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8857 /* Enable timestamping of PTP packets. */
8858 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8859 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8861 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8862 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8863 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8865 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8866 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8872 i40e_timesync_disable(struct rte_eth_dev *dev)
8874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8875 uint32_t tsync_ctl_l;
8876 uint32_t tsync_ctl_h;
8878 /* Disable timestamping of transmitted PTP packets. */
8879 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8880 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8882 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8883 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8885 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8886 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8888 /* Reset the timesync increment value. */
8889 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8890 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8896 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8897 struct timespec *timestamp, uint32_t flags)
8899 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8900 struct i40e_adapter *adapter =
8901 (struct i40e_adapter *)dev->data->dev_private;
8903 uint32_t sync_status;
8904 uint32_t index = flags & 0x03;
8905 uint64_t rx_tstamp_cycles;
8908 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8909 if ((sync_status & (1 << index)) == 0)
8912 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8913 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8914 *timestamp = rte_ns_to_timespec(ns);
8920 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8921 struct timespec *timestamp)
8923 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8924 struct i40e_adapter *adapter =
8925 (struct i40e_adapter *)dev->data->dev_private;
8927 uint32_t sync_status;
8928 uint64_t tx_tstamp_cycles;
8931 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8932 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8935 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8936 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8937 *timestamp = rte_ns_to_timespec(ns);
8943 * i40e_parse_dcb_configure - parse dcb configure from user
8944 * @dev: the device being configured
8945 * @dcb_cfg: pointer of the result of parse
8946 * @*tc_map: bit map of enabled traffic classes
8948 * Returns 0 on success, negative value on failure
8951 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8952 struct i40e_dcbx_config *dcb_cfg,
8955 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8956 uint8_t i, tc_bw, bw_lf;
8958 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8960 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8961 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8962 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8966 /* assume each tc has the same bw */
8967 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8968 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8969 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8970 /* to ensure the sum of tcbw is equal to 100 */
8971 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8972 for (i = 0; i < bw_lf; i++)
8973 dcb_cfg->etscfg.tcbwtable[i]++;
8975 /* assume each tc has the same Transmission Selection Algorithm */
8976 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8977 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8979 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8980 dcb_cfg->etscfg.prioritytable[i] =
8981 dcb_rx_conf->dcb_tc[i];
8983 /* FW needs one App to configure HW */
8984 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8985 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8986 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8987 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8989 if (dcb_rx_conf->nb_tcs == 0)
8990 *tc_map = 1; /* tc0 only */
8992 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8994 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8995 dcb_cfg->pfc.willing = 0;
8996 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8997 dcb_cfg->pfc.pfcenable = *tc_map;
9003 static enum i40e_status_code
9004 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9005 struct i40e_aqc_vsi_properties_data *info,
9006 uint8_t enabled_tcmap)
9008 enum i40e_status_code ret;
9009 int i, total_tc = 0;
9010 uint16_t qpnum_per_tc, bsf, qp_idx;
9011 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9012 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9013 uint16_t used_queues;
9015 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9016 if (ret != I40E_SUCCESS)
9019 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9020 if (enabled_tcmap & (1 << i))
9025 vsi->enabled_tc = enabled_tcmap;
9027 /* different VSI has different queues assigned */
9028 if (vsi->type == I40E_VSI_MAIN)
9029 used_queues = dev_data->nb_rx_queues -
9030 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9031 else if (vsi->type == I40E_VSI_VMDQ2)
9032 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9034 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9035 return I40E_ERR_NO_AVAILABLE_VSI;
9038 qpnum_per_tc = used_queues / total_tc;
9039 /* Number of queues per enabled TC */
9040 if (qpnum_per_tc == 0) {
9041 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9042 return I40E_ERR_INVALID_QP_ID;
9044 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9046 bsf = rte_bsf32(qpnum_per_tc);
9049 * Configure TC and queue mapping parameters, for enabled TC,
9050 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9051 * default queue will serve it.
9054 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9055 if (vsi->enabled_tc & (1 << i)) {
9056 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9057 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9058 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9059 qp_idx += qpnum_per_tc;
9061 info->tc_mapping[i] = 0;
9064 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9065 if (vsi->type == I40E_VSI_SRIOV) {
9066 info->mapping_flags |=
9067 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9068 for (i = 0; i < vsi->nb_qps; i++)
9069 info->queue_mapping[i] =
9070 rte_cpu_to_le_16(vsi->base_queue + i);
9072 info->mapping_flags |=
9073 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9074 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9076 info->valid_sections |=
9077 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9079 return I40E_SUCCESS;
9083 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9084 * @veb: VEB to be configured
9085 * @tc_map: enabled TC bitmap
9087 * Returns 0 on success, negative value on failure
9089 static enum i40e_status_code
9090 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9092 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9093 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9094 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9095 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9096 enum i40e_status_code ret = I40E_SUCCESS;
9100 /* Check if enabled_tc is same as existing or new TCs */
9101 if (veb->enabled_tc == tc_map)
9104 /* configure tc bandwidth */
9105 memset(&veb_bw, 0, sizeof(veb_bw));
9106 veb_bw.tc_valid_bits = tc_map;
9107 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9108 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9109 if (tc_map & BIT_ULL(i))
9110 veb_bw.tc_bw_share_credits[i] = 1;
9112 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9115 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9116 " per TC failed = %d",
9117 hw->aq.asq_last_status);
9121 memset(&ets_query, 0, sizeof(ets_query));
9122 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9124 if (ret != I40E_SUCCESS) {
9125 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9126 " configuration %u", hw->aq.asq_last_status);
9129 memset(&bw_query, 0, sizeof(bw_query));
9130 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9132 if (ret != I40E_SUCCESS) {
9133 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9134 " configuration %u", hw->aq.asq_last_status);
9138 /* store and print out BW info */
9139 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9140 veb->bw_info.bw_max = ets_query.tc_bw_max;
9141 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9142 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9143 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9144 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9146 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9147 veb->bw_info.bw_ets_share_credits[i] =
9148 bw_query.tc_bw_share_credits[i];
9149 veb->bw_info.bw_ets_credits[i] =
9150 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9151 /* 4 bits per TC, 4th bit is reserved */
9152 veb->bw_info.bw_ets_max[i] =
9153 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9154 RTE_LEN2MASK(3, uint8_t));
9155 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9156 veb->bw_info.bw_ets_share_credits[i]);
9157 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9158 veb->bw_info.bw_ets_credits[i]);
9159 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9160 veb->bw_info.bw_ets_max[i]);
9163 veb->enabled_tc = tc_map;
9170 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9171 * @vsi: VSI to be configured
9172 * @tc_map: enabled TC bitmap
9174 * Returns 0 on success, negative value on failure
9176 static enum i40e_status_code
9177 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9179 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9180 struct i40e_vsi_context ctxt;
9181 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9182 enum i40e_status_code ret = I40E_SUCCESS;
9185 /* Check if enabled_tc is same as existing or new TCs */
9186 if (vsi->enabled_tc == tc_map)
9189 /* configure tc bandwidth */
9190 memset(&bw_data, 0, sizeof(bw_data));
9191 bw_data.tc_valid_bits = tc_map;
9192 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9193 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9194 if (tc_map & BIT_ULL(i))
9195 bw_data.tc_bw_credits[i] = 1;
9197 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9199 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9200 " per TC failed = %d",
9201 hw->aq.asq_last_status);
9204 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9205 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9207 /* Update Queue Pairs Mapping for currently enabled UPs */
9208 ctxt.seid = vsi->seid;
9209 ctxt.pf_num = hw->pf_id;
9211 ctxt.uplink_seid = vsi->uplink_seid;
9212 ctxt.info = vsi->info;
9214 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9218 /* Update the VSI after updating the VSI queue-mapping information */
9219 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9221 PMD_INIT_LOG(ERR, "Failed to configure "
9222 "TC queue mapping = %d",
9223 hw->aq.asq_last_status);
9226 /* update the local VSI info with updated queue map */
9227 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9228 sizeof(vsi->info.tc_mapping));
9229 (void)rte_memcpy(&vsi->info.queue_mapping,
9230 &ctxt.info.queue_mapping,
9231 sizeof(vsi->info.queue_mapping));
9232 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9233 vsi->info.valid_sections = 0;
9235 /* query and update current VSI BW information */
9236 ret = i40e_vsi_get_bw_config(vsi);
9239 "Failed updating vsi bw info, err %s aq_err %s",
9240 i40e_stat_str(hw, ret),
9241 i40e_aq_str(hw, hw->aq.asq_last_status));
9245 vsi->enabled_tc = tc_map;
9252 * i40e_dcb_hw_configure - program the dcb setting to hw
9253 * @pf: pf the configuration is taken on
9254 * @new_cfg: new configuration
9255 * @tc_map: enabled TC bitmap
9257 * Returns 0 on success, negative value on failure
9259 static enum i40e_status_code
9260 i40e_dcb_hw_configure(struct i40e_pf *pf,
9261 struct i40e_dcbx_config *new_cfg,
9264 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9265 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9266 struct i40e_vsi *main_vsi = pf->main_vsi;
9267 struct i40e_vsi_list *vsi_list;
9268 enum i40e_status_code ret;
9272 /* Use the FW API if FW > v4.4*/
9273 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9274 (hw->aq.fw_maj_ver >= 5))) {
9275 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9276 " to configure DCB");
9277 return I40E_ERR_FIRMWARE_API_VERSION;
9280 /* Check if need reconfiguration */
9281 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9282 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9283 return I40E_SUCCESS;
9286 /* Copy the new config to the current config */
9287 *old_cfg = *new_cfg;
9288 old_cfg->etsrec = old_cfg->etscfg;
9289 ret = i40e_set_dcb_config(hw);
9292 "Set DCB Config failed, err %s aq_err %s\n",
9293 i40e_stat_str(hw, ret),
9294 i40e_aq_str(hw, hw->aq.asq_last_status));
9297 /* set receive Arbiter to RR mode and ETS scheme by default */
9298 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9299 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9300 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9301 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9302 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9303 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9304 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9305 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9306 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9307 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9308 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9309 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9310 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9312 /* get local mib to check whether it is configured correctly */
9314 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9315 /* Get Local DCB Config */
9316 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9317 &hw->local_dcbx_config);
9319 /* if Veb is created, need to update TC of it at first */
9320 if (main_vsi->veb) {
9321 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9323 PMD_INIT_LOG(WARNING,
9324 "Failed configuring TC for VEB seid=%d\n",
9325 main_vsi->veb->seid);
9327 /* Update each VSI */
9328 i40e_vsi_config_tc(main_vsi, tc_map);
9329 if (main_vsi->veb) {
9330 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9331 /* Beside main VSI and VMDQ VSIs, only enable default
9334 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9335 ret = i40e_vsi_config_tc(vsi_list->vsi,
9338 ret = i40e_vsi_config_tc(vsi_list->vsi,
9339 I40E_DEFAULT_TCMAP);
9341 PMD_INIT_LOG(WARNING,
9342 "Failed configuring TC for VSI seid=%d\n",
9343 vsi_list->vsi->seid);
9347 return I40E_SUCCESS;
9351 * i40e_dcb_init_configure - initial dcb config
9352 * @dev: device being configured
9353 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9355 * Returns 0 on success, negative value on failure
9358 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9360 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9361 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9364 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9365 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9369 /* DCB initialization:
9370 * Update DCB configuration from the Firmware and configure
9371 * LLDP MIB change event.
9373 if (sw_dcb == TRUE) {
9374 ret = i40e_init_dcb(hw);
9375 /* If lldp agent is stopped, the return value from
9376 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9377 * adminq status. Otherwise, it should return success.
9379 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9380 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9381 memset(&hw->local_dcbx_config, 0,
9382 sizeof(struct i40e_dcbx_config));
9383 /* set dcb default configuration */
9384 hw->local_dcbx_config.etscfg.willing = 0;
9385 hw->local_dcbx_config.etscfg.maxtcs = 0;
9386 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9387 hw->local_dcbx_config.etscfg.tsatable[0] =
9389 hw->local_dcbx_config.etsrec =
9390 hw->local_dcbx_config.etscfg;
9391 hw->local_dcbx_config.pfc.willing = 0;
9392 hw->local_dcbx_config.pfc.pfccap =
9393 I40E_MAX_TRAFFIC_CLASS;
9394 /* FW needs one App to configure HW */
9395 hw->local_dcbx_config.numapps = 1;
9396 hw->local_dcbx_config.app[0].selector =
9397 I40E_APP_SEL_ETHTYPE;
9398 hw->local_dcbx_config.app[0].priority = 3;
9399 hw->local_dcbx_config.app[0].protocolid =
9400 I40E_APP_PROTOID_FCOE;
9401 ret = i40e_set_dcb_config(hw);
9403 PMD_INIT_LOG(ERR, "default dcb config fails."
9404 " err = %d, aq_err = %d.", ret,
9405 hw->aq.asq_last_status);
9409 PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9410 " err = %d, aq_err = %d.", ret,
9411 hw->aq.asq_last_status);
9415 ret = i40e_aq_start_lldp(hw, NULL);
9416 if (ret != I40E_SUCCESS)
9417 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9419 ret = i40e_init_dcb(hw);
9421 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9422 PMD_INIT_LOG(ERR, "HW doesn't support"
9427 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9428 " aq_err = %d.", ret,
9429 hw->aq.asq_last_status);
9437 * i40e_dcb_setup - setup dcb related config
9438 * @dev: device being configured
9440 * Returns 0 on success, negative value on failure
9443 i40e_dcb_setup(struct rte_eth_dev *dev)
9445 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9446 struct i40e_dcbx_config dcb_cfg;
9450 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9451 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9455 if (pf->vf_num != 0)
9456 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9458 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9460 PMD_INIT_LOG(ERR, "invalid dcb config");
9463 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9465 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9473 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9474 struct rte_eth_dcb_info *dcb_info)
9476 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9477 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9478 struct i40e_vsi *vsi = pf->main_vsi;
9479 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9480 uint16_t bsf, tc_mapping;
9483 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9484 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9486 dcb_info->nb_tcs = 1;
9487 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9488 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9489 for (i = 0; i < dcb_info->nb_tcs; i++)
9490 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9492 /* get queue mapping if vmdq is disabled */
9493 if (!pf->nb_cfg_vmdq_vsi) {
9494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9495 if (!(vsi->enabled_tc & (1 << i)))
9497 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9498 dcb_info->tc_queue.tc_rxq[j][i].base =
9499 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9500 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9501 dcb_info->tc_queue.tc_txq[j][i].base =
9502 dcb_info->tc_queue.tc_rxq[j][i].base;
9503 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9504 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9505 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9506 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9507 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9512 /* get queue mapping if vmdq is enabled */
9514 vsi = pf->vmdq[j].vsi;
9515 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9516 if (!(vsi->enabled_tc & (1 << i)))
9518 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9519 dcb_info->tc_queue.tc_rxq[j][i].base =
9520 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9521 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9522 dcb_info->tc_queue.tc_txq[j][i].base =
9523 dcb_info->tc_queue.tc_rxq[j][i].base;
9524 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9525 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9526 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9527 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9528 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9531 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9536 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9538 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9539 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9541 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9544 msix_intr = intr_handle->intr_vec[queue_id];
9545 if (msix_intr == I40E_MISC_VEC_ID)
9546 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9547 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9548 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9549 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9551 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9554 I40E_PFINT_DYN_CTLN(msix_intr -
9556 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9557 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9558 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9560 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9562 I40E_WRITE_FLUSH(hw);
9563 rte_intr_enable(&dev->pci_dev->intr_handle);
9569 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9571 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9572 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9575 msix_intr = intr_handle->intr_vec[queue_id];
9576 if (msix_intr == I40E_MISC_VEC_ID)
9577 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9580 I40E_PFINT_DYN_CTLN(msix_intr -
9583 I40E_WRITE_FLUSH(hw);
9588 static int i40e_get_regs(struct rte_eth_dev *dev,
9589 struct rte_dev_reg_info *regs)
9591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9592 uint32_t *ptr_data = regs->data;
9593 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9594 const struct i40e_reg_info *reg_info;
9596 if (ptr_data == NULL) {
9597 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9598 regs->width = sizeof(uint32_t);
9602 /* The first few registers have to be read using AQ operations */
9604 while (i40e_regs_adminq[reg_idx].name) {
9605 reg_info = &i40e_regs_adminq[reg_idx++];
9606 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9608 arr_idx2 <= reg_info->count2;
9610 reg_offset = arr_idx * reg_info->stride1 +
9611 arr_idx2 * reg_info->stride2;
9612 reg_offset += reg_info->base_addr;
9613 ptr_data[reg_offset >> 2] =
9614 i40e_read_rx_ctl(hw, reg_offset);
9618 /* The remaining registers can be read using primitives */
9620 while (i40e_regs_others[reg_idx].name) {
9621 reg_info = &i40e_regs_others[reg_idx++];
9622 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9624 arr_idx2 <= reg_info->count2;
9626 reg_offset = arr_idx * reg_info->stride1 +
9627 arr_idx2 * reg_info->stride2;
9628 reg_offset += reg_info->base_addr;
9629 ptr_data[reg_offset >> 2] =
9630 I40E_READ_REG(hw, reg_offset);
9637 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9639 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9641 /* Convert word count to byte count */
9642 return hw->nvm.sr_size << 1;
9645 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9646 struct rte_dev_eeprom_info *eeprom)
9648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9649 uint16_t *data = eeprom->data;
9650 uint16_t offset, length, cnt_words;
9653 offset = eeprom->offset >> 1;
9654 length = eeprom->length >> 1;
9657 if (offset > hw->nvm.sr_size ||
9658 offset + length > hw->nvm.sr_size) {
9659 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9663 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9665 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9666 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9667 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9674 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9675 struct ether_addr *mac_addr)
9677 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9679 if (!is_valid_assigned_ether_addr(mac_addr)) {
9680 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9684 /* Flags: 0x3 updates port address */
9685 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9689 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9692 struct rte_eth_dev_data *dev_data = pf->dev_data;
9693 uint32_t frame_size = mtu + ETHER_HDR_LEN
9694 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9697 /* check if mtu is within the allowed range */
9698 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9701 /* mtu setting is forbidden if port is start */
9702 if (dev_data->dev_started) {
9704 "port %d must be stopped before configuration\n",
9709 if (frame_size > ETHER_MAX_LEN)
9710 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9712 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9714 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;