1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
50 #define I40E_CLEAR_PXE_WAIT_MS 200
52 /* Maximun number of capability elements */
53 #define I40E_MAX_CAP_ELE_NUM 128
55 /* Wait count and interval */
56 #define I40E_CHK_Q_ENA_COUNT 1000
57 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
59 /* Maximun number of VSI */
60 #define I40E_MAX_NUM_VSIS (384UL)
62 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
64 /* Flow control default timer */
65 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
67 /* Flow control enable fwd bit */
68 #define I40E_PRTMAC_FWD_CTRL 0x00000001
70 /* Receive Packet Buffer size */
71 #define I40E_RXPBSIZE (968 * 1024)
74 #define I40E_KILOSHIFT 10
76 /* Flow control default high water */
77 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
79 /* Flow control default low water */
80 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
82 /* Receive Average Packet Size in Byte*/
83 #define I40E_PACKET_AVERAGE_SIZE 128
85 /* Mask of PF interrupt causes */
86 #define I40E_PFINT_ICR0_ENA_MASK ( \
87 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
88 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
89 I40E_PFINT_ICR0_ENA_GRST_MASK | \
90 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
91 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
92 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
93 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
94 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
95 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
97 #define I40E_FLOW_TYPES ( \
98 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
103 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
108 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
110 /* Additional timesync values. */
111 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
112 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
113 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
114 #define I40E_PRTTSYN_TSYNENA 0x80000000
115 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
116 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
119 * Below are values for writing un-exposed registers suggested
122 /* Destination MAC address */
123 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
124 /* Source MAC address */
125 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
126 /* Outer (S-Tag) VLAN tag in the outer L2 header */
127 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
128 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
129 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
130 /* Single VLAN tag in the inner L2 header */
131 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
132 /* Source IPv4 address */
133 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
134 /* Destination IPv4 address */
135 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
136 /* Source IPv4 address for X722 */
137 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
138 /* Destination IPv4 address for X722 */
139 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
140 /* IPv4 Protocol for X722 */
141 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
142 /* IPv4 Time to Live for X722 */
143 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
144 /* IPv4 Type of Service (TOS) */
145 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
147 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
148 /* IPv4 Time to Live */
149 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
150 /* Source IPv6 address */
151 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
152 /* Destination IPv6 address */
153 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
154 /* IPv6 Traffic Class (TC) */
155 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
156 /* IPv6 Next Header */
157 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
159 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
161 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
162 /* Destination L4 port */
163 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
164 /* SCTP verification tag */
165 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
166 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
167 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
168 /* Source port of tunneling UDP */
169 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
170 /* Destination port of tunneling UDP */
171 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
172 /* UDP Tunneling ID, NVGRE/GRE key */
173 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
174 /* Last ether type */
175 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
176 /* Tunneling outer destination IPv4 address */
177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
178 /* Tunneling outer destination IPv6 address */
179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
180 /* 1st word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
182 /* 2nd word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
184 /* 3rd word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
186 /* 4th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
188 /* 5th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
190 /* 6th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
192 /* 7th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
194 /* 8th word of flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
196 /* all 8 words flex payload */
197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
198 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
200 #define I40E_TRANSLATE_INSET 0
201 #define I40E_TRANSLATE_REG 1
203 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
204 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
205 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
206 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
207 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
208 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
210 /* PCI offset for querying capability */
211 #define PCI_DEV_CAP_REG 0xA4
212 /* PCI offset for enabling/disabling Extended Tag */
213 #define PCI_DEV_CTRL_REG 0xA8
214 /* Bit mask of Extended Tag capability */
215 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
216 /* Bit shift of Extended Tag enable/disable */
217 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
218 /* Bit mask of Extended Tag enable/disable */
219 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
221 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
222 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
223 static int i40e_dev_configure(struct rte_eth_dev *dev);
224 static int i40e_dev_start(struct rte_eth_dev *dev);
225 static void i40e_dev_stop(struct rte_eth_dev *dev);
226 static void i40e_dev_close(struct rte_eth_dev *dev);
227 static int i40e_dev_reset(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
229 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
231 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
233 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
234 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
235 struct rte_eth_stats *stats);
236 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
237 struct rte_eth_xstat *xstats, unsigned n);
238 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
239 struct rte_eth_xstat_name *xstats_names,
241 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static int i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct rte_ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static void i40e_dev_alarm_handler(void *param);
294 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
295 uint32_t base, uint32_t num);
296 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
297 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
299 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
301 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
302 static int i40e_veb_release(struct i40e_veb *veb);
303 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
304 struct i40e_vsi *vsi);
305 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
306 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
307 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
308 struct i40e_macvlan_filter *mv_f,
311 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
312 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
314 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
315 struct rte_eth_rss_conf *rss_conf);
316 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
317 struct rte_eth_udp_tunnel *udp_tunnel);
318 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
319 struct rte_eth_udp_tunnel *udp_tunnel);
320 static void i40e_filter_input_set_init(struct i40e_pf *pf);
321 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
325 enum rte_filter_type filter_type,
326 enum rte_filter_op filter_op,
328 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
329 struct rte_eth_dcb_info *dcb_info);
330 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
331 static void i40e_configure_registers(struct i40e_hw *hw);
332 static void i40e_hw_init(struct rte_eth_dev *dev);
333 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
334 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
340 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
341 struct rte_eth_mirror_conf *mirror_conf,
342 uint8_t sw_id, uint8_t on);
343 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
345 static int i40e_timesync_enable(struct rte_eth_dev *dev);
346 static int i40e_timesync_disable(struct rte_eth_dev *dev);
347 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
348 struct timespec *timestamp,
350 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp);
352 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
354 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
356 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
357 struct timespec *timestamp);
358 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
359 const struct timespec *timestamp);
361 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
363 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
366 static int i40e_get_regs(struct rte_eth_dev *dev,
367 struct rte_dev_reg_info *regs);
369 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
371 static int i40e_get_eeprom(struct rte_eth_dev *dev,
372 struct rte_dev_eeprom_info *eeprom);
374 static int i40e_get_module_info(struct rte_eth_dev *dev,
375 struct rte_eth_dev_module_info *modinfo);
376 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
377 struct rte_dev_eeprom_info *info);
379 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
380 struct rte_ether_addr *mac_addr);
382 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
384 static int i40e_ethertype_filter_convert(
385 const struct rte_eth_ethertype_filter *input,
386 struct i40e_ethertype_filter *filter);
387 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
388 struct i40e_ethertype_filter *filter);
390 static int i40e_tunnel_filter_convert(
391 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
392 struct i40e_tunnel_filter *tunnel_filter);
393 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
394 struct i40e_tunnel_filter *tunnel_filter);
395 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
397 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
398 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
399 static void i40e_filter_restore(struct i40e_pf *pf);
400 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
402 static const char *const valid_keys[] = {
403 ETH_I40E_FLOATING_VEB_ARG,
404 ETH_I40E_FLOATING_VEB_LIST_ARG,
405 ETH_I40E_SUPPORT_MULTI_DRIVER,
406 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
407 ETH_I40E_USE_LATEST_VEC,
411 static const struct rte_pci_id pci_id_i40e_map[] = {
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
438 { .vendor_id = 0, /* sentinel */ },
441 static const struct eth_dev_ops i40e_eth_dev_ops = {
442 .dev_configure = i40e_dev_configure,
443 .dev_start = i40e_dev_start,
444 .dev_stop = i40e_dev_stop,
445 .dev_close = i40e_dev_close,
446 .dev_reset = i40e_dev_reset,
447 .promiscuous_enable = i40e_dev_promiscuous_enable,
448 .promiscuous_disable = i40e_dev_promiscuous_disable,
449 .allmulticast_enable = i40e_dev_allmulticast_enable,
450 .allmulticast_disable = i40e_dev_allmulticast_disable,
451 .dev_set_link_up = i40e_dev_set_link_up,
452 .dev_set_link_down = i40e_dev_set_link_down,
453 .link_update = i40e_dev_link_update,
454 .stats_get = i40e_dev_stats_get,
455 .xstats_get = i40e_dev_xstats_get,
456 .xstats_get_names = i40e_dev_xstats_get_names,
457 .stats_reset = i40e_dev_stats_reset,
458 .xstats_reset = i40e_dev_stats_reset,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .rx_burst_mode_get = i40e_rx_burst_mode_get,
498 .tx_burst_mode_get = i40e_tx_burst_mode_get,
499 .mirror_rule_set = i40e_mirror_rule_set,
500 .mirror_rule_reset = i40e_mirror_rule_reset,
501 .timesync_enable = i40e_timesync_enable,
502 .timesync_disable = i40e_timesync_disable,
503 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
504 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
505 .get_dcb_info = i40e_dev_get_dcb_info,
506 .timesync_adjust_time = i40e_timesync_adjust_time,
507 .timesync_read_time = i40e_timesync_read_time,
508 .timesync_write_time = i40e_timesync_write_time,
509 .get_reg = i40e_get_regs,
510 .get_eeprom_length = i40e_get_eeprom_length,
511 .get_eeprom = i40e_get_eeprom,
512 .get_module_info = i40e_get_module_info,
513 .get_module_eeprom = i40e_get_module_eeprom,
514 .mac_addr_set = i40e_set_default_mac_addr,
515 .mtu_set = i40e_dev_mtu_set,
516 .tm_ops_get = i40e_tm_ops_get,
517 .tx_done_cleanup = i40e_tx_done_cleanup,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
534 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
535 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
536 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
540 sizeof(rte_i40e_stats_strings[0]))
542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
543 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
544 tx_dropped_link_down)},
545 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
546 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
548 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
549 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
551 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
555 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
556 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
557 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
558 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
559 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
560 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
577 mac_short_packet_dropped)},
578 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
581 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
582 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
594 {"rx_flow_director_atr_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
596 {"rx_flow_director_sb_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
598 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
609 sizeof(rte_i40e_hw_port_strings[0]))
611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
612 {"xon_packets", offsetof(struct i40e_hw_port_stats,
614 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
619 sizeof(rte_i40e_rxq_prio_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
627 priority_xon_2_xoff)},
630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
631 sizeof(rte_i40e_txq_prio_strings[0]))
634 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
635 struct rte_pci_device *pci_dev)
637 char name[RTE_ETH_NAME_MAX_LEN];
638 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
641 if (pci_dev->device.devargs) {
642 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
648 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
649 sizeof(struct i40e_adapter),
650 eth_dev_pci_specific_init, pci_dev,
651 eth_i40e_dev_init, NULL);
653 if (retval || eth_da.nb_representor_ports < 1)
656 /* probe VF representor ports */
657 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
658 pci_dev->device.name);
660 if (pf_ethdev == NULL)
663 for (i = 0; i < eth_da.nb_representor_ports; i++) {
664 struct i40e_vf_representor representor = {
665 .vf_id = eth_da.representor_ports[i],
666 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
667 pf_ethdev->data->dev_private)->switch_domain_id,
668 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
669 pf_ethdev->data->dev_private)
672 /* representor port net_bdf_port */
673 snprintf(name, sizeof(name), "net_%s_representor_%d",
674 pci_dev->device.name, eth_da.representor_ports[i]);
676 retval = rte_eth_dev_create(&pci_dev->device, name,
677 sizeof(struct i40e_vf_representor), NULL, NULL,
678 i40e_vf_representor_init, &representor);
681 PMD_DRV_LOG(ERR, "failed to create i40e vf "
682 "representor %s.", name);
688 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
690 struct rte_eth_dev *ethdev;
692 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
696 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
697 return rte_eth_dev_pci_generic_remove(pci_dev,
698 i40e_vf_representor_uninit);
700 return rte_eth_dev_pci_generic_remove(pci_dev,
701 eth_i40e_dev_uninit);
704 static struct rte_pci_driver rte_i40e_pmd = {
705 .id_table = pci_id_i40e_map,
706 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
707 .probe = eth_i40e_pci_probe,
708 .remove = eth_i40e_pci_remove,
712 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
715 uint32_t ori_reg_val;
716 struct rte_eth_dev *dev;
718 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
719 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
720 i40e_write_rx_ctl(hw, reg_addr, reg_val);
721 if (ori_reg_val != reg_val)
723 "i40e device %s changed global register [0x%08x]."
724 " original: 0x%08x, new: 0x%08x",
725 dev->device->name, reg_addr, ori_reg_val, reg_val);
728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
730 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
732 #ifndef I40E_GLQF_ORT
733 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
735 #ifndef I40E_GLQF_PIT
736 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
738 #ifndef I40E_GLQF_L3_MAP
739 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
742 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
745 * Initialize registers for parsing packet type of QinQ
746 * This should be removed from code once proper
747 * configuration API is added to avoid configuration conflicts
748 * between ports of the same device.
750 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
751 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
754 static inline void i40e_config_automask(struct i40e_pf *pf)
756 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
759 /* INTENA flag is not auto-cleared for interrupt */
760 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
761 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
762 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
764 /* If support multi-driver, PF will use INT0. */
765 if (!pf->support_multi_driver)
766 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
768 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
771 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
774 * Add a ethertype filter to drop all flow control frames transmitted
778 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
780 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
781 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
782 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
783 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
786 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
787 I40E_FLOW_CONTROL_ETHERTYPE, flags,
788 pf->main_vsi_seid, 0,
792 "Failed to add filter to drop flow control frames from VSIs.");
796 floating_veb_list_handler(__rte_unused const char *key,
797 const char *floating_veb_value,
801 unsigned int count = 0;
804 bool *vf_floating_veb = opaque;
806 while (isblank(*floating_veb_value))
807 floating_veb_value++;
809 /* Reset floating VEB configuration for VFs */
810 for (idx = 0; idx < I40E_MAX_VF; idx++)
811 vf_floating_veb[idx] = false;
815 while (isblank(*floating_veb_value))
816 floating_veb_value++;
817 if (*floating_veb_value == '\0')
820 idx = strtoul(floating_veb_value, &end, 10);
821 if (errno || end == NULL)
823 while (isblank(*end))
827 } else if ((*end == ';') || (*end == '\0')) {
829 if (min == I40E_MAX_VF)
831 if (max >= I40E_MAX_VF)
832 max = I40E_MAX_VF - 1;
833 for (idx = min; idx <= max; idx++) {
834 vf_floating_veb[idx] = true;
841 floating_veb_value = end + 1;
842 } while (*end != '\0');
851 config_vf_floating_veb(struct rte_devargs *devargs,
852 uint16_t floating_veb,
853 bool *vf_floating_veb)
855 struct rte_kvargs *kvlist;
857 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
861 /* All the VFs attach to the floating VEB by default
862 * when the floating VEB is enabled.
864 for (i = 0; i < I40E_MAX_VF; i++)
865 vf_floating_veb[i] = true;
870 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
874 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
875 rte_kvargs_free(kvlist);
878 /* When the floating_veb_list parameter exists, all the VFs
879 * will attach to the legacy VEB firstly, then configure VFs
880 * to the floating VEB according to the floating_veb_list.
882 if (rte_kvargs_process(kvlist, floating_veb_list,
883 floating_veb_list_handler,
884 vf_floating_veb) < 0) {
885 rte_kvargs_free(kvlist);
888 rte_kvargs_free(kvlist);
892 i40e_check_floating_handler(__rte_unused const char *key,
894 __rte_unused void *opaque)
896 if (strcmp(value, "1"))
903 is_floating_veb_supported(struct rte_devargs *devargs)
905 struct rte_kvargs *kvlist;
906 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
911 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
915 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
916 rte_kvargs_free(kvlist);
919 /* Floating VEB is enabled when there's key-value:
920 * enable_floating_veb=1
922 if (rte_kvargs_process(kvlist, floating_veb_key,
923 i40e_check_floating_handler, NULL) < 0) {
924 rte_kvargs_free(kvlist);
927 rte_kvargs_free(kvlist);
933 config_floating_veb(struct rte_eth_dev *dev)
935 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
936 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
939 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
941 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
943 is_floating_veb_supported(pci_dev->device.devargs);
944 config_vf_floating_veb(pci_dev->device.devargs,
946 pf->floating_veb_list);
948 pf->floating_veb = false;
952 #define I40E_L2_TAGS_S_TAG_SHIFT 1
953 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
956 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
958 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
959 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
960 char ethertype_hash_name[RTE_HASH_NAMESIZE];
963 struct rte_hash_parameters ethertype_hash_params = {
964 .name = ethertype_hash_name,
965 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
966 .key_len = sizeof(struct i40e_ethertype_filter_input),
967 .hash_func = rte_hash_crc,
968 .hash_func_init_val = 0,
969 .socket_id = rte_socket_id(),
972 /* Initialize ethertype filter rule list and hash */
973 TAILQ_INIT(ðertype_rule->ethertype_list);
974 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
975 "ethertype_%s", dev->device->name);
976 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
977 if (!ethertype_rule->hash_table) {
978 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
981 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
982 sizeof(struct i40e_ethertype_filter *) *
983 I40E_MAX_ETHERTYPE_FILTER_NUM,
985 if (!ethertype_rule->hash_map) {
987 "Failed to allocate memory for ethertype hash map!");
989 goto err_ethertype_hash_map_alloc;
994 err_ethertype_hash_map_alloc:
995 rte_hash_free(ethertype_rule->hash_table);
1001 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1005 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1008 struct rte_hash_parameters tunnel_hash_params = {
1009 .name = tunnel_hash_name,
1010 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1011 .key_len = sizeof(struct i40e_tunnel_filter_input),
1012 .hash_func = rte_hash_crc,
1013 .hash_func_init_val = 0,
1014 .socket_id = rte_socket_id(),
1017 /* Initialize tunnel filter rule list and hash */
1018 TAILQ_INIT(&tunnel_rule->tunnel_list);
1019 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1020 "tunnel_%s", dev->device->name);
1021 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1022 if (!tunnel_rule->hash_table) {
1023 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1026 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1027 sizeof(struct i40e_tunnel_filter *) *
1028 I40E_MAX_TUNNEL_FILTER_NUM,
1030 if (!tunnel_rule->hash_map) {
1032 "Failed to allocate memory for tunnel hash map!");
1034 goto err_tunnel_hash_map_alloc;
1039 err_tunnel_hash_map_alloc:
1040 rte_hash_free(tunnel_rule->hash_table);
1046 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1048 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1050 struct i40e_fdir_info *fdir_info = &pf->fdir;
1051 char fdir_hash_name[RTE_HASH_NAMESIZE];
1052 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1053 uint32_t best = hw->func_caps.fd_filters_best_effort;
1054 struct rte_bitmap *bmp = NULL;
1060 struct rte_hash_parameters fdir_hash_params = {
1061 .name = fdir_hash_name,
1062 .entries = I40E_MAX_FDIR_FILTER_NUM,
1063 .key_len = sizeof(struct i40e_fdir_input),
1064 .hash_func = rte_hash_crc,
1065 .hash_func_init_val = 0,
1066 .socket_id = rte_socket_id(),
1069 /* Initialize flow director filter rule list and hash */
1070 TAILQ_INIT(&fdir_info->fdir_list);
1071 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1072 "fdir_%s", dev->device->name);
1073 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1074 if (!fdir_info->hash_table) {
1075 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1079 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1080 sizeof(struct i40e_fdir_filter *) *
1081 I40E_MAX_FDIR_FILTER_NUM,
1083 if (!fdir_info->hash_map) {
1085 "Failed to allocate memory for fdir hash map!");
1087 goto err_fdir_hash_map_alloc;
1090 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1091 sizeof(struct i40e_fdir_filter) *
1092 I40E_MAX_FDIR_FILTER_NUM,
1095 if (!fdir_info->fdir_filter_array) {
1097 "Failed to allocate memory for fdir filter array!");
1099 goto err_fdir_filter_array_alloc;
1102 fdir_info->fdir_space_size = alloc + best;
1103 fdir_info->fdir_actual_cnt = 0;
1104 fdir_info->fdir_guarantee_total_space = alloc;
1105 fdir_info->fdir_guarantee_free_space =
1106 fdir_info->fdir_guarantee_total_space;
1108 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1110 fdir_info->fdir_flow_pool.pool =
1111 rte_zmalloc("i40e_fdir_entry",
1112 sizeof(struct i40e_fdir_entry) *
1113 fdir_info->fdir_space_size,
1116 if (!fdir_info->fdir_flow_pool.pool) {
1118 "Failed to allocate memory for bitmap flow!");
1120 goto err_fdir_bitmap_flow_alloc;
1123 for (i = 0; i < fdir_info->fdir_space_size; i++)
1124 fdir_info->fdir_flow_pool.pool[i].idx = i;
1127 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1128 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1131 "Failed to allocate memory for fdir bitmap!");
1133 goto err_fdir_mem_alloc;
1135 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1138 "Failed to initialization fdir bitmap!");
1140 goto err_fdir_bmp_alloc;
1142 for (i = 0; i < fdir_info->fdir_space_size; i++)
1143 rte_bitmap_set(bmp, i);
1145 fdir_info->fdir_flow_pool.bitmap = bmp;
1152 rte_free(fdir_info->fdir_flow_pool.pool);
1153 err_fdir_bitmap_flow_alloc:
1154 rte_free(fdir_info->fdir_filter_array);
1155 err_fdir_filter_array_alloc:
1156 rte_free(fdir_info->hash_map);
1157 err_fdir_hash_map_alloc:
1158 rte_hash_free(fdir_info->hash_table);
1164 i40e_init_customized_info(struct i40e_pf *pf)
1168 /* Initialize customized pctype */
1169 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1170 pf->customized_pctype[i].index = i;
1171 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1172 pf->customized_pctype[i].valid = false;
1175 pf->gtp_support = false;
1176 pf->esp_support = false;
1180 i40e_init_filter_invalidation(struct i40e_pf *pf)
1182 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1183 struct i40e_fdir_info *fdir_info = &pf->fdir;
1184 uint32_t glqf_ctl_reg = 0;
1186 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1187 if (!pf->support_multi_driver) {
1188 fdir_info->fdir_invalprio = 1;
1189 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1190 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1191 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1193 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1194 fdir_info->fdir_invalprio = 1;
1195 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1197 fdir_info->fdir_invalprio = 0;
1198 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1204 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1206 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1208 struct i40e_queue_regions *info = &pf->queue_region;
1211 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1212 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1214 memset(info, 0, sizeof(struct i40e_queue_regions));
1218 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1223 unsigned long support_multi_driver;
1226 pf = (struct i40e_pf *)opaque;
1229 support_multi_driver = strtoul(value, &end, 10);
1230 if (errno != 0 || end == value || *end != 0) {
1231 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1235 if (support_multi_driver == 1 || support_multi_driver == 0)
1236 pf->support_multi_driver = (bool)support_multi_driver;
1238 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1239 "enable global configuration by default."
1240 ETH_I40E_SUPPORT_MULTI_DRIVER);
1245 i40e_support_multi_driver(struct rte_eth_dev *dev)
1247 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1248 struct rte_kvargs *kvlist;
1251 /* Enable global configuration by default */
1252 pf->support_multi_driver = false;
1254 if (!dev->device->devargs)
1257 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1261 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1262 if (!kvargs_count) {
1263 rte_kvargs_free(kvlist);
1267 if (kvargs_count > 1)
1268 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1269 "the first invalid or last valid one is used !",
1270 ETH_I40E_SUPPORT_MULTI_DRIVER);
1272 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1273 i40e_parse_multi_drv_handler, pf) < 0) {
1274 rte_kvargs_free(kvlist);
1278 rte_kvargs_free(kvlist);
1283 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1284 uint32_t reg_addr, uint64_t reg_val,
1285 struct i40e_asq_cmd_details *cmd_details)
1287 uint64_t ori_reg_val;
1288 struct rte_eth_dev *dev;
1291 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1292 if (ret != I40E_SUCCESS) {
1294 "Fail to debug read from 0x%08x",
1298 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1300 if (ori_reg_val != reg_val)
1301 PMD_DRV_LOG(WARNING,
1302 "i40e device %s changed global register [0x%08x]."
1303 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1304 dev->device->name, reg_addr, ori_reg_val, reg_val);
1306 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1310 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1314 struct i40e_adapter *ad = opaque;
1317 use_latest_vec = atoi(value);
1319 if (use_latest_vec != 0 && use_latest_vec != 1)
1320 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1322 ad->use_latest_vec = (uint8_t)use_latest_vec;
1328 i40e_use_latest_vec(struct rte_eth_dev *dev)
1330 struct i40e_adapter *ad =
1331 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1332 struct rte_kvargs *kvlist;
1335 ad->use_latest_vec = false;
1337 if (!dev->device->devargs)
1340 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1344 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1345 if (!kvargs_count) {
1346 rte_kvargs_free(kvlist);
1350 if (kvargs_count > 1)
1351 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1352 "the first invalid or last valid one is used !",
1353 ETH_I40E_USE_LATEST_VEC);
1355 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1356 i40e_parse_latest_vec_handler, ad) < 0) {
1357 rte_kvargs_free(kvlist);
1361 rte_kvargs_free(kvlist);
1366 read_vf_msg_config(__rte_unused const char *key,
1370 struct i40e_vf_msg_cfg *cfg = opaque;
1372 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1373 &cfg->ignore_second) != 3) {
1374 memset(cfg, 0, sizeof(*cfg));
1375 PMD_DRV_LOG(ERR, "format error! example: "
1376 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1381 * If the message validation function been enabled, the 'period'
1382 * and 'ignore_second' must greater than 0.
1384 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1385 memset(cfg, 0, sizeof(*cfg));
1386 PMD_DRV_LOG(ERR, "%s error! the second and third"
1387 " number must be greater than 0!",
1388 ETH_I40E_VF_MSG_CFG);
1396 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1397 struct i40e_vf_msg_cfg *msg_cfg)
1399 struct rte_kvargs *kvlist;
1403 memset(msg_cfg, 0, sizeof(*msg_cfg));
1405 if (!dev->device->devargs)
1408 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1412 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1416 if (kvargs_count > 1) {
1417 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1418 ETH_I40E_VF_MSG_CFG);
1423 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1424 read_vf_msg_config, msg_cfg) < 0)
1428 rte_kvargs_free(kvlist);
1432 #define I40E_ALARM_INTERVAL 50000 /* us */
1435 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1437 struct rte_pci_device *pci_dev;
1438 struct rte_intr_handle *intr_handle;
1439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441 struct i40e_vsi *vsi;
1444 uint8_t aq_fail = 0;
1446 PMD_INIT_FUNC_TRACE();
1448 dev->dev_ops = &i40e_eth_dev_ops;
1449 dev->rx_pkt_burst = i40e_recv_pkts;
1450 dev->tx_pkt_burst = i40e_xmit_pkts;
1451 dev->tx_pkt_prepare = i40e_prep_pkts;
1453 /* for secondary processes, we don't initialise any further as primary
1454 * has already done this work. Only check we don't need a different
1456 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1457 i40e_set_rx_function(dev);
1458 i40e_set_tx_function(dev);
1461 i40e_set_default_ptype_table(dev);
1462 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1463 intr_handle = &pci_dev->intr_handle;
1465 rte_eth_copy_pci_info(dev, pci_dev);
1467 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1468 pf->adapter->eth_dev = dev;
1469 pf->dev_data = dev->data;
1471 hw->back = I40E_PF_TO_ADAPTER(pf);
1472 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1475 "Hardware is not available, as address is NULL");
1479 hw->vendor_id = pci_dev->id.vendor_id;
1480 hw->device_id = pci_dev->id.device_id;
1481 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1482 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1483 hw->bus.device = pci_dev->addr.devid;
1484 hw->bus.func = pci_dev->addr.function;
1485 hw->adapter_stopped = 0;
1486 hw->adapter_closed = 0;
1488 /* Init switch device pointer */
1489 hw->switch_dev = NULL;
1492 * Switch Tag value should not be identical to either the First Tag
1493 * or Second Tag values. So set something other than common Ethertype
1494 * for internal switching.
1496 hw->switch_tag = 0xffff;
1498 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1499 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1500 PMD_INIT_LOG(ERR, "\nERROR: "
1501 "Firmware recovery mode detected. Limiting functionality.\n"
1502 "Refer to the Intel(R) Ethernet Adapters and Devices "
1503 "User Guide for details on firmware recovery mode.");
1507 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1508 /* Check if need to support multi-driver */
1509 i40e_support_multi_driver(dev);
1510 /* Check if users want the latest supported vec path */
1511 i40e_use_latest_vec(dev);
1513 /* Make sure all is clean before doing PF reset */
1516 /* Reset here to make sure all is clean for each PF */
1517 ret = i40e_pf_reset(hw);
1519 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1523 /* Initialize the shared code (base driver) */
1524 ret = i40e_init_shared_code(hw);
1526 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1530 /* Initialize the parameters for adminq */
1531 i40e_init_adminq_parameter(hw);
1532 ret = i40e_init_adminq(hw);
1533 if (ret != I40E_SUCCESS) {
1534 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1537 /* Firmware of SFP x722 does not support adminq option */
1538 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1539 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1541 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1542 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1543 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1544 ((hw->nvm.version >> 12) & 0xf),
1545 ((hw->nvm.version >> 4) & 0xff),
1546 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1548 /* Initialize the hardware */
1551 i40e_config_automask(pf);
1553 i40e_set_default_pctype_table(dev);
1556 * To work around the NVM issue, initialize registers
1557 * for packet type of QinQ by software.
1558 * It should be removed once issues are fixed in NVM.
1560 if (!pf->support_multi_driver)
1561 i40e_GLQF_reg_init(hw);
1563 /* Initialize the input set for filters (hash and fd) to default value */
1564 i40e_filter_input_set_init(pf);
1566 /* initialise the L3_MAP register */
1567 if (!pf->support_multi_driver) {
1568 ret = i40e_aq_debug_write_global_register(hw,
1569 I40E_GLQF_L3_MAP(40),
1572 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1575 "Global register 0x%08x is changed with 0x28",
1576 I40E_GLQF_L3_MAP(40));
1579 /* Need the special FW version to support floating VEB */
1580 config_floating_veb(dev);
1581 /* Clear PXE mode */
1582 i40e_clear_pxe_mode(hw);
1583 i40e_dev_sync_phy_type(hw);
1586 * On X710, performance number is far from the expectation on recent
1587 * firmware versions. The fix for this issue may not be integrated in
1588 * the following firmware version. So the workaround in software driver
1589 * is needed. It needs to modify the initial values of 3 internal only
1590 * registers. Note that the workaround can be removed when it is fixed
1591 * in firmware in the future.
1593 i40e_configure_registers(hw);
1595 /* Get hw capabilities */
1596 ret = i40e_get_cap(hw);
1597 if (ret != I40E_SUCCESS) {
1598 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1599 goto err_get_capabilities;
1602 /* Initialize parameters for PF */
1603 ret = i40e_pf_parameter_init(dev);
1605 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1606 goto err_parameter_init;
1609 /* Initialize the queue management */
1610 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1612 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1613 goto err_qp_pool_init;
1615 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1616 hw->func_caps.num_msix_vectors - 1);
1618 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1619 goto err_msix_pool_init;
1622 /* Initialize lan hmc */
1623 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1624 hw->func_caps.num_rx_qp, 0, 0);
1625 if (ret != I40E_SUCCESS) {
1626 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1627 goto err_init_lan_hmc;
1630 /* Configure lan hmc */
1631 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1632 if (ret != I40E_SUCCESS) {
1633 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1634 goto err_configure_lan_hmc;
1637 /* Get and check the mac address */
1638 i40e_get_mac_addr(hw, hw->mac.addr);
1639 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1640 PMD_INIT_LOG(ERR, "mac address is not valid");
1642 goto err_get_mac_addr;
1644 /* Copy the permanent MAC address */
1645 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1646 (struct rte_ether_addr *)hw->mac.perm_addr);
1648 /* Disable flow control */
1649 hw->fc.requested_mode = I40E_FC_NONE;
1650 i40e_set_fc(hw, &aq_fail, TRUE);
1652 /* Set the global registers with default ether type value */
1653 if (!pf->support_multi_driver) {
1654 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1655 RTE_ETHER_TYPE_VLAN);
1656 if (ret != I40E_SUCCESS) {
1658 "Failed to set the default outer "
1660 goto err_setup_pf_switch;
1664 /* PF setup, which includes VSI setup */
1665 ret = i40e_pf_setup(pf);
1667 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1668 goto err_setup_pf_switch;
1673 /* Disable double vlan by default */
1674 i40e_vsi_config_double_vlan(vsi, FALSE);
1676 /* Disable S-TAG identification when floating_veb is disabled */
1677 if (!pf->floating_veb) {
1678 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1679 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1680 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1681 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1685 if (!vsi->max_macaddrs)
1686 len = RTE_ETHER_ADDR_LEN;
1688 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1690 /* Should be after VSI initialized */
1691 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1692 if (!dev->data->mac_addrs) {
1694 "Failed to allocated memory for storing mac address");
1697 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1698 &dev->data->mac_addrs[0]);
1700 /* Pass the information to the rte_eth_dev_close() that it should also
1701 * release the private port resources.
1703 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1705 /* Init dcb to sw mode by default */
1706 ret = i40e_dcb_init_configure(dev, TRUE);
1707 if (ret != I40E_SUCCESS) {
1708 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1709 pf->flags &= ~I40E_FLAG_DCB;
1711 /* Update HW struct after DCB configuration */
1714 /* initialize pf host driver to setup SRIOV resource if applicable */
1715 i40e_pf_host_init(dev);
1717 /* register callback func to eal lib */
1718 rte_intr_callback_register(intr_handle,
1719 i40e_dev_interrupt_handler, dev);
1721 /* configure and enable device interrupt */
1722 i40e_pf_config_irq0(hw, TRUE);
1723 i40e_pf_enable_irq0(hw);
1725 /* enable uio intr after callback register */
1726 rte_intr_enable(intr_handle);
1728 /* By default disable flexible payload in global configuration */
1729 if (!pf->support_multi_driver)
1730 i40e_flex_payload_reg_set_default(hw);
1733 * Add an ethertype filter to drop all flow control frames transmitted
1734 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1737 i40e_add_tx_flow_control_drop_filter(pf);
1739 /* Set the max frame size to 0x2600 by default,
1740 * in case other drivers changed the default value.
1742 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1744 /* initialize mirror rule list */
1745 TAILQ_INIT(&pf->mirror_list);
1747 /* initialize RSS rule list */
1748 TAILQ_INIT(&pf->rss_config_list);
1750 /* initialize Traffic Manager configuration */
1751 i40e_tm_conf_init(dev);
1753 /* Initialize customized information */
1754 i40e_init_customized_info(pf);
1756 /* Initialize the filter invalidation configuration */
1757 i40e_init_filter_invalidation(pf);
1759 ret = i40e_init_ethtype_filter_list(dev);
1761 goto err_init_ethtype_filter_list;
1762 ret = i40e_init_tunnel_filter_list(dev);
1764 goto err_init_tunnel_filter_list;
1765 ret = i40e_init_fdir_filter_list(dev);
1767 goto err_init_fdir_filter_list;
1769 /* initialize queue region configuration */
1770 i40e_init_queue_region_conf(dev);
1772 /* initialize RSS configuration from rte_flow */
1773 memset(&pf->rss_info, 0,
1774 sizeof(struct i40e_rte_flow_rss_conf));
1776 /* reset all stats of the device, including pf and main vsi */
1777 i40e_dev_stats_reset(dev);
1781 err_init_fdir_filter_list:
1782 rte_free(pf->tunnel.hash_table);
1783 rte_free(pf->tunnel.hash_map);
1784 err_init_tunnel_filter_list:
1785 rte_free(pf->ethertype.hash_table);
1786 rte_free(pf->ethertype.hash_map);
1787 err_init_ethtype_filter_list:
1788 rte_free(dev->data->mac_addrs);
1789 dev->data->mac_addrs = NULL;
1791 i40e_vsi_release(pf->main_vsi);
1792 err_setup_pf_switch:
1794 err_configure_lan_hmc:
1795 (void)i40e_shutdown_lan_hmc(hw);
1797 i40e_res_pool_destroy(&pf->msix_pool);
1799 i40e_res_pool_destroy(&pf->qp_pool);
1802 err_get_capabilities:
1803 (void)i40e_shutdown_adminq(hw);
1809 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1811 struct i40e_ethertype_filter *p_ethertype;
1812 struct i40e_ethertype_rule *ethertype_rule;
1814 ethertype_rule = &pf->ethertype;
1815 /* Remove all ethertype filter rules and hash */
1816 if (ethertype_rule->hash_map)
1817 rte_free(ethertype_rule->hash_map);
1818 if (ethertype_rule->hash_table)
1819 rte_hash_free(ethertype_rule->hash_table);
1821 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1822 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1823 p_ethertype, rules);
1824 rte_free(p_ethertype);
1829 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1831 struct i40e_tunnel_filter *p_tunnel;
1832 struct i40e_tunnel_rule *tunnel_rule;
1834 tunnel_rule = &pf->tunnel;
1835 /* Remove all tunnel director rules and hash */
1836 if (tunnel_rule->hash_map)
1837 rte_free(tunnel_rule->hash_map);
1838 if (tunnel_rule->hash_table)
1839 rte_hash_free(tunnel_rule->hash_table);
1841 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1842 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1848 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1850 struct i40e_fdir_filter *p_fdir;
1851 struct i40e_fdir_info *fdir_info;
1853 fdir_info = &pf->fdir;
1855 /* Remove all flow director rules */
1856 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1857 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1861 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1863 struct i40e_fdir_info *fdir_info;
1865 fdir_info = &pf->fdir;
1867 /* flow director memory cleanup */
1868 if (fdir_info->hash_map)
1869 rte_free(fdir_info->hash_map);
1870 if (fdir_info->hash_table)
1871 rte_hash_free(fdir_info->hash_table);
1872 if (fdir_info->fdir_flow_pool.bitmap)
1873 rte_bitmap_free(fdir_info->fdir_flow_pool.bitmap);
1874 if (fdir_info->fdir_flow_pool.pool)
1875 rte_free(fdir_info->fdir_flow_pool.pool);
1876 if (fdir_info->fdir_filter_array)
1877 rte_free(fdir_info->fdir_filter_array);
1880 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1883 * Disable by default flexible payload
1884 * for corresponding L2/L3/L4 layers.
1886 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1887 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1888 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1892 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1896 PMD_INIT_FUNC_TRACE();
1898 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1901 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903 if (hw->adapter_closed == 0)
1904 i40e_dev_close(dev);
1910 i40e_dev_configure(struct rte_eth_dev *dev)
1912 struct i40e_adapter *ad =
1913 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1919 ret = i40e_dev_sync_phy_type(hw);
1923 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1924 * bulk allocation or vector Rx preconditions we will reset it.
1926 ad->rx_bulk_alloc_allowed = true;
1927 ad->rx_vec_allowed = true;
1928 ad->tx_simple_allowed = true;
1929 ad->tx_vec_allowed = true;
1931 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1932 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1934 /* Only legacy filter API needs the following fdir config. So when the
1935 * legacy filter API is deprecated, the following codes should also be
1938 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1939 ret = i40e_fdir_setup(pf);
1940 if (ret != I40E_SUCCESS) {
1941 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1944 ret = i40e_fdir_configure(dev);
1946 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1950 i40e_fdir_teardown(pf);
1952 ret = i40e_dev_init_vlan(dev);
1957 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1958 * RSS setting have different requirements.
1959 * General PMD driver call sequence are NIC init, configure,
1960 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961 * will try to lookup the VSI that specific queue belongs to if VMDQ
1962 * applicable. So, VMDQ setting has to be done before
1963 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1964 * For RSS setting, it will try to calculate actual configured RX queue
1965 * number, which will be available after rx_queue_setup(). dev_start()
1966 * function is good to place RSS setup.
1968 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969 ret = i40e_vmdq_setup(dev);
1974 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975 ret = i40e_dcb_setup(dev);
1977 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1982 TAILQ_INIT(&pf->flow_list);
1987 /* need to release vmdq resource if exists */
1988 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989 i40e_vsi_release(pf->vmdq[i].vsi);
1990 pf->vmdq[i].vsi = NULL;
1995 /* Need to release fdir resource if exists.
1996 * Only legacy filter API needs the following fdir config. So when the
1997 * legacy filter API is deprecated, the following code should also be
2000 i40e_fdir_teardown(pf);
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2007 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011 uint16_t msix_vect = vsi->msix_intr;
2014 for (i = 0; i < vsi->nb_qps; i++) {
2015 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2020 if (vsi->type != I40E_VSI_SRIOV) {
2021 if (!rte_intr_allow_others(intr_handle)) {
2022 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2025 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2028 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2031 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2036 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037 vsi->user_param + (msix_vect - 1);
2039 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2042 I40E_WRITE_FLUSH(hw);
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047 int base_queue, int nb_queue,
2052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2055 /* Bind all RX queues to allocated MSIX interrupt */
2056 for (i = 0; i < nb_queue; i++) {
2057 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059 ((base_queue + i + 1) <<
2060 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2064 if (i == nb_queue - 1)
2065 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2069 /* Write first RX queue to Link list register as the head element */
2070 if (vsi->type != I40E_VSI_SRIOV) {
2072 i40e_calc_itr_interval(1, pf->support_multi_driver);
2074 if (msix_vect == I40E_MISC_VEC_ID) {
2075 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2077 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2079 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2081 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2084 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2086 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2088 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2090 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2097 if (msix_vect == I40E_MISC_VEC_ID) {
2099 I40E_VPINT_LNKLST0(vsi->user_param),
2101 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2103 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2105 /* num_msix_vectors_vf needs to minus irq0 */
2106 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107 vsi->user_param + (msix_vect - 1);
2109 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2111 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2113 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2117 I40E_WRITE_FLUSH(hw);
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2123 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127 uint16_t msix_vect = vsi->msix_intr;
2128 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129 uint16_t queue_idx = 0;
2133 for (i = 0; i < vsi->nb_qps; i++) {
2134 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2138 /* VF bind interrupt */
2139 if (vsi->type == I40E_VSI_SRIOV) {
2140 if (vsi->nb_msix == 0) {
2141 PMD_DRV_LOG(ERR, "No msix resource");
2144 __vsi_queues_bind_intr(vsi, msix_vect,
2145 vsi->base_queue, vsi->nb_qps,
2150 /* PF & VMDq bind interrupt */
2151 if (rte_intr_dp_is_en(intr_handle)) {
2152 if (vsi->type == I40E_VSI_MAIN) {
2155 } else if (vsi->type == I40E_VSI_VMDQ2) {
2156 struct i40e_vsi *main_vsi =
2157 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2158 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2163 for (i = 0; i < vsi->nb_used_qps; i++) {
2164 if (vsi->nb_msix == 0) {
2165 PMD_DRV_LOG(ERR, "No msix resource");
2167 } else if (nb_msix <= 1) {
2168 if (!rte_intr_allow_others(intr_handle))
2169 /* allow to share MISC_VEC_ID */
2170 msix_vect = I40E_MISC_VEC_ID;
2172 /* no enough msix_vect, map all to one */
2173 __vsi_queues_bind_intr(vsi, msix_vect,
2174 vsi->base_queue + i,
2175 vsi->nb_used_qps - i,
2177 for (; !!record && i < vsi->nb_used_qps; i++)
2178 intr_handle->intr_vec[queue_idx + i] =
2182 /* 1:1 queue/msix_vect mapping */
2183 __vsi_queues_bind_intr(vsi, msix_vect,
2184 vsi->base_queue + i, 1,
2187 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2197 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2199 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2200 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2204 uint16_t msix_intr, i;
2206 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2207 for (i = 0; i < vsi->nb_msix; i++) {
2208 msix_intr = vsi->msix_intr + i;
2209 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2210 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2211 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2212 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2215 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2216 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2217 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2218 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2220 I40E_WRITE_FLUSH(hw);
2224 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2226 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2227 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2229 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2230 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2231 uint16_t msix_intr, i;
2233 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2234 for (i = 0; i < vsi->nb_msix; i++) {
2235 msix_intr = vsi->msix_intr + i;
2236 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2237 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2240 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2241 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2243 I40E_WRITE_FLUSH(hw);
2246 static inline uint8_t
2247 i40e_parse_link_speeds(uint16_t link_speeds)
2249 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2251 if (link_speeds & ETH_LINK_SPEED_40G)
2252 link_speed |= I40E_LINK_SPEED_40GB;
2253 if (link_speeds & ETH_LINK_SPEED_25G)
2254 link_speed |= I40E_LINK_SPEED_25GB;
2255 if (link_speeds & ETH_LINK_SPEED_20G)
2256 link_speed |= I40E_LINK_SPEED_20GB;
2257 if (link_speeds & ETH_LINK_SPEED_10G)
2258 link_speed |= I40E_LINK_SPEED_10GB;
2259 if (link_speeds & ETH_LINK_SPEED_1G)
2260 link_speed |= I40E_LINK_SPEED_1GB;
2261 if (link_speeds & ETH_LINK_SPEED_100M)
2262 link_speed |= I40E_LINK_SPEED_100MB;
2268 i40e_phy_conf_link(struct i40e_hw *hw,
2270 uint8_t force_speed,
2273 enum i40e_status_code status;
2274 struct i40e_aq_get_phy_abilities_resp phy_ab;
2275 struct i40e_aq_set_phy_config phy_conf;
2276 enum i40e_aq_phy_type cnt;
2277 uint8_t avail_speed;
2278 uint32_t phy_type_mask = 0;
2280 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2281 I40E_AQ_PHY_FLAG_PAUSE_RX |
2282 I40E_AQ_PHY_FLAG_PAUSE_RX |
2283 I40E_AQ_PHY_FLAG_LOW_POWER;
2286 /* To get phy capabilities of available speeds. */
2287 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2290 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2294 avail_speed = phy_ab.link_speed;
2296 /* To get the current phy config. */
2297 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2300 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2305 /* If link needs to go up and it is in autoneg mode the speed is OK,
2306 * no need to set up again.
2308 if (is_up && phy_ab.phy_type != 0 &&
2309 abilities & I40E_AQ_PHY_AN_ENABLED &&
2310 phy_ab.link_speed != 0)
2311 return I40E_SUCCESS;
2313 memset(&phy_conf, 0, sizeof(phy_conf));
2315 /* bits 0-2 use the values from get_phy_abilities_resp */
2317 abilities |= phy_ab.abilities & mask;
2319 phy_conf.abilities = abilities;
2321 /* If link needs to go up, but the force speed is not supported,
2322 * Warn users and config the default available speeds.
2324 if (is_up && !(force_speed & avail_speed)) {
2325 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2326 phy_conf.link_speed = avail_speed;
2328 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2331 /* PHY type mask needs to include each type except PHY type extension */
2332 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2333 phy_type_mask |= 1 << cnt;
2335 /* use get_phy_abilities_resp value for the rest */
2336 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2337 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2338 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2339 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2340 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2341 phy_conf.eee_capability = phy_ab.eee_capability;
2342 phy_conf.eeer = phy_ab.eeer_val;
2343 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2345 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2346 phy_ab.abilities, phy_ab.link_speed);
2347 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2348 phy_conf.abilities, phy_conf.link_speed);
2350 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2354 return I40E_SUCCESS;
2358 i40e_apply_link_speed(struct rte_eth_dev *dev)
2361 uint8_t abilities = 0;
2362 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363 struct rte_eth_conf *conf = &dev->data->dev_conf;
2365 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2366 I40E_AQ_PHY_LINK_ENABLED;
2368 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2369 conf->link_speeds = ETH_LINK_SPEED_40G |
2370 ETH_LINK_SPEED_25G |
2371 ETH_LINK_SPEED_20G |
2372 ETH_LINK_SPEED_10G |
2374 ETH_LINK_SPEED_100M;
2376 abilities |= I40E_AQ_PHY_AN_ENABLED;
2378 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2380 speed = i40e_parse_link_speeds(conf->link_speeds);
2382 return i40e_phy_conf_link(hw, abilities, speed, true);
2386 i40e_dev_start(struct rte_eth_dev *dev)
2388 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390 struct i40e_vsi *main_vsi = pf->main_vsi;
2392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2393 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394 uint32_t intr_vector = 0;
2395 struct i40e_vsi *vsi;
2396 uint16_t nb_rxq, nb_txq;
2398 hw->adapter_stopped = 0;
2400 rte_intr_disable(intr_handle);
2402 if ((rte_intr_cap_multiple(intr_handle) ||
2403 !RTE_ETH_DEV_SRIOV(dev).active) &&
2404 dev->data->dev_conf.intr_conf.rxq != 0) {
2405 intr_vector = dev->data->nb_rx_queues;
2406 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2411 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2412 intr_handle->intr_vec =
2413 rte_zmalloc("intr_vec",
2414 dev->data->nb_rx_queues * sizeof(int),
2416 if (!intr_handle->intr_vec) {
2418 "Failed to allocate %d rx_queues intr_vec",
2419 dev->data->nb_rx_queues);
2424 /* Initialize VSI */
2425 ret = i40e_dev_rxtx_init(pf);
2426 if (ret != I40E_SUCCESS) {
2427 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2431 /* Map queues with MSIX interrupt */
2432 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2433 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2434 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2437 i40e_vsi_enable_queues_intr(main_vsi);
2439 /* Map VMDQ VSI queues with MSIX interrupt */
2440 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2441 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2442 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2443 I40E_ITR_INDEX_DEFAULT);
2446 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2449 /* Enable all queues which have been configured */
2450 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2451 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2456 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2457 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2462 /* Enable receiving broadcast packets */
2463 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2464 if (ret != I40E_SUCCESS)
2465 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2467 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2468 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2470 if (ret != I40E_SUCCESS)
2471 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2474 /* Enable the VLAN promiscuous mode. */
2476 for (i = 0; i < pf->vf_num; i++) {
2477 vsi = pf->vfs[i].vsi;
2478 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2483 /* Enable mac loopback mode */
2484 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2485 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2486 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2487 if (ret != I40E_SUCCESS) {
2488 PMD_DRV_LOG(ERR, "fail to set loopback link");
2493 /* Apply link configure */
2494 ret = i40e_apply_link_speed(dev);
2495 if (I40E_SUCCESS != ret) {
2496 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2500 if (!rte_intr_allow_others(intr_handle)) {
2501 rte_intr_callback_unregister(intr_handle,
2502 i40e_dev_interrupt_handler,
2504 /* configure and enable device interrupt */
2505 i40e_pf_config_irq0(hw, FALSE);
2506 i40e_pf_enable_irq0(hw);
2508 if (dev->data->dev_conf.intr_conf.lsc != 0)
2510 "lsc won't enable because of no intr multiplex");
2512 ret = i40e_aq_set_phy_int_mask(hw,
2513 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2514 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2515 I40E_AQ_EVENT_MEDIA_NA), NULL);
2516 if (ret != I40E_SUCCESS)
2517 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2519 /* Call get_link_info aq commond to enable/disable LSE */
2520 i40e_dev_link_update(dev, 0);
2523 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2524 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2525 i40e_dev_alarm_handler, dev);
2527 /* enable uio intr after callback register */
2528 rte_intr_enable(intr_handle);
2531 i40e_filter_restore(pf);
2533 if (pf->tm_conf.root && !pf->tm_conf.committed)
2534 PMD_DRV_LOG(WARNING,
2535 "please call hierarchy_commit() "
2536 "before starting the port");
2538 return I40E_SUCCESS;
2541 for (i = 0; i < nb_txq; i++)
2542 i40e_dev_tx_queue_stop(dev, i);
2544 for (i = 0; i < nb_rxq; i++)
2545 i40e_dev_rx_queue_stop(dev, i);
2551 i40e_dev_stop(struct rte_eth_dev *dev)
2553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555 struct i40e_vsi *main_vsi = pf->main_vsi;
2556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2557 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2560 if (hw->adapter_stopped == 1)
2563 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2564 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2565 rte_intr_enable(intr_handle);
2568 /* Disable all queues */
2569 for (i = 0; i < dev->data->nb_tx_queues; i++)
2570 i40e_dev_tx_queue_stop(dev, i);
2572 for (i = 0; i < dev->data->nb_rx_queues; i++)
2573 i40e_dev_rx_queue_stop(dev, i);
2575 /* un-map queues with interrupt registers */
2576 i40e_vsi_disable_queues_intr(main_vsi);
2577 i40e_vsi_queues_unbind_intr(main_vsi);
2579 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2580 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2581 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2584 /* Clear all queues and release memory */
2585 i40e_dev_clear_queues(dev);
2588 i40e_dev_set_link_down(dev);
2590 if (!rte_intr_allow_others(intr_handle))
2591 /* resume to the default handler */
2592 rte_intr_callback_register(intr_handle,
2593 i40e_dev_interrupt_handler,
2596 /* Clean datapath event and queue/vec mapping */
2597 rte_intr_efd_disable(intr_handle);
2598 if (intr_handle->intr_vec) {
2599 rte_free(intr_handle->intr_vec);
2600 intr_handle->intr_vec = NULL;
2603 /* reset hierarchy commit */
2604 pf->tm_conf.committed = false;
2606 hw->adapter_stopped = 1;
2608 pf->adapter->rss_reta_updated = 0;
2612 i40e_dev_close(struct rte_eth_dev *dev)
2614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2617 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618 struct i40e_mirror_rule *p_mirror;
2619 struct i40e_filter_control_settings settings;
2620 struct rte_flow *p_flow;
2624 uint8_t aq_fail = 0;
2627 PMD_INIT_FUNC_TRACE();
2629 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2631 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2636 /* Remove all mirror rules */
2637 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2638 ret = i40e_aq_del_mirror_rule(hw,
2639 pf->main_vsi->veb->seid,
2640 p_mirror->rule_type,
2642 p_mirror->num_entries,
2645 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2646 "status = %d, aq_err = %d.", ret,
2647 hw->aq.asq_last_status);
2649 /* remove mirror software resource anyway */
2650 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2652 pf->nb_mirror_rule--;
2655 i40e_dev_free_queues(dev);
2657 /* Disable interrupt */
2658 i40e_pf_disable_irq0(hw);
2659 rte_intr_disable(intr_handle);
2662 * Only legacy filter API needs the following fdir config. So when the
2663 * legacy filter API is deprecated, the following code should also be
2666 i40e_fdir_teardown(pf);
2668 /* shutdown and destroy the HMC */
2669 i40e_shutdown_lan_hmc(hw);
2671 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2672 i40e_vsi_release(pf->vmdq[i].vsi);
2673 pf->vmdq[i].vsi = NULL;
2678 /* release all the existing VSIs and VEBs */
2679 i40e_vsi_release(pf->main_vsi);
2681 /* shutdown the adminq */
2682 i40e_aq_queue_shutdown(hw, true);
2683 i40e_shutdown_adminq(hw);
2685 i40e_res_pool_destroy(&pf->qp_pool);
2686 i40e_res_pool_destroy(&pf->msix_pool);
2688 /* Disable flexible payload in global configuration */
2689 if (!pf->support_multi_driver)
2690 i40e_flex_payload_reg_set_default(hw);
2692 /* force a PF reset to clean anything leftover */
2693 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2694 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2695 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2696 I40E_WRITE_FLUSH(hw);
2698 dev->dev_ops = NULL;
2699 dev->rx_pkt_burst = NULL;
2700 dev->tx_pkt_burst = NULL;
2702 /* Clear PXE mode */
2703 i40e_clear_pxe_mode(hw);
2705 /* Unconfigure filter control */
2706 memset(&settings, 0, sizeof(settings));
2707 ret = i40e_set_filter_control(hw, &settings);
2709 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2712 /* Disable flow control */
2713 hw->fc.requested_mode = I40E_FC_NONE;
2714 i40e_set_fc(hw, &aq_fail, TRUE);
2716 /* uninitialize pf host driver */
2717 i40e_pf_host_uninit(dev);
2720 ret = rte_intr_callback_unregister(intr_handle,
2721 i40e_dev_interrupt_handler, dev);
2722 if (ret >= 0 || ret == -ENOENT) {
2724 } else if (ret != -EAGAIN) {
2726 "intr callback unregister failed: %d",
2729 i40e_msec_delay(500);
2730 } while (retries++ < 5);
2732 i40e_rm_ethtype_filter_list(pf);
2733 i40e_rm_tunnel_filter_list(pf);
2734 i40e_rm_fdir_filter_list(pf);
2736 /* Remove all flows */
2737 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2738 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2739 /* Do not free FDIR flows since they are static allocated */
2740 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2744 /* release the fdir static allocated memory */
2745 i40e_fdir_memory_cleanup(pf);
2747 /* Remove all Traffic Manager configuration */
2748 i40e_tm_conf_uninit(dev);
2750 hw->adapter_closed = 1;
2754 * Reset PF device only to re-initialize resources in PMD layer
2757 i40e_dev_reset(struct rte_eth_dev *dev)
2761 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2762 * its VF to make them align with it. The detailed notification
2763 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2764 * To avoid unexpected behavior in VF, currently reset of PF with
2765 * SR-IOV activation is not supported. It might be supported later.
2767 if (dev->data->sriov.active)
2770 ret = eth_i40e_dev_uninit(dev);
2774 ret = eth_i40e_dev_init(dev, NULL);
2780 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 struct i40e_vsi *vsi = pf->main_vsi;
2787 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2789 if (status != I40E_SUCCESS) {
2790 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2794 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2796 if (status != I40E_SUCCESS) {
2797 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2798 /* Rollback unicast promiscuous mode */
2799 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2808 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 struct i40e_vsi *vsi = pf->main_vsi;
2815 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2817 if (status != I40E_SUCCESS) {
2818 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2822 /* must remain in all_multicast mode */
2823 if (dev->data->all_multicast == 1)
2826 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2828 if (status != I40E_SUCCESS) {
2829 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2830 /* Rollback unicast promiscuous mode */
2831 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2840 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2842 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844 struct i40e_vsi *vsi = pf->main_vsi;
2847 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2848 if (ret != I40E_SUCCESS) {
2849 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2857 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2859 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 struct i40e_vsi *vsi = pf->main_vsi;
2864 if (dev->data->promiscuous == 1)
2865 return 0; /* must remain in all_multicast mode */
2867 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2868 vsi->seid, FALSE, NULL);
2869 if (ret != I40E_SUCCESS) {
2870 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2878 * Set device link up.
2881 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2883 /* re-apply link speed setting */
2884 return i40e_apply_link_speed(dev);
2888 * Set device link down.
2891 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2893 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2894 uint8_t abilities = 0;
2895 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2898 return i40e_phy_conf_link(hw, abilities, speed, false);
2901 static __rte_always_inline void
2902 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2904 /* Link status registers and values*/
2905 #define I40E_PRTMAC_LINKSTA 0x001E2420
2906 #define I40E_REG_LINK_UP 0x40000080
2907 #define I40E_PRTMAC_MACC 0x001E24E0
2908 #define I40E_REG_MACC_25GB 0x00020000
2909 #define I40E_REG_SPEED_MASK 0x38000000
2910 #define I40E_REG_SPEED_0 0x00000000
2911 #define I40E_REG_SPEED_1 0x08000000
2912 #define I40E_REG_SPEED_2 0x10000000
2913 #define I40E_REG_SPEED_3 0x18000000
2914 #define I40E_REG_SPEED_4 0x20000000
2915 uint32_t link_speed;
2918 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2919 link_speed = reg_val & I40E_REG_SPEED_MASK;
2920 reg_val &= I40E_REG_LINK_UP;
2921 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2923 if (unlikely(link->link_status == 0))
2926 /* Parse the link status */
2927 switch (link_speed) {
2928 case I40E_REG_SPEED_0:
2929 link->link_speed = ETH_SPEED_NUM_100M;
2931 case I40E_REG_SPEED_1:
2932 link->link_speed = ETH_SPEED_NUM_1G;
2934 case I40E_REG_SPEED_2:
2935 if (hw->mac.type == I40E_MAC_X722)
2936 link->link_speed = ETH_SPEED_NUM_2_5G;
2938 link->link_speed = ETH_SPEED_NUM_10G;
2940 case I40E_REG_SPEED_3:
2941 if (hw->mac.type == I40E_MAC_X722) {
2942 link->link_speed = ETH_SPEED_NUM_5G;
2944 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2946 if (reg_val & I40E_REG_MACC_25GB)
2947 link->link_speed = ETH_SPEED_NUM_25G;
2949 link->link_speed = ETH_SPEED_NUM_40G;
2952 case I40E_REG_SPEED_4:
2953 if (hw->mac.type == I40E_MAC_X722)
2954 link->link_speed = ETH_SPEED_NUM_10G;
2956 link->link_speed = ETH_SPEED_NUM_20G;
2959 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2964 static __rte_always_inline void
2965 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2966 bool enable_lse, int wait_to_complete)
2968 #define CHECK_INTERVAL 100 /* 100ms */
2969 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2970 uint32_t rep_cnt = MAX_REPEAT_TIME;
2971 struct i40e_link_status link_status;
2974 memset(&link_status, 0, sizeof(link_status));
2977 memset(&link_status, 0, sizeof(link_status));
2979 /* Get link status information from hardware */
2980 status = i40e_aq_get_link_info(hw, enable_lse,
2981 &link_status, NULL);
2982 if (unlikely(status != I40E_SUCCESS)) {
2983 link->link_speed = ETH_SPEED_NUM_NONE;
2984 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2985 PMD_DRV_LOG(ERR, "Failed to get link info");
2989 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2990 if (!wait_to_complete || link->link_status)
2993 rte_delay_ms(CHECK_INTERVAL);
2994 } while (--rep_cnt);
2996 /* Parse the link status */
2997 switch (link_status.link_speed) {
2998 case I40E_LINK_SPEED_100MB:
2999 link->link_speed = ETH_SPEED_NUM_100M;
3001 case I40E_LINK_SPEED_1GB:
3002 link->link_speed = ETH_SPEED_NUM_1G;
3004 case I40E_LINK_SPEED_10GB:
3005 link->link_speed = ETH_SPEED_NUM_10G;
3007 case I40E_LINK_SPEED_20GB:
3008 link->link_speed = ETH_SPEED_NUM_20G;
3010 case I40E_LINK_SPEED_25GB:
3011 link->link_speed = ETH_SPEED_NUM_25G;
3013 case I40E_LINK_SPEED_40GB:
3014 link->link_speed = ETH_SPEED_NUM_40G;
3017 link->link_speed = ETH_SPEED_NUM_NONE;
3023 i40e_dev_link_update(struct rte_eth_dev *dev,
3024 int wait_to_complete)
3026 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027 struct rte_eth_link link;
3028 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3031 memset(&link, 0, sizeof(link));
3033 /* i40e uses full duplex only */
3034 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3035 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3036 ETH_LINK_SPEED_FIXED);
3038 if (!wait_to_complete && !enable_lse)
3039 update_link_reg(hw, &link);
3041 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3044 rte_eth_linkstatus_get(hw->switch_dev, &link);
3046 ret = rte_eth_linkstatus_set(dev, &link);
3047 i40e_notify_all_vfs_link_status(dev);
3052 /* Get all the statistics of a VSI */
3054 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3056 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3057 struct i40e_eth_stats *nes = &vsi->eth_stats;
3058 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3059 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3061 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3062 vsi->offset_loaded, &oes->rx_bytes,
3064 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3065 vsi->offset_loaded, &oes->rx_unicast,
3067 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3068 vsi->offset_loaded, &oes->rx_multicast,
3069 &nes->rx_multicast);
3070 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3071 vsi->offset_loaded, &oes->rx_broadcast,
3072 &nes->rx_broadcast);
3073 /* exclude CRC bytes */
3074 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3075 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3077 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3078 &oes->rx_discards, &nes->rx_discards);
3079 /* GLV_REPC not supported */
3080 /* GLV_RMPC not supported */
3081 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3082 &oes->rx_unknown_protocol,
3083 &nes->rx_unknown_protocol);
3084 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3085 vsi->offset_loaded, &oes->tx_bytes,
3087 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3088 vsi->offset_loaded, &oes->tx_unicast,
3090 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3091 vsi->offset_loaded, &oes->tx_multicast,
3092 &nes->tx_multicast);
3093 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3094 vsi->offset_loaded, &oes->tx_broadcast,
3095 &nes->tx_broadcast);
3096 /* GLV_TDPC not supported */
3097 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3098 &oes->tx_errors, &nes->tx_errors);
3099 vsi->offset_loaded = true;
3101 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3103 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3104 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3105 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3106 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3107 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3108 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3109 nes->rx_unknown_protocol);
3110 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3111 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3112 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3113 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3114 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3115 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3116 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3121 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3124 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3125 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3127 /* Get rx/tx bytes of internal transfer packets */
3128 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3129 I40E_GLV_GORCL(hw->port),
3131 &pf->internal_stats_offset.rx_bytes,
3132 &pf->internal_stats.rx_bytes);
3134 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3135 I40E_GLV_GOTCL(hw->port),
3137 &pf->internal_stats_offset.tx_bytes,
3138 &pf->internal_stats.tx_bytes);
3139 /* Get total internal rx packet count */
3140 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3141 I40E_GLV_UPRCL(hw->port),
3143 &pf->internal_stats_offset.rx_unicast,
3144 &pf->internal_stats.rx_unicast);
3145 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3146 I40E_GLV_MPRCL(hw->port),
3148 &pf->internal_stats_offset.rx_multicast,
3149 &pf->internal_stats.rx_multicast);
3150 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3151 I40E_GLV_BPRCL(hw->port),
3153 &pf->internal_stats_offset.rx_broadcast,
3154 &pf->internal_stats.rx_broadcast);
3155 /* Get total internal tx packet count */
3156 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3157 I40E_GLV_UPTCL(hw->port),
3159 &pf->internal_stats_offset.tx_unicast,
3160 &pf->internal_stats.tx_unicast);
3161 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3162 I40E_GLV_MPTCL(hw->port),
3164 &pf->internal_stats_offset.tx_multicast,
3165 &pf->internal_stats.tx_multicast);
3166 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3167 I40E_GLV_BPTCL(hw->port),
3169 &pf->internal_stats_offset.tx_broadcast,
3170 &pf->internal_stats.tx_broadcast);
3172 /* exclude CRC size */
3173 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3174 pf->internal_stats.rx_multicast +
3175 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3177 /* Get statistics of struct i40e_eth_stats */
3178 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3179 I40E_GLPRT_GORCL(hw->port),
3180 pf->offset_loaded, &os->eth.rx_bytes,
3182 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3183 I40E_GLPRT_UPRCL(hw->port),
3184 pf->offset_loaded, &os->eth.rx_unicast,
3185 &ns->eth.rx_unicast);
3186 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3187 I40E_GLPRT_MPRCL(hw->port),
3188 pf->offset_loaded, &os->eth.rx_multicast,
3189 &ns->eth.rx_multicast);
3190 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3191 I40E_GLPRT_BPRCL(hw->port),
3192 pf->offset_loaded, &os->eth.rx_broadcast,
3193 &ns->eth.rx_broadcast);
3194 /* Workaround: CRC size should not be included in byte statistics,
3195 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3198 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3199 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3201 /* exclude internal rx bytes
3202 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3203 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3205 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3207 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3208 ns->eth.rx_bytes = 0;
3210 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3212 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3213 ns->eth.rx_unicast = 0;
3215 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3217 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3218 ns->eth.rx_multicast = 0;
3220 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3222 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3223 ns->eth.rx_broadcast = 0;
3225 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3227 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3228 pf->offset_loaded, &os->eth.rx_discards,
3229 &ns->eth.rx_discards);
3230 /* GLPRT_REPC not supported */
3231 /* GLPRT_RMPC not supported */
3232 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3234 &os->eth.rx_unknown_protocol,
3235 &ns->eth.rx_unknown_protocol);
3236 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3237 I40E_GLPRT_GOTCL(hw->port),
3238 pf->offset_loaded, &os->eth.tx_bytes,
3240 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3241 I40E_GLPRT_UPTCL(hw->port),
3242 pf->offset_loaded, &os->eth.tx_unicast,
3243 &ns->eth.tx_unicast);
3244 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3245 I40E_GLPRT_MPTCL(hw->port),
3246 pf->offset_loaded, &os->eth.tx_multicast,
3247 &ns->eth.tx_multicast);
3248 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3249 I40E_GLPRT_BPTCL(hw->port),
3250 pf->offset_loaded, &os->eth.tx_broadcast,
3251 &ns->eth.tx_broadcast);
3252 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3253 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3255 /* exclude internal tx bytes
3256 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3257 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3259 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3261 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3262 ns->eth.tx_bytes = 0;
3264 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3266 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3267 ns->eth.tx_unicast = 0;
3269 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3271 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3272 ns->eth.tx_multicast = 0;
3274 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3276 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3277 ns->eth.tx_broadcast = 0;
3279 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3281 /* GLPRT_TEPC not supported */
3283 /* additional port specific stats */
3284 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3285 pf->offset_loaded, &os->tx_dropped_link_down,
3286 &ns->tx_dropped_link_down);
3287 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3288 pf->offset_loaded, &os->crc_errors,
3290 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3291 pf->offset_loaded, &os->illegal_bytes,
3292 &ns->illegal_bytes);
3293 /* GLPRT_ERRBC not supported */
3294 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3295 pf->offset_loaded, &os->mac_local_faults,
3296 &ns->mac_local_faults);
3297 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3298 pf->offset_loaded, &os->mac_remote_faults,
3299 &ns->mac_remote_faults);
3300 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3301 pf->offset_loaded, &os->rx_length_errors,
3302 &ns->rx_length_errors);
3303 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3304 pf->offset_loaded, &os->link_xon_rx,
3306 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3307 pf->offset_loaded, &os->link_xoff_rx,
3309 for (i = 0; i < 8; i++) {
3310 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3312 &os->priority_xon_rx[i],
3313 &ns->priority_xon_rx[i]);
3314 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3316 &os->priority_xoff_rx[i],
3317 &ns->priority_xoff_rx[i]);
3319 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3320 pf->offset_loaded, &os->link_xon_tx,
3322 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3323 pf->offset_loaded, &os->link_xoff_tx,
3325 for (i = 0; i < 8; i++) {
3326 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3328 &os->priority_xon_tx[i],
3329 &ns->priority_xon_tx[i]);
3330 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3332 &os->priority_xoff_tx[i],
3333 &ns->priority_xoff_tx[i]);
3334 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3336 &os->priority_xon_2_xoff[i],
3337 &ns->priority_xon_2_xoff[i]);
3339 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3340 I40E_GLPRT_PRC64L(hw->port),
3341 pf->offset_loaded, &os->rx_size_64,
3343 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3344 I40E_GLPRT_PRC127L(hw->port),
3345 pf->offset_loaded, &os->rx_size_127,
3347 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3348 I40E_GLPRT_PRC255L(hw->port),
3349 pf->offset_loaded, &os->rx_size_255,
3351 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3352 I40E_GLPRT_PRC511L(hw->port),
3353 pf->offset_loaded, &os->rx_size_511,
3355 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3356 I40E_GLPRT_PRC1023L(hw->port),
3357 pf->offset_loaded, &os->rx_size_1023,
3359 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3360 I40E_GLPRT_PRC1522L(hw->port),
3361 pf->offset_loaded, &os->rx_size_1522,
3363 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3364 I40E_GLPRT_PRC9522L(hw->port),
3365 pf->offset_loaded, &os->rx_size_big,
3367 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3368 pf->offset_loaded, &os->rx_undersize,
3370 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3371 pf->offset_loaded, &os->rx_fragments,
3373 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3374 pf->offset_loaded, &os->rx_oversize,
3376 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3377 pf->offset_loaded, &os->rx_jabber,
3379 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3380 I40E_GLPRT_PTC64L(hw->port),
3381 pf->offset_loaded, &os->tx_size_64,
3383 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3384 I40E_GLPRT_PTC127L(hw->port),
3385 pf->offset_loaded, &os->tx_size_127,
3387 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3388 I40E_GLPRT_PTC255L(hw->port),
3389 pf->offset_loaded, &os->tx_size_255,
3391 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3392 I40E_GLPRT_PTC511L(hw->port),
3393 pf->offset_loaded, &os->tx_size_511,
3395 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3396 I40E_GLPRT_PTC1023L(hw->port),
3397 pf->offset_loaded, &os->tx_size_1023,
3399 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3400 I40E_GLPRT_PTC1522L(hw->port),
3401 pf->offset_loaded, &os->tx_size_1522,
3403 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3404 I40E_GLPRT_PTC9522L(hw->port),
3405 pf->offset_loaded, &os->tx_size_big,
3407 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3409 &os->fd_sb_match, &ns->fd_sb_match);
3410 /* GLPRT_MSPDC not supported */
3411 /* GLPRT_XEC not supported */
3413 pf->offset_loaded = true;
3416 i40e_update_vsi_stats(pf->main_vsi);
3419 /* Get all statistics of a port */
3421 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3423 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3424 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3426 struct i40e_vsi *vsi;
3429 /* call read registers - updates values, now write them to struct */
3430 i40e_read_stats_registers(pf, hw);
3432 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3433 pf->main_vsi->eth_stats.rx_multicast +
3434 pf->main_vsi->eth_stats.rx_broadcast -
3435 pf->main_vsi->eth_stats.rx_discards;
3436 stats->opackets = ns->eth.tx_unicast +
3437 ns->eth.tx_multicast +
3438 ns->eth.tx_broadcast;
3439 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3440 stats->obytes = ns->eth.tx_bytes;
3441 stats->oerrors = ns->eth.tx_errors +
3442 pf->main_vsi->eth_stats.tx_errors;
3445 stats->imissed = ns->eth.rx_discards +
3446 pf->main_vsi->eth_stats.rx_discards;
3447 stats->ierrors = ns->crc_errors +
3448 ns->rx_length_errors + ns->rx_undersize +
3449 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3452 for (i = 0; i < pf->vf_num; i++) {
3453 vsi = pf->vfs[i].vsi;
3454 i40e_update_vsi_stats(vsi);
3456 stats->ipackets += (vsi->eth_stats.rx_unicast +
3457 vsi->eth_stats.rx_multicast +
3458 vsi->eth_stats.rx_broadcast -
3459 vsi->eth_stats.rx_discards);
3460 stats->ibytes += vsi->eth_stats.rx_bytes;
3461 stats->oerrors += vsi->eth_stats.tx_errors;
3462 stats->imissed += vsi->eth_stats.rx_discards;
3466 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3467 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3468 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3469 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3470 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3471 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3472 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3473 ns->eth.rx_unknown_protocol);
3474 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3475 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3476 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3477 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3478 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3479 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3481 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3482 ns->tx_dropped_link_down);
3483 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3484 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3486 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3487 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3488 ns->mac_local_faults);
3489 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3490 ns->mac_remote_faults);
3491 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3492 ns->rx_length_errors);
3493 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3494 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3495 for (i = 0; i < 8; i++) {
3496 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3497 i, ns->priority_xon_rx[i]);
3498 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3499 i, ns->priority_xoff_rx[i]);
3501 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3502 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3503 for (i = 0; i < 8; i++) {
3504 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3505 i, ns->priority_xon_tx[i]);
3506 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3507 i, ns->priority_xoff_tx[i]);
3508 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3509 i, ns->priority_xon_2_xoff[i]);
3511 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3512 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3513 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3514 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3515 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3516 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3517 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3518 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3519 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3520 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3521 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3522 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3523 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3524 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3525 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3526 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3527 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3528 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3529 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3530 ns->mac_short_packet_dropped);
3531 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3532 ns->checksum_error);
3533 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3534 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3538 /* Reset the statistics */
3540 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3542 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3543 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3545 /* Mark PF and VSI stats to update the offset, aka "reset" */
3546 pf->offset_loaded = false;
3548 pf->main_vsi->offset_loaded = false;
3550 /* read the stats, reading current register values into offset */
3551 i40e_read_stats_registers(pf, hw);
3557 i40e_xstats_calc_num(void)
3559 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3560 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3561 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3564 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3565 struct rte_eth_xstat_name *xstats_names,
3566 __rte_unused unsigned limit)
3571 if (xstats_names == NULL)
3572 return i40e_xstats_calc_num();
3574 /* Note: limit checked in rte_eth_xstats_names() */
3576 /* Get stats from i40e_eth_stats struct */
3577 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3578 strlcpy(xstats_names[count].name,
3579 rte_i40e_stats_strings[i].name,
3580 sizeof(xstats_names[count].name));
3584 /* Get individiual stats from i40e_hw_port struct */
3585 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3586 strlcpy(xstats_names[count].name,
3587 rte_i40e_hw_port_strings[i].name,
3588 sizeof(xstats_names[count].name));
3592 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3593 for (prio = 0; prio < 8; prio++) {
3594 snprintf(xstats_names[count].name,
3595 sizeof(xstats_names[count].name),
3596 "rx_priority%u_%s", prio,
3597 rte_i40e_rxq_prio_strings[i].name);
3602 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3603 for (prio = 0; prio < 8; prio++) {
3604 snprintf(xstats_names[count].name,
3605 sizeof(xstats_names[count].name),
3606 "tx_priority%u_%s", prio,
3607 rte_i40e_txq_prio_strings[i].name);
3615 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3618 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3619 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620 unsigned i, count, prio;
3621 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3623 count = i40e_xstats_calc_num();
3627 i40e_read_stats_registers(pf, hw);
3634 /* Get stats from i40e_eth_stats struct */
3635 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3636 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3637 rte_i40e_stats_strings[i].offset);
3638 xstats[count].id = count;
3642 /* Get individiual stats from i40e_hw_port struct */
3643 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3644 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3645 rte_i40e_hw_port_strings[i].offset);
3646 xstats[count].id = count;
3650 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3651 for (prio = 0; prio < 8; prio++) {
3652 xstats[count].value =
3653 *(uint64_t *)(((char *)hw_stats) +
3654 rte_i40e_rxq_prio_strings[i].offset +
3655 (sizeof(uint64_t) * prio));
3656 xstats[count].id = count;
3661 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3662 for (prio = 0; prio < 8; prio++) {
3663 xstats[count].value =
3664 *(uint64_t *)(((char *)hw_stats) +
3665 rte_i40e_txq_prio_strings[i].offset +
3666 (sizeof(uint64_t) * prio));
3667 xstats[count].id = count;
3676 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3678 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3684 full_ver = hw->nvm.oem_ver;
3685 ver = (u8)(full_ver >> 24);
3686 build = (u16)((full_ver >> 8) & 0xffff);
3687 patch = (u8)(full_ver & 0xff);
3689 ret = snprintf(fw_version, fw_size,
3690 "%d.%d%d 0x%08x %d.%d.%d",
3691 ((hw->nvm.version >> 12) & 0xf),
3692 ((hw->nvm.version >> 4) & 0xff),
3693 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3696 ret += 1; /* add the size of '\0' */
3697 if (fw_size < (u32)ret)
3704 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3705 * the Rx data path does not hang if the FW LLDP is stopped.
3706 * return true if lldp need to stop
3707 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3710 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3713 char ver_str[64] = {0};
3714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 i40e_fw_version_get(dev, ver_str, 64);
3717 nvm_ver = atof(ver_str);
3718 if ((hw->mac.type == I40E_MAC_X722 ||
3719 hw->mac.type == I40E_MAC_X722_VF) &&
3720 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3722 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3729 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3731 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733 struct i40e_vsi *vsi = pf->main_vsi;
3734 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3736 dev_info->max_rx_queues = vsi->nb_qps;
3737 dev_info->max_tx_queues = vsi->nb_qps;
3738 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3739 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3740 dev_info->max_mac_addrs = vsi->max_macaddrs;
3741 dev_info->max_vfs = pci_dev->max_vfs;
3742 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3743 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3744 dev_info->rx_queue_offload_capa = 0;
3745 dev_info->rx_offload_capa =
3746 DEV_RX_OFFLOAD_VLAN_STRIP |
3747 DEV_RX_OFFLOAD_QINQ_STRIP |
3748 DEV_RX_OFFLOAD_IPV4_CKSUM |
3749 DEV_RX_OFFLOAD_UDP_CKSUM |
3750 DEV_RX_OFFLOAD_TCP_CKSUM |
3751 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3752 DEV_RX_OFFLOAD_KEEP_CRC |
3753 DEV_RX_OFFLOAD_SCATTER |
3754 DEV_RX_OFFLOAD_VLAN_EXTEND |
3755 DEV_RX_OFFLOAD_VLAN_FILTER |
3756 DEV_RX_OFFLOAD_JUMBO_FRAME |
3757 DEV_RX_OFFLOAD_RSS_HASH;
3759 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3760 dev_info->tx_offload_capa =
3761 DEV_TX_OFFLOAD_VLAN_INSERT |
3762 DEV_TX_OFFLOAD_QINQ_INSERT |
3763 DEV_TX_OFFLOAD_IPV4_CKSUM |
3764 DEV_TX_OFFLOAD_UDP_CKSUM |
3765 DEV_TX_OFFLOAD_TCP_CKSUM |
3766 DEV_TX_OFFLOAD_SCTP_CKSUM |
3767 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3768 DEV_TX_OFFLOAD_TCP_TSO |
3769 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3770 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3771 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3772 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3773 DEV_TX_OFFLOAD_MULTI_SEGS |
3774 dev_info->tx_queue_offload_capa;
3775 dev_info->dev_capa =
3776 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3777 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3779 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3781 dev_info->reta_size = pf->hash_lut_size;
3782 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3784 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3786 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3787 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3788 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3790 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3795 dev_info->default_txconf = (struct rte_eth_txconf) {
3797 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3798 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3799 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3801 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3802 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3806 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3807 .nb_max = I40E_MAX_RING_DESC,
3808 .nb_min = I40E_MIN_RING_DESC,
3809 .nb_align = I40E_ALIGN_RING_DESC,
3812 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3813 .nb_max = I40E_MAX_RING_DESC,
3814 .nb_min = I40E_MIN_RING_DESC,
3815 .nb_align = I40E_ALIGN_RING_DESC,
3816 .nb_seg_max = I40E_TX_MAX_SEG,
3817 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3820 if (pf->flags & I40E_FLAG_VMDQ) {
3821 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3822 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3823 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3824 pf->max_nb_vmdq_vsi;
3825 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3826 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3827 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3830 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3832 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3833 dev_info->default_rxportconf.nb_queues = 2;
3834 dev_info->default_txportconf.nb_queues = 2;
3835 if (dev->data->nb_rx_queues == 1)
3836 dev_info->default_rxportconf.ring_size = 2048;
3838 dev_info->default_rxportconf.ring_size = 1024;
3839 if (dev->data->nb_tx_queues == 1)
3840 dev_info->default_txportconf.ring_size = 1024;
3842 dev_info->default_txportconf.ring_size = 512;
3844 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3846 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3847 dev_info->default_rxportconf.nb_queues = 1;
3848 dev_info->default_txportconf.nb_queues = 1;
3849 dev_info->default_rxportconf.ring_size = 256;
3850 dev_info->default_txportconf.ring_size = 256;
3853 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3854 dev_info->default_rxportconf.nb_queues = 1;
3855 dev_info->default_txportconf.nb_queues = 1;
3856 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3857 dev_info->default_rxportconf.ring_size = 512;
3858 dev_info->default_txportconf.ring_size = 256;
3860 dev_info->default_rxportconf.ring_size = 256;
3861 dev_info->default_txportconf.ring_size = 256;
3864 dev_info->default_rxportconf.burst_size = 32;
3865 dev_info->default_txportconf.burst_size = 32;
3871 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3873 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3874 struct i40e_vsi *vsi = pf->main_vsi;
3875 PMD_INIT_FUNC_TRACE();
3878 return i40e_vsi_add_vlan(vsi, vlan_id);
3880 return i40e_vsi_delete_vlan(vsi, vlan_id);
3884 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3885 enum rte_vlan_type vlan_type,
3886 uint16_t tpid, int qinq)
3888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3891 uint16_t reg_id = 3;
3895 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3899 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3901 if (ret != I40E_SUCCESS) {
3903 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3908 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3911 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3912 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3913 if (reg_r == reg_w) {
3914 PMD_DRV_LOG(DEBUG, "No need to write");
3918 ret = i40e_aq_debug_write_global_register(hw,
3919 I40E_GL_SWT_L2TAGCTRL(reg_id),
3921 if (ret != I40E_SUCCESS) {
3923 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3928 "Global register 0x%08x is changed with value 0x%08x",
3929 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3935 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3936 enum rte_vlan_type vlan_type,
3939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3941 int qinq = dev->data->dev_conf.rxmode.offloads &
3942 DEV_RX_OFFLOAD_VLAN_EXTEND;
3945 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3946 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3947 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3949 "Unsupported vlan type.");
3953 if (pf->support_multi_driver) {
3954 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3958 /* 802.1ad frames ability is added in NVM API 1.7*/
3959 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3961 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3962 hw->first_tag = rte_cpu_to_le_16(tpid);
3963 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3964 hw->second_tag = rte_cpu_to_le_16(tpid);
3966 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3967 hw->second_tag = rte_cpu_to_le_16(tpid);
3969 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3970 if (ret != I40E_SUCCESS) {
3972 "Set switch config failed aq_err: %d",
3973 hw->aq.asq_last_status);
3977 /* If NVM API < 1.7, keep the register setting */
3978 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3985 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3987 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3988 struct i40e_vsi *vsi = pf->main_vsi;
3989 struct rte_eth_rxmode *rxmode;
3991 rxmode = &dev->data->dev_conf.rxmode;
3992 if (mask & ETH_VLAN_FILTER_MASK) {
3993 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3994 i40e_vsi_config_vlan_filter(vsi, TRUE);
3996 i40e_vsi_config_vlan_filter(vsi, FALSE);
3999 if (mask & ETH_VLAN_STRIP_MASK) {
4000 /* Enable or disable VLAN stripping */
4001 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4002 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4004 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4007 if (mask & ETH_VLAN_EXTEND_MASK) {
4008 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4009 i40e_vsi_config_double_vlan(vsi, TRUE);
4010 /* Set global registers with default ethertype. */
4011 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4012 RTE_ETHER_TYPE_VLAN);
4013 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4014 RTE_ETHER_TYPE_VLAN);
4017 i40e_vsi_config_double_vlan(vsi, FALSE);
4024 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4025 __rte_unused uint16_t queue,
4026 __rte_unused int on)
4028 PMD_INIT_FUNC_TRACE();
4032 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4034 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4035 struct i40e_vsi *vsi = pf->main_vsi;
4036 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4037 struct i40e_vsi_vlan_pvid_info info;
4039 memset(&info, 0, sizeof(info));
4042 info.config.pvid = pvid;
4044 info.config.reject.tagged =
4045 data->dev_conf.txmode.hw_vlan_reject_tagged;
4046 info.config.reject.untagged =
4047 data->dev_conf.txmode.hw_vlan_reject_untagged;
4050 return i40e_vsi_vlan_pvid_set(vsi, &info);
4054 i40e_dev_led_on(struct rte_eth_dev *dev)
4056 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4057 uint32_t mode = i40e_led_get(hw);
4060 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4066 i40e_dev_led_off(struct rte_eth_dev *dev)
4068 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069 uint32_t mode = i40e_led_get(hw);
4072 i40e_led_set(hw, 0, false);
4078 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4080 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4083 fc_conf->pause_time = pf->fc_conf.pause_time;
4085 /* read out from register, in case they are modified by other port */
4086 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4087 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4088 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4089 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4091 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4092 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4094 /* Return current mode according to actual setting*/
4095 switch (hw->fc.current_mode) {
4097 fc_conf->mode = RTE_FC_FULL;
4099 case I40E_FC_TX_PAUSE:
4100 fc_conf->mode = RTE_FC_TX_PAUSE;
4102 case I40E_FC_RX_PAUSE:
4103 fc_conf->mode = RTE_FC_RX_PAUSE;
4107 fc_conf->mode = RTE_FC_NONE;
4114 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4116 uint32_t mflcn_reg, fctrl_reg, reg;
4117 uint32_t max_high_water;
4118 uint8_t i, aq_failure;
4122 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4123 [RTE_FC_NONE] = I40E_FC_NONE,
4124 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4125 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4126 [RTE_FC_FULL] = I40E_FC_FULL
4129 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4131 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4132 if ((fc_conf->high_water > max_high_water) ||
4133 (fc_conf->high_water < fc_conf->low_water)) {
4135 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4140 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4142 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4144 pf->fc_conf.pause_time = fc_conf->pause_time;
4145 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4146 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4148 PMD_INIT_FUNC_TRACE();
4150 /* All the link flow control related enable/disable register
4151 * configuration is handle by the F/W
4153 err = i40e_set_fc(hw, &aq_failure, true);
4157 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4158 /* Configure flow control refresh threshold,
4159 * the value for stat_tx_pause_refresh_timer[8]
4160 * is used for global pause operation.
4164 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4165 pf->fc_conf.pause_time);
4167 /* configure the timer value included in transmitted pause
4169 * the value for stat_tx_pause_quanta[8] is used for global
4172 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4173 pf->fc_conf.pause_time);
4175 fctrl_reg = I40E_READ_REG(hw,
4176 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4178 if (fc_conf->mac_ctrl_frame_fwd != 0)
4179 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4181 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4183 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4186 /* Configure pause time (2 TCs per register) */
4187 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4188 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4189 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4191 /* Configure flow control refresh threshold value */
4192 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4193 pf->fc_conf.pause_time / 2);
4195 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4197 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4198 *depending on configuration
4200 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4201 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4202 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4204 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4205 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4208 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4211 if (!pf->support_multi_driver) {
4212 /* config water marker both based on the packets and bytes */
4213 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4214 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4215 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4216 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4217 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4218 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4219 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4220 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4222 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4223 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4227 "Water marker configuration is not supported.");
4230 I40E_WRITE_FLUSH(hw);
4236 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4237 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4239 PMD_INIT_FUNC_TRACE();
4244 /* Add a MAC address, and update filters */
4246 i40e_macaddr_add(struct rte_eth_dev *dev,
4247 struct rte_ether_addr *mac_addr,
4248 __rte_unused uint32_t index,
4251 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4252 struct i40e_mac_filter_info mac_filter;
4253 struct i40e_vsi *vsi;
4254 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4257 /* If VMDQ not enabled or configured, return */
4258 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4259 !pf->nb_cfg_vmdq_vsi)) {
4260 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4261 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4266 if (pool > pf->nb_cfg_vmdq_vsi) {
4267 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4268 pool, pf->nb_cfg_vmdq_vsi);
4272 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4273 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4274 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4276 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4281 vsi = pf->vmdq[pool - 1].vsi;
4283 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4284 if (ret != I40E_SUCCESS) {
4285 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4291 /* Remove a MAC address, and update filters */
4293 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4296 struct i40e_vsi *vsi;
4297 struct rte_eth_dev_data *data = dev->data;
4298 struct rte_ether_addr *macaddr;
4303 macaddr = &(data->mac_addrs[index]);
4305 pool_sel = dev->data->mac_pool_sel[index];
4307 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4308 if (pool_sel & (1ULL << i)) {
4312 /* No VMDQ pool enabled or configured */
4313 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4314 (i > pf->nb_cfg_vmdq_vsi)) {
4316 "No VMDQ pool enabled/configured");
4319 vsi = pf->vmdq[i - 1].vsi;
4321 ret = i40e_vsi_delete_mac(vsi, macaddr);
4324 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4331 /* Set perfect match or hash match of MAC and VLAN for a VF */
4333 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4334 struct rte_eth_mac_filter *filter,
4338 struct i40e_mac_filter_info mac_filter;
4339 struct rte_ether_addr old_mac;
4340 struct rte_ether_addr *new_mac;
4341 struct i40e_pf_vf *vf = NULL;
4346 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4349 hw = I40E_PF_TO_HW(pf);
4351 if (filter == NULL) {
4352 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4356 new_mac = &filter->mac_addr;
4358 if (rte_is_zero_ether_addr(new_mac)) {
4359 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4363 vf_id = filter->dst_id;
4365 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4366 PMD_DRV_LOG(ERR, "Invalid argument.");
4369 vf = &pf->vfs[vf_id];
4371 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4372 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4377 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4378 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4379 RTE_ETHER_ADDR_LEN);
4380 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4381 RTE_ETHER_ADDR_LEN);
4383 mac_filter.filter_type = filter->filter_type;
4384 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4385 if (ret != I40E_SUCCESS) {
4386 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4389 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4391 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4392 RTE_ETHER_ADDR_LEN);
4393 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4394 if (ret != I40E_SUCCESS) {
4395 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4399 /* Clear device address as it has been removed */
4400 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4401 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4407 /* MAC filter handle */
4409 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4412 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4413 struct rte_eth_mac_filter *filter;
4414 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4415 int ret = I40E_NOT_SUPPORTED;
4417 filter = (struct rte_eth_mac_filter *)(arg);
4419 switch (filter_op) {
4420 case RTE_ETH_FILTER_NOP:
4423 case RTE_ETH_FILTER_ADD:
4424 i40e_pf_disable_irq0(hw);
4426 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4427 i40e_pf_enable_irq0(hw);
4429 case RTE_ETH_FILTER_DELETE:
4430 i40e_pf_disable_irq0(hw);
4432 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4433 i40e_pf_enable_irq0(hw);
4436 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4437 ret = I40E_ERR_PARAM;
4445 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4447 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4448 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4455 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4456 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4457 vsi->type != I40E_VSI_SRIOV,
4460 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4464 uint32_t *lut_dw = (uint32_t *)lut;
4465 uint16_t i, lut_size_dw = lut_size / 4;
4467 if (vsi->type == I40E_VSI_SRIOV) {
4468 for (i = 0; i <= lut_size_dw; i++) {
4469 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4470 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4473 for (i = 0; i < lut_size_dw; i++)
4474 lut_dw[i] = I40E_READ_REG(hw,
4483 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4492 pf = I40E_VSI_TO_PF(vsi);
4493 hw = I40E_VSI_TO_HW(vsi);
4495 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4496 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4497 vsi->type != I40E_VSI_SRIOV,
4500 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4504 uint32_t *lut_dw = (uint32_t *)lut;
4505 uint16_t i, lut_size_dw = lut_size / 4;
4507 if (vsi->type == I40E_VSI_SRIOV) {
4508 for (i = 0; i < lut_size_dw; i++)
4511 I40E_VFQF_HLUT1(i, vsi->user_param),
4514 for (i = 0; i < lut_size_dw; i++)
4515 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4518 I40E_WRITE_FLUSH(hw);
4525 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4526 struct rte_eth_rss_reta_entry64 *reta_conf,
4529 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4530 uint16_t i, lut_size = pf->hash_lut_size;
4531 uint16_t idx, shift;
4535 if (reta_size != lut_size ||
4536 reta_size > ETH_RSS_RETA_SIZE_512) {
4538 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4539 reta_size, lut_size);
4543 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4545 PMD_DRV_LOG(ERR, "No memory can be allocated");
4548 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4551 for (i = 0; i < reta_size; i++) {
4552 idx = i / RTE_RETA_GROUP_SIZE;
4553 shift = i % RTE_RETA_GROUP_SIZE;
4554 if (reta_conf[idx].mask & (1ULL << shift))
4555 lut[i] = reta_conf[idx].reta[shift];
4557 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4559 pf->adapter->rss_reta_updated = 1;
4568 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4569 struct rte_eth_rss_reta_entry64 *reta_conf,
4572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4573 uint16_t i, lut_size = pf->hash_lut_size;
4574 uint16_t idx, shift;
4578 if (reta_size != lut_size ||
4579 reta_size > ETH_RSS_RETA_SIZE_512) {
4581 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4582 reta_size, lut_size);
4586 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4588 PMD_DRV_LOG(ERR, "No memory can be allocated");
4592 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4595 for (i = 0; i < reta_size; i++) {
4596 idx = i / RTE_RETA_GROUP_SIZE;
4597 shift = i % RTE_RETA_GROUP_SIZE;
4598 if (reta_conf[idx].mask & (1ULL << shift))
4599 reta_conf[idx].reta[shift] = lut[i];
4609 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4610 * @hw: pointer to the HW structure
4611 * @mem: pointer to mem struct to fill out
4612 * @size: size of memory requested
4613 * @alignment: what to align the allocation to
4615 enum i40e_status_code
4616 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4617 struct i40e_dma_mem *mem,
4621 const struct rte_memzone *mz = NULL;
4622 char z_name[RTE_MEMZONE_NAMESIZE];
4625 return I40E_ERR_PARAM;
4627 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4628 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4629 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4631 return I40E_ERR_NO_MEMORY;
4636 mem->zone = (const void *)mz;
4638 "memzone %s allocated with physical address: %"PRIu64,
4641 return I40E_SUCCESS;
4645 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4646 * @hw: pointer to the HW structure
4647 * @mem: ptr to mem struct to free
4649 enum i40e_status_code
4650 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4651 struct i40e_dma_mem *mem)
4654 return I40E_ERR_PARAM;
4657 "memzone %s to be freed with physical address: %"PRIu64,
4658 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4659 rte_memzone_free((const struct rte_memzone *)mem->zone);
4664 return I40E_SUCCESS;
4668 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4669 * @hw: pointer to the HW structure
4670 * @mem: pointer to mem struct to fill out
4671 * @size: size of memory requested
4673 enum i40e_status_code
4674 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4675 struct i40e_virt_mem *mem,
4679 return I40E_ERR_PARAM;
4682 mem->va = rte_zmalloc("i40e", size, 0);
4685 return I40E_SUCCESS;
4687 return I40E_ERR_NO_MEMORY;
4691 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4692 * @hw: pointer to the HW structure
4693 * @mem: pointer to mem struct to free
4695 enum i40e_status_code
4696 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4697 struct i40e_virt_mem *mem)
4700 return I40E_ERR_PARAM;
4705 return I40E_SUCCESS;
4709 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4711 rte_spinlock_init(&sp->spinlock);
4715 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4717 rte_spinlock_lock(&sp->spinlock);
4721 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4723 rte_spinlock_unlock(&sp->spinlock);
4727 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4733 * Get the hardware capabilities, which will be parsed
4734 * and saved into struct i40e_hw.
4737 i40e_get_cap(struct i40e_hw *hw)
4739 struct i40e_aqc_list_capabilities_element_resp *buf;
4740 uint16_t len, size = 0;
4743 /* Calculate a huge enough buff for saving response data temporarily */
4744 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4745 I40E_MAX_CAP_ELE_NUM;
4746 buf = rte_zmalloc("i40e", len, 0);
4748 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4749 return I40E_ERR_NO_MEMORY;
4752 /* Get, parse the capabilities and save it to hw */
4753 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4754 i40e_aqc_opc_list_func_capabilities, NULL);
4755 if (ret != I40E_SUCCESS)
4756 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4758 /* Free the temporary buffer after being used */
4764 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4766 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4774 pf = (struct i40e_pf *)opaque;
4778 num = strtoul(value, &end, 0);
4779 if (errno != 0 || end == value || *end != 0) {
4780 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4781 "kept the value = %hu", value, pf->vf_nb_qp_max);
4785 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4786 pf->vf_nb_qp_max = (uint16_t)num;
4788 /* here return 0 to make next valid same argument work */
4789 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4790 "power of 2 and equal or less than 16 !, Now it is "
4791 "kept the value = %hu", num, pf->vf_nb_qp_max);
4796 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4799 struct rte_kvargs *kvlist;
4802 /* set default queue number per VF as 4 */
4803 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4805 if (dev->device->devargs == NULL)
4808 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4812 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4813 if (!kvargs_count) {
4814 rte_kvargs_free(kvlist);
4818 if (kvargs_count > 1)
4819 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4820 "the first invalid or last valid one is used !",
4821 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4823 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4824 i40e_pf_parse_vf_queue_number_handler, pf);
4826 rte_kvargs_free(kvlist);
4832 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4834 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4835 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4836 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4837 uint16_t qp_count = 0, vsi_count = 0;
4839 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4840 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4844 i40e_pf_config_vf_rxq_number(dev);
4846 /* Add the parameter init for LFC */
4847 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4848 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4849 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4851 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4852 pf->max_num_vsi = hw->func_caps.num_vsis;
4853 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4854 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4856 /* FDir queue/VSI allocation */
4857 pf->fdir_qp_offset = 0;
4858 if (hw->func_caps.fd) {
4859 pf->flags |= I40E_FLAG_FDIR;
4860 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4862 pf->fdir_nb_qps = 0;
4864 qp_count += pf->fdir_nb_qps;
4867 /* LAN queue/VSI allocation */
4868 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4869 if (!hw->func_caps.rss) {
4872 pf->flags |= I40E_FLAG_RSS;
4873 if (hw->mac.type == I40E_MAC_X722)
4874 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4875 pf->lan_nb_qps = pf->lan_nb_qp_max;
4877 qp_count += pf->lan_nb_qps;
4880 /* VF queue/VSI allocation */
4881 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4882 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4883 pf->flags |= I40E_FLAG_SRIOV;
4884 pf->vf_nb_qps = pf->vf_nb_qp_max;
4885 pf->vf_num = pci_dev->max_vfs;
4887 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4888 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4893 qp_count += pf->vf_nb_qps * pf->vf_num;
4894 vsi_count += pf->vf_num;
4896 /* VMDq queue/VSI allocation */
4897 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4898 pf->vmdq_nb_qps = 0;
4899 pf->max_nb_vmdq_vsi = 0;
4900 if (hw->func_caps.vmdq) {
4901 if (qp_count < hw->func_caps.num_tx_qp &&
4902 vsi_count < hw->func_caps.num_vsis) {
4903 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4904 qp_count) / pf->vmdq_nb_qp_max;
4906 /* Limit the maximum number of VMDq vsi to the maximum
4907 * ethdev can support
4909 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4910 hw->func_caps.num_vsis - vsi_count);
4911 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4913 if (pf->max_nb_vmdq_vsi) {
4914 pf->flags |= I40E_FLAG_VMDQ;
4915 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4917 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4918 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4919 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4922 "No enough queues left for VMDq");
4925 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4928 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4929 vsi_count += pf->max_nb_vmdq_vsi;
4931 if (hw->func_caps.dcb)
4932 pf->flags |= I40E_FLAG_DCB;
4934 if (qp_count > hw->func_caps.num_tx_qp) {
4936 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4937 qp_count, hw->func_caps.num_tx_qp);
4940 if (vsi_count > hw->func_caps.num_vsis) {
4942 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4943 vsi_count, hw->func_caps.num_vsis);
4951 i40e_pf_get_switch_config(struct i40e_pf *pf)
4953 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4954 struct i40e_aqc_get_switch_config_resp *switch_config;
4955 struct i40e_aqc_switch_config_element_resp *element;
4956 uint16_t start_seid = 0, num_reported;
4959 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4960 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4961 if (!switch_config) {
4962 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4966 /* Get the switch configurations */
4967 ret = i40e_aq_get_switch_config(hw, switch_config,
4968 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4969 if (ret != I40E_SUCCESS) {
4970 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4973 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4974 if (num_reported != 1) { /* The number should be 1 */
4975 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4979 /* Parse the switch configuration elements */
4980 element = &(switch_config->element[0]);
4981 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4982 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4983 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4985 PMD_DRV_LOG(INFO, "Unknown element type");
4988 rte_free(switch_config);
4994 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4997 struct pool_entry *entry;
4999 if (pool == NULL || num == 0)
5002 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5003 if (entry == NULL) {
5004 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5008 /* queue heap initialize */
5009 pool->num_free = num;
5010 pool->num_alloc = 0;
5012 LIST_INIT(&pool->alloc_list);
5013 LIST_INIT(&pool->free_list);
5015 /* Initialize element */
5019 LIST_INSERT_HEAD(&pool->free_list, entry, next);
5024 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5026 struct pool_entry *entry, *next_entry;
5031 for (entry = LIST_FIRST(&pool->alloc_list);
5032 entry && (next_entry = LIST_NEXT(entry, next), 1);
5033 entry = next_entry) {
5034 LIST_REMOVE(entry, next);
5038 for (entry = LIST_FIRST(&pool->free_list);
5039 entry && (next_entry = LIST_NEXT(entry, next), 1);
5040 entry = next_entry) {
5041 LIST_REMOVE(entry, next);
5046 pool->num_alloc = 0;
5048 LIST_INIT(&pool->alloc_list);
5049 LIST_INIT(&pool->free_list);
5053 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5056 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5057 uint32_t pool_offset;
5062 PMD_DRV_LOG(ERR, "Invalid parameter");
5066 pool_offset = base - pool->base;
5067 /* Lookup in alloc list */
5068 LIST_FOREACH(entry, &pool->alloc_list, next) {
5069 if (entry->base == pool_offset) {
5070 valid_entry = entry;
5071 LIST_REMOVE(entry, next);
5076 /* Not find, return */
5077 if (valid_entry == NULL) {
5078 PMD_DRV_LOG(ERR, "Failed to find entry");
5083 * Found it, move it to free list and try to merge.
5084 * In order to make merge easier, always sort it by qbase.
5085 * Find adjacent prev and last entries.
5088 LIST_FOREACH(entry, &pool->free_list, next) {
5089 if (entry->base > valid_entry->base) {
5097 len = valid_entry->len;
5098 /* Try to merge with next one*/
5100 /* Merge with next one */
5101 if (valid_entry->base + len == next->base) {
5102 next->base = valid_entry->base;
5104 rte_free(valid_entry);
5111 /* Merge with previous one */
5112 if (prev->base + prev->len == valid_entry->base) {
5114 /* If it merge with next one, remove next node */
5116 LIST_REMOVE(valid_entry, next);
5117 rte_free(valid_entry);
5120 rte_free(valid_entry);
5127 /* Not find any entry to merge, insert */
5130 LIST_INSERT_AFTER(prev, valid_entry, next);
5131 else if (next != NULL)
5132 LIST_INSERT_BEFORE(next, valid_entry, next);
5133 else /* It's empty list, insert to head */
5134 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5137 pool->num_free += len;
5138 pool->num_alloc -= len;
5144 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5147 struct pool_entry *entry, *valid_entry;
5149 if (pool == NULL || num == 0) {
5150 PMD_DRV_LOG(ERR, "Invalid parameter");
5154 if (pool->num_free < num) {
5155 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5156 num, pool->num_free);
5161 /* Lookup in free list and find most fit one */
5162 LIST_FOREACH(entry, &pool->free_list, next) {
5163 if (entry->len >= num) {
5165 if (entry->len == num) {
5166 valid_entry = entry;
5169 if (valid_entry == NULL || valid_entry->len > entry->len)
5170 valid_entry = entry;
5174 /* Not find one to satisfy the request, return */
5175 if (valid_entry == NULL) {
5176 PMD_DRV_LOG(ERR, "No valid entry found");
5180 * The entry have equal queue number as requested,
5181 * remove it from alloc_list.
5183 if (valid_entry->len == num) {
5184 LIST_REMOVE(valid_entry, next);
5187 * The entry have more numbers than requested,
5188 * create a new entry for alloc_list and minus its
5189 * queue base and number in free_list.
5191 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5192 if (entry == NULL) {
5194 "Failed to allocate memory for resource pool");
5197 entry->base = valid_entry->base;
5199 valid_entry->base += num;
5200 valid_entry->len -= num;
5201 valid_entry = entry;
5204 /* Insert it into alloc list, not sorted */
5205 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5207 pool->num_free -= valid_entry->len;
5208 pool->num_alloc += valid_entry->len;
5210 return valid_entry->base + pool->base;
5214 * bitmap_is_subset - Check whether src2 is subset of src1
5217 bitmap_is_subset(uint8_t src1, uint8_t src2)
5219 return !((src1 ^ src2) & src2);
5222 static enum i40e_status_code
5223 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5225 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5227 /* If DCB is not supported, only default TC is supported */
5228 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5229 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5230 return I40E_NOT_SUPPORTED;
5233 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5235 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5236 hw->func_caps.enabled_tcmap, enabled_tcmap);
5237 return I40E_NOT_SUPPORTED;
5239 return I40E_SUCCESS;
5243 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5244 struct i40e_vsi_vlan_pvid_info *info)
5247 struct i40e_vsi_context ctxt;
5248 uint8_t vlan_flags = 0;
5251 if (vsi == NULL || info == NULL) {
5252 PMD_DRV_LOG(ERR, "invalid parameters");
5253 return I40E_ERR_PARAM;
5257 vsi->info.pvid = info->config.pvid;
5259 * If insert pvid is enabled, only tagged pkts are
5260 * allowed to be sent out.
5262 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5263 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5266 if (info->config.reject.tagged == 0)
5267 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5269 if (info->config.reject.untagged == 0)
5270 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5272 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5273 I40E_AQ_VSI_PVLAN_MODE_MASK);
5274 vsi->info.port_vlan_flags |= vlan_flags;
5275 vsi->info.valid_sections =
5276 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5277 memset(&ctxt, 0, sizeof(ctxt));
5278 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5279 ctxt.seid = vsi->seid;
5281 hw = I40E_VSI_TO_HW(vsi);
5282 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5283 if (ret != I40E_SUCCESS)
5284 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5290 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5292 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5294 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5296 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5297 if (ret != I40E_SUCCESS)
5301 PMD_DRV_LOG(ERR, "seid not valid");
5305 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5306 tc_bw_data.tc_valid_bits = enabled_tcmap;
5307 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5308 tc_bw_data.tc_bw_credits[i] =
5309 (enabled_tcmap & (1 << i)) ? 1 : 0;
5311 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5312 if (ret != I40E_SUCCESS) {
5313 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5317 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5318 sizeof(vsi->info.qs_handle));
5319 return I40E_SUCCESS;
5322 static enum i40e_status_code
5323 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5324 struct i40e_aqc_vsi_properties_data *info,
5325 uint8_t enabled_tcmap)
5327 enum i40e_status_code ret;
5328 int i, total_tc = 0;
5329 uint16_t qpnum_per_tc, bsf, qp_idx;
5331 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5332 if (ret != I40E_SUCCESS)
5335 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5336 if (enabled_tcmap & (1 << i))
5340 vsi->enabled_tc = enabled_tcmap;
5342 /* Number of queues per enabled TC */
5343 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5344 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5345 bsf = rte_bsf32(qpnum_per_tc);
5347 /* Adjust the queue number to actual queues that can be applied */
5348 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5349 vsi->nb_qps = qpnum_per_tc * total_tc;
5352 * Configure TC and queue mapping parameters, for enabled TC,
5353 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5354 * default queue will serve it.
5357 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5358 if (vsi->enabled_tc & (1 << i)) {
5359 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5360 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5361 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5362 qp_idx += qpnum_per_tc;
5364 info->tc_mapping[i] = 0;
5367 /* Associate queue number with VSI */
5368 if (vsi->type == I40E_VSI_SRIOV) {
5369 info->mapping_flags |=
5370 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5371 for (i = 0; i < vsi->nb_qps; i++)
5372 info->queue_mapping[i] =
5373 rte_cpu_to_le_16(vsi->base_queue + i);
5375 info->mapping_flags |=
5376 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5377 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5379 info->valid_sections |=
5380 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5382 return I40E_SUCCESS;
5386 i40e_veb_release(struct i40e_veb *veb)
5388 struct i40e_vsi *vsi;
5394 if (!TAILQ_EMPTY(&veb->head)) {
5395 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5398 /* associate_vsi field is NULL for floating VEB */
5399 if (veb->associate_vsi != NULL) {
5400 vsi = veb->associate_vsi;
5401 hw = I40E_VSI_TO_HW(vsi);
5403 vsi->uplink_seid = veb->uplink_seid;
5406 veb->associate_pf->main_vsi->floating_veb = NULL;
5407 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5410 i40e_aq_delete_element(hw, veb->seid, NULL);
5412 return I40E_SUCCESS;
5416 static struct i40e_veb *
5417 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5419 struct i40e_veb *veb;
5425 "veb setup failed, associated PF shouldn't null");
5428 hw = I40E_PF_TO_HW(pf);
5430 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5432 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5436 veb->associate_vsi = vsi;
5437 veb->associate_pf = pf;
5438 TAILQ_INIT(&veb->head);
5439 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5441 /* create floating veb if vsi is NULL */
5443 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5444 I40E_DEFAULT_TCMAP, false,
5445 &veb->seid, false, NULL);
5447 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5448 true, &veb->seid, false, NULL);
5451 if (ret != I40E_SUCCESS) {
5452 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5453 hw->aq.asq_last_status);
5456 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5458 /* get statistics index */
5459 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5460 &veb->stats_idx, NULL, NULL, NULL);
5461 if (ret != I40E_SUCCESS) {
5462 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5463 hw->aq.asq_last_status);
5466 /* Get VEB bandwidth, to be implemented */
5467 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5469 vsi->uplink_seid = veb->seid;
5478 i40e_vsi_release(struct i40e_vsi *vsi)
5482 struct i40e_vsi_list *vsi_list;
5485 struct i40e_mac_filter *f;
5486 uint16_t user_param;
5489 return I40E_SUCCESS;
5494 user_param = vsi->user_param;
5496 pf = I40E_VSI_TO_PF(vsi);
5497 hw = I40E_VSI_TO_HW(vsi);
5499 /* VSI has child to attach, release child first */
5501 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5502 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5505 i40e_veb_release(vsi->veb);
5508 if (vsi->floating_veb) {
5509 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5510 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5515 /* Remove all macvlan filters of the VSI */
5516 i40e_vsi_remove_all_macvlan_filter(vsi);
5517 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5520 if (vsi->type != I40E_VSI_MAIN &&
5521 ((vsi->type != I40E_VSI_SRIOV) ||
5522 !pf->floating_veb_list[user_param])) {
5523 /* Remove vsi from parent's sibling list */
5524 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5525 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5526 return I40E_ERR_PARAM;
5528 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5529 &vsi->sib_vsi_list, list);
5531 /* Remove all switch element of the VSI */
5532 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5533 if (ret != I40E_SUCCESS)
5534 PMD_DRV_LOG(ERR, "Failed to delete element");
5537 if ((vsi->type == I40E_VSI_SRIOV) &&
5538 pf->floating_veb_list[user_param]) {
5539 /* Remove vsi from parent's sibling list */
5540 if (vsi->parent_vsi == NULL ||
5541 vsi->parent_vsi->floating_veb == NULL) {
5542 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5543 return I40E_ERR_PARAM;
5545 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5546 &vsi->sib_vsi_list, list);
5548 /* Remove all switch element of the VSI */
5549 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5550 if (ret != I40E_SUCCESS)
5551 PMD_DRV_LOG(ERR, "Failed to delete element");
5554 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5556 if (vsi->type != I40E_VSI_SRIOV)
5557 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5560 return I40E_SUCCESS;
5564 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5566 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5567 struct i40e_aqc_remove_macvlan_element_data def_filter;
5568 struct i40e_mac_filter_info filter;
5571 if (vsi->type != I40E_VSI_MAIN)
5572 return I40E_ERR_CONFIG;
5573 memset(&def_filter, 0, sizeof(def_filter));
5574 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5576 def_filter.vlan_tag = 0;
5577 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5578 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5579 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5580 if (ret != I40E_SUCCESS) {
5581 struct i40e_mac_filter *f;
5582 struct rte_ether_addr *mac;
5585 "Cannot remove the default macvlan filter");
5586 /* It needs to add the permanent mac into mac list */
5587 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5589 PMD_DRV_LOG(ERR, "failed to allocate memory");
5590 return I40E_ERR_NO_MEMORY;
5592 mac = &f->mac_info.mac_addr;
5593 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5595 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5596 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5601 rte_memcpy(&filter.mac_addr,
5602 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5603 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5604 return i40e_vsi_add_mac(vsi, &filter);
5608 * i40e_vsi_get_bw_config - Query VSI BW Information
5609 * @vsi: the VSI to be queried
5611 * Returns 0 on success, negative value on failure
5613 static enum i40e_status_code
5614 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5616 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5617 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5618 struct i40e_hw *hw = &vsi->adapter->hw;
5623 memset(&bw_config, 0, sizeof(bw_config));
5624 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5625 if (ret != I40E_SUCCESS) {
5626 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5627 hw->aq.asq_last_status);
5631 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5632 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5633 &ets_sla_config, NULL);
5634 if (ret != I40E_SUCCESS) {
5636 "VSI failed to get TC bandwdith configuration %u",
5637 hw->aq.asq_last_status);
5641 /* store and print out BW info */
5642 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5643 vsi->bw_info.bw_max = bw_config.max_bw;
5644 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5645 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5646 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5647 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5649 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5650 vsi->bw_info.bw_ets_share_credits[i] =
5651 ets_sla_config.share_credits[i];
5652 vsi->bw_info.bw_ets_credits[i] =
5653 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5654 /* 4 bits per TC, 4th bit is reserved */
5655 vsi->bw_info.bw_ets_max[i] =
5656 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5657 RTE_LEN2MASK(3, uint8_t));
5658 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5659 vsi->bw_info.bw_ets_share_credits[i]);
5660 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5661 vsi->bw_info.bw_ets_credits[i]);
5662 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5663 vsi->bw_info.bw_ets_max[i]);
5666 return I40E_SUCCESS;
5669 /* i40e_enable_pf_lb
5670 * @pf: pointer to the pf structure
5672 * allow loopback on pf
5675 i40e_enable_pf_lb(struct i40e_pf *pf)
5677 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5678 struct i40e_vsi_context ctxt;
5681 /* Use the FW API if FW >= v5.0 */
5682 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5683 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5687 memset(&ctxt, 0, sizeof(ctxt));
5688 ctxt.seid = pf->main_vsi_seid;
5689 ctxt.pf_num = hw->pf_id;
5690 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5692 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5693 ret, hw->aq.asq_last_status);
5696 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5697 ctxt.info.valid_sections =
5698 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5699 ctxt.info.switch_id |=
5700 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5702 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5704 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5705 hw->aq.asq_last_status);
5710 i40e_vsi_setup(struct i40e_pf *pf,
5711 enum i40e_vsi_type type,
5712 struct i40e_vsi *uplink_vsi,
5713 uint16_t user_param)
5715 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5716 struct i40e_vsi *vsi;
5717 struct i40e_mac_filter_info filter;
5719 struct i40e_vsi_context ctxt;
5720 struct rte_ether_addr broadcast =
5721 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5723 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5724 uplink_vsi == NULL) {
5726 "VSI setup failed, VSI link shouldn't be NULL");
5730 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5732 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5737 * 1.type is not MAIN and uplink vsi is not NULL
5738 * If uplink vsi didn't setup VEB, create one first under veb field
5739 * 2.type is SRIOV and the uplink is NULL
5740 * If floating VEB is NULL, create one veb under floating veb field
5743 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5744 uplink_vsi->veb == NULL) {
5745 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5747 if (uplink_vsi->veb == NULL) {
5748 PMD_DRV_LOG(ERR, "VEB setup failed");
5751 /* set ALLOWLOOPBACk on pf, when veb is created */
5752 i40e_enable_pf_lb(pf);
5755 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5756 pf->main_vsi->floating_veb == NULL) {
5757 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5759 if (pf->main_vsi->floating_veb == NULL) {
5760 PMD_DRV_LOG(ERR, "VEB setup failed");
5765 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5767 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5770 TAILQ_INIT(&vsi->mac_list);
5772 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5773 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5774 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5775 vsi->user_param = user_param;
5776 vsi->vlan_anti_spoof_on = 0;
5777 vsi->vlan_filter_on = 0;
5778 /* Allocate queues */
5779 switch (vsi->type) {
5780 case I40E_VSI_MAIN :
5781 vsi->nb_qps = pf->lan_nb_qps;
5783 case I40E_VSI_SRIOV :
5784 vsi->nb_qps = pf->vf_nb_qps;
5786 case I40E_VSI_VMDQ2:
5787 vsi->nb_qps = pf->vmdq_nb_qps;
5790 vsi->nb_qps = pf->fdir_nb_qps;
5796 * The filter status descriptor is reported in rx queue 0,
5797 * while the tx queue for fdir filter programming has no
5798 * such constraints, can be non-zero queues.
5799 * To simplify it, choose FDIR vsi use queue 0 pair.
5800 * To make sure it will use queue 0 pair, queue allocation
5801 * need be done before this function is called
5803 if (type != I40E_VSI_FDIR) {
5804 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5806 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5810 vsi->base_queue = ret;
5812 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5814 /* VF has MSIX interrupt in VF range, don't allocate here */
5815 if (type == I40E_VSI_MAIN) {
5816 if (pf->support_multi_driver) {
5817 /* If support multi-driver, need to use INT0 instead of
5818 * allocating from msix pool. The Msix pool is init from
5819 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5820 * to 1 without calling i40e_res_pool_alloc.
5825 ret = i40e_res_pool_alloc(&pf->msix_pool,
5826 RTE_MIN(vsi->nb_qps,
5827 RTE_MAX_RXTX_INTR_VEC_ID));
5830 "VSI MAIN %d get heap failed %d",
5832 goto fail_queue_alloc;
5834 vsi->msix_intr = ret;
5835 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5836 RTE_MAX_RXTX_INTR_VEC_ID);
5838 } else if (type != I40E_VSI_SRIOV) {
5839 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5841 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5842 goto fail_queue_alloc;
5844 vsi->msix_intr = ret;
5852 if (type == I40E_VSI_MAIN) {
5853 /* For main VSI, no need to add since it's default one */
5854 vsi->uplink_seid = pf->mac_seid;
5855 vsi->seid = pf->main_vsi_seid;
5856 /* Bind queues with specific MSIX interrupt */
5858 * Needs 2 interrupt at least, one for misc cause which will
5859 * enabled from OS side, Another for queues binding the
5860 * interrupt from device side only.
5863 /* Get default VSI parameters from hardware */
5864 memset(&ctxt, 0, sizeof(ctxt));
5865 ctxt.seid = vsi->seid;
5866 ctxt.pf_num = hw->pf_id;
5867 ctxt.uplink_seid = vsi->uplink_seid;
5869 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5870 if (ret != I40E_SUCCESS) {
5871 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5872 goto fail_msix_alloc;
5874 rte_memcpy(&vsi->info, &ctxt.info,
5875 sizeof(struct i40e_aqc_vsi_properties_data));
5876 vsi->vsi_id = ctxt.vsi_number;
5877 vsi->info.valid_sections = 0;
5879 /* Configure tc, enabled TC0 only */
5880 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5882 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5883 goto fail_msix_alloc;
5886 /* TC, queue mapping */
5887 memset(&ctxt, 0, sizeof(ctxt));
5888 vsi->info.valid_sections |=
5889 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5890 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5891 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5892 rte_memcpy(&ctxt.info, &vsi->info,
5893 sizeof(struct i40e_aqc_vsi_properties_data));
5894 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5895 I40E_DEFAULT_TCMAP);
5896 if (ret != I40E_SUCCESS) {
5898 "Failed to configure TC queue mapping");
5899 goto fail_msix_alloc;
5901 ctxt.seid = vsi->seid;
5902 ctxt.pf_num = hw->pf_id;
5903 ctxt.uplink_seid = vsi->uplink_seid;
5906 /* Update VSI parameters */
5907 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5908 if (ret != I40E_SUCCESS) {
5909 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5910 goto fail_msix_alloc;
5913 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5914 sizeof(vsi->info.tc_mapping));
5915 rte_memcpy(&vsi->info.queue_mapping,
5916 &ctxt.info.queue_mapping,
5917 sizeof(vsi->info.queue_mapping));
5918 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5919 vsi->info.valid_sections = 0;
5921 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5925 * Updating default filter settings are necessary to prevent
5926 * reception of tagged packets.
5927 * Some old firmware configurations load a default macvlan
5928 * filter which accepts both tagged and untagged packets.
5929 * The updating is to use a normal filter instead if needed.
5930 * For NVM 4.2.2 or after, the updating is not needed anymore.
5931 * The firmware with correct configurations load the default
5932 * macvlan filter which is expected and cannot be removed.
5934 i40e_update_default_filter_setting(vsi);
5935 i40e_config_qinq(hw, vsi);
5936 } else if (type == I40E_VSI_SRIOV) {
5937 memset(&ctxt, 0, sizeof(ctxt));
5939 * For other VSI, the uplink_seid equals to uplink VSI's
5940 * uplink_seid since they share same VEB
5942 if (uplink_vsi == NULL)
5943 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5945 vsi->uplink_seid = uplink_vsi->uplink_seid;
5946 ctxt.pf_num = hw->pf_id;
5947 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5948 ctxt.uplink_seid = vsi->uplink_seid;
5949 ctxt.connection_type = 0x1;
5950 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5952 /* Use the VEB configuration if FW >= v5.0 */
5953 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5954 /* Configure switch ID */
5955 ctxt.info.valid_sections |=
5956 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5957 ctxt.info.switch_id =
5958 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5961 /* Configure port/vlan */
5962 ctxt.info.valid_sections |=
5963 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5964 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5965 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5966 hw->func_caps.enabled_tcmap);
5967 if (ret != I40E_SUCCESS) {
5969 "Failed to configure TC queue mapping");
5970 goto fail_msix_alloc;
5973 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5974 ctxt.info.valid_sections |=
5975 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5977 * Since VSI is not created yet, only configure parameter,
5978 * will add vsi below.
5981 i40e_config_qinq(hw, vsi);
5982 } else if (type == I40E_VSI_VMDQ2) {
5983 memset(&ctxt, 0, sizeof(ctxt));
5985 * For other VSI, the uplink_seid equals to uplink VSI's
5986 * uplink_seid since they share same VEB
5988 vsi->uplink_seid = uplink_vsi->uplink_seid;
5989 ctxt.pf_num = hw->pf_id;
5991 ctxt.uplink_seid = vsi->uplink_seid;
5992 ctxt.connection_type = 0x1;
5993 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5995 ctxt.info.valid_sections |=
5996 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5997 /* user_param carries flag to enable loop back */
5999 ctxt.info.switch_id =
6000 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6001 ctxt.info.switch_id |=
6002 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6005 /* Configure port/vlan */
6006 ctxt.info.valid_sections |=
6007 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6008 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6009 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6010 I40E_DEFAULT_TCMAP);
6011 if (ret != I40E_SUCCESS) {
6013 "Failed to configure TC queue mapping");
6014 goto fail_msix_alloc;
6016 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6017 ctxt.info.valid_sections |=
6018 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6019 } else if (type == I40E_VSI_FDIR) {
6020 memset(&ctxt, 0, sizeof(ctxt));
6021 vsi->uplink_seid = uplink_vsi->uplink_seid;
6022 ctxt.pf_num = hw->pf_id;
6024 ctxt.uplink_seid = vsi->uplink_seid;
6025 ctxt.connection_type = 0x1; /* regular data port */
6026 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6027 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6028 I40E_DEFAULT_TCMAP);
6029 if (ret != I40E_SUCCESS) {
6031 "Failed to configure TC queue mapping.");
6032 goto fail_msix_alloc;
6034 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6035 ctxt.info.valid_sections |=
6036 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6038 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6039 goto fail_msix_alloc;
6042 if (vsi->type != I40E_VSI_MAIN) {
6043 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6044 if (ret != I40E_SUCCESS) {
6045 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6046 hw->aq.asq_last_status);
6047 goto fail_msix_alloc;
6049 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6050 vsi->info.valid_sections = 0;
6051 vsi->seid = ctxt.seid;
6052 vsi->vsi_id = ctxt.vsi_number;
6053 vsi->sib_vsi_list.vsi = vsi;
6054 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6055 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6056 &vsi->sib_vsi_list, list);
6058 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6059 &vsi->sib_vsi_list, list);
6063 /* MAC/VLAN configuration */
6064 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6065 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6067 ret = i40e_vsi_add_mac(vsi, &filter);
6068 if (ret != I40E_SUCCESS) {
6069 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6070 goto fail_msix_alloc;
6073 /* Get VSI BW information */
6074 i40e_vsi_get_bw_config(vsi);
6077 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6079 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6085 /* Configure vlan filter on or off */
6087 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6090 struct i40e_mac_filter *f;
6092 struct i40e_mac_filter_info *mac_filter;
6093 enum rte_mac_filter_type desired_filter;
6094 int ret = I40E_SUCCESS;
6097 /* Filter to match MAC and VLAN */
6098 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6100 /* Filter to match only MAC */
6101 desired_filter = RTE_MAC_PERFECT_MATCH;
6106 mac_filter = rte_zmalloc("mac_filter_info_data",
6107 num * sizeof(*mac_filter), 0);
6108 if (mac_filter == NULL) {
6109 PMD_DRV_LOG(ERR, "failed to allocate memory");
6110 return I40E_ERR_NO_MEMORY;
6115 /* Remove all existing mac */
6116 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6117 mac_filter[i] = f->mac_info;
6118 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6120 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6121 on ? "enable" : "disable");
6127 /* Override with new filter */
6128 for (i = 0; i < num; i++) {
6129 mac_filter[i].filter_type = desired_filter;
6130 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6132 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6133 on ? "enable" : "disable");
6139 rte_free(mac_filter);
6143 /* Configure vlan stripping on or off */
6145 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6147 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6148 struct i40e_vsi_context ctxt;
6150 int ret = I40E_SUCCESS;
6152 /* Check if it has been already on or off */
6153 if (vsi->info.valid_sections &
6154 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6156 if ((vsi->info.port_vlan_flags &
6157 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6158 return 0; /* already on */
6160 if ((vsi->info.port_vlan_flags &
6161 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6162 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6163 return 0; /* already off */
6168 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6170 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6171 vsi->info.valid_sections =
6172 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6173 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6174 vsi->info.port_vlan_flags |= vlan_flags;
6175 ctxt.seid = vsi->seid;
6176 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6177 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6179 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6180 on ? "enable" : "disable");
6186 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6188 struct rte_eth_dev_data *data = dev->data;
6192 /* Apply vlan offload setting */
6193 mask = ETH_VLAN_STRIP_MASK |
6194 ETH_VLAN_FILTER_MASK |
6195 ETH_VLAN_EXTEND_MASK;
6196 ret = i40e_vlan_offload_set(dev, mask);
6198 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6202 /* Apply pvid setting */
6203 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6204 data->dev_conf.txmode.hw_vlan_insert_pvid);
6206 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6212 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6214 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6216 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6220 i40e_update_flow_control(struct i40e_hw *hw)
6222 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6223 struct i40e_link_status link_status;
6224 uint32_t rxfc = 0, txfc = 0, reg;
6228 memset(&link_status, 0, sizeof(link_status));
6229 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6230 if (ret != I40E_SUCCESS) {
6231 PMD_DRV_LOG(ERR, "Failed to get link status information");
6232 goto write_reg; /* Disable flow control */
6235 an_info = hw->phy.link_info.an_info;
6236 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6237 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6238 ret = I40E_ERR_NOT_READY;
6239 goto write_reg; /* Disable flow control */
6242 * If link auto negotiation is enabled, flow control needs to
6243 * be configured according to it
6245 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6246 case I40E_LINK_PAUSE_RXTX:
6249 hw->fc.current_mode = I40E_FC_FULL;
6251 case I40E_AQ_LINK_PAUSE_RX:
6253 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6255 case I40E_AQ_LINK_PAUSE_TX:
6257 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6260 hw->fc.current_mode = I40E_FC_NONE;
6265 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6266 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6267 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6268 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6269 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6270 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6277 i40e_pf_setup(struct i40e_pf *pf)
6279 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6280 struct i40e_filter_control_settings settings;
6281 struct i40e_vsi *vsi;
6284 /* Clear all stats counters */
6285 pf->offset_loaded = FALSE;
6286 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6287 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6288 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6289 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6291 ret = i40e_pf_get_switch_config(pf);
6292 if (ret != I40E_SUCCESS) {
6293 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6297 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6299 PMD_INIT_LOG(WARNING,
6300 "failed to allocate switch domain for device %d", ret);
6302 if (pf->flags & I40E_FLAG_FDIR) {
6303 /* make queue allocated first, let FDIR use queue pair 0*/
6304 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6305 if (ret != I40E_FDIR_QUEUE_ID) {
6307 "queue allocation fails for FDIR: ret =%d",
6309 pf->flags &= ~I40E_FLAG_FDIR;
6312 /* main VSI setup */
6313 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6315 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6316 return I40E_ERR_NOT_READY;
6320 /* Configure filter control */
6321 memset(&settings, 0, sizeof(settings));
6322 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6323 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6324 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6325 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6327 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6328 hw->func_caps.rss_table_size);
6329 return I40E_ERR_PARAM;
6331 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6332 hw->func_caps.rss_table_size);
6333 pf->hash_lut_size = hw->func_caps.rss_table_size;
6335 /* Enable ethtype and macvlan filters */
6336 settings.enable_ethtype = TRUE;
6337 settings.enable_macvlan = TRUE;
6338 ret = i40e_set_filter_control(hw, &settings);
6340 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6343 /* Update flow control according to the auto negotiation */
6344 i40e_update_flow_control(hw);
6346 return I40E_SUCCESS;
6350 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6356 * Set or clear TX Queue Disable flags,
6357 * which is required by hardware.
6359 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6360 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6362 /* Wait until the request is finished */
6363 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6364 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6365 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6366 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6367 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6373 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6374 return I40E_SUCCESS; /* already on, skip next steps */
6376 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6377 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6379 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6380 return I40E_SUCCESS; /* already off, skip next steps */
6381 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6383 /* Write the register */
6384 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6385 /* Check the result */
6386 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6387 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6388 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6390 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6391 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6394 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6395 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6399 /* Check if it is timeout */
6400 if (j >= I40E_CHK_Q_ENA_COUNT) {
6401 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6402 (on ? "enable" : "disable"), q_idx);
6403 return I40E_ERR_TIMEOUT;
6406 return I40E_SUCCESS;
6410 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6415 /* Wait until the request is finished */
6416 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6417 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6418 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6419 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6420 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6425 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6426 return I40E_SUCCESS; /* Already on, skip next steps */
6427 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6429 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6430 return I40E_SUCCESS; /* Already off, skip next steps */
6431 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6434 /* Write the register */
6435 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6436 /* Check the result */
6437 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6438 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6439 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6441 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6442 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6445 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6446 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6451 /* Check if it is timeout */
6452 if (j >= I40E_CHK_Q_ENA_COUNT) {
6453 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6454 (on ? "enable" : "disable"), q_idx);
6455 return I40E_ERR_TIMEOUT;
6458 return I40E_SUCCESS;
6461 /* Initialize VSI for TX */
6463 i40e_dev_tx_init(struct i40e_pf *pf)
6465 struct rte_eth_dev_data *data = pf->dev_data;
6467 uint32_t ret = I40E_SUCCESS;
6468 struct i40e_tx_queue *txq;
6470 for (i = 0; i < data->nb_tx_queues; i++) {
6471 txq = data->tx_queues[i];
6472 if (!txq || !txq->q_set)
6474 ret = i40e_tx_queue_init(txq);
6475 if (ret != I40E_SUCCESS)
6478 if (ret == I40E_SUCCESS)
6479 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6485 /* Initialize VSI for RX */
6487 i40e_dev_rx_init(struct i40e_pf *pf)
6489 struct rte_eth_dev_data *data = pf->dev_data;
6490 int ret = I40E_SUCCESS;
6492 struct i40e_rx_queue *rxq;
6494 i40e_pf_config_mq_rx(pf);
6495 for (i = 0; i < data->nb_rx_queues; i++) {
6496 rxq = data->rx_queues[i];
6497 if (!rxq || !rxq->q_set)
6500 ret = i40e_rx_queue_init(rxq);
6501 if (ret != I40E_SUCCESS) {
6503 "Failed to do RX queue initialization");
6507 if (ret == I40E_SUCCESS)
6508 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6515 i40e_dev_rxtx_init(struct i40e_pf *pf)
6519 err = i40e_dev_tx_init(pf);
6521 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6524 err = i40e_dev_rx_init(pf);
6526 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6534 i40e_vmdq_setup(struct rte_eth_dev *dev)
6536 struct rte_eth_conf *conf = &dev->data->dev_conf;
6537 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6538 int i, err, conf_vsis, j, loop;
6539 struct i40e_vsi *vsi;
6540 struct i40e_vmdq_info *vmdq_info;
6541 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6542 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6545 * Disable interrupt to avoid message from VF. Furthermore, it will
6546 * avoid race condition in VSI creation/destroy.
6548 i40e_pf_disable_irq0(hw);
6550 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6551 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6555 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6556 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6557 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6558 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6559 pf->max_nb_vmdq_vsi);
6563 if (pf->vmdq != NULL) {
6564 PMD_INIT_LOG(INFO, "VMDQ already configured");
6568 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6569 sizeof(*vmdq_info) * conf_vsis, 0);
6571 if (pf->vmdq == NULL) {
6572 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6576 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6578 /* Create VMDQ VSI */
6579 for (i = 0; i < conf_vsis; i++) {
6580 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6581 vmdq_conf->enable_loop_back);
6583 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6587 vmdq_info = &pf->vmdq[i];
6589 vmdq_info->vsi = vsi;
6591 pf->nb_cfg_vmdq_vsi = conf_vsis;
6593 /* Configure Vlan */
6594 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6595 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6596 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6597 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6598 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6599 vmdq_conf->pool_map[i].vlan_id, j);
6601 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6602 vmdq_conf->pool_map[i].vlan_id);
6604 PMD_INIT_LOG(ERR, "Failed to add vlan");
6612 i40e_pf_enable_irq0(hw);
6617 for (i = 0; i < conf_vsis; i++)
6618 if (pf->vmdq[i].vsi == NULL)
6621 i40e_vsi_release(pf->vmdq[i].vsi);
6625 i40e_pf_enable_irq0(hw);
6630 i40e_stat_update_32(struct i40e_hw *hw,
6638 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6642 if (new_data >= *offset)
6643 *stat = (uint64_t)(new_data - *offset);
6645 *stat = (uint64_t)((new_data +
6646 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6650 i40e_stat_update_48(struct i40e_hw *hw,
6659 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6660 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6661 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6666 if (new_data >= *offset)
6667 *stat = new_data - *offset;
6669 *stat = (uint64_t)((new_data +
6670 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6672 *stat &= I40E_48_BIT_MASK;
6677 i40e_pf_disable_irq0(struct i40e_hw *hw)
6679 /* Disable all interrupt types */
6680 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6681 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6682 I40E_WRITE_FLUSH(hw);
6687 i40e_pf_enable_irq0(struct i40e_hw *hw)
6689 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6690 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6691 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6692 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6693 I40E_WRITE_FLUSH(hw);
6697 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6699 /* read pending request and disable first */
6700 i40e_pf_disable_irq0(hw);
6701 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6702 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6703 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6706 /* Link no queues with irq0 */
6707 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6708 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6712 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6718 uint32_t index, offset, val;
6723 * Try to find which VF trigger a reset, use absolute VF id to access
6724 * since the reg is global register.
6726 for (i = 0; i < pf->vf_num; i++) {
6727 abs_vf_id = hw->func_caps.vf_base_id + i;
6728 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6729 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6730 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6731 /* VFR event occurred */
6732 if (val & (0x1 << offset)) {
6735 /* Clear the event first */
6736 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6738 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6740 * Only notify a VF reset event occurred,
6741 * don't trigger another SW reset
6743 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6744 if (ret != I40E_SUCCESS)
6745 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6751 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6753 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6756 for (i = 0; i < pf->vf_num; i++)
6757 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6761 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6764 struct i40e_arq_event_info info;
6765 uint16_t pending, opcode;
6768 info.buf_len = I40E_AQ_BUF_SZ;
6769 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6770 if (!info.msg_buf) {
6771 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6777 ret = i40e_clean_arq_element(hw, &info, &pending);
6779 if (ret != I40E_SUCCESS) {
6781 "Failed to read msg from AdminQ, aq_err: %u",
6782 hw->aq.asq_last_status);
6785 opcode = rte_le_to_cpu_16(info.desc.opcode);
6788 case i40e_aqc_opc_send_msg_to_pf:
6789 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6790 i40e_pf_host_handle_vf_msg(dev,
6791 rte_le_to_cpu_16(info.desc.retval),
6792 rte_le_to_cpu_32(info.desc.cookie_high),
6793 rte_le_to_cpu_32(info.desc.cookie_low),
6797 case i40e_aqc_opc_get_link_status:
6798 ret = i40e_dev_link_update(dev, 0);
6800 _rte_eth_dev_callback_process(dev,
6801 RTE_ETH_EVENT_INTR_LSC, NULL);
6804 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6809 rte_free(info.msg_buf);
6813 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6815 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6816 #define I40E_MDD_CLEAR16 0xFFFF
6817 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6818 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6819 bool mdd_detected = false;
6820 struct i40e_pf_vf *vf;
6824 /* find what triggered the MDD event */
6825 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6826 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6827 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6828 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6829 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6830 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6831 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6832 I40E_GL_MDET_TX_EVENT_SHIFT;
6833 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6834 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6835 hw->func_caps.base_queue;
6836 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6837 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6838 event, queue, pf_num, vf_num, dev->data->name);
6839 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6840 mdd_detected = true;
6842 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6843 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6844 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6845 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6846 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6847 I40E_GL_MDET_RX_EVENT_SHIFT;
6848 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6849 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6850 hw->func_caps.base_queue;
6852 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6853 "queue %d of function 0x%02x device %s\n",
6854 event, queue, func, dev->data->name);
6855 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6856 mdd_detected = true;
6860 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6861 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6862 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6863 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6865 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6866 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6867 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6869 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6873 /* see if one of the VFs needs its hand slapped */
6874 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6876 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6877 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6878 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6880 vf->num_mdd_events++;
6881 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6883 i, vf->num_mdd_events);
6886 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6887 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6888 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6890 vf->num_mdd_events++;
6891 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6893 i, vf->num_mdd_events);
6899 * Interrupt handler triggered by NIC for handling
6900 * specific interrupt.
6903 * Pointer to interrupt handle.
6905 * The address of parameter (struct rte_eth_dev *) regsitered before.
6911 i40e_dev_interrupt_handler(void *param)
6913 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6914 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6917 /* Disable interrupt */
6918 i40e_pf_disable_irq0(hw);
6920 /* read out interrupt causes */
6921 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6923 /* No interrupt event indicated */
6924 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6925 PMD_DRV_LOG(INFO, "No interrupt event");
6928 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6929 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6930 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6931 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6932 i40e_handle_mdd_event(dev);
6934 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6935 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6936 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6937 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6938 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6939 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6940 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6941 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6942 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6943 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6945 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6946 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6947 i40e_dev_handle_vfr_event(dev);
6949 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6950 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6951 i40e_dev_handle_aq_msg(dev);
6955 /* Enable interrupt */
6956 i40e_pf_enable_irq0(hw);
6960 i40e_dev_alarm_handler(void *param)
6962 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6966 /* Disable interrupt */
6967 i40e_pf_disable_irq0(hw);
6969 /* read out interrupt causes */
6970 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6972 /* No interrupt event indicated */
6973 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6975 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6976 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6977 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6978 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6979 i40e_handle_mdd_event(dev);
6981 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6982 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6983 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6984 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6985 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6986 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6987 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6988 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6989 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6990 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6992 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6993 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6994 i40e_dev_handle_vfr_event(dev);
6996 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6997 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6998 i40e_dev_handle_aq_msg(dev);
7002 /* Enable interrupt */
7003 i40e_pf_enable_irq0(hw);
7004 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7005 i40e_dev_alarm_handler, dev);
7009 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7010 struct i40e_macvlan_filter *filter,
7013 int ele_num, ele_buff_size;
7014 int num, actual_num, i;
7016 int ret = I40E_SUCCESS;
7017 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7018 struct i40e_aqc_add_macvlan_element_data *req_list;
7020 if (filter == NULL || total == 0)
7021 return I40E_ERR_PARAM;
7022 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7023 ele_buff_size = hw->aq.asq_buf_size;
7025 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7026 if (req_list == NULL) {
7027 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7028 return I40E_ERR_NO_MEMORY;
7033 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7034 memset(req_list, 0, ele_buff_size);
7036 for (i = 0; i < actual_num; i++) {
7037 rte_memcpy(req_list[i].mac_addr,
7038 &filter[num + i].macaddr, ETH_ADDR_LEN);
7039 req_list[i].vlan_tag =
7040 rte_cpu_to_le_16(filter[num + i].vlan_id);
7042 switch (filter[num + i].filter_type) {
7043 case RTE_MAC_PERFECT_MATCH:
7044 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7045 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7047 case RTE_MACVLAN_PERFECT_MATCH:
7048 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7050 case RTE_MAC_HASH_MATCH:
7051 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7052 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7054 case RTE_MACVLAN_HASH_MATCH:
7055 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7058 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7059 ret = I40E_ERR_PARAM;
7063 req_list[i].queue_number = 0;
7065 req_list[i].flags = rte_cpu_to_le_16(flags);
7068 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7070 if (ret != I40E_SUCCESS) {
7071 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7075 } while (num < total);
7083 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7084 struct i40e_macvlan_filter *filter,
7087 int ele_num, ele_buff_size;
7088 int num, actual_num, i;
7090 int ret = I40E_SUCCESS;
7091 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7092 struct i40e_aqc_remove_macvlan_element_data *req_list;
7094 if (filter == NULL || total == 0)
7095 return I40E_ERR_PARAM;
7097 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7098 ele_buff_size = hw->aq.asq_buf_size;
7100 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7101 if (req_list == NULL) {
7102 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7103 return I40E_ERR_NO_MEMORY;
7108 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7109 memset(req_list, 0, ele_buff_size);
7111 for (i = 0; i < actual_num; i++) {
7112 rte_memcpy(req_list[i].mac_addr,
7113 &filter[num + i].macaddr, ETH_ADDR_LEN);
7114 req_list[i].vlan_tag =
7115 rte_cpu_to_le_16(filter[num + i].vlan_id);
7117 switch (filter[num + i].filter_type) {
7118 case RTE_MAC_PERFECT_MATCH:
7119 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7120 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7122 case RTE_MACVLAN_PERFECT_MATCH:
7123 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7125 case RTE_MAC_HASH_MATCH:
7126 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7127 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7129 case RTE_MACVLAN_HASH_MATCH:
7130 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7133 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7134 ret = I40E_ERR_PARAM;
7137 req_list[i].flags = rte_cpu_to_le_16(flags);
7140 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7142 if (ret != I40E_SUCCESS) {
7143 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7147 } while (num < total);
7154 /* Find out specific MAC filter */
7155 static struct i40e_mac_filter *
7156 i40e_find_mac_filter(struct i40e_vsi *vsi,
7157 struct rte_ether_addr *macaddr)
7159 struct i40e_mac_filter *f;
7161 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7162 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7170 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7173 uint32_t vid_idx, vid_bit;
7175 if (vlan_id > ETH_VLAN_ID_MAX)
7178 vid_idx = I40E_VFTA_IDX(vlan_id);
7179 vid_bit = I40E_VFTA_BIT(vlan_id);
7181 if (vsi->vfta[vid_idx] & vid_bit)
7188 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7189 uint16_t vlan_id, bool on)
7191 uint32_t vid_idx, vid_bit;
7193 vid_idx = I40E_VFTA_IDX(vlan_id);
7194 vid_bit = I40E_VFTA_BIT(vlan_id);
7197 vsi->vfta[vid_idx] |= vid_bit;
7199 vsi->vfta[vid_idx] &= ~vid_bit;
7203 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7204 uint16_t vlan_id, bool on)
7206 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7207 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7210 if (vlan_id > ETH_VLAN_ID_MAX)
7213 i40e_store_vlan_filter(vsi, vlan_id, on);
7215 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7218 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7221 ret = i40e_aq_add_vlan(hw, vsi->seid,
7222 &vlan_data, 1, NULL);
7223 if (ret != I40E_SUCCESS)
7224 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7226 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7227 &vlan_data, 1, NULL);
7228 if (ret != I40E_SUCCESS)
7230 "Failed to remove vlan filter");
7235 * Find all vlan options for specific mac addr,
7236 * return with actual vlan found.
7239 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7240 struct i40e_macvlan_filter *mv_f,
7241 int num, struct rte_ether_addr *addr)
7247 * Not to use i40e_find_vlan_filter to decrease the loop time,
7248 * although the code looks complex.
7250 if (num < vsi->vlan_num)
7251 return I40E_ERR_PARAM;
7254 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7256 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7257 if (vsi->vfta[j] & (1 << k)) {
7260 "vlan number doesn't match");
7261 return I40E_ERR_PARAM;
7263 rte_memcpy(&mv_f[i].macaddr,
7264 addr, ETH_ADDR_LEN);
7266 j * I40E_UINT32_BIT_SIZE + k;
7272 return I40E_SUCCESS;
7276 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7277 struct i40e_macvlan_filter *mv_f,
7282 struct i40e_mac_filter *f;
7284 if (num < vsi->mac_num)
7285 return I40E_ERR_PARAM;
7287 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7289 PMD_DRV_LOG(ERR, "buffer number not match");
7290 return I40E_ERR_PARAM;
7292 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7294 mv_f[i].vlan_id = vlan;
7295 mv_f[i].filter_type = f->mac_info.filter_type;
7299 return I40E_SUCCESS;
7303 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7306 struct i40e_mac_filter *f;
7307 struct i40e_macvlan_filter *mv_f;
7308 int ret = I40E_SUCCESS;
7310 if (vsi == NULL || vsi->mac_num == 0)
7311 return I40E_ERR_PARAM;
7313 /* Case that no vlan is set */
7314 if (vsi->vlan_num == 0)
7317 num = vsi->mac_num * vsi->vlan_num;
7319 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7321 PMD_DRV_LOG(ERR, "failed to allocate memory");
7322 return I40E_ERR_NO_MEMORY;
7326 if (vsi->vlan_num == 0) {
7327 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7328 rte_memcpy(&mv_f[i].macaddr,
7329 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7330 mv_f[i].filter_type = f->mac_info.filter_type;
7331 mv_f[i].vlan_id = 0;
7335 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7336 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7337 vsi->vlan_num, &f->mac_info.mac_addr);
7338 if (ret != I40E_SUCCESS)
7340 for (j = i; j < i + vsi->vlan_num; j++)
7341 mv_f[j].filter_type = f->mac_info.filter_type;
7346 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7354 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7356 struct i40e_macvlan_filter *mv_f;
7358 int ret = I40E_SUCCESS;
7360 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7361 return I40E_ERR_PARAM;
7363 /* If it's already set, just return */
7364 if (i40e_find_vlan_filter(vsi,vlan))
7365 return I40E_SUCCESS;
7367 mac_num = vsi->mac_num;
7370 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7371 return I40E_ERR_PARAM;
7374 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7377 PMD_DRV_LOG(ERR, "failed to allocate memory");
7378 return I40E_ERR_NO_MEMORY;
7381 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7383 if (ret != I40E_SUCCESS)
7386 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7388 if (ret != I40E_SUCCESS)
7391 i40e_set_vlan_filter(vsi, vlan, 1);
7401 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7403 struct i40e_macvlan_filter *mv_f;
7405 int ret = I40E_SUCCESS;
7408 * Vlan 0 is the generic filter for untagged packets
7409 * and can't be removed.
7411 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7412 return I40E_ERR_PARAM;
7414 /* If can't find it, just return */
7415 if (!i40e_find_vlan_filter(vsi, vlan))
7416 return I40E_ERR_PARAM;
7418 mac_num = vsi->mac_num;
7421 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7422 return I40E_ERR_PARAM;
7425 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7428 PMD_DRV_LOG(ERR, "failed to allocate memory");
7429 return I40E_ERR_NO_MEMORY;
7432 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7434 if (ret != I40E_SUCCESS)
7437 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7439 if (ret != I40E_SUCCESS)
7442 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7443 if (vsi->vlan_num == 1) {
7444 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7445 if (ret != I40E_SUCCESS)
7448 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7449 if (ret != I40E_SUCCESS)
7453 i40e_set_vlan_filter(vsi, vlan, 0);
7463 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7465 struct i40e_mac_filter *f;
7466 struct i40e_macvlan_filter *mv_f;
7467 int i, vlan_num = 0;
7468 int ret = I40E_SUCCESS;
7470 /* If it's add and we've config it, return */
7471 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7473 return I40E_SUCCESS;
7474 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7475 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7478 * If vlan_num is 0, that's the first time to add mac,
7479 * set mask for vlan_id 0.
7481 if (vsi->vlan_num == 0) {
7482 i40e_set_vlan_filter(vsi, 0, 1);
7485 vlan_num = vsi->vlan_num;
7486 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7487 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7490 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7492 PMD_DRV_LOG(ERR, "failed to allocate memory");
7493 return I40E_ERR_NO_MEMORY;
7496 for (i = 0; i < vlan_num; i++) {
7497 mv_f[i].filter_type = mac_filter->filter_type;
7498 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7502 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7503 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7504 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7505 &mac_filter->mac_addr);
7506 if (ret != I40E_SUCCESS)
7510 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7511 if (ret != I40E_SUCCESS)
7514 /* Add the mac addr into mac list */
7515 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7517 PMD_DRV_LOG(ERR, "failed to allocate memory");
7518 ret = I40E_ERR_NO_MEMORY;
7521 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7523 f->mac_info.filter_type = mac_filter->filter_type;
7524 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7535 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7537 struct i40e_mac_filter *f;
7538 struct i40e_macvlan_filter *mv_f;
7540 enum rte_mac_filter_type filter_type;
7541 int ret = I40E_SUCCESS;
7543 /* Can't find it, return an error */
7544 f = i40e_find_mac_filter(vsi, addr);
7546 return I40E_ERR_PARAM;
7548 vlan_num = vsi->vlan_num;
7549 filter_type = f->mac_info.filter_type;
7550 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7551 filter_type == RTE_MACVLAN_HASH_MATCH) {
7552 if (vlan_num == 0) {
7553 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7554 return I40E_ERR_PARAM;
7556 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7557 filter_type == RTE_MAC_HASH_MATCH)
7560 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7562 PMD_DRV_LOG(ERR, "failed to allocate memory");
7563 return I40E_ERR_NO_MEMORY;
7566 for (i = 0; i < vlan_num; i++) {
7567 mv_f[i].filter_type = filter_type;
7568 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7571 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7572 filter_type == RTE_MACVLAN_HASH_MATCH) {
7573 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7574 if (ret != I40E_SUCCESS)
7578 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7579 if (ret != I40E_SUCCESS)
7582 /* Remove the mac addr into mac list */
7583 TAILQ_REMOVE(&vsi->mac_list, f, next);
7593 /* Configure hash enable flags for RSS */
7595 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7603 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7604 if (flags & (1ULL << i))
7605 hena |= adapter->pctypes_tbl[i];
7611 /* Parse the hash enable flags */
7613 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7615 uint64_t rss_hf = 0;
7621 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7622 if (flags & adapter->pctypes_tbl[i])
7623 rss_hf |= (1ULL << i);
7630 i40e_pf_disable_rss(struct i40e_pf *pf)
7632 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7634 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7635 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7636 I40E_WRITE_FLUSH(hw);
7640 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7642 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7643 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7644 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7645 I40E_VFQF_HKEY_MAX_INDEX :
7646 I40E_PFQF_HKEY_MAX_INDEX;
7649 if (!key || key_len == 0) {
7650 PMD_DRV_LOG(DEBUG, "No key to be configured");
7652 } else if (key_len != (key_idx + 1) *
7654 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7658 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7659 struct i40e_aqc_get_set_rss_key_data *key_dw =
7660 (struct i40e_aqc_get_set_rss_key_data *)key;
7662 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7664 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7666 uint32_t *hash_key = (uint32_t *)key;
7669 if (vsi->type == I40E_VSI_SRIOV) {
7670 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7673 I40E_VFQF_HKEY1(i, vsi->user_param),
7677 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7678 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7681 I40E_WRITE_FLUSH(hw);
7688 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7690 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7691 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7695 if (!key || !key_len)
7698 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7699 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7700 (struct i40e_aqc_get_set_rss_key_data *)key);
7702 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7706 uint32_t *key_dw = (uint32_t *)key;
7709 if (vsi->type == I40E_VSI_SRIOV) {
7710 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7711 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7712 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7714 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7717 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7718 reg = I40E_PFQF_HKEY(i);
7719 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7721 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7729 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7731 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7735 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7736 rss_conf->rss_key_len);
7740 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7741 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7742 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7743 I40E_WRITE_FLUSH(hw);
7749 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7750 struct rte_eth_rss_conf *rss_conf)
7752 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7754 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7757 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7758 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7760 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7761 if (rss_hf != 0) /* Enable RSS */
7763 return 0; /* Nothing to do */
7766 if (rss_hf == 0) /* Disable RSS */
7769 return i40e_hw_rss_hash_set(pf, rss_conf);
7773 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7774 struct rte_eth_rss_conf *rss_conf)
7776 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7784 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7785 &rss_conf->rss_key_len);
7789 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7790 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7791 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7797 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7799 switch (filter_type) {
7800 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7801 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7803 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7804 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7806 case RTE_TUNNEL_FILTER_IMAC_TENID:
7807 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7809 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7810 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7812 case ETH_TUNNEL_FILTER_IMAC:
7813 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7815 case ETH_TUNNEL_FILTER_OIP:
7816 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7818 case ETH_TUNNEL_FILTER_IIP:
7819 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7822 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7829 /* Convert tunnel filter structure */
7831 i40e_tunnel_filter_convert(
7832 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7833 struct i40e_tunnel_filter *tunnel_filter)
7835 rte_ether_addr_copy((struct rte_ether_addr *)
7836 &cld_filter->element.outer_mac,
7837 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7838 rte_ether_addr_copy((struct rte_ether_addr *)
7839 &cld_filter->element.inner_mac,
7840 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7841 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7842 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7843 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7844 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7845 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7847 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7848 tunnel_filter->input.flags = cld_filter->element.flags;
7849 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7850 tunnel_filter->queue = cld_filter->element.queue_number;
7851 rte_memcpy(tunnel_filter->input.general_fields,
7852 cld_filter->general_fields,
7853 sizeof(cld_filter->general_fields));
7858 /* Check if there exists the tunnel filter */
7859 struct i40e_tunnel_filter *
7860 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7861 const struct i40e_tunnel_filter_input *input)
7865 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7869 return tunnel_rule->hash_map[ret];
7872 /* Add a tunnel filter into the SW list */
7874 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7875 struct i40e_tunnel_filter *tunnel_filter)
7877 struct i40e_tunnel_rule *rule = &pf->tunnel;
7880 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7883 "Failed to insert tunnel filter to hash table %d!",
7887 rule->hash_map[ret] = tunnel_filter;
7889 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7894 /* Delete a tunnel filter from the SW list */
7896 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7897 struct i40e_tunnel_filter_input *input)
7899 struct i40e_tunnel_rule *rule = &pf->tunnel;
7900 struct i40e_tunnel_filter *tunnel_filter;
7903 ret = rte_hash_del_key(rule->hash_table, input);
7906 "Failed to delete tunnel filter to hash table %d!",
7910 tunnel_filter = rule->hash_map[ret];
7911 rule->hash_map[ret] = NULL;
7913 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7914 rte_free(tunnel_filter);
7920 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7921 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7925 uint32_t ipv4_addr, ipv4_addr_le;
7926 uint8_t i, tun_type = 0;
7927 /* internal varialbe to convert ipv6 byte order */
7928 uint32_t convert_ipv6[4];
7930 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7931 struct i40e_vsi *vsi = pf->main_vsi;
7932 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7933 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7934 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7935 struct i40e_tunnel_filter *tunnel, *node;
7936 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7938 cld_filter = rte_zmalloc("tunnel_filter",
7939 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7942 if (NULL == cld_filter) {
7943 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7946 pfilter = cld_filter;
7948 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7949 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7950 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7951 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7953 pfilter->element.inner_vlan =
7954 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7955 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7956 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7957 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7958 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7959 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7961 sizeof(pfilter->element.ipaddr.v4.data));
7963 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7964 for (i = 0; i < 4; i++) {
7966 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7968 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7970 sizeof(pfilter->element.ipaddr.v6.data));
7973 /* check tunneled type */
7974 switch (tunnel_filter->tunnel_type) {
7975 case RTE_TUNNEL_TYPE_VXLAN:
7976 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7978 case RTE_TUNNEL_TYPE_NVGRE:
7979 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7981 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7982 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7984 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7985 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7988 /* Other tunnel types is not supported. */
7989 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7990 rte_free(cld_filter);
7994 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7995 &pfilter->element.flags);
7997 rte_free(cld_filter);
8001 pfilter->element.flags |= rte_cpu_to_le_16(
8002 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8003 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8004 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8005 pfilter->element.queue_number =
8006 rte_cpu_to_le_16(tunnel_filter->queue_id);
8008 /* Check if there is the filter in SW list */
8009 memset(&check_filter, 0, sizeof(check_filter));
8010 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8011 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8013 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8014 rte_free(cld_filter);
8018 if (!add && !node) {
8019 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8020 rte_free(cld_filter);
8025 ret = i40e_aq_add_cloud_filters(hw,
8026 vsi->seid, &cld_filter->element, 1);
8028 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8029 rte_free(cld_filter);
8032 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8033 if (tunnel == NULL) {
8034 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8035 rte_free(cld_filter);
8039 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8040 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8044 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8045 &cld_filter->element, 1);
8047 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8048 rte_free(cld_filter);
8051 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8054 rte_free(cld_filter);
8058 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8059 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
8060 #define I40E_TR_GENEVE_KEY_MASK 0x8
8061 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
8062 #define I40E_TR_GRE_KEY_MASK 0x400
8063 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
8064 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
8065 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8066 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8067 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8068 #define I40E_DIRECTION_INGRESS_KEY 0x8000
8069 #define I40E_TR_L4_TYPE_TCP 0x2
8070 #define I40E_TR_L4_TYPE_UDP 0x4
8071 #define I40E_TR_L4_TYPE_SCTP 0x8
8074 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8076 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8077 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8078 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8079 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8080 enum i40e_status_code status = I40E_SUCCESS;
8082 if (pf->support_multi_driver) {
8083 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8084 return I40E_NOT_SUPPORTED;
8087 memset(&filter_replace, 0,
8088 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8089 memset(&filter_replace_buf, 0,
8090 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8092 /* create L1 filter */
8093 filter_replace.old_filter_type =
8094 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8095 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8096 filter_replace.tr_bit = 0;
8098 /* Prepare the buffer, 3 entries */
8099 filter_replace_buf.data[0] =
8100 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8101 filter_replace_buf.data[0] |=
8102 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8103 filter_replace_buf.data[2] = 0xFF;
8104 filter_replace_buf.data[3] = 0xFF;
8105 filter_replace_buf.data[4] =
8106 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8107 filter_replace_buf.data[4] |=
8108 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8109 filter_replace_buf.data[7] = 0xF0;
8110 filter_replace_buf.data[8]
8111 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8112 filter_replace_buf.data[8] |=
8113 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8114 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8115 I40E_TR_GENEVE_KEY_MASK |
8116 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8117 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8118 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8119 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8121 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8122 &filter_replace_buf);
8123 if (!status && (filter_replace.old_filter_type !=
8124 filter_replace.new_filter_type))
8125 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8126 " original: 0x%x, new: 0x%x",
8128 filter_replace.old_filter_type,
8129 filter_replace.new_filter_type);
8135 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8137 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8138 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8139 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8140 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8141 enum i40e_status_code status = I40E_SUCCESS;
8143 if (pf->support_multi_driver) {
8144 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8145 return I40E_NOT_SUPPORTED;
8149 memset(&filter_replace, 0,
8150 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8151 memset(&filter_replace_buf, 0,
8152 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8153 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8154 I40E_AQC_MIRROR_CLOUD_FILTER;
8155 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8156 filter_replace.new_filter_type =
8157 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8158 /* Prepare the buffer, 2 entries */
8159 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8160 filter_replace_buf.data[0] |=
8161 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8162 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8163 filter_replace_buf.data[4] |=
8164 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8165 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8166 &filter_replace_buf);
8169 if (filter_replace.old_filter_type !=
8170 filter_replace.new_filter_type)
8171 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8172 " original: 0x%x, new: 0x%x",
8174 filter_replace.old_filter_type,
8175 filter_replace.new_filter_type);
8178 memset(&filter_replace, 0,
8179 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8180 memset(&filter_replace_buf, 0,
8181 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8183 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8184 I40E_AQC_MIRROR_CLOUD_FILTER;
8185 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8186 filter_replace.new_filter_type =
8187 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8188 /* Prepare the buffer, 2 entries */
8189 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8190 filter_replace_buf.data[0] |=
8191 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8192 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8193 filter_replace_buf.data[4] |=
8194 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8196 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8197 &filter_replace_buf);
8198 if (!status && (filter_replace.old_filter_type !=
8199 filter_replace.new_filter_type))
8200 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8201 " original: 0x%x, new: 0x%x",
8203 filter_replace.old_filter_type,
8204 filter_replace.new_filter_type);
8209 static enum i40e_status_code
8210 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8212 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8213 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8214 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8215 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8216 enum i40e_status_code status = I40E_SUCCESS;
8218 if (pf->support_multi_driver) {
8219 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8220 return I40E_NOT_SUPPORTED;
8224 memset(&filter_replace, 0,
8225 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8226 memset(&filter_replace_buf, 0,
8227 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8228 /* create L1 filter */
8229 filter_replace.old_filter_type =
8230 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8231 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8232 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8233 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8234 /* Prepare the buffer, 2 entries */
8235 filter_replace_buf.data[0] =
8236 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8237 filter_replace_buf.data[0] |=
8238 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8239 filter_replace_buf.data[2] = 0xFF;
8240 filter_replace_buf.data[3] = 0xFF;
8241 filter_replace_buf.data[4] =
8242 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8243 filter_replace_buf.data[4] |=
8244 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8245 filter_replace_buf.data[6] = 0xFF;
8246 filter_replace_buf.data[7] = 0xFF;
8247 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8248 &filter_replace_buf);
8251 if (filter_replace.old_filter_type !=
8252 filter_replace.new_filter_type)
8253 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8254 " original: 0x%x, new: 0x%x",
8256 filter_replace.old_filter_type,
8257 filter_replace.new_filter_type);
8260 memset(&filter_replace, 0,
8261 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8262 memset(&filter_replace_buf, 0,
8263 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8264 /* create L1 filter */
8265 filter_replace.old_filter_type =
8266 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8267 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8268 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8269 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8270 /* Prepare the buffer, 2 entries */
8271 filter_replace_buf.data[0] =
8272 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8273 filter_replace_buf.data[0] |=
8274 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8275 filter_replace_buf.data[2] = 0xFF;
8276 filter_replace_buf.data[3] = 0xFF;
8277 filter_replace_buf.data[4] =
8278 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8279 filter_replace_buf.data[4] |=
8280 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8281 filter_replace_buf.data[6] = 0xFF;
8282 filter_replace_buf.data[7] = 0xFF;
8284 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8285 &filter_replace_buf);
8286 if (!status && (filter_replace.old_filter_type !=
8287 filter_replace.new_filter_type))
8288 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8289 " original: 0x%x, new: 0x%x",
8291 filter_replace.old_filter_type,
8292 filter_replace.new_filter_type);
8298 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8300 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8301 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8302 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8303 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8304 enum i40e_status_code status = I40E_SUCCESS;
8306 if (pf->support_multi_driver) {
8307 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8308 return I40E_NOT_SUPPORTED;
8312 memset(&filter_replace, 0,
8313 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8314 memset(&filter_replace_buf, 0,
8315 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8316 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8317 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8318 filter_replace.new_filter_type =
8319 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8320 /* Prepare the buffer, 2 entries */
8321 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8322 filter_replace_buf.data[0] |=
8323 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8324 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8325 filter_replace_buf.data[4] |=
8326 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8327 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8328 &filter_replace_buf);
8331 if (filter_replace.old_filter_type !=
8332 filter_replace.new_filter_type)
8333 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8334 " original: 0x%x, new: 0x%x",
8336 filter_replace.old_filter_type,
8337 filter_replace.new_filter_type);
8340 memset(&filter_replace, 0,
8341 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8342 memset(&filter_replace_buf, 0,
8343 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8344 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8345 filter_replace.old_filter_type =
8346 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8347 filter_replace.new_filter_type =
8348 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8349 /* Prepare the buffer, 2 entries */
8350 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8351 filter_replace_buf.data[0] |=
8352 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8353 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8354 filter_replace_buf.data[4] |=
8355 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8357 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8358 &filter_replace_buf);
8359 if (!status && (filter_replace.old_filter_type !=
8360 filter_replace.new_filter_type))
8361 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8362 " original: 0x%x, new: 0x%x",
8364 filter_replace.old_filter_type,
8365 filter_replace.new_filter_type);
8370 static enum i40e_status_code
8371 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8372 enum i40e_l4_port_type l4_port_type)
8374 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8375 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8376 enum i40e_status_code status = I40E_SUCCESS;
8377 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8378 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8380 if (pf->support_multi_driver) {
8381 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8382 return I40E_NOT_SUPPORTED;
8385 memset(&filter_replace, 0,
8386 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8387 memset(&filter_replace_buf, 0,
8388 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8390 /* create L1 filter */
8391 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8392 filter_replace.old_filter_type =
8393 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8394 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8395 filter_replace_buf.data[8] =
8396 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8398 filter_replace.old_filter_type =
8399 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8400 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8401 filter_replace_buf.data[8] =
8402 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8405 filter_replace.tr_bit = 0;
8406 /* Prepare the buffer, 3 entries */
8407 filter_replace_buf.data[0] =
8408 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8409 filter_replace_buf.data[0] |=
8410 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8411 filter_replace_buf.data[2] = 0x00;
8412 filter_replace_buf.data[3] =
8413 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8414 filter_replace_buf.data[4] =
8415 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8416 filter_replace_buf.data[4] |=
8417 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8418 filter_replace_buf.data[5] = 0x00;
8419 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8420 I40E_TR_L4_TYPE_TCP |
8421 I40E_TR_L4_TYPE_SCTP;
8422 filter_replace_buf.data[7] = 0x00;
8423 filter_replace_buf.data[8] |=
8424 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8425 filter_replace_buf.data[9] = 0x00;
8426 filter_replace_buf.data[10] = 0xFF;
8427 filter_replace_buf.data[11] = 0xFF;
8429 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8430 &filter_replace_buf);
8431 if (!status && filter_replace.old_filter_type !=
8432 filter_replace.new_filter_type)
8433 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8434 " original: 0x%x, new: 0x%x",
8436 filter_replace.old_filter_type,
8437 filter_replace.new_filter_type);
8442 static enum i40e_status_code
8443 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8444 enum i40e_l4_port_type l4_port_type)
8446 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8447 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8448 enum i40e_status_code status = I40E_SUCCESS;
8449 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8450 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8452 if (pf->support_multi_driver) {
8453 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8454 return I40E_NOT_SUPPORTED;
8457 memset(&filter_replace, 0,
8458 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8459 memset(&filter_replace_buf, 0,
8460 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8462 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8463 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8464 filter_replace.new_filter_type =
8465 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8466 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8468 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8469 filter_replace.new_filter_type =
8470 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8471 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8474 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8475 filter_replace.tr_bit = 0;
8476 /* Prepare the buffer, 2 entries */
8477 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8478 filter_replace_buf.data[0] |=
8479 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8480 filter_replace_buf.data[4] |=
8481 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8482 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8483 &filter_replace_buf);
8485 if (!status && filter_replace.old_filter_type !=
8486 filter_replace.new_filter_type)
8487 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8488 " original: 0x%x, new: 0x%x",
8490 filter_replace.old_filter_type,
8491 filter_replace.new_filter_type);
8497 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8498 struct i40e_tunnel_filter_conf *tunnel_filter,
8502 uint32_t ipv4_addr, ipv4_addr_le;
8503 uint8_t i, tun_type = 0;
8504 /* internal variable to convert ipv6 byte order */
8505 uint32_t convert_ipv6[4];
8507 struct i40e_pf_vf *vf = NULL;
8508 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8509 struct i40e_vsi *vsi;
8510 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8511 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8512 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8513 struct i40e_tunnel_filter *tunnel, *node;
8514 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8516 bool big_buffer = 0;
8518 cld_filter = rte_zmalloc("tunnel_filter",
8519 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8522 if (cld_filter == NULL) {
8523 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8526 pfilter = cld_filter;
8528 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8529 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8530 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8531 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8533 pfilter->element.inner_vlan =
8534 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8535 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8536 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8537 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8538 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8539 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8541 sizeof(pfilter->element.ipaddr.v4.data));
8543 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8544 for (i = 0; i < 4; i++) {
8546 rte_cpu_to_le_32(rte_be_to_cpu_32(
8547 tunnel_filter->ip_addr.ipv6_addr[i]));
8549 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8551 sizeof(pfilter->element.ipaddr.v6.data));
8554 /* check tunneled type */
8555 switch (tunnel_filter->tunnel_type) {
8556 case I40E_TUNNEL_TYPE_VXLAN:
8557 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8559 case I40E_TUNNEL_TYPE_NVGRE:
8560 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8562 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8563 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8565 case I40E_TUNNEL_TYPE_MPLSoUDP:
8566 if (!pf->mpls_replace_flag) {
8567 i40e_replace_mpls_l1_filter(pf);
8568 i40e_replace_mpls_cloud_filter(pf);
8569 pf->mpls_replace_flag = 1;
8571 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8572 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8574 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8575 (teid_le & 0xF) << 12;
8576 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8579 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8581 case I40E_TUNNEL_TYPE_MPLSoGRE:
8582 if (!pf->mpls_replace_flag) {
8583 i40e_replace_mpls_l1_filter(pf);
8584 i40e_replace_mpls_cloud_filter(pf);
8585 pf->mpls_replace_flag = 1;
8587 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8588 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8590 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8591 (teid_le & 0xF) << 12;
8592 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8595 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8597 case I40E_TUNNEL_TYPE_GTPC:
8598 if (!pf->gtp_replace_flag) {
8599 i40e_replace_gtp_l1_filter(pf);
8600 i40e_replace_gtp_cloud_filter(pf);
8601 pf->gtp_replace_flag = 1;
8603 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8604 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8605 (teid_le >> 16) & 0xFFFF;
8606 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8608 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8612 case I40E_TUNNEL_TYPE_GTPU:
8613 if (!pf->gtp_replace_flag) {
8614 i40e_replace_gtp_l1_filter(pf);
8615 i40e_replace_gtp_cloud_filter(pf);
8616 pf->gtp_replace_flag = 1;
8618 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8619 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8620 (teid_le >> 16) & 0xFFFF;
8621 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8623 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8627 case I40E_TUNNEL_TYPE_QINQ:
8628 if (!pf->qinq_replace_flag) {
8629 ret = i40e_cloud_filter_qinq_create(pf);
8632 "QinQ tunnel filter already created.");
8633 pf->qinq_replace_flag = 1;
8635 /* Add in the General fields the values of
8636 * the Outer and Inner VLAN
8637 * Big Buffer should be set, see changes in
8638 * i40e_aq_add_cloud_filters
8640 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8641 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8644 case I40E_CLOUD_TYPE_UDP:
8645 case I40E_CLOUD_TYPE_TCP:
8646 case I40E_CLOUD_TYPE_SCTP:
8647 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8648 if (!pf->sport_replace_flag) {
8649 i40e_replace_port_l1_filter(pf,
8650 tunnel_filter->l4_port_type);
8651 i40e_replace_port_cloud_filter(pf,
8652 tunnel_filter->l4_port_type);
8653 pf->sport_replace_flag = 1;
8655 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8656 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8657 I40E_DIRECTION_INGRESS_KEY;
8659 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8660 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8661 I40E_TR_L4_TYPE_UDP;
8662 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8663 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8664 I40E_TR_L4_TYPE_TCP;
8666 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8667 I40E_TR_L4_TYPE_SCTP;
8669 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8670 (teid_le >> 16) & 0xFFFF;
8673 if (!pf->dport_replace_flag) {
8674 i40e_replace_port_l1_filter(pf,
8675 tunnel_filter->l4_port_type);
8676 i40e_replace_port_cloud_filter(pf,
8677 tunnel_filter->l4_port_type);
8678 pf->dport_replace_flag = 1;
8680 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8681 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8682 I40E_DIRECTION_INGRESS_KEY;
8684 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8685 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8686 I40E_TR_L4_TYPE_UDP;
8687 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8688 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8689 I40E_TR_L4_TYPE_TCP;
8691 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8692 I40E_TR_L4_TYPE_SCTP;
8694 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8695 (teid_le >> 16) & 0xFFFF;
8701 /* Other tunnel types is not supported. */
8702 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8703 rte_free(cld_filter);
8707 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8708 pfilter->element.flags =
8709 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8710 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8711 pfilter->element.flags =
8712 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8713 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8714 pfilter->element.flags =
8715 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8716 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8717 pfilter->element.flags =
8718 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8719 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8720 pfilter->element.flags |=
8721 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8722 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8723 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8724 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8725 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8726 pfilter->element.flags |=
8727 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8729 pfilter->element.flags |=
8730 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8732 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8733 &pfilter->element.flags);
8735 rte_free(cld_filter);
8740 pfilter->element.flags |= rte_cpu_to_le_16(
8741 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8742 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8743 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8744 pfilter->element.queue_number =
8745 rte_cpu_to_le_16(tunnel_filter->queue_id);
8747 if (!tunnel_filter->is_to_vf)
8750 if (tunnel_filter->vf_id >= pf->vf_num) {
8751 PMD_DRV_LOG(ERR, "Invalid argument.");
8752 rte_free(cld_filter);
8755 vf = &pf->vfs[tunnel_filter->vf_id];
8759 /* Check if there is the filter in SW list */
8760 memset(&check_filter, 0, sizeof(check_filter));
8761 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8762 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8763 check_filter.vf_id = tunnel_filter->vf_id;
8764 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8766 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8767 rte_free(cld_filter);
8771 if (!add && !node) {
8772 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8773 rte_free(cld_filter);
8779 ret = i40e_aq_add_cloud_filters_bb(hw,
8780 vsi->seid, cld_filter, 1);
8782 ret = i40e_aq_add_cloud_filters(hw,
8783 vsi->seid, &cld_filter->element, 1);
8785 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8786 rte_free(cld_filter);
8789 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8790 if (tunnel == NULL) {
8791 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8792 rte_free(cld_filter);
8796 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8797 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8802 ret = i40e_aq_rem_cloud_filters_bb(
8803 hw, vsi->seid, cld_filter, 1);
8805 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8806 &cld_filter->element, 1);
8808 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8809 rte_free(cld_filter);
8812 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8815 rte_free(cld_filter);
8820 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8824 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8825 if (pf->vxlan_ports[i] == port)
8833 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8836 uint8_t filter_idx = 0;
8837 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8839 idx = i40e_get_vxlan_port_idx(pf, port);
8841 /* Check if port already exists */
8843 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8847 /* Now check if there is space to add the new port */
8848 idx = i40e_get_vxlan_port_idx(pf, 0);
8851 "Maximum number of UDP ports reached, not adding port %d",
8856 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8859 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8863 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8866 /* New port: add it and mark its index in the bitmap */
8867 pf->vxlan_ports[idx] = port;
8868 pf->vxlan_bitmap |= (1 << idx);
8870 if (!(pf->flags & I40E_FLAG_VXLAN))
8871 pf->flags |= I40E_FLAG_VXLAN;
8877 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8880 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8882 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8883 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8887 idx = i40e_get_vxlan_port_idx(pf, port);
8890 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8894 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8895 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8899 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8902 pf->vxlan_ports[idx] = 0;
8903 pf->vxlan_bitmap &= ~(1 << idx);
8905 if (!pf->vxlan_bitmap)
8906 pf->flags &= ~I40E_FLAG_VXLAN;
8911 /* Add UDP tunneling port */
8913 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8914 struct rte_eth_udp_tunnel *udp_tunnel)
8917 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8919 if (udp_tunnel == NULL)
8922 switch (udp_tunnel->prot_type) {
8923 case RTE_TUNNEL_TYPE_VXLAN:
8924 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8925 I40E_AQC_TUNNEL_TYPE_VXLAN);
8927 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8928 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8929 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8931 case RTE_TUNNEL_TYPE_GENEVE:
8932 case RTE_TUNNEL_TYPE_TEREDO:
8933 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8938 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8946 /* Remove UDP tunneling port */
8948 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8949 struct rte_eth_udp_tunnel *udp_tunnel)
8952 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8954 if (udp_tunnel == NULL)
8957 switch (udp_tunnel->prot_type) {
8958 case RTE_TUNNEL_TYPE_VXLAN:
8959 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8960 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8962 case RTE_TUNNEL_TYPE_GENEVE:
8963 case RTE_TUNNEL_TYPE_TEREDO:
8964 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8968 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8976 /* Calculate the maximum number of contiguous PF queues that are configured */
8978 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8980 struct rte_eth_dev_data *data = pf->dev_data;
8982 struct i40e_rx_queue *rxq;
8985 for (i = 0; i < pf->lan_nb_qps; i++) {
8986 rxq = data->rx_queues[i];
8987 if (rxq && rxq->q_set)
8998 i40e_pf_config_rss(struct i40e_pf *pf)
9000 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9001 struct rte_eth_rss_conf rss_conf;
9002 uint32_t i, lut = 0;
9006 * If both VMDQ and RSS enabled, not all of PF queues are configured.
9007 * It's necessary to calculate the actual PF queues that are configured.
9009 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9010 num = i40e_pf_calc_configured_queues_num(pf);
9012 num = pf->dev_data->nb_rx_queues;
9014 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9015 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9020 "No PF queues are configured to enable RSS for port %u",
9021 pf->dev_data->port_id);
9025 if (pf->adapter->rss_reta_updated == 0) {
9026 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9029 lut = (lut << 8) | (j & ((0x1 <<
9030 hw->func_caps.rss_table_entry_width) - 1));
9032 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9037 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9038 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
9039 i40e_pf_disable_rss(pf);
9042 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9043 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9044 /* Random default keys */
9045 static uint32_t rss_key_default[] = {0x6b793944,
9046 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9047 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9048 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9050 rss_conf.rss_key = (uint8_t *)rss_key_default;
9051 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9055 return i40e_hw_rss_hash_set(pf, &rss_conf);
9059 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9060 struct rte_eth_tunnel_filter_conf *filter)
9062 if (pf == NULL || filter == NULL) {
9063 PMD_DRV_LOG(ERR, "Invalid parameter");
9067 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9068 PMD_DRV_LOG(ERR, "Invalid queue ID");
9072 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9073 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9077 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9078 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9079 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9083 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9084 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9085 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9092 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9093 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
9095 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9097 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9101 if (pf->support_multi_driver) {
9102 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9106 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9107 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9110 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9111 } else if (len == 4) {
9112 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9114 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9119 ret = i40e_aq_debug_write_global_register(hw,
9120 I40E_GL_PRS_FVBM(2),
9124 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9125 "with value 0x%08x",
9126 I40E_GL_PRS_FVBM(2), reg);
9130 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9131 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9137 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9144 switch (cfg->cfg_type) {
9145 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9146 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9149 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9157 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9158 enum rte_filter_op filter_op,
9161 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9162 int ret = I40E_ERR_PARAM;
9164 switch (filter_op) {
9165 case RTE_ETH_FILTER_SET:
9166 ret = i40e_dev_global_config_set(hw,
9167 (struct rte_eth_global_cfg *)arg);
9170 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9178 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9179 enum rte_filter_op filter_op,
9182 struct rte_eth_tunnel_filter_conf *filter;
9183 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9184 int ret = I40E_SUCCESS;
9186 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9188 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9189 return I40E_ERR_PARAM;
9191 switch (filter_op) {
9192 case RTE_ETH_FILTER_NOP:
9193 if (!(pf->flags & I40E_FLAG_VXLAN))
9194 ret = I40E_NOT_SUPPORTED;
9196 case RTE_ETH_FILTER_ADD:
9197 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9199 case RTE_ETH_FILTER_DELETE:
9200 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9203 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9204 ret = I40E_ERR_PARAM;
9212 i40e_pf_config_mq_rx(struct i40e_pf *pf)
9215 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9218 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
9219 ret = i40e_pf_config_rss(pf);
9221 i40e_pf_disable_rss(pf);
9226 /* Get the symmetric hash enable configurations per port */
9228 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9230 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9232 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9235 /* Set the symmetric hash enable configurations per port */
9237 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9239 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9242 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9244 "Symmetric hash has already been enabled");
9247 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9249 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9251 "Symmetric hash has already been disabled");
9254 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9256 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9257 I40E_WRITE_FLUSH(hw);
9261 * Get global configurations of hash function type and symmetric hash enable
9262 * per flow type (pctype). Note that global configuration means it affects all
9263 * the ports on the same NIC.
9266 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9267 struct rte_eth_hash_global_conf *g_cfg)
9269 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9273 memset(g_cfg, 0, sizeof(*g_cfg));
9274 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9275 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9276 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9278 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9279 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9280 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9283 * As i40e supports less than 64 flow types, only first 64 bits need to
9286 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9287 g_cfg->valid_bit_mask[i] = 0ULL;
9288 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9291 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9293 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9294 if (!adapter->pctypes_tbl[i])
9296 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9297 j < I40E_FILTER_PCTYPE_MAX; j++) {
9298 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9299 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9300 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9301 g_cfg->sym_hash_enable_mask[0] |=
9312 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9313 const struct rte_eth_hash_global_conf *g_cfg)
9316 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9318 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9319 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9320 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9321 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9327 * As i40e supports less than 64 flow types, only first 64 bits need to
9330 mask0 = g_cfg->valid_bit_mask[0];
9331 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9333 /* Check if any unsupported flow type configured */
9334 if ((mask0 | i40e_mask) ^ i40e_mask)
9337 if (g_cfg->valid_bit_mask[i])
9345 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9351 * Set global configurations of hash function type and symmetric hash enable
9352 * per flow type (pctype). Note any modifying global configuration will affect
9353 * all the ports on the same NIC.
9356 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9357 struct rte_eth_hash_global_conf *g_cfg)
9359 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9360 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9364 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9366 if (pf->support_multi_driver) {
9367 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9371 /* Check the input parameters */
9372 ret = i40e_hash_global_config_check(adapter, g_cfg);
9377 * As i40e supports less than 64 flow types, only first 64 bits need to
9380 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9381 if (mask0 & (1UL << i)) {
9382 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9383 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9385 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9386 j < I40E_FILTER_PCTYPE_MAX; j++) {
9387 if (adapter->pctypes_tbl[i] & (1ULL << j))
9388 i40e_write_global_rx_ctl(hw,
9395 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9396 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9398 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9400 "Hash function already set to Toeplitz");
9403 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9404 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9406 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9408 "Hash function already set to Simple XOR");
9411 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9413 /* Use the default, and keep it as it is */
9416 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9419 I40E_WRITE_FLUSH(hw);
9425 * Valid input sets for hash and flow director filters per PCTYPE
9428 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9429 enum rte_filter_type filter)
9433 static const uint64_t valid_hash_inset_table[] = {
9434 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9435 I40E_INSET_DMAC | I40E_INSET_SMAC |
9436 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9437 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9438 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9439 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9440 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9441 I40E_INSET_FLEX_PAYLOAD,
9442 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9443 I40E_INSET_DMAC | I40E_INSET_SMAC |
9444 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9445 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9446 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9447 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9448 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9449 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9450 I40E_INSET_FLEX_PAYLOAD,
9451 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9452 I40E_INSET_DMAC | I40E_INSET_SMAC |
9453 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9454 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9455 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9456 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9457 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9458 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9459 I40E_INSET_FLEX_PAYLOAD,
9460 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9461 I40E_INSET_DMAC | I40E_INSET_SMAC |
9462 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9463 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9464 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9465 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9466 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9467 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9468 I40E_INSET_FLEX_PAYLOAD,
9469 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9470 I40E_INSET_DMAC | I40E_INSET_SMAC |
9471 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9472 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9473 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9474 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9475 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9476 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9477 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9478 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9479 I40E_INSET_DMAC | I40E_INSET_SMAC |
9480 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9481 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9482 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9483 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9484 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9485 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9486 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9487 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9488 I40E_INSET_DMAC | I40E_INSET_SMAC |
9489 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9490 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9491 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9492 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9493 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9494 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9495 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9496 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9497 I40E_INSET_DMAC | I40E_INSET_SMAC |
9498 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9499 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9500 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9501 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9502 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9503 I40E_INSET_FLEX_PAYLOAD,
9504 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9505 I40E_INSET_DMAC | I40E_INSET_SMAC |
9506 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9507 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9508 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9509 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9510 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9511 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9512 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9513 I40E_INSET_DMAC | I40E_INSET_SMAC |
9514 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9515 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9516 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9517 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9518 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9519 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9520 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9521 I40E_INSET_DMAC | I40E_INSET_SMAC |
9522 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9523 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9524 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9525 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9526 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9527 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9528 I40E_INSET_FLEX_PAYLOAD,
9529 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9530 I40E_INSET_DMAC | I40E_INSET_SMAC |
9531 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9532 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9533 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9534 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9535 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9536 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9537 I40E_INSET_FLEX_PAYLOAD,
9538 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9539 I40E_INSET_DMAC | I40E_INSET_SMAC |
9540 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9541 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9542 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9543 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9544 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9545 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9546 I40E_INSET_FLEX_PAYLOAD,
9547 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9548 I40E_INSET_DMAC | I40E_INSET_SMAC |
9549 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9550 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9551 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9552 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9553 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9554 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9555 I40E_INSET_FLEX_PAYLOAD,
9556 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9557 I40E_INSET_DMAC | I40E_INSET_SMAC |
9558 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9559 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9560 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9561 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9562 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9563 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9564 I40E_INSET_FLEX_PAYLOAD,
9565 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9566 I40E_INSET_DMAC | I40E_INSET_SMAC |
9567 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9568 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9569 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9570 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9571 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9572 I40E_INSET_FLEX_PAYLOAD,
9573 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9574 I40E_INSET_DMAC | I40E_INSET_SMAC |
9575 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9576 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9577 I40E_INSET_FLEX_PAYLOAD,
9581 * Flow director supports only fields defined in
9582 * union rte_eth_fdir_flow.
9584 static const uint64_t valid_fdir_inset_table[] = {
9585 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9586 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9587 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9588 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9589 I40E_INSET_IPV4_TTL,
9590 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9591 I40E_INSET_DMAC | I40E_INSET_SMAC |
9592 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9593 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9594 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9595 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9596 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9597 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9598 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9599 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9600 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9601 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9602 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9603 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9604 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9605 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9606 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9607 I40E_INSET_DMAC | I40E_INSET_SMAC |
9608 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9609 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9610 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9611 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9612 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9613 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9614 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9615 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9616 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9617 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9618 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9619 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9620 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9621 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9623 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9624 I40E_INSET_DMAC | I40E_INSET_SMAC |
9625 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9626 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9627 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9628 I40E_INSET_IPV4_TTL,
9629 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9630 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9631 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9632 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9633 I40E_INSET_IPV6_HOP_LIMIT,
9634 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9635 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9636 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9637 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9638 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9639 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9640 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9641 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9642 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9643 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9644 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9645 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9646 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9647 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9648 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9649 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9650 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9651 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9652 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9653 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9654 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9655 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9656 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9657 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9658 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9659 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9660 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9661 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9662 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9663 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9665 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9666 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9667 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9668 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9669 I40E_INSET_IPV6_HOP_LIMIT,
9670 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9671 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9672 I40E_INSET_LAST_ETHER_TYPE,
9675 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9677 if (filter == RTE_ETH_FILTER_HASH)
9678 valid = valid_hash_inset_table[pctype];
9680 valid = valid_fdir_inset_table[pctype];
9686 * Validate if the input set is allowed for a specific PCTYPE
9689 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9690 enum rte_filter_type filter, uint64_t inset)
9694 valid = i40e_get_valid_input_set(pctype, filter);
9695 if (inset & (~valid))
9701 /* default input set fields combination per pctype */
9703 i40e_get_default_input_set(uint16_t pctype)
9705 static const uint64_t default_inset_table[] = {
9706 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9707 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9708 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9709 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9710 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9711 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9712 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9713 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9714 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9715 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9716 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9717 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9718 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9719 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9720 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9721 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9722 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9723 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9724 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9725 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9727 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9728 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9729 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9730 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9731 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9732 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9733 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9734 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9735 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9736 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9737 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9738 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9739 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9740 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9741 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9742 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9743 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9744 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9745 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9746 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9747 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9748 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9750 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9751 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9752 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9753 I40E_INSET_LAST_ETHER_TYPE,
9756 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9759 return default_inset_table[pctype];
9763 * Parse the input set from index to logical bit masks
9766 i40e_parse_input_set(uint64_t *inset,
9767 enum i40e_filter_pctype pctype,
9768 enum rte_eth_input_set_field *field,
9774 static const struct {
9775 enum rte_eth_input_set_field field;
9777 } inset_convert_table[] = {
9778 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9779 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9780 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9781 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9782 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9783 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9784 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9785 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9786 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9787 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9788 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9789 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9790 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9791 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9792 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9793 I40E_INSET_IPV6_NEXT_HDR},
9794 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9795 I40E_INSET_IPV6_HOP_LIMIT},
9796 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9797 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9798 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9799 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9800 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9801 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9802 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9803 I40E_INSET_SCTP_VT},
9804 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9805 I40E_INSET_TUNNEL_DMAC},
9806 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9807 I40E_INSET_VLAN_TUNNEL},
9808 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9809 I40E_INSET_TUNNEL_ID},
9810 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9811 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9812 I40E_INSET_FLEX_PAYLOAD_W1},
9813 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9814 I40E_INSET_FLEX_PAYLOAD_W2},
9815 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9816 I40E_INSET_FLEX_PAYLOAD_W3},
9817 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9818 I40E_INSET_FLEX_PAYLOAD_W4},
9819 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9820 I40E_INSET_FLEX_PAYLOAD_W5},
9821 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9822 I40E_INSET_FLEX_PAYLOAD_W6},
9823 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9824 I40E_INSET_FLEX_PAYLOAD_W7},
9825 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9826 I40E_INSET_FLEX_PAYLOAD_W8},
9829 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9832 /* Only one item allowed for default or all */
9834 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9835 *inset = i40e_get_default_input_set(pctype);
9837 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9838 *inset = I40E_INSET_NONE;
9843 for (i = 0, *inset = 0; i < size; i++) {
9844 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9845 if (field[i] == inset_convert_table[j].field) {
9846 *inset |= inset_convert_table[j].inset;
9851 /* It contains unsupported input set, return immediately */
9852 if (j == RTE_DIM(inset_convert_table))
9860 * Translate the input set from bit masks to register aware bit masks
9864 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9874 static const struct inset_map inset_map_common[] = {
9875 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9876 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9877 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9878 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9879 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9880 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9881 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9882 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9883 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9884 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9885 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9886 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9887 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9888 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9889 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9890 {I40E_INSET_TUNNEL_DMAC,
9891 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9892 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9893 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9894 {I40E_INSET_TUNNEL_SRC_PORT,
9895 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9896 {I40E_INSET_TUNNEL_DST_PORT,
9897 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9898 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9899 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9900 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9901 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9902 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9903 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9904 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9905 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9906 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9909 /* some different registers map in x722*/
9910 static const struct inset_map inset_map_diff_x722[] = {
9911 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9912 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9913 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9914 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9917 static const struct inset_map inset_map_diff_not_x722[] = {
9918 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9919 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9920 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9921 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9927 /* Translate input set to register aware inset */
9928 if (type == I40E_MAC_X722) {
9929 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9930 if (input & inset_map_diff_x722[i].inset)
9931 val |= inset_map_diff_x722[i].inset_reg;
9934 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9935 if (input & inset_map_diff_not_x722[i].inset)
9936 val |= inset_map_diff_not_x722[i].inset_reg;
9940 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9941 if (input & inset_map_common[i].inset)
9942 val |= inset_map_common[i].inset_reg;
9949 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9952 uint64_t inset_need_mask = inset;
9954 static const struct {
9957 } inset_mask_map[] = {
9958 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9959 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9960 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9961 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9962 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9963 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9964 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9965 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9968 if (!inset || !mask || !nb_elem)
9971 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9972 /* Clear the inset bit, if no MASK is required,
9973 * for example proto + ttl
9975 if ((inset & inset_mask_map[i].inset) ==
9976 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9977 inset_need_mask &= ~inset_mask_map[i].inset;
9978 if (!inset_need_mask)
9981 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9982 if ((inset_need_mask & inset_mask_map[i].inset) ==
9983 inset_mask_map[i].inset) {
9984 if (idx >= nb_elem) {
9985 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9988 mask[idx] = inset_mask_map[i].mask;
9997 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9999 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10001 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10003 i40e_write_rx_ctl(hw, addr, val);
10004 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10005 (uint32_t)i40e_read_rx_ctl(hw, addr));
10009 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10011 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10012 struct rte_eth_dev *dev;
10014 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10016 i40e_write_rx_ctl(hw, addr, val);
10017 PMD_DRV_LOG(WARNING,
10018 "i40e device %s changed global register [0x%08x]."
10019 " original: 0x%08x, new: 0x%08x",
10020 dev->device->name, addr, reg,
10021 (uint32_t)i40e_read_rx_ctl(hw, addr));
10026 i40e_filter_input_set_init(struct i40e_pf *pf)
10028 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10029 enum i40e_filter_pctype pctype;
10030 uint64_t input_set, inset_reg;
10031 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10033 uint16_t flow_type;
10035 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10036 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10037 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10039 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10042 input_set = i40e_get_default_input_set(pctype);
10044 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10045 I40E_INSET_MASK_NUM_REG);
10048 if (pf->support_multi_driver && num > 0) {
10049 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10052 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10055 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10056 (uint32_t)(inset_reg & UINT32_MAX));
10057 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10058 (uint32_t)((inset_reg >>
10059 I40E_32_BIT_WIDTH) & UINT32_MAX));
10060 if (!pf->support_multi_driver) {
10061 i40e_check_write_global_reg(hw,
10062 I40E_GLQF_HASH_INSET(0, pctype),
10063 (uint32_t)(inset_reg & UINT32_MAX));
10064 i40e_check_write_global_reg(hw,
10065 I40E_GLQF_HASH_INSET(1, pctype),
10066 (uint32_t)((inset_reg >>
10067 I40E_32_BIT_WIDTH) & UINT32_MAX));
10069 for (i = 0; i < num; i++) {
10070 i40e_check_write_global_reg(hw,
10071 I40E_GLQF_FD_MSK(i, pctype),
10073 i40e_check_write_global_reg(hw,
10074 I40E_GLQF_HASH_MSK(i, pctype),
10077 /*clear unused mask registers of the pctype */
10078 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10079 i40e_check_write_global_reg(hw,
10080 I40E_GLQF_FD_MSK(i, pctype),
10082 i40e_check_write_global_reg(hw,
10083 I40E_GLQF_HASH_MSK(i, pctype),
10087 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10089 I40E_WRITE_FLUSH(hw);
10091 /* store the default input set */
10092 if (!pf->support_multi_driver)
10093 pf->hash_input_set[pctype] = input_set;
10094 pf->fdir.input_set[pctype] = input_set;
10099 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10100 struct rte_eth_input_set_conf *conf)
10102 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10103 enum i40e_filter_pctype pctype;
10104 uint64_t input_set, inset_reg = 0;
10105 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10109 PMD_DRV_LOG(ERR, "Invalid pointer");
10112 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10113 conf->op != RTE_ETH_INPUT_SET_ADD) {
10114 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10118 if (pf->support_multi_driver) {
10119 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10123 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10124 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10125 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10129 if (hw->mac.type == I40E_MAC_X722) {
10130 /* get translated pctype value in fd pctype register */
10131 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10132 I40E_GLQF_FD_PCTYPES((int)pctype));
10135 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10138 PMD_DRV_LOG(ERR, "Failed to parse input set");
10142 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10143 /* get inset value in register */
10144 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10145 inset_reg <<= I40E_32_BIT_WIDTH;
10146 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10147 input_set |= pf->hash_input_set[pctype];
10149 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10150 I40E_INSET_MASK_NUM_REG);
10154 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10156 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10157 (uint32_t)(inset_reg & UINT32_MAX));
10158 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10159 (uint32_t)((inset_reg >>
10160 I40E_32_BIT_WIDTH) & UINT32_MAX));
10162 for (i = 0; i < num; i++)
10163 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10165 /*clear unused mask registers of the pctype */
10166 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10167 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10169 I40E_WRITE_FLUSH(hw);
10171 pf->hash_input_set[pctype] = input_set;
10176 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10177 struct rte_eth_input_set_conf *conf)
10179 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10180 enum i40e_filter_pctype pctype;
10181 uint64_t input_set, inset_reg = 0;
10182 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10185 if (!hw || !conf) {
10186 PMD_DRV_LOG(ERR, "Invalid pointer");
10189 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10190 conf->op != RTE_ETH_INPUT_SET_ADD) {
10191 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10195 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10197 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10198 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10202 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10205 PMD_DRV_LOG(ERR, "Failed to parse input set");
10209 /* get inset value in register */
10210 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10211 inset_reg <<= I40E_32_BIT_WIDTH;
10212 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10214 /* Can not change the inset reg for flex payload for fdir,
10215 * it is done by writing I40E_PRTQF_FD_FLXINSET
10216 * in i40e_set_flex_mask_on_pctype.
10218 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10219 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10221 input_set |= pf->fdir.input_set[pctype];
10222 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10223 I40E_INSET_MASK_NUM_REG);
10226 if (pf->support_multi_driver && num > 0) {
10227 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10231 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10233 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10234 (uint32_t)(inset_reg & UINT32_MAX));
10235 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10236 (uint32_t)((inset_reg >>
10237 I40E_32_BIT_WIDTH) & UINT32_MAX));
10239 if (!pf->support_multi_driver) {
10240 for (i = 0; i < num; i++)
10241 i40e_check_write_global_reg(hw,
10242 I40E_GLQF_FD_MSK(i, pctype),
10244 /*clear unused mask registers of the pctype */
10245 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10246 i40e_check_write_global_reg(hw,
10247 I40E_GLQF_FD_MSK(i, pctype),
10250 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10252 I40E_WRITE_FLUSH(hw);
10254 pf->fdir.input_set[pctype] = input_set;
10259 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10263 if (!hw || !info) {
10264 PMD_DRV_LOG(ERR, "Invalid pointer");
10268 switch (info->info_type) {
10269 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10270 i40e_get_symmetric_hash_enable_per_port(hw,
10271 &(info->info.enable));
10273 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10274 ret = i40e_get_hash_filter_global_config(hw,
10275 &(info->info.global_conf));
10278 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10288 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10292 if (!hw || !info) {
10293 PMD_DRV_LOG(ERR, "Invalid pointer");
10297 switch (info->info_type) {
10298 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10299 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10301 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10302 ret = i40e_set_hash_filter_global_config(hw,
10303 &(info->info.global_conf));
10305 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10306 ret = i40e_hash_filter_inset_select(hw,
10307 &(info->info.input_set_conf));
10311 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10320 /* Operations for hash function */
10322 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10323 enum rte_filter_op filter_op,
10326 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10329 switch (filter_op) {
10330 case RTE_ETH_FILTER_NOP:
10332 case RTE_ETH_FILTER_GET:
10333 ret = i40e_hash_filter_get(hw,
10334 (struct rte_eth_hash_filter_info *)arg);
10336 case RTE_ETH_FILTER_SET:
10337 ret = i40e_hash_filter_set(hw,
10338 (struct rte_eth_hash_filter_info *)arg);
10341 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10350 /* Convert ethertype filter structure */
10352 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10353 struct i40e_ethertype_filter *filter)
10355 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10356 RTE_ETHER_ADDR_LEN);
10357 filter->input.ether_type = input->ether_type;
10358 filter->flags = input->flags;
10359 filter->queue = input->queue;
10364 /* Check if there exists the ehtertype filter */
10365 struct i40e_ethertype_filter *
10366 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10367 const struct i40e_ethertype_filter_input *input)
10371 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10375 return ethertype_rule->hash_map[ret];
10378 /* Add ethertype filter in SW list */
10380 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10381 struct i40e_ethertype_filter *filter)
10383 struct i40e_ethertype_rule *rule = &pf->ethertype;
10386 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10389 "Failed to insert ethertype filter"
10390 " to hash table %d!",
10394 rule->hash_map[ret] = filter;
10396 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10401 /* Delete ethertype filter in SW list */
10403 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10404 struct i40e_ethertype_filter_input *input)
10406 struct i40e_ethertype_rule *rule = &pf->ethertype;
10407 struct i40e_ethertype_filter *filter;
10410 ret = rte_hash_del_key(rule->hash_table, input);
10413 "Failed to delete ethertype filter"
10414 " to hash table %d!",
10418 filter = rule->hash_map[ret];
10419 rule->hash_map[ret] = NULL;
10421 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10428 * Configure ethertype filter, which can director packet by filtering
10429 * with mac address and ether_type or only ether_type
10432 i40e_ethertype_filter_set(struct i40e_pf *pf,
10433 struct rte_eth_ethertype_filter *filter,
10436 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10437 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10438 struct i40e_ethertype_filter *ethertype_filter, *node;
10439 struct i40e_ethertype_filter check_filter;
10440 struct i40e_control_filter_stats stats;
10441 uint16_t flags = 0;
10444 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10445 PMD_DRV_LOG(ERR, "Invalid queue ID");
10448 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10449 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10451 "unsupported ether_type(0x%04x) in control packet filter.",
10452 filter->ether_type);
10455 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10456 PMD_DRV_LOG(WARNING,
10457 "filter vlan ether_type in first tag is not supported.");
10459 /* Check if there is the filter in SW list */
10460 memset(&check_filter, 0, sizeof(check_filter));
10461 i40e_ethertype_filter_convert(filter, &check_filter);
10462 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10463 &check_filter.input);
10465 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10469 if (!add && !node) {
10470 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10474 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10475 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10476 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10477 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10478 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10480 memset(&stats, 0, sizeof(stats));
10481 ret = i40e_aq_add_rem_control_packet_filter(hw,
10482 filter->mac_addr.addr_bytes,
10483 filter->ether_type, flags,
10484 pf->main_vsi->seid,
10485 filter->queue, add, &stats, NULL);
10488 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10489 ret, stats.mac_etype_used, stats.etype_used,
10490 stats.mac_etype_free, stats.etype_free);
10494 /* Add or delete a filter in SW list */
10496 ethertype_filter = rte_zmalloc("ethertype_filter",
10497 sizeof(*ethertype_filter), 0);
10498 if (ethertype_filter == NULL) {
10499 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10503 rte_memcpy(ethertype_filter, &check_filter,
10504 sizeof(check_filter));
10505 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10507 rte_free(ethertype_filter);
10509 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10516 * Handle operations for ethertype filter.
10519 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10520 enum rte_filter_op filter_op,
10523 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10526 if (filter_op == RTE_ETH_FILTER_NOP)
10530 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10535 switch (filter_op) {
10536 case RTE_ETH_FILTER_ADD:
10537 ret = i40e_ethertype_filter_set(pf,
10538 (struct rte_eth_ethertype_filter *)arg,
10541 case RTE_ETH_FILTER_DELETE:
10542 ret = i40e_ethertype_filter_set(pf,
10543 (struct rte_eth_ethertype_filter *)arg,
10547 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10555 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10556 enum rte_filter_type filter_type,
10557 enum rte_filter_op filter_op,
10565 switch (filter_type) {
10566 case RTE_ETH_FILTER_NONE:
10567 /* For global configuration */
10568 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10570 case RTE_ETH_FILTER_HASH:
10571 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10573 case RTE_ETH_FILTER_MACVLAN:
10574 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10576 case RTE_ETH_FILTER_ETHERTYPE:
10577 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10579 case RTE_ETH_FILTER_TUNNEL:
10580 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10582 case RTE_ETH_FILTER_FDIR:
10583 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10585 case RTE_ETH_FILTER_GENERIC:
10586 if (filter_op != RTE_ETH_FILTER_GET)
10588 *(const void **)arg = &i40e_flow_ops;
10591 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10601 * Check and enable Extended Tag.
10602 * Enabling Extended Tag is important for 40G performance.
10605 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10607 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10611 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10614 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10618 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10619 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10624 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10627 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10631 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10632 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10635 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10636 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10639 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10646 * As some registers wouldn't be reset unless a global hardware reset,
10647 * hardware initialization is needed to put those registers into an
10648 * expected initial state.
10651 i40e_hw_init(struct rte_eth_dev *dev)
10653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10655 i40e_enable_extended_tag(dev);
10657 /* clear the PF Queue Filter control register */
10658 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10660 /* Disable symmetric hash per port */
10661 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10665 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10666 * however this function will return only one highest pctype index,
10667 * which is not quite correct. This is known problem of i40e driver
10668 * and needs to be fixed later.
10670 enum i40e_filter_pctype
10671 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10674 uint64_t pctype_mask;
10676 if (flow_type < I40E_FLOW_TYPE_MAX) {
10677 pctype_mask = adapter->pctypes_tbl[flow_type];
10678 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10679 if (pctype_mask & (1ULL << i))
10680 return (enum i40e_filter_pctype)i;
10683 return I40E_FILTER_PCTYPE_INVALID;
10687 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10688 enum i40e_filter_pctype pctype)
10691 uint64_t pctype_mask = 1ULL << pctype;
10693 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10695 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10699 return RTE_ETH_FLOW_UNKNOWN;
10703 * On X710, performance number is far from the expectation on recent firmware
10704 * versions; on XL710, performance number is also far from the expectation on
10705 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10706 * mode is enabled and port MAC address is equal to the packet destination MAC
10707 * address. The fix for this issue may not be integrated in the following
10708 * firmware version. So the workaround in software driver is needed. It needs
10709 * to modify the initial values of 3 internal only registers for both X710 and
10710 * XL710. Note that the values for X710 or XL710 could be different, and the
10711 * workaround can be removed when it is fixed in firmware in the future.
10714 /* For both X710 and XL710 */
10715 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10716 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10717 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10719 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10720 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10723 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10724 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10727 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10729 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10730 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10733 * GL_SWR_PM_UP_THR:
10734 * The value is not impacted from the link speed, its value is set according
10735 * to the total number of ports for a better pipe-monitor configuration.
10738 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10740 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10741 .device_id = (dev), \
10742 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10744 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10745 .device_id = (dev), \
10746 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10748 static const struct {
10749 uint16_t device_id;
10751 } swr_pm_table[] = {
10752 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10753 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10754 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10755 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10756 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10758 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10759 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10760 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10761 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10762 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10763 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10764 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10768 if (value == NULL) {
10769 PMD_DRV_LOG(ERR, "value is NULL");
10773 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10774 if (hw->device_id == swr_pm_table[i].device_id) {
10775 *value = swr_pm_table[i].val;
10777 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10779 hw->device_id, *value);
10788 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10790 enum i40e_status_code status;
10791 struct i40e_aq_get_phy_abilities_resp phy_ab;
10792 int ret = -ENOTSUP;
10795 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10799 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10802 rte_delay_us(100000);
10804 status = i40e_aq_get_phy_capabilities(hw, false,
10805 true, &phy_ab, NULL);
10813 i40e_configure_registers(struct i40e_hw *hw)
10819 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10820 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10821 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10827 for (i = 0; i < RTE_DIM(reg_table); i++) {
10828 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10829 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10831 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10832 else /* For X710/XL710/XXV710 */
10833 if (hw->aq.fw_maj_ver < 6)
10835 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10838 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10841 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10842 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10844 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10845 else /* For X710/XL710/XXV710 */
10847 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10850 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10853 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10854 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10855 "GL_SWR_PM_UP_THR value fixup",
10860 reg_table[i].val = cfg_val;
10863 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10866 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10867 reg_table[i].addr);
10870 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10871 reg_table[i].addr, reg);
10872 if (reg == reg_table[i].val)
10875 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10876 reg_table[i].val, NULL);
10879 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10880 reg_table[i].val, reg_table[i].addr);
10883 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10884 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10888 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10889 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10890 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10891 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10893 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10898 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10899 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10903 /* Configure for double VLAN RX stripping */
10904 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10905 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10906 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10907 ret = i40e_aq_debug_write_register(hw,
10908 I40E_VSI_TSR(vsi->vsi_id),
10911 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10913 return I40E_ERR_CONFIG;
10917 /* Configure for double VLAN TX insertion */
10918 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10919 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10920 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10921 ret = i40e_aq_debug_write_register(hw,
10922 I40E_VSI_L2TAGSTXVALID(
10923 vsi->vsi_id), reg, NULL);
10926 "Failed to update VSI_L2TAGSTXVALID[%d]",
10928 return I40E_ERR_CONFIG;
10936 * i40e_aq_add_mirror_rule
10937 * @hw: pointer to the hardware structure
10938 * @seid: VEB seid to add mirror rule to
10939 * @dst_id: destination vsi seid
10940 * @entries: Buffer which contains the entities to be mirrored
10941 * @count: number of entities contained in the buffer
10942 * @rule_id:the rule_id of the rule to be added
10944 * Add a mirror rule for a given veb.
10947 static enum i40e_status_code
10948 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10949 uint16_t seid, uint16_t dst_id,
10950 uint16_t rule_type, uint16_t *entries,
10951 uint16_t count, uint16_t *rule_id)
10953 struct i40e_aq_desc desc;
10954 struct i40e_aqc_add_delete_mirror_rule cmd;
10955 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10956 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10959 enum i40e_status_code status;
10961 i40e_fill_default_direct_cmd_desc(&desc,
10962 i40e_aqc_opc_add_mirror_rule);
10963 memset(&cmd, 0, sizeof(cmd));
10965 buff_len = sizeof(uint16_t) * count;
10966 desc.datalen = rte_cpu_to_le_16(buff_len);
10968 desc.flags |= rte_cpu_to_le_16(
10969 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10970 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10971 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10972 cmd.num_entries = rte_cpu_to_le_16(count);
10973 cmd.seid = rte_cpu_to_le_16(seid);
10974 cmd.destination = rte_cpu_to_le_16(dst_id);
10976 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10977 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10979 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10980 hw->aq.asq_last_status, resp->rule_id,
10981 resp->mirror_rules_used, resp->mirror_rules_free);
10982 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10988 * i40e_aq_del_mirror_rule
10989 * @hw: pointer to the hardware structure
10990 * @seid: VEB seid to add mirror rule to
10991 * @entries: Buffer which contains the entities to be mirrored
10992 * @count: number of entities contained in the buffer
10993 * @rule_id:the rule_id of the rule to be delete
10995 * Delete a mirror rule for a given veb.
10998 static enum i40e_status_code
10999 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
11000 uint16_t seid, uint16_t rule_type, uint16_t *entries,
11001 uint16_t count, uint16_t rule_id)
11003 struct i40e_aq_desc desc;
11004 struct i40e_aqc_add_delete_mirror_rule cmd;
11005 uint16_t buff_len = 0;
11006 enum i40e_status_code status;
11009 i40e_fill_default_direct_cmd_desc(&desc,
11010 i40e_aqc_opc_delete_mirror_rule);
11011 memset(&cmd, 0, sizeof(cmd));
11012 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11013 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11015 cmd.num_entries = count;
11016 buff_len = sizeof(uint16_t) * count;
11017 desc.datalen = rte_cpu_to_le_16(buff_len);
11018 buff = (void *)entries;
11020 /* rule id is filled in destination field for deleting mirror rule */
11021 cmd.destination = rte_cpu_to_le_16(rule_id);
11023 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11024 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11025 cmd.seid = rte_cpu_to_le_16(seid);
11027 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11028 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11034 * i40e_mirror_rule_set
11035 * @dev: pointer to the hardware structure
11036 * @mirror_conf: mirror rule info
11037 * @sw_id: mirror rule's sw_id
11038 * @on: enable/disable
11040 * set a mirror rule.
11044 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11045 struct rte_eth_mirror_conf *mirror_conf,
11046 uint8_t sw_id, uint8_t on)
11048 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11049 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11050 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11051 struct i40e_mirror_rule *parent = NULL;
11052 uint16_t seid, dst_seid, rule_id;
11056 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11058 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11060 "mirror rule can not be configured without veb or vfs.");
11063 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11064 PMD_DRV_LOG(ERR, "mirror table is full.");
11067 if (mirror_conf->dst_pool > pf->vf_num) {
11068 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11069 mirror_conf->dst_pool);
11073 seid = pf->main_vsi->veb->seid;
11075 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11076 if (sw_id <= it->index) {
11082 if (mirr_rule && sw_id == mirr_rule->index) {
11084 PMD_DRV_LOG(ERR, "mirror rule exists.");
11087 ret = i40e_aq_del_mirror_rule(hw, seid,
11088 mirr_rule->rule_type,
11089 mirr_rule->entries,
11090 mirr_rule->num_entries, mirr_rule->id);
11093 "failed to remove mirror rule: ret = %d, aq_err = %d.",
11094 ret, hw->aq.asq_last_status);
11097 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11098 rte_free(mirr_rule);
11099 pf->nb_mirror_rule--;
11103 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11107 mirr_rule = rte_zmalloc("i40e_mirror_rule",
11108 sizeof(struct i40e_mirror_rule) , 0);
11110 PMD_DRV_LOG(ERR, "failed to allocate memory");
11111 return I40E_ERR_NO_MEMORY;
11113 switch (mirror_conf->rule_type) {
11114 case ETH_MIRROR_VLAN:
11115 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11116 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11117 mirr_rule->entries[j] =
11118 mirror_conf->vlan.vlan_id[i];
11123 PMD_DRV_LOG(ERR, "vlan is not specified.");
11124 rte_free(mirr_rule);
11127 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11129 case ETH_MIRROR_VIRTUAL_POOL_UP:
11130 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11131 /* check if the specified pool bit is out of range */
11132 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11133 PMD_DRV_LOG(ERR, "pool mask is out of range.");
11134 rte_free(mirr_rule);
11137 for (i = 0, j = 0; i < pf->vf_num; i++) {
11138 if (mirror_conf->pool_mask & (1ULL << i)) {
11139 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11143 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11144 /* add pf vsi to entries */
11145 mirr_rule->entries[j] = pf->main_vsi_seid;
11149 PMD_DRV_LOG(ERR, "pool is not specified.");
11150 rte_free(mirr_rule);
11153 /* egress and ingress in aq commands means from switch but not port */
11154 mirr_rule->rule_type =
11155 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11156 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11157 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11159 case ETH_MIRROR_UPLINK_PORT:
11160 /* egress and ingress in aq commands means from switch but not port*/
11161 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11163 case ETH_MIRROR_DOWNLINK_PORT:
11164 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11167 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11168 mirror_conf->rule_type);
11169 rte_free(mirr_rule);
11173 /* If the dst_pool is equal to vf_num, consider it as PF */
11174 if (mirror_conf->dst_pool == pf->vf_num)
11175 dst_seid = pf->main_vsi_seid;
11177 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11179 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11180 mirr_rule->rule_type, mirr_rule->entries,
11184 "failed to add mirror rule: ret = %d, aq_err = %d.",
11185 ret, hw->aq.asq_last_status);
11186 rte_free(mirr_rule);
11190 mirr_rule->index = sw_id;
11191 mirr_rule->num_entries = j;
11192 mirr_rule->id = rule_id;
11193 mirr_rule->dst_vsi_seid = dst_seid;
11196 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11198 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11200 pf->nb_mirror_rule++;
11205 * i40e_mirror_rule_reset
11206 * @dev: pointer to the device
11207 * @sw_id: mirror rule's sw_id
11209 * reset a mirror rule.
11213 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11215 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11217 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11221 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11223 seid = pf->main_vsi->veb->seid;
11225 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11226 if (sw_id == it->index) {
11232 ret = i40e_aq_del_mirror_rule(hw, seid,
11233 mirr_rule->rule_type,
11234 mirr_rule->entries,
11235 mirr_rule->num_entries, mirr_rule->id);
11238 "failed to remove mirror rule: status = %d, aq_err = %d.",
11239 ret, hw->aq.asq_last_status);
11242 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11243 rte_free(mirr_rule);
11244 pf->nb_mirror_rule--;
11246 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11253 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11256 uint64_t systim_cycles;
11258 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11259 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11262 return systim_cycles;
11266 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11268 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11269 uint64_t rx_tstamp;
11271 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11272 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11279 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11281 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11282 uint64_t tx_tstamp;
11284 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11285 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11292 i40e_start_timecounters(struct rte_eth_dev *dev)
11294 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11295 struct i40e_adapter *adapter = dev->data->dev_private;
11296 struct rte_eth_link link;
11297 uint32_t tsync_inc_l;
11298 uint32_t tsync_inc_h;
11300 /* Get current link speed. */
11301 i40e_dev_link_update(dev, 1);
11302 rte_eth_linkstatus_get(dev, &link);
11304 switch (link.link_speed) {
11305 case ETH_SPEED_NUM_40G:
11306 case ETH_SPEED_NUM_25G:
11307 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11308 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11310 case ETH_SPEED_NUM_10G:
11311 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11312 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11314 case ETH_SPEED_NUM_1G:
11315 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11316 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11323 /* Set the timesync increment value. */
11324 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11325 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11327 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11328 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11329 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11331 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11332 adapter->systime_tc.cc_shift = 0;
11333 adapter->systime_tc.nsec_mask = 0;
11335 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11336 adapter->rx_tstamp_tc.cc_shift = 0;
11337 adapter->rx_tstamp_tc.nsec_mask = 0;
11339 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11340 adapter->tx_tstamp_tc.cc_shift = 0;
11341 adapter->tx_tstamp_tc.nsec_mask = 0;
11345 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11347 struct i40e_adapter *adapter = dev->data->dev_private;
11349 adapter->systime_tc.nsec += delta;
11350 adapter->rx_tstamp_tc.nsec += delta;
11351 adapter->tx_tstamp_tc.nsec += delta;
11357 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11360 struct i40e_adapter *adapter = dev->data->dev_private;
11362 ns = rte_timespec_to_ns(ts);
11364 /* Set the timecounters to a new value. */
11365 adapter->systime_tc.nsec = ns;
11366 adapter->rx_tstamp_tc.nsec = ns;
11367 adapter->tx_tstamp_tc.nsec = ns;
11373 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11375 uint64_t ns, systime_cycles;
11376 struct i40e_adapter *adapter = dev->data->dev_private;
11378 systime_cycles = i40e_read_systime_cyclecounter(dev);
11379 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11380 *ts = rte_ns_to_timespec(ns);
11386 i40e_timesync_enable(struct rte_eth_dev *dev)
11388 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11389 uint32_t tsync_ctl_l;
11390 uint32_t tsync_ctl_h;
11392 /* Stop the timesync system time. */
11393 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11394 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11395 /* Reset the timesync system time value. */
11396 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11397 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11399 i40e_start_timecounters(dev);
11401 /* Clear timesync registers. */
11402 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11403 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11404 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11405 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11406 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11407 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11409 /* Enable timestamping of PTP packets. */
11410 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11411 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11413 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11414 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11415 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11417 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11418 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11424 i40e_timesync_disable(struct rte_eth_dev *dev)
11426 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11427 uint32_t tsync_ctl_l;
11428 uint32_t tsync_ctl_h;
11430 /* Disable timestamping of transmitted PTP packets. */
11431 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11432 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11434 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11435 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11437 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11438 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11440 /* Reset the timesync increment value. */
11441 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11442 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11448 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11449 struct timespec *timestamp, uint32_t flags)
11451 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11452 struct i40e_adapter *adapter = dev->data->dev_private;
11453 uint32_t sync_status;
11454 uint32_t index = flags & 0x03;
11455 uint64_t rx_tstamp_cycles;
11458 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11459 if ((sync_status & (1 << index)) == 0)
11462 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11463 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11464 *timestamp = rte_ns_to_timespec(ns);
11470 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11471 struct timespec *timestamp)
11473 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11474 struct i40e_adapter *adapter = dev->data->dev_private;
11475 uint32_t sync_status;
11476 uint64_t tx_tstamp_cycles;
11479 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11480 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11483 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11484 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11485 *timestamp = rte_ns_to_timespec(ns);
11491 * i40e_parse_dcb_configure - parse dcb configure from user
11492 * @dev: the device being configured
11493 * @dcb_cfg: pointer of the result of parse
11494 * @*tc_map: bit map of enabled traffic classes
11496 * Returns 0 on success, negative value on failure
11499 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11500 struct i40e_dcbx_config *dcb_cfg,
11503 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11504 uint8_t i, tc_bw, bw_lf;
11506 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11508 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11509 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11510 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11514 /* assume each tc has the same bw */
11515 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11516 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11517 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11518 /* to ensure the sum of tcbw is equal to 100 */
11519 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11520 for (i = 0; i < bw_lf; i++)
11521 dcb_cfg->etscfg.tcbwtable[i]++;
11523 /* assume each tc has the same Transmission Selection Algorithm */
11524 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11525 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11527 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11528 dcb_cfg->etscfg.prioritytable[i] =
11529 dcb_rx_conf->dcb_tc[i];
11531 /* FW needs one App to configure HW */
11532 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11533 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11534 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11535 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11537 if (dcb_rx_conf->nb_tcs == 0)
11538 *tc_map = 1; /* tc0 only */
11540 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11542 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11543 dcb_cfg->pfc.willing = 0;
11544 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11545 dcb_cfg->pfc.pfcenable = *tc_map;
11551 static enum i40e_status_code
11552 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11553 struct i40e_aqc_vsi_properties_data *info,
11554 uint8_t enabled_tcmap)
11556 enum i40e_status_code ret;
11557 int i, total_tc = 0;
11558 uint16_t qpnum_per_tc, bsf, qp_idx;
11559 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11560 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11561 uint16_t used_queues;
11563 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11564 if (ret != I40E_SUCCESS)
11567 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11568 if (enabled_tcmap & (1 << i))
11573 vsi->enabled_tc = enabled_tcmap;
11575 /* different VSI has different queues assigned */
11576 if (vsi->type == I40E_VSI_MAIN)
11577 used_queues = dev_data->nb_rx_queues -
11578 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11579 else if (vsi->type == I40E_VSI_VMDQ2)
11580 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11582 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11583 return I40E_ERR_NO_AVAILABLE_VSI;
11586 qpnum_per_tc = used_queues / total_tc;
11587 /* Number of queues per enabled TC */
11588 if (qpnum_per_tc == 0) {
11589 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11590 return I40E_ERR_INVALID_QP_ID;
11592 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11593 I40E_MAX_Q_PER_TC);
11594 bsf = rte_bsf32(qpnum_per_tc);
11597 * Configure TC and queue mapping parameters, for enabled TC,
11598 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11599 * default queue will serve it.
11602 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11603 if (vsi->enabled_tc & (1 << i)) {
11604 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11605 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11606 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11607 qp_idx += qpnum_per_tc;
11609 info->tc_mapping[i] = 0;
11612 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11613 if (vsi->type == I40E_VSI_SRIOV) {
11614 info->mapping_flags |=
11615 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11616 for (i = 0; i < vsi->nb_qps; i++)
11617 info->queue_mapping[i] =
11618 rte_cpu_to_le_16(vsi->base_queue + i);
11620 info->mapping_flags |=
11621 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11622 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11624 info->valid_sections |=
11625 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11627 return I40E_SUCCESS;
11631 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11632 * @veb: VEB to be configured
11633 * @tc_map: enabled TC bitmap
11635 * Returns 0 on success, negative value on failure
11637 static enum i40e_status_code
11638 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11640 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11641 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11642 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11643 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11644 enum i40e_status_code ret = I40E_SUCCESS;
11648 /* Check if enabled_tc is same as existing or new TCs */
11649 if (veb->enabled_tc == tc_map)
11652 /* configure tc bandwidth */
11653 memset(&veb_bw, 0, sizeof(veb_bw));
11654 veb_bw.tc_valid_bits = tc_map;
11655 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11656 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11657 if (tc_map & BIT_ULL(i))
11658 veb_bw.tc_bw_share_credits[i] = 1;
11660 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11664 "AQ command Config switch_comp BW allocation per TC failed = %d",
11665 hw->aq.asq_last_status);
11669 memset(&ets_query, 0, sizeof(ets_query));
11670 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11672 if (ret != I40E_SUCCESS) {
11674 "Failed to get switch_comp ETS configuration %u",
11675 hw->aq.asq_last_status);
11678 memset(&bw_query, 0, sizeof(bw_query));
11679 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11681 if (ret != I40E_SUCCESS) {
11683 "Failed to get switch_comp bandwidth configuration %u",
11684 hw->aq.asq_last_status);
11688 /* store and print out BW info */
11689 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11690 veb->bw_info.bw_max = ets_query.tc_bw_max;
11691 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11692 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11693 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11694 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11695 I40E_16_BIT_WIDTH);
11696 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11697 veb->bw_info.bw_ets_share_credits[i] =
11698 bw_query.tc_bw_share_credits[i];
11699 veb->bw_info.bw_ets_credits[i] =
11700 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11701 /* 4 bits per TC, 4th bit is reserved */
11702 veb->bw_info.bw_ets_max[i] =
11703 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11704 RTE_LEN2MASK(3, uint8_t));
11705 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11706 veb->bw_info.bw_ets_share_credits[i]);
11707 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11708 veb->bw_info.bw_ets_credits[i]);
11709 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11710 veb->bw_info.bw_ets_max[i]);
11713 veb->enabled_tc = tc_map;
11720 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11721 * @vsi: VSI to be configured
11722 * @tc_map: enabled TC bitmap
11724 * Returns 0 on success, negative value on failure
11726 static enum i40e_status_code
11727 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11729 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11730 struct i40e_vsi_context ctxt;
11731 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11732 enum i40e_status_code ret = I40E_SUCCESS;
11735 /* Check if enabled_tc is same as existing or new TCs */
11736 if (vsi->enabled_tc == tc_map)
11739 /* configure tc bandwidth */
11740 memset(&bw_data, 0, sizeof(bw_data));
11741 bw_data.tc_valid_bits = tc_map;
11742 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11743 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11744 if (tc_map & BIT_ULL(i))
11745 bw_data.tc_bw_credits[i] = 1;
11747 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11750 "AQ command Config VSI BW allocation per TC failed = %d",
11751 hw->aq.asq_last_status);
11754 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11755 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11757 /* Update Queue Pairs Mapping for currently enabled UPs */
11758 ctxt.seid = vsi->seid;
11759 ctxt.pf_num = hw->pf_id;
11761 ctxt.uplink_seid = vsi->uplink_seid;
11762 ctxt.info = vsi->info;
11764 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11768 /* Update the VSI after updating the VSI queue-mapping information */
11769 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11771 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11772 hw->aq.asq_last_status);
11775 /* update the local VSI info with updated queue map */
11776 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11777 sizeof(vsi->info.tc_mapping));
11778 rte_memcpy(&vsi->info.queue_mapping,
11779 &ctxt.info.queue_mapping,
11780 sizeof(vsi->info.queue_mapping));
11781 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11782 vsi->info.valid_sections = 0;
11784 /* query and update current VSI BW information */
11785 ret = i40e_vsi_get_bw_config(vsi);
11788 "Failed updating vsi bw info, err %s aq_err %s",
11789 i40e_stat_str(hw, ret),
11790 i40e_aq_str(hw, hw->aq.asq_last_status));
11794 vsi->enabled_tc = tc_map;
11801 * i40e_dcb_hw_configure - program the dcb setting to hw
11802 * @pf: pf the configuration is taken on
11803 * @new_cfg: new configuration
11804 * @tc_map: enabled TC bitmap
11806 * Returns 0 on success, negative value on failure
11808 static enum i40e_status_code
11809 i40e_dcb_hw_configure(struct i40e_pf *pf,
11810 struct i40e_dcbx_config *new_cfg,
11813 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11814 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11815 struct i40e_vsi *main_vsi = pf->main_vsi;
11816 struct i40e_vsi_list *vsi_list;
11817 enum i40e_status_code ret;
11821 /* Use the FW API if FW > v4.4*/
11822 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11823 (hw->aq.fw_maj_ver >= 5))) {
11825 "FW < v4.4, can not use FW LLDP API to configure DCB");
11826 return I40E_ERR_FIRMWARE_API_VERSION;
11829 /* Check if need reconfiguration */
11830 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11831 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11832 return I40E_SUCCESS;
11835 /* Copy the new config to the current config */
11836 *old_cfg = *new_cfg;
11837 old_cfg->etsrec = old_cfg->etscfg;
11838 ret = i40e_set_dcb_config(hw);
11840 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11841 i40e_stat_str(hw, ret),
11842 i40e_aq_str(hw, hw->aq.asq_last_status));
11845 /* set receive Arbiter to RR mode and ETS scheme by default */
11846 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11847 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11848 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11849 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11850 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11851 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11852 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11853 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11854 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11855 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11856 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11857 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11858 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11860 /* get local mib to check whether it is configured correctly */
11862 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11863 /* Get Local DCB Config */
11864 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11865 &hw->local_dcbx_config);
11867 /* if Veb is created, need to update TC of it at first */
11868 if (main_vsi->veb) {
11869 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11871 PMD_INIT_LOG(WARNING,
11872 "Failed configuring TC for VEB seid=%d",
11873 main_vsi->veb->seid);
11875 /* Update each VSI */
11876 i40e_vsi_config_tc(main_vsi, tc_map);
11877 if (main_vsi->veb) {
11878 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11879 /* Beside main VSI and VMDQ VSIs, only enable default
11880 * TC for other VSIs
11882 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11883 ret = i40e_vsi_config_tc(vsi_list->vsi,
11886 ret = i40e_vsi_config_tc(vsi_list->vsi,
11887 I40E_DEFAULT_TCMAP);
11889 PMD_INIT_LOG(WARNING,
11890 "Failed configuring TC for VSI seid=%d",
11891 vsi_list->vsi->seid);
11895 return I40E_SUCCESS;
11899 * i40e_dcb_init_configure - initial dcb config
11900 * @dev: device being configured
11901 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11903 * Returns 0 on success, negative value on failure
11906 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11912 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11913 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11917 /* DCB initialization:
11918 * Update DCB configuration from the Firmware and configure
11919 * LLDP MIB change event.
11921 if (sw_dcb == TRUE) {
11922 /* Stopping lldp is necessary for DPDK, but it will cause
11923 * DCB init failed. For i40e_init_dcb(), the prerequisite
11924 * for successful initialization of DCB is that LLDP is
11925 * enabled. So it is needed to start lldp before DCB init
11926 * and stop it after initialization.
11928 ret = i40e_aq_start_lldp(hw, true, NULL);
11929 if (ret != I40E_SUCCESS)
11930 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11932 ret = i40e_init_dcb(hw, true);
11933 /* If lldp agent is stopped, the return value from
11934 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11935 * adminq status. Otherwise, it should return success.
11937 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11938 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11939 memset(&hw->local_dcbx_config, 0,
11940 sizeof(struct i40e_dcbx_config));
11941 /* set dcb default configuration */
11942 hw->local_dcbx_config.etscfg.willing = 0;
11943 hw->local_dcbx_config.etscfg.maxtcs = 0;
11944 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11945 hw->local_dcbx_config.etscfg.tsatable[0] =
11947 /* all UPs mapping to TC0 */
11948 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11949 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11950 hw->local_dcbx_config.etsrec =
11951 hw->local_dcbx_config.etscfg;
11952 hw->local_dcbx_config.pfc.willing = 0;
11953 hw->local_dcbx_config.pfc.pfccap =
11954 I40E_MAX_TRAFFIC_CLASS;
11955 /* FW needs one App to configure HW */
11956 hw->local_dcbx_config.numapps = 1;
11957 hw->local_dcbx_config.app[0].selector =
11958 I40E_APP_SEL_ETHTYPE;
11959 hw->local_dcbx_config.app[0].priority = 3;
11960 hw->local_dcbx_config.app[0].protocolid =
11961 I40E_APP_PROTOID_FCOE;
11962 ret = i40e_set_dcb_config(hw);
11965 "default dcb config fails. err = %d, aq_err = %d.",
11966 ret, hw->aq.asq_last_status);
11971 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11972 ret, hw->aq.asq_last_status);
11976 if (i40e_need_stop_lldp(dev)) {
11977 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11978 if (ret != I40E_SUCCESS)
11979 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11982 ret = i40e_aq_start_lldp(hw, true, NULL);
11983 if (ret != I40E_SUCCESS)
11984 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11986 ret = i40e_init_dcb(hw, true);
11988 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11990 "HW doesn't support DCBX offload.");
11995 "DCBX configuration failed, err = %d, aq_err = %d.",
11996 ret, hw->aq.asq_last_status);
12004 * i40e_dcb_setup - setup dcb related config
12005 * @dev: device being configured
12007 * Returns 0 on success, negative value on failure
12010 i40e_dcb_setup(struct rte_eth_dev *dev)
12012 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12013 struct i40e_dcbx_config dcb_cfg;
12014 uint8_t tc_map = 0;
12017 if ((pf->flags & I40E_FLAG_DCB) == 0) {
12018 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12022 if (pf->vf_num != 0)
12023 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12025 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12027 PMD_INIT_LOG(ERR, "invalid dcb config");
12030 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12032 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12040 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12041 struct rte_eth_dcb_info *dcb_info)
12043 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12045 struct i40e_vsi *vsi = pf->main_vsi;
12046 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12047 uint16_t bsf, tc_mapping;
12050 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12051 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12053 dcb_info->nb_tcs = 1;
12054 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12055 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12056 for (i = 0; i < dcb_info->nb_tcs; i++)
12057 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12059 /* get queue mapping if vmdq is disabled */
12060 if (!pf->nb_cfg_vmdq_vsi) {
12061 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12062 if (!(vsi->enabled_tc & (1 << i)))
12064 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12065 dcb_info->tc_queue.tc_rxq[j][i].base =
12066 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12067 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12068 dcb_info->tc_queue.tc_txq[j][i].base =
12069 dcb_info->tc_queue.tc_rxq[j][i].base;
12070 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12071 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12072 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12073 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12074 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12079 /* get queue mapping if vmdq is enabled */
12081 vsi = pf->vmdq[j].vsi;
12082 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12083 if (!(vsi->enabled_tc & (1 << i)))
12085 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12086 dcb_info->tc_queue.tc_rxq[j][i].base =
12087 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12088 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12089 dcb_info->tc_queue.tc_txq[j][i].base =
12090 dcb_info->tc_queue.tc_rxq[j][i].base;
12091 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12092 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12093 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12094 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12095 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12098 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12103 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12105 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12106 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12108 uint16_t msix_intr;
12110 msix_intr = intr_handle->intr_vec[queue_id];
12111 if (msix_intr == I40E_MISC_VEC_ID)
12112 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12113 I40E_PFINT_DYN_CTL0_INTENA_MASK |
12114 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12115 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12118 I40E_PFINT_DYN_CTLN(msix_intr -
12119 I40E_RX_VEC_START),
12120 I40E_PFINT_DYN_CTLN_INTENA_MASK |
12121 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12122 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12124 I40E_WRITE_FLUSH(hw);
12125 rte_intr_ack(&pci_dev->intr_handle);
12131 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12133 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12134 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12135 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12136 uint16_t msix_intr;
12138 msix_intr = intr_handle->intr_vec[queue_id];
12139 if (msix_intr == I40E_MISC_VEC_ID)
12140 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12141 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12144 I40E_PFINT_DYN_CTLN(msix_intr -
12145 I40E_RX_VEC_START),
12146 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12147 I40E_WRITE_FLUSH(hw);
12153 * This function is used to check if the register is valid.
12154 * Below is the valid registers list for X722 only:
12158 * 0x208e00--0x209000
12159 * 0x20be00--0x20c000
12160 * 0x263c00--0x264000
12161 * 0x265c00--0x266000
12163 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12165 if ((type != I40E_MAC_X722) &&
12166 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12167 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12168 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12169 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12170 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12171 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12172 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12178 static int i40e_get_regs(struct rte_eth_dev *dev,
12179 struct rte_dev_reg_info *regs)
12181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12182 uint32_t *ptr_data = regs->data;
12183 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12184 const struct i40e_reg_info *reg_info;
12186 if (ptr_data == NULL) {
12187 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12188 regs->width = sizeof(uint32_t);
12192 /* The first few registers have to be read using AQ operations */
12194 while (i40e_regs_adminq[reg_idx].name) {
12195 reg_info = &i40e_regs_adminq[reg_idx++];
12196 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12198 arr_idx2 <= reg_info->count2;
12200 reg_offset = arr_idx * reg_info->stride1 +
12201 arr_idx2 * reg_info->stride2;
12202 reg_offset += reg_info->base_addr;
12203 ptr_data[reg_offset >> 2] =
12204 i40e_read_rx_ctl(hw, reg_offset);
12208 /* The remaining registers can be read using primitives */
12210 while (i40e_regs_others[reg_idx].name) {
12211 reg_info = &i40e_regs_others[reg_idx++];
12212 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12214 arr_idx2 <= reg_info->count2;
12216 reg_offset = arr_idx * reg_info->stride1 +
12217 arr_idx2 * reg_info->stride2;
12218 reg_offset += reg_info->base_addr;
12219 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12220 ptr_data[reg_offset >> 2] = 0;
12222 ptr_data[reg_offset >> 2] =
12223 I40E_READ_REG(hw, reg_offset);
12230 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12234 /* Convert word count to byte count */
12235 return hw->nvm.sr_size << 1;
12238 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12239 struct rte_dev_eeprom_info *eeprom)
12241 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12242 uint16_t *data = eeprom->data;
12243 uint16_t offset, length, cnt_words;
12246 offset = eeprom->offset >> 1;
12247 length = eeprom->length >> 1;
12248 cnt_words = length;
12250 if (offset > hw->nvm.sr_size ||
12251 offset + length > hw->nvm.sr_size) {
12252 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12256 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12258 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12259 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12260 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12267 static int i40e_get_module_info(struct rte_eth_dev *dev,
12268 struct rte_eth_dev_module_info *modinfo)
12270 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12271 uint32_t sff8472_comp = 0;
12272 uint32_t sff8472_swap = 0;
12273 uint32_t sff8636_rev = 0;
12274 i40e_status status;
12277 /* Check if firmware supports reading module EEPROM. */
12278 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12280 "Module EEPROM memory read not supported. "
12281 "Please update the NVM image.\n");
12285 status = i40e_update_link_info(hw);
12289 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12291 "Cannot read module EEPROM memory. "
12292 "No module connected.\n");
12296 type = hw->phy.link_info.module_type[0];
12299 case I40E_MODULE_TYPE_SFP:
12300 status = i40e_aq_get_phy_register(hw,
12301 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12302 I40E_I2C_EEPROM_DEV_ADDR, 1,
12303 I40E_MODULE_SFF_8472_COMP,
12304 &sff8472_comp, NULL);
12308 status = i40e_aq_get_phy_register(hw,
12309 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12310 I40E_I2C_EEPROM_DEV_ADDR, 1,
12311 I40E_MODULE_SFF_8472_SWAP,
12312 &sff8472_swap, NULL);
12316 /* Check if the module requires address swap to access
12317 * the other EEPROM memory page.
12319 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12320 PMD_DRV_LOG(WARNING,
12321 "Module address swap to access "
12322 "page 0xA2 is not supported.\n");
12323 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12324 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12325 } else if (sff8472_comp == 0x00) {
12326 /* Module is not SFF-8472 compliant */
12327 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12328 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12330 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12331 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12334 case I40E_MODULE_TYPE_QSFP_PLUS:
12335 /* Read from memory page 0. */
12336 status = i40e_aq_get_phy_register(hw,
12337 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12339 I40E_MODULE_REVISION_ADDR,
12340 &sff8636_rev, NULL);
12343 /* Determine revision compliance byte */
12344 if (sff8636_rev > 0x02) {
12345 /* Module is SFF-8636 compliant */
12346 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12347 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12349 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12350 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12353 case I40E_MODULE_TYPE_QSFP28:
12354 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12355 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12358 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12364 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12365 struct rte_dev_eeprom_info *info)
12367 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12368 bool is_sfp = false;
12369 i40e_status status;
12371 uint32_t value = 0;
12374 if (!info || !info->length || !info->data)
12377 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12381 for (i = 0; i < info->length; i++) {
12382 u32 offset = i + info->offset;
12383 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12385 /* Check if we need to access the other memory page */
12387 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12388 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12389 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12392 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12393 /* Compute memory page number and offset. */
12394 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12398 status = i40e_aq_get_phy_register(hw,
12399 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12400 addr, 1, offset, &value, NULL);
12403 data[i] = (uint8_t)value;
12408 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12409 struct rte_ether_addr *mac_addr)
12411 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12412 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12413 struct i40e_vsi *vsi = pf->main_vsi;
12414 struct i40e_mac_filter_info mac_filter;
12415 struct i40e_mac_filter *f;
12418 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12419 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12423 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12424 if (rte_is_same_ether_addr(&pf->dev_addr,
12425 &f->mac_info.mac_addr))
12430 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12434 mac_filter = f->mac_info;
12435 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12436 if (ret != I40E_SUCCESS) {
12437 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12440 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12441 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12442 if (ret != I40E_SUCCESS) {
12443 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12446 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12448 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12449 mac_addr->addr_bytes, NULL);
12450 if (ret != I40E_SUCCESS) {
12451 PMD_DRV_LOG(ERR, "Failed to change mac");
12459 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12461 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12462 struct rte_eth_dev_data *dev_data = pf->dev_data;
12463 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12466 /* check if mtu is within the allowed range */
12467 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12470 /* mtu setting is forbidden if port is start */
12471 if (dev_data->dev_started) {
12472 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12473 dev_data->port_id);
12477 if (frame_size > RTE_ETHER_MAX_LEN)
12478 dev_data->dev_conf.rxmode.offloads |=
12479 DEV_RX_OFFLOAD_JUMBO_FRAME;
12481 dev_data->dev_conf.rxmode.offloads &=
12482 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12484 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12489 /* Restore ethertype filter */
12491 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12493 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12494 struct i40e_ethertype_filter_list
12495 *ethertype_list = &pf->ethertype.ethertype_list;
12496 struct i40e_ethertype_filter *f;
12497 struct i40e_control_filter_stats stats;
12500 TAILQ_FOREACH(f, ethertype_list, rules) {
12502 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12503 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12504 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12505 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12506 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12508 memset(&stats, 0, sizeof(stats));
12509 i40e_aq_add_rem_control_packet_filter(hw,
12510 f->input.mac_addr.addr_bytes,
12511 f->input.ether_type,
12512 flags, pf->main_vsi->seid,
12513 f->queue, 1, &stats, NULL);
12515 PMD_DRV_LOG(INFO, "Ethertype filter:"
12516 " mac_etype_used = %u, etype_used = %u,"
12517 " mac_etype_free = %u, etype_free = %u",
12518 stats.mac_etype_used, stats.etype_used,
12519 stats.mac_etype_free, stats.etype_free);
12522 /* Restore tunnel filter */
12524 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12526 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12527 struct i40e_vsi *vsi;
12528 struct i40e_pf_vf *vf;
12529 struct i40e_tunnel_filter_list
12530 *tunnel_list = &pf->tunnel.tunnel_list;
12531 struct i40e_tunnel_filter *f;
12532 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12533 bool big_buffer = 0;
12535 TAILQ_FOREACH(f, tunnel_list, rules) {
12537 vsi = pf->main_vsi;
12539 vf = &pf->vfs[f->vf_id];
12542 memset(&cld_filter, 0, sizeof(cld_filter));
12543 rte_ether_addr_copy((struct rte_ether_addr *)
12544 &f->input.outer_mac,
12545 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12546 rte_ether_addr_copy((struct rte_ether_addr *)
12547 &f->input.inner_mac,
12548 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12549 cld_filter.element.inner_vlan = f->input.inner_vlan;
12550 cld_filter.element.flags = f->input.flags;
12551 cld_filter.element.tenant_id = f->input.tenant_id;
12552 cld_filter.element.queue_number = f->queue;
12553 rte_memcpy(cld_filter.general_fields,
12554 f->input.general_fields,
12555 sizeof(f->input.general_fields));
12557 if (((f->input.flags &
12558 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12559 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12561 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12562 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12564 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12565 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12569 i40e_aq_add_cloud_filters_bb(hw,
12570 vsi->seid, &cld_filter, 1);
12572 i40e_aq_add_cloud_filters(hw, vsi->seid,
12573 &cld_filter.element, 1);
12577 /* Restore RSS filter */
12579 i40e_rss_filter_restore(struct i40e_pf *pf)
12581 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12582 struct i40e_rss_filter *filter;
12584 TAILQ_FOREACH(filter, list, next) {
12585 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12590 i40e_filter_restore(struct i40e_pf *pf)
12592 i40e_ethertype_filter_restore(pf);
12593 i40e_tunnel_filter_restore(pf);
12594 i40e_fdir_filter_restore(pf);
12595 i40e_rss_filter_restore(pf);
12599 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12601 if (strcmp(dev->device->driver->name, drv->driver.name))
12608 is_i40e_supported(struct rte_eth_dev *dev)
12610 return is_device_supported(dev, &rte_i40e_pmd);
12613 struct i40e_customized_pctype*
12614 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12618 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12619 if (pf->customized_pctype[i].index == index)
12620 return &pf->customized_pctype[i];
12626 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12627 uint32_t pkg_size, uint32_t proto_num,
12628 struct rte_pmd_i40e_proto_info *proto,
12629 enum rte_pmd_i40e_package_op op)
12631 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12632 uint32_t pctype_num;
12633 struct rte_pmd_i40e_ptype_info *pctype;
12634 uint32_t buff_size;
12635 struct i40e_customized_pctype *new_pctype = NULL;
12637 uint8_t pctype_value;
12642 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12643 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12644 PMD_DRV_LOG(ERR, "Unsupported operation.");
12648 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12649 (uint8_t *)&pctype_num, sizeof(pctype_num),
12650 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12652 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12656 PMD_DRV_LOG(INFO, "No new pctype added");
12660 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12661 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12663 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12666 /* get information about new pctype list */
12667 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12668 (uint8_t *)pctype, buff_size,
12669 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12671 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12676 /* Update customized pctype. */
12677 for (i = 0; i < pctype_num; i++) {
12678 pctype_value = pctype[i].ptype_id;
12679 memset(name, 0, sizeof(name));
12680 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12681 proto_id = pctype[i].protocols[j];
12682 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12684 for (n = 0; n < proto_num; n++) {
12685 if (proto[n].proto_id != proto_id)
12687 strlcat(name, proto[n].name, sizeof(name));
12688 strlcat(name, "_", sizeof(name));
12692 name[strlen(name) - 1] = '\0';
12693 PMD_DRV_LOG(INFO, "name = %s\n", name);
12694 if (!strcmp(name, "GTPC"))
12696 i40e_find_customized_pctype(pf,
12697 I40E_CUSTOMIZED_GTPC);
12698 else if (!strcmp(name, "GTPU_IPV4"))
12700 i40e_find_customized_pctype(pf,
12701 I40E_CUSTOMIZED_GTPU_IPV4);
12702 else if (!strcmp(name, "GTPU_IPV6"))
12704 i40e_find_customized_pctype(pf,
12705 I40E_CUSTOMIZED_GTPU_IPV6);
12706 else if (!strcmp(name, "GTPU"))
12708 i40e_find_customized_pctype(pf,
12709 I40E_CUSTOMIZED_GTPU);
12710 else if (!strcmp(name, "IPV4_L2TPV3"))
12712 i40e_find_customized_pctype(pf,
12713 I40E_CUSTOMIZED_IPV4_L2TPV3);
12714 else if (!strcmp(name, "IPV6_L2TPV3"))
12716 i40e_find_customized_pctype(pf,
12717 I40E_CUSTOMIZED_IPV6_L2TPV3);
12718 else if (!strcmp(name, "IPV4_ESP"))
12720 i40e_find_customized_pctype(pf,
12721 I40E_CUSTOMIZED_ESP_IPV4);
12722 else if (!strcmp(name, "IPV6_ESP"))
12724 i40e_find_customized_pctype(pf,
12725 I40E_CUSTOMIZED_ESP_IPV6);
12726 else if (!strcmp(name, "IPV4_UDP_ESP"))
12728 i40e_find_customized_pctype(pf,
12729 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12730 else if (!strcmp(name, "IPV6_UDP_ESP"))
12732 i40e_find_customized_pctype(pf,
12733 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12734 else if (!strcmp(name, "IPV4_AH"))
12736 i40e_find_customized_pctype(pf,
12737 I40E_CUSTOMIZED_AH_IPV4);
12738 else if (!strcmp(name, "IPV6_AH"))
12740 i40e_find_customized_pctype(pf,
12741 I40E_CUSTOMIZED_AH_IPV6);
12743 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12744 new_pctype->pctype = pctype_value;
12745 new_pctype->valid = true;
12747 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12748 new_pctype->valid = false;
12758 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12759 uint32_t pkg_size, uint32_t proto_num,
12760 struct rte_pmd_i40e_proto_info *proto,
12761 enum rte_pmd_i40e_package_op op)
12763 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12764 uint16_t port_id = dev->data->port_id;
12765 uint32_t ptype_num;
12766 struct rte_pmd_i40e_ptype_info *ptype;
12767 uint32_t buff_size;
12769 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12774 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12775 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12776 PMD_DRV_LOG(ERR, "Unsupported operation.");
12780 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12781 rte_pmd_i40e_ptype_mapping_reset(port_id);
12785 /* get information about new ptype num */
12786 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12787 (uint8_t *)&ptype_num, sizeof(ptype_num),
12788 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12790 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12794 PMD_DRV_LOG(INFO, "No new ptype added");
12798 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12799 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12801 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12805 /* get information about new ptype list */
12806 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12807 (uint8_t *)ptype, buff_size,
12808 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12810 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12815 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12816 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12817 if (!ptype_mapping) {
12818 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12823 /* Update ptype mapping table. */
12824 for (i = 0; i < ptype_num; i++) {
12825 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12826 ptype_mapping[i].sw_ptype = 0;
12828 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12829 proto_id = ptype[i].protocols[j];
12830 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12832 for (n = 0; n < proto_num; n++) {
12833 if (proto[n].proto_id != proto_id)
12835 memset(name, 0, sizeof(name));
12836 strcpy(name, proto[n].name);
12837 PMD_DRV_LOG(INFO, "name = %s\n", name);
12838 if (!strncasecmp(name, "PPPOE", 5))
12839 ptype_mapping[i].sw_ptype |=
12840 RTE_PTYPE_L2_ETHER_PPPOE;
12841 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12843 ptype_mapping[i].sw_ptype |=
12844 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12845 ptype_mapping[i].sw_ptype |=
12847 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12849 ptype_mapping[i].sw_ptype |=
12850 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12851 ptype_mapping[i].sw_ptype |=
12852 RTE_PTYPE_INNER_L4_FRAG;
12853 } else if (!strncasecmp(name, "OIPV4", 5)) {
12854 ptype_mapping[i].sw_ptype |=
12855 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12857 } else if (!strncasecmp(name, "IPV4", 4) &&
12859 ptype_mapping[i].sw_ptype |=
12860 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12861 else if (!strncasecmp(name, "IPV4", 4) &&
12863 ptype_mapping[i].sw_ptype |=
12864 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12865 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12867 ptype_mapping[i].sw_ptype |=
12868 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12869 ptype_mapping[i].sw_ptype |=
12871 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12873 ptype_mapping[i].sw_ptype |=
12874 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12875 ptype_mapping[i].sw_ptype |=
12876 RTE_PTYPE_INNER_L4_FRAG;
12877 } else if (!strncasecmp(name, "OIPV6", 5)) {
12878 ptype_mapping[i].sw_ptype |=
12879 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12881 } else if (!strncasecmp(name, "IPV6", 4) &&
12883 ptype_mapping[i].sw_ptype |=
12884 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12885 else if (!strncasecmp(name, "IPV6", 4) &&
12887 ptype_mapping[i].sw_ptype |=
12888 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12889 else if (!strncasecmp(name, "UDP", 3) &&
12891 ptype_mapping[i].sw_ptype |=
12893 else if (!strncasecmp(name, "UDP", 3) &&
12895 ptype_mapping[i].sw_ptype |=
12896 RTE_PTYPE_INNER_L4_UDP;
12897 else if (!strncasecmp(name, "TCP", 3) &&
12899 ptype_mapping[i].sw_ptype |=
12901 else if (!strncasecmp(name, "TCP", 3) &&
12903 ptype_mapping[i].sw_ptype |=
12904 RTE_PTYPE_INNER_L4_TCP;
12905 else if (!strncasecmp(name, "SCTP", 4) &&
12907 ptype_mapping[i].sw_ptype |=
12909 else if (!strncasecmp(name, "SCTP", 4) &&
12911 ptype_mapping[i].sw_ptype |=
12912 RTE_PTYPE_INNER_L4_SCTP;
12913 else if ((!strncasecmp(name, "ICMP", 4) ||
12914 !strncasecmp(name, "ICMPV6", 6)) &&
12916 ptype_mapping[i].sw_ptype |=
12918 else if ((!strncasecmp(name, "ICMP", 4) ||
12919 !strncasecmp(name, "ICMPV6", 6)) &&
12921 ptype_mapping[i].sw_ptype |=
12922 RTE_PTYPE_INNER_L4_ICMP;
12923 else if (!strncasecmp(name, "GTPC", 4)) {
12924 ptype_mapping[i].sw_ptype |=
12925 RTE_PTYPE_TUNNEL_GTPC;
12927 } else if (!strncasecmp(name, "GTPU", 4)) {
12928 ptype_mapping[i].sw_ptype |=
12929 RTE_PTYPE_TUNNEL_GTPU;
12931 } else if (!strncasecmp(name, "ESP", 3)) {
12932 ptype_mapping[i].sw_ptype |=
12933 RTE_PTYPE_TUNNEL_ESP;
12935 } else if (!strncasecmp(name, "GRENAT", 6)) {
12936 ptype_mapping[i].sw_ptype |=
12937 RTE_PTYPE_TUNNEL_GRENAT;
12939 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12940 !strncasecmp(name, "L2TPV2", 6) ||
12941 !strncasecmp(name, "L2TPV3", 6)) {
12942 ptype_mapping[i].sw_ptype |=
12943 RTE_PTYPE_TUNNEL_L2TP;
12952 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12955 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12957 rte_free(ptype_mapping);
12963 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12964 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12967 uint32_t proto_num;
12968 struct rte_pmd_i40e_proto_info *proto;
12969 uint32_t buff_size;
12973 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12974 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12975 PMD_DRV_LOG(ERR, "Unsupported operation.");
12979 /* get information about protocol number */
12980 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12981 (uint8_t *)&proto_num, sizeof(proto_num),
12982 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12984 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12988 PMD_DRV_LOG(INFO, "No new protocol added");
12992 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12993 proto = rte_zmalloc("new_proto", buff_size, 0);
12995 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12999 /* get information about protocol list */
13000 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13001 (uint8_t *)proto, buff_size,
13002 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13004 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13009 /* Check if GTP is supported. */
13010 for (i = 0; i < proto_num; i++) {
13011 if (!strncmp(proto[i].name, "GTP", 3)) {
13012 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13013 pf->gtp_support = true;
13015 pf->gtp_support = false;
13020 /* Check if ESP is supported. */
13021 for (i = 0; i < proto_num; i++) {
13022 if (!strncmp(proto[i].name, "ESP", 3)) {
13023 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13024 pf->esp_support = true;
13026 pf->esp_support = false;
13031 /* Update customized pctype info */
13032 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13033 proto_num, proto, op);
13035 PMD_DRV_LOG(INFO, "No pctype is updated.");
13037 /* Update customized ptype info */
13038 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13039 proto_num, proto, op);
13041 PMD_DRV_LOG(INFO, "No ptype is updated.");
13046 /* Create a QinQ cloud filter
13048 * The Fortville NIC has limited resources for tunnel filters,
13049 * so we can only reuse existing filters.
13051 * In step 1 we define which Field Vector fields can be used for
13053 * As we do not have the inner tag defined as a field,
13054 * we have to define it first, by reusing one of L1 entries.
13056 * In step 2 we are replacing one of existing filter types with
13057 * a new one for QinQ.
13058 * As we reusing L1 and replacing L2, some of the default filter
13059 * types will disappear,which depends on L1 and L2 entries we reuse.
13061 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13063 * 1. Create L1 filter of outer vlan (12b) which will be in use
13064 * later when we define the cloud filter.
13065 * a. Valid_flags.replace_cloud = 0
13066 * b. Old_filter = 10 (Stag_Inner_Vlan)
13067 * c. New_filter = 0x10
13068 * d. TR bit = 0xff (optional, not used here)
13069 * e. Buffer – 2 entries:
13070 * i. Byte 0 = 8 (outer vlan FV index).
13072 * Byte 2-3 = 0x0fff
13073 * ii. Byte 0 = 37 (inner vlan FV index).
13075 * Byte 2-3 = 0x0fff
13078 * 2. Create cloud filter using two L1 filters entries: stag and
13079 * new filter(outer vlan+ inner vlan)
13080 * a. Valid_flags.replace_cloud = 1
13081 * b. Old_filter = 1 (instead of outer IP)
13082 * c. New_filter = 0x10
13083 * d. Buffer – 2 entries:
13084 * i. Byte 0 = 0x80 | 7 (valid | Stag).
13085 * Byte 1-3 = 0 (rsv)
13086 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13087 * Byte 9-11 = 0 (rsv)
13090 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13092 int ret = -ENOTSUP;
13093 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
13094 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
13095 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13096 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13098 if (pf->support_multi_driver) {
13099 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13104 memset(&filter_replace, 0,
13105 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13106 memset(&filter_replace_buf, 0,
13107 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13109 /* create L1 filter */
13110 filter_replace.old_filter_type =
13111 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13112 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13113 filter_replace.tr_bit = 0;
13115 /* Prepare the buffer, 2 entries */
13116 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13117 filter_replace_buf.data[0] |=
13118 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13119 /* Field Vector 12b mask */
13120 filter_replace_buf.data[2] = 0xff;
13121 filter_replace_buf.data[3] = 0x0f;
13122 filter_replace_buf.data[4] =
13123 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13124 filter_replace_buf.data[4] |=
13125 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13126 /* Field Vector 12b mask */
13127 filter_replace_buf.data[6] = 0xff;
13128 filter_replace_buf.data[7] = 0x0f;
13129 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13130 &filter_replace_buf);
13131 if (ret != I40E_SUCCESS)
13134 if (filter_replace.old_filter_type !=
13135 filter_replace.new_filter_type)
13136 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13137 " original: 0x%x, new: 0x%x",
13139 filter_replace.old_filter_type,
13140 filter_replace.new_filter_type);
13142 /* Apply the second L2 cloud filter */
13143 memset(&filter_replace, 0,
13144 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13145 memset(&filter_replace_buf, 0,
13146 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13148 /* create L2 filter, input for L2 filter will be L1 filter */
13149 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13150 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13151 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13153 /* Prepare the buffer, 2 entries */
13154 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13155 filter_replace_buf.data[0] |=
13156 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13157 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13158 filter_replace_buf.data[4] |=
13159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13160 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13161 &filter_replace_buf);
13162 if (!ret && (filter_replace.old_filter_type !=
13163 filter_replace.new_filter_type))
13164 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13165 " original: 0x%x, new: 0x%x",
13167 filter_replace.old_filter_type,
13168 filter_replace.new_filter_type);
13174 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13175 const struct rte_flow_action_rss *in)
13177 if (in->key_len > RTE_DIM(out->key) ||
13178 in->queue_num > RTE_DIM(out->queue))
13180 if (!in->key && in->key_len)
13182 out->conf = (struct rte_flow_action_rss){
13184 .level = in->level,
13185 .types = in->types,
13186 .key_len = in->key_len,
13187 .queue_num = in->queue_num,
13188 .queue = memcpy(out->queue, in->queue,
13189 sizeof(*in->queue) * in->queue_num),
13192 out->conf.key = memcpy(out->key, in->key, in->key_len);
13196 /* Write HENA register to enable hash */
13198 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13200 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13201 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13205 ret = i40e_set_rss_key(pf->main_vsi, key,
13206 rss_conf->conf.key_len);
13210 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13211 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13212 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13213 I40E_WRITE_FLUSH(hw);
13218 /* Configure hash input set */
13220 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13222 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13223 struct rte_eth_input_set_conf conf;
13228 static const struct {
13230 enum rte_eth_input_set_field field;
13231 } inset_match_table[] = {
13232 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13233 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13234 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13235 RTE_ETH_INPUT_SET_L3_DST_IP4},
13236 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13237 RTE_ETH_INPUT_SET_UNKNOWN},
13238 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13239 RTE_ETH_INPUT_SET_UNKNOWN},
13241 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13242 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13243 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13244 RTE_ETH_INPUT_SET_L3_DST_IP4},
13245 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13246 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13247 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13248 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13250 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13251 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13252 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13253 RTE_ETH_INPUT_SET_L3_DST_IP4},
13254 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13255 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13256 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13257 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13259 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13260 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13261 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13262 RTE_ETH_INPUT_SET_L3_DST_IP4},
13263 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13264 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13265 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13266 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13268 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13269 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13270 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13271 RTE_ETH_INPUT_SET_L3_DST_IP4},
13272 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13273 RTE_ETH_INPUT_SET_UNKNOWN},
13274 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13275 RTE_ETH_INPUT_SET_UNKNOWN},
13277 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13278 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13279 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13280 RTE_ETH_INPUT_SET_L3_DST_IP6},
13281 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13282 RTE_ETH_INPUT_SET_UNKNOWN},
13283 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13284 RTE_ETH_INPUT_SET_UNKNOWN},
13286 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13287 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13288 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13289 RTE_ETH_INPUT_SET_L3_DST_IP6},
13290 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13291 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13292 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13293 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13295 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13296 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13297 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13298 RTE_ETH_INPUT_SET_L3_DST_IP6},
13299 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13300 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13301 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13302 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13304 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13305 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13306 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13307 RTE_ETH_INPUT_SET_L3_DST_IP6},
13308 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13309 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13310 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13311 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13313 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13314 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13315 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13316 RTE_ETH_INPUT_SET_L3_DST_IP6},
13317 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13318 RTE_ETH_INPUT_SET_UNKNOWN},
13319 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13320 RTE_ETH_INPUT_SET_UNKNOWN},
13323 mask0 = types & pf->adapter->flow_types_mask;
13324 conf.op = RTE_ETH_INPUT_SET_SELECT;
13325 conf.inset_size = 0;
13326 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13327 if (mask0 & (1ULL << i)) {
13328 conf.flow_type = i;
13333 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13334 if ((types & inset_match_table[j].type) ==
13335 inset_match_table[j].type) {
13336 if (inset_match_table[j].field ==
13337 RTE_ETH_INPUT_SET_UNKNOWN)
13340 conf.field[conf.inset_size] =
13341 inset_match_table[j].field;
13346 if (conf.inset_size) {
13347 ret = i40e_hash_filter_inset_select(hw, &conf);
13355 /* Look up the conflicted rule then mark it as invalid */
13357 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13358 struct i40e_rte_flow_rss_conf *conf)
13360 struct i40e_rss_filter *rss_item;
13361 uint64_t rss_inset;
13363 /* Clear input set bits before comparing the pctype */
13364 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13365 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13367 /* Look up the conflicted rule then mark it as invalid */
13368 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13369 if (!rss_item->rss_filter_info.valid)
13372 if (conf->conf.queue_num &&
13373 rss_item->rss_filter_info.conf.queue_num)
13374 rss_item->rss_filter_info.valid = false;
13376 if (conf->conf.types &&
13377 (rss_item->rss_filter_info.conf.types &
13379 (conf->conf.types & rss_inset))
13380 rss_item->rss_filter_info.valid = false;
13382 if (conf->conf.func ==
13383 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13384 rss_item->rss_filter_info.conf.func ==
13385 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13386 rss_item->rss_filter_info.valid = false;
13390 /* Configure RSS hash function */
13392 i40e_rss_config_hash_function(struct i40e_pf *pf,
13393 struct i40e_rte_flow_rss_conf *conf)
13395 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13400 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13401 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13402 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13403 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13404 I40E_WRITE_FLUSH(hw);
13405 i40e_rss_mark_invalid_rule(pf, conf);
13409 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13411 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13412 I40E_WRITE_FLUSH(hw);
13413 i40e_rss_mark_invalid_rule(pf, conf);
13414 } else if (conf->conf.func ==
13415 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13416 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13418 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13419 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13420 if (mask0 & (1UL << i))
13424 if (i == UINT64_BIT)
13427 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13428 j < I40E_FILTER_PCTYPE_MAX; j++) {
13429 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13430 i40e_write_global_rx_ctl(hw,
13432 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13439 /* Enable RSS according to the configuration */
13441 i40e_rss_enable_hash(struct i40e_pf *pf,
13442 struct i40e_rte_flow_rss_conf *conf)
13444 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13445 struct i40e_rte_flow_rss_conf rss_conf;
13447 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13450 memset(&rss_conf, 0, sizeof(rss_conf));
13451 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13453 /* Configure hash input set */
13454 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13457 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13458 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13459 /* Random default keys */
13460 static uint32_t rss_key_default[] = {0x6b793944,
13461 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13462 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13463 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13465 rss_conf.conf.key = (uint8_t *)rss_key_default;
13466 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13469 "No valid RSS key config for i40e, using default\n");
13472 rss_conf.conf.types |= rss_info->conf.types;
13473 i40e_rss_hash_set(pf, &rss_conf);
13475 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13476 i40e_rss_config_hash_function(pf, conf);
13478 i40e_rss_mark_invalid_rule(pf, conf);
13483 /* Configure RSS queue region */
13485 i40e_rss_config_queue_region(struct i40e_pf *pf,
13486 struct i40e_rte_flow_rss_conf *conf)
13488 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13493 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13494 * It's necessary to calculate the actual PF queues that are configured.
13496 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13497 num = i40e_pf_calc_configured_queues_num(pf);
13499 num = pf->dev_data->nb_rx_queues;
13501 num = RTE_MIN(num, conf->conf.queue_num);
13502 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13507 "No PF queues are configured to enable RSS for port %u",
13508 pf->dev_data->port_id);
13512 /* Fill in redirection table */
13513 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13516 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13517 hw->func_caps.rss_table_entry_width) - 1));
13519 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13522 i40e_rss_mark_invalid_rule(pf, conf);
13527 /* Configure RSS hash function to default */
13529 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13530 struct i40e_rte_flow_rss_conf *conf)
13532 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13537 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13538 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13539 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13541 "Hash function already set to Toeplitz");
13542 I40E_WRITE_FLUSH(hw);
13546 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13548 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13549 I40E_WRITE_FLUSH(hw);
13550 } else if (conf->conf.func ==
13551 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13552 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13554 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13555 if (mask0 & (1UL << i))
13559 if (i == UINT64_BIT)
13562 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13563 j < I40E_FILTER_PCTYPE_MAX; j++) {
13564 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13565 i40e_write_global_rx_ctl(hw,
13574 /* Disable RSS hash and configure default input set */
13576 i40e_rss_disable_hash(struct i40e_pf *pf,
13577 struct i40e_rte_flow_rss_conf *conf)
13579 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13580 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13581 struct i40e_rte_flow_rss_conf rss_conf;
13584 memset(&rss_conf, 0, sizeof(rss_conf));
13585 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13587 /* Disable RSS hash */
13588 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13589 i40e_rss_hash_set(pf, &rss_conf);
13591 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13592 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13593 !(conf->conf.types & (1ULL << i)))
13596 /* Configure default input set */
13597 struct rte_eth_input_set_conf input_conf = {
13598 .op = RTE_ETH_INPUT_SET_SELECT,
13602 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13603 i40e_hash_filter_inset_select(hw, &input_conf);
13606 rss_info->conf.types = rss_conf.conf.types;
13608 i40e_rss_clear_hash_function(pf, conf);
13613 /* Configure RSS queue region to default */
13615 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13617 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13618 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13619 uint16_t queue[I40E_MAX_Q_PER_TC];
13620 uint32_t num_rxq, i;
13624 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13626 for (j = 0; j < num_rxq; j++)
13629 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13630 * It's necessary to calculate the actual PF queues that are configured.
13632 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13633 num = i40e_pf_calc_configured_queues_num(pf);
13635 num = pf->dev_data->nb_rx_queues;
13637 num = RTE_MIN(num, num_rxq);
13638 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13643 "No PF queues are configured to enable RSS for port %u",
13644 pf->dev_data->port_id);
13648 /* Fill in redirection table */
13649 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13652 lut = (lut << 8) | (queue[j] & ((0x1 <<
13653 hw->func_caps.rss_table_entry_width) - 1));
13655 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13658 rss_info->conf.queue_num = 0;
13659 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13665 i40e_config_rss_filter(struct i40e_pf *pf,
13666 struct i40e_rte_flow_rss_conf *conf, bool add)
13668 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13669 struct rte_flow_action_rss update_conf = rss_info->conf;
13673 if (conf->conf.queue_num) {
13674 /* Configure RSS queue region */
13675 ret = i40e_rss_config_queue_region(pf, conf);
13679 update_conf.queue_num = conf->conf.queue_num;
13680 update_conf.queue = conf->conf.queue;
13681 } else if (conf->conf.func ==
13682 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13683 /* Configure hash function */
13684 ret = i40e_rss_config_hash_function(pf, conf);
13688 update_conf.func = conf->conf.func;
13690 /* Configure hash enable and input set */
13691 ret = i40e_rss_enable_hash(pf, conf);
13695 update_conf.types |= conf->conf.types;
13696 update_conf.key = conf->conf.key;
13697 update_conf.key_len = conf->conf.key_len;
13700 /* Update RSS info in pf */
13701 if (i40e_rss_conf_init(rss_info, &update_conf))
13707 if (conf->conf.queue_num)
13708 i40e_rss_clear_queue_region(pf);
13709 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13710 i40e_rss_clear_hash_function(pf, conf);
13712 i40e_rss_disable_hash(pf, conf);
13718 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13719 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13720 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13721 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13723 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13724 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13726 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13727 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13730 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13731 ETH_I40E_FLOATING_VEB_ARG "=1"
13732 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13733 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13734 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13735 ETH_I40E_USE_LATEST_VEC "=0|1");