1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
50 #define I40E_CLEAR_PXE_WAIT_MS 200
51 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
52 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
54 /* Maximun number of capability elements */
55 #define I40E_MAX_CAP_ELE_NUM 128
57 /* Wait count and interval */
58 #define I40E_CHK_Q_ENA_COUNT 1000
59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
61 /* Maximun number of VSI */
62 #define I40E_MAX_NUM_VSIS (384UL)
64 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
66 /* Flow control default timer */
67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
69 /* Flow control enable fwd bit */
70 #define I40E_PRTMAC_FWD_CTRL 0x00000001
72 /* Receive Packet Buffer size */
73 #define I40E_RXPBSIZE (968 * 1024)
76 #define I40E_KILOSHIFT 10
78 /* Flow control default high water */
79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Flow control default low water */
82 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
84 /* Receive Average Packet Size in Byte*/
85 #define I40E_PACKET_AVERAGE_SIZE 128
87 /* Mask of PF interrupt causes */
88 #define I40E_PFINT_ICR0_ENA_MASK ( \
89 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
90 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_GRST_MASK | \
92 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
93 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
94 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
95 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
96 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
97 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
99 #define I40E_FLOW_TYPES ( \
100 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
105 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
110 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
112 /* Additional timesync values. */
113 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
114 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
115 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
116 #define I40E_PRTTSYN_TSYNENA 0x80000000
117 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
118 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
121 * Below are values for writing un-exposed registers suggested
124 /* Destination MAC address */
125 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
126 /* Source MAC address */
127 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
129 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
131 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
132 /* Single VLAN tag in the inner L2 header */
133 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
134 /* Source IPv4 address */
135 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
136 /* Destination IPv4 address */
137 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
138 /* Source IPv4 address for X722 */
139 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
140 /* Destination IPv4 address for X722 */
141 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
142 /* IPv4 Protocol for X722 */
143 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
144 /* IPv4 Time to Live for X722 */
145 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
146 /* IPv4 Type of Service (TOS) */
147 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
149 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
150 /* IPv4 Time to Live */
151 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
152 /* Source IPv6 address */
153 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
154 /* Destination IPv6 address */
155 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
156 /* IPv6 Traffic Class (TC) */
157 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
158 /* IPv6 Next Header */
159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
163 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
164 /* Destination L4 port */
165 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
166 /* SCTP verification tag */
167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
170 /* Source port of tunneling UDP */
171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
172 /* Destination port of tunneling UDP */
173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
174 /* UDP Tunneling ID, NVGRE/GRE key */
175 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
176 /* Last ether type */
177 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
178 /* Tunneling outer destination IPv4 address */
179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
180 /* Tunneling outer destination IPv6 address */
181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
182 /* 1st word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
184 /* 2nd word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
186 /* 3rd word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
188 /* 4th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
190 /* 5th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
192 /* 6th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
194 /* 7th word of flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
196 /* 8th word of flex payload */
197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
198 /* all 8 words flex payload */
199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
200 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
202 #define I40E_TRANSLATE_INSET 0
203 #define I40E_TRANSLATE_REG 1
205 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
206 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
207 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
208 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
210 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
212 /* PCI offset for querying capability */
213 #define PCI_DEV_CAP_REG 0xA4
214 /* PCI offset for enabling/disabling Extended Tag */
215 #define PCI_DEV_CTRL_REG 0xA8
216 /* Bit mask of Extended Tag capability */
217 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
218 /* Bit shift of Extended Tag enable/disable */
219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
220 /* Bit mask of Extended Tag enable/disable */
221 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
225 static int i40e_dev_configure(struct rte_eth_dev *dev);
226 static int i40e_dev_start(struct rte_eth_dev *dev);
227 static void i40e_dev_stop(struct rte_eth_dev *dev);
228 static void i40e_dev_close(struct rte_eth_dev *dev);
229 static int i40e_dev_reset(struct rte_eth_dev *dev);
230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
237 struct rte_eth_stats *stats);
238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
239 struct rte_eth_xstat *xstats, unsigned n);
240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
241 struct rte_eth_xstat_name *xstats_names,
243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
245 char *fw_version, size_t fw_size);
246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
247 struct rte_eth_dev_info *dev_info);
248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
252 enum rte_vlan_type vlan_type,
254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_fc_conf *fc_conf);
265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
266 struct rte_eth_pfc_conf *pfc_conf);
267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
268 struct rte_ether_addr *mac_addr,
271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
276 struct rte_eth_rss_reta_entry64 *reta_conf,
279 static int i40e_get_cap(struct i40e_hw *hw);
280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
281 static int i40e_pf_setup(struct i40e_pf *pf);
282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
286 bool offset_loaded, uint64_t *offset, uint64_t *stat);
287 static void i40e_stat_update_48(struct i40e_hw *hw,
293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
294 static void i40e_dev_interrupt_handler(void *param);
295 static void i40e_dev_alarm_handler(void *param);
296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
297 uint32_t base, uint32_t num);
298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
304 static int i40e_veb_release(struct i40e_veb *veb);
305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
306 struct i40e_vsi *vsi);
307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
309 struct i40e_macvlan_filter *mv_f,
312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
322 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
326 enum rte_filter_type filter_type,
327 enum rte_filter_op filter_op,
329 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
331 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
332 static void i40e_configure_registers(struct i40e_hw *hw);
333 static void i40e_hw_init(struct rte_eth_dev *dev);
334 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
335 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
341 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
342 struct rte_eth_mirror_conf *mirror_conf,
343 uint8_t sw_id, uint8_t on);
344 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
346 static int i40e_timesync_enable(struct rte_eth_dev *dev);
347 static int i40e_timesync_disable(struct rte_eth_dev *dev);
348 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp,
351 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
352 struct timespec *timestamp);
353 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
355 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
357 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
360 const struct timespec *timestamp);
362 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
364 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
367 static int i40e_get_regs(struct rte_eth_dev *dev,
368 struct rte_dev_reg_info *regs);
370 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
372 static int i40e_get_eeprom(struct rte_eth_dev *dev,
373 struct rte_dev_eeprom_info *eeprom);
375 static int i40e_get_module_info(struct rte_eth_dev *dev,
376 struct rte_eth_dev_module_info *modinfo);
377 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
378 struct rte_dev_eeprom_info *info);
380 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
381 struct rte_ether_addr *mac_addr);
383 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
385 static int i40e_ethertype_filter_convert(
386 const struct rte_eth_ethertype_filter *input,
387 struct i40e_ethertype_filter *filter);
388 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
389 struct i40e_ethertype_filter *filter);
391 static int i40e_tunnel_filter_convert(
392 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
398 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
399 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
400 static void i40e_filter_restore(struct i40e_pf *pf);
401 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
402 static int i40e_pf_config_rss(struct i40e_pf *pf);
404 static const char *const valid_keys[] = {
405 ETH_I40E_FLOATING_VEB_ARG,
406 ETH_I40E_FLOATING_VEB_LIST_ARG,
407 ETH_I40E_SUPPORT_MULTI_DRIVER,
408 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
409 ETH_I40E_USE_LATEST_VEC,
413 static const struct rte_pci_id pci_id_i40e_map[] = {
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
440 { .vendor_id = 0, /* sentinel */ },
443 static const struct eth_dev_ops i40e_eth_dev_ops = {
444 .dev_configure = i40e_dev_configure,
445 .dev_start = i40e_dev_start,
446 .dev_stop = i40e_dev_stop,
447 .dev_close = i40e_dev_close,
448 .dev_reset = i40e_dev_reset,
449 .promiscuous_enable = i40e_dev_promiscuous_enable,
450 .promiscuous_disable = i40e_dev_promiscuous_disable,
451 .allmulticast_enable = i40e_dev_allmulticast_enable,
452 .allmulticast_disable = i40e_dev_allmulticast_disable,
453 .dev_set_link_up = i40e_dev_set_link_up,
454 .dev_set_link_down = i40e_dev_set_link_down,
455 .link_update = i40e_dev_link_update,
456 .stats_get = i40e_dev_stats_get,
457 .xstats_get = i40e_dev_xstats_get,
458 .xstats_get_names = i40e_dev_xstats_get_names,
459 .stats_reset = i40e_dev_stats_reset,
460 .xstats_reset = i40e_dev_stats_reset,
461 .fw_version_get = i40e_fw_version_get,
462 .dev_infos_get = i40e_dev_info_get,
463 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
464 .vlan_filter_set = i40e_vlan_filter_set,
465 .vlan_tpid_set = i40e_vlan_tpid_set,
466 .vlan_offload_set = i40e_vlan_offload_set,
467 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
468 .vlan_pvid_set = i40e_vlan_pvid_set,
469 .rx_queue_start = i40e_dev_rx_queue_start,
470 .rx_queue_stop = i40e_dev_rx_queue_stop,
471 .tx_queue_start = i40e_dev_tx_queue_start,
472 .tx_queue_stop = i40e_dev_tx_queue_stop,
473 .rx_queue_setup = i40e_dev_rx_queue_setup,
474 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
475 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
476 .rx_queue_release = i40e_dev_rx_queue_release,
477 .rx_queue_count = i40e_dev_rx_queue_count,
478 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
479 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
480 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
481 .tx_queue_setup = i40e_dev_tx_queue_setup,
482 .tx_queue_release = i40e_dev_tx_queue_release,
483 .dev_led_on = i40e_dev_led_on,
484 .dev_led_off = i40e_dev_led_off,
485 .flow_ctrl_get = i40e_flow_ctrl_get,
486 .flow_ctrl_set = i40e_flow_ctrl_set,
487 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
488 .mac_addr_add = i40e_macaddr_add,
489 .mac_addr_remove = i40e_macaddr_remove,
490 .reta_update = i40e_dev_rss_reta_update,
491 .reta_query = i40e_dev_rss_reta_query,
492 .rss_hash_update = i40e_dev_rss_hash_update,
493 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
494 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
495 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
496 .filter_ctrl = i40e_dev_filter_ctrl,
497 .rxq_info_get = i40e_rxq_info_get,
498 .txq_info_get = i40e_txq_info_get,
499 .rx_burst_mode_get = i40e_rx_burst_mode_get,
500 .tx_burst_mode_get = i40e_tx_burst_mode_get,
501 .mirror_rule_set = i40e_mirror_rule_set,
502 .mirror_rule_reset = i40e_mirror_rule_reset,
503 .timesync_enable = i40e_timesync_enable,
504 .timesync_disable = i40e_timesync_disable,
505 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
506 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
507 .get_dcb_info = i40e_dev_get_dcb_info,
508 .timesync_adjust_time = i40e_timesync_adjust_time,
509 .timesync_read_time = i40e_timesync_read_time,
510 .timesync_write_time = i40e_timesync_write_time,
511 .get_reg = i40e_get_regs,
512 .get_eeprom_length = i40e_get_eeprom_length,
513 .get_eeprom = i40e_get_eeprom,
514 .get_module_info = i40e_get_module_info,
515 .get_module_eeprom = i40e_get_module_eeprom,
516 .mac_addr_set = i40e_set_default_mac_addr,
517 .mtu_set = i40e_dev_mtu_set,
518 .tm_ops_get = i40e_tm_ops_get,
519 .tx_done_cleanup = i40e_tx_done_cleanup,
522 /* store statistics names and its offset in stats structure */
523 struct rte_i40e_xstats_name_off {
524 char name[RTE_ETH_XSTATS_NAME_SIZE];
528 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
529 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
530 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
531 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
532 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
533 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
534 rx_unknown_protocol)},
535 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
536 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
537 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
538 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
541 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
542 sizeof(rte_i40e_stats_strings[0]))
544 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
545 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
546 tx_dropped_link_down)},
547 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
548 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
551 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
553 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
555 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
557 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
558 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
559 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
560 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
561 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
562 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
578 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
579 mac_short_packet_dropped)},
580 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
582 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
583 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
584 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
596 {"rx_flow_director_atr_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
598 {"rx_flow_director_sb_match_packets",
599 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
600 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
604 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
606 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
610 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
611 sizeof(rte_i40e_hw_port_strings[0]))
613 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
614 {"xon_packets", offsetof(struct i40e_hw_port_stats,
616 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
621 sizeof(rte_i40e_rxq_prio_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
628 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
629 priority_xon_2_xoff)},
632 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
633 sizeof(rte_i40e_txq_prio_strings[0]))
636 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
637 struct rte_pci_device *pci_dev)
639 char name[RTE_ETH_NAME_MAX_LEN];
640 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
643 if (pci_dev->device.devargs) {
644 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
650 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
651 sizeof(struct i40e_adapter),
652 eth_dev_pci_specific_init, pci_dev,
653 eth_i40e_dev_init, NULL);
655 if (retval || eth_da.nb_representor_ports < 1)
658 /* probe VF representor ports */
659 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
660 pci_dev->device.name);
662 if (pf_ethdev == NULL)
665 for (i = 0; i < eth_da.nb_representor_ports; i++) {
666 struct i40e_vf_representor representor = {
667 .vf_id = eth_da.representor_ports[i],
668 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
669 pf_ethdev->data->dev_private)->switch_domain_id,
670 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
671 pf_ethdev->data->dev_private)
674 /* representor port net_bdf_port */
675 snprintf(name, sizeof(name), "net_%s_representor_%d",
676 pci_dev->device.name, eth_da.representor_ports[i]);
678 retval = rte_eth_dev_create(&pci_dev->device, name,
679 sizeof(struct i40e_vf_representor), NULL, NULL,
680 i40e_vf_representor_init, &representor);
683 PMD_DRV_LOG(ERR, "failed to create i40e vf "
684 "representor %s.", name);
690 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
692 struct rte_eth_dev *ethdev;
694 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
698 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
699 return rte_eth_dev_pci_generic_remove(pci_dev,
700 i40e_vf_representor_uninit);
702 return rte_eth_dev_pci_generic_remove(pci_dev,
703 eth_i40e_dev_uninit);
706 static struct rte_pci_driver rte_i40e_pmd = {
707 .id_table = pci_id_i40e_map,
708 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
709 .probe = eth_i40e_pci_probe,
710 .remove = eth_i40e_pci_remove,
714 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
717 uint32_t ori_reg_val;
718 struct rte_eth_dev *dev;
720 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
721 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
722 i40e_write_rx_ctl(hw, reg_addr, reg_val);
723 if (ori_reg_val != reg_val)
725 "i40e device %s changed global register [0x%08x]."
726 " original: 0x%08x, new: 0x%08x",
727 dev->device->name, reg_addr, ori_reg_val, reg_val);
730 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
731 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
732 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
734 #ifndef I40E_GLQF_ORT
735 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
737 #ifndef I40E_GLQF_PIT
738 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
740 #ifndef I40E_GLQF_L3_MAP
741 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
744 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
747 * Initialize registers for parsing packet type of QinQ
748 * This should be removed from code once proper
749 * configuration API is added to avoid configuration conflicts
750 * between ports of the same device.
752 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
753 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
756 static inline void i40e_config_automask(struct i40e_pf *pf)
758 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
761 /* INTENA flag is not auto-cleared for interrupt */
762 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
764 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
766 /* If support multi-driver, PF will use INT0. */
767 if (!pf->support_multi_driver)
768 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
770 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
773 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
776 * Add a ethertype filter to drop all flow control frames transmitted
780 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
782 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
783 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
784 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
785 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
788 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
789 I40E_FLOW_CONTROL_ETHERTYPE, flags,
790 pf->main_vsi_seid, 0,
794 "Failed to add filter to drop flow control frames from VSIs.");
798 floating_veb_list_handler(__rte_unused const char *key,
799 const char *floating_veb_value,
803 unsigned int count = 0;
806 bool *vf_floating_veb = opaque;
808 while (isblank(*floating_veb_value))
809 floating_veb_value++;
811 /* Reset floating VEB configuration for VFs */
812 for (idx = 0; idx < I40E_MAX_VF; idx++)
813 vf_floating_veb[idx] = false;
817 while (isblank(*floating_veb_value))
818 floating_veb_value++;
819 if (*floating_veb_value == '\0')
822 idx = strtoul(floating_veb_value, &end, 10);
823 if (errno || end == NULL)
825 while (isblank(*end))
829 } else if ((*end == ';') || (*end == '\0')) {
831 if (min == I40E_MAX_VF)
833 if (max >= I40E_MAX_VF)
834 max = I40E_MAX_VF - 1;
835 for (idx = min; idx <= max; idx++) {
836 vf_floating_veb[idx] = true;
843 floating_veb_value = end + 1;
844 } while (*end != '\0');
853 config_vf_floating_veb(struct rte_devargs *devargs,
854 uint16_t floating_veb,
855 bool *vf_floating_veb)
857 struct rte_kvargs *kvlist;
859 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
863 /* All the VFs attach to the floating VEB by default
864 * when the floating VEB is enabled.
866 for (i = 0; i < I40E_MAX_VF; i++)
867 vf_floating_veb[i] = true;
872 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
876 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
877 rte_kvargs_free(kvlist);
880 /* When the floating_veb_list parameter exists, all the VFs
881 * will attach to the legacy VEB firstly, then configure VFs
882 * to the floating VEB according to the floating_veb_list.
884 if (rte_kvargs_process(kvlist, floating_veb_list,
885 floating_veb_list_handler,
886 vf_floating_veb) < 0) {
887 rte_kvargs_free(kvlist);
890 rte_kvargs_free(kvlist);
894 i40e_check_floating_handler(__rte_unused const char *key,
896 __rte_unused void *opaque)
898 if (strcmp(value, "1"))
905 is_floating_veb_supported(struct rte_devargs *devargs)
907 struct rte_kvargs *kvlist;
908 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
913 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
917 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
918 rte_kvargs_free(kvlist);
921 /* Floating VEB is enabled when there's key-value:
922 * enable_floating_veb=1
924 if (rte_kvargs_process(kvlist, floating_veb_key,
925 i40e_check_floating_handler, NULL) < 0) {
926 rte_kvargs_free(kvlist);
929 rte_kvargs_free(kvlist);
935 config_floating_veb(struct rte_eth_dev *dev)
937 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
941 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
943 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
945 is_floating_veb_supported(pci_dev->device.devargs);
946 config_vf_floating_veb(pci_dev->device.devargs,
948 pf->floating_veb_list);
950 pf->floating_veb = false;
954 #define I40E_L2_TAGS_S_TAG_SHIFT 1
955 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
958 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
960 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
961 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
962 char ethertype_hash_name[RTE_HASH_NAMESIZE];
965 struct rte_hash_parameters ethertype_hash_params = {
966 .name = ethertype_hash_name,
967 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
968 .key_len = sizeof(struct i40e_ethertype_filter_input),
969 .hash_func = rte_hash_crc,
970 .hash_func_init_val = 0,
971 .socket_id = rte_socket_id(),
974 /* Initialize ethertype filter rule list and hash */
975 TAILQ_INIT(ðertype_rule->ethertype_list);
976 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
977 "ethertype_%s", dev->device->name);
978 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
979 if (!ethertype_rule->hash_table) {
980 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
983 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
984 sizeof(struct i40e_ethertype_filter *) *
985 I40E_MAX_ETHERTYPE_FILTER_NUM,
987 if (!ethertype_rule->hash_map) {
989 "Failed to allocate memory for ethertype hash map!");
991 goto err_ethertype_hash_map_alloc;
996 err_ethertype_hash_map_alloc:
997 rte_hash_free(ethertype_rule->hash_table);
1003 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1005 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1006 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1007 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1010 struct rte_hash_parameters tunnel_hash_params = {
1011 .name = tunnel_hash_name,
1012 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1013 .key_len = sizeof(struct i40e_tunnel_filter_input),
1014 .hash_func = rte_hash_crc,
1015 .hash_func_init_val = 0,
1016 .socket_id = rte_socket_id(),
1019 /* Initialize tunnel filter rule list and hash */
1020 TAILQ_INIT(&tunnel_rule->tunnel_list);
1021 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1022 "tunnel_%s", dev->device->name);
1023 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1024 if (!tunnel_rule->hash_table) {
1025 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1028 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1029 sizeof(struct i40e_tunnel_filter *) *
1030 I40E_MAX_TUNNEL_FILTER_NUM,
1032 if (!tunnel_rule->hash_map) {
1034 "Failed to allocate memory for tunnel hash map!");
1036 goto err_tunnel_hash_map_alloc;
1041 err_tunnel_hash_map_alloc:
1042 rte_hash_free(tunnel_rule->hash_table);
1048 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1051 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1052 struct i40e_fdir_info *fdir_info = &pf->fdir;
1053 char fdir_hash_name[RTE_HASH_NAMESIZE];
1054 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1055 uint32_t best = hw->func_caps.fd_filters_best_effort;
1056 struct rte_bitmap *bmp = NULL;
1062 struct rte_hash_parameters fdir_hash_params = {
1063 .name = fdir_hash_name,
1064 .entries = I40E_MAX_FDIR_FILTER_NUM,
1065 .key_len = sizeof(struct i40e_fdir_input),
1066 .hash_func = rte_hash_crc,
1067 .hash_func_init_val = 0,
1068 .socket_id = rte_socket_id(),
1071 /* Initialize flow director filter rule list and hash */
1072 TAILQ_INIT(&fdir_info->fdir_list);
1073 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1074 "fdir_%s", dev->device->name);
1075 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1076 if (!fdir_info->hash_table) {
1077 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1081 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1082 sizeof(struct i40e_fdir_filter *) *
1083 I40E_MAX_FDIR_FILTER_NUM,
1085 if (!fdir_info->hash_map) {
1087 "Failed to allocate memory for fdir hash map!");
1089 goto err_fdir_hash_map_alloc;
1092 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1093 sizeof(struct i40e_fdir_filter) *
1094 I40E_MAX_FDIR_FILTER_NUM,
1097 if (!fdir_info->fdir_filter_array) {
1099 "Failed to allocate memory for fdir filter array!");
1101 goto err_fdir_filter_array_alloc;
1104 fdir_info->fdir_space_size = alloc + best;
1105 fdir_info->fdir_actual_cnt = 0;
1106 fdir_info->fdir_guarantee_total_space = alloc;
1107 fdir_info->fdir_guarantee_free_space =
1108 fdir_info->fdir_guarantee_total_space;
1110 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1112 fdir_info->fdir_flow_pool.pool =
1113 rte_zmalloc("i40e_fdir_entry",
1114 sizeof(struct i40e_fdir_entry) *
1115 fdir_info->fdir_space_size,
1118 if (!fdir_info->fdir_flow_pool.pool) {
1120 "Failed to allocate memory for bitmap flow!");
1122 goto err_fdir_bitmap_flow_alloc;
1125 for (i = 0; i < fdir_info->fdir_space_size; i++)
1126 fdir_info->fdir_flow_pool.pool[i].idx = i;
1129 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1130 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1133 "Failed to allocate memory for fdir bitmap!");
1135 goto err_fdir_mem_alloc;
1137 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1140 "Failed to initialization fdir bitmap!");
1142 goto err_fdir_bmp_alloc;
1144 for (i = 0; i < fdir_info->fdir_space_size; i++)
1145 rte_bitmap_set(bmp, i);
1147 fdir_info->fdir_flow_pool.bitmap = bmp;
1154 rte_free(fdir_info->fdir_flow_pool.pool);
1155 err_fdir_bitmap_flow_alloc:
1156 rte_free(fdir_info->fdir_filter_array);
1157 err_fdir_filter_array_alloc:
1158 rte_free(fdir_info->hash_map);
1159 err_fdir_hash_map_alloc:
1160 rte_hash_free(fdir_info->hash_table);
1166 i40e_init_customized_info(struct i40e_pf *pf)
1170 /* Initialize customized pctype */
1171 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1172 pf->customized_pctype[i].index = i;
1173 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1174 pf->customized_pctype[i].valid = false;
1177 pf->gtp_support = false;
1178 pf->esp_support = false;
1182 i40e_init_filter_invalidation(struct i40e_pf *pf)
1184 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1185 struct i40e_fdir_info *fdir_info = &pf->fdir;
1186 uint32_t glqf_ctl_reg = 0;
1188 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1189 if (!pf->support_multi_driver) {
1190 fdir_info->fdir_invalprio = 1;
1191 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1192 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1193 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1195 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1196 fdir_info->fdir_invalprio = 1;
1197 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1199 fdir_info->fdir_invalprio = 0;
1200 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1206 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1208 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1210 struct i40e_queue_regions *info = &pf->queue_region;
1213 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1214 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1216 memset(info, 0, sizeof(struct i40e_queue_regions));
1220 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1225 unsigned long support_multi_driver;
1228 pf = (struct i40e_pf *)opaque;
1231 support_multi_driver = strtoul(value, &end, 10);
1232 if (errno != 0 || end == value || *end != 0) {
1233 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1237 if (support_multi_driver == 1 || support_multi_driver == 0)
1238 pf->support_multi_driver = (bool)support_multi_driver;
1240 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1241 "enable global configuration by default."
1242 ETH_I40E_SUPPORT_MULTI_DRIVER);
1247 i40e_support_multi_driver(struct rte_eth_dev *dev)
1249 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1250 struct rte_kvargs *kvlist;
1253 /* Enable global configuration by default */
1254 pf->support_multi_driver = false;
1256 if (!dev->device->devargs)
1259 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1263 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1264 if (!kvargs_count) {
1265 rte_kvargs_free(kvlist);
1269 if (kvargs_count > 1)
1270 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1271 "the first invalid or last valid one is used !",
1272 ETH_I40E_SUPPORT_MULTI_DRIVER);
1274 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1275 i40e_parse_multi_drv_handler, pf) < 0) {
1276 rte_kvargs_free(kvlist);
1280 rte_kvargs_free(kvlist);
1285 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1286 uint32_t reg_addr, uint64_t reg_val,
1287 struct i40e_asq_cmd_details *cmd_details)
1289 uint64_t ori_reg_val;
1290 struct rte_eth_dev *dev;
1293 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1294 if (ret != I40E_SUCCESS) {
1296 "Fail to debug read from 0x%08x",
1300 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1302 if (ori_reg_val != reg_val)
1303 PMD_DRV_LOG(WARNING,
1304 "i40e device %s changed global register [0x%08x]."
1305 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1306 dev->device->name, reg_addr, ori_reg_val, reg_val);
1308 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1312 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1316 struct i40e_adapter *ad = opaque;
1319 use_latest_vec = atoi(value);
1321 if (use_latest_vec != 0 && use_latest_vec != 1)
1322 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1324 ad->use_latest_vec = (uint8_t)use_latest_vec;
1330 i40e_use_latest_vec(struct rte_eth_dev *dev)
1332 struct i40e_adapter *ad =
1333 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1334 struct rte_kvargs *kvlist;
1337 ad->use_latest_vec = false;
1339 if (!dev->device->devargs)
1342 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1346 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1347 if (!kvargs_count) {
1348 rte_kvargs_free(kvlist);
1352 if (kvargs_count > 1)
1353 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1354 "the first invalid or last valid one is used !",
1355 ETH_I40E_USE_LATEST_VEC);
1357 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1358 i40e_parse_latest_vec_handler, ad) < 0) {
1359 rte_kvargs_free(kvlist);
1363 rte_kvargs_free(kvlist);
1368 read_vf_msg_config(__rte_unused const char *key,
1372 struct i40e_vf_msg_cfg *cfg = opaque;
1374 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1375 &cfg->ignore_second) != 3) {
1376 memset(cfg, 0, sizeof(*cfg));
1377 PMD_DRV_LOG(ERR, "format error! example: "
1378 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1383 * If the message validation function been enabled, the 'period'
1384 * and 'ignore_second' must greater than 0.
1386 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1387 memset(cfg, 0, sizeof(*cfg));
1388 PMD_DRV_LOG(ERR, "%s error! the second and third"
1389 " number must be greater than 0!",
1390 ETH_I40E_VF_MSG_CFG);
1398 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1399 struct i40e_vf_msg_cfg *msg_cfg)
1401 struct rte_kvargs *kvlist;
1405 memset(msg_cfg, 0, sizeof(*msg_cfg));
1407 if (!dev->device->devargs)
1410 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1414 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1418 if (kvargs_count > 1) {
1419 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1420 ETH_I40E_VF_MSG_CFG);
1425 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1426 read_vf_msg_config, msg_cfg) < 0)
1430 rte_kvargs_free(kvlist);
1434 #define I40E_ALARM_INTERVAL 50000 /* us */
1437 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1439 struct rte_pci_device *pci_dev;
1440 struct rte_intr_handle *intr_handle;
1441 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1442 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443 struct i40e_vsi *vsi;
1446 uint8_t aq_fail = 0;
1448 PMD_INIT_FUNC_TRACE();
1450 dev->dev_ops = &i40e_eth_dev_ops;
1451 dev->rx_pkt_burst = i40e_recv_pkts;
1452 dev->tx_pkt_burst = i40e_xmit_pkts;
1453 dev->tx_pkt_prepare = i40e_prep_pkts;
1455 /* for secondary processes, we don't initialise any further as primary
1456 * has already done this work. Only check we don't need a different
1458 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459 i40e_set_rx_function(dev);
1460 i40e_set_tx_function(dev);
1463 i40e_set_default_ptype_table(dev);
1464 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465 intr_handle = &pci_dev->intr_handle;
1467 rte_eth_copy_pci_info(dev, pci_dev);
1469 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1470 pf->adapter->eth_dev = dev;
1471 pf->dev_data = dev->data;
1473 hw->back = I40E_PF_TO_ADAPTER(pf);
1474 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1477 "Hardware is not available, as address is NULL");
1481 hw->vendor_id = pci_dev->id.vendor_id;
1482 hw->device_id = pci_dev->id.device_id;
1483 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1484 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1485 hw->bus.device = pci_dev->addr.devid;
1486 hw->bus.func = pci_dev->addr.function;
1487 hw->adapter_stopped = 0;
1488 hw->adapter_closed = 0;
1490 /* Init switch device pointer */
1491 hw->switch_dev = NULL;
1494 * Switch Tag value should not be identical to either the First Tag
1495 * or Second Tag values. So set something other than common Ethertype
1496 * for internal switching.
1498 hw->switch_tag = 0xffff;
1500 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1501 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1502 PMD_INIT_LOG(ERR, "\nERROR: "
1503 "Firmware recovery mode detected. Limiting functionality.\n"
1504 "Refer to the Intel(R) Ethernet Adapters and Devices "
1505 "User Guide for details on firmware recovery mode.");
1509 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1510 /* Check if need to support multi-driver */
1511 i40e_support_multi_driver(dev);
1512 /* Check if users want the latest supported vec path */
1513 i40e_use_latest_vec(dev);
1515 /* Make sure all is clean before doing PF reset */
1518 /* Reset here to make sure all is clean for each PF */
1519 ret = i40e_pf_reset(hw);
1521 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1525 /* Initialize the shared code (base driver) */
1526 ret = i40e_init_shared_code(hw);
1528 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1532 /* Initialize the parameters for adminq */
1533 i40e_init_adminq_parameter(hw);
1534 ret = i40e_init_adminq(hw);
1535 if (ret != I40E_SUCCESS) {
1536 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1539 /* Firmware of SFP x722 does not support adminq option */
1540 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1541 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1543 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1544 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1545 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1546 ((hw->nvm.version >> 12) & 0xf),
1547 ((hw->nvm.version >> 4) & 0xff),
1548 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1550 /* Initialize the hardware */
1553 i40e_config_automask(pf);
1555 i40e_set_default_pctype_table(dev);
1558 * To work around the NVM issue, initialize registers
1559 * for packet type of QinQ by software.
1560 * It should be removed once issues are fixed in NVM.
1562 if (!pf->support_multi_driver)
1563 i40e_GLQF_reg_init(hw);
1565 /* Initialize the input set for filters (hash and fd) to default value */
1566 i40e_filter_input_set_init(pf);
1568 /* initialise the L3_MAP register */
1569 if (!pf->support_multi_driver) {
1570 ret = i40e_aq_debug_write_global_register(hw,
1571 I40E_GLQF_L3_MAP(40),
1574 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1577 "Global register 0x%08x is changed with 0x28",
1578 I40E_GLQF_L3_MAP(40));
1581 /* Need the special FW version to support floating VEB */
1582 config_floating_veb(dev);
1583 /* Clear PXE mode */
1584 i40e_clear_pxe_mode(hw);
1585 i40e_dev_sync_phy_type(hw);
1588 * On X710, performance number is far from the expectation on recent
1589 * firmware versions. The fix for this issue may not be integrated in
1590 * the following firmware version. So the workaround in software driver
1591 * is needed. It needs to modify the initial values of 3 internal only
1592 * registers. Note that the workaround can be removed when it is fixed
1593 * in firmware in the future.
1595 i40e_configure_registers(hw);
1597 /* Get hw capabilities */
1598 ret = i40e_get_cap(hw);
1599 if (ret != I40E_SUCCESS) {
1600 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1601 goto err_get_capabilities;
1604 /* Initialize parameters for PF */
1605 ret = i40e_pf_parameter_init(dev);
1607 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1608 goto err_parameter_init;
1611 /* Initialize the queue management */
1612 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1614 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1615 goto err_qp_pool_init;
1617 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1618 hw->func_caps.num_msix_vectors - 1);
1620 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1621 goto err_msix_pool_init;
1624 /* Initialize lan hmc */
1625 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1626 hw->func_caps.num_rx_qp, 0, 0);
1627 if (ret != I40E_SUCCESS) {
1628 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1629 goto err_init_lan_hmc;
1632 /* Configure lan hmc */
1633 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1634 if (ret != I40E_SUCCESS) {
1635 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1636 goto err_configure_lan_hmc;
1639 /* Get and check the mac address */
1640 i40e_get_mac_addr(hw, hw->mac.addr);
1641 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1642 PMD_INIT_LOG(ERR, "mac address is not valid");
1644 goto err_get_mac_addr;
1646 /* Copy the permanent MAC address */
1647 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1648 (struct rte_ether_addr *)hw->mac.perm_addr);
1650 /* Disable flow control */
1651 hw->fc.requested_mode = I40E_FC_NONE;
1652 i40e_set_fc(hw, &aq_fail, TRUE);
1654 /* Set the global registers with default ether type value */
1655 if (!pf->support_multi_driver) {
1656 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1657 RTE_ETHER_TYPE_VLAN);
1658 if (ret != I40E_SUCCESS) {
1660 "Failed to set the default outer "
1662 goto err_setup_pf_switch;
1666 /* PF setup, which includes VSI setup */
1667 ret = i40e_pf_setup(pf);
1669 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1670 goto err_setup_pf_switch;
1675 /* Disable double vlan by default */
1676 i40e_vsi_config_double_vlan(vsi, FALSE);
1678 /* Disable S-TAG identification when floating_veb is disabled */
1679 if (!pf->floating_veb) {
1680 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1681 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1682 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1683 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1687 if (!vsi->max_macaddrs)
1688 len = RTE_ETHER_ADDR_LEN;
1690 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1692 /* Should be after VSI initialized */
1693 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1694 if (!dev->data->mac_addrs) {
1696 "Failed to allocated memory for storing mac address");
1699 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1700 &dev->data->mac_addrs[0]);
1702 /* Pass the information to the rte_eth_dev_close() that it should also
1703 * release the private port resources.
1705 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1707 /* Init dcb to sw mode by default */
1708 ret = i40e_dcb_init_configure(dev, TRUE);
1709 if (ret != I40E_SUCCESS) {
1710 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1711 pf->flags &= ~I40E_FLAG_DCB;
1713 /* Update HW struct after DCB configuration */
1716 /* initialize pf host driver to setup SRIOV resource if applicable */
1717 i40e_pf_host_init(dev);
1719 /* register callback func to eal lib */
1720 rte_intr_callback_register(intr_handle,
1721 i40e_dev_interrupt_handler, dev);
1723 /* configure and enable device interrupt */
1724 i40e_pf_config_irq0(hw, TRUE);
1725 i40e_pf_enable_irq0(hw);
1727 /* enable uio intr after callback register */
1728 rte_intr_enable(intr_handle);
1730 /* By default disable flexible payload in global configuration */
1731 if (!pf->support_multi_driver)
1732 i40e_flex_payload_reg_set_default(hw);
1735 * Add an ethertype filter to drop all flow control frames transmitted
1736 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1739 i40e_add_tx_flow_control_drop_filter(pf);
1741 /* Set the max frame size to 0x2600 by default,
1742 * in case other drivers changed the default value.
1744 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1746 /* initialize mirror rule list */
1747 TAILQ_INIT(&pf->mirror_list);
1749 /* initialize RSS rule list */
1750 TAILQ_INIT(&pf->rss_config_list);
1752 /* initialize Traffic Manager configuration */
1753 i40e_tm_conf_init(dev);
1755 /* Initialize customized information */
1756 i40e_init_customized_info(pf);
1758 /* Initialize the filter invalidation configuration */
1759 i40e_init_filter_invalidation(pf);
1761 ret = i40e_init_ethtype_filter_list(dev);
1763 goto err_init_ethtype_filter_list;
1764 ret = i40e_init_tunnel_filter_list(dev);
1766 goto err_init_tunnel_filter_list;
1767 ret = i40e_init_fdir_filter_list(dev);
1769 goto err_init_fdir_filter_list;
1771 /* initialize queue region configuration */
1772 i40e_init_queue_region_conf(dev);
1774 /* initialize RSS configuration from rte_flow */
1775 memset(&pf->rss_info, 0,
1776 sizeof(struct i40e_rte_flow_rss_conf));
1778 /* reset all stats of the device, including pf and main vsi */
1779 i40e_dev_stats_reset(dev);
1783 err_init_fdir_filter_list:
1784 rte_free(pf->tunnel.hash_table);
1785 rte_free(pf->tunnel.hash_map);
1786 err_init_tunnel_filter_list:
1787 rte_free(pf->ethertype.hash_table);
1788 rte_free(pf->ethertype.hash_map);
1789 err_init_ethtype_filter_list:
1790 rte_free(dev->data->mac_addrs);
1791 dev->data->mac_addrs = NULL;
1793 i40e_vsi_release(pf->main_vsi);
1794 err_setup_pf_switch:
1796 err_configure_lan_hmc:
1797 (void)i40e_shutdown_lan_hmc(hw);
1799 i40e_res_pool_destroy(&pf->msix_pool);
1801 i40e_res_pool_destroy(&pf->qp_pool);
1804 err_get_capabilities:
1805 (void)i40e_shutdown_adminq(hw);
1811 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1813 struct i40e_ethertype_filter *p_ethertype;
1814 struct i40e_ethertype_rule *ethertype_rule;
1816 ethertype_rule = &pf->ethertype;
1817 /* Remove all ethertype filter rules and hash */
1818 if (ethertype_rule->hash_map)
1819 rte_free(ethertype_rule->hash_map);
1820 if (ethertype_rule->hash_table)
1821 rte_hash_free(ethertype_rule->hash_table);
1823 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1824 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1825 p_ethertype, rules);
1826 rte_free(p_ethertype);
1831 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1833 struct i40e_tunnel_filter *p_tunnel;
1834 struct i40e_tunnel_rule *tunnel_rule;
1836 tunnel_rule = &pf->tunnel;
1837 /* Remove all tunnel director rules and hash */
1838 if (tunnel_rule->hash_map)
1839 rte_free(tunnel_rule->hash_map);
1840 if (tunnel_rule->hash_table)
1841 rte_hash_free(tunnel_rule->hash_table);
1843 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1844 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1850 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1852 struct i40e_fdir_filter *p_fdir;
1853 struct i40e_fdir_info *fdir_info;
1855 fdir_info = &pf->fdir;
1857 /* Remove all flow director rules */
1858 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1859 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1863 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1865 struct i40e_fdir_info *fdir_info;
1867 fdir_info = &pf->fdir;
1869 /* flow director memory cleanup */
1870 if (fdir_info->hash_map)
1871 rte_free(fdir_info->hash_map);
1872 if (fdir_info->hash_table)
1873 rte_hash_free(fdir_info->hash_table);
1874 if (fdir_info->fdir_flow_pool.bitmap)
1875 rte_free(fdir_info->fdir_flow_pool.bitmap);
1876 if (fdir_info->fdir_flow_pool.pool)
1877 rte_free(fdir_info->fdir_flow_pool.pool);
1878 if (fdir_info->fdir_filter_array)
1879 rte_free(fdir_info->fdir_filter_array);
1882 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1885 * Disable by default flexible payload
1886 * for corresponding L2/L3/L4 layers.
1888 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1889 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1890 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1894 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1898 PMD_INIT_FUNC_TRACE();
1900 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1903 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905 if (hw->adapter_closed == 0)
1906 i40e_dev_close(dev);
1912 i40e_dev_configure(struct rte_eth_dev *dev)
1914 struct i40e_adapter *ad =
1915 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1916 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1921 ret = i40e_dev_sync_phy_type(hw);
1925 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1926 * bulk allocation or vector Rx preconditions we will reset it.
1928 ad->rx_bulk_alloc_allowed = true;
1929 ad->rx_vec_allowed = true;
1930 ad->tx_simple_allowed = true;
1931 ad->tx_vec_allowed = true;
1933 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1934 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1936 /* Only legacy filter API needs the following fdir config. So when the
1937 * legacy filter API is deprecated, the following codes should also be
1940 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1941 ret = i40e_fdir_setup(pf);
1942 if (ret != I40E_SUCCESS) {
1943 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1946 ret = i40e_fdir_configure(dev);
1948 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1952 i40e_fdir_teardown(pf);
1954 ret = i40e_dev_init_vlan(dev);
1959 * General PMD driver call sequence are NIC init, configure,
1960 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961 * will try to lookup the VSI that specific queue belongs to if VMDQ
1962 * applicable. So, VMDQ setting has to be done before
1963 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1964 * For RSS setting, it will try to calculate actual configured RX queue
1965 * number, which will be available after rx_queue_setup(). dev_start()
1966 * function is good to place RSS setup.
1968 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969 ret = i40e_vmdq_setup(dev);
1974 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975 ret = i40e_dcb_setup(dev);
1977 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1982 TAILQ_INIT(&pf->flow_list);
1987 /* need to release vmdq resource if exists */
1988 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989 i40e_vsi_release(pf->vmdq[i].vsi);
1990 pf->vmdq[i].vsi = NULL;
1995 /* Need to release fdir resource if exists.
1996 * Only legacy filter API needs the following fdir config. So when the
1997 * legacy filter API is deprecated, the following code should also be
2000 i40e_fdir_teardown(pf);
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2007 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011 uint16_t msix_vect = vsi->msix_intr;
2014 for (i = 0; i < vsi->nb_qps; i++) {
2015 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2020 if (vsi->type != I40E_VSI_SRIOV) {
2021 if (!rte_intr_allow_others(intr_handle)) {
2022 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2025 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2028 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2031 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2036 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037 vsi->user_param + (msix_vect - 1);
2039 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2042 I40E_WRITE_FLUSH(hw);
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047 int base_queue, int nb_queue,
2052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2055 /* Bind all RX queues to allocated MSIX interrupt */
2056 for (i = 0; i < nb_queue; i++) {
2057 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059 ((base_queue + i + 1) <<
2060 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2064 if (i == nb_queue - 1)
2065 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2069 /* Write first RX queue to Link list register as the head element */
2070 if (vsi->type != I40E_VSI_SRIOV) {
2072 i40e_calc_itr_interval(1, pf->support_multi_driver);
2074 if (msix_vect == I40E_MISC_VEC_ID) {
2075 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2077 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2079 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2081 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2084 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2086 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2088 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2090 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2097 if (msix_vect == I40E_MISC_VEC_ID) {
2099 I40E_VPINT_LNKLST0(vsi->user_param),
2101 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2103 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2105 /* num_msix_vectors_vf needs to minus irq0 */
2106 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107 vsi->user_param + (msix_vect - 1);
2109 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2111 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2113 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2117 I40E_WRITE_FLUSH(hw);
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2123 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127 uint16_t msix_vect = vsi->msix_intr;
2128 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129 uint16_t queue_idx = 0;
2133 for (i = 0; i < vsi->nb_qps; i++) {
2134 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2138 /* VF bind interrupt */
2139 if (vsi->type == I40E_VSI_SRIOV) {
2140 if (vsi->nb_msix == 0) {
2141 PMD_DRV_LOG(ERR, "No msix resource");
2144 __vsi_queues_bind_intr(vsi, msix_vect,
2145 vsi->base_queue, vsi->nb_qps,
2150 /* PF & VMDq bind interrupt */
2151 if (rte_intr_dp_is_en(intr_handle)) {
2152 if (vsi->type == I40E_VSI_MAIN) {
2155 } else if (vsi->type == I40E_VSI_VMDQ2) {
2156 struct i40e_vsi *main_vsi =
2157 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2158 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2163 for (i = 0; i < vsi->nb_used_qps; i++) {
2164 if (vsi->nb_msix == 0) {
2165 PMD_DRV_LOG(ERR, "No msix resource");
2167 } else if (nb_msix <= 1) {
2168 if (!rte_intr_allow_others(intr_handle))
2169 /* allow to share MISC_VEC_ID */
2170 msix_vect = I40E_MISC_VEC_ID;
2172 /* no enough msix_vect, map all to one */
2173 __vsi_queues_bind_intr(vsi, msix_vect,
2174 vsi->base_queue + i,
2175 vsi->nb_used_qps - i,
2177 for (; !!record && i < vsi->nb_used_qps; i++)
2178 intr_handle->intr_vec[queue_idx + i] =
2182 /* 1:1 queue/msix_vect mapping */
2183 __vsi_queues_bind_intr(vsi, msix_vect,
2184 vsi->base_queue + i, 1,
2187 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2197 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2199 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2200 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2204 uint16_t msix_intr, i;
2206 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2207 for (i = 0; i < vsi->nb_msix; i++) {
2208 msix_intr = vsi->msix_intr + i;
2209 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2210 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2211 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2212 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2215 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2216 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2217 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2218 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2220 I40E_WRITE_FLUSH(hw);
2224 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2226 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2227 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2229 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2230 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2231 uint16_t msix_intr, i;
2233 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2234 for (i = 0; i < vsi->nb_msix; i++) {
2235 msix_intr = vsi->msix_intr + i;
2236 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2237 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2240 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2241 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2243 I40E_WRITE_FLUSH(hw);
2246 static inline uint8_t
2247 i40e_parse_link_speeds(uint16_t link_speeds)
2249 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2251 if (link_speeds & ETH_LINK_SPEED_40G)
2252 link_speed |= I40E_LINK_SPEED_40GB;
2253 if (link_speeds & ETH_LINK_SPEED_25G)
2254 link_speed |= I40E_LINK_SPEED_25GB;
2255 if (link_speeds & ETH_LINK_SPEED_20G)
2256 link_speed |= I40E_LINK_SPEED_20GB;
2257 if (link_speeds & ETH_LINK_SPEED_10G)
2258 link_speed |= I40E_LINK_SPEED_10GB;
2259 if (link_speeds & ETH_LINK_SPEED_1G)
2260 link_speed |= I40E_LINK_SPEED_1GB;
2261 if (link_speeds & ETH_LINK_SPEED_100M)
2262 link_speed |= I40E_LINK_SPEED_100MB;
2268 i40e_phy_conf_link(struct i40e_hw *hw,
2270 uint8_t force_speed,
2273 enum i40e_status_code status;
2274 struct i40e_aq_get_phy_abilities_resp phy_ab;
2275 struct i40e_aq_set_phy_config phy_conf;
2276 enum i40e_aq_phy_type cnt;
2277 uint8_t avail_speed;
2278 uint32_t phy_type_mask = 0;
2280 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2281 I40E_AQ_PHY_FLAG_PAUSE_RX |
2282 I40E_AQ_PHY_FLAG_PAUSE_RX |
2283 I40E_AQ_PHY_FLAG_LOW_POWER;
2286 /* To get phy capabilities of available speeds. */
2287 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2290 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2294 avail_speed = phy_ab.link_speed;
2296 /* To get the current phy config. */
2297 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2300 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2305 /* If link needs to go up and it is in autoneg mode the speed is OK,
2306 * no need to set up again.
2308 if (is_up && phy_ab.phy_type != 0 &&
2309 abilities & I40E_AQ_PHY_AN_ENABLED &&
2310 phy_ab.link_speed != 0)
2311 return I40E_SUCCESS;
2313 memset(&phy_conf, 0, sizeof(phy_conf));
2315 /* bits 0-2 use the values from get_phy_abilities_resp */
2317 abilities |= phy_ab.abilities & mask;
2319 phy_conf.abilities = abilities;
2321 /* If link needs to go up, but the force speed is not supported,
2322 * Warn users and config the default available speeds.
2324 if (is_up && !(force_speed & avail_speed)) {
2325 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2326 phy_conf.link_speed = avail_speed;
2328 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2331 /* PHY type mask needs to include each type except PHY type extension */
2332 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2333 phy_type_mask |= 1 << cnt;
2335 /* use get_phy_abilities_resp value for the rest */
2336 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2337 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2338 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2339 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2340 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2341 phy_conf.eee_capability = phy_ab.eee_capability;
2342 phy_conf.eeer = phy_ab.eeer_val;
2343 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2345 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2346 phy_ab.abilities, phy_ab.link_speed);
2347 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2348 phy_conf.abilities, phy_conf.link_speed);
2350 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2354 return I40E_SUCCESS;
2358 i40e_apply_link_speed(struct rte_eth_dev *dev)
2361 uint8_t abilities = 0;
2362 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363 struct rte_eth_conf *conf = &dev->data->dev_conf;
2365 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2366 I40E_AQ_PHY_LINK_ENABLED;
2368 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2369 conf->link_speeds = ETH_LINK_SPEED_40G |
2370 ETH_LINK_SPEED_25G |
2371 ETH_LINK_SPEED_20G |
2372 ETH_LINK_SPEED_10G |
2374 ETH_LINK_SPEED_100M;
2376 abilities |= I40E_AQ_PHY_AN_ENABLED;
2378 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2380 speed = i40e_parse_link_speeds(conf->link_speeds);
2382 return i40e_phy_conf_link(hw, abilities, speed, true);
2386 i40e_dev_start(struct rte_eth_dev *dev)
2388 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390 struct i40e_vsi *main_vsi = pf->main_vsi;
2392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2393 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394 uint32_t intr_vector = 0;
2395 struct i40e_vsi *vsi;
2396 uint16_t nb_rxq, nb_txq;
2398 hw->adapter_stopped = 0;
2400 rte_intr_disable(intr_handle);
2402 if ((rte_intr_cap_multiple(intr_handle) ||
2403 !RTE_ETH_DEV_SRIOV(dev).active) &&
2404 dev->data->dev_conf.intr_conf.rxq != 0) {
2405 intr_vector = dev->data->nb_rx_queues;
2406 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2411 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2412 intr_handle->intr_vec =
2413 rte_zmalloc("intr_vec",
2414 dev->data->nb_rx_queues * sizeof(int),
2416 if (!intr_handle->intr_vec) {
2418 "Failed to allocate %d rx_queues intr_vec",
2419 dev->data->nb_rx_queues);
2424 /* Initialize VSI */
2425 ret = i40e_dev_rxtx_init(pf);
2426 if (ret != I40E_SUCCESS) {
2427 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2431 /* Map queues with MSIX interrupt */
2432 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2433 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2434 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2437 i40e_vsi_enable_queues_intr(main_vsi);
2439 /* Map VMDQ VSI queues with MSIX interrupt */
2440 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2441 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2442 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2443 I40E_ITR_INDEX_DEFAULT);
2446 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2449 /* Enable all queues which have been configured */
2450 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2451 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2456 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2457 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2462 /* Enable receiving broadcast packets */
2463 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2464 if (ret != I40E_SUCCESS)
2465 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2467 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2468 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2470 if (ret != I40E_SUCCESS)
2471 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2474 /* Enable the VLAN promiscuous mode. */
2476 for (i = 0; i < pf->vf_num; i++) {
2477 vsi = pf->vfs[i].vsi;
2478 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2483 /* Enable mac loopback mode */
2484 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2485 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2486 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2487 if (ret != I40E_SUCCESS) {
2488 PMD_DRV_LOG(ERR, "fail to set loopback link");
2493 /* Apply link configure */
2494 ret = i40e_apply_link_speed(dev);
2495 if (I40E_SUCCESS != ret) {
2496 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2500 if (!rte_intr_allow_others(intr_handle)) {
2501 rte_intr_callback_unregister(intr_handle,
2502 i40e_dev_interrupt_handler,
2504 /* configure and enable device interrupt */
2505 i40e_pf_config_irq0(hw, FALSE);
2506 i40e_pf_enable_irq0(hw);
2508 if (dev->data->dev_conf.intr_conf.lsc != 0)
2510 "lsc won't enable because of no intr multiplex");
2512 ret = i40e_aq_set_phy_int_mask(hw,
2513 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2514 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2515 I40E_AQ_EVENT_MEDIA_NA), NULL);
2516 if (ret != I40E_SUCCESS)
2517 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2519 /* Call get_link_info aq commond to enable/disable LSE */
2520 i40e_dev_link_update(dev, 0);
2523 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2524 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2525 i40e_dev_alarm_handler, dev);
2527 /* enable uio intr after callback register */
2528 rte_intr_enable(intr_handle);
2531 i40e_filter_restore(pf);
2533 if (pf->tm_conf.root && !pf->tm_conf.committed)
2534 PMD_DRV_LOG(WARNING,
2535 "please call hierarchy_commit() "
2536 "before starting the port");
2538 return I40E_SUCCESS;
2541 for (i = 0; i < nb_txq; i++)
2542 i40e_dev_tx_queue_stop(dev, i);
2544 for (i = 0; i < nb_rxq; i++)
2545 i40e_dev_rx_queue_stop(dev, i);
2551 i40e_dev_stop(struct rte_eth_dev *dev)
2553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555 struct i40e_vsi *main_vsi = pf->main_vsi;
2556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2557 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2560 if (hw->adapter_stopped == 1)
2563 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2564 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2565 rte_intr_enable(intr_handle);
2568 /* Disable all queues */
2569 for (i = 0; i < dev->data->nb_tx_queues; i++)
2570 i40e_dev_tx_queue_stop(dev, i);
2572 for (i = 0; i < dev->data->nb_rx_queues; i++)
2573 i40e_dev_rx_queue_stop(dev, i);
2575 /* un-map queues with interrupt registers */
2576 i40e_vsi_disable_queues_intr(main_vsi);
2577 i40e_vsi_queues_unbind_intr(main_vsi);
2579 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2580 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2581 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2584 /* Clear all queues and release memory */
2585 i40e_dev_clear_queues(dev);
2588 i40e_dev_set_link_down(dev);
2590 if (!rte_intr_allow_others(intr_handle))
2591 /* resume to the default handler */
2592 rte_intr_callback_register(intr_handle,
2593 i40e_dev_interrupt_handler,
2596 /* Clean datapath event and queue/vec mapping */
2597 rte_intr_efd_disable(intr_handle);
2598 if (intr_handle->intr_vec) {
2599 rte_free(intr_handle->intr_vec);
2600 intr_handle->intr_vec = NULL;
2603 /* reset hierarchy commit */
2604 pf->tm_conf.committed = false;
2606 hw->adapter_stopped = 1;
2608 pf->adapter->rss_reta_updated = 0;
2612 i40e_dev_close(struct rte_eth_dev *dev)
2614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2617 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618 struct i40e_mirror_rule *p_mirror;
2619 struct i40e_filter_control_settings settings;
2620 struct rte_flow *p_flow;
2624 uint8_t aq_fail = 0;
2627 PMD_INIT_FUNC_TRACE();
2629 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2631 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2636 /* Remove all mirror rules */
2637 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2638 ret = i40e_aq_del_mirror_rule(hw,
2639 pf->main_vsi->veb->seid,
2640 p_mirror->rule_type,
2642 p_mirror->num_entries,
2645 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2646 "status = %d, aq_err = %d.", ret,
2647 hw->aq.asq_last_status);
2649 /* remove mirror software resource anyway */
2650 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2652 pf->nb_mirror_rule--;
2655 i40e_dev_free_queues(dev);
2657 /* Disable interrupt */
2658 i40e_pf_disable_irq0(hw);
2659 rte_intr_disable(intr_handle);
2662 * Only legacy filter API needs the following fdir config. So when the
2663 * legacy filter API is deprecated, the following code should also be
2666 i40e_fdir_teardown(pf);
2668 /* shutdown and destroy the HMC */
2669 i40e_shutdown_lan_hmc(hw);
2671 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2672 i40e_vsi_release(pf->vmdq[i].vsi);
2673 pf->vmdq[i].vsi = NULL;
2678 /* release all the existing VSIs and VEBs */
2679 i40e_vsi_release(pf->main_vsi);
2681 /* shutdown the adminq */
2682 i40e_aq_queue_shutdown(hw, true);
2683 i40e_shutdown_adminq(hw);
2685 i40e_res_pool_destroy(&pf->qp_pool);
2686 i40e_res_pool_destroy(&pf->msix_pool);
2688 /* Disable flexible payload in global configuration */
2689 if (!pf->support_multi_driver)
2690 i40e_flex_payload_reg_set_default(hw);
2692 /* force a PF reset to clean anything leftover */
2693 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2694 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2695 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2696 I40E_WRITE_FLUSH(hw);
2698 dev->dev_ops = NULL;
2699 dev->rx_pkt_burst = NULL;
2700 dev->tx_pkt_burst = NULL;
2702 /* Clear PXE mode */
2703 i40e_clear_pxe_mode(hw);
2705 /* Unconfigure filter control */
2706 memset(&settings, 0, sizeof(settings));
2707 ret = i40e_set_filter_control(hw, &settings);
2709 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2712 /* Disable flow control */
2713 hw->fc.requested_mode = I40E_FC_NONE;
2714 i40e_set_fc(hw, &aq_fail, TRUE);
2716 /* uninitialize pf host driver */
2717 i40e_pf_host_uninit(dev);
2720 ret = rte_intr_callback_unregister(intr_handle,
2721 i40e_dev_interrupt_handler, dev);
2722 if (ret >= 0 || ret == -ENOENT) {
2724 } else if (ret != -EAGAIN) {
2726 "intr callback unregister failed: %d",
2729 i40e_msec_delay(500);
2730 } while (retries++ < 5);
2732 i40e_rm_ethtype_filter_list(pf);
2733 i40e_rm_tunnel_filter_list(pf);
2734 i40e_rm_fdir_filter_list(pf);
2736 /* Remove all flows */
2737 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2738 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2739 /* Do not free FDIR flows since they are static allocated */
2740 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2744 /* release the fdir static allocated memory */
2745 i40e_fdir_memory_cleanup(pf);
2747 /* Remove all Traffic Manager configuration */
2748 i40e_tm_conf_uninit(dev);
2750 hw->adapter_closed = 1;
2754 * Reset PF device only to re-initialize resources in PMD layer
2757 i40e_dev_reset(struct rte_eth_dev *dev)
2761 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2762 * its VF to make them align with it. The detailed notification
2763 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2764 * To avoid unexpected behavior in VF, currently reset of PF with
2765 * SR-IOV activation is not supported. It might be supported later.
2767 if (dev->data->sriov.active)
2770 ret = eth_i40e_dev_uninit(dev);
2774 ret = eth_i40e_dev_init(dev, NULL);
2780 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 struct i40e_vsi *vsi = pf->main_vsi;
2787 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2789 if (status != I40E_SUCCESS) {
2790 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2794 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2796 if (status != I40E_SUCCESS) {
2797 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2798 /* Rollback unicast promiscuous mode */
2799 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2808 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 struct i40e_vsi *vsi = pf->main_vsi;
2815 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2817 if (status != I40E_SUCCESS) {
2818 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2822 /* must remain in all_multicast mode */
2823 if (dev->data->all_multicast == 1)
2826 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2828 if (status != I40E_SUCCESS) {
2829 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2830 /* Rollback unicast promiscuous mode */
2831 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2840 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2842 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844 struct i40e_vsi *vsi = pf->main_vsi;
2847 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2848 if (ret != I40E_SUCCESS) {
2849 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2857 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2859 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 struct i40e_vsi *vsi = pf->main_vsi;
2864 if (dev->data->promiscuous == 1)
2865 return 0; /* must remain in all_multicast mode */
2867 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2868 vsi->seid, FALSE, NULL);
2869 if (ret != I40E_SUCCESS) {
2870 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2878 * Set device link up.
2881 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2883 /* re-apply link speed setting */
2884 return i40e_apply_link_speed(dev);
2888 * Set device link down.
2891 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2893 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2894 uint8_t abilities = 0;
2895 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2898 return i40e_phy_conf_link(hw, abilities, speed, false);
2901 static __rte_always_inline void
2902 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2904 /* Link status registers and values*/
2905 #define I40E_PRTMAC_LINKSTA 0x001E2420
2906 #define I40E_REG_LINK_UP 0x40000080
2907 #define I40E_PRTMAC_MACC 0x001E24E0
2908 #define I40E_REG_MACC_25GB 0x00020000
2909 #define I40E_REG_SPEED_MASK 0x38000000
2910 #define I40E_REG_SPEED_0 0x00000000
2911 #define I40E_REG_SPEED_1 0x08000000
2912 #define I40E_REG_SPEED_2 0x10000000
2913 #define I40E_REG_SPEED_3 0x18000000
2914 #define I40E_REG_SPEED_4 0x20000000
2915 uint32_t link_speed;
2918 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2919 link_speed = reg_val & I40E_REG_SPEED_MASK;
2920 reg_val &= I40E_REG_LINK_UP;
2921 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2923 if (unlikely(link->link_status == 0))
2926 /* Parse the link status */
2927 switch (link_speed) {
2928 case I40E_REG_SPEED_0:
2929 link->link_speed = ETH_SPEED_NUM_100M;
2931 case I40E_REG_SPEED_1:
2932 link->link_speed = ETH_SPEED_NUM_1G;
2934 case I40E_REG_SPEED_2:
2935 if (hw->mac.type == I40E_MAC_X722)
2936 link->link_speed = ETH_SPEED_NUM_2_5G;
2938 link->link_speed = ETH_SPEED_NUM_10G;
2940 case I40E_REG_SPEED_3:
2941 if (hw->mac.type == I40E_MAC_X722) {
2942 link->link_speed = ETH_SPEED_NUM_5G;
2944 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2946 if (reg_val & I40E_REG_MACC_25GB)
2947 link->link_speed = ETH_SPEED_NUM_25G;
2949 link->link_speed = ETH_SPEED_NUM_40G;
2952 case I40E_REG_SPEED_4:
2953 if (hw->mac.type == I40E_MAC_X722)
2954 link->link_speed = ETH_SPEED_NUM_10G;
2956 link->link_speed = ETH_SPEED_NUM_20G;
2959 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2964 static __rte_always_inline void
2965 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2966 bool enable_lse, int wait_to_complete)
2968 #define CHECK_INTERVAL 100 /* 100ms */
2969 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2970 uint32_t rep_cnt = MAX_REPEAT_TIME;
2971 struct i40e_link_status link_status;
2974 memset(&link_status, 0, sizeof(link_status));
2977 memset(&link_status, 0, sizeof(link_status));
2979 /* Get link status information from hardware */
2980 status = i40e_aq_get_link_info(hw, enable_lse,
2981 &link_status, NULL);
2982 if (unlikely(status != I40E_SUCCESS)) {
2983 link->link_speed = ETH_SPEED_NUM_NONE;
2984 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2985 PMD_DRV_LOG(ERR, "Failed to get link info");
2989 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2990 if (!wait_to_complete || link->link_status)
2993 rte_delay_ms(CHECK_INTERVAL);
2994 } while (--rep_cnt);
2996 /* Parse the link status */
2997 switch (link_status.link_speed) {
2998 case I40E_LINK_SPEED_100MB:
2999 link->link_speed = ETH_SPEED_NUM_100M;
3001 case I40E_LINK_SPEED_1GB:
3002 link->link_speed = ETH_SPEED_NUM_1G;
3004 case I40E_LINK_SPEED_10GB:
3005 link->link_speed = ETH_SPEED_NUM_10G;
3007 case I40E_LINK_SPEED_20GB:
3008 link->link_speed = ETH_SPEED_NUM_20G;
3010 case I40E_LINK_SPEED_25GB:
3011 link->link_speed = ETH_SPEED_NUM_25G;
3013 case I40E_LINK_SPEED_40GB:
3014 link->link_speed = ETH_SPEED_NUM_40G;
3017 link->link_speed = ETH_SPEED_NUM_NONE;
3023 i40e_dev_link_update(struct rte_eth_dev *dev,
3024 int wait_to_complete)
3026 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027 struct rte_eth_link link;
3028 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3031 memset(&link, 0, sizeof(link));
3033 /* i40e uses full duplex only */
3034 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3035 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3036 ETH_LINK_SPEED_FIXED);
3038 if (!wait_to_complete && !enable_lse)
3039 update_link_reg(hw, &link);
3041 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3044 rte_eth_linkstatus_get(hw->switch_dev, &link);
3046 ret = rte_eth_linkstatus_set(dev, &link);
3047 i40e_notify_all_vfs_link_status(dev);
3052 /* Get all the statistics of a VSI */
3054 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3056 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3057 struct i40e_eth_stats *nes = &vsi->eth_stats;
3058 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3059 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3061 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3062 vsi->offset_loaded, &oes->rx_bytes,
3064 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3065 vsi->offset_loaded, &oes->rx_unicast,
3067 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3068 vsi->offset_loaded, &oes->rx_multicast,
3069 &nes->rx_multicast);
3070 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3071 vsi->offset_loaded, &oes->rx_broadcast,
3072 &nes->rx_broadcast);
3073 /* exclude CRC bytes */
3074 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3075 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3077 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3078 &oes->rx_discards, &nes->rx_discards);
3079 /* GLV_REPC not supported */
3080 /* GLV_RMPC not supported */
3081 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3082 &oes->rx_unknown_protocol,
3083 &nes->rx_unknown_protocol);
3084 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3085 vsi->offset_loaded, &oes->tx_bytes,
3087 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3088 vsi->offset_loaded, &oes->tx_unicast,
3090 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3091 vsi->offset_loaded, &oes->tx_multicast,
3092 &nes->tx_multicast);
3093 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3094 vsi->offset_loaded, &oes->tx_broadcast,
3095 &nes->tx_broadcast);
3096 /* GLV_TDPC not supported */
3097 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3098 &oes->tx_errors, &nes->tx_errors);
3099 vsi->offset_loaded = true;
3101 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3103 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3104 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3105 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3106 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3107 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3108 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3109 nes->rx_unknown_protocol);
3110 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3111 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3112 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3113 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3114 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3115 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3116 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3121 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3124 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3125 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3127 /* Get rx/tx bytes of internal transfer packets */
3128 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3129 I40E_GLV_GORCL(hw->port),
3131 &pf->internal_stats_offset.rx_bytes,
3132 &pf->internal_stats.rx_bytes);
3134 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3135 I40E_GLV_GOTCL(hw->port),
3137 &pf->internal_stats_offset.tx_bytes,
3138 &pf->internal_stats.tx_bytes);
3139 /* Get total internal rx packet count */
3140 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3141 I40E_GLV_UPRCL(hw->port),
3143 &pf->internal_stats_offset.rx_unicast,
3144 &pf->internal_stats.rx_unicast);
3145 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3146 I40E_GLV_MPRCL(hw->port),
3148 &pf->internal_stats_offset.rx_multicast,
3149 &pf->internal_stats.rx_multicast);
3150 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3151 I40E_GLV_BPRCL(hw->port),
3153 &pf->internal_stats_offset.rx_broadcast,
3154 &pf->internal_stats.rx_broadcast);
3155 /* Get total internal tx packet count */
3156 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3157 I40E_GLV_UPTCL(hw->port),
3159 &pf->internal_stats_offset.tx_unicast,
3160 &pf->internal_stats.tx_unicast);
3161 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3162 I40E_GLV_MPTCL(hw->port),
3164 &pf->internal_stats_offset.tx_multicast,
3165 &pf->internal_stats.tx_multicast);
3166 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3167 I40E_GLV_BPTCL(hw->port),
3169 &pf->internal_stats_offset.tx_broadcast,
3170 &pf->internal_stats.tx_broadcast);
3172 /* exclude CRC size */
3173 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3174 pf->internal_stats.rx_multicast +
3175 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3177 /* Get statistics of struct i40e_eth_stats */
3178 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3179 I40E_GLPRT_GORCL(hw->port),
3180 pf->offset_loaded, &os->eth.rx_bytes,
3182 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3183 I40E_GLPRT_UPRCL(hw->port),
3184 pf->offset_loaded, &os->eth.rx_unicast,
3185 &ns->eth.rx_unicast);
3186 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3187 I40E_GLPRT_MPRCL(hw->port),
3188 pf->offset_loaded, &os->eth.rx_multicast,
3189 &ns->eth.rx_multicast);
3190 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3191 I40E_GLPRT_BPRCL(hw->port),
3192 pf->offset_loaded, &os->eth.rx_broadcast,
3193 &ns->eth.rx_broadcast);
3194 /* Workaround: CRC size should not be included in byte statistics,
3195 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3198 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3199 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3201 /* exclude internal rx bytes
3202 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3203 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3205 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3207 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3208 ns->eth.rx_bytes = 0;
3210 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3212 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3213 ns->eth.rx_unicast = 0;
3215 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3217 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3218 ns->eth.rx_multicast = 0;
3220 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3222 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3223 ns->eth.rx_broadcast = 0;
3225 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3227 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3228 pf->offset_loaded, &os->eth.rx_discards,
3229 &ns->eth.rx_discards);
3230 /* GLPRT_REPC not supported */
3231 /* GLPRT_RMPC not supported */
3232 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3234 &os->eth.rx_unknown_protocol,
3235 &ns->eth.rx_unknown_protocol);
3236 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3237 I40E_GLPRT_GOTCL(hw->port),
3238 pf->offset_loaded, &os->eth.tx_bytes,
3240 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3241 I40E_GLPRT_UPTCL(hw->port),
3242 pf->offset_loaded, &os->eth.tx_unicast,
3243 &ns->eth.tx_unicast);
3244 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3245 I40E_GLPRT_MPTCL(hw->port),
3246 pf->offset_loaded, &os->eth.tx_multicast,
3247 &ns->eth.tx_multicast);
3248 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3249 I40E_GLPRT_BPTCL(hw->port),
3250 pf->offset_loaded, &os->eth.tx_broadcast,
3251 &ns->eth.tx_broadcast);
3252 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3253 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3255 /* exclude internal tx bytes
3256 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3257 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3259 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3261 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3262 ns->eth.tx_bytes = 0;
3264 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3266 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3267 ns->eth.tx_unicast = 0;
3269 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3271 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3272 ns->eth.tx_multicast = 0;
3274 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3276 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3277 ns->eth.tx_broadcast = 0;
3279 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3281 /* GLPRT_TEPC not supported */
3283 /* additional port specific stats */
3284 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3285 pf->offset_loaded, &os->tx_dropped_link_down,
3286 &ns->tx_dropped_link_down);
3287 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3288 pf->offset_loaded, &os->crc_errors,
3290 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3291 pf->offset_loaded, &os->illegal_bytes,
3292 &ns->illegal_bytes);
3293 /* GLPRT_ERRBC not supported */
3294 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3295 pf->offset_loaded, &os->mac_local_faults,
3296 &ns->mac_local_faults);
3297 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3298 pf->offset_loaded, &os->mac_remote_faults,
3299 &ns->mac_remote_faults);
3300 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3301 pf->offset_loaded, &os->rx_length_errors,
3302 &ns->rx_length_errors);
3303 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3304 pf->offset_loaded, &os->link_xon_rx,
3306 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3307 pf->offset_loaded, &os->link_xoff_rx,
3309 for (i = 0; i < 8; i++) {
3310 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3312 &os->priority_xon_rx[i],
3313 &ns->priority_xon_rx[i]);
3314 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3316 &os->priority_xoff_rx[i],
3317 &ns->priority_xoff_rx[i]);
3319 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3320 pf->offset_loaded, &os->link_xon_tx,
3322 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3323 pf->offset_loaded, &os->link_xoff_tx,
3325 for (i = 0; i < 8; i++) {
3326 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3328 &os->priority_xon_tx[i],
3329 &ns->priority_xon_tx[i]);
3330 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3332 &os->priority_xoff_tx[i],
3333 &ns->priority_xoff_tx[i]);
3334 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3336 &os->priority_xon_2_xoff[i],
3337 &ns->priority_xon_2_xoff[i]);
3339 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3340 I40E_GLPRT_PRC64L(hw->port),
3341 pf->offset_loaded, &os->rx_size_64,
3343 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3344 I40E_GLPRT_PRC127L(hw->port),
3345 pf->offset_loaded, &os->rx_size_127,
3347 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3348 I40E_GLPRT_PRC255L(hw->port),
3349 pf->offset_loaded, &os->rx_size_255,
3351 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3352 I40E_GLPRT_PRC511L(hw->port),
3353 pf->offset_loaded, &os->rx_size_511,
3355 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3356 I40E_GLPRT_PRC1023L(hw->port),
3357 pf->offset_loaded, &os->rx_size_1023,
3359 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3360 I40E_GLPRT_PRC1522L(hw->port),
3361 pf->offset_loaded, &os->rx_size_1522,
3363 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3364 I40E_GLPRT_PRC9522L(hw->port),
3365 pf->offset_loaded, &os->rx_size_big,
3367 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3368 pf->offset_loaded, &os->rx_undersize,
3370 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3371 pf->offset_loaded, &os->rx_fragments,
3373 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3374 pf->offset_loaded, &os->rx_oversize,
3376 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3377 pf->offset_loaded, &os->rx_jabber,
3379 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3380 I40E_GLPRT_PTC64L(hw->port),
3381 pf->offset_loaded, &os->tx_size_64,
3383 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3384 I40E_GLPRT_PTC127L(hw->port),
3385 pf->offset_loaded, &os->tx_size_127,
3387 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3388 I40E_GLPRT_PTC255L(hw->port),
3389 pf->offset_loaded, &os->tx_size_255,
3391 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3392 I40E_GLPRT_PTC511L(hw->port),
3393 pf->offset_loaded, &os->tx_size_511,
3395 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3396 I40E_GLPRT_PTC1023L(hw->port),
3397 pf->offset_loaded, &os->tx_size_1023,
3399 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3400 I40E_GLPRT_PTC1522L(hw->port),
3401 pf->offset_loaded, &os->tx_size_1522,
3403 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3404 I40E_GLPRT_PTC9522L(hw->port),
3405 pf->offset_loaded, &os->tx_size_big,
3407 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3409 &os->fd_sb_match, &ns->fd_sb_match);
3410 /* GLPRT_MSPDC not supported */
3411 /* GLPRT_XEC not supported */
3413 pf->offset_loaded = true;
3416 i40e_update_vsi_stats(pf->main_vsi);
3419 /* Get all statistics of a port */
3421 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3423 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3424 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3426 struct i40e_vsi *vsi;
3429 /* call read registers - updates values, now write them to struct */
3430 i40e_read_stats_registers(pf, hw);
3432 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3433 pf->main_vsi->eth_stats.rx_multicast +
3434 pf->main_vsi->eth_stats.rx_broadcast -
3435 pf->main_vsi->eth_stats.rx_discards;
3436 stats->opackets = ns->eth.tx_unicast +
3437 ns->eth.tx_multicast +
3438 ns->eth.tx_broadcast;
3439 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3440 stats->obytes = ns->eth.tx_bytes;
3441 stats->oerrors = ns->eth.tx_errors +
3442 pf->main_vsi->eth_stats.tx_errors;
3445 stats->imissed = ns->eth.rx_discards +
3446 pf->main_vsi->eth_stats.rx_discards;
3447 stats->ierrors = ns->crc_errors +
3448 ns->rx_length_errors + ns->rx_undersize +
3449 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3452 for (i = 0; i < pf->vf_num; i++) {
3453 vsi = pf->vfs[i].vsi;
3454 i40e_update_vsi_stats(vsi);
3456 stats->ipackets += (vsi->eth_stats.rx_unicast +
3457 vsi->eth_stats.rx_multicast +
3458 vsi->eth_stats.rx_broadcast -
3459 vsi->eth_stats.rx_discards);
3460 stats->ibytes += vsi->eth_stats.rx_bytes;
3461 stats->oerrors += vsi->eth_stats.tx_errors;
3462 stats->imissed += vsi->eth_stats.rx_discards;
3466 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3467 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3468 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3469 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3470 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3471 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3472 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3473 ns->eth.rx_unknown_protocol);
3474 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3475 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3476 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3477 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3478 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3479 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3481 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3482 ns->tx_dropped_link_down);
3483 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3484 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3486 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3487 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3488 ns->mac_local_faults);
3489 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3490 ns->mac_remote_faults);
3491 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3492 ns->rx_length_errors);
3493 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3494 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3495 for (i = 0; i < 8; i++) {
3496 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3497 i, ns->priority_xon_rx[i]);
3498 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3499 i, ns->priority_xoff_rx[i]);
3501 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3502 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3503 for (i = 0; i < 8; i++) {
3504 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3505 i, ns->priority_xon_tx[i]);
3506 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3507 i, ns->priority_xoff_tx[i]);
3508 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3509 i, ns->priority_xon_2_xoff[i]);
3511 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3512 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3513 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3514 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3515 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3516 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3517 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3518 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3519 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3520 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3521 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3522 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3523 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3524 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3525 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3526 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3527 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3528 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3529 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3530 ns->mac_short_packet_dropped);
3531 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3532 ns->checksum_error);
3533 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3534 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3538 /* Reset the statistics */
3540 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3542 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3543 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3545 /* Mark PF and VSI stats to update the offset, aka "reset" */
3546 pf->offset_loaded = false;
3548 pf->main_vsi->offset_loaded = false;
3550 /* read the stats, reading current register values into offset */
3551 i40e_read_stats_registers(pf, hw);
3557 i40e_xstats_calc_num(void)
3559 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3560 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3561 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3564 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3565 struct rte_eth_xstat_name *xstats_names,
3566 __rte_unused unsigned limit)
3571 if (xstats_names == NULL)
3572 return i40e_xstats_calc_num();
3574 /* Note: limit checked in rte_eth_xstats_names() */
3576 /* Get stats from i40e_eth_stats struct */
3577 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3578 strlcpy(xstats_names[count].name,
3579 rte_i40e_stats_strings[i].name,
3580 sizeof(xstats_names[count].name));
3584 /* Get individiual stats from i40e_hw_port struct */
3585 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3586 strlcpy(xstats_names[count].name,
3587 rte_i40e_hw_port_strings[i].name,
3588 sizeof(xstats_names[count].name));
3592 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3593 for (prio = 0; prio < 8; prio++) {
3594 snprintf(xstats_names[count].name,
3595 sizeof(xstats_names[count].name),
3596 "rx_priority%u_%s", prio,
3597 rte_i40e_rxq_prio_strings[i].name);
3602 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3603 for (prio = 0; prio < 8; prio++) {
3604 snprintf(xstats_names[count].name,
3605 sizeof(xstats_names[count].name),
3606 "tx_priority%u_%s", prio,
3607 rte_i40e_txq_prio_strings[i].name);
3615 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3618 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3619 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620 unsigned i, count, prio;
3621 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3623 count = i40e_xstats_calc_num();
3627 i40e_read_stats_registers(pf, hw);
3634 /* Get stats from i40e_eth_stats struct */
3635 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3636 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3637 rte_i40e_stats_strings[i].offset);
3638 xstats[count].id = count;
3642 /* Get individiual stats from i40e_hw_port struct */
3643 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3644 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3645 rte_i40e_hw_port_strings[i].offset);
3646 xstats[count].id = count;
3650 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3651 for (prio = 0; prio < 8; prio++) {
3652 xstats[count].value =
3653 *(uint64_t *)(((char *)hw_stats) +
3654 rte_i40e_rxq_prio_strings[i].offset +
3655 (sizeof(uint64_t) * prio));
3656 xstats[count].id = count;
3661 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3662 for (prio = 0; prio < 8; prio++) {
3663 xstats[count].value =
3664 *(uint64_t *)(((char *)hw_stats) +
3665 rte_i40e_txq_prio_strings[i].offset +
3666 (sizeof(uint64_t) * prio));
3667 xstats[count].id = count;
3676 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3678 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3684 full_ver = hw->nvm.oem_ver;
3685 ver = (u8)(full_ver >> 24);
3686 build = (u16)((full_ver >> 8) & 0xffff);
3687 patch = (u8)(full_ver & 0xff);
3689 ret = snprintf(fw_version, fw_size,
3690 "%d.%d%d 0x%08x %d.%d.%d",
3691 ((hw->nvm.version >> 12) & 0xf),
3692 ((hw->nvm.version >> 4) & 0xff),
3693 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3696 ret += 1; /* add the size of '\0' */
3697 if (fw_size < (u32)ret)
3704 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3705 * the Rx data path does not hang if the FW LLDP is stopped.
3706 * return true if lldp need to stop
3707 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3710 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3713 char ver_str[64] = {0};
3714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 i40e_fw_version_get(dev, ver_str, 64);
3717 nvm_ver = atof(ver_str);
3718 if ((hw->mac.type == I40E_MAC_X722 ||
3719 hw->mac.type == I40E_MAC_X722_VF) &&
3720 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3722 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3729 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3731 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733 struct i40e_vsi *vsi = pf->main_vsi;
3734 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3736 dev_info->max_rx_queues = vsi->nb_qps;
3737 dev_info->max_tx_queues = vsi->nb_qps;
3738 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3739 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3740 dev_info->max_mac_addrs = vsi->max_macaddrs;
3741 dev_info->max_vfs = pci_dev->max_vfs;
3742 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3743 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3744 dev_info->rx_queue_offload_capa = 0;
3745 dev_info->rx_offload_capa =
3746 DEV_RX_OFFLOAD_VLAN_STRIP |
3747 DEV_RX_OFFLOAD_QINQ_STRIP |
3748 DEV_RX_OFFLOAD_IPV4_CKSUM |
3749 DEV_RX_OFFLOAD_UDP_CKSUM |
3750 DEV_RX_OFFLOAD_TCP_CKSUM |
3751 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3752 DEV_RX_OFFLOAD_KEEP_CRC |
3753 DEV_RX_OFFLOAD_SCATTER |
3754 DEV_RX_OFFLOAD_VLAN_EXTEND |
3755 DEV_RX_OFFLOAD_VLAN_FILTER |
3756 DEV_RX_OFFLOAD_JUMBO_FRAME |
3757 DEV_RX_OFFLOAD_RSS_HASH;
3759 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3760 dev_info->tx_offload_capa =
3761 DEV_TX_OFFLOAD_VLAN_INSERT |
3762 DEV_TX_OFFLOAD_QINQ_INSERT |
3763 DEV_TX_OFFLOAD_IPV4_CKSUM |
3764 DEV_TX_OFFLOAD_UDP_CKSUM |
3765 DEV_TX_OFFLOAD_TCP_CKSUM |
3766 DEV_TX_OFFLOAD_SCTP_CKSUM |
3767 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3768 DEV_TX_OFFLOAD_TCP_TSO |
3769 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3770 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3771 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3772 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3773 DEV_TX_OFFLOAD_MULTI_SEGS |
3774 dev_info->tx_queue_offload_capa;
3775 dev_info->dev_capa =
3776 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3777 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3779 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3781 dev_info->reta_size = pf->hash_lut_size;
3782 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3784 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3786 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3787 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3788 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3790 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3795 dev_info->default_txconf = (struct rte_eth_txconf) {
3797 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3798 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3799 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3801 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3802 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3806 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3807 .nb_max = I40E_MAX_RING_DESC,
3808 .nb_min = I40E_MIN_RING_DESC,
3809 .nb_align = I40E_ALIGN_RING_DESC,
3812 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3813 .nb_max = I40E_MAX_RING_DESC,
3814 .nb_min = I40E_MIN_RING_DESC,
3815 .nb_align = I40E_ALIGN_RING_DESC,
3816 .nb_seg_max = I40E_TX_MAX_SEG,
3817 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3820 if (pf->flags & I40E_FLAG_VMDQ) {
3821 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3822 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3823 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3824 pf->max_nb_vmdq_vsi;
3825 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3826 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3827 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3830 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3832 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3833 dev_info->default_rxportconf.nb_queues = 2;
3834 dev_info->default_txportconf.nb_queues = 2;
3835 if (dev->data->nb_rx_queues == 1)
3836 dev_info->default_rxportconf.ring_size = 2048;
3838 dev_info->default_rxportconf.ring_size = 1024;
3839 if (dev->data->nb_tx_queues == 1)
3840 dev_info->default_txportconf.ring_size = 1024;
3842 dev_info->default_txportconf.ring_size = 512;
3844 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3846 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3847 dev_info->default_rxportconf.nb_queues = 1;
3848 dev_info->default_txportconf.nb_queues = 1;
3849 dev_info->default_rxportconf.ring_size = 256;
3850 dev_info->default_txportconf.ring_size = 256;
3853 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3854 dev_info->default_rxportconf.nb_queues = 1;
3855 dev_info->default_txportconf.nb_queues = 1;
3856 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3857 dev_info->default_rxportconf.ring_size = 512;
3858 dev_info->default_txportconf.ring_size = 256;
3860 dev_info->default_rxportconf.ring_size = 256;
3861 dev_info->default_txportconf.ring_size = 256;
3864 dev_info->default_rxportconf.burst_size = 32;
3865 dev_info->default_txportconf.burst_size = 32;
3871 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3873 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3874 struct i40e_vsi *vsi = pf->main_vsi;
3875 PMD_INIT_FUNC_TRACE();
3878 return i40e_vsi_add_vlan(vsi, vlan_id);
3880 return i40e_vsi_delete_vlan(vsi, vlan_id);
3884 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3885 enum rte_vlan_type vlan_type,
3886 uint16_t tpid, int qinq)
3888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3891 uint16_t reg_id = 3;
3895 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3899 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3901 if (ret != I40E_SUCCESS) {
3903 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3908 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3911 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3912 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3913 if (reg_r == reg_w) {
3914 PMD_DRV_LOG(DEBUG, "No need to write");
3918 ret = i40e_aq_debug_write_global_register(hw,
3919 I40E_GL_SWT_L2TAGCTRL(reg_id),
3921 if (ret != I40E_SUCCESS) {
3923 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3928 "Global register 0x%08x is changed with value 0x%08x",
3929 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3935 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3936 enum rte_vlan_type vlan_type,
3939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3941 int qinq = dev->data->dev_conf.rxmode.offloads &
3942 DEV_RX_OFFLOAD_VLAN_EXTEND;
3945 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3946 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3947 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3949 "Unsupported vlan type.");
3953 if (pf->support_multi_driver) {
3954 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3958 /* 802.1ad frames ability is added in NVM API 1.7*/
3959 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3961 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3962 hw->first_tag = rte_cpu_to_le_16(tpid);
3963 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3964 hw->second_tag = rte_cpu_to_le_16(tpid);
3966 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3967 hw->second_tag = rte_cpu_to_le_16(tpid);
3969 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3970 if (ret != I40E_SUCCESS) {
3972 "Set switch config failed aq_err: %d",
3973 hw->aq.asq_last_status);
3977 /* If NVM API < 1.7, keep the register setting */
3978 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3984 /* Configure outer vlan stripping on or off in QinQ mode */
3986 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3989 int ret = I40E_SUCCESS;
3992 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3993 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3997 /* Configure for outer VLAN RX stripping */
3998 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4001 reg |= I40E_VSI_TSR_QINQ_STRIP;
4003 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4005 ret = i40e_aq_debug_write_register(hw,
4006 I40E_VSI_TSR(vsi->vsi_id),
4009 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4011 return I40E_ERR_CONFIG;
4018 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4020 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4021 struct i40e_vsi *vsi = pf->main_vsi;
4022 struct rte_eth_rxmode *rxmode;
4024 rxmode = &dev->data->dev_conf.rxmode;
4025 if (mask & ETH_VLAN_FILTER_MASK) {
4026 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4027 i40e_vsi_config_vlan_filter(vsi, TRUE);
4029 i40e_vsi_config_vlan_filter(vsi, FALSE);
4032 if (mask & ETH_VLAN_STRIP_MASK) {
4033 /* Enable or disable VLAN stripping */
4034 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4035 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4037 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4040 if (mask & ETH_VLAN_EXTEND_MASK) {
4041 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4042 i40e_vsi_config_double_vlan(vsi, TRUE);
4043 /* Set global registers with default ethertype. */
4044 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4045 RTE_ETHER_TYPE_VLAN);
4046 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4047 RTE_ETHER_TYPE_VLAN);
4050 i40e_vsi_config_double_vlan(vsi, FALSE);
4053 if (mask & ETH_QINQ_STRIP_MASK) {
4054 /* Enable or disable outer VLAN stripping */
4055 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4056 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4058 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4065 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4066 __rte_unused uint16_t queue,
4067 __rte_unused int on)
4069 PMD_INIT_FUNC_TRACE();
4073 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4075 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4076 struct i40e_vsi *vsi = pf->main_vsi;
4077 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4078 struct i40e_vsi_vlan_pvid_info info;
4080 memset(&info, 0, sizeof(info));
4083 info.config.pvid = pvid;
4085 info.config.reject.tagged =
4086 data->dev_conf.txmode.hw_vlan_reject_tagged;
4087 info.config.reject.untagged =
4088 data->dev_conf.txmode.hw_vlan_reject_untagged;
4091 return i40e_vsi_vlan_pvid_set(vsi, &info);
4095 i40e_dev_led_on(struct rte_eth_dev *dev)
4097 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4098 uint32_t mode = i40e_led_get(hw);
4101 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4107 i40e_dev_led_off(struct rte_eth_dev *dev)
4109 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110 uint32_t mode = i40e_led_get(hw);
4113 i40e_led_set(hw, 0, false);
4119 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4121 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4124 fc_conf->pause_time = pf->fc_conf.pause_time;
4126 /* read out from register, in case they are modified by other port */
4127 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4128 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4129 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4130 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4132 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4133 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4135 /* Return current mode according to actual setting*/
4136 switch (hw->fc.current_mode) {
4138 fc_conf->mode = RTE_FC_FULL;
4140 case I40E_FC_TX_PAUSE:
4141 fc_conf->mode = RTE_FC_TX_PAUSE;
4143 case I40E_FC_RX_PAUSE:
4144 fc_conf->mode = RTE_FC_RX_PAUSE;
4148 fc_conf->mode = RTE_FC_NONE;
4155 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4157 uint32_t mflcn_reg, fctrl_reg, reg;
4158 uint32_t max_high_water;
4159 uint8_t i, aq_failure;
4163 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4164 [RTE_FC_NONE] = I40E_FC_NONE,
4165 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4166 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4167 [RTE_FC_FULL] = I40E_FC_FULL
4170 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4172 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4173 if ((fc_conf->high_water > max_high_water) ||
4174 (fc_conf->high_water < fc_conf->low_water)) {
4176 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4181 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4183 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4185 pf->fc_conf.pause_time = fc_conf->pause_time;
4186 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4187 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4189 PMD_INIT_FUNC_TRACE();
4191 /* All the link flow control related enable/disable register
4192 * configuration is handle by the F/W
4194 err = i40e_set_fc(hw, &aq_failure, true);
4198 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4199 /* Configure flow control refresh threshold,
4200 * the value for stat_tx_pause_refresh_timer[8]
4201 * is used for global pause operation.
4205 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4206 pf->fc_conf.pause_time);
4208 /* configure the timer value included in transmitted pause
4210 * the value for stat_tx_pause_quanta[8] is used for global
4213 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4214 pf->fc_conf.pause_time);
4216 fctrl_reg = I40E_READ_REG(hw,
4217 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4219 if (fc_conf->mac_ctrl_frame_fwd != 0)
4220 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4222 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4224 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4227 /* Configure pause time (2 TCs per register) */
4228 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4229 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4230 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4232 /* Configure flow control refresh threshold value */
4233 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4234 pf->fc_conf.pause_time / 2);
4236 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4238 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4239 *depending on configuration
4241 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4242 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4243 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4245 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4246 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4249 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4252 if (!pf->support_multi_driver) {
4253 /* config water marker both based on the packets and bytes */
4254 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4255 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4256 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4257 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4258 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4259 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4260 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4261 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4263 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4264 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4268 "Water marker configuration is not supported.");
4271 I40E_WRITE_FLUSH(hw);
4277 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4278 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4280 PMD_INIT_FUNC_TRACE();
4285 /* Add a MAC address, and update filters */
4287 i40e_macaddr_add(struct rte_eth_dev *dev,
4288 struct rte_ether_addr *mac_addr,
4289 __rte_unused uint32_t index,
4292 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4293 struct i40e_mac_filter_info mac_filter;
4294 struct i40e_vsi *vsi;
4295 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4298 /* If VMDQ not enabled or configured, return */
4299 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4300 !pf->nb_cfg_vmdq_vsi)) {
4301 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4302 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4307 if (pool > pf->nb_cfg_vmdq_vsi) {
4308 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4309 pool, pf->nb_cfg_vmdq_vsi);
4313 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4314 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4315 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4317 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4322 vsi = pf->vmdq[pool - 1].vsi;
4324 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4325 if (ret != I40E_SUCCESS) {
4326 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4332 /* Remove a MAC address, and update filters */
4334 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4336 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4337 struct i40e_vsi *vsi;
4338 struct rte_eth_dev_data *data = dev->data;
4339 struct rte_ether_addr *macaddr;
4344 macaddr = &(data->mac_addrs[index]);
4346 pool_sel = dev->data->mac_pool_sel[index];
4348 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4349 if (pool_sel & (1ULL << i)) {
4353 /* No VMDQ pool enabled or configured */
4354 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4355 (i > pf->nb_cfg_vmdq_vsi)) {
4357 "No VMDQ pool enabled/configured");
4360 vsi = pf->vmdq[i - 1].vsi;
4362 ret = i40e_vsi_delete_mac(vsi, macaddr);
4365 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4372 /* Set perfect match or hash match of MAC and VLAN for a VF */
4374 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4375 struct rte_eth_mac_filter *filter,
4379 struct i40e_mac_filter_info mac_filter;
4380 struct rte_ether_addr old_mac;
4381 struct rte_ether_addr *new_mac;
4382 struct i40e_pf_vf *vf = NULL;
4387 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4390 hw = I40E_PF_TO_HW(pf);
4392 if (filter == NULL) {
4393 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4397 new_mac = &filter->mac_addr;
4399 if (rte_is_zero_ether_addr(new_mac)) {
4400 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4404 vf_id = filter->dst_id;
4406 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4407 PMD_DRV_LOG(ERR, "Invalid argument.");
4410 vf = &pf->vfs[vf_id];
4412 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4413 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4418 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4419 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4420 RTE_ETHER_ADDR_LEN);
4421 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4422 RTE_ETHER_ADDR_LEN);
4424 mac_filter.filter_type = filter->filter_type;
4425 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4426 if (ret != I40E_SUCCESS) {
4427 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4430 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4432 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4433 RTE_ETHER_ADDR_LEN);
4434 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4435 if (ret != I40E_SUCCESS) {
4436 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4440 /* Clear device address as it has been removed */
4441 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4442 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4448 /* MAC filter handle */
4450 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4453 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4454 struct rte_eth_mac_filter *filter;
4455 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4456 int ret = I40E_NOT_SUPPORTED;
4458 filter = (struct rte_eth_mac_filter *)(arg);
4460 switch (filter_op) {
4461 case RTE_ETH_FILTER_NOP:
4464 case RTE_ETH_FILTER_ADD:
4465 i40e_pf_disable_irq0(hw);
4467 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4468 i40e_pf_enable_irq0(hw);
4470 case RTE_ETH_FILTER_DELETE:
4471 i40e_pf_disable_irq0(hw);
4473 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4474 i40e_pf_enable_irq0(hw);
4477 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4478 ret = I40E_ERR_PARAM;
4486 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4488 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4489 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4496 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4497 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4498 vsi->type != I40E_VSI_SRIOV,
4501 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4505 uint32_t *lut_dw = (uint32_t *)lut;
4506 uint16_t i, lut_size_dw = lut_size / 4;
4508 if (vsi->type == I40E_VSI_SRIOV) {
4509 for (i = 0; i <= lut_size_dw; i++) {
4510 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4511 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4514 for (i = 0; i < lut_size_dw; i++)
4515 lut_dw[i] = I40E_READ_REG(hw,
4524 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4533 pf = I40E_VSI_TO_PF(vsi);
4534 hw = I40E_VSI_TO_HW(vsi);
4536 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4537 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4538 vsi->type != I40E_VSI_SRIOV,
4541 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4545 uint32_t *lut_dw = (uint32_t *)lut;
4546 uint16_t i, lut_size_dw = lut_size / 4;
4548 if (vsi->type == I40E_VSI_SRIOV) {
4549 for (i = 0; i < lut_size_dw; i++)
4552 I40E_VFQF_HLUT1(i, vsi->user_param),
4555 for (i = 0; i < lut_size_dw; i++)
4556 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4559 I40E_WRITE_FLUSH(hw);
4566 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4567 struct rte_eth_rss_reta_entry64 *reta_conf,
4570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4571 uint16_t i, lut_size = pf->hash_lut_size;
4572 uint16_t idx, shift;
4576 if (reta_size != lut_size ||
4577 reta_size > ETH_RSS_RETA_SIZE_512) {
4579 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4580 reta_size, lut_size);
4584 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4586 PMD_DRV_LOG(ERR, "No memory can be allocated");
4589 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4592 for (i = 0; i < reta_size; i++) {
4593 idx = i / RTE_RETA_GROUP_SIZE;
4594 shift = i % RTE_RETA_GROUP_SIZE;
4595 if (reta_conf[idx].mask & (1ULL << shift))
4596 lut[i] = reta_conf[idx].reta[shift];
4598 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4600 pf->adapter->rss_reta_updated = 1;
4609 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4610 struct rte_eth_rss_reta_entry64 *reta_conf,
4613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4614 uint16_t i, lut_size = pf->hash_lut_size;
4615 uint16_t idx, shift;
4619 if (reta_size != lut_size ||
4620 reta_size > ETH_RSS_RETA_SIZE_512) {
4622 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4623 reta_size, lut_size);
4627 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4629 PMD_DRV_LOG(ERR, "No memory can be allocated");
4633 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4636 for (i = 0; i < reta_size; i++) {
4637 idx = i / RTE_RETA_GROUP_SIZE;
4638 shift = i % RTE_RETA_GROUP_SIZE;
4639 if (reta_conf[idx].mask & (1ULL << shift))
4640 reta_conf[idx].reta[shift] = lut[i];
4650 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4651 * @hw: pointer to the HW structure
4652 * @mem: pointer to mem struct to fill out
4653 * @size: size of memory requested
4654 * @alignment: what to align the allocation to
4656 enum i40e_status_code
4657 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4658 struct i40e_dma_mem *mem,
4662 const struct rte_memzone *mz = NULL;
4663 char z_name[RTE_MEMZONE_NAMESIZE];
4666 return I40E_ERR_PARAM;
4668 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4669 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4670 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4672 return I40E_ERR_NO_MEMORY;
4677 mem->zone = (const void *)mz;
4679 "memzone %s allocated with physical address: %"PRIu64,
4682 return I40E_SUCCESS;
4686 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4687 * @hw: pointer to the HW structure
4688 * @mem: ptr to mem struct to free
4690 enum i40e_status_code
4691 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4692 struct i40e_dma_mem *mem)
4695 return I40E_ERR_PARAM;
4698 "memzone %s to be freed with physical address: %"PRIu64,
4699 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4700 rte_memzone_free((const struct rte_memzone *)mem->zone);
4705 return I40E_SUCCESS;
4709 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4710 * @hw: pointer to the HW structure
4711 * @mem: pointer to mem struct to fill out
4712 * @size: size of memory requested
4714 enum i40e_status_code
4715 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4716 struct i40e_virt_mem *mem,
4720 return I40E_ERR_PARAM;
4723 mem->va = rte_zmalloc("i40e", size, 0);
4726 return I40E_SUCCESS;
4728 return I40E_ERR_NO_MEMORY;
4732 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4733 * @hw: pointer to the HW structure
4734 * @mem: pointer to mem struct to free
4736 enum i40e_status_code
4737 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4738 struct i40e_virt_mem *mem)
4741 return I40E_ERR_PARAM;
4746 return I40E_SUCCESS;
4750 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4752 rte_spinlock_init(&sp->spinlock);
4756 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4758 rte_spinlock_lock(&sp->spinlock);
4762 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4764 rte_spinlock_unlock(&sp->spinlock);
4768 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4774 * Get the hardware capabilities, which will be parsed
4775 * and saved into struct i40e_hw.
4778 i40e_get_cap(struct i40e_hw *hw)
4780 struct i40e_aqc_list_capabilities_element_resp *buf;
4781 uint16_t len, size = 0;
4784 /* Calculate a huge enough buff for saving response data temporarily */
4785 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4786 I40E_MAX_CAP_ELE_NUM;
4787 buf = rte_zmalloc("i40e", len, 0);
4789 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4790 return I40E_ERR_NO_MEMORY;
4793 /* Get, parse the capabilities and save it to hw */
4794 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4795 i40e_aqc_opc_list_func_capabilities, NULL);
4796 if (ret != I40E_SUCCESS)
4797 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4799 /* Free the temporary buffer after being used */
4805 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4807 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4815 pf = (struct i40e_pf *)opaque;
4819 num = strtoul(value, &end, 0);
4820 if (errno != 0 || end == value || *end != 0) {
4821 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4822 "kept the value = %hu", value, pf->vf_nb_qp_max);
4826 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4827 pf->vf_nb_qp_max = (uint16_t)num;
4829 /* here return 0 to make next valid same argument work */
4830 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4831 "power of 2 and equal or less than 16 !, Now it is "
4832 "kept the value = %hu", num, pf->vf_nb_qp_max);
4837 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4839 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4840 struct rte_kvargs *kvlist;
4843 /* set default queue number per VF as 4 */
4844 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4846 if (dev->device->devargs == NULL)
4849 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4853 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4854 if (!kvargs_count) {
4855 rte_kvargs_free(kvlist);
4859 if (kvargs_count > 1)
4860 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4861 "the first invalid or last valid one is used !",
4862 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4864 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4865 i40e_pf_parse_vf_queue_number_handler, pf);
4867 rte_kvargs_free(kvlist);
4873 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4875 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4876 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4877 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4878 uint16_t qp_count = 0, vsi_count = 0;
4880 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4881 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4885 i40e_pf_config_vf_rxq_number(dev);
4887 /* Add the parameter init for LFC */
4888 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4889 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4890 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4892 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4893 pf->max_num_vsi = hw->func_caps.num_vsis;
4894 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4895 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4897 /* FDir queue/VSI allocation */
4898 pf->fdir_qp_offset = 0;
4899 if (hw->func_caps.fd) {
4900 pf->flags |= I40E_FLAG_FDIR;
4901 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4903 pf->fdir_nb_qps = 0;
4905 qp_count += pf->fdir_nb_qps;
4908 /* LAN queue/VSI allocation */
4909 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4910 if (!hw->func_caps.rss) {
4913 pf->flags |= I40E_FLAG_RSS;
4914 if (hw->mac.type == I40E_MAC_X722)
4915 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4916 pf->lan_nb_qps = pf->lan_nb_qp_max;
4918 qp_count += pf->lan_nb_qps;
4921 /* VF queue/VSI allocation */
4922 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4923 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4924 pf->flags |= I40E_FLAG_SRIOV;
4925 pf->vf_nb_qps = pf->vf_nb_qp_max;
4926 pf->vf_num = pci_dev->max_vfs;
4928 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4929 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4934 qp_count += pf->vf_nb_qps * pf->vf_num;
4935 vsi_count += pf->vf_num;
4937 /* VMDq queue/VSI allocation */
4938 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4939 pf->vmdq_nb_qps = 0;
4940 pf->max_nb_vmdq_vsi = 0;
4941 if (hw->func_caps.vmdq) {
4942 if (qp_count < hw->func_caps.num_tx_qp &&
4943 vsi_count < hw->func_caps.num_vsis) {
4944 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4945 qp_count) / pf->vmdq_nb_qp_max;
4947 /* Limit the maximum number of VMDq vsi to the maximum
4948 * ethdev can support
4950 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4951 hw->func_caps.num_vsis - vsi_count);
4952 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4954 if (pf->max_nb_vmdq_vsi) {
4955 pf->flags |= I40E_FLAG_VMDQ;
4956 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4958 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4959 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4960 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4963 "No enough queues left for VMDq");
4966 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4969 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4970 vsi_count += pf->max_nb_vmdq_vsi;
4972 if (hw->func_caps.dcb)
4973 pf->flags |= I40E_FLAG_DCB;
4975 if (qp_count > hw->func_caps.num_tx_qp) {
4977 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4978 qp_count, hw->func_caps.num_tx_qp);
4981 if (vsi_count > hw->func_caps.num_vsis) {
4983 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4984 vsi_count, hw->func_caps.num_vsis);
4992 i40e_pf_get_switch_config(struct i40e_pf *pf)
4994 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4995 struct i40e_aqc_get_switch_config_resp *switch_config;
4996 struct i40e_aqc_switch_config_element_resp *element;
4997 uint16_t start_seid = 0, num_reported;
5000 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
5001 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
5002 if (!switch_config) {
5003 PMD_DRV_LOG(ERR, "Failed to allocated memory");
5007 /* Get the switch configurations */
5008 ret = i40e_aq_get_switch_config(hw, switch_config,
5009 I40E_AQ_LARGE_BUF, &start_seid, NULL);
5010 if (ret != I40E_SUCCESS) {
5011 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
5014 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
5015 if (num_reported != 1) { /* The number should be 1 */
5016 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
5020 /* Parse the switch configuration elements */
5021 element = &(switch_config->element[0]);
5022 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
5023 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
5024 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
5026 PMD_DRV_LOG(INFO, "Unknown element type");
5029 rte_free(switch_config);
5035 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
5038 struct pool_entry *entry;
5040 if (pool == NULL || num == 0)
5043 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5044 if (entry == NULL) {
5045 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5049 /* queue heap initialize */
5050 pool->num_free = num;
5051 pool->num_alloc = 0;
5053 LIST_INIT(&pool->alloc_list);
5054 LIST_INIT(&pool->free_list);
5056 /* Initialize element */
5060 LIST_INSERT_HEAD(&pool->free_list, entry, next);
5065 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5067 struct pool_entry *entry, *next_entry;
5072 for (entry = LIST_FIRST(&pool->alloc_list);
5073 entry && (next_entry = LIST_NEXT(entry, next), 1);
5074 entry = next_entry) {
5075 LIST_REMOVE(entry, next);
5079 for (entry = LIST_FIRST(&pool->free_list);
5080 entry && (next_entry = LIST_NEXT(entry, next), 1);
5081 entry = next_entry) {
5082 LIST_REMOVE(entry, next);
5087 pool->num_alloc = 0;
5089 LIST_INIT(&pool->alloc_list);
5090 LIST_INIT(&pool->free_list);
5094 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5097 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5098 uint32_t pool_offset;
5103 PMD_DRV_LOG(ERR, "Invalid parameter");
5107 pool_offset = base - pool->base;
5108 /* Lookup in alloc list */
5109 LIST_FOREACH(entry, &pool->alloc_list, next) {
5110 if (entry->base == pool_offset) {
5111 valid_entry = entry;
5112 LIST_REMOVE(entry, next);
5117 /* Not find, return */
5118 if (valid_entry == NULL) {
5119 PMD_DRV_LOG(ERR, "Failed to find entry");
5124 * Found it, move it to free list and try to merge.
5125 * In order to make merge easier, always sort it by qbase.
5126 * Find adjacent prev and last entries.
5129 LIST_FOREACH(entry, &pool->free_list, next) {
5130 if (entry->base > valid_entry->base) {
5138 len = valid_entry->len;
5139 /* Try to merge with next one*/
5141 /* Merge with next one */
5142 if (valid_entry->base + len == next->base) {
5143 next->base = valid_entry->base;
5145 rte_free(valid_entry);
5152 /* Merge with previous one */
5153 if (prev->base + prev->len == valid_entry->base) {
5155 /* If it merge with next one, remove next node */
5157 LIST_REMOVE(valid_entry, next);
5158 rte_free(valid_entry);
5161 rte_free(valid_entry);
5168 /* Not find any entry to merge, insert */
5171 LIST_INSERT_AFTER(prev, valid_entry, next);
5172 else if (next != NULL)
5173 LIST_INSERT_BEFORE(next, valid_entry, next);
5174 else /* It's empty list, insert to head */
5175 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5178 pool->num_free += len;
5179 pool->num_alloc -= len;
5185 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5188 struct pool_entry *entry, *valid_entry;
5190 if (pool == NULL || num == 0) {
5191 PMD_DRV_LOG(ERR, "Invalid parameter");
5195 if (pool->num_free < num) {
5196 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5197 num, pool->num_free);
5202 /* Lookup in free list and find most fit one */
5203 LIST_FOREACH(entry, &pool->free_list, next) {
5204 if (entry->len >= num) {
5206 if (entry->len == num) {
5207 valid_entry = entry;
5210 if (valid_entry == NULL || valid_entry->len > entry->len)
5211 valid_entry = entry;
5215 /* Not find one to satisfy the request, return */
5216 if (valid_entry == NULL) {
5217 PMD_DRV_LOG(ERR, "No valid entry found");
5221 * The entry have equal queue number as requested,
5222 * remove it from alloc_list.
5224 if (valid_entry->len == num) {
5225 LIST_REMOVE(valid_entry, next);
5228 * The entry have more numbers than requested,
5229 * create a new entry for alloc_list and minus its
5230 * queue base and number in free_list.
5232 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5233 if (entry == NULL) {
5235 "Failed to allocate memory for resource pool");
5238 entry->base = valid_entry->base;
5240 valid_entry->base += num;
5241 valid_entry->len -= num;
5242 valid_entry = entry;
5245 /* Insert it into alloc list, not sorted */
5246 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5248 pool->num_free -= valid_entry->len;
5249 pool->num_alloc += valid_entry->len;
5251 return valid_entry->base + pool->base;
5255 * bitmap_is_subset - Check whether src2 is subset of src1
5258 bitmap_is_subset(uint8_t src1, uint8_t src2)
5260 return !((src1 ^ src2) & src2);
5263 static enum i40e_status_code
5264 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5266 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5268 /* If DCB is not supported, only default TC is supported */
5269 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5270 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5271 return I40E_NOT_SUPPORTED;
5274 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5276 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5277 hw->func_caps.enabled_tcmap, enabled_tcmap);
5278 return I40E_NOT_SUPPORTED;
5280 return I40E_SUCCESS;
5284 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5285 struct i40e_vsi_vlan_pvid_info *info)
5288 struct i40e_vsi_context ctxt;
5289 uint8_t vlan_flags = 0;
5292 if (vsi == NULL || info == NULL) {
5293 PMD_DRV_LOG(ERR, "invalid parameters");
5294 return I40E_ERR_PARAM;
5298 vsi->info.pvid = info->config.pvid;
5300 * If insert pvid is enabled, only tagged pkts are
5301 * allowed to be sent out.
5303 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5304 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5307 if (info->config.reject.tagged == 0)
5308 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5310 if (info->config.reject.untagged == 0)
5311 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5313 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5314 I40E_AQ_VSI_PVLAN_MODE_MASK);
5315 vsi->info.port_vlan_flags |= vlan_flags;
5316 vsi->info.valid_sections =
5317 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5318 memset(&ctxt, 0, sizeof(ctxt));
5319 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5320 ctxt.seid = vsi->seid;
5322 hw = I40E_VSI_TO_HW(vsi);
5323 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5324 if (ret != I40E_SUCCESS)
5325 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5331 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5333 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5335 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5337 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5338 if (ret != I40E_SUCCESS)
5342 PMD_DRV_LOG(ERR, "seid not valid");
5346 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5347 tc_bw_data.tc_valid_bits = enabled_tcmap;
5348 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5349 tc_bw_data.tc_bw_credits[i] =
5350 (enabled_tcmap & (1 << i)) ? 1 : 0;
5352 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5353 if (ret != I40E_SUCCESS) {
5354 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5358 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5359 sizeof(vsi->info.qs_handle));
5360 return I40E_SUCCESS;
5363 static enum i40e_status_code
5364 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5365 struct i40e_aqc_vsi_properties_data *info,
5366 uint8_t enabled_tcmap)
5368 enum i40e_status_code ret;
5369 int i, total_tc = 0;
5370 uint16_t qpnum_per_tc, bsf, qp_idx;
5372 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5373 if (ret != I40E_SUCCESS)
5376 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5377 if (enabled_tcmap & (1 << i))
5381 vsi->enabled_tc = enabled_tcmap;
5383 /* Number of queues per enabled TC */
5384 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5385 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5386 bsf = rte_bsf32(qpnum_per_tc);
5388 /* Adjust the queue number to actual queues that can be applied */
5389 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5390 vsi->nb_qps = qpnum_per_tc * total_tc;
5393 * Configure TC and queue mapping parameters, for enabled TC,
5394 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5395 * default queue will serve it.
5398 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5399 if (vsi->enabled_tc & (1 << i)) {
5400 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5401 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5402 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5403 qp_idx += qpnum_per_tc;
5405 info->tc_mapping[i] = 0;
5408 /* Associate queue number with VSI */
5409 if (vsi->type == I40E_VSI_SRIOV) {
5410 info->mapping_flags |=
5411 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5412 for (i = 0; i < vsi->nb_qps; i++)
5413 info->queue_mapping[i] =
5414 rte_cpu_to_le_16(vsi->base_queue + i);
5416 info->mapping_flags |=
5417 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5418 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5420 info->valid_sections |=
5421 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5423 return I40E_SUCCESS;
5427 i40e_veb_release(struct i40e_veb *veb)
5429 struct i40e_vsi *vsi;
5435 if (!TAILQ_EMPTY(&veb->head)) {
5436 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5439 /* associate_vsi field is NULL for floating VEB */
5440 if (veb->associate_vsi != NULL) {
5441 vsi = veb->associate_vsi;
5442 hw = I40E_VSI_TO_HW(vsi);
5444 vsi->uplink_seid = veb->uplink_seid;
5447 veb->associate_pf->main_vsi->floating_veb = NULL;
5448 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5451 i40e_aq_delete_element(hw, veb->seid, NULL);
5453 return I40E_SUCCESS;
5457 static struct i40e_veb *
5458 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5460 struct i40e_veb *veb;
5466 "veb setup failed, associated PF shouldn't null");
5469 hw = I40E_PF_TO_HW(pf);
5471 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5473 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5477 veb->associate_vsi = vsi;
5478 veb->associate_pf = pf;
5479 TAILQ_INIT(&veb->head);
5480 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5482 /* create floating veb if vsi is NULL */
5484 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5485 I40E_DEFAULT_TCMAP, false,
5486 &veb->seid, false, NULL);
5488 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5489 true, &veb->seid, false, NULL);
5492 if (ret != I40E_SUCCESS) {
5493 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5494 hw->aq.asq_last_status);
5497 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5499 /* get statistics index */
5500 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5501 &veb->stats_idx, NULL, NULL, NULL);
5502 if (ret != I40E_SUCCESS) {
5503 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5504 hw->aq.asq_last_status);
5507 /* Get VEB bandwidth, to be implemented */
5508 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5510 vsi->uplink_seid = veb->seid;
5519 i40e_vsi_release(struct i40e_vsi *vsi)
5523 struct i40e_vsi_list *vsi_list;
5526 struct i40e_mac_filter *f;
5527 uint16_t user_param;
5530 return I40E_SUCCESS;
5535 user_param = vsi->user_param;
5537 pf = I40E_VSI_TO_PF(vsi);
5538 hw = I40E_VSI_TO_HW(vsi);
5540 /* VSI has child to attach, release child first */
5542 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5543 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5546 i40e_veb_release(vsi->veb);
5549 if (vsi->floating_veb) {
5550 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5551 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5556 /* Remove all macvlan filters of the VSI */
5557 i40e_vsi_remove_all_macvlan_filter(vsi);
5558 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5561 if (vsi->type != I40E_VSI_MAIN &&
5562 ((vsi->type != I40E_VSI_SRIOV) ||
5563 !pf->floating_veb_list[user_param])) {
5564 /* Remove vsi from parent's sibling list */
5565 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5566 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5567 return I40E_ERR_PARAM;
5569 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5570 &vsi->sib_vsi_list, list);
5572 /* Remove all switch element of the VSI */
5573 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5574 if (ret != I40E_SUCCESS)
5575 PMD_DRV_LOG(ERR, "Failed to delete element");
5578 if ((vsi->type == I40E_VSI_SRIOV) &&
5579 pf->floating_veb_list[user_param]) {
5580 /* Remove vsi from parent's sibling list */
5581 if (vsi->parent_vsi == NULL ||
5582 vsi->parent_vsi->floating_veb == NULL) {
5583 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5584 return I40E_ERR_PARAM;
5586 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5587 &vsi->sib_vsi_list, list);
5589 /* Remove all switch element of the VSI */
5590 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5591 if (ret != I40E_SUCCESS)
5592 PMD_DRV_LOG(ERR, "Failed to delete element");
5595 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5597 if (vsi->type != I40E_VSI_SRIOV)
5598 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5601 return I40E_SUCCESS;
5605 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5607 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5608 struct i40e_aqc_remove_macvlan_element_data def_filter;
5609 struct i40e_mac_filter_info filter;
5612 if (vsi->type != I40E_VSI_MAIN)
5613 return I40E_ERR_CONFIG;
5614 memset(&def_filter, 0, sizeof(def_filter));
5615 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5617 def_filter.vlan_tag = 0;
5618 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5619 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5620 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5621 if (ret != I40E_SUCCESS) {
5622 struct i40e_mac_filter *f;
5623 struct rte_ether_addr *mac;
5626 "Cannot remove the default macvlan filter");
5627 /* It needs to add the permanent mac into mac list */
5628 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5630 PMD_DRV_LOG(ERR, "failed to allocate memory");
5631 return I40E_ERR_NO_MEMORY;
5633 mac = &f->mac_info.mac_addr;
5634 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5636 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5637 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5642 rte_memcpy(&filter.mac_addr,
5643 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5644 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5645 return i40e_vsi_add_mac(vsi, &filter);
5649 * i40e_vsi_get_bw_config - Query VSI BW Information
5650 * @vsi: the VSI to be queried
5652 * Returns 0 on success, negative value on failure
5654 static enum i40e_status_code
5655 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5657 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5658 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5659 struct i40e_hw *hw = &vsi->adapter->hw;
5664 memset(&bw_config, 0, sizeof(bw_config));
5665 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5666 if (ret != I40E_SUCCESS) {
5667 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5668 hw->aq.asq_last_status);
5672 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5673 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5674 &ets_sla_config, NULL);
5675 if (ret != I40E_SUCCESS) {
5677 "VSI failed to get TC bandwdith configuration %u",
5678 hw->aq.asq_last_status);
5682 /* store and print out BW info */
5683 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5684 vsi->bw_info.bw_max = bw_config.max_bw;
5685 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5686 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5687 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5688 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5690 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5691 vsi->bw_info.bw_ets_share_credits[i] =
5692 ets_sla_config.share_credits[i];
5693 vsi->bw_info.bw_ets_credits[i] =
5694 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5695 /* 4 bits per TC, 4th bit is reserved */
5696 vsi->bw_info.bw_ets_max[i] =
5697 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5698 RTE_LEN2MASK(3, uint8_t));
5699 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5700 vsi->bw_info.bw_ets_share_credits[i]);
5701 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5702 vsi->bw_info.bw_ets_credits[i]);
5703 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5704 vsi->bw_info.bw_ets_max[i]);
5707 return I40E_SUCCESS;
5710 /* i40e_enable_pf_lb
5711 * @pf: pointer to the pf structure
5713 * allow loopback on pf
5716 i40e_enable_pf_lb(struct i40e_pf *pf)
5718 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5719 struct i40e_vsi_context ctxt;
5722 /* Use the FW API if FW >= v5.0 */
5723 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5724 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5728 memset(&ctxt, 0, sizeof(ctxt));
5729 ctxt.seid = pf->main_vsi_seid;
5730 ctxt.pf_num = hw->pf_id;
5731 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5733 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5734 ret, hw->aq.asq_last_status);
5737 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5738 ctxt.info.valid_sections =
5739 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5740 ctxt.info.switch_id |=
5741 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5743 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5745 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5746 hw->aq.asq_last_status);
5751 i40e_vsi_setup(struct i40e_pf *pf,
5752 enum i40e_vsi_type type,
5753 struct i40e_vsi *uplink_vsi,
5754 uint16_t user_param)
5756 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5757 struct i40e_vsi *vsi;
5758 struct i40e_mac_filter_info filter;
5760 struct i40e_vsi_context ctxt;
5761 struct rte_ether_addr broadcast =
5762 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5764 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5765 uplink_vsi == NULL) {
5767 "VSI setup failed, VSI link shouldn't be NULL");
5771 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5773 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5778 * 1.type is not MAIN and uplink vsi is not NULL
5779 * If uplink vsi didn't setup VEB, create one first under veb field
5780 * 2.type is SRIOV and the uplink is NULL
5781 * If floating VEB is NULL, create one veb under floating veb field
5784 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5785 uplink_vsi->veb == NULL) {
5786 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5788 if (uplink_vsi->veb == NULL) {
5789 PMD_DRV_LOG(ERR, "VEB setup failed");
5792 /* set ALLOWLOOPBACk on pf, when veb is created */
5793 i40e_enable_pf_lb(pf);
5796 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5797 pf->main_vsi->floating_veb == NULL) {
5798 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5800 if (pf->main_vsi->floating_veb == NULL) {
5801 PMD_DRV_LOG(ERR, "VEB setup failed");
5806 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5808 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5811 TAILQ_INIT(&vsi->mac_list);
5813 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5814 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5815 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5816 vsi->user_param = user_param;
5817 vsi->vlan_anti_spoof_on = 0;
5818 vsi->vlan_filter_on = 0;
5819 /* Allocate queues */
5820 switch (vsi->type) {
5821 case I40E_VSI_MAIN :
5822 vsi->nb_qps = pf->lan_nb_qps;
5824 case I40E_VSI_SRIOV :
5825 vsi->nb_qps = pf->vf_nb_qps;
5827 case I40E_VSI_VMDQ2:
5828 vsi->nb_qps = pf->vmdq_nb_qps;
5831 vsi->nb_qps = pf->fdir_nb_qps;
5837 * The filter status descriptor is reported in rx queue 0,
5838 * while the tx queue for fdir filter programming has no
5839 * such constraints, can be non-zero queues.
5840 * To simplify it, choose FDIR vsi use queue 0 pair.
5841 * To make sure it will use queue 0 pair, queue allocation
5842 * need be done before this function is called
5844 if (type != I40E_VSI_FDIR) {
5845 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5847 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5851 vsi->base_queue = ret;
5853 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5855 /* VF has MSIX interrupt in VF range, don't allocate here */
5856 if (type == I40E_VSI_MAIN) {
5857 if (pf->support_multi_driver) {
5858 /* If support multi-driver, need to use INT0 instead of
5859 * allocating from msix pool. The Msix pool is init from
5860 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5861 * to 1 without calling i40e_res_pool_alloc.
5866 ret = i40e_res_pool_alloc(&pf->msix_pool,
5867 RTE_MIN(vsi->nb_qps,
5868 RTE_MAX_RXTX_INTR_VEC_ID));
5871 "VSI MAIN %d get heap failed %d",
5873 goto fail_queue_alloc;
5875 vsi->msix_intr = ret;
5876 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5877 RTE_MAX_RXTX_INTR_VEC_ID);
5879 } else if (type != I40E_VSI_SRIOV) {
5880 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5882 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5883 if (type != I40E_VSI_FDIR)
5884 goto fail_queue_alloc;
5888 vsi->msix_intr = ret;
5897 if (type == I40E_VSI_MAIN) {
5898 /* For main VSI, no need to add since it's default one */
5899 vsi->uplink_seid = pf->mac_seid;
5900 vsi->seid = pf->main_vsi_seid;
5901 /* Bind queues with specific MSIX interrupt */
5903 * Needs 2 interrupt at least, one for misc cause which will
5904 * enabled from OS side, Another for queues binding the
5905 * interrupt from device side only.
5908 /* Get default VSI parameters from hardware */
5909 memset(&ctxt, 0, sizeof(ctxt));
5910 ctxt.seid = vsi->seid;
5911 ctxt.pf_num = hw->pf_id;
5912 ctxt.uplink_seid = vsi->uplink_seid;
5914 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5915 if (ret != I40E_SUCCESS) {
5916 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5917 goto fail_msix_alloc;
5919 rte_memcpy(&vsi->info, &ctxt.info,
5920 sizeof(struct i40e_aqc_vsi_properties_data));
5921 vsi->vsi_id = ctxt.vsi_number;
5922 vsi->info.valid_sections = 0;
5924 /* Configure tc, enabled TC0 only */
5925 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5927 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5928 goto fail_msix_alloc;
5931 /* TC, queue mapping */
5932 memset(&ctxt, 0, sizeof(ctxt));
5933 vsi->info.valid_sections |=
5934 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5935 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5936 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5937 rte_memcpy(&ctxt.info, &vsi->info,
5938 sizeof(struct i40e_aqc_vsi_properties_data));
5939 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5940 I40E_DEFAULT_TCMAP);
5941 if (ret != I40E_SUCCESS) {
5943 "Failed to configure TC queue mapping");
5944 goto fail_msix_alloc;
5946 ctxt.seid = vsi->seid;
5947 ctxt.pf_num = hw->pf_id;
5948 ctxt.uplink_seid = vsi->uplink_seid;
5951 /* Update VSI parameters */
5952 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5953 if (ret != I40E_SUCCESS) {
5954 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5955 goto fail_msix_alloc;
5958 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5959 sizeof(vsi->info.tc_mapping));
5960 rte_memcpy(&vsi->info.queue_mapping,
5961 &ctxt.info.queue_mapping,
5962 sizeof(vsi->info.queue_mapping));
5963 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5964 vsi->info.valid_sections = 0;
5966 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5970 * Updating default filter settings are necessary to prevent
5971 * reception of tagged packets.
5972 * Some old firmware configurations load a default macvlan
5973 * filter which accepts both tagged and untagged packets.
5974 * The updating is to use a normal filter instead if needed.
5975 * For NVM 4.2.2 or after, the updating is not needed anymore.
5976 * The firmware with correct configurations load the default
5977 * macvlan filter which is expected and cannot be removed.
5979 i40e_update_default_filter_setting(vsi);
5980 i40e_config_qinq(hw, vsi);
5981 } else if (type == I40E_VSI_SRIOV) {
5982 memset(&ctxt, 0, sizeof(ctxt));
5984 * For other VSI, the uplink_seid equals to uplink VSI's
5985 * uplink_seid since they share same VEB
5987 if (uplink_vsi == NULL)
5988 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5990 vsi->uplink_seid = uplink_vsi->uplink_seid;
5991 ctxt.pf_num = hw->pf_id;
5992 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5993 ctxt.uplink_seid = vsi->uplink_seid;
5994 ctxt.connection_type = 0x1;
5995 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5997 /* Use the VEB configuration if FW >= v5.0 */
5998 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5999 /* Configure switch ID */
6000 ctxt.info.valid_sections |=
6001 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6002 ctxt.info.switch_id =
6003 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6006 /* Configure port/vlan */
6007 ctxt.info.valid_sections |=
6008 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6009 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6010 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6011 hw->func_caps.enabled_tcmap);
6012 if (ret != I40E_SUCCESS) {
6014 "Failed to configure TC queue mapping");
6015 goto fail_msix_alloc;
6018 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
6019 ctxt.info.valid_sections |=
6020 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6022 * Since VSI is not created yet, only configure parameter,
6023 * will add vsi below.
6026 i40e_config_qinq(hw, vsi);
6027 } else if (type == I40E_VSI_VMDQ2) {
6028 memset(&ctxt, 0, sizeof(ctxt));
6030 * For other VSI, the uplink_seid equals to uplink VSI's
6031 * uplink_seid since they share same VEB
6033 vsi->uplink_seid = uplink_vsi->uplink_seid;
6034 ctxt.pf_num = hw->pf_id;
6036 ctxt.uplink_seid = vsi->uplink_seid;
6037 ctxt.connection_type = 0x1;
6038 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6040 ctxt.info.valid_sections |=
6041 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6042 /* user_param carries flag to enable loop back */
6044 ctxt.info.switch_id =
6045 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6046 ctxt.info.switch_id |=
6047 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6050 /* Configure port/vlan */
6051 ctxt.info.valid_sections |=
6052 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6053 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6054 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6055 I40E_DEFAULT_TCMAP);
6056 if (ret != I40E_SUCCESS) {
6058 "Failed to configure TC queue mapping");
6059 goto fail_msix_alloc;
6061 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6062 ctxt.info.valid_sections |=
6063 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6064 } else if (type == I40E_VSI_FDIR) {
6065 memset(&ctxt, 0, sizeof(ctxt));
6066 vsi->uplink_seid = uplink_vsi->uplink_seid;
6067 ctxt.pf_num = hw->pf_id;
6069 ctxt.uplink_seid = vsi->uplink_seid;
6070 ctxt.connection_type = 0x1; /* regular data port */
6071 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6072 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6073 I40E_DEFAULT_TCMAP);
6074 if (ret != I40E_SUCCESS) {
6076 "Failed to configure TC queue mapping.");
6077 goto fail_msix_alloc;
6079 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6080 ctxt.info.valid_sections |=
6081 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6083 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6084 goto fail_msix_alloc;
6087 if (vsi->type != I40E_VSI_MAIN) {
6088 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6089 if (ret != I40E_SUCCESS) {
6090 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6091 hw->aq.asq_last_status);
6092 goto fail_msix_alloc;
6094 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6095 vsi->info.valid_sections = 0;
6096 vsi->seid = ctxt.seid;
6097 vsi->vsi_id = ctxt.vsi_number;
6098 vsi->sib_vsi_list.vsi = vsi;
6099 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6100 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6101 &vsi->sib_vsi_list, list);
6103 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6104 &vsi->sib_vsi_list, list);
6108 /* MAC/VLAN configuration */
6109 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6110 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6112 ret = i40e_vsi_add_mac(vsi, &filter);
6113 if (ret != I40E_SUCCESS) {
6114 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6115 goto fail_msix_alloc;
6118 /* Get VSI BW information */
6119 i40e_vsi_get_bw_config(vsi);
6122 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6124 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6130 /* Configure vlan filter on or off */
6132 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6135 struct i40e_mac_filter *f;
6137 struct i40e_mac_filter_info *mac_filter;
6138 enum rte_mac_filter_type desired_filter;
6139 int ret = I40E_SUCCESS;
6142 /* Filter to match MAC and VLAN */
6143 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6145 /* Filter to match only MAC */
6146 desired_filter = RTE_MAC_PERFECT_MATCH;
6151 mac_filter = rte_zmalloc("mac_filter_info_data",
6152 num * sizeof(*mac_filter), 0);
6153 if (mac_filter == NULL) {
6154 PMD_DRV_LOG(ERR, "failed to allocate memory");
6155 return I40E_ERR_NO_MEMORY;
6160 /* Remove all existing mac */
6161 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6162 mac_filter[i] = f->mac_info;
6163 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6165 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6166 on ? "enable" : "disable");
6172 /* Override with new filter */
6173 for (i = 0; i < num; i++) {
6174 mac_filter[i].filter_type = desired_filter;
6175 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6177 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6178 on ? "enable" : "disable");
6184 rte_free(mac_filter);
6188 /* Configure vlan stripping on or off */
6190 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6192 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6193 struct i40e_vsi_context ctxt;
6195 int ret = I40E_SUCCESS;
6197 /* Check if it has been already on or off */
6198 if (vsi->info.valid_sections &
6199 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6201 if ((vsi->info.port_vlan_flags &
6202 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6203 return 0; /* already on */
6205 if ((vsi->info.port_vlan_flags &
6206 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6207 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6208 return 0; /* already off */
6213 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6215 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6216 vsi->info.valid_sections =
6217 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6218 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6219 vsi->info.port_vlan_flags |= vlan_flags;
6220 ctxt.seid = vsi->seid;
6221 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6222 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6224 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6225 on ? "enable" : "disable");
6231 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6233 struct rte_eth_dev_data *data = dev->data;
6237 /* Apply vlan offload setting */
6238 mask = ETH_VLAN_STRIP_MASK |
6239 ETH_QINQ_STRIP_MASK |
6240 ETH_VLAN_FILTER_MASK |
6241 ETH_VLAN_EXTEND_MASK;
6242 ret = i40e_vlan_offload_set(dev, mask);
6244 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6248 /* Apply pvid setting */
6249 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6250 data->dev_conf.txmode.hw_vlan_insert_pvid);
6252 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6258 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6260 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6262 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6266 i40e_update_flow_control(struct i40e_hw *hw)
6268 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6269 struct i40e_link_status link_status;
6270 uint32_t rxfc = 0, txfc = 0, reg;
6274 memset(&link_status, 0, sizeof(link_status));
6275 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6276 if (ret != I40E_SUCCESS) {
6277 PMD_DRV_LOG(ERR, "Failed to get link status information");
6278 goto write_reg; /* Disable flow control */
6281 an_info = hw->phy.link_info.an_info;
6282 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6283 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6284 ret = I40E_ERR_NOT_READY;
6285 goto write_reg; /* Disable flow control */
6288 * If link auto negotiation is enabled, flow control needs to
6289 * be configured according to it
6291 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6292 case I40E_LINK_PAUSE_RXTX:
6295 hw->fc.current_mode = I40E_FC_FULL;
6297 case I40E_AQ_LINK_PAUSE_RX:
6299 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6301 case I40E_AQ_LINK_PAUSE_TX:
6303 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6306 hw->fc.current_mode = I40E_FC_NONE;
6311 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6312 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6313 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6314 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6315 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6316 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6323 i40e_pf_setup(struct i40e_pf *pf)
6325 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6326 struct i40e_filter_control_settings settings;
6327 struct i40e_vsi *vsi;
6330 /* Clear all stats counters */
6331 pf->offset_loaded = FALSE;
6332 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6333 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6334 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6335 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6337 ret = i40e_pf_get_switch_config(pf);
6338 if (ret != I40E_SUCCESS) {
6339 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6343 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6345 PMD_INIT_LOG(WARNING,
6346 "failed to allocate switch domain for device %d", ret);
6348 if (pf->flags & I40E_FLAG_FDIR) {
6349 /* make queue allocated first, let FDIR use queue pair 0*/
6350 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6351 if (ret != I40E_FDIR_QUEUE_ID) {
6353 "queue allocation fails for FDIR: ret =%d",
6355 pf->flags &= ~I40E_FLAG_FDIR;
6358 /* main VSI setup */
6359 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6361 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6362 return I40E_ERR_NOT_READY;
6366 /* Configure filter control */
6367 memset(&settings, 0, sizeof(settings));
6368 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6369 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6370 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6371 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6373 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6374 hw->func_caps.rss_table_size);
6375 return I40E_ERR_PARAM;
6377 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6378 hw->func_caps.rss_table_size);
6379 pf->hash_lut_size = hw->func_caps.rss_table_size;
6381 /* Enable ethtype and macvlan filters */
6382 settings.enable_ethtype = TRUE;
6383 settings.enable_macvlan = TRUE;
6384 ret = i40e_set_filter_control(hw, &settings);
6386 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6389 /* Update flow control according to the auto negotiation */
6390 i40e_update_flow_control(hw);
6392 return I40E_SUCCESS;
6396 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6402 * Set or clear TX Queue Disable flags,
6403 * which is required by hardware.
6405 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6406 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6408 /* Wait until the request is finished */
6409 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6410 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6411 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6412 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6413 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6419 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6420 return I40E_SUCCESS; /* already on, skip next steps */
6422 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6423 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6425 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6426 return I40E_SUCCESS; /* already off, skip next steps */
6427 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6429 /* Write the register */
6430 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6431 /* Check the result */
6432 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6433 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6434 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6436 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6437 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6440 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6441 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6445 /* Check if it is timeout */
6446 if (j >= I40E_CHK_Q_ENA_COUNT) {
6447 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6448 (on ? "enable" : "disable"), q_idx);
6449 return I40E_ERR_TIMEOUT;
6452 return I40E_SUCCESS;
6456 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6461 /* Wait until the request is finished */
6462 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6463 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6464 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6465 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6466 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6471 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6472 return I40E_SUCCESS; /* Already on, skip next steps */
6473 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6475 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6476 return I40E_SUCCESS; /* Already off, skip next steps */
6477 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6480 /* Write the register */
6481 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6482 /* Check the result */
6483 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6484 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6485 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6487 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6488 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6491 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6492 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6497 /* Check if it is timeout */
6498 if (j >= I40E_CHK_Q_ENA_COUNT) {
6499 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6500 (on ? "enable" : "disable"), q_idx);
6501 return I40E_ERR_TIMEOUT;
6504 return I40E_SUCCESS;
6507 /* Initialize VSI for TX */
6509 i40e_dev_tx_init(struct i40e_pf *pf)
6511 struct rte_eth_dev_data *data = pf->dev_data;
6513 uint32_t ret = I40E_SUCCESS;
6514 struct i40e_tx_queue *txq;
6516 for (i = 0; i < data->nb_tx_queues; i++) {
6517 txq = data->tx_queues[i];
6518 if (!txq || !txq->q_set)
6520 ret = i40e_tx_queue_init(txq);
6521 if (ret != I40E_SUCCESS)
6524 if (ret == I40E_SUCCESS)
6525 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6531 /* Initialize VSI for RX */
6533 i40e_dev_rx_init(struct i40e_pf *pf)
6535 struct rte_eth_dev_data *data = pf->dev_data;
6536 int ret = I40E_SUCCESS;
6538 struct i40e_rx_queue *rxq;
6540 i40e_pf_config_rss(pf);
6541 for (i = 0; i < data->nb_rx_queues; i++) {
6542 rxq = data->rx_queues[i];
6543 if (!rxq || !rxq->q_set)
6546 ret = i40e_rx_queue_init(rxq);
6547 if (ret != I40E_SUCCESS) {
6549 "Failed to do RX queue initialization");
6553 if (ret == I40E_SUCCESS)
6554 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6561 i40e_dev_rxtx_init(struct i40e_pf *pf)
6565 err = i40e_dev_tx_init(pf);
6567 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6570 err = i40e_dev_rx_init(pf);
6572 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6580 i40e_vmdq_setup(struct rte_eth_dev *dev)
6582 struct rte_eth_conf *conf = &dev->data->dev_conf;
6583 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6584 int i, err, conf_vsis, j, loop;
6585 struct i40e_vsi *vsi;
6586 struct i40e_vmdq_info *vmdq_info;
6587 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6588 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6591 * Disable interrupt to avoid message from VF. Furthermore, it will
6592 * avoid race condition in VSI creation/destroy.
6594 i40e_pf_disable_irq0(hw);
6596 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6597 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6601 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6602 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6603 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6604 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6605 pf->max_nb_vmdq_vsi);
6609 if (pf->vmdq != NULL) {
6610 PMD_INIT_LOG(INFO, "VMDQ already configured");
6614 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6615 sizeof(*vmdq_info) * conf_vsis, 0);
6617 if (pf->vmdq == NULL) {
6618 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6622 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6624 /* Create VMDQ VSI */
6625 for (i = 0; i < conf_vsis; i++) {
6626 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6627 vmdq_conf->enable_loop_back);
6629 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6633 vmdq_info = &pf->vmdq[i];
6635 vmdq_info->vsi = vsi;
6637 pf->nb_cfg_vmdq_vsi = conf_vsis;
6639 /* Configure Vlan */
6640 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6641 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6642 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6643 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6644 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6645 vmdq_conf->pool_map[i].vlan_id, j);
6647 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6648 vmdq_conf->pool_map[i].vlan_id);
6650 PMD_INIT_LOG(ERR, "Failed to add vlan");
6658 i40e_pf_enable_irq0(hw);
6663 for (i = 0; i < conf_vsis; i++)
6664 if (pf->vmdq[i].vsi == NULL)
6667 i40e_vsi_release(pf->vmdq[i].vsi);
6671 i40e_pf_enable_irq0(hw);
6676 i40e_stat_update_32(struct i40e_hw *hw,
6684 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6688 if (new_data >= *offset)
6689 *stat = (uint64_t)(new_data - *offset);
6691 *stat = (uint64_t)((new_data +
6692 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6696 i40e_stat_update_48(struct i40e_hw *hw,
6705 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6706 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6707 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6712 if (new_data >= *offset)
6713 *stat = new_data - *offset;
6715 *stat = (uint64_t)((new_data +
6716 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6718 *stat &= I40E_48_BIT_MASK;
6723 i40e_pf_disable_irq0(struct i40e_hw *hw)
6725 /* Disable all interrupt types */
6726 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6727 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6728 I40E_WRITE_FLUSH(hw);
6733 i40e_pf_enable_irq0(struct i40e_hw *hw)
6735 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6736 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6737 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6738 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6739 I40E_WRITE_FLUSH(hw);
6743 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6745 /* read pending request and disable first */
6746 i40e_pf_disable_irq0(hw);
6747 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6748 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6749 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6752 /* Link no queues with irq0 */
6753 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6754 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6758 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6764 uint32_t index, offset, val;
6769 * Try to find which VF trigger a reset, use absolute VF id to access
6770 * since the reg is global register.
6772 for (i = 0; i < pf->vf_num; i++) {
6773 abs_vf_id = hw->func_caps.vf_base_id + i;
6774 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6775 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6776 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6777 /* VFR event occurred */
6778 if (val & (0x1 << offset)) {
6781 /* Clear the event first */
6782 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6784 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6786 * Only notify a VF reset event occurred,
6787 * don't trigger another SW reset
6789 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6790 if (ret != I40E_SUCCESS)
6791 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6797 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6799 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6802 for (i = 0; i < pf->vf_num; i++)
6803 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6807 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6809 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6810 struct i40e_arq_event_info info;
6811 uint16_t pending, opcode;
6814 info.buf_len = I40E_AQ_BUF_SZ;
6815 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6816 if (!info.msg_buf) {
6817 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6823 ret = i40e_clean_arq_element(hw, &info, &pending);
6825 if (ret != I40E_SUCCESS) {
6827 "Failed to read msg from AdminQ, aq_err: %u",
6828 hw->aq.asq_last_status);
6831 opcode = rte_le_to_cpu_16(info.desc.opcode);
6834 case i40e_aqc_opc_send_msg_to_pf:
6835 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6836 i40e_pf_host_handle_vf_msg(dev,
6837 rte_le_to_cpu_16(info.desc.retval),
6838 rte_le_to_cpu_32(info.desc.cookie_high),
6839 rte_le_to_cpu_32(info.desc.cookie_low),
6843 case i40e_aqc_opc_get_link_status:
6844 ret = i40e_dev_link_update(dev, 0);
6846 _rte_eth_dev_callback_process(dev,
6847 RTE_ETH_EVENT_INTR_LSC, NULL);
6850 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6855 rte_free(info.msg_buf);
6859 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6861 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6862 #define I40E_MDD_CLEAR16 0xFFFF
6863 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6864 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6865 bool mdd_detected = false;
6866 struct i40e_pf_vf *vf;
6870 /* find what triggered the MDD event */
6871 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6872 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6873 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6874 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6875 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6876 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6877 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6878 I40E_GL_MDET_TX_EVENT_SHIFT;
6879 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6880 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6881 hw->func_caps.base_queue;
6882 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6883 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6884 event, queue, pf_num, vf_num, dev->data->name);
6885 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6886 mdd_detected = true;
6888 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6889 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6890 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6891 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6892 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6893 I40E_GL_MDET_RX_EVENT_SHIFT;
6894 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6895 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6896 hw->func_caps.base_queue;
6898 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6899 "queue %d of function 0x%02x device %s\n",
6900 event, queue, func, dev->data->name);
6901 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6902 mdd_detected = true;
6906 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6907 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6908 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6909 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6911 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6912 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6913 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6915 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6919 /* see if one of the VFs needs its hand slapped */
6920 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6922 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6923 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6924 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6926 vf->num_mdd_events++;
6927 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6929 i, vf->num_mdd_events);
6932 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6933 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6934 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6936 vf->num_mdd_events++;
6937 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6939 i, vf->num_mdd_events);
6945 * Interrupt handler triggered by NIC for handling
6946 * specific interrupt.
6949 * Pointer to interrupt handle.
6951 * The address of parameter (struct rte_eth_dev *) regsitered before.
6957 i40e_dev_interrupt_handler(void *param)
6959 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6963 /* Disable interrupt */
6964 i40e_pf_disable_irq0(hw);
6966 /* read out interrupt causes */
6967 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6969 /* No interrupt event indicated */
6970 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6971 PMD_DRV_LOG(INFO, "No interrupt event");
6974 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6975 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6976 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6977 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6978 i40e_handle_mdd_event(dev);
6980 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6981 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6982 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6983 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6984 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6985 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6986 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6987 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6988 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6989 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6991 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6992 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6993 i40e_dev_handle_vfr_event(dev);
6995 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6996 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6997 i40e_dev_handle_aq_msg(dev);
7001 /* Enable interrupt */
7002 i40e_pf_enable_irq0(hw);
7006 i40e_dev_alarm_handler(void *param)
7008 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7012 /* Disable interrupt */
7013 i40e_pf_disable_irq0(hw);
7015 /* read out interrupt causes */
7016 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
7018 /* No interrupt event indicated */
7019 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
7021 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
7022 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
7023 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
7024 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
7025 i40e_handle_mdd_event(dev);
7027 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7028 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7029 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7030 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7031 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7032 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7033 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7034 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7035 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7036 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7038 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7039 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7040 i40e_dev_handle_vfr_event(dev);
7042 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7043 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7044 i40e_dev_handle_aq_msg(dev);
7048 /* Enable interrupt */
7049 i40e_pf_enable_irq0(hw);
7050 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7051 i40e_dev_alarm_handler, dev);
7055 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7056 struct i40e_macvlan_filter *filter,
7059 int ele_num, ele_buff_size;
7060 int num, actual_num, i;
7062 int ret = I40E_SUCCESS;
7063 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7064 struct i40e_aqc_add_macvlan_element_data *req_list;
7066 if (filter == NULL || total == 0)
7067 return I40E_ERR_PARAM;
7068 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7069 ele_buff_size = hw->aq.asq_buf_size;
7071 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7072 if (req_list == NULL) {
7073 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7074 return I40E_ERR_NO_MEMORY;
7079 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7080 memset(req_list, 0, ele_buff_size);
7082 for (i = 0; i < actual_num; i++) {
7083 rte_memcpy(req_list[i].mac_addr,
7084 &filter[num + i].macaddr, ETH_ADDR_LEN);
7085 req_list[i].vlan_tag =
7086 rte_cpu_to_le_16(filter[num + i].vlan_id);
7088 switch (filter[num + i].filter_type) {
7089 case RTE_MAC_PERFECT_MATCH:
7090 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7091 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7093 case RTE_MACVLAN_PERFECT_MATCH:
7094 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7096 case RTE_MAC_HASH_MATCH:
7097 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7098 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7100 case RTE_MACVLAN_HASH_MATCH:
7101 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7104 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7105 ret = I40E_ERR_PARAM;
7109 req_list[i].queue_number = 0;
7111 req_list[i].flags = rte_cpu_to_le_16(flags);
7114 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7116 if (ret != I40E_SUCCESS) {
7117 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7121 } while (num < total);
7129 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7130 struct i40e_macvlan_filter *filter,
7133 int ele_num, ele_buff_size;
7134 int num, actual_num, i;
7136 int ret = I40E_SUCCESS;
7137 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7138 struct i40e_aqc_remove_macvlan_element_data *req_list;
7140 if (filter == NULL || total == 0)
7141 return I40E_ERR_PARAM;
7143 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7144 ele_buff_size = hw->aq.asq_buf_size;
7146 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7147 if (req_list == NULL) {
7148 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7149 return I40E_ERR_NO_MEMORY;
7154 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7155 memset(req_list, 0, ele_buff_size);
7157 for (i = 0; i < actual_num; i++) {
7158 rte_memcpy(req_list[i].mac_addr,
7159 &filter[num + i].macaddr, ETH_ADDR_LEN);
7160 req_list[i].vlan_tag =
7161 rte_cpu_to_le_16(filter[num + i].vlan_id);
7163 switch (filter[num + i].filter_type) {
7164 case RTE_MAC_PERFECT_MATCH:
7165 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7166 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7168 case RTE_MACVLAN_PERFECT_MATCH:
7169 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7171 case RTE_MAC_HASH_MATCH:
7172 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7173 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7175 case RTE_MACVLAN_HASH_MATCH:
7176 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7179 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7180 ret = I40E_ERR_PARAM;
7183 req_list[i].flags = rte_cpu_to_le_16(flags);
7186 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7188 if (ret != I40E_SUCCESS) {
7189 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7193 } while (num < total);
7200 /* Find out specific MAC filter */
7201 static struct i40e_mac_filter *
7202 i40e_find_mac_filter(struct i40e_vsi *vsi,
7203 struct rte_ether_addr *macaddr)
7205 struct i40e_mac_filter *f;
7207 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7208 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7216 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7219 uint32_t vid_idx, vid_bit;
7221 if (vlan_id > ETH_VLAN_ID_MAX)
7224 vid_idx = I40E_VFTA_IDX(vlan_id);
7225 vid_bit = I40E_VFTA_BIT(vlan_id);
7227 if (vsi->vfta[vid_idx] & vid_bit)
7234 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7235 uint16_t vlan_id, bool on)
7237 uint32_t vid_idx, vid_bit;
7239 vid_idx = I40E_VFTA_IDX(vlan_id);
7240 vid_bit = I40E_VFTA_BIT(vlan_id);
7243 vsi->vfta[vid_idx] |= vid_bit;
7245 vsi->vfta[vid_idx] &= ~vid_bit;
7249 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7250 uint16_t vlan_id, bool on)
7252 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7253 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7256 if (vlan_id > ETH_VLAN_ID_MAX)
7259 i40e_store_vlan_filter(vsi, vlan_id, on);
7261 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7264 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7267 ret = i40e_aq_add_vlan(hw, vsi->seid,
7268 &vlan_data, 1, NULL);
7269 if (ret != I40E_SUCCESS)
7270 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7272 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7273 &vlan_data, 1, NULL);
7274 if (ret != I40E_SUCCESS)
7276 "Failed to remove vlan filter");
7281 * Find all vlan options for specific mac addr,
7282 * return with actual vlan found.
7285 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7286 struct i40e_macvlan_filter *mv_f,
7287 int num, struct rte_ether_addr *addr)
7293 * Not to use i40e_find_vlan_filter to decrease the loop time,
7294 * although the code looks complex.
7296 if (num < vsi->vlan_num)
7297 return I40E_ERR_PARAM;
7300 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7302 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7303 if (vsi->vfta[j] & (1 << k)) {
7306 "vlan number doesn't match");
7307 return I40E_ERR_PARAM;
7309 rte_memcpy(&mv_f[i].macaddr,
7310 addr, ETH_ADDR_LEN);
7312 j * I40E_UINT32_BIT_SIZE + k;
7318 return I40E_SUCCESS;
7322 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7323 struct i40e_macvlan_filter *mv_f,
7328 struct i40e_mac_filter *f;
7330 if (num < vsi->mac_num)
7331 return I40E_ERR_PARAM;
7333 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7335 PMD_DRV_LOG(ERR, "buffer number not match");
7336 return I40E_ERR_PARAM;
7338 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7340 mv_f[i].vlan_id = vlan;
7341 mv_f[i].filter_type = f->mac_info.filter_type;
7345 return I40E_SUCCESS;
7349 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7352 struct i40e_mac_filter *f;
7353 struct i40e_macvlan_filter *mv_f;
7354 int ret = I40E_SUCCESS;
7356 if (vsi == NULL || vsi->mac_num == 0)
7357 return I40E_ERR_PARAM;
7359 /* Case that no vlan is set */
7360 if (vsi->vlan_num == 0)
7363 num = vsi->mac_num * vsi->vlan_num;
7365 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7367 PMD_DRV_LOG(ERR, "failed to allocate memory");
7368 return I40E_ERR_NO_MEMORY;
7372 if (vsi->vlan_num == 0) {
7373 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7374 rte_memcpy(&mv_f[i].macaddr,
7375 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7376 mv_f[i].filter_type = f->mac_info.filter_type;
7377 mv_f[i].vlan_id = 0;
7381 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7382 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7383 vsi->vlan_num, &f->mac_info.mac_addr);
7384 if (ret != I40E_SUCCESS)
7386 for (j = i; j < i + vsi->vlan_num; j++)
7387 mv_f[j].filter_type = f->mac_info.filter_type;
7392 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7400 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7402 struct i40e_macvlan_filter *mv_f;
7404 int ret = I40E_SUCCESS;
7406 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7407 return I40E_ERR_PARAM;
7409 /* If it's already set, just return */
7410 if (i40e_find_vlan_filter(vsi,vlan))
7411 return I40E_SUCCESS;
7413 mac_num = vsi->mac_num;
7416 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7417 return I40E_ERR_PARAM;
7420 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7423 PMD_DRV_LOG(ERR, "failed to allocate memory");
7424 return I40E_ERR_NO_MEMORY;
7427 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7429 if (ret != I40E_SUCCESS)
7432 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7434 if (ret != I40E_SUCCESS)
7437 i40e_set_vlan_filter(vsi, vlan, 1);
7447 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7449 struct i40e_macvlan_filter *mv_f;
7451 int ret = I40E_SUCCESS;
7454 * Vlan 0 is the generic filter for untagged packets
7455 * and can't be removed.
7457 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7458 return I40E_ERR_PARAM;
7460 /* If can't find it, just return */
7461 if (!i40e_find_vlan_filter(vsi, vlan))
7462 return I40E_ERR_PARAM;
7464 mac_num = vsi->mac_num;
7467 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7468 return I40E_ERR_PARAM;
7471 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7474 PMD_DRV_LOG(ERR, "failed to allocate memory");
7475 return I40E_ERR_NO_MEMORY;
7478 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7480 if (ret != I40E_SUCCESS)
7483 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7485 if (ret != I40E_SUCCESS)
7488 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7489 if (vsi->vlan_num == 1) {
7490 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7491 if (ret != I40E_SUCCESS)
7494 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7495 if (ret != I40E_SUCCESS)
7499 i40e_set_vlan_filter(vsi, vlan, 0);
7509 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7511 struct i40e_mac_filter *f;
7512 struct i40e_macvlan_filter *mv_f;
7513 int i, vlan_num = 0;
7514 int ret = I40E_SUCCESS;
7516 /* If it's add and we've config it, return */
7517 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7519 return I40E_SUCCESS;
7520 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7521 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7524 * If vlan_num is 0, that's the first time to add mac,
7525 * set mask for vlan_id 0.
7527 if (vsi->vlan_num == 0) {
7528 i40e_set_vlan_filter(vsi, 0, 1);
7531 vlan_num = vsi->vlan_num;
7532 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7533 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7536 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7538 PMD_DRV_LOG(ERR, "failed to allocate memory");
7539 return I40E_ERR_NO_MEMORY;
7542 for (i = 0; i < vlan_num; i++) {
7543 mv_f[i].filter_type = mac_filter->filter_type;
7544 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7548 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7549 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7550 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7551 &mac_filter->mac_addr);
7552 if (ret != I40E_SUCCESS)
7556 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7557 if (ret != I40E_SUCCESS)
7560 /* Add the mac addr into mac list */
7561 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7563 PMD_DRV_LOG(ERR, "failed to allocate memory");
7564 ret = I40E_ERR_NO_MEMORY;
7567 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7569 f->mac_info.filter_type = mac_filter->filter_type;
7570 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7581 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7583 struct i40e_mac_filter *f;
7584 struct i40e_macvlan_filter *mv_f;
7586 enum rte_mac_filter_type filter_type;
7587 int ret = I40E_SUCCESS;
7589 /* Can't find it, return an error */
7590 f = i40e_find_mac_filter(vsi, addr);
7592 return I40E_ERR_PARAM;
7594 vlan_num = vsi->vlan_num;
7595 filter_type = f->mac_info.filter_type;
7596 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7597 filter_type == RTE_MACVLAN_HASH_MATCH) {
7598 if (vlan_num == 0) {
7599 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7600 return I40E_ERR_PARAM;
7602 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7603 filter_type == RTE_MAC_HASH_MATCH)
7606 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7608 PMD_DRV_LOG(ERR, "failed to allocate memory");
7609 return I40E_ERR_NO_MEMORY;
7612 for (i = 0; i < vlan_num; i++) {
7613 mv_f[i].filter_type = filter_type;
7614 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7617 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7618 filter_type == RTE_MACVLAN_HASH_MATCH) {
7619 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7620 if (ret != I40E_SUCCESS)
7624 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7625 if (ret != I40E_SUCCESS)
7628 /* Remove the mac addr into mac list */
7629 TAILQ_REMOVE(&vsi->mac_list, f, next);
7639 /* Configure hash enable flags for RSS */
7641 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7649 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7650 if (flags & (1ULL << i))
7651 hena |= adapter->pctypes_tbl[i];
7657 /* Parse the hash enable flags */
7659 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7661 uint64_t rss_hf = 0;
7667 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7668 if (flags & adapter->pctypes_tbl[i])
7669 rss_hf |= (1ULL << i);
7676 i40e_pf_disable_rss(struct i40e_pf *pf)
7678 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7680 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7681 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7682 I40E_WRITE_FLUSH(hw);
7686 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7688 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7689 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7690 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7691 I40E_VFQF_HKEY_MAX_INDEX :
7692 I40E_PFQF_HKEY_MAX_INDEX;
7695 if (!key || key_len == 0) {
7696 PMD_DRV_LOG(DEBUG, "No key to be configured");
7698 } else if (key_len != (key_idx + 1) *
7700 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7704 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7705 struct i40e_aqc_get_set_rss_key_data *key_dw =
7706 (struct i40e_aqc_get_set_rss_key_data *)key;
7708 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7710 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7712 uint32_t *hash_key = (uint32_t *)key;
7715 if (vsi->type == I40E_VSI_SRIOV) {
7716 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7719 I40E_VFQF_HKEY1(i, vsi->user_param),
7723 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7724 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7727 I40E_WRITE_FLUSH(hw);
7734 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7736 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7737 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7741 if (!key || !key_len)
7744 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7745 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7746 (struct i40e_aqc_get_set_rss_key_data *)key);
7748 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7752 uint32_t *key_dw = (uint32_t *)key;
7755 if (vsi->type == I40E_VSI_SRIOV) {
7756 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7757 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7758 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7760 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7763 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7764 reg = I40E_PFQF_HKEY(i);
7765 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7767 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7775 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7781 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7782 rss_conf->rss_key_len);
7786 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7787 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7788 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7789 I40E_WRITE_FLUSH(hw);
7795 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7796 struct rte_eth_rss_conf *rss_conf)
7798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7800 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7803 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7804 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7806 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7807 if (rss_hf != 0) /* Enable RSS */
7809 return 0; /* Nothing to do */
7812 if (rss_hf == 0) /* Disable RSS */
7815 return i40e_hw_rss_hash_set(pf, rss_conf);
7819 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7820 struct rte_eth_rss_conf *rss_conf)
7822 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7823 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7830 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7831 &rss_conf->rss_key_len);
7835 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7836 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7837 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7843 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7845 switch (filter_type) {
7846 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7847 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7849 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7850 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7852 case RTE_TUNNEL_FILTER_IMAC_TENID:
7853 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7855 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7856 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7858 case ETH_TUNNEL_FILTER_IMAC:
7859 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7861 case ETH_TUNNEL_FILTER_OIP:
7862 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7864 case ETH_TUNNEL_FILTER_IIP:
7865 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7868 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7875 /* Convert tunnel filter structure */
7877 i40e_tunnel_filter_convert(
7878 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7879 struct i40e_tunnel_filter *tunnel_filter)
7881 rte_ether_addr_copy((struct rte_ether_addr *)
7882 &cld_filter->element.outer_mac,
7883 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7884 rte_ether_addr_copy((struct rte_ether_addr *)
7885 &cld_filter->element.inner_mac,
7886 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7887 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7888 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7889 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7890 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7891 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7893 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7894 tunnel_filter->input.flags = cld_filter->element.flags;
7895 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7896 tunnel_filter->queue = cld_filter->element.queue_number;
7897 rte_memcpy(tunnel_filter->input.general_fields,
7898 cld_filter->general_fields,
7899 sizeof(cld_filter->general_fields));
7904 /* Check if there exists the tunnel filter */
7905 struct i40e_tunnel_filter *
7906 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7907 const struct i40e_tunnel_filter_input *input)
7911 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7915 return tunnel_rule->hash_map[ret];
7918 /* Add a tunnel filter into the SW list */
7920 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7921 struct i40e_tunnel_filter *tunnel_filter)
7923 struct i40e_tunnel_rule *rule = &pf->tunnel;
7926 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7929 "Failed to insert tunnel filter to hash table %d!",
7933 rule->hash_map[ret] = tunnel_filter;
7935 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7940 /* Delete a tunnel filter from the SW list */
7942 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7943 struct i40e_tunnel_filter_input *input)
7945 struct i40e_tunnel_rule *rule = &pf->tunnel;
7946 struct i40e_tunnel_filter *tunnel_filter;
7949 ret = rte_hash_del_key(rule->hash_table, input);
7952 "Failed to delete tunnel filter to hash table %d!",
7956 tunnel_filter = rule->hash_map[ret];
7957 rule->hash_map[ret] = NULL;
7959 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7960 rte_free(tunnel_filter);
7966 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7967 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7971 uint32_t ipv4_addr, ipv4_addr_le;
7972 uint8_t i, tun_type = 0;
7973 /* internal varialbe to convert ipv6 byte order */
7974 uint32_t convert_ipv6[4];
7976 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7977 struct i40e_vsi *vsi = pf->main_vsi;
7978 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7979 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7980 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7981 struct i40e_tunnel_filter *tunnel, *node;
7982 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7984 cld_filter = rte_zmalloc("tunnel_filter",
7985 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7988 if (NULL == cld_filter) {
7989 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7992 pfilter = cld_filter;
7994 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7995 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7996 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7997 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7999 pfilter->element.inner_vlan =
8000 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8001 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
8002 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8003 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8004 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8005 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8007 sizeof(pfilter->element.ipaddr.v4.data));
8009 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8010 for (i = 0; i < 4; i++) {
8012 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
8014 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8016 sizeof(pfilter->element.ipaddr.v6.data));
8019 /* check tunneled type */
8020 switch (tunnel_filter->tunnel_type) {
8021 case RTE_TUNNEL_TYPE_VXLAN:
8022 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8024 case RTE_TUNNEL_TYPE_NVGRE:
8025 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8027 case RTE_TUNNEL_TYPE_IP_IN_GRE:
8028 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8030 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8031 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
8034 /* Other tunnel types is not supported. */
8035 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8036 rte_free(cld_filter);
8040 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8041 &pfilter->element.flags);
8043 rte_free(cld_filter);
8047 pfilter->element.flags |= rte_cpu_to_le_16(
8048 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8049 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8050 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8051 pfilter->element.queue_number =
8052 rte_cpu_to_le_16(tunnel_filter->queue_id);
8054 /* Check if there is the filter in SW list */
8055 memset(&check_filter, 0, sizeof(check_filter));
8056 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8057 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8059 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8060 rte_free(cld_filter);
8064 if (!add && !node) {
8065 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8066 rte_free(cld_filter);
8071 ret = i40e_aq_add_cloud_filters(hw,
8072 vsi->seid, &cld_filter->element, 1);
8074 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8075 rte_free(cld_filter);
8078 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8079 if (tunnel == NULL) {
8080 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8081 rte_free(cld_filter);
8085 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8086 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8090 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8091 &cld_filter->element, 1);
8093 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8094 rte_free(cld_filter);
8097 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8100 rte_free(cld_filter);
8104 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8105 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
8106 #define I40E_TR_GENEVE_KEY_MASK 0x8
8107 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
8108 #define I40E_TR_GRE_KEY_MASK 0x400
8109 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
8110 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
8111 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8112 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8113 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8114 #define I40E_DIRECTION_INGRESS_KEY 0x8000
8115 #define I40E_TR_L4_TYPE_TCP 0x2
8116 #define I40E_TR_L4_TYPE_UDP 0x4
8117 #define I40E_TR_L4_TYPE_SCTP 0x8
8120 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8122 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8123 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8124 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8125 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8126 enum i40e_status_code status = I40E_SUCCESS;
8128 if (pf->support_multi_driver) {
8129 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8130 return I40E_NOT_SUPPORTED;
8133 memset(&filter_replace, 0,
8134 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8135 memset(&filter_replace_buf, 0,
8136 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8138 /* create L1 filter */
8139 filter_replace.old_filter_type =
8140 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8141 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8142 filter_replace.tr_bit = 0;
8144 /* Prepare the buffer, 3 entries */
8145 filter_replace_buf.data[0] =
8146 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8147 filter_replace_buf.data[0] |=
8148 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8149 filter_replace_buf.data[2] = 0xFF;
8150 filter_replace_buf.data[3] = 0xFF;
8151 filter_replace_buf.data[4] =
8152 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8153 filter_replace_buf.data[4] |=
8154 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8155 filter_replace_buf.data[7] = 0xF0;
8156 filter_replace_buf.data[8]
8157 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8158 filter_replace_buf.data[8] |=
8159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8160 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8161 I40E_TR_GENEVE_KEY_MASK |
8162 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8163 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8164 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8165 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8167 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8168 &filter_replace_buf);
8169 if (!status && (filter_replace.old_filter_type !=
8170 filter_replace.new_filter_type))
8171 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8172 " original: 0x%x, new: 0x%x",
8174 filter_replace.old_filter_type,
8175 filter_replace.new_filter_type);
8181 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8183 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8184 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8185 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8186 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8187 enum i40e_status_code status = I40E_SUCCESS;
8189 if (pf->support_multi_driver) {
8190 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8191 return I40E_NOT_SUPPORTED;
8195 memset(&filter_replace, 0,
8196 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8197 memset(&filter_replace_buf, 0,
8198 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8199 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8200 I40E_AQC_MIRROR_CLOUD_FILTER;
8201 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8202 filter_replace.new_filter_type =
8203 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8204 /* Prepare the buffer, 2 entries */
8205 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8206 filter_replace_buf.data[0] |=
8207 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8208 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8209 filter_replace_buf.data[4] |=
8210 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8211 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8212 &filter_replace_buf);
8215 if (filter_replace.old_filter_type !=
8216 filter_replace.new_filter_type)
8217 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8218 " original: 0x%x, new: 0x%x",
8220 filter_replace.old_filter_type,
8221 filter_replace.new_filter_type);
8224 memset(&filter_replace, 0,
8225 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8226 memset(&filter_replace_buf, 0,
8227 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8229 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8230 I40E_AQC_MIRROR_CLOUD_FILTER;
8231 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8232 filter_replace.new_filter_type =
8233 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8234 /* Prepare the buffer, 2 entries */
8235 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8236 filter_replace_buf.data[0] |=
8237 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8238 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8239 filter_replace_buf.data[4] |=
8240 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8242 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8243 &filter_replace_buf);
8244 if (!status && (filter_replace.old_filter_type !=
8245 filter_replace.new_filter_type))
8246 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8247 " original: 0x%x, new: 0x%x",
8249 filter_replace.old_filter_type,
8250 filter_replace.new_filter_type);
8255 static enum i40e_status_code
8256 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8258 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8259 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8260 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8261 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8262 enum i40e_status_code status = I40E_SUCCESS;
8264 if (pf->support_multi_driver) {
8265 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8266 return I40E_NOT_SUPPORTED;
8270 memset(&filter_replace, 0,
8271 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8272 memset(&filter_replace_buf, 0,
8273 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8274 /* create L1 filter */
8275 filter_replace.old_filter_type =
8276 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8277 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8278 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8279 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8280 /* Prepare the buffer, 2 entries */
8281 filter_replace_buf.data[0] =
8282 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8283 filter_replace_buf.data[0] |=
8284 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8285 filter_replace_buf.data[2] = 0xFF;
8286 filter_replace_buf.data[3] = 0xFF;
8287 filter_replace_buf.data[4] =
8288 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8289 filter_replace_buf.data[4] |=
8290 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8291 filter_replace_buf.data[6] = 0xFF;
8292 filter_replace_buf.data[7] = 0xFF;
8293 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8294 &filter_replace_buf);
8297 if (filter_replace.old_filter_type !=
8298 filter_replace.new_filter_type)
8299 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8300 " original: 0x%x, new: 0x%x",
8302 filter_replace.old_filter_type,
8303 filter_replace.new_filter_type);
8306 memset(&filter_replace, 0,
8307 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8308 memset(&filter_replace_buf, 0,
8309 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8310 /* create L1 filter */
8311 filter_replace.old_filter_type =
8312 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8313 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8314 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8315 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8316 /* Prepare the buffer, 2 entries */
8317 filter_replace_buf.data[0] =
8318 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8319 filter_replace_buf.data[0] |=
8320 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8321 filter_replace_buf.data[2] = 0xFF;
8322 filter_replace_buf.data[3] = 0xFF;
8323 filter_replace_buf.data[4] =
8324 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8325 filter_replace_buf.data[4] |=
8326 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8327 filter_replace_buf.data[6] = 0xFF;
8328 filter_replace_buf.data[7] = 0xFF;
8330 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8331 &filter_replace_buf);
8332 if (!status && (filter_replace.old_filter_type !=
8333 filter_replace.new_filter_type))
8334 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8335 " original: 0x%x, new: 0x%x",
8337 filter_replace.old_filter_type,
8338 filter_replace.new_filter_type);
8344 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8346 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8347 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8348 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8349 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8350 enum i40e_status_code status = I40E_SUCCESS;
8352 if (pf->support_multi_driver) {
8353 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8354 return I40E_NOT_SUPPORTED;
8358 memset(&filter_replace, 0,
8359 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8360 memset(&filter_replace_buf, 0,
8361 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8362 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8363 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8364 filter_replace.new_filter_type =
8365 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8366 /* Prepare the buffer, 2 entries */
8367 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8368 filter_replace_buf.data[0] |=
8369 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8370 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8371 filter_replace_buf.data[4] |=
8372 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8373 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8374 &filter_replace_buf);
8377 if (filter_replace.old_filter_type !=
8378 filter_replace.new_filter_type)
8379 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8380 " original: 0x%x, new: 0x%x",
8382 filter_replace.old_filter_type,
8383 filter_replace.new_filter_type);
8386 memset(&filter_replace, 0,
8387 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8388 memset(&filter_replace_buf, 0,
8389 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8390 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8391 filter_replace.old_filter_type =
8392 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8393 filter_replace.new_filter_type =
8394 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8395 /* Prepare the buffer, 2 entries */
8396 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8397 filter_replace_buf.data[0] |=
8398 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8399 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8400 filter_replace_buf.data[4] |=
8401 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8403 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8404 &filter_replace_buf);
8405 if (!status && (filter_replace.old_filter_type !=
8406 filter_replace.new_filter_type))
8407 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8408 " original: 0x%x, new: 0x%x",
8410 filter_replace.old_filter_type,
8411 filter_replace.new_filter_type);
8416 static enum i40e_status_code
8417 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8418 enum i40e_l4_port_type l4_port_type)
8420 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8421 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8422 enum i40e_status_code status = I40E_SUCCESS;
8423 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8424 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8426 if (pf->support_multi_driver) {
8427 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8428 return I40E_NOT_SUPPORTED;
8431 memset(&filter_replace, 0,
8432 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8433 memset(&filter_replace_buf, 0,
8434 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8436 /* create L1 filter */
8437 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8438 filter_replace.old_filter_type =
8439 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8440 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8441 filter_replace_buf.data[8] =
8442 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8444 filter_replace.old_filter_type =
8445 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8446 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8447 filter_replace_buf.data[8] =
8448 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8451 filter_replace.tr_bit = 0;
8452 /* Prepare the buffer, 3 entries */
8453 filter_replace_buf.data[0] =
8454 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8455 filter_replace_buf.data[0] |=
8456 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8457 filter_replace_buf.data[2] = 0x00;
8458 filter_replace_buf.data[3] =
8459 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8460 filter_replace_buf.data[4] =
8461 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8462 filter_replace_buf.data[4] |=
8463 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8464 filter_replace_buf.data[5] = 0x00;
8465 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8466 I40E_TR_L4_TYPE_TCP |
8467 I40E_TR_L4_TYPE_SCTP;
8468 filter_replace_buf.data[7] = 0x00;
8469 filter_replace_buf.data[8] |=
8470 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8471 filter_replace_buf.data[9] = 0x00;
8472 filter_replace_buf.data[10] = 0xFF;
8473 filter_replace_buf.data[11] = 0xFF;
8475 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8476 &filter_replace_buf);
8477 if (!status && filter_replace.old_filter_type !=
8478 filter_replace.new_filter_type)
8479 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8480 " original: 0x%x, new: 0x%x",
8482 filter_replace.old_filter_type,
8483 filter_replace.new_filter_type);
8488 static enum i40e_status_code
8489 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8490 enum i40e_l4_port_type l4_port_type)
8492 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8493 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8494 enum i40e_status_code status = I40E_SUCCESS;
8495 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8496 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8498 if (pf->support_multi_driver) {
8499 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8500 return I40E_NOT_SUPPORTED;
8503 memset(&filter_replace, 0,
8504 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8505 memset(&filter_replace_buf, 0,
8506 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8508 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8509 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8510 filter_replace.new_filter_type =
8511 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8512 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8514 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8515 filter_replace.new_filter_type =
8516 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8517 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8520 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8521 filter_replace.tr_bit = 0;
8522 /* Prepare the buffer, 2 entries */
8523 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8524 filter_replace_buf.data[0] |=
8525 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8526 filter_replace_buf.data[4] |=
8527 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8528 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8529 &filter_replace_buf);
8531 if (!status && filter_replace.old_filter_type !=
8532 filter_replace.new_filter_type)
8533 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8534 " original: 0x%x, new: 0x%x",
8536 filter_replace.old_filter_type,
8537 filter_replace.new_filter_type);
8543 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8544 struct i40e_tunnel_filter_conf *tunnel_filter,
8548 uint32_t ipv4_addr, ipv4_addr_le;
8549 uint8_t i, tun_type = 0;
8550 /* internal variable to convert ipv6 byte order */
8551 uint32_t convert_ipv6[4];
8553 struct i40e_pf_vf *vf = NULL;
8554 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8555 struct i40e_vsi *vsi;
8556 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8557 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8558 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8559 struct i40e_tunnel_filter *tunnel, *node;
8560 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8562 bool big_buffer = 0;
8564 cld_filter = rte_zmalloc("tunnel_filter",
8565 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8568 if (cld_filter == NULL) {
8569 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8572 pfilter = cld_filter;
8574 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8575 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8576 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8577 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8579 pfilter->element.inner_vlan =
8580 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8581 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8582 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8583 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8584 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8585 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8587 sizeof(pfilter->element.ipaddr.v4.data));
8589 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8590 for (i = 0; i < 4; i++) {
8592 rte_cpu_to_le_32(rte_be_to_cpu_32(
8593 tunnel_filter->ip_addr.ipv6_addr[i]));
8595 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8597 sizeof(pfilter->element.ipaddr.v6.data));
8600 /* check tunneled type */
8601 switch (tunnel_filter->tunnel_type) {
8602 case I40E_TUNNEL_TYPE_VXLAN:
8603 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8605 case I40E_TUNNEL_TYPE_NVGRE:
8606 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8608 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8609 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8611 case I40E_TUNNEL_TYPE_MPLSoUDP:
8612 if (!pf->mpls_replace_flag) {
8613 i40e_replace_mpls_l1_filter(pf);
8614 i40e_replace_mpls_cloud_filter(pf);
8615 pf->mpls_replace_flag = 1;
8617 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8618 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8620 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8621 (teid_le & 0xF) << 12;
8622 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8625 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8627 case I40E_TUNNEL_TYPE_MPLSoGRE:
8628 if (!pf->mpls_replace_flag) {
8629 i40e_replace_mpls_l1_filter(pf);
8630 i40e_replace_mpls_cloud_filter(pf);
8631 pf->mpls_replace_flag = 1;
8633 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8634 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8636 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8637 (teid_le & 0xF) << 12;
8638 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8641 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8643 case I40E_TUNNEL_TYPE_GTPC:
8644 if (!pf->gtp_replace_flag) {
8645 i40e_replace_gtp_l1_filter(pf);
8646 i40e_replace_gtp_cloud_filter(pf);
8647 pf->gtp_replace_flag = 1;
8649 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8650 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8651 (teid_le >> 16) & 0xFFFF;
8652 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8654 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8658 case I40E_TUNNEL_TYPE_GTPU:
8659 if (!pf->gtp_replace_flag) {
8660 i40e_replace_gtp_l1_filter(pf);
8661 i40e_replace_gtp_cloud_filter(pf);
8662 pf->gtp_replace_flag = 1;
8664 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8665 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8666 (teid_le >> 16) & 0xFFFF;
8667 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8669 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8673 case I40E_TUNNEL_TYPE_QINQ:
8674 if (!pf->qinq_replace_flag) {
8675 ret = i40e_cloud_filter_qinq_create(pf);
8678 "QinQ tunnel filter already created.");
8679 pf->qinq_replace_flag = 1;
8681 /* Add in the General fields the values of
8682 * the Outer and Inner VLAN
8683 * Big Buffer should be set, see changes in
8684 * i40e_aq_add_cloud_filters
8686 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8687 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8690 case I40E_CLOUD_TYPE_UDP:
8691 case I40E_CLOUD_TYPE_TCP:
8692 case I40E_CLOUD_TYPE_SCTP:
8693 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8694 if (!pf->sport_replace_flag) {
8695 i40e_replace_port_l1_filter(pf,
8696 tunnel_filter->l4_port_type);
8697 i40e_replace_port_cloud_filter(pf,
8698 tunnel_filter->l4_port_type);
8699 pf->sport_replace_flag = 1;
8701 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8702 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8703 I40E_DIRECTION_INGRESS_KEY;
8705 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8706 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8707 I40E_TR_L4_TYPE_UDP;
8708 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8709 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8710 I40E_TR_L4_TYPE_TCP;
8712 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8713 I40E_TR_L4_TYPE_SCTP;
8715 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8716 (teid_le >> 16) & 0xFFFF;
8719 if (!pf->dport_replace_flag) {
8720 i40e_replace_port_l1_filter(pf,
8721 tunnel_filter->l4_port_type);
8722 i40e_replace_port_cloud_filter(pf,
8723 tunnel_filter->l4_port_type);
8724 pf->dport_replace_flag = 1;
8726 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8727 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8728 I40E_DIRECTION_INGRESS_KEY;
8730 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8731 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8732 I40E_TR_L4_TYPE_UDP;
8733 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8734 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8735 I40E_TR_L4_TYPE_TCP;
8737 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8738 I40E_TR_L4_TYPE_SCTP;
8740 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8741 (teid_le >> 16) & 0xFFFF;
8747 /* Other tunnel types is not supported. */
8748 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8749 rte_free(cld_filter);
8753 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8754 pfilter->element.flags =
8755 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8756 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8757 pfilter->element.flags =
8758 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8759 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8760 pfilter->element.flags =
8761 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8762 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8763 pfilter->element.flags =
8764 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8765 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8766 pfilter->element.flags |=
8767 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8768 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8769 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8770 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8771 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8772 pfilter->element.flags |=
8773 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8775 pfilter->element.flags |=
8776 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8778 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8779 &pfilter->element.flags);
8781 rte_free(cld_filter);
8786 pfilter->element.flags |= rte_cpu_to_le_16(
8787 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8788 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8789 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8790 pfilter->element.queue_number =
8791 rte_cpu_to_le_16(tunnel_filter->queue_id);
8793 if (!tunnel_filter->is_to_vf)
8796 if (tunnel_filter->vf_id >= pf->vf_num) {
8797 PMD_DRV_LOG(ERR, "Invalid argument.");
8798 rte_free(cld_filter);
8801 vf = &pf->vfs[tunnel_filter->vf_id];
8805 /* Check if there is the filter in SW list */
8806 memset(&check_filter, 0, sizeof(check_filter));
8807 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8808 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8809 check_filter.vf_id = tunnel_filter->vf_id;
8810 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8812 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8813 rte_free(cld_filter);
8817 if (!add && !node) {
8818 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8819 rte_free(cld_filter);
8825 ret = i40e_aq_add_cloud_filters_bb(hw,
8826 vsi->seid, cld_filter, 1);
8828 ret = i40e_aq_add_cloud_filters(hw,
8829 vsi->seid, &cld_filter->element, 1);
8831 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8832 rte_free(cld_filter);
8835 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8836 if (tunnel == NULL) {
8837 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8838 rte_free(cld_filter);
8842 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8843 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8848 ret = i40e_aq_rem_cloud_filters_bb(
8849 hw, vsi->seid, cld_filter, 1);
8851 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8852 &cld_filter->element, 1);
8854 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8855 rte_free(cld_filter);
8858 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8861 rte_free(cld_filter);
8866 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8870 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8871 if (pf->vxlan_ports[i] == port)
8879 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8882 uint8_t filter_idx = 0;
8883 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8885 idx = i40e_get_vxlan_port_idx(pf, port);
8887 /* Check if port already exists */
8889 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8893 /* Now check if there is space to add the new port */
8894 idx = i40e_get_vxlan_port_idx(pf, 0);
8897 "Maximum number of UDP ports reached, not adding port %d",
8902 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8905 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8909 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8912 /* New port: add it and mark its index in the bitmap */
8913 pf->vxlan_ports[idx] = port;
8914 pf->vxlan_bitmap |= (1 << idx);
8916 if (!(pf->flags & I40E_FLAG_VXLAN))
8917 pf->flags |= I40E_FLAG_VXLAN;
8923 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8926 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8928 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8929 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8933 idx = i40e_get_vxlan_port_idx(pf, port);
8936 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8940 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8941 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8945 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8948 pf->vxlan_ports[idx] = 0;
8949 pf->vxlan_bitmap &= ~(1 << idx);
8951 if (!pf->vxlan_bitmap)
8952 pf->flags &= ~I40E_FLAG_VXLAN;
8957 /* Add UDP tunneling port */
8959 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8960 struct rte_eth_udp_tunnel *udp_tunnel)
8963 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8965 if (udp_tunnel == NULL)
8968 switch (udp_tunnel->prot_type) {
8969 case RTE_TUNNEL_TYPE_VXLAN:
8970 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8971 I40E_AQC_TUNNEL_TYPE_VXLAN);
8973 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8974 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8975 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8977 case RTE_TUNNEL_TYPE_GENEVE:
8978 case RTE_TUNNEL_TYPE_TEREDO:
8979 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8984 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8992 /* Remove UDP tunneling port */
8994 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8995 struct rte_eth_udp_tunnel *udp_tunnel)
8998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9000 if (udp_tunnel == NULL)
9003 switch (udp_tunnel->prot_type) {
9004 case RTE_TUNNEL_TYPE_VXLAN:
9005 case RTE_TUNNEL_TYPE_VXLAN_GPE:
9006 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
9008 case RTE_TUNNEL_TYPE_GENEVE:
9009 case RTE_TUNNEL_TYPE_TEREDO:
9010 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9014 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9022 /* Calculate the maximum number of contiguous PF queues that are configured */
9024 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
9026 struct rte_eth_dev_data *data = pf->dev_data;
9028 struct i40e_rx_queue *rxq;
9031 for (i = 0; i < pf->lan_nb_qps; i++) {
9032 rxq = data->rx_queues[i];
9033 if (rxq && rxq->q_set)
9044 i40e_pf_config_rss(struct i40e_pf *pf)
9046 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9047 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9048 struct rte_eth_rss_conf rss_conf;
9049 uint32_t i, lut = 0;
9053 * If both VMDQ and RSS enabled, not all of PF queues are configured.
9054 * It's necessary to calculate the actual PF queues that are configured.
9056 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9057 num = i40e_pf_calc_configured_queues_num(pf);
9059 num = pf->dev_data->nb_rx_queues;
9061 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9062 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9067 "No PF queues are configured to enable RSS for port %u",
9068 pf->dev_data->port_id);
9072 if (pf->adapter->rss_reta_updated == 0) {
9073 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9076 lut = (lut << 8) | (j & ((0x1 <<
9077 hw->func_caps.rss_table_entry_width) - 1));
9079 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9084 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9085 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
9086 !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
9087 i40e_pf_disable_rss(pf);
9090 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9091 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9092 /* Random default keys */
9093 static uint32_t rss_key_default[] = {0x6b793944,
9094 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9095 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9096 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9098 rss_conf.rss_key = (uint8_t *)rss_key_default;
9099 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9103 return i40e_hw_rss_hash_set(pf, &rss_conf);
9107 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9108 struct rte_eth_tunnel_filter_conf *filter)
9110 if (pf == NULL || filter == NULL) {
9111 PMD_DRV_LOG(ERR, "Invalid parameter");
9115 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9116 PMD_DRV_LOG(ERR, "Invalid queue ID");
9120 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9121 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9125 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9126 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9127 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9131 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9132 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9133 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9140 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9141 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
9143 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9145 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9149 if (pf->support_multi_driver) {
9150 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9154 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9155 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9158 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9159 } else if (len == 4) {
9160 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9162 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9167 ret = i40e_aq_debug_write_global_register(hw,
9168 I40E_GL_PRS_FVBM(2),
9172 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9173 "with value 0x%08x",
9174 I40E_GL_PRS_FVBM(2), reg);
9178 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9179 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9185 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9192 switch (cfg->cfg_type) {
9193 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9194 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9197 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9205 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9206 enum rte_filter_op filter_op,
9209 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9210 int ret = I40E_ERR_PARAM;
9212 switch (filter_op) {
9213 case RTE_ETH_FILTER_SET:
9214 ret = i40e_dev_global_config_set(hw,
9215 (struct rte_eth_global_cfg *)arg);
9218 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9226 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9227 enum rte_filter_op filter_op,
9230 struct rte_eth_tunnel_filter_conf *filter;
9231 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9232 int ret = I40E_SUCCESS;
9234 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9236 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9237 return I40E_ERR_PARAM;
9239 switch (filter_op) {
9240 case RTE_ETH_FILTER_NOP:
9241 if (!(pf->flags & I40E_FLAG_VXLAN))
9242 ret = I40E_NOT_SUPPORTED;
9244 case RTE_ETH_FILTER_ADD:
9245 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9247 case RTE_ETH_FILTER_DELETE:
9248 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9251 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9252 ret = I40E_ERR_PARAM;
9259 /* Get the symmetric hash enable configurations per port */
9261 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9263 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9265 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9268 /* Set the symmetric hash enable configurations per port */
9270 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9272 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9275 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9277 "Symmetric hash has already been enabled");
9280 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9282 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9284 "Symmetric hash has already been disabled");
9287 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9289 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9290 I40E_WRITE_FLUSH(hw);
9294 * Get global configurations of hash function type and symmetric hash enable
9295 * per flow type (pctype). Note that global configuration means it affects all
9296 * the ports on the same NIC.
9299 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9300 struct rte_eth_hash_global_conf *g_cfg)
9302 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9306 memset(g_cfg, 0, sizeof(*g_cfg));
9307 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9308 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9309 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9311 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9312 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9313 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9316 * As i40e supports less than 64 flow types, only first 64 bits need to
9319 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9320 g_cfg->valid_bit_mask[i] = 0ULL;
9321 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9324 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9326 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9327 if (!adapter->pctypes_tbl[i])
9329 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9330 j < I40E_FILTER_PCTYPE_MAX; j++) {
9331 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9332 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9333 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9334 g_cfg->sym_hash_enable_mask[0] |=
9345 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9346 const struct rte_eth_hash_global_conf *g_cfg)
9349 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9351 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9352 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9353 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9354 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9360 * As i40e supports less than 64 flow types, only first 64 bits need to
9363 mask0 = g_cfg->valid_bit_mask[0];
9364 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9366 /* Check if any unsupported flow type configured */
9367 if ((mask0 | i40e_mask) ^ i40e_mask)
9370 if (g_cfg->valid_bit_mask[i])
9378 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9384 * Set global configurations of hash function type and symmetric hash enable
9385 * per flow type (pctype). Note any modifying global configuration will affect
9386 * all the ports on the same NIC.
9389 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9390 struct rte_eth_hash_global_conf *g_cfg)
9392 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9393 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9397 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9399 if (pf->support_multi_driver) {
9400 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9404 /* Check the input parameters */
9405 ret = i40e_hash_global_config_check(adapter, g_cfg);
9410 * As i40e supports less than 64 flow types, only first 64 bits need to
9413 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9414 if (mask0 & (1UL << i)) {
9415 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9416 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9418 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9419 j < I40E_FILTER_PCTYPE_MAX; j++) {
9420 if (adapter->pctypes_tbl[i] & (1ULL << j))
9421 i40e_write_global_rx_ctl(hw,
9428 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9429 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9431 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9433 "Hash function already set to Toeplitz");
9436 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9437 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9439 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9441 "Hash function already set to Simple XOR");
9444 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9446 /* Use the default, and keep it as it is */
9449 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9452 I40E_WRITE_FLUSH(hw);
9458 * Valid input sets for hash and flow director filters per PCTYPE
9461 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9462 enum rte_filter_type filter)
9466 static const uint64_t valid_hash_inset_table[] = {
9467 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9468 I40E_INSET_DMAC | I40E_INSET_SMAC |
9469 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9470 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9471 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9472 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9473 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9474 I40E_INSET_FLEX_PAYLOAD,
9475 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9476 I40E_INSET_DMAC | I40E_INSET_SMAC |
9477 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9478 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9479 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9480 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9481 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9482 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9483 I40E_INSET_FLEX_PAYLOAD,
9484 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9485 I40E_INSET_DMAC | I40E_INSET_SMAC |
9486 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9487 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9488 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9489 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9490 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9491 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9492 I40E_INSET_FLEX_PAYLOAD,
9493 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9494 I40E_INSET_DMAC | I40E_INSET_SMAC |
9495 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9496 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9497 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9498 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9499 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9500 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9501 I40E_INSET_FLEX_PAYLOAD,
9502 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9503 I40E_INSET_DMAC | I40E_INSET_SMAC |
9504 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9505 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9506 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9507 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9508 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9509 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9510 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9511 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9512 I40E_INSET_DMAC | I40E_INSET_SMAC |
9513 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9514 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9515 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9516 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9517 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9518 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9519 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9520 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9521 I40E_INSET_DMAC | I40E_INSET_SMAC |
9522 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9523 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9524 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9525 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9526 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9527 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9528 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9529 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9530 I40E_INSET_DMAC | I40E_INSET_SMAC |
9531 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9532 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9533 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9534 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9535 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9536 I40E_INSET_FLEX_PAYLOAD,
9537 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9538 I40E_INSET_DMAC | I40E_INSET_SMAC |
9539 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9540 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9541 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9542 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9543 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9544 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9545 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9546 I40E_INSET_DMAC | I40E_INSET_SMAC |
9547 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9548 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9549 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9550 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9551 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9552 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9553 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9554 I40E_INSET_DMAC | I40E_INSET_SMAC |
9555 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9556 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9557 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9558 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9559 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9560 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9561 I40E_INSET_FLEX_PAYLOAD,
9562 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9563 I40E_INSET_DMAC | I40E_INSET_SMAC |
9564 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9565 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9566 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9567 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9568 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9569 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9570 I40E_INSET_FLEX_PAYLOAD,
9571 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9572 I40E_INSET_DMAC | I40E_INSET_SMAC |
9573 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9574 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9575 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9576 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9577 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9578 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9579 I40E_INSET_FLEX_PAYLOAD,
9580 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9581 I40E_INSET_DMAC | I40E_INSET_SMAC |
9582 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9583 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9584 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9585 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9586 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9587 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9588 I40E_INSET_FLEX_PAYLOAD,
9589 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9590 I40E_INSET_DMAC | I40E_INSET_SMAC |
9591 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9592 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9593 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9594 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9595 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9596 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9597 I40E_INSET_FLEX_PAYLOAD,
9598 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9599 I40E_INSET_DMAC | I40E_INSET_SMAC |
9600 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9601 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9602 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9603 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9604 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9605 I40E_INSET_FLEX_PAYLOAD,
9606 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9607 I40E_INSET_DMAC | I40E_INSET_SMAC |
9608 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9609 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9610 I40E_INSET_FLEX_PAYLOAD,
9614 * Flow director supports only fields defined in
9615 * union rte_eth_fdir_flow.
9617 static const uint64_t valid_fdir_inset_table[] = {
9618 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9619 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9620 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9621 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9622 I40E_INSET_IPV4_TTL,
9623 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9624 I40E_INSET_DMAC | I40E_INSET_SMAC |
9625 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9626 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9627 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9628 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9629 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9630 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9631 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9632 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9633 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9634 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9635 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9636 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9637 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9638 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9639 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9640 I40E_INSET_DMAC | I40E_INSET_SMAC |
9641 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9642 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9643 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9644 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9645 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9646 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9647 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9648 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9649 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9650 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9651 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9652 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9653 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9654 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9656 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9657 I40E_INSET_DMAC | I40E_INSET_SMAC |
9658 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9659 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9660 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9661 I40E_INSET_IPV4_TTL,
9662 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9663 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9664 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9665 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9666 I40E_INSET_IPV6_HOP_LIMIT,
9667 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9668 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9669 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9670 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9671 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9672 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9673 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9674 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9675 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9676 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9677 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9678 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9679 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9680 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9681 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9682 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9683 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9684 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9685 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9686 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9687 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9688 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9689 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9690 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9691 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9692 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9693 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9694 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9695 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9696 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9698 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9699 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9700 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9701 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9702 I40E_INSET_IPV6_HOP_LIMIT,
9703 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9704 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9705 I40E_INSET_LAST_ETHER_TYPE,
9708 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9710 if (filter == RTE_ETH_FILTER_HASH)
9711 valid = valid_hash_inset_table[pctype];
9713 valid = valid_fdir_inset_table[pctype];
9719 * Validate if the input set is allowed for a specific PCTYPE
9722 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9723 enum rte_filter_type filter, uint64_t inset)
9727 valid = i40e_get_valid_input_set(pctype, filter);
9728 if (inset & (~valid))
9734 /* default input set fields combination per pctype */
9736 i40e_get_default_input_set(uint16_t pctype)
9738 static const uint64_t default_inset_table[] = {
9739 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9740 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9741 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9742 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9743 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9744 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9745 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9746 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9747 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9748 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9749 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9750 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9751 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9752 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9753 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9754 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9755 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9756 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9757 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9758 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9760 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9761 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9762 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9763 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9764 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9765 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9766 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9767 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9768 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9769 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9770 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9771 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9772 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9773 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9774 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9775 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9776 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9777 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9778 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9779 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9780 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9781 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9783 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9784 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9785 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9786 I40E_INSET_LAST_ETHER_TYPE,
9789 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9792 return default_inset_table[pctype];
9796 * Parse the input set from index to logical bit masks
9799 i40e_parse_input_set(uint64_t *inset,
9800 enum i40e_filter_pctype pctype,
9801 enum rte_eth_input_set_field *field,
9807 static const struct {
9808 enum rte_eth_input_set_field field;
9810 } inset_convert_table[] = {
9811 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9812 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9813 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9814 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9815 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9816 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9817 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9818 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9819 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9820 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9821 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9822 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9823 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9824 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9825 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9826 I40E_INSET_IPV6_NEXT_HDR},
9827 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9828 I40E_INSET_IPV6_HOP_LIMIT},
9829 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9830 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9831 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9832 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9833 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9834 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9835 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9836 I40E_INSET_SCTP_VT},
9837 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9838 I40E_INSET_TUNNEL_DMAC},
9839 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9840 I40E_INSET_VLAN_TUNNEL},
9841 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9842 I40E_INSET_TUNNEL_ID},
9843 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9844 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9845 I40E_INSET_FLEX_PAYLOAD_W1},
9846 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9847 I40E_INSET_FLEX_PAYLOAD_W2},
9848 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9849 I40E_INSET_FLEX_PAYLOAD_W3},
9850 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9851 I40E_INSET_FLEX_PAYLOAD_W4},
9852 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9853 I40E_INSET_FLEX_PAYLOAD_W5},
9854 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9855 I40E_INSET_FLEX_PAYLOAD_W6},
9856 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9857 I40E_INSET_FLEX_PAYLOAD_W7},
9858 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9859 I40E_INSET_FLEX_PAYLOAD_W8},
9862 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9865 /* Only one item allowed for default or all */
9867 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9868 *inset = i40e_get_default_input_set(pctype);
9870 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9871 *inset = I40E_INSET_NONE;
9876 for (i = 0, *inset = 0; i < size; i++) {
9877 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9878 if (field[i] == inset_convert_table[j].field) {
9879 *inset |= inset_convert_table[j].inset;
9884 /* It contains unsupported input set, return immediately */
9885 if (j == RTE_DIM(inset_convert_table))
9893 * Translate the input set from bit masks to register aware bit masks
9897 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9907 static const struct inset_map inset_map_common[] = {
9908 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9909 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9910 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9911 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9912 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9913 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9914 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9915 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9916 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9917 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9918 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9919 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9920 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9921 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9922 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9923 {I40E_INSET_TUNNEL_DMAC,
9924 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9925 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9926 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9927 {I40E_INSET_TUNNEL_SRC_PORT,
9928 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9929 {I40E_INSET_TUNNEL_DST_PORT,
9930 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9931 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9932 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9933 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9934 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9935 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9936 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9937 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9938 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9939 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9942 /* some different registers map in x722*/
9943 static const struct inset_map inset_map_diff_x722[] = {
9944 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9945 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9946 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9947 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9950 static const struct inset_map inset_map_diff_not_x722[] = {
9951 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9952 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9953 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9954 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9960 /* Translate input set to register aware inset */
9961 if (type == I40E_MAC_X722) {
9962 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9963 if (input & inset_map_diff_x722[i].inset)
9964 val |= inset_map_diff_x722[i].inset_reg;
9967 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9968 if (input & inset_map_diff_not_x722[i].inset)
9969 val |= inset_map_diff_not_x722[i].inset_reg;
9973 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9974 if (input & inset_map_common[i].inset)
9975 val |= inset_map_common[i].inset_reg;
9982 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9985 uint64_t inset_need_mask = inset;
9987 static const struct {
9990 } inset_mask_map[] = {
9991 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9992 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9993 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9994 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9995 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9996 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9997 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9998 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
10001 if (!inset || !mask || !nb_elem)
10004 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10005 /* Clear the inset bit, if no MASK is required,
10006 * for example proto + ttl
10008 if ((inset & inset_mask_map[i].inset) ==
10009 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
10010 inset_need_mask &= ~inset_mask_map[i].inset;
10011 if (!inset_need_mask)
10014 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10015 if ((inset_need_mask & inset_mask_map[i].inset) ==
10016 inset_mask_map[i].inset) {
10017 if (idx >= nb_elem) {
10018 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
10021 mask[idx] = inset_mask_map[i].mask;
10030 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10032 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10034 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10036 i40e_write_rx_ctl(hw, addr, val);
10037 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10038 (uint32_t)i40e_read_rx_ctl(hw, addr));
10042 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10044 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10045 struct rte_eth_dev *dev;
10047 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10049 i40e_write_rx_ctl(hw, addr, val);
10050 PMD_DRV_LOG(WARNING,
10051 "i40e device %s changed global register [0x%08x]."
10052 " original: 0x%08x, new: 0x%08x",
10053 dev->device->name, addr, reg,
10054 (uint32_t)i40e_read_rx_ctl(hw, addr));
10059 i40e_filter_input_set_init(struct i40e_pf *pf)
10061 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10062 enum i40e_filter_pctype pctype;
10063 uint64_t input_set, inset_reg;
10064 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10066 uint16_t flow_type;
10068 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10069 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10070 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10072 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10075 input_set = i40e_get_default_input_set(pctype);
10077 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10078 I40E_INSET_MASK_NUM_REG);
10081 if (pf->support_multi_driver && num > 0) {
10082 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10085 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10088 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10089 (uint32_t)(inset_reg & UINT32_MAX));
10090 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10091 (uint32_t)((inset_reg >>
10092 I40E_32_BIT_WIDTH) & UINT32_MAX));
10093 if (!pf->support_multi_driver) {
10094 i40e_check_write_global_reg(hw,
10095 I40E_GLQF_HASH_INSET(0, pctype),
10096 (uint32_t)(inset_reg & UINT32_MAX));
10097 i40e_check_write_global_reg(hw,
10098 I40E_GLQF_HASH_INSET(1, pctype),
10099 (uint32_t)((inset_reg >>
10100 I40E_32_BIT_WIDTH) & UINT32_MAX));
10102 for (i = 0; i < num; i++) {
10103 i40e_check_write_global_reg(hw,
10104 I40E_GLQF_FD_MSK(i, pctype),
10106 i40e_check_write_global_reg(hw,
10107 I40E_GLQF_HASH_MSK(i, pctype),
10110 /*clear unused mask registers of the pctype */
10111 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10112 i40e_check_write_global_reg(hw,
10113 I40E_GLQF_FD_MSK(i, pctype),
10115 i40e_check_write_global_reg(hw,
10116 I40E_GLQF_HASH_MSK(i, pctype),
10120 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10122 I40E_WRITE_FLUSH(hw);
10124 /* store the default input set */
10125 if (!pf->support_multi_driver)
10126 pf->hash_input_set[pctype] = input_set;
10127 pf->fdir.input_set[pctype] = input_set;
10132 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10133 struct rte_eth_input_set_conf *conf)
10135 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10136 enum i40e_filter_pctype pctype;
10137 uint64_t input_set, inset_reg = 0;
10138 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10142 PMD_DRV_LOG(ERR, "Invalid pointer");
10145 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10146 conf->op != RTE_ETH_INPUT_SET_ADD) {
10147 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10151 if (pf->support_multi_driver) {
10152 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10156 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10157 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10158 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10162 if (hw->mac.type == I40E_MAC_X722) {
10163 /* get translated pctype value in fd pctype register */
10164 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10165 I40E_GLQF_FD_PCTYPES((int)pctype));
10168 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10171 PMD_DRV_LOG(ERR, "Failed to parse input set");
10175 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10176 /* get inset value in register */
10177 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10178 inset_reg <<= I40E_32_BIT_WIDTH;
10179 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10180 input_set |= pf->hash_input_set[pctype];
10182 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10183 I40E_INSET_MASK_NUM_REG);
10187 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10189 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10190 (uint32_t)(inset_reg & UINT32_MAX));
10191 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10192 (uint32_t)((inset_reg >>
10193 I40E_32_BIT_WIDTH) & UINT32_MAX));
10195 for (i = 0; i < num; i++)
10196 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10198 /*clear unused mask registers of the pctype */
10199 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10200 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10202 I40E_WRITE_FLUSH(hw);
10204 pf->hash_input_set[pctype] = input_set;
10209 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10210 struct rte_eth_input_set_conf *conf)
10212 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10213 enum i40e_filter_pctype pctype;
10214 uint64_t input_set, inset_reg = 0;
10215 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10218 if (!hw || !conf) {
10219 PMD_DRV_LOG(ERR, "Invalid pointer");
10222 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10223 conf->op != RTE_ETH_INPUT_SET_ADD) {
10224 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10228 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10230 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10231 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10235 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10238 PMD_DRV_LOG(ERR, "Failed to parse input set");
10242 /* get inset value in register */
10243 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10244 inset_reg <<= I40E_32_BIT_WIDTH;
10245 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10247 /* Can not change the inset reg for flex payload for fdir,
10248 * it is done by writing I40E_PRTQF_FD_FLXINSET
10249 * in i40e_set_flex_mask_on_pctype.
10251 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10252 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10254 input_set |= pf->fdir.input_set[pctype];
10255 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10256 I40E_INSET_MASK_NUM_REG);
10259 if (pf->support_multi_driver && num > 0) {
10260 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10264 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10266 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10267 (uint32_t)(inset_reg & UINT32_MAX));
10268 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10269 (uint32_t)((inset_reg >>
10270 I40E_32_BIT_WIDTH) & UINT32_MAX));
10272 if (!pf->support_multi_driver) {
10273 for (i = 0; i < num; i++)
10274 i40e_check_write_global_reg(hw,
10275 I40E_GLQF_FD_MSK(i, pctype),
10277 /*clear unused mask registers of the pctype */
10278 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10279 i40e_check_write_global_reg(hw,
10280 I40E_GLQF_FD_MSK(i, pctype),
10283 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10285 I40E_WRITE_FLUSH(hw);
10287 pf->fdir.input_set[pctype] = input_set;
10292 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10296 if (!hw || !info) {
10297 PMD_DRV_LOG(ERR, "Invalid pointer");
10301 switch (info->info_type) {
10302 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10303 i40e_get_symmetric_hash_enable_per_port(hw,
10304 &(info->info.enable));
10306 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10307 ret = i40e_get_hash_filter_global_config(hw,
10308 &(info->info.global_conf));
10311 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10321 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10325 if (!hw || !info) {
10326 PMD_DRV_LOG(ERR, "Invalid pointer");
10330 switch (info->info_type) {
10331 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10332 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10334 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10335 ret = i40e_set_hash_filter_global_config(hw,
10336 &(info->info.global_conf));
10338 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10339 ret = i40e_hash_filter_inset_select(hw,
10340 &(info->info.input_set_conf));
10344 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10353 /* Operations for hash function */
10355 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10356 enum rte_filter_op filter_op,
10359 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10362 switch (filter_op) {
10363 case RTE_ETH_FILTER_NOP:
10365 case RTE_ETH_FILTER_GET:
10366 ret = i40e_hash_filter_get(hw,
10367 (struct rte_eth_hash_filter_info *)arg);
10369 case RTE_ETH_FILTER_SET:
10370 ret = i40e_hash_filter_set(hw,
10371 (struct rte_eth_hash_filter_info *)arg);
10374 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10383 /* Convert ethertype filter structure */
10385 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10386 struct i40e_ethertype_filter *filter)
10388 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10389 RTE_ETHER_ADDR_LEN);
10390 filter->input.ether_type = input->ether_type;
10391 filter->flags = input->flags;
10392 filter->queue = input->queue;
10397 /* Check if there exists the ehtertype filter */
10398 struct i40e_ethertype_filter *
10399 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10400 const struct i40e_ethertype_filter_input *input)
10404 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10408 return ethertype_rule->hash_map[ret];
10411 /* Add ethertype filter in SW list */
10413 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10414 struct i40e_ethertype_filter *filter)
10416 struct i40e_ethertype_rule *rule = &pf->ethertype;
10419 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10422 "Failed to insert ethertype filter"
10423 " to hash table %d!",
10427 rule->hash_map[ret] = filter;
10429 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10434 /* Delete ethertype filter in SW list */
10436 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10437 struct i40e_ethertype_filter_input *input)
10439 struct i40e_ethertype_rule *rule = &pf->ethertype;
10440 struct i40e_ethertype_filter *filter;
10443 ret = rte_hash_del_key(rule->hash_table, input);
10446 "Failed to delete ethertype filter"
10447 " to hash table %d!",
10451 filter = rule->hash_map[ret];
10452 rule->hash_map[ret] = NULL;
10454 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10461 * Configure ethertype filter, which can director packet by filtering
10462 * with mac address and ether_type or only ether_type
10465 i40e_ethertype_filter_set(struct i40e_pf *pf,
10466 struct rte_eth_ethertype_filter *filter,
10469 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10470 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10471 struct i40e_ethertype_filter *ethertype_filter, *node;
10472 struct i40e_ethertype_filter check_filter;
10473 struct i40e_control_filter_stats stats;
10474 uint16_t flags = 0;
10477 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10478 PMD_DRV_LOG(ERR, "Invalid queue ID");
10481 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10482 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10484 "unsupported ether_type(0x%04x) in control packet filter.",
10485 filter->ether_type);
10488 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10489 PMD_DRV_LOG(WARNING,
10490 "filter vlan ether_type in first tag is not supported.");
10492 /* Check if there is the filter in SW list */
10493 memset(&check_filter, 0, sizeof(check_filter));
10494 i40e_ethertype_filter_convert(filter, &check_filter);
10495 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10496 &check_filter.input);
10498 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10502 if (!add && !node) {
10503 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10507 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10508 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10509 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10510 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10511 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10513 memset(&stats, 0, sizeof(stats));
10514 ret = i40e_aq_add_rem_control_packet_filter(hw,
10515 filter->mac_addr.addr_bytes,
10516 filter->ether_type, flags,
10517 pf->main_vsi->seid,
10518 filter->queue, add, &stats, NULL);
10521 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10522 ret, stats.mac_etype_used, stats.etype_used,
10523 stats.mac_etype_free, stats.etype_free);
10527 /* Add or delete a filter in SW list */
10529 ethertype_filter = rte_zmalloc("ethertype_filter",
10530 sizeof(*ethertype_filter), 0);
10531 if (ethertype_filter == NULL) {
10532 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10536 rte_memcpy(ethertype_filter, &check_filter,
10537 sizeof(check_filter));
10538 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10540 rte_free(ethertype_filter);
10542 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10549 * Handle operations for ethertype filter.
10552 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10553 enum rte_filter_op filter_op,
10556 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10559 if (filter_op == RTE_ETH_FILTER_NOP)
10563 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10568 switch (filter_op) {
10569 case RTE_ETH_FILTER_ADD:
10570 ret = i40e_ethertype_filter_set(pf,
10571 (struct rte_eth_ethertype_filter *)arg,
10574 case RTE_ETH_FILTER_DELETE:
10575 ret = i40e_ethertype_filter_set(pf,
10576 (struct rte_eth_ethertype_filter *)arg,
10580 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10588 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10589 enum rte_filter_type filter_type,
10590 enum rte_filter_op filter_op,
10598 switch (filter_type) {
10599 case RTE_ETH_FILTER_NONE:
10600 /* For global configuration */
10601 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10603 case RTE_ETH_FILTER_HASH:
10604 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10606 case RTE_ETH_FILTER_MACVLAN:
10607 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10609 case RTE_ETH_FILTER_ETHERTYPE:
10610 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10612 case RTE_ETH_FILTER_TUNNEL:
10613 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10615 case RTE_ETH_FILTER_FDIR:
10616 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10618 case RTE_ETH_FILTER_GENERIC:
10619 if (filter_op != RTE_ETH_FILTER_GET)
10621 *(const void **)arg = &i40e_flow_ops;
10624 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10634 * Check and enable Extended Tag.
10635 * Enabling Extended Tag is important for 40G performance.
10638 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10640 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10644 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10647 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10651 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10652 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10657 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10660 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10664 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10665 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10668 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10669 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10672 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10679 * As some registers wouldn't be reset unless a global hardware reset,
10680 * hardware initialization is needed to put those registers into an
10681 * expected initial state.
10684 i40e_hw_init(struct rte_eth_dev *dev)
10686 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10688 i40e_enable_extended_tag(dev);
10690 /* clear the PF Queue Filter control register */
10691 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10693 /* Disable symmetric hash per port */
10694 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10698 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10699 * however this function will return only one highest pctype index,
10700 * which is not quite correct. This is known problem of i40e driver
10701 * and needs to be fixed later.
10703 enum i40e_filter_pctype
10704 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10707 uint64_t pctype_mask;
10709 if (flow_type < I40E_FLOW_TYPE_MAX) {
10710 pctype_mask = adapter->pctypes_tbl[flow_type];
10711 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10712 if (pctype_mask & (1ULL << i))
10713 return (enum i40e_filter_pctype)i;
10716 return I40E_FILTER_PCTYPE_INVALID;
10720 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10721 enum i40e_filter_pctype pctype)
10724 uint64_t pctype_mask = 1ULL << pctype;
10726 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10728 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10732 return RTE_ETH_FLOW_UNKNOWN;
10736 * On X710, performance number is far from the expectation on recent firmware
10737 * versions; on XL710, performance number is also far from the expectation on
10738 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10739 * mode is enabled and port MAC address is equal to the packet destination MAC
10740 * address. The fix for this issue may not be integrated in the following
10741 * firmware version. So the workaround in software driver is needed. It needs
10742 * to modify the initial values of 3 internal only registers for both X710 and
10743 * XL710. Note that the values for X710 or XL710 could be different, and the
10744 * workaround can be removed when it is fixed in firmware in the future.
10747 /* For both X710 and XL710 */
10748 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10749 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10750 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10752 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10753 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10756 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10757 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10760 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10762 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10763 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10766 * GL_SWR_PM_UP_THR:
10767 * The value is not impacted from the link speed, its value is set according
10768 * to the total number of ports for a better pipe-monitor configuration.
10771 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10773 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10774 .device_id = (dev), \
10775 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10777 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10778 .device_id = (dev), \
10779 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10781 static const struct {
10782 uint16_t device_id;
10784 } swr_pm_table[] = {
10785 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10786 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10787 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10788 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10789 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10791 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10792 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10793 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10794 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10795 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10796 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10797 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10801 if (value == NULL) {
10802 PMD_DRV_LOG(ERR, "value is NULL");
10806 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10807 if (hw->device_id == swr_pm_table[i].device_id) {
10808 *value = swr_pm_table[i].val;
10810 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10812 hw->device_id, *value);
10821 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10823 enum i40e_status_code status;
10824 struct i40e_aq_get_phy_abilities_resp phy_ab;
10825 int ret = -ENOTSUP;
10828 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10832 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10835 rte_delay_us(100000);
10837 status = i40e_aq_get_phy_capabilities(hw, false,
10838 true, &phy_ab, NULL);
10846 i40e_configure_registers(struct i40e_hw *hw)
10852 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10853 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10854 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10860 for (i = 0; i < RTE_DIM(reg_table); i++) {
10861 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10862 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10864 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10865 else /* For X710/XL710/XXV710 */
10866 if (hw->aq.fw_maj_ver < 6)
10868 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10871 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10874 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10875 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10877 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10878 else /* For X710/XL710/XXV710 */
10880 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10883 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10886 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10887 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10888 "GL_SWR_PM_UP_THR value fixup",
10893 reg_table[i].val = cfg_val;
10896 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10899 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10900 reg_table[i].addr);
10903 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10904 reg_table[i].addr, reg);
10905 if (reg == reg_table[i].val)
10908 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10909 reg_table[i].val, NULL);
10912 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10913 reg_table[i].val, reg_table[i].addr);
10916 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10917 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10921 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10922 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10923 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10925 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10930 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10931 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10935 /* Configure for double VLAN RX stripping */
10936 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10937 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10938 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10939 ret = i40e_aq_debug_write_register(hw,
10940 I40E_VSI_TSR(vsi->vsi_id),
10943 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10945 return I40E_ERR_CONFIG;
10949 /* Configure for double VLAN TX insertion */
10950 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10951 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10952 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10953 ret = i40e_aq_debug_write_register(hw,
10954 I40E_VSI_L2TAGSTXVALID(
10955 vsi->vsi_id), reg, NULL);
10958 "Failed to update VSI_L2TAGSTXVALID[%d]",
10960 return I40E_ERR_CONFIG;
10968 * i40e_aq_add_mirror_rule
10969 * @hw: pointer to the hardware structure
10970 * @seid: VEB seid to add mirror rule to
10971 * @dst_id: destination vsi seid
10972 * @entries: Buffer which contains the entities to be mirrored
10973 * @count: number of entities contained in the buffer
10974 * @rule_id:the rule_id of the rule to be added
10976 * Add a mirror rule for a given veb.
10979 static enum i40e_status_code
10980 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10981 uint16_t seid, uint16_t dst_id,
10982 uint16_t rule_type, uint16_t *entries,
10983 uint16_t count, uint16_t *rule_id)
10985 struct i40e_aq_desc desc;
10986 struct i40e_aqc_add_delete_mirror_rule cmd;
10987 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10988 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10991 enum i40e_status_code status;
10993 i40e_fill_default_direct_cmd_desc(&desc,
10994 i40e_aqc_opc_add_mirror_rule);
10995 memset(&cmd, 0, sizeof(cmd));
10997 buff_len = sizeof(uint16_t) * count;
10998 desc.datalen = rte_cpu_to_le_16(buff_len);
11000 desc.flags |= rte_cpu_to_le_16(
11001 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
11002 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11003 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11004 cmd.num_entries = rte_cpu_to_le_16(count);
11005 cmd.seid = rte_cpu_to_le_16(seid);
11006 cmd.destination = rte_cpu_to_le_16(dst_id);
11008 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11009 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
11011 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
11012 hw->aq.asq_last_status, resp->rule_id,
11013 resp->mirror_rules_used, resp->mirror_rules_free);
11014 *rule_id = rte_le_to_cpu_16(resp->rule_id);
11020 * i40e_aq_del_mirror_rule
11021 * @hw: pointer to the hardware structure
11022 * @seid: VEB seid to add mirror rule to
11023 * @entries: Buffer which contains the entities to be mirrored
11024 * @count: number of entities contained in the buffer
11025 * @rule_id:the rule_id of the rule to be delete
11027 * Delete a mirror rule for a given veb.
11030 static enum i40e_status_code
11031 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
11032 uint16_t seid, uint16_t rule_type, uint16_t *entries,
11033 uint16_t count, uint16_t rule_id)
11035 struct i40e_aq_desc desc;
11036 struct i40e_aqc_add_delete_mirror_rule cmd;
11037 uint16_t buff_len = 0;
11038 enum i40e_status_code status;
11041 i40e_fill_default_direct_cmd_desc(&desc,
11042 i40e_aqc_opc_delete_mirror_rule);
11043 memset(&cmd, 0, sizeof(cmd));
11044 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11045 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11047 cmd.num_entries = count;
11048 buff_len = sizeof(uint16_t) * count;
11049 desc.datalen = rte_cpu_to_le_16(buff_len);
11050 buff = (void *)entries;
11052 /* rule id is filled in destination field for deleting mirror rule */
11053 cmd.destination = rte_cpu_to_le_16(rule_id);
11055 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11056 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11057 cmd.seid = rte_cpu_to_le_16(seid);
11059 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11060 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11066 * i40e_mirror_rule_set
11067 * @dev: pointer to the hardware structure
11068 * @mirror_conf: mirror rule info
11069 * @sw_id: mirror rule's sw_id
11070 * @on: enable/disable
11072 * set a mirror rule.
11076 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11077 struct rte_eth_mirror_conf *mirror_conf,
11078 uint8_t sw_id, uint8_t on)
11080 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11081 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11082 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11083 struct i40e_mirror_rule *parent = NULL;
11084 uint16_t seid, dst_seid, rule_id;
11088 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11090 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11092 "mirror rule can not be configured without veb or vfs.");
11095 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11096 PMD_DRV_LOG(ERR, "mirror table is full.");
11099 if (mirror_conf->dst_pool > pf->vf_num) {
11100 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11101 mirror_conf->dst_pool);
11105 seid = pf->main_vsi->veb->seid;
11107 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11108 if (sw_id <= it->index) {
11114 if (mirr_rule && sw_id == mirr_rule->index) {
11116 PMD_DRV_LOG(ERR, "mirror rule exists.");
11119 ret = i40e_aq_del_mirror_rule(hw, seid,
11120 mirr_rule->rule_type,
11121 mirr_rule->entries,
11122 mirr_rule->num_entries, mirr_rule->id);
11125 "failed to remove mirror rule: ret = %d, aq_err = %d.",
11126 ret, hw->aq.asq_last_status);
11129 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11130 rte_free(mirr_rule);
11131 pf->nb_mirror_rule--;
11135 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11139 mirr_rule = rte_zmalloc("i40e_mirror_rule",
11140 sizeof(struct i40e_mirror_rule) , 0);
11142 PMD_DRV_LOG(ERR, "failed to allocate memory");
11143 return I40E_ERR_NO_MEMORY;
11145 switch (mirror_conf->rule_type) {
11146 case ETH_MIRROR_VLAN:
11147 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11148 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11149 mirr_rule->entries[j] =
11150 mirror_conf->vlan.vlan_id[i];
11155 PMD_DRV_LOG(ERR, "vlan is not specified.");
11156 rte_free(mirr_rule);
11159 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11161 case ETH_MIRROR_VIRTUAL_POOL_UP:
11162 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11163 /* check if the specified pool bit is out of range */
11164 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11165 PMD_DRV_LOG(ERR, "pool mask is out of range.");
11166 rte_free(mirr_rule);
11169 for (i = 0, j = 0; i < pf->vf_num; i++) {
11170 if (mirror_conf->pool_mask & (1ULL << i)) {
11171 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11175 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11176 /* add pf vsi to entries */
11177 mirr_rule->entries[j] = pf->main_vsi_seid;
11181 PMD_DRV_LOG(ERR, "pool is not specified.");
11182 rte_free(mirr_rule);
11185 /* egress and ingress in aq commands means from switch but not port */
11186 mirr_rule->rule_type =
11187 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11188 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11189 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11191 case ETH_MIRROR_UPLINK_PORT:
11192 /* egress and ingress in aq commands means from switch but not port*/
11193 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11195 case ETH_MIRROR_DOWNLINK_PORT:
11196 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11199 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11200 mirror_conf->rule_type);
11201 rte_free(mirr_rule);
11205 /* If the dst_pool is equal to vf_num, consider it as PF */
11206 if (mirror_conf->dst_pool == pf->vf_num)
11207 dst_seid = pf->main_vsi_seid;
11209 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11211 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11212 mirr_rule->rule_type, mirr_rule->entries,
11216 "failed to add mirror rule: ret = %d, aq_err = %d.",
11217 ret, hw->aq.asq_last_status);
11218 rte_free(mirr_rule);
11222 mirr_rule->index = sw_id;
11223 mirr_rule->num_entries = j;
11224 mirr_rule->id = rule_id;
11225 mirr_rule->dst_vsi_seid = dst_seid;
11228 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11230 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11232 pf->nb_mirror_rule++;
11237 * i40e_mirror_rule_reset
11238 * @dev: pointer to the device
11239 * @sw_id: mirror rule's sw_id
11241 * reset a mirror rule.
11245 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11247 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11248 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11249 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11253 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11255 seid = pf->main_vsi->veb->seid;
11257 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11258 if (sw_id == it->index) {
11264 ret = i40e_aq_del_mirror_rule(hw, seid,
11265 mirr_rule->rule_type,
11266 mirr_rule->entries,
11267 mirr_rule->num_entries, mirr_rule->id);
11270 "failed to remove mirror rule: status = %d, aq_err = %d.",
11271 ret, hw->aq.asq_last_status);
11274 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11275 rte_free(mirr_rule);
11276 pf->nb_mirror_rule--;
11278 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11285 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11287 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11288 uint64_t systim_cycles;
11290 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11291 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11294 return systim_cycles;
11298 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11300 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11301 uint64_t rx_tstamp;
11303 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11304 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11311 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11313 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11314 uint64_t tx_tstamp;
11316 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11317 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11324 i40e_start_timecounters(struct rte_eth_dev *dev)
11326 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11327 struct i40e_adapter *adapter = dev->data->dev_private;
11328 struct rte_eth_link link;
11329 uint32_t tsync_inc_l;
11330 uint32_t tsync_inc_h;
11332 /* Get current link speed. */
11333 i40e_dev_link_update(dev, 1);
11334 rte_eth_linkstatus_get(dev, &link);
11336 switch (link.link_speed) {
11337 case ETH_SPEED_NUM_40G:
11338 case ETH_SPEED_NUM_25G:
11339 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11340 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11342 case ETH_SPEED_NUM_10G:
11343 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11344 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11346 case ETH_SPEED_NUM_1G:
11347 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11348 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11355 /* Set the timesync increment value. */
11356 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11357 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11359 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11360 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11361 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11363 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11364 adapter->systime_tc.cc_shift = 0;
11365 adapter->systime_tc.nsec_mask = 0;
11367 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11368 adapter->rx_tstamp_tc.cc_shift = 0;
11369 adapter->rx_tstamp_tc.nsec_mask = 0;
11371 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11372 adapter->tx_tstamp_tc.cc_shift = 0;
11373 adapter->tx_tstamp_tc.nsec_mask = 0;
11377 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11379 struct i40e_adapter *adapter = dev->data->dev_private;
11381 adapter->systime_tc.nsec += delta;
11382 adapter->rx_tstamp_tc.nsec += delta;
11383 adapter->tx_tstamp_tc.nsec += delta;
11389 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11392 struct i40e_adapter *adapter = dev->data->dev_private;
11394 ns = rte_timespec_to_ns(ts);
11396 /* Set the timecounters to a new value. */
11397 adapter->systime_tc.nsec = ns;
11398 adapter->rx_tstamp_tc.nsec = ns;
11399 adapter->tx_tstamp_tc.nsec = ns;
11405 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11407 uint64_t ns, systime_cycles;
11408 struct i40e_adapter *adapter = dev->data->dev_private;
11410 systime_cycles = i40e_read_systime_cyclecounter(dev);
11411 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11412 *ts = rte_ns_to_timespec(ns);
11418 i40e_timesync_enable(struct rte_eth_dev *dev)
11420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11421 uint32_t tsync_ctl_l;
11422 uint32_t tsync_ctl_h;
11424 /* Stop the timesync system time. */
11425 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11426 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11427 /* Reset the timesync system time value. */
11428 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11429 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11431 i40e_start_timecounters(dev);
11433 /* Clear timesync registers. */
11434 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11435 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11436 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11437 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11438 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11439 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11441 /* Enable timestamping of PTP packets. */
11442 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11443 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11445 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11446 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11447 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11449 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11450 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11456 i40e_timesync_disable(struct rte_eth_dev *dev)
11458 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11459 uint32_t tsync_ctl_l;
11460 uint32_t tsync_ctl_h;
11462 /* Disable timestamping of transmitted PTP packets. */
11463 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11464 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11466 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11467 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11469 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11470 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11472 /* Reset the timesync increment value. */
11473 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11474 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11480 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11481 struct timespec *timestamp, uint32_t flags)
11483 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11484 struct i40e_adapter *adapter = dev->data->dev_private;
11485 uint32_t sync_status;
11486 uint32_t index = flags & 0x03;
11487 uint64_t rx_tstamp_cycles;
11490 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11491 if ((sync_status & (1 << index)) == 0)
11494 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11495 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11496 *timestamp = rte_ns_to_timespec(ns);
11502 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11503 struct timespec *timestamp)
11505 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11506 struct i40e_adapter *adapter = dev->data->dev_private;
11507 uint32_t sync_status;
11508 uint64_t tx_tstamp_cycles;
11511 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11512 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11515 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11516 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11517 *timestamp = rte_ns_to_timespec(ns);
11523 * i40e_parse_dcb_configure - parse dcb configure from user
11524 * @dev: the device being configured
11525 * @dcb_cfg: pointer of the result of parse
11526 * @*tc_map: bit map of enabled traffic classes
11528 * Returns 0 on success, negative value on failure
11531 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11532 struct i40e_dcbx_config *dcb_cfg,
11535 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11536 uint8_t i, tc_bw, bw_lf;
11538 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11540 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11541 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11542 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11546 /* assume each tc has the same bw */
11547 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11548 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11549 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11550 /* to ensure the sum of tcbw is equal to 100 */
11551 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11552 for (i = 0; i < bw_lf; i++)
11553 dcb_cfg->etscfg.tcbwtable[i]++;
11555 /* assume each tc has the same Transmission Selection Algorithm */
11556 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11557 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11559 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11560 dcb_cfg->etscfg.prioritytable[i] =
11561 dcb_rx_conf->dcb_tc[i];
11563 /* FW needs one App to configure HW */
11564 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11565 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11566 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11567 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11569 if (dcb_rx_conf->nb_tcs == 0)
11570 *tc_map = 1; /* tc0 only */
11572 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11574 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11575 dcb_cfg->pfc.willing = 0;
11576 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11577 dcb_cfg->pfc.pfcenable = *tc_map;
11583 static enum i40e_status_code
11584 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11585 struct i40e_aqc_vsi_properties_data *info,
11586 uint8_t enabled_tcmap)
11588 enum i40e_status_code ret;
11589 int i, total_tc = 0;
11590 uint16_t qpnum_per_tc, bsf, qp_idx;
11591 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11592 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11593 uint16_t used_queues;
11595 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11596 if (ret != I40E_SUCCESS)
11599 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11600 if (enabled_tcmap & (1 << i))
11605 vsi->enabled_tc = enabled_tcmap;
11607 /* different VSI has different queues assigned */
11608 if (vsi->type == I40E_VSI_MAIN)
11609 used_queues = dev_data->nb_rx_queues -
11610 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11611 else if (vsi->type == I40E_VSI_VMDQ2)
11612 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11614 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11615 return I40E_ERR_NO_AVAILABLE_VSI;
11618 qpnum_per_tc = used_queues / total_tc;
11619 /* Number of queues per enabled TC */
11620 if (qpnum_per_tc == 0) {
11621 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11622 return I40E_ERR_INVALID_QP_ID;
11624 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11625 I40E_MAX_Q_PER_TC);
11626 bsf = rte_bsf32(qpnum_per_tc);
11629 * Configure TC and queue mapping parameters, for enabled TC,
11630 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11631 * default queue will serve it.
11634 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11635 if (vsi->enabled_tc & (1 << i)) {
11636 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11637 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11638 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11639 qp_idx += qpnum_per_tc;
11641 info->tc_mapping[i] = 0;
11644 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11645 if (vsi->type == I40E_VSI_SRIOV) {
11646 info->mapping_flags |=
11647 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11648 for (i = 0; i < vsi->nb_qps; i++)
11649 info->queue_mapping[i] =
11650 rte_cpu_to_le_16(vsi->base_queue + i);
11652 info->mapping_flags |=
11653 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11654 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11656 info->valid_sections |=
11657 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11659 return I40E_SUCCESS;
11663 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11664 * @veb: VEB to be configured
11665 * @tc_map: enabled TC bitmap
11667 * Returns 0 on success, negative value on failure
11669 static enum i40e_status_code
11670 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11672 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11673 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11674 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11675 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11676 enum i40e_status_code ret = I40E_SUCCESS;
11680 /* Check if enabled_tc is same as existing or new TCs */
11681 if (veb->enabled_tc == tc_map)
11684 /* configure tc bandwidth */
11685 memset(&veb_bw, 0, sizeof(veb_bw));
11686 veb_bw.tc_valid_bits = tc_map;
11687 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11688 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11689 if (tc_map & BIT_ULL(i))
11690 veb_bw.tc_bw_share_credits[i] = 1;
11692 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11696 "AQ command Config switch_comp BW allocation per TC failed = %d",
11697 hw->aq.asq_last_status);
11701 memset(&ets_query, 0, sizeof(ets_query));
11702 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11704 if (ret != I40E_SUCCESS) {
11706 "Failed to get switch_comp ETS configuration %u",
11707 hw->aq.asq_last_status);
11710 memset(&bw_query, 0, sizeof(bw_query));
11711 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11713 if (ret != I40E_SUCCESS) {
11715 "Failed to get switch_comp bandwidth configuration %u",
11716 hw->aq.asq_last_status);
11720 /* store and print out BW info */
11721 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11722 veb->bw_info.bw_max = ets_query.tc_bw_max;
11723 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11724 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11725 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11726 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11727 I40E_16_BIT_WIDTH);
11728 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11729 veb->bw_info.bw_ets_share_credits[i] =
11730 bw_query.tc_bw_share_credits[i];
11731 veb->bw_info.bw_ets_credits[i] =
11732 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11733 /* 4 bits per TC, 4th bit is reserved */
11734 veb->bw_info.bw_ets_max[i] =
11735 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11736 RTE_LEN2MASK(3, uint8_t));
11737 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11738 veb->bw_info.bw_ets_share_credits[i]);
11739 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11740 veb->bw_info.bw_ets_credits[i]);
11741 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11742 veb->bw_info.bw_ets_max[i]);
11745 veb->enabled_tc = tc_map;
11752 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11753 * @vsi: VSI to be configured
11754 * @tc_map: enabled TC bitmap
11756 * Returns 0 on success, negative value on failure
11758 static enum i40e_status_code
11759 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11761 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11762 struct i40e_vsi_context ctxt;
11763 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11764 enum i40e_status_code ret = I40E_SUCCESS;
11767 /* Check if enabled_tc is same as existing or new TCs */
11768 if (vsi->enabled_tc == tc_map)
11771 /* configure tc bandwidth */
11772 memset(&bw_data, 0, sizeof(bw_data));
11773 bw_data.tc_valid_bits = tc_map;
11774 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11775 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11776 if (tc_map & BIT_ULL(i))
11777 bw_data.tc_bw_credits[i] = 1;
11779 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11782 "AQ command Config VSI BW allocation per TC failed = %d",
11783 hw->aq.asq_last_status);
11786 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11787 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11789 /* Update Queue Pairs Mapping for currently enabled UPs */
11790 ctxt.seid = vsi->seid;
11791 ctxt.pf_num = hw->pf_id;
11793 ctxt.uplink_seid = vsi->uplink_seid;
11794 ctxt.info = vsi->info;
11796 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11800 /* Update the VSI after updating the VSI queue-mapping information */
11801 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11803 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11804 hw->aq.asq_last_status);
11807 /* update the local VSI info with updated queue map */
11808 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11809 sizeof(vsi->info.tc_mapping));
11810 rte_memcpy(&vsi->info.queue_mapping,
11811 &ctxt.info.queue_mapping,
11812 sizeof(vsi->info.queue_mapping));
11813 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11814 vsi->info.valid_sections = 0;
11816 /* query and update current VSI BW information */
11817 ret = i40e_vsi_get_bw_config(vsi);
11820 "Failed updating vsi bw info, err %s aq_err %s",
11821 i40e_stat_str(hw, ret),
11822 i40e_aq_str(hw, hw->aq.asq_last_status));
11826 vsi->enabled_tc = tc_map;
11833 * i40e_dcb_hw_configure - program the dcb setting to hw
11834 * @pf: pf the configuration is taken on
11835 * @new_cfg: new configuration
11836 * @tc_map: enabled TC bitmap
11838 * Returns 0 on success, negative value on failure
11840 static enum i40e_status_code
11841 i40e_dcb_hw_configure(struct i40e_pf *pf,
11842 struct i40e_dcbx_config *new_cfg,
11845 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11846 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11847 struct i40e_vsi *main_vsi = pf->main_vsi;
11848 struct i40e_vsi_list *vsi_list;
11849 enum i40e_status_code ret;
11853 /* Use the FW API if FW > v4.4*/
11854 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11855 (hw->aq.fw_maj_ver >= 5))) {
11857 "FW < v4.4, can not use FW LLDP API to configure DCB");
11858 return I40E_ERR_FIRMWARE_API_VERSION;
11861 /* Check if need reconfiguration */
11862 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11863 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11864 return I40E_SUCCESS;
11867 /* Copy the new config to the current config */
11868 *old_cfg = *new_cfg;
11869 old_cfg->etsrec = old_cfg->etscfg;
11870 ret = i40e_set_dcb_config(hw);
11872 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11873 i40e_stat_str(hw, ret),
11874 i40e_aq_str(hw, hw->aq.asq_last_status));
11877 /* set receive Arbiter to RR mode and ETS scheme by default */
11878 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11879 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11880 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11881 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11882 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11883 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11884 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11885 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11886 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11887 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11888 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11889 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11890 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11892 /* get local mib to check whether it is configured correctly */
11894 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11895 /* Get Local DCB Config */
11896 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11897 &hw->local_dcbx_config);
11899 /* if Veb is created, need to update TC of it at first */
11900 if (main_vsi->veb) {
11901 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11903 PMD_INIT_LOG(WARNING,
11904 "Failed configuring TC for VEB seid=%d",
11905 main_vsi->veb->seid);
11907 /* Update each VSI */
11908 i40e_vsi_config_tc(main_vsi, tc_map);
11909 if (main_vsi->veb) {
11910 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11911 /* Beside main VSI and VMDQ VSIs, only enable default
11912 * TC for other VSIs
11914 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11915 ret = i40e_vsi_config_tc(vsi_list->vsi,
11918 ret = i40e_vsi_config_tc(vsi_list->vsi,
11919 I40E_DEFAULT_TCMAP);
11921 PMD_INIT_LOG(WARNING,
11922 "Failed configuring TC for VSI seid=%d",
11923 vsi_list->vsi->seid);
11927 return I40E_SUCCESS;
11931 * i40e_dcb_init_configure - initial dcb config
11932 * @dev: device being configured
11933 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11935 * Returns 0 on success, negative value on failure
11938 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11944 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11945 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11949 /* DCB initialization:
11950 * Update DCB configuration from the Firmware and configure
11951 * LLDP MIB change event.
11953 if (sw_dcb == TRUE) {
11954 /* Stopping lldp is necessary for DPDK, but it will cause
11955 * DCB init failed. For i40e_init_dcb(), the prerequisite
11956 * for successful initialization of DCB is that LLDP is
11957 * enabled. So it is needed to start lldp before DCB init
11958 * and stop it after initialization.
11960 ret = i40e_aq_start_lldp(hw, true, NULL);
11961 if (ret != I40E_SUCCESS)
11962 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11964 ret = i40e_init_dcb(hw, true);
11965 /* If lldp agent is stopped, the return value from
11966 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11967 * adminq status. Otherwise, it should return success.
11969 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11970 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11971 memset(&hw->local_dcbx_config, 0,
11972 sizeof(struct i40e_dcbx_config));
11973 /* set dcb default configuration */
11974 hw->local_dcbx_config.etscfg.willing = 0;
11975 hw->local_dcbx_config.etscfg.maxtcs = 0;
11976 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11977 hw->local_dcbx_config.etscfg.tsatable[0] =
11979 /* all UPs mapping to TC0 */
11980 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11981 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11982 hw->local_dcbx_config.etsrec =
11983 hw->local_dcbx_config.etscfg;
11984 hw->local_dcbx_config.pfc.willing = 0;
11985 hw->local_dcbx_config.pfc.pfccap =
11986 I40E_MAX_TRAFFIC_CLASS;
11987 /* FW needs one App to configure HW */
11988 hw->local_dcbx_config.numapps = 1;
11989 hw->local_dcbx_config.app[0].selector =
11990 I40E_APP_SEL_ETHTYPE;
11991 hw->local_dcbx_config.app[0].priority = 3;
11992 hw->local_dcbx_config.app[0].protocolid =
11993 I40E_APP_PROTOID_FCOE;
11994 ret = i40e_set_dcb_config(hw);
11997 "default dcb config fails. err = %d, aq_err = %d.",
11998 ret, hw->aq.asq_last_status);
12003 "DCB initialization in FW fails, err = %d, aq_err = %d.",
12004 ret, hw->aq.asq_last_status);
12008 if (i40e_need_stop_lldp(dev)) {
12009 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
12010 if (ret != I40E_SUCCESS)
12011 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
12014 ret = i40e_aq_start_lldp(hw, true, NULL);
12015 if (ret != I40E_SUCCESS)
12016 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
12018 ret = i40e_init_dcb(hw, true);
12020 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
12022 "HW doesn't support DCBX offload.");
12027 "DCBX configuration failed, err = %d, aq_err = %d.",
12028 ret, hw->aq.asq_last_status);
12036 * i40e_dcb_setup - setup dcb related config
12037 * @dev: device being configured
12039 * Returns 0 on success, negative value on failure
12042 i40e_dcb_setup(struct rte_eth_dev *dev)
12044 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12045 struct i40e_dcbx_config dcb_cfg;
12046 uint8_t tc_map = 0;
12049 if ((pf->flags & I40E_FLAG_DCB) == 0) {
12050 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12054 if (pf->vf_num != 0)
12055 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12057 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12059 PMD_INIT_LOG(ERR, "invalid dcb config");
12062 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12064 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12072 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12073 struct rte_eth_dcb_info *dcb_info)
12075 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12076 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12077 struct i40e_vsi *vsi = pf->main_vsi;
12078 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12079 uint16_t bsf, tc_mapping;
12082 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12083 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12085 dcb_info->nb_tcs = 1;
12086 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12087 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12088 for (i = 0; i < dcb_info->nb_tcs; i++)
12089 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12091 /* get queue mapping if vmdq is disabled */
12092 if (!pf->nb_cfg_vmdq_vsi) {
12093 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12094 if (!(vsi->enabled_tc & (1 << i)))
12096 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12097 dcb_info->tc_queue.tc_rxq[j][i].base =
12098 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12099 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12100 dcb_info->tc_queue.tc_txq[j][i].base =
12101 dcb_info->tc_queue.tc_rxq[j][i].base;
12102 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12103 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12104 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12105 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12106 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12111 /* get queue mapping if vmdq is enabled */
12113 vsi = pf->vmdq[j].vsi;
12114 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12115 if (!(vsi->enabled_tc & (1 << i)))
12117 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12118 dcb_info->tc_queue.tc_rxq[j][i].base =
12119 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12120 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12121 dcb_info->tc_queue.tc_txq[j][i].base =
12122 dcb_info->tc_queue.tc_rxq[j][i].base;
12123 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12124 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12125 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12126 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12127 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12130 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12135 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12137 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12138 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12139 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12140 uint16_t msix_intr;
12142 msix_intr = intr_handle->intr_vec[queue_id];
12143 if (msix_intr == I40E_MISC_VEC_ID)
12144 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12145 I40E_PFINT_DYN_CTL0_INTENA_MASK |
12146 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12147 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12150 I40E_PFINT_DYN_CTLN(msix_intr -
12151 I40E_RX_VEC_START),
12152 I40E_PFINT_DYN_CTLN_INTENA_MASK |
12153 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12154 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12156 I40E_WRITE_FLUSH(hw);
12157 rte_intr_ack(&pci_dev->intr_handle);
12163 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12165 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12166 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12168 uint16_t msix_intr;
12170 msix_intr = intr_handle->intr_vec[queue_id];
12171 if (msix_intr == I40E_MISC_VEC_ID)
12172 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12173 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12176 I40E_PFINT_DYN_CTLN(msix_intr -
12177 I40E_RX_VEC_START),
12178 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12179 I40E_WRITE_FLUSH(hw);
12185 * This function is used to check if the register is valid.
12186 * Below is the valid registers list for X722 only:
12190 * 0x208e00--0x209000
12191 * 0x20be00--0x20c000
12192 * 0x263c00--0x264000
12193 * 0x265c00--0x266000
12195 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12197 if ((type != I40E_MAC_X722) &&
12198 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12199 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12200 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12201 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12202 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12203 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12204 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12210 static int i40e_get_regs(struct rte_eth_dev *dev,
12211 struct rte_dev_reg_info *regs)
12213 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12214 uint32_t *ptr_data = regs->data;
12215 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12216 const struct i40e_reg_info *reg_info;
12218 if (ptr_data == NULL) {
12219 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12220 regs->width = sizeof(uint32_t);
12224 /* The first few registers have to be read using AQ operations */
12226 while (i40e_regs_adminq[reg_idx].name) {
12227 reg_info = &i40e_regs_adminq[reg_idx++];
12228 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12230 arr_idx2 <= reg_info->count2;
12232 reg_offset = arr_idx * reg_info->stride1 +
12233 arr_idx2 * reg_info->stride2;
12234 reg_offset += reg_info->base_addr;
12235 ptr_data[reg_offset >> 2] =
12236 i40e_read_rx_ctl(hw, reg_offset);
12240 /* The remaining registers can be read using primitives */
12242 while (i40e_regs_others[reg_idx].name) {
12243 reg_info = &i40e_regs_others[reg_idx++];
12244 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12246 arr_idx2 <= reg_info->count2;
12248 reg_offset = arr_idx * reg_info->stride1 +
12249 arr_idx2 * reg_info->stride2;
12250 reg_offset += reg_info->base_addr;
12251 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12252 ptr_data[reg_offset >> 2] = 0;
12254 ptr_data[reg_offset >> 2] =
12255 I40E_READ_REG(hw, reg_offset);
12262 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12264 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12266 /* Convert word count to byte count */
12267 return hw->nvm.sr_size << 1;
12270 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12271 struct rte_dev_eeprom_info *eeprom)
12273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12274 uint16_t *data = eeprom->data;
12275 uint16_t offset, length, cnt_words;
12278 offset = eeprom->offset >> 1;
12279 length = eeprom->length >> 1;
12280 cnt_words = length;
12282 if (offset > hw->nvm.sr_size ||
12283 offset + length > hw->nvm.sr_size) {
12284 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12288 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12290 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12291 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12292 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12299 static int i40e_get_module_info(struct rte_eth_dev *dev,
12300 struct rte_eth_dev_module_info *modinfo)
12302 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12303 uint32_t sff8472_comp = 0;
12304 uint32_t sff8472_swap = 0;
12305 uint32_t sff8636_rev = 0;
12306 i40e_status status;
12309 /* Check if firmware supports reading module EEPROM. */
12310 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12312 "Module EEPROM memory read not supported. "
12313 "Please update the NVM image.\n");
12317 status = i40e_update_link_info(hw);
12321 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12323 "Cannot read module EEPROM memory. "
12324 "No module connected.\n");
12328 type = hw->phy.link_info.module_type[0];
12331 case I40E_MODULE_TYPE_SFP:
12332 status = i40e_aq_get_phy_register(hw,
12333 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12334 I40E_I2C_EEPROM_DEV_ADDR, 1,
12335 I40E_MODULE_SFF_8472_COMP,
12336 &sff8472_comp, NULL);
12340 status = i40e_aq_get_phy_register(hw,
12341 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12342 I40E_I2C_EEPROM_DEV_ADDR, 1,
12343 I40E_MODULE_SFF_8472_SWAP,
12344 &sff8472_swap, NULL);
12348 /* Check if the module requires address swap to access
12349 * the other EEPROM memory page.
12351 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12352 PMD_DRV_LOG(WARNING,
12353 "Module address swap to access "
12354 "page 0xA2 is not supported.\n");
12355 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12356 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12357 } else if (sff8472_comp == 0x00) {
12358 /* Module is not SFF-8472 compliant */
12359 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12360 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12362 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12363 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12366 case I40E_MODULE_TYPE_QSFP_PLUS:
12367 /* Read from memory page 0. */
12368 status = i40e_aq_get_phy_register(hw,
12369 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12371 I40E_MODULE_REVISION_ADDR,
12372 &sff8636_rev, NULL);
12375 /* Determine revision compliance byte */
12376 if (sff8636_rev > 0x02) {
12377 /* Module is SFF-8636 compliant */
12378 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12379 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12381 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12382 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12385 case I40E_MODULE_TYPE_QSFP28:
12386 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12387 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12390 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12396 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12397 struct rte_dev_eeprom_info *info)
12399 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12400 bool is_sfp = false;
12401 i40e_status status;
12403 uint32_t value = 0;
12406 if (!info || !info->length || !info->data)
12409 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12413 for (i = 0; i < info->length; i++) {
12414 u32 offset = i + info->offset;
12415 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12417 /* Check if we need to access the other memory page */
12419 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12420 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12421 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12424 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12425 /* Compute memory page number and offset. */
12426 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12430 status = i40e_aq_get_phy_register(hw,
12431 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12432 addr, 1, offset, &value, NULL);
12435 data[i] = (uint8_t)value;
12440 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12441 struct rte_ether_addr *mac_addr)
12443 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12445 struct i40e_vsi *vsi = pf->main_vsi;
12446 struct i40e_mac_filter_info mac_filter;
12447 struct i40e_mac_filter *f;
12450 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12451 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12455 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12456 if (rte_is_same_ether_addr(&pf->dev_addr,
12457 &f->mac_info.mac_addr))
12462 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12466 mac_filter = f->mac_info;
12467 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12468 if (ret != I40E_SUCCESS) {
12469 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12472 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12473 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12474 if (ret != I40E_SUCCESS) {
12475 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12478 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12480 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12481 mac_addr->addr_bytes, NULL);
12482 if (ret != I40E_SUCCESS) {
12483 PMD_DRV_LOG(ERR, "Failed to change mac");
12491 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12494 struct rte_eth_dev_data *dev_data = pf->dev_data;
12495 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12498 /* check if mtu is within the allowed range */
12499 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12502 /* mtu setting is forbidden if port is start */
12503 if (dev_data->dev_started) {
12504 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12505 dev_data->port_id);
12509 if (frame_size > RTE_ETHER_MAX_LEN)
12510 dev_data->dev_conf.rxmode.offloads |=
12511 DEV_RX_OFFLOAD_JUMBO_FRAME;
12513 dev_data->dev_conf.rxmode.offloads &=
12514 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12516 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12521 /* Restore ethertype filter */
12523 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12525 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12526 struct i40e_ethertype_filter_list
12527 *ethertype_list = &pf->ethertype.ethertype_list;
12528 struct i40e_ethertype_filter *f;
12529 struct i40e_control_filter_stats stats;
12532 TAILQ_FOREACH(f, ethertype_list, rules) {
12534 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12535 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12536 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12537 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12538 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12540 memset(&stats, 0, sizeof(stats));
12541 i40e_aq_add_rem_control_packet_filter(hw,
12542 f->input.mac_addr.addr_bytes,
12543 f->input.ether_type,
12544 flags, pf->main_vsi->seid,
12545 f->queue, 1, &stats, NULL);
12547 PMD_DRV_LOG(INFO, "Ethertype filter:"
12548 " mac_etype_used = %u, etype_used = %u,"
12549 " mac_etype_free = %u, etype_free = %u",
12550 stats.mac_etype_used, stats.etype_used,
12551 stats.mac_etype_free, stats.etype_free);
12554 /* Restore tunnel filter */
12556 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12558 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12559 struct i40e_vsi *vsi;
12560 struct i40e_pf_vf *vf;
12561 struct i40e_tunnel_filter_list
12562 *tunnel_list = &pf->tunnel.tunnel_list;
12563 struct i40e_tunnel_filter *f;
12564 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12565 bool big_buffer = 0;
12567 TAILQ_FOREACH(f, tunnel_list, rules) {
12569 vsi = pf->main_vsi;
12571 vf = &pf->vfs[f->vf_id];
12574 memset(&cld_filter, 0, sizeof(cld_filter));
12575 rte_ether_addr_copy((struct rte_ether_addr *)
12576 &f->input.outer_mac,
12577 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12578 rte_ether_addr_copy((struct rte_ether_addr *)
12579 &f->input.inner_mac,
12580 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12581 cld_filter.element.inner_vlan = f->input.inner_vlan;
12582 cld_filter.element.flags = f->input.flags;
12583 cld_filter.element.tenant_id = f->input.tenant_id;
12584 cld_filter.element.queue_number = f->queue;
12585 rte_memcpy(cld_filter.general_fields,
12586 f->input.general_fields,
12587 sizeof(f->input.general_fields));
12589 if (((f->input.flags &
12590 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12591 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12593 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12594 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12596 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12597 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12601 i40e_aq_add_cloud_filters_bb(hw,
12602 vsi->seid, &cld_filter, 1);
12604 i40e_aq_add_cloud_filters(hw, vsi->seid,
12605 &cld_filter.element, 1);
12609 /* Restore RSS filter */
12611 i40e_rss_filter_restore(struct i40e_pf *pf)
12613 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12614 struct i40e_rss_filter *filter;
12616 TAILQ_FOREACH(filter, list, next) {
12617 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12622 i40e_filter_restore(struct i40e_pf *pf)
12624 i40e_ethertype_filter_restore(pf);
12625 i40e_tunnel_filter_restore(pf);
12626 i40e_fdir_filter_restore(pf);
12627 i40e_rss_filter_restore(pf);
12631 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12633 if (strcmp(dev->device->driver->name, drv->driver.name))
12640 is_i40e_supported(struct rte_eth_dev *dev)
12642 return is_device_supported(dev, &rte_i40e_pmd);
12645 struct i40e_customized_pctype*
12646 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12650 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12651 if (pf->customized_pctype[i].index == index)
12652 return &pf->customized_pctype[i];
12658 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12659 uint32_t pkg_size, uint32_t proto_num,
12660 struct rte_pmd_i40e_proto_info *proto,
12661 enum rte_pmd_i40e_package_op op)
12663 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12664 uint32_t pctype_num;
12665 struct rte_pmd_i40e_ptype_info *pctype;
12666 uint32_t buff_size;
12667 struct i40e_customized_pctype *new_pctype = NULL;
12669 uint8_t pctype_value;
12674 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12675 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12676 PMD_DRV_LOG(ERR, "Unsupported operation.");
12680 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12681 (uint8_t *)&pctype_num, sizeof(pctype_num),
12682 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12684 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12688 PMD_DRV_LOG(INFO, "No new pctype added");
12692 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12693 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12695 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12698 /* get information about new pctype list */
12699 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12700 (uint8_t *)pctype, buff_size,
12701 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12703 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12708 /* Update customized pctype. */
12709 for (i = 0; i < pctype_num; i++) {
12710 pctype_value = pctype[i].ptype_id;
12711 memset(name, 0, sizeof(name));
12712 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12713 proto_id = pctype[i].protocols[j];
12714 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12716 for (n = 0; n < proto_num; n++) {
12717 if (proto[n].proto_id != proto_id)
12719 strlcat(name, proto[n].name, sizeof(name));
12720 strlcat(name, "_", sizeof(name));
12724 name[strlen(name) - 1] = '\0';
12725 PMD_DRV_LOG(INFO, "name = %s\n", name);
12726 if (!strcmp(name, "GTPC"))
12728 i40e_find_customized_pctype(pf,
12729 I40E_CUSTOMIZED_GTPC);
12730 else if (!strcmp(name, "GTPU_IPV4"))
12732 i40e_find_customized_pctype(pf,
12733 I40E_CUSTOMIZED_GTPU_IPV4);
12734 else if (!strcmp(name, "GTPU_IPV6"))
12736 i40e_find_customized_pctype(pf,
12737 I40E_CUSTOMIZED_GTPU_IPV6);
12738 else if (!strcmp(name, "GTPU"))
12740 i40e_find_customized_pctype(pf,
12741 I40E_CUSTOMIZED_GTPU);
12742 else if (!strcmp(name, "IPV4_L2TPV3"))
12744 i40e_find_customized_pctype(pf,
12745 I40E_CUSTOMIZED_IPV4_L2TPV3);
12746 else if (!strcmp(name, "IPV6_L2TPV3"))
12748 i40e_find_customized_pctype(pf,
12749 I40E_CUSTOMIZED_IPV6_L2TPV3);
12750 else if (!strcmp(name, "IPV4_ESP"))
12752 i40e_find_customized_pctype(pf,
12753 I40E_CUSTOMIZED_ESP_IPV4);
12754 else if (!strcmp(name, "IPV6_ESP"))
12756 i40e_find_customized_pctype(pf,
12757 I40E_CUSTOMIZED_ESP_IPV6);
12758 else if (!strcmp(name, "IPV4_UDP_ESP"))
12760 i40e_find_customized_pctype(pf,
12761 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12762 else if (!strcmp(name, "IPV6_UDP_ESP"))
12764 i40e_find_customized_pctype(pf,
12765 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12766 else if (!strcmp(name, "IPV4_AH"))
12768 i40e_find_customized_pctype(pf,
12769 I40E_CUSTOMIZED_AH_IPV4);
12770 else if (!strcmp(name, "IPV6_AH"))
12772 i40e_find_customized_pctype(pf,
12773 I40E_CUSTOMIZED_AH_IPV6);
12775 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12776 new_pctype->pctype = pctype_value;
12777 new_pctype->valid = true;
12779 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12780 new_pctype->valid = false;
12790 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12791 uint32_t pkg_size, uint32_t proto_num,
12792 struct rte_pmd_i40e_proto_info *proto,
12793 enum rte_pmd_i40e_package_op op)
12795 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12796 uint16_t port_id = dev->data->port_id;
12797 uint32_t ptype_num;
12798 struct rte_pmd_i40e_ptype_info *ptype;
12799 uint32_t buff_size;
12801 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12806 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12807 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12808 PMD_DRV_LOG(ERR, "Unsupported operation.");
12812 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12813 rte_pmd_i40e_ptype_mapping_reset(port_id);
12817 /* get information about new ptype num */
12818 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12819 (uint8_t *)&ptype_num, sizeof(ptype_num),
12820 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12822 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12826 PMD_DRV_LOG(INFO, "No new ptype added");
12830 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12831 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12833 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12837 /* get information about new ptype list */
12838 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12839 (uint8_t *)ptype, buff_size,
12840 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12842 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12847 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12848 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12849 if (!ptype_mapping) {
12850 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12855 /* Update ptype mapping table. */
12856 for (i = 0; i < ptype_num; i++) {
12857 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12858 ptype_mapping[i].sw_ptype = 0;
12860 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12861 proto_id = ptype[i].protocols[j];
12862 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12864 for (n = 0; n < proto_num; n++) {
12865 if (proto[n].proto_id != proto_id)
12867 memset(name, 0, sizeof(name));
12868 strcpy(name, proto[n].name);
12869 PMD_DRV_LOG(INFO, "name = %s\n", name);
12870 if (!strncasecmp(name, "PPPOE", 5))
12871 ptype_mapping[i].sw_ptype |=
12872 RTE_PTYPE_L2_ETHER_PPPOE;
12873 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12875 ptype_mapping[i].sw_ptype |=
12876 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12877 ptype_mapping[i].sw_ptype |=
12879 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12881 ptype_mapping[i].sw_ptype |=
12882 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12883 ptype_mapping[i].sw_ptype |=
12884 RTE_PTYPE_INNER_L4_FRAG;
12885 } else if (!strncasecmp(name, "OIPV4", 5)) {
12886 ptype_mapping[i].sw_ptype |=
12887 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12889 } else if (!strncasecmp(name, "IPV4", 4) &&
12891 ptype_mapping[i].sw_ptype |=
12892 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12893 else if (!strncasecmp(name, "IPV4", 4) &&
12895 ptype_mapping[i].sw_ptype |=
12896 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12897 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12899 ptype_mapping[i].sw_ptype |=
12900 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12901 ptype_mapping[i].sw_ptype |=
12903 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12905 ptype_mapping[i].sw_ptype |=
12906 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12907 ptype_mapping[i].sw_ptype |=
12908 RTE_PTYPE_INNER_L4_FRAG;
12909 } else if (!strncasecmp(name, "OIPV6", 5)) {
12910 ptype_mapping[i].sw_ptype |=
12911 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12913 } else if (!strncasecmp(name, "IPV6", 4) &&
12915 ptype_mapping[i].sw_ptype |=
12916 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12917 else if (!strncasecmp(name, "IPV6", 4) &&
12919 ptype_mapping[i].sw_ptype |=
12920 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12921 else if (!strncasecmp(name, "UDP", 3) &&
12923 ptype_mapping[i].sw_ptype |=
12925 else if (!strncasecmp(name, "UDP", 3) &&
12927 ptype_mapping[i].sw_ptype |=
12928 RTE_PTYPE_INNER_L4_UDP;
12929 else if (!strncasecmp(name, "TCP", 3) &&
12931 ptype_mapping[i].sw_ptype |=
12933 else if (!strncasecmp(name, "TCP", 3) &&
12935 ptype_mapping[i].sw_ptype |=
12936 RTE_PTYPE_INNER_L4_TCP;
12937 else if (!strncasecmp(name, "SCTP", 4) &&
12939 ptype_mapping[i].sw_ptype |=
12941 else if (!strncasecmp(name, "SCTP", 4) &&
12943 ptype_mapping[i].sw_ptype |=
12944 RTE_PTYPE_INNER_L4_SCTP;
12945 else if ((!strncasecmp(name, "ICMP", 4) ||
12946 !strncasecmp(name, "ICMPV6", 6)) &&
12948 ptype_mapping[i].sw_ptype |=
12950 else if ((!strncasecmp(name, "ICMP", 4) ||
12951 !strncasecmp(name, "ICMPV6", 6)) &&
12953 ptype_mapping[i].sw_ptype |=
12954 RTE_PTYPE_INNER_L4_ICMP;
12955 else if (!strncasecmp(name, "GTPC", 4)) {
12956 ptype_mapping[i].sw_ptype |=
12957 RTE_PTYPE_TUNNEL_GTPC;
12959 } else if (!strncasecmp(name, "GTPU", 4)) {
12960 ptype_mapping[i].sw_ptype |=
12961 RTE_PTYPE_TUNNEL_GTPU;
12963 } else if (!strncasecmp(name, "ESP", 3)) {
12964 ptype_mapping[i].sw_ptype |=
12965 RTE_PTYPE_TUNNEL_ESP;
12967 } else if (!strncasecmp(name, "GRENAT", 6)) {
12968 ptype_mapping[i].sw_ptype |=
12969 RTE_PTYPE_TUNNEL_GRENAT;
12971 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12972 !strncasecmp(name, "L2TPV2", 6) ||
12973 !strncasecmp(name, "L2TPV3", 6)) {
12974 ptype_mapping[i].sw_ptype |=
12975 RTE_PTYPE_TUNNEL_L2TP;
12984 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12987 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12989 rte_free(ptype_mapping);
12995 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12996 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12999 uint32_t proto_num;
13000 struct rte_pmd_i40e_proto_info *proto;
13001 uint32_t buff_size;
13005 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
13006 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
13007 PMD_DRV_LOG(ERR, "Unsupported operation.");
13011 /* get information about protocol number */
13012 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13013 (uint8_t *)&proto_num, sizeof(proto_num),
13014 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
13016 PMD_DRV_LOG(ERR, "Failed to get protocol number");
13020 PMD_DRV_LOG(INFO, "No new protocol added");
13024 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
13025 proto = rte_zmalloc("new_proto", buff_size, 0);
13027 PMD_DRV_LOG(ERR, "Failed to allocate memory");
13031 /* get information about protocol list */
13032 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13033 (uint8_t *)proto, buff_size,
13034 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13036 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13041 /* Check if GTP is supported. */
13042 for (i = 0; i < proto_num; i++) {
13043 if (!strncmp(proto[i].name, "GTP", 3)) {
13044 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13045 pf->gtp_support = true;
13047 pf->gtp_support = false;
13052 /* Check if ESP is supported. */
13053 for (i = 0; i < proto_num; i++) {
13054 if (!strncmp(proto[i].name, "ESP", 3)) {
13055 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13056 pf->esp_support = true;
13058 pf->esp_support = false;
13063 /* Update customized pctype info */
13064 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13065 proto_num, proto, op);
13067 PMD_DRV_LOG(INFO, "No pctype is updated.");
13069 /* Update customized ptype info */
13070 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13071 proto_num, proto, op);
13073 PMD_DRV_LOG(INFO, "No ptype is updated.");
13078 /* Create a QinQ cloud filter
13080 * The Fortville NIC has limited resources for tunnel filters,
13081 * so we can only reuse existing filters.
13083 * In step 1 we define which Field Vector fields can be used for
13085 * As we do not have the inner tag defined as a field,
13086 * we have to define it first, by reusing one of L1 entries.
13088 * In step 2 we are replacing one of existing filter types with
13089 * a new one for QinQ.
13090 * As we reusing L1 and replacing L2, some of the default filter
13091 * types will disappear,which depends on L1 and L2 entries we reuse.
13093 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13095 * 1. Create L1 filter of outer vlan (12b) which will be in use
13096 * later when we define the cloud filter.
13097 * a. Valid_flags.replace_cloud = 0
13098 * b. Old_filter = 10 (Stag_Inner_Vlan)
13099 * c. New_filter = 0x10
13100 * d. TR bit = 0xff (optional, not used here)
13101 * e. Buffer – 2 entries:
13102 * i. Byte 0 = 8 (outer vlan FV index).
13104 * Byte 2-3 = 0x0fff
13105 * ii. Byte 0 = 37 (inner vlan FV index).
13107 * Byte 2-3 = 0x0fff
13110 * 2. Create cloud filter using two L1 filters entries: stag and
13111 * new filter(outer vlan+ inner vlan)
13112 * a. Valid_flags.replace_cloud = 1
13113 * b. Old_filter = 1 (instead of outer IP)
13114 * c. New_filter = 0x10
13115 * d. Buffer – 2 entries:
13116 * i. Byte 0 = 0x80 | 7 (valid | Stag).
13117 * Byte 1-3 = 0 (rsv)
13118 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13119 * Byte 9-11 = 0 (rsv)
13122 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13124 int ret = -ENOTSUP;
13125 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
13126 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
13127 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13128 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13130 if (pf->support_multi_driver) {
13131 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13136 memset(&filter_replace, 0,
13137 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13138 memset(&filter_replace_buf, 0,
13139 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13141 /* create L1 filter */
13142 filter_replace.old_filter_type =
13143 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13144 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13145 filter_replace.tr_bit = 0;
13147 /* Prepare the buffer, 2 entries */
13148 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13149 filter_replace_buf.data[0] |=
13150 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13151 /* Field Vector 12b mask */
13152 filter_replace_buf.data[2] = 0xff;
13153 filter_replace_buf.data[3] = 0x0f;
13154 filter_replace_buf.data[4] =
13155 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13156 filter_replace_buf.data[4] |=
13157 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13158 /* Field Vector 12b mask */
13159 filter_replace_buf.data[6] = 0xff;
13160 filter_replace_buf.data[7] = 0x0f;
13161 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13162 &filter_replace_buf);
13163 if (ret != I40E_SUCCESS)
13166 if (filter_replace.old_filter_type !=
13167 filter_replace.new_filter_type)
13168 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13169 " original: 0x%x, new: 0x%x",
13171 filter_replace.old_filter_type,
13172 filter_replace.new_filter_type);
13174 /* Apply the second L2 cloud filter */
13175 memset(&filter_replace, 0,
13176 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13177 memset(&filter_replace_buf, 0,
13178 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13180 /* create L2 filter, input for L2 filter will be L1 filter */
13181 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13182 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13183 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13185 /* Prepare the buffer, 2 entries */
13186 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13187 filter_replace_buf.data[0] |=
13188 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13189 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13190 filter_replace_buf.data[4] |=
13191 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13192 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13193 &filter_replace_buf);
13194 if (!ret && (filter_replace.old_filter_type !=
13195 filter_replace.new_filter_type))
13196 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13197 " original: 0x%x, new: 0x%x",
13199 filter_replace.old_filter_type,
13200 filter_replace.new_filter_type);
13206 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13207 const struct rte_flow_action_rss *in)
13209 if (in->key_len > RTE_DIM(out->key) ||
13210 in->queue_num > RTE_DIM(out->queue))
13212 if (!in->key && in->key_len)
13214 out->conf = (struct rte_flow_action_rss){
13216 .level = in->level,
13217 .types = in->types,
13218 .key_len = in->key_len,
13219 .queue_num = in->queue_num,
13220 .queue = memcpy(out->queue, in->queue,
13221 sizeof(*in->queue) * in->queue_num),
13224 out->conf.key = memcpy(out->key, in->key, in->key_len);
13228 /* Write HENA register to enable hash */
13230 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13232 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13233 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13237 ret = i40e_set_rss_key(pf->main_vsi, key,
13238 rss_conf->conf.key_len);
13242 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13243 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13244 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13245 I40E_WRITE_FLUSH(hw);
13250 /* Configure hash input set */
13252 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13254 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13255 struct rte_eth_input_set_conf conf;
13260 static const struct {
13262 enum rte_eth_input_set_field field;
13263 } inset_match_table[] = {
13264 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13265 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13266 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13267 RTE_ETH_INPUT_SET_L3_DST_IP4},
13268 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13269 RTE_ETH_INPUT_SET_UNKNOWN},
13270 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13271 RTE_ETH_INPUT_SET_UNKNOWN},
13273 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13274 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13275 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13276 RTE_ETH_INPUT_SET_L3_DST_IP4},
13277 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13278 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13279 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13280 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13282 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13283 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13284 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13285 RTE_ETH_INPUT_SET_L3_DST_IP4},
13286 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13287 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13288 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13289 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13291 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13292 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13293 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13294 RTE_ETH_INPUT_SET_L3_DST_IP4},
13295 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13296 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13297 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13298 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13300 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13301 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13302 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13303 RTE_ETH_INPUT_SET_L3_DST_IP4},
13304 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13305 RTE_ETH_INPUT_SET_UNKNOWN},
13306 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13307 RTE_ETH_INPUT_SET_UNKNOWN},
13309 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13310 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13311 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13312 RTE_ETH_INPUT_SET_L3_DST_IP6},
13313 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13314 RTE_ETH_INPUT_SET_UNKNOWN},
13315 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13316 RTE_ETH_INPUT_SET_UNKNOWN},
13318 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13319 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13320 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13321 RTE_ETH_INPUT_SET_L3_DST_IP6},
13322 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13323 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13324 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13325 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13327 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13328 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13329 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13330 RTE_ETH_INPUT_SET_L3_DST_IP6},
13331 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13332 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13333 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13334 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13336 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13337 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13338 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13339 RTE_ETH_INPUT_SET_L3_DST_IP6},
13340 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13341 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13342 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13343 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13345 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13346 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13347 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13348 RTE_ETH_INPUT_SET_L3_DST_IP6},
13349 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13350 RTE_ETH_INPUT_SET_UNKNOWN},
13351 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13352 RTE_ETH_INPUT_SET_UNKNOWN},
13355 mask0 = types & pf->adapter->flow_types_mask;
13356 conf.op = RTE_ETH_INPUT_SET_SELECT;
13357 conf.inset_size = 0;
13358 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13359 if (mask0 & (1ULL << i)) {
13360 conf.flow_type = i;
13365 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13366 if ((types & inset_match_table[j].type) ==
13367 inset_match_table[j].type) {
13368 if (inset_match_table[j].field ==
13369 RTE_ETH_INPUT_SET_UNKNOWN)
13372 conf.field[conf.inset_size] =
13373 inset_match_table[j].field;
13378 if (conf.inset_size) {
13379 ret = i40e_hash_filter_inset_select(hw, &conf);
13387 /* Look up the conflicted rule then mark it as invalid */
13389 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13390 struct i40e_rte_flow_rss_conf *conf)
13392 struct i40e_rss_filter *rss_item;
13393 uint64_t rss_inset;
13395 /* Clear input set bits before comparing the pctype */
13396 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13397 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13399 /* Look up the conflicted rule then mark it as invalid */
13400 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13401 if (!rss_item->rss_filter_info.valid)
13404 if (conf->conf.queue_num &&
13405 rss_item->rss_filter_info.conf.queue_num)
13406 rss_item->rss_filter_info.valid = false;
13408 if (conf->conf.types &&
13409 (rss_item->rss_filter_info.conf.types &
13411 (conf->conf.types & rss_inset))
13412 rss_item->rss_filter_info.valid = false;
13414 if (conf->conf.func ==
13415 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13416 rss_item->rss_filter_info.conf.func ==
13417 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13418 rss_item->rss_filter_info.valid = false;
13422 /* Configure RSS hash function */
13424 i40e_rss_config_hash_function(struct i40e_pf *pf,
13425 struct i40e_rte_flow_rss_conf *conf)
13427 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13432 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13433 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13434 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13435 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13436 I40E_WRITE_FLUSH(hw);
13437 i40e_rss_mark_invalid_rule(pf, conf);
13441 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13443 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13444 I40E_WRITE_FLUSH(hw);
13445 i40e_rss_mark_invalid_rule(pf, conf);
13446 } else if (conf->conf.func ==
13447 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13448 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13450 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13451 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13452 if (mask0 & (1UL << i))
13456 if (i == UINT64_BIT)
13459 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13460 j < I40E_FILTER_PCTYPE_MAX; j++) {
13461 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13462 i40e_write_global_rx_ctl(hw,
13464 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13471 /* Enable RSS according to the configuration */
13473 i40e_rss_enable_hash(struct i40e_pf *pf,
13474 struct i40e_rte_flow_rss_conf *conf)
13476 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13477 struct i40e_rte_flow_rss_conf rss_conf;
13479 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13482 memset(&rss_conf, 0, sizeof(rss_conf));
13483 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13485 /* Configure hash input set */
13486 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13489 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13490 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13491 /* Random default keys */
13492 static uint32_t rss_key_default[] = {0x6b793944,
13493 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13494 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13495 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13497 rss_conf.conf.key = (uint8_t *)rss_key_default;
13498 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13501 "No valid RSS key config for i40e, using default\n");
13504 rss_conf.conf.types |= rss_info->conf.types;
13505 i40e_rss_hash_set(pf, &rss_conf);
13507 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13508 i40e_rss_config_hash_function(pf, conf);
13510 i40e_rss_mark_invalid_rule(pf, conf);
13515 /* Configure RSS queue region */
13517 i40e_rss_config_queue_region(struct i40e_pf *pf,
13518 struct i40e_rte_flow_rss_conf *conf)
13520 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13525 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13526 * It's necessary to calculate the actual PF queues that are configured.
13528 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13529 num = i40e_pf_calc_configured_queues_num(pf);
13531 num = pf->dev_data->nb_rx_queues;
13533 num = RTE_MIN(num, conf->conf.queue_num);
13534 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13539 "No PF queues are configured to enable RSS for port %u",
13540 pf->dev_data->port_id);
13544 /* Fill in redirection table */
13545 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13548 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13549 hw->func_caps.rss_table_entry_width) - 1));
13551 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13554 i40e_rss_mark_invalid_rule(pf, conf);
13559 /* Configure RSS hash function to default */
13561 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13562 struct i40e_rte_flow_rss_conf *conf)
13564 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13569 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13570 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13571 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13573 "Hash function already set to Toeplitz");
13574 I40E_WRITE_FLUSH(hw);
13578 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13580 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13581 I40E_WRITE_FLUSH(hw);
13582 } else if (conf->conf.func ==
13583 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13584 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13586 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13587 if (mask0 & (1UL << i))
13591 if (i == UINT64_BIT)
13594 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13595 j < I40E_FILTER_PCTYPE_MAX; j++) {
13596 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13597 i40e_write_global_rx_ctl(hw,
13606 /* Disable RSS hash and configure default input set */
13608 i40e_rss_disable_hash(struct i40e_pf *pf,
13609 struct i40e_rte_flow_rss_conf *conf)
13611 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13612 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13613 struct i40e_rte_flow_rss_conf rss_conf;
13616 memset(&rss_conf, 0, sizeof(rss_conf));
13617 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13619 /* Disable RSS hash */
13620 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13621 i40e_rss_hash_set(pf, &rss_conf);
13623 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13624 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13625 !(conf->conf.types & (1ULL << i)))
13628 /* Configure default input set */
13629 struct rte_eth_input_set_conf input_conf = {
13630 .op = RTE_ETH_INPUT_SET_SELECT,
13634 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13635 i40e_hash_filter_inset_select(hw, &input_conf);
13638 rss_info->conf.types = rss_conf.conf.types;
13640 i40e_rss_clear_hash_function(pf, conf);
13645 /* Configure RSS queue region to default */
13647 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13649 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13650 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13651 uint16_t queue[I40E_MAX_Q_PER_TC];
13652 uint32_t num_rxq, i;
13656 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13658 for (j = 0; j < num_rxq; j++)
13661 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13662 * It's necessary to calculate the actual PF queues that are configured.
13664 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13665 num = i40e_pf_calc_configured_queues_num(pf);
13667 num = pf->dev_data->nb_rx_queues;
13669 num = RTE_MIN(num, num_rxq);
13670 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13675 "No PF queues are configured to enable RSS for port %u",
13676 pf->dev_data->port_id);
13680 /* Fill in redirection table */
13681 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13684 lut = (lut << 8) | (queue[j] & ((0x1 <<
13685 hw->func_caps.rss_table_entry_width) - 1));
13687 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13690 rss_info->conf.queue_num = 0;
13691 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13697 i40e_config_rss_filter(struct i40e_pf *pf,
13698 struct i40e_rte_flow_rss_conf *conf, bool add)
13700 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13701 struct rte_flow_action_rss update_conf = rss_info->conf;
13705 if (conf->conf.queue_num) {
13706 /* Configure RSS queue region */
13707 ret = i40e_rss_config_queue_region(pf, conf);
13711 update_conf.queue_num = conf->conf.queue_num;
13712 update_conf.queue = conf->conf.queue;
13713 } else if (conf->conf.func ==
13714 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13715 /* Configure hash function */
13716 ret = i40e_rss_config_hash_function(pf, conf);
13720 update_conf.func = conf->conf.func;
13722 /* Configure hash enable and input set */
13723 ret = i40e_rss_enable_hash(pf, conf);
13727 update_conf.types |= conf->conf.types;
13728 update_conf.key = conf->conf.key;
13729 update_conf.key_len = conf->conf.key_len;
13732 /* Update RSS info in pf */
13733 if (i40e_rss_conf_init(rss_info, &update_conf))
13739 if (conf->conf.queue_num)
13740 i40e_rss_clear_queue_region(pf);
13741 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13742 i40e_rss_clear_hash_function(pf, conf);
13744 i40e_rss_disable_hash(pf, conf);
13750 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13751 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13752 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13753 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13755 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13756 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13758 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13759 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13762 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13763 ETH_I40E_FLOATING_VEB_ARG "=1"
13764 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13765 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13766 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13767 ETH_I40E_USE_LATEST_VEC "=0|1");