drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 458 #include "rte_pci_dev_ids.h"
 459 { .vendor_id = 0, /* sentinel */ },
 460 };
 461
 462 static const struct eth_dev_ops i40e_eth_dev_ops = {
 463         .dev_configure                = i40e_dev_configure,
 464         .dev_start                    = i40e_dev_start,
 465         .dev_stop                     = i40e_dev_stop,
 466         .dev_close                    = i40e_dev_close,
 467         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 468         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 469         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 470         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 471         .dev_set_link_up              = i40e_dev_set_link_up,
 472         .dev_set_link_down            = i40e_dev_set_link_down,
 473         .link_update                  = i40e_dev_link_update,
 474         .stats_get                    = i40e_dev_stats_get,
 475         .xstats_get                   = i40e_dev_xstats_get,
 476         .xstats_get_names             = i40e_dev_xstats_get_names,
 477         .stats_reset                  = i40e_dev_stats_reset,
 478         .xstats_reset                 = i40e_dev_stats_reset,
 479         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 480         .dev_infos_get                = i40e_dev_info_get,
 481         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 482         .vlan_filter_set              = i40e_vlan_filter_set,
 483         .vlan_tpid_set                = i40e_vlan_tpid_set,
 484         .vlan_offload_set             = i40e_vlan_offload_set,
 485         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 486         .vlan_pvid_set                = i40e_vlan_pvid_set,
 487         .rx_queue_start               = i40e_dev_rx_queue_start,
 488         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 489         .tx_queue_start               = i40e_dev_tx_queue_start,
 490         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 491         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 492         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 493         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 494         .rx_queue_release             = i40e_dev_rx_queue_release,
 495         .rx_queue_count               = i40e_dev_rx_queue_count,
 496         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 497         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 498         .tx_queue_release             = i40e_dev_tx_queue_release,
 499         .dev_led_on                   = i40e_dev_led_on,
 500         .dev_led_off                  = i40e_dev_led_off,
 501         .flow_ctrl_get                = i40e_flow_ctrl_get,
 502         .flow_ctrl_set                = i40e_flow_ctrl_set,
 503         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 504         .mac_addr_add                 = i40e_macaddr_add,
 505         .mac_addr_remove              = i40e_macaddr_remove,
 506         .reta_update                  = i40e_dev_rss_reta_update,
 507         .reta_query                   = i40e_dev_rss_reta_query,
 508         .rss_hash_update              = i40e_dev_rss_hash_update,
 509         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 510         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 511         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 512         .filter_ctrl                  = i40e_dev_filter_ctrl,
 513         .rxq_info_get                 = i40e_rxq_info_get,
 514         .txq_info_get                 = i40e_txq_info_get,
 515         .mirror_rule_set              = i40e_mirror_rule_set,
 516         .mirror_rule_reset            = i40e_mirror_rule_reset,
 517         .timesync_enable              = i40e_timesync_enable,
 518         .timesync_disable             = i40e_timesync_disable,
 519         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 520         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 521         .get_dcb_info                 = i40e_dev_get_dcb_info,
 522         .timesync_adjust_time         = i40e_timesync_adjust_time,
 523         .timesync_read_time           = i40e_timesync_read_time,
 524         .timesync_write_time          = i40e_timesync_write_time,
 525         .get_reg                      = i40e_get_regs,
 526         .get_eeprom_length            = i40e_get_eeprom_length,
 527         .get_eeprom                   = i40e_get_eeprom,
 528         .mac_addr_set                 = i40e_set_default_mac_addr,
 529         .mtu_set                      = i40e_dev_mtu_set,
 530 };
 531
 532 /* store statistics names and its offset in stats structure */
 533 struct rte_i40e_xstats_name_off {
 534         char name[RTE_ETH_XSTATS_NAME_SIZE];
 535         unsigned offset;
 536 };
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 539         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 540         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 541         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 542         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 543         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 544                 rx_unknown_protocol)},
 545         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 546         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 547         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 548         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 549 };
 550
 551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 552                 sizeof(rte_i40e_stats_strings[0]))
 553
 554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 555         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 556                 tx_dropped_link_down)},
 557         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 558         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 559                 illegal_bytes)},
 560         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 561         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_local_faults)},
 563         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 564                 mac_remote_faults)},
 565         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 566                 rx_length_errors)},
 567         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 568         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 569         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 570         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 571         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 572         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_127)},
 574         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_255)},
 576         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_511)},
 578         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1023)},
 580         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_1522)},
 582         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 583                 rx_size_big)},
 584         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_undersize)},
 586         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 587                 rx_oversize)},
 588         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 589                 mac_short_packet_dropped)},
 590         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 591                 rx_fragments)},
 592         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 593         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 594         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_127)},
 596         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_255)},
 598         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_511)},
 600         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1023)},
 602         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_1522)},
 604         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 605                 tx_size_big)},
 606         {"rx_flow_director_atr_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 608         {"rx_flow_director_sb_match_packets",
 609                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 610         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 tx_lpi_status)},
 612         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 613                 rx_lpi_status)},
 614         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 tx_lpi_count)},
 616         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 617                 rx_lpi_count)},
 618 };
 619
 620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 621                 sizeof(rte_i40e_hw_port_strings[0]))
 622
 623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 624         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_rx)},
 626         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xoff_rx)},
 628 };
 629
 630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 631                 sizeof(rte_i40e_rxq_prio_strings[0]))
 632
 633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 634         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xon_tx)},
 636         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xoff_tx)},
 638         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 639                 priority_xon_2_xoff)},
 640 };
 641
 642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 643                 sizeof(rte_i40e_txq_prio_strings[0]))
 644
 645 static struct eth_driver rte_i40e_pmd = {
 646         .pci_drv = {
 647                 .name = "rte_i40e_pmd",
 648                 .id_table = pci_id_i40e_map,
 649                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 650                         RTE_PCI_DRV_DETACHABLE,
 651         },
 652         .eth_dev_init = eth_i40e_dev_init,
 653         .eth_dev_uninit = eth_i40e_dev_uninit,
 654         .dev_private_size = sizeof(struct i40e_adapter),
 655 };
 656
 657 static inline int
 658 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 659                                      struct rte_eth_link *link)
 660 {
 661         struct rte_eth_link *dst = link;
 662         struct rte_eth_link *src = &(dev->data->dev_link);
 663
 664         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 665                                         *(uint64_t *)src) == 0)
 666                 return -1;
 667
 668         return 0;
 669 }
 670
 671 static inline int
 672 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 673                                       struct rte_eth_link *link)
 674 {
 675         struct rte_eth_link *dst = &(dev->data->dev_link);
 676         struct rte_eth_link *src = link;
 677
 678         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 679                                         *(uint64_t *)src) == 0)
 680                 return -1;
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * Driver initialization routine.
 687  * Invoked once at EAL init time.
 688  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 689  */
 690 static int
 691 rte_i40e_pmd_init(const char *name __rte_unused,
 692                   const char *params __rte_unused)
 693 {
 694         PMD_INIT_FUNC_TRACE();
 695         rte_eth_driver_register(&rte_i40e_pmd);
 696
 697         return 0;
 698 }
 699
 700 static struct rte_driver rte_i40e_driver = {
 701         .type = PMD_PDEV,
 702         .init = rte_i40e_pmd_init,
 703 };
 704
 705 PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
 706 DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
 707
 708 /*
 709  * Initialize registers for flexible payload, which should be set by NVM.
 710  * This should be removed from code once it is fixed in NVM.
 711  */
 712 #ifndef I40E_GLQF_ORT
 713 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 714 #endif
 715 #ifndef I40E_GLQF_PIT
 716 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 717 #endif
 718
 719 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 720 {
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731
 732         /* GLQF_PIT Registers */
 733         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 734         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 735 }
 736
 737 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 738
 739 /*
 740  * Add a ethertype filter to drop all flow control frames transmitted
 741  * from VSIs.
 742 */
 743 static void
 744 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 745 {
 746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 747         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 748                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 749                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 750         int ret;
 751
 752         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 753                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 754                                 pf->main_vsi_seid, 0,
 755                                 TRUE, NULL, NULL);
 756         if (ret)
 757                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 758                                   " frames from VSIs.");
 759 }
 760
 761 static int
 762 floating_veb_list_handler(__rte_unused const char *key,
 763                           const char *floating_veb_value,
 764                           void *opaque)
 765 {
 766         int idx = 0;
 767         unsigned int count = 0;
 768         char *end = NULL;
 769         int min, max;
 770         bool *vf_floating_veb = opaque;
 771
 772         while (isblank(*floating_veb_value))
 773                 floating_veb_value++;
 774
 775         /* Reset floating VEB configuration for VFs */
 776         for (idx = 0; idx < I40E_MAX_VF; idx++)
 777                 vf_floating_veb[idx] = false;
 778
 779         min = I40E_MAX_VF;
 780         do {
 781                 while (isblank(*floating_veb_value))
 782                         floating_veb_value++;
 783                 if (*floating_veb_value == '\0')
 784                         return -1;
 785                 errno = 0;
 786                 idx = strtoul(floating_veb_value, &end, 10);
 787                 if (errno || end == NULL)
 788                         return -1;
 789                 while (isblank(*end))
 790                         end++;
 791                 if (*end == '-') {
 792                         min = idx;
 793                 } else if ((*end == ';') || (*end == '\0')) {
 794                         max = idx;
 795                         if (min == I40E_MAX_VF)
 796                                 min = idx;
 797                         if (max >= I40E_MAX_VF)
 798                                 max = I40E_MAX_VF - 1;
 799                         for (idx = min; idx <= max; idx++) {
 800                                 vf_floating_veb[idx] = true;
 801                                 count++;
 802                         }
 803                         min = I40E_MAX_VF;
 804                 } else {
 805                         return -1;
 806                 }
 807                 floating_veb_value = end + 1;
 808         } while (*end != '\0');
 809
 810         if (count == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static void
 817 config_vf_floating_veb(struct rte_devargs *devargs,
 818                        uint16_t floating_veb,
 819                        bool *vf_floating_veb)
 820 {
 821         struct rte_kvargs *kvlist;
 822         int i;
 823         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 824
 825         if (!floating_veb)
 826                 return;
 827         /* All the VFs attach to the floating VEB by default
 828          * when the floating VEB is enabled.
 829          */
 830         for (i = 0; i < I40E_MAX_VF; i++)
 831                 vf_floating_veb[i] = true;
 832
 833         if (devargs == NULL)
 834                 return;
 835
 836         kvlist = rte_kvargs_parse(devargs->args, NULL);
 837         if (kvlist == NULL)
 838                 return;
 839
 840         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 841                 rte_kvargs_free(kvlist);
 842                 return;
 843         }
 844         /* When the floating_veb_list parameter exists, all the VFs
 845          * will attach to the legacy VEB firstly, then configure VFs
 846          * to the floating VEB according to the floating_veb_list.
 847          */
 848         if (rte_kvargs_process(kvlist, floating_veb_list,
 849                                floating_veb_list_handler,
 850                                vf_floating_veb) < 0) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         rte_kvargs_free(kvlist);
 855 }
 856
 857 static int
 858 i40e_check_floating_handler(__rte_unused const char *key,
 859                             const char *value,
 860                             __rte_unused void *opaque)
 861 {
 862         if (strcmp(value, "1"))
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 static int
 869 is_floating_veb_supported(struct rte_devargs *devargs)
 870 {
 871         struct rte_kvargs *kvlist;
 872         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 873
 874         if (devargs == NULL)
 875                 return 0;
 876
 877         kvlist = rte_kvargs_parse(devargs->args, NULL);
 878         if (kvlist == NULL)
 879                 return 0;
 880
 881         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 882                 rte_kvargs_free(kvlist);
 883                 return 0;
 884         }
 885         /* Floating VEB is enabled when there's key-value:
 886          * enable_floating_veb=1
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_key,
 889                                i40e_check_floating_handler, NULL) < 0) {
 890                 rte_kvargs_free(kvlist);
 891                 return 0;
 892         }
 893         rte_kvargs_free(kvlist);
 894
 895         return 1;
 896 }
 897
 898 static void
 899 config_floating_veb(struct rte_eth_dev *dev)
 900 {
 901         struct rte_pci_device *pci_dev = dev->pci_dev;
 902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 904
 905         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 906
 907         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 908                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 909                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 910                                        pf->floating_veb_list);
 911         } else {
 912                 pf->floating_veb = false;
 913         }
 914 }
 915
 916 static int
 917 eth_i40e_dev_init(struct rte_eth_dev *dev)
 918 {
 919         struct rte_pci_device *pci_dev;
 920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 922         struct i40e_vsi *vsi;
 923         int ret;
 924         uint32_t len;
 925         uint8_t aq_fail = 0;
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         dev->dev_ops = &i40e_eth_dev_ops;
 930         dev->rx_pkt_burst = i40e_recv_pkts;
 931         dev->tx_pkt_burst = i40e_xmit_pkts;
 932
 933         /* for secondary processes, we don't initialise any further as primary
 934          * has already done this work. Only check we don't need a different
 935          * RX function */
 936         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 937                 i40e_set_rx_function(dev);
 938                 i40e_set_tx_function(dev);
 939                 return 0;
 940         }
 941         pci_dev = dev->pci_dev;
 942
 943         rte_eth_copy_pci_info(dev, pci_dev);
 944
 945         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 946         pf->adapter->eth_dev = dev;
 947         pf->dev_data = dev->data;
 948
 949         hw->back = I40E_PF_TO_ADAPTER(pf);
 950         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 951         if (!hw->hw_addr) {
 952                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 953                              "as address is NULL");
 954                 return -ENODEV;
 955         }
 956
 957         hw->vendor_id = pci_dev->id.vendor_id;
 958         hw->device_id = pci_dev->id.device_id;
 959         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 960         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 961         hw->bus.device = pci_dev->addr.devid;
 962         hw->bus.func = pci_dev->addr.function;
 963         hw->adapter_stopped = 0;
 964
 965         /* Make sure all is clean before doing PF reset */
 966         i40e_clear_hw(hw);
 967
 968         /* Initialize the hardware */
 969         i40e_hw_init(dev);
 970
 971         /* Reset here to make sure all is clean for each PF */
 972         ret = i40e_pf_reset(hw);
 973         if (ret) {
 974                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 975                 return ret;
 976         }
 977
 978         /* Initialize the shared code (base driver) */
 979         ret = i40e_init_shared_code(hw);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 982                 return ret;
 983         }
 984
 985         /*
 986          * To work around the NVM issue,initialize registers
 987          * for flexible payload by software.
 988          * It should be removed once issues are fixed in NVM.
 989          */
 990         i40e_flex_payload_reg_init(hw);
 991
 992         /* Initialize the input set for filters (hash and fd) to default value */
 993         i40e_filter_input_set_init(pf);
 994
 995         /* Initialize the parameters for adminq */
 996         i40e_init_adminq_parameter(hw);
 997         ret = i40e_init_adminq(hw);
 998         if (ret != I40E_SUCCESS) {
 999                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1000                 return -EIO;
1001         }
1002         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1003                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1004                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1005                      ((hw->nvm.version >> 12) & 0xf),
1006                      ((hw->nvm.version >> 4) & 0xff),
1007                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1008
1009         /* Need the special FW version to support floating VEB */
1010         config_floating_veb(dev);
1011         /* Clear PXE mode */
1012         i40e_clear_pxe_mode(hw);
1013
1014         /*
1015          * On X710, performance number is far from the expectation on recent
1016          * firmware versions. The fix for this issue may not be integrated in
1017          * the following firmware version. So the workaround in software driver
1018          * is needed. It needs to modify the initial values of 3 internal only
1019          * registers. Note that the workaround can be removed when it is fixed
1020          * in firmware in the future.
1021          */
1022         i40e_configure_registers(hw);
1023
1024         /* Get hw capabilities */
1025         ret = i40e_get_cap(hw);
1026         if (ret != I40E_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1028                 goto err_get_capabilities;
1029         }
1030
1031         /* Initialize parameters for PF */
1032         ret = i40e_pf_parameter_init(dev);
1033         if (ret != 0) {
1034                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1035                 goto err_parameter_init;
1036         }
1037
1038         /* Initialize the queue management */
1039         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1040         if (ret < 0) {
1041                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1042                 goto err_qp_pool_init;
1043         }
1044         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1045                                 hw->func_caps.num_msix_vectors - 1);
1046         if (ret < 0) {
1047                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1048                 goto err_msix_pool_init;
1049         }
1050
1051         /* Initialize lan hmc */
1052         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1053                                 hw->func_caps.num_rx_qp, 0, 0);
1054         if (ret != I40E_SUCCESS) {
1055                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1056                 goto err_init_lan_hmc;
1057         }
1058
1059         /* Configure lan hmc */
1060         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1061         if (ret != I40E_SUCCESS) {
1062                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1063                 goto err_configure_lan_hmc;
1064         }
1065
1066         /* Get and check the mac address */
1067         i40e_get_mac_addr(hw, hw->mac.addr);
1068         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1069                 PMD_INIT_LOG(ERR, "mac address is not valid");
1070                 ret = -EIO;
1071                 goto err_get_mac_addr;
1072         }
1073         /* Copy the permanent MAC address */
1074         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1075                         (struct ether_addr *) hw->mac.perm_addr);
1076
1077         /* Disable flow control */
1078         hw->fc.requested_mode = I40E_FC_NONE;
1079         i40e_set_fc(hw, &aq_fail, TRUE);
1080
1081         /* Set the global registers with default ether type value */
1082         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1083         if (ret != I40E_SUCCESS) {
1084                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1085                              "VLAN ether type");
1086                 goto err_setup_pf_switch;
1087         }
1088
1089         /* PF setup, which includes VSI setup */
1090         ret = i40e_pf_setup(pf);
1091         if (ret) {
1092                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1093                 goto err_setup_pf_switch;
1094         }
1095
1096         /* reset all stats of the device, including pf and main vsi */
1097         i40e_dev_stats_reset(dev);
1098
1099         vsi = pf->main_vsi;
1100
1101         /* Disable double vlan by default */
1102         i40e_vsi_config_double_vlan(vsi, FALSE);
1103
1104         if (!vsi->max_macaddrs)
1105                 len = ETHER_ADDR_LEN;
1106         else
1107                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1108
1109         /* Should be after VSI initialized */
1110         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1111         if (!dev->data->mac_addrs) {
1112                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1113                                         "for storing mac address");
1114                 goto err_mac_alloc;
1115         }
1116         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1117                                         &dev->data->mac_addrs[0]);
1118
1119         /* initialize pf host driver to setup SRIOV resource if applicable */
1120         i40e_pf_host_init(dev);
1121
1122         /* register callback func to eal lib */
1123         rte_intr_callback_register(&(pci_dev->intr_handle),
1124                 i40e_dev_interrupt_handler, (void *)dev);
1125
1126         /* configure and enable device interrupt */
1127         i40e_pf_config_irq0(hw, TRUE);
1128         i40e_pf_enable_irq0(hw);
1129
1130         /* enable uio intr after callback register */
1131         rte_intr_enable(&(pci_dev->intr_handle));
1132         /*
1133          * Add an ethertype filter to drop all flow control frames transmitted
1134          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1135          * frames to wire.
1136          */
1137         i40e_add_tx_flow_control_drop_filter(pf);
1138
1139         /* Set the max frame size to 0x2600 by default,
1140          * in case other drivers changed the default value.
1141          */
1142         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1143
1144         /* initialize mirror rule list */
1145         TAILQ_INIT(&pf->mirror_list);
1146
1147         /* Init dcb to sw mode by default */
1148         ret = i40e_dcb_init_configure(dev, TRUE);
1149         if (ret != I40E_SUCCESS) {
1150                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1151                 pf->flags &= ~I40E_FLAG_DCB;
1152         }
1153
1154         return 0;
1155
1156 err_mac_alloc:
1157         i40e_vsi_release(pf->main_vsi);
1158 err_setup_pf_switch:
1159 err_get_mac_addr:
1160 err_configure_lan_hmc:
1161         (void)i40e_shutdown_lan_hmc(hw);
1162 err_init_lan_hmc:
1163         i40e_res_pool_destroy(&pf->msix_pool);
1164 err_msix_pool_init:
1165         i40e_res_pool_destroy(&pf->qp_pool);
1166 err_qp_pool_init:
1167 err_parameter_init:
1168 err_get_capabilities:
1169         (void)i40e_shutdown_adminq(hw);
1170
1171         return ret;
1172 }
1173
1174 static int
1175 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1176 {
1177         struct rte_pci_device *pci_dev;
1178         struct i40e_hw *hw;
1179         struct i40e_filter_control_settings settings;
1180         int ret;
1181         uint8_t aq_fail = 0;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1186                 return 0;
1187
1188         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189         pci_dev = dev->pci_dev;
1190
1191         if (hw->adapter_stopped == 0)
1192                 i40e_dev_close(dev);
1193
1194         dev->dev_ops = NULL;
1195         dev->rx_pkt_burst = NULL;
1196         dev->tx_pkt_burst = NULL;
1197
1198         /* Disable LLDP */
1199         ret = i40e_aq_stop_lldp(hw, true, NULL);
1200         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1201                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1202
1203         /* Clear PXE mode */
1204         i40e_clear_pxe_mode(hw);
1205
1206         /* Unconfigure filter control */
1207         memset(&settings, 0, sizeof(settings));
1208         ret = i40e_set_filter_control(hw, &settings);
1209         if (ret)
1210                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1211                                         ret);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* uninitialize pf host driver */
1218         i40e_pf_host_uninit(dev);
1219
1220         rte_free(dev->data->mac_addrs);
1221         dev->data->mac_addrs = NULL;
1222
1223         /* disable uio intr before callback unregister */
1224         rte_intr_disable(&(pci_dev->intr_handle));
1225
1226         /* register callback func to eal lib */
1227         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1228                 i40e_dev_interrupt_handler, (void *)dev);
1229
1230         return 0;
1231 }
1232
1233 static int
1234 i40e_dev_configure(struct rte_eth_dev *dev)
1235 {
1236         struct i40e_adapter *ad =
1237                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1239         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1240         int i, ret;
1241
1242         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1243          * bulk allocation or vector Rx preconditions we will reset it.
1244          */
1245         ad->rx_bulk_alloc_allowed = true;
1246         ad->rx_vec_allowed = true;
1247         ad->tx_simple_allowed = true;
1248         ad->tx_vec_allowed = true;
1249
1250         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1251                 ret = i40e_fdir_setup(pf);
1252                 if (ret != I40E_SUCCESS) {
1253                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1254                         return -ENOTSUP;
1255                 }
1256                 ret = i40e_fdir_configure(dev);
1257                 if (ret < 0) {
1258                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1259                         goto err;
1260                 }
1261         } else
1262                 i40e_fdir_teardown(pf);
1263
1264         ret = i40e_dev_init_vlan(dev);
1265         if (ret < 0)
1266                 goto err;
1267
1268         /* VMDQ setup.
1269          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1270          *  RSS setting have different requirements.
1271          *  General PMD driver call sequence are NIC init, configure,
1272          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1273          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1274          *  applicable. So, VMDQ setting has to be done before
1275          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1276          *  For RSS setting, it will try to calculate actual configured RX queue
1277          *  number, which will be available after rx_queue_setup(). dev_start()
1278          *  function is good to place RSS setup.
1279          */
1280         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1281                 ret = i40e_vmdq_setup(dev);
1282                 if (ret)
1283                         goto err;
1284         }
1285
1286         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1287                 ret = i40e_dcb_setup(dev);
1288                 if (ret) {
1289                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1290                         goto err_dcb;
1291                 }
1292         }
1293
1294         return 0;
1295
1296 err_dcb:
1297         /* need to release vmdq resource if exists */
1298         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1299                 i40e_vsi_release(pf->vmdq[i].vsi);
1300                 pf->vmdq[i].vsi = NULL;
1301         }
1302         rte_free(pf->vmdq);
1303         pf->vmdq = NULL;
1304 err:
1305         /* need to release fdir resource if exists */
1306         i40e_fdir_teardown(pf);
1307         return ret;
1308 }
1309
1310 void
1311 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1312 {
1313         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1314         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1315         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1316         uint16_t msix_vect = vsi->msix_intr;
1317         uint16_t i;
1318
1319         for (i = 0; i < vsi->nb_qps; i++) {
1320                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1321                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1322                 rte_wmb();
1323         }
1324
1325         if (vsi->type != I40E_VSI_SRIOV) {
1326                 if (!rte_intr_allow_others(intr_handle)) {
1327                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1328                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1329                         I40E_WRITE_REG(hw,
1330                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1331                                        0);
1332                 } else {
1333                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1334                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1335                         I40E_WRITE_REG(hw,
1336                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1337                                                        msix_vect - 1), 0);
1338                 }
1339         } else {
1340                 uint32_t reg;
1341                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1342                         vsi->user_param + (msix_vect - 1);
1343
1344                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1345                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1346         }
1347         I40E_WRITE_FLUSH(hw);
1348 }
1349
1350 static void
1351 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1352                        int base_queue, int nb_queue)
1353 {
1354         int i;
1355         uint32_t val;
1356         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1357
1358         /* Bind all RX queues to allocated MSIX interrupt */
1359         for (i = 0; i < nb_queue; i++) {
1360                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1361                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1362                         ((base_queue + i + 1) <<
1363                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1364                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1365                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1366
1367                 if (i == nb_queue - 1)
1368                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1369                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1370         }
1371
1372         /* Write first RX queue to Link list register as the head element */
1373         if (vsi->type != I40E_VSI_SRIOV) {
1374                 uint16_t interval =
1375                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1376
1377                 if (msix_vect == I40E_MISC_VEC_ID) {
1378                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1379                                        (base_queue <<
1380                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1381                                        (0x0 <<
1382                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1383                         I40E_WRITE_REG(hw,
1384                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1385                                        interval);
1386                 } else {
1387                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1388                                        (base_queue <<
1389                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1390                                        (0x0 <<
1391                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1392                         I40E_WRITE_REG(hw,
1393                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1394                                                        msix_vect - 1),
1395                                        interval);
1396                 }
1397         } else {
1398                 uint32_t reg;
1399
1400                 if (msix_vect == I40E_MISC_VEC_ID) {
1401                         I40E_WRITE_REG(hw,
1402                                        I40E_VPINT_LNKLST0(vsi->user_param),
1403                                        (base_queue <<
1404                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1405                                        (0x0 <<
1406                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1407                 } else {
1408                         /* num_msix_vectors_vf needs to minus irq0 */
1409                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1410                                 vsi->user_param + (msix_vect - 1);
1411
1412                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1413                                        (base_queue <<
1414                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1415                                        (0x0 <<
1416                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1417                 }
1418         }
1419
1420         I40E_WRITE_FLUSH(hw);
1421 }
1422
1423 void
1424 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1425 {
1426         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1427         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1428         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1429         uint16_t msix_vect = vsi->msix_intr;
1430         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1431         uint16_t queue_idx = 0;
1432         int record = 0;
1433         uint32_t val;
1434         int i;
1435
1436         for (i = 0; i < vsi->nb_qps; i++) {
1437                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1438                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1439         }
1440
1441         /* INTENA flag is not auto-cleared for interrupt */
1442         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1443         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1444                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1445                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1446         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1447
1448         /* VF bind interrupt */
1449         if (vsi->type == I40E_VSI_SRIOV) {
1450                 __vsi_queues_bind_intr(vsi, msix_vect,
1451                                        vsi->base_queue, vsi->nb_qps);
1452                 return;
1453         }
1454
1455         /* PF & VMDq bind interrupt */
1456         if (rte_intr_dp_is_en(intr_handle)) {
1457                 if (vsi->type == I40E_VSI_MAIN) {
1458                         queue_idx = 0;
1459                         record = 1;
1460                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1461                         struct i40e_vsi *main_vsi =
1462                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1463                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1464                         record = 1;
1465                 }
1466         }
1467
1468         for (i = 0; i < vsi->nb_used_qps; i++) {
1469                 if (nb_msix <= 1) {
1470                         if (!rte_intr_allow_others(intr_handle))
1471                                 /* allow to share MISC_VEC_ID */
1472                                 msix_vect = I40E_MISC_VEC_ID;
1473
1474                         /* no enough msix_vect, map all to one */
1475                         __vsi_queues_bind_intr(vsi, msix_vect,
1476                                                vsi->base_queue + i,
1477                                                vsi->nb_used_qps - i);
1478                         for (; !!record && i < vsi->nb_used_qps; i++)
1479                                 intr_handle->intr_vec[queue_idx + i] =
1480                                         msix_vect;
1481                         break;
1482                 }
1483                 /* 1:1 queue/msix_vect mapping */
1484                 __vsi_queues_bind_intr(vsi, msix_vect,
1485                                        vsi->base_queue + i, 1);
1486                 if (!!record)
1487                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1488
1489                 msix_vect++;
1490                 nb_msix--;
1491         }
1492 }
1493
1494 static void
1495 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1496 {
1497         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1498         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1500         uint16_t interval = i40e_calc_itr_interval(\
1501                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1502         uint16_t msix_intr, i;
1503
1504         if (rte_intr_allow_others(intr_handle))
1505                 for (i = 0; i < vsi->nb_msix; i++) {
1506                         msix_intr = vsi->msix_intr + i;
1507                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1508                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1509                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1510                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1511                                 (interval <<
1512                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1513                 }
1514         else
1515                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1516                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1517                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1518                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1519                                (interval <<
1520                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1521
1522         I40E_WRITE_FLUSH(hw);
1523 }
1524
1525 static void
1526 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1530         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1531         uint16_t msix_intr, i;
1532
1533         if (rte_intr_allow_others(intr_handle))
1534                 for (i = 0; i < vsi->nb_msix; i++) {
1535                         msix_intr = vsi->msix_intr + i;
1536                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1537                                        0);
1538                 }
1539         else
1540                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1541
1542         I40E_WRITE_FLUSH(hw);
1543 }
1544
1545 static inline uint8_t
1546 i40e_parse_link_speeds(uint16_t link_speeds)
1547 {
1548         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1549
1550         if (link_speeds & ETH_LINK_SPEED_40G)
1551                 link_speed |= I40E_LINK_SPEED_40GB;
1552         if (link_speeds & ETH_LINK_SPEED_20G)
1553                 link_speed |= I40E_LINK_SPEED_20GB;
1554         if (link_speeds & ETH_LINK_SPEED_10G)
1555                 link_speed |= I40E_LINK_SPEED_10GB;
1556         if (link_speeds & ETH_LINK_SPEED_1G)
1557                 link_speed |= I40E_LINK_SPEED_1GB;
1558         if (link_speeds & ETH_LINK_SPEED_100M)
1559                 link_speed |= I40E_LINK_SPEED_100MB;
1560
1561         return link_speed;
1562 }
1563
1564 static int
1565 i40e_phy_conf_link(struct i40e_hw *hw,
1566                    uint8_t abilities,
1567                    uint8_t force_speed)
1568 {
1569         enum i40e_status_code status;
1570         struct i40e_aq_get_phy_abilities_resp phy_ab;
1571         struct i40e_aq_set_phy_config phy_conf;
1572         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1573                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1574                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1575                         I40E_AQ_PHY_FLAG_LOW_POWER;
1576         const uint8_t advt = I40E_LINK_SPEED_40GB |
1577                         I40E_LINK_SPEED_10GB |
1578                         I40E_LINK_SPEED_1GB |
1579                         I40E_LINK_SPEED_100MB;
1580         int ret = -ENOTSUP;
1581
1582
1583         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1584                                               NULL);
1585         if (status)
1586                 return ret;
1587
1588         memset(&phy_conf, 0, sizeof(phy_conf));
1589
1590         /* bits 0-2 use the values from get_phy_abilities_resp */
1591         abilities &= ~mask;
1592         abilities |= phy_ab.abilities & mask;
1593
1594         /* update ablities and speed */
1595         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1596                 phy_conf.link_speed = advt;
1597         else
1598                 phy_conf.link_speed = force_speed;
1599
1600         phy_conf.abilities = abilities;
1601
1602         /* use get_phy_abilities_resp value for the rest */
1603         phy_conf.phy_type = phy_ab.phy_type;
1604         phy_conf.eee_capability = phy_ab.eee_capability;
1605         phy_conf.eeer = phy_ab.eeer_val;
1606         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1607
1608         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1609                     phy_ab.abilities, phy_ab.link_speed);
1610         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1611                     phy_conf.abilities, phy_conf.link_speed);
1612
1613         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1614         if (status)
1615                 return ret;
1616
1617         return I40E_SUCCESS;
1618 }
1619
1620 static int
1621 i40e_apply_link_speed(struct rte_eth_dev *dev)
1622 {
1623         uint8_t speed;
1624         uint8_t abilities = 0;
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626         struct rte_eth_conf *conf = &dev->data->dev_conf;
1627
1628         speed = i40e_parse_link_speeds(conf->link_speeds);
1629         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1630         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1631                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1632         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1633
1634         /* Skip changing speed on 40G interfaces, FW does not support */
1635         if (i40e_is_40G_device(hw->device_id)) {
1636                 speed =  I40E_LINK_SPEED_UNKNOWN;
1637                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1638         }
1639
1640         return i40e_phy_conf_link(hw, abilities, speed);
1641 }
1642
1643 static int
1644 i40e_dev_start(struct rte_eth_dev *dev)
1645 {
1646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         struct i40e_vsi *main_vsi = pf->main_vsi;
1649         int ret, i;
1650         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1651         uint32_t intr_vector = 0;
1652
1653         hw->adapter_stopped = 0;
1654
1655         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1656                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1657                              dev->data->port_id);
1658                 return -EINVAL;
1659         }
1660
1661         rte_intr_disable(intr_handle);
1662
1663         if ((rte_intr_cap_multiple(intr_handle) ||
1664              !RTE_ETH_DEV_SRIOV(dev).active) &&
1665             dev->data->dev_conf.intr_conf.rxq != 0) {
1666                 intr_vector = dev->data->nb_rx_queues;
1667                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1668                         return -1;
1669         }
1670
1671         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1672                 intr_handle->intr_vec =
1673                         rte_zmalloc("intr_vec",
1674                                     dev->data->nb_rx_queues * sizeof(int),
1675                                     0);
1676                 if (!intr_handle->intr_vec) {
1677                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1678                                      " intr_vec\n", dev->data->nb_rx_queues);
1679                         return -ENOMEM;
1680                 }
1681         }
1682
1683         /* Initialize VSI */
1684         ret = i40e_dev_rxtx_init(pf);
1685         if (ret != I40E_SUCCESS) {
1686                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1687                 goto err_up;
1688         }
1689
1690         /* Map queues with MSIX interrupt */
1691         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1692                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1693         i40e_vsi_queues_bind_intr(main_vsi);
1694         i40e_vsi_enable_queues_intr(main_vsi);
1695
1696         /* Map VMDQ VSI queues with MSIX interrupt */
1697         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1698                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1699                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1700                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1701         }
1702
1703         /* enable FDIR MSIX interrupt */
1704         if (pf->fdir.fdir_vsi) {
1705                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1706                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1707         }
1708
1709         /* Enable all queues which have been configured */
1710         ret = i40e_dev_switch_queues(pf, TRUE);
1711         if (ret != I40E_SUCCESS) {
1712                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1713                 goto err_up;
1714         }
1715
1716         /* Enable receiving broadcast packets */
1717         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1718         if (ret != I40E_SUCCESS)
1719                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1720
1721         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1722                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1723                                                 true, NULL);
1724                 if (ret != I40E_SUCCESS)
1725                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1726         }
1727
1728         /* Apply link configure */
1729         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1730                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1731                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1732                 PMD_DRV_LOG(ERR, "Invalid link setting");
1733                 goto err_up;
1734         }
1735         ret = i40e_apply_link_speed(dev);
1736         if (I40E_SUCCESS != ret) {
1737                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1738                 goto err_up;
1739         }
1740
1741         if (!rte_intr_allow_others(intr_handle)) {
1742                 rte_intr_callback_unregister(intr_handle,
1743                                              i40e_dev_interrupt_handler,
1744                                              (void *)dev);
1745                 /* configure and enable device interrupt */
1746                 i40e_pf_config_irq0(hw, FALSE);
1747                 i40e_pf_enable_irq0(hw);
1748
1749                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1750                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1751                                      " no intr multiplex\n");
1752         }
1753
1754         /* enable uio intr after callback register */
1755         rte_intr_enable(intr_handle);
1756
1757         return I40E_SUCCESS;
1758
1759 err_up:
1760         i40e_dev_switch_queues(pf, FALSE);
1761         i40e_dev_clear_queues(dev);
1762
1763         return ret;
1764 }
1765
1766 static void
1767 i40e_dev_stop(struct rte_eth_dev *dev)
1768 {
1769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1770         struct i40e_vsi *main_vsi = pf->main_vsi;
1771         struct i40e_mirror_rule *p_mirror;
1772         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1773         int i;
1774
1775         /* Disable all queues */
1776         i40e_dev_switch_queues(pf, FALSE);
1777
1778         /* un-map queues with interrupt registers */
1779         i40e_vsi_disable_queues_intr(main_vsi);
1780         i40e_vsi_queues_unbind_intr(main_vsi);
1781
1782         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1783                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1784                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1785         }
1786
1787         if (pf->fdir.fdir_vsi) {
1788                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1789                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1790         }
1791         /* Clear all queues and release memory */
1792         i40e_dev_clear_queues(dev);
1793
1794         /* Set link down */
1795         i40e_dev_set_link_down(dev);
1796
1797         /* Remove all mirror rules */
1798         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1799                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1800                 rte_free(p_mirror);
1801         }
1802         pf->nb_mirror_rule = 0;
1803
1804         if (!rte_intr_allow_others(intr_handle))
1805                 /* resume to the default handler */
1806                 rte_intr_callback_register(intr_handle,
1807                                            i40e_dev_interrupt_handler,
1808                                            (void *)dev);
1809
1810         /* Clean datapath event and queue/vec mapping */
1811         rte_intr_efd_disable(intr_handle);
1812         if (intr_handle->intr_vec) {
1813                 rte_free(intr_handle->intr_vec);
1814                 intr_handle->intr_vec = NULL;
1815         }
1816 }
1817
1818 static void
1819 i40e_dev_close(struct rte_eth_dev *dev)
1820 {
1821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         uint32_t reg;
1824         int i;
1825
1826         PMD_INIT_FUNC_TRACE();
1827
1828         i40e_dev_stop(dev);
1829         hw->adapter_stopped = 1;
1830         i40e_dev_free_queues(dev);
1831
1832         /* Disable interrupt */
1833         i40e_pf_disable_irq0(hw);
1834         rte_intr_disable(&(dev->pci_dev->intr_handle));
1835
1836         /* shutdown and destroy the HMC */
1837         i40e_shutdown_lan_hmc(hw);
1838
1839         /* release all the existing VSIs and VEBs */
1840         i40e_fdir_teardown(pf);
1841         i40e_vsi_release(pf->main_vsi);
1842
1843         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1844                 i40e_vsi_release(pf->vmdq[i].vsi);
1845                 pf->vmdq[i].vsi = NULL;
1846         }
1847
1848         rte_free(pf->vmdq);
1849         pf->vmdq = NULL;
1850
1851         /* shutdown the adminq */
1852         i40e_aq_queue_shutdown(hw, true);
1853         i40e_shutdown_adminq(hw);
1854
1855         i40e_res_pool_destroy(&pf->qp_pool);
1856         i40e_res_pool_destroy(&pf->msix_pool);
1857
1858         /* force a PF reset to clean anything leftover */
1859         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1860         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1861                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1862         I40E_WRITE_FLUSH(hw);
1863 }
1864
1865 static void
1866 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1867 {
1868         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         struct i40e_vsi *vsi = pf->main_vsi;
1871         int status;
1872
1873         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1874                                                      true, NULL, true);
1875         if (status != I40E_SUCCESS)
1876                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1877
1878         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1879                                                         TRUE, NULL);
1880         if (status != I40E_SUCCESS)
1881                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1882
1883 }
1884
1885 static void
1886 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1887 {
1888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         struct i40e_vsi *vsi = pf->main_vsi;
1891         int status;
1892
1893         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1894                                                      false, NULL, true);
1895         if (status != I40E_SUCCESS)
1896                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1897
1898         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1899                                                         false, NULL);
1900         if (status != I40E_SUCCESS)
1901                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1902 }
1903
1904 static void
1905 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int ret;
1911
1912         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1913         if (ret != I40E_SUCCESS)
1914                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1915 }
1916
1917 static void
1918 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1919 {
1920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct i40e_vsi *vsi = pf->main_vsi;
1923         int ret;
1924
1925         if (dev->data->promiscuous == 1)
1926                 return; /* must remain in all_multicast mode */
1927
1928         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1929                                 vsi->seid, FALSE, NULL);
1930         if (ret != I40E_SUCCESS)
1931                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1932 }
1933
1934 /*
1935  * Set device link up.
1936  */
1937 static int
1938 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1939 {
1940         /* re-apply link speed setting */
1941         return i40e_apply_link_speed(dev);
1942 }
1943
1944 /*
1945  * Set device link down.
1946  */
1947 static int
1948 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1949 {
1950         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1951         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953
1954         return i40e_phy_conf_link(hw, abilities, speed);
1955 }
1956
1957 int
1958 i40e_dev_link_update(struct rte_eth_dev *dev,
1959                      int wait_to_complete)
1960 {
1961 #define CHECK_INTERVAL 100  /* 100ms */
1962 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct i40e_link_status link_status;
1965         struct rte_eth_link link, old;
1966         int status;
1967         unsigned rep_cnt = MAX_REPEAT_TIME;
1968
1969         memset(&link, 0, sizeof(link));
1970         memset(&old, 0, sizeof(old));
1971         memset(&link_status, 0, sizeof(link_status));
1972         rte_i40e_dev_atomic_read_link_status(dev, &old);
1973
1974         do {
1975                 /* Get link status information from hardware */
1976                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1977                 if (status != I40E_SUCCESS) {
1978                         link.link_speed = ETH_SPEED_NUM_100M;
1979                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1980                         PMD_DRV_LOG(ERR, "Failed to get link info");
1981                         goto out;
1982                 }
1983
1984                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1985                 if (!wait_to_complete)
1986                         break;
1987
1988                 rte_delay_ms(CHECK_INTERVAL);
1989         } while (!link.link_status && rep_cnt--);
1990
1991         if (!link.link_status)
1992                 goto out;
1993
1994         /* i40e uses full duplex only */
1995         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1996
1997         /* Parse the link status */
1998         switch (link_status.link_speed) {
1999         case I40E_LINK_SPEED_100MB:
2000                 link.link_speed = ETH_SPEED_NUM_100M;
2001                 break;
2002         case I40E_LINK_SPEED_1GB:
2003                 link.link_speed = ETH_SPEED_NUM_1G;
2004                 break;
2005         case I40E_LINK_SPEED_10GB:
2006                 link.link_speed = ETH_SPEED_NUM_10G;
2007                 break;
2008         case I40E_LINK_SPEED_20GB:
2009                 link.link_speed = ETH_SPEED_NUM_20G;
2010                 break;
2011         case I40E_LINK_SPEED_40GB:
2012                 link.link_speed = ETH_SPEED_NUM_40G;
2013                 break;
2014         default:
2015                 link.link_speed = ETH_SPEED_NUM_100M;
2016                 break;
2017         }
2018
2019         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2020                         ETH_LINK_SPEED_FIXED);
2021
2022 out:
2023         rte_i40e_dev_atomic_write_link_status(dev, &link);
2024         if (link.link_status == old.link_status)
2025                 return -1;
2026
2027         return 0;
2028 }
2029
2030 /* Get all the statistics of a VSI */
2031 void
2032 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2033 {
2034         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2035         struct i40e_eth_stats *nes = &vsi->eth_stats;
2036         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2037         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2038
2039         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2040                             vsi->offset_loaded, &oes->rx_bytes,
2041                             &nes->rx_bytes);
2042         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2043                             vsi->offset_loaded, &oes->rx_unicast,
2044                             &nes->rx_unicast);
2045         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2046                             vsi->offset_loaded, &oes->rx_multicast,
2047                             &nes->rx_multicast);
2048         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2049                             vsi->offset_loaded, &oes->rx_broadcast,
2050                             &nes->rx_broadcast);
2051         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2052                             &oes->rx_discards, &nes->rx_discards);
2053         /* GLV_REPC not supported */
2054         /* GLV_RMPC not supported */
2055         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2056                             &oes->rx_unknown_protocol,
2057                             &nes->rx_unknown_protocol);
2058         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2059                             vsi->offset_loaded, &oes->tx_bytes,
2060                             &nes->tx_bytes);
2061         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2062                             vsi->offset_loaded, &oes->tx_unicast,
2063                             &nes->tx_unicast);
2064         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2065                             vsi->offset_loaded, &oes->tx_multicast,
2066                             &nes->tx_multicast);
2067         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2068                             vsi->offset_loaded,  &oes->tx_broadcast,
2069                             &nes->tx_broadcast);
2070         /* GLV_TDPC not supported */
2071         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2072                             &oes->tx_errors, &nes->tx_errors);
2073         vsi->offset_loaded = true;
2074
2075         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2076                     vsi->vsi_id);
2077         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2078         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2079         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2080         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2081         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2082         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2083                     nes->rx_unknown_protocol);
2084         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2085         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2086         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2087         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2088         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2089         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2090         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2091                     vsi->vsi_id);
2092 }
2093
2094 static void
2095 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2096 {
2097         unsigned int i;
2098         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2099         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2100
2101         /* Get statistics of struct i40e_eth_stats */
2102         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2103                             I40E_GLPRT_GORCL(hw->port),
2104                             pf->offset_loaded, &os->eth.rx_bytes,
2105                             &ns->eth.rx_bytes);
2106         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2107                             I40E_GLPRT_UPRCL(hw->port),
2108                             pf->offset_loaded, &os->eth.rx_unicast,
2109                             &ns->eth.rx_unicast);
2110         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2111                             I40E_GLPRT_MPRCL(hw->port),
2112                             pf->offset_loaded, &os->eth.rx_multicast,
2113                             &ns->eth.rx_multicast);
2114         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2115                             I40E_GLPRT_BPRCL(hw->port),
2116                             pf->offset_loaded, &os->eth.rx_broadcast,
2117                             &ns->eth.rx_broadcast);
2118         /* Workaround: CRC size should not be included in byte statistics,
2119          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2120          */
2121         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2122                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2123
2124         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2125                             pf->offset_loaded, &os->eth.rx_discards,
2126                             &ns->eth.rx_discards);
2127         /* GLPRT_REPC not supported */
2128         /* GLPRT_RMPC not supported */
2129         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2130                             pf->offset_loaded,
2131                             &os->eth.rx_unknown_protocol,
2132                             &ns->eth.rx_unknown_protocol);
2133         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2134                             I40E_GLPRT_GOTCL(hw->port),
2135                             pf->offset_loaded, &os->eth.tx_bytes,
2136                             &ns->eth.tx_bytes);
2137         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2138                             I40E_GLPRT_UPTCL(hw->port),
2139                             pf->offset_loaded, &os->eth.tx_unicast,
2140                             &ns->eth.tx_unicast);
2141         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2142                             I40E_GLPRT_MPTCL(hw->port),
2143                             pf->offset_loaded, &os->eth.tx_multicast,
2144                             &ns->eth.tx_multicast);
2145         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2146                             I40E_GLPRT_BPTCL(hw->port),
2147                             pf->offset_loaded, &os->eth.tx_broadcast,
2148                             &ns->eth.tx_broadcast);
2149         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2150                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2151         /* GLPRT_TEPC not supported */
2152
2153         /* additional port specific stats */
2154         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2155                             pf->offset_loaded, &os->tx_dropped_link_down,
2156                             &ns->tx_dropped_link_down);
2157         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2158                             pf->offset_loaded, &os->crc_errors,
2159                             &ns->crc_errors);
2160         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2161                             pf->offset_loaded, &os->illegal_bytes,
2162                             &ns->illegal_bytes);
2163         /* GLPRT_ERRBC not supported */
2164         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2165                             pf->offset_loaded, &os->mac_local_faults,
2166                             &ns->mac_local_faults);
2167         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2168                             pf->offset_loaded, &os->mac_remote_faults,
2169                             &ns->mac_remote_faults);
2170         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2171                             pf->offset_loaded, &os->rx_length_errors,
2172                             &ns->rx_length_errors);
2173         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2174                             pf->offset_loaded, &os->link_xon_rx,
2175                             &ns->link_xon_rx);
2176         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2177                             pf->offset_loaded, &os->link_xoff_rx,
2178                             &ns->link_xoff_rx);
2179         for (i = 0; i < 8; i++) {
2180                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2181                                     pf->offset_loaded,
2182                                     &os->priority_xon_rx[i],
2183                                     &ns->priority_xon_rx[i]);
2184                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2185                                     pf->offset_loaded,
2186                                     &os->priority_xoff_rx[i],
2187                                     &ns->priority_xoff_rx[i]);
2188         }
2189         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2190                             pf->offset_loaded, &os->link_xon_tx,
2191                             &ns->link_xon_tx);
2192         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2193                             pf->offset_loaded, &os->link_xoff_tx,
2194                             &ns->link_xoff_tx);
2195         for (i = 0; i < 8; i++) {
2196                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2197                                     pf->offset_loaded,
2198                                     &os->priority_xon_tx[i],
2199                                     &ns->priority_xon_tx[i]);
2200                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2201                                     pf->offset_loaded,
2202                                     &os->priority_xoff_tx[i],
2203                                     &ns->priority_xoff_tx[i]);
2204                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2205                                     pf->offset_loaded,
2206                                     &os->priority_xon_2_xoff[i],
2207                                     &ns->priority_xon_2_xoff[i]);
2208         }
2209         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2210                             I40E_GLPRT_PRC64L(hw->port),
2211                             pf->offset_loaded, &os->rx_size_64,
2212                             &ns->rx_size_64);
2213         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2214                             I40E_GLPRT_PRC127L(hw->port),
2215                             pf->offset_loaded, &os->rx_size_127,
2216                             &ns->rx_size_127);
2217         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2218                             I40E_GLPRT_PRC255L(hw->port),
2219                             pf->offset_loaded, &os->rx_size_255,
2220                             &ns->rx_size_255);
2221         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2222                             I40E_GLPRT_PRC511L(hw->port),
2223                             pf->offset_loaded, &os->rx_size_511,
2224                             &ns->rx_size_511);
2225         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2226                             I40E_GLPRT_PRC1023L(hw->port),
2227                             pf->offset_loaded, &os->rx_size_1023,
2228                             &ns->rx_size_1023);
2229         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2230                             I40E_GLPRT_PRC1522L(hw->port),
2231                             pf->offset_loaded, &os->rx_size_1522,
2232                             &ns->rx_size_1522);
2233         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2234                             I40E_GLPRT_PRC9522L(hw->port),
2235                             pf->offset_loaded, &os->rx_size_big,
2236                             &ns->rx_size_big);
2237         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2238                             pf->offset_loaded, &os->rx_undersize,
2239                             &ns->rx_undersize);
2240         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2241                             pf->offset_loaded, &os->rx_fragments,
2242                             &ns->rx_fragments);
2243         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2244                             pf->offset_loaded, &os->rx_oversize,
2245                             &ns->rx_oversize);
2246         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2247                             pf->offset_loaded, &os->rx_jabber,
2248                             &ns->rx_jabber);
2249         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2250                             I40E_GLPRT_PTC64L(hw->port),
2251                             pf->offset_loaded, &os->tx_size_64,
2252                             &ns->tx_size_64);
2253         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2254                             I40E_GLPRT_PTC127L(hw->port),
2255                             pf->offset_loaded, &os->tx_size_127,
2256                             &ns->tx_size_127);
2257         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2258                             I40E_GLPRT_PTC255L(hw->port),
2259                             pf->offset_loaded, &os->tx_size_255,
2260                             &ns->tx_size_255);
2261         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2262                             I40E_GLPRT_PTC511L(hw->port),
2263                             pf->offset_loaded, &os->tx_size_511,
2264                             &ns->tx_size_511);
2265         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2266                             I40E_GLPRT_PTC1023L(hw->port),
2267                             pf->offset_loaded, &os->tx_size_1023,
2268                             &ns->tx_size_1023);
2269         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2270                             I40E_GLPRT_PTC1522L(hw->port),
2271                             pf->offset_loaded, &os->tx_size_1522,
2272                             &ns->tx_size_1522);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2274                             I40E_GLPRT_PTC9522L(hw->port),
2275                             pf->offset_loaded, &os->tx_size_big,
2276                             &ns->tx_size_big);
2277         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2278                            pf->offset_loaded,
2279                            &os->fd_sb_match, &ns->fd_sb_match);
2280         /* GLPRT_MSPDC not supported */
2281         /* GLPRT_XEC not supported */
2282
2283         pf->offset_loaded = true;
2284
2285         if (pf->main_vsi)
2286                 i40e_update_vsi_stats(pf->main_vsi);
2287 }
2288
2289 /* Get all statistics of a port */
2290 static void
2291 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2292 {
2293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2296         unsigned i;
2297
2298         /* call read registers - updates values, now write them to struct */
2299         i40e_read_stats_registers(pf, hw);
2300
2301         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2302                         pf->main_vsi->eth_stats.rx_multicast +
2303                         pf->main_vsi->eth_stats.rx_broadcast -
2304                         pf->main_vsi->eth_stats.rx_discards;
2305         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2306                         pf->main_vsi->eth_stats.tx_multicast +
2307                         pf->main_vsi->eth_stats.tx_broadcast;
2308         stats->ibytes   = ns->eth.rx_bytes;
2309         stats->obytes   = ns->eth.tx_bytes;
2310         stats->oerrors  = ns->eth.tx_errors +
2311                         pf->main_vsi->eth_stats.tx_errors;
2312
2313         /* Rx Errors */
2314         stats->imissed  = ns->eth.rx_discards +
2315                         pf->main_vsi->eth_stats.rx_discards;
2316         stats->ierrors  = ns->crc_errors +
2317                         ns->rx_length_errors + ns->rx_undersize +
2318                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2319
2320         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2321         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2322         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2323         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2324         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2325         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2326         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2327                     ns->eth.rx_unknown_protocol);
2328         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2329         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2330         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2331         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2332         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2333         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2334
2335         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2336                     ns->tx_dropped_link_down);
2337         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2338         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2339                     ns->illegal_bytes);
2340         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2341         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2342                     ns->mac_local_faults);
2343         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2344                     ns->mac_remote_faults);
2345         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2346                     ns->rx_length_errors);
2347         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2348         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2349         for (i = 0; i < 8; i++) {
2350                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2351                                 i, ns->priority_xon_rx[i]);
2352                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2353                                 i, ns->priority_xoff_rx[i]);
2354         }
2355         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2356         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2357         for (i = 0; i < 8; i++) {
2358                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2359                                 i, ns->priority_xon_tx[i]);
2360                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2361                                 i, ns->priority_xoff_tx[i]);
2362                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2363                                 i, ns->priority_xon_2_xoff[i]);
2364         }
2365         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2366         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2367         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2368         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2369         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2370         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2371         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2372         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2373         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2374         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2375         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2376         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2377         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2378         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2379         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2380         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2381         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2382         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2383         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2384                         ns->mac_short_packet_dropped);
2385         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2386                     ns->checksum_error);
2387         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2388         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2389 }
2390
2391 /* Reset the statistics */
2392 static void
2393 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2394 {
2395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397
2398         /* Mark PF and VSI stats to update the offset, aka "reset" */
2399         pf->offset_loaded = false;
2400         if (pf->main_vsi)
2401                 pf->main_vsi->offset_loaded = false;
2402
2403         /* read the stats, reading current register values into offset */
2404         i40e_read_stats_registers(pf, hw);
2405 }
2406
2407 static uint32_t
2408 i40e_xstats_calc_num(void)
2409 {
2410         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2411                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2412                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2413 }
2414
2415 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2416                                      struct rte_eth_xstat_name *xstats_names,
2417                                      __rte_unused unsigned limit)
2418 {
2419         unsigned count = 0;
2420         unsigned i, prio;
2421
2422         if (xstats_names == NULL)
2423                 return i40e_xstats_calc_num();
2424
2425         /* Note: limit checked in rte_eth_xstats_names() */
2426
2427         /* Get stats from i40e_eth_stats struct */
2428         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2429                 snprintf(xstats_names[count].name,
2430                          sizeof(xstats_names[count].name),
2431                          "%s", rte_i40e_stats_strings[i].name);
2432                 count++;
2433         }
2434
2435         /* Get individiual stats from i40e_hw_port struct */
2436         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2437                 snprintf(xstats_names[count].name,
2438                         sizeof(xstats_names[count].name),
2439                          "%s", rte_i40e_hw_port_strings[i].name);
2440                 count++;
2441         }
2442
2443         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2444                 for (prio = 0; prio < 8; prio++) {
2445                         snprintf(xstats_names[count].name,
2446                                  sizeof(xstats_names[count].name),
2447                                  "rx_priority%u_%s", prio,
2448                                  rte_i40e_rxq_prio_strings[i].name);
2449                         count++;
2450                 }
2451         }
2452
2453         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2454                 for (prio = 0; prio < 8; prio++) {
2455                         snprintf(xstats_names[count].name,
2456                                  sizeof(xstats_names[count].name),
2457                                  "tx_priority%u_%s", prio,
2458                                  rte_i40e_txq_prio_strings[i].name);
2459                         count++;
2460                 }
2461         }
2462         return count;
2463 }
2464
2465 static int
2466 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2467                     unsigned n)
2468 {
2469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         unsigned i, count, prio;
2472         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2473
2474         count = i40e_xstats_calc_num();
2475         if (n < count)
2476                 return count;
2477
2478         i40e_read_stats_registers(pf, hw);
2479
2480         if (xstats == NULL)
2481                 return 0;
2482
2483         count = 0;
2484
2485         /* Get stats from i40e_eth_stats struct */
2486         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2487                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2488                         rte_i40e_stats_strings[i].offset);
2489                 count++;
2490         }
2491
2492         /* Get individiual stats from i40e_hw_port struct */
2493         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2494                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2495                         rte_i40e_hw_port_strings[i].offset);
2496                 count++;
2497         }
2498
2499         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2500                 for (prio = 0; prio < 8; prio++) {
2501                         xstats[count].value =
2502                                 *(uint64_t *)(((char *)hw_stats) +
2503                                 rte_i40e_rxq_prio_strings[i].offset +
2504                                 (sizeof(uint64_t) * prio));
2505                         count++;
2506                 }
2507         }
2508
2509         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2510                 for (prio = 0; prio < 8; prio++) {
2511                         xstats[count].value =
2512                                 *(uint64_t *)(((char *)hw_stats) +
2513                                 rte_i40e_txq_prio_strings[i].offset +
2514                                 (sizeof(uint64_t) * prio));
2515                         count++;
2516                 }
2517         }
2518
2519         return count;
2520 }
2521
2522 static int
2523 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2524                                  __rte_unused uint16_t queue_id,
2525                                  __rte_unused uint8_t stat_idx,
2526                                  __rte_unused uint8_t is_rx)
2527 {
2528         PMD_INIT_FUNC_TRACE();
2529
2530         return -ENOSYS;
2531 }
2532
2533 static void
2534 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2535 {
2536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct i40e_vsi *vsi = pf->main_vsi;
2539
2540         dev_info->max_rx_queues = vsi->nb_qps;
2541         dev_info->max_tx_queues = vsi->nb_qps;
2542         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2543         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2544         dev_info->max_mac_addrs = vsi->max_macaddrs;
2545         dev_info->max_vfs = dev->pci_dev->max_vfs;
2546         dev_info->rx_offload_capa =
2547                 DEV_RX_OFFLOAD_VLAN_STRIP |
2548                 DEV_RX_OFFLOAD_QINQ_STRIP |
2549                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2550                 DEV_RX_OFFLOAD_UDP_CKSUM |
2551                 DEV_RX_OFFLOAD_TCP_CKSUM;
2552         dev_info->tx_offload_capa =
2553                 DEV_TX_OFFLOAD_VLAN_INSERT |
2554                 DEV_TX_OFFLOAD_QINQ_INSERT |
2555                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2556                 DEV_TX_OFFLOAD_UDP_CKSUM |
2557                 DEV_TX_OFFLOAD_TCP_CKSUM |
2558                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2559                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2560                 DEV_TX_OFFLOAD_TCP_TSO;
2561         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2562                                                 sizeof(uint32_t);
2563         dev_info->reta_size = pf->hash_lut_size;
2564         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2565
2566         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2567                 .rx_thresh = {
2568                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2569                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2570                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2571                 },
2572                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2573                 .rx_drop_en = 0,
2574         };
2575
2576         dev_info->default_txconf = (struct rte_eth_txconf) {
2577                 .tx_thresh = {
2578                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2579                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2580                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2581                 },
2582                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2583                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2584                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2585                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2586         };
2587
2588         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2589                 .nb_max = I40E_MAX_RING_DESC,
2590                 .nb_min = I40E_MIN_RING_DESC,
2591                 .nb_align = I40E_ALIGN_RING_DESC,
2592         };
2593
2594         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2595                 .nb_max = I40E_MAX_RING_DESC,
2596                 .nb_min = I40E_MIN_RING_DESC,
2597                 .nb_align = I40E_ALIGN_RING_DESC,
2598         };
2599
2600         if (pf->flags & I40E_FLAG_VMDQ) {
2601                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2602                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2603                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2604                                                 pf->max_nb_vmdq_vsi;
2605                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2606                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2607                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2608         }
2609
2610         if (i40e_is_40G_device(hw->device_id))
2611                 /* For XL710 */
2612                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2613         else
2614                 /* For X710 */
2615                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2616 }
2617
2618 static int
2619 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2620 {
2621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2622         struct i40e_vsi *vsi = pf->main_vsi;
2623         PMD_INIT_FUNC_TRACE();
2624
2625         if (on)
2626                 return i40e_vsi_add_vlan(vsi, vlan_id);
2627         else
2628                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2629 }
2630
2631 static int
2632 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2633                    enum rte_vlan_type vlan_type,
2634                    uint16_t tpid)
2635 {
2636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637         uint64_t reg_r = 0, reg_w = 0;
2638         uint16_t reg_id = 0;
2639         int ret = 0;
2640         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2641
2642         switch (vlan_type) {
2643         case ETH_VLAN_TYPE_OUTER:
2644                 if (qinq)
2645                         reg_id = 2;
2646                 else
2647                         reg_id = 3;
2648                 break;
2649         case ETH_VLAN_TYPE_INNER:
2650                 if (qinq)
2651                         reg_id = 3;
2652                 else {
2653                         ret = -EINVAL;
2654                         PMD_DRV_LOG(ERR,
2655                                 "Unsupported vlan type in single vlan.\n");
2656                         return ret;
2657                 }
2658                 break;
2659         default:
2660                 ret = -EINVAL;
2661                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2662                 return ret;
2663         }
2664         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2665                                           &reg_r, NULL);
2666         if (ret != I40E_SUCCESS) {
2667                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2668                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2669                 ret = -EIO;
2670                 return ret;
2671         }
2672         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2673                     "0x%08"PRIx64"", reg_id, reg_r);
2674
2675         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2676         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2677         if (reg_r == reg_w) {
2678                 ret = 0;
2679                 PMD_DRV_LOG(DEBUG, "No need to write");
2680                 return ret;
2681         }
2682
2683         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2684                                            reg_w, NULL);
2685         if (ret != I40E_SUCCESS) {
2686                 ret = -EIO;
2687                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2688                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2689                 return ret;
2690         }
2691         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2692                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2693
2694         return ret;
2695 }
2696
2697 static void
2698 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2699 {
2700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701         struct i40e_vsi *vsi = pf->main_vsi;
2702         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703
2704         if (mask & ETH_VLAN_FILTER_MASK) {
2705                 if (dev->data->dev_conf.rxmode.hw_vlan_filter) {
2706                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, false, NULL);
2707                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2708                 } else {
2709                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, true, NULL);
2710                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2711                 }
2712         }
2713
2714         if (mask & ETH_VLAN_STRIP_MASK) {
2715                 /* Enable or disable VLAN stripping */
2716                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2717                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2718                 else
2719                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2720         }
2721
2722         if (mask & ETH_VLAN_EXTEND_MASK) {
2723                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2724                         i40e_vsi_config_double_vlan(vsi, TRUE);
2725                         /* Set global registers with default ether type value */
2726                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2727                                            ETHER_TYPE_VLAN);
2728                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2729                                            ETHER_TYPE_VLAN);
2730                 }
2731                 else
2732                         i40e_vsi_config_double_vlan(vsi, FALSE);
2733         }
2734 }
2735
2736 static void
2737 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2738                           __rte_unused uint16_t queue,
2739                           __rte_unused int on)
2740 {
2741         PMD_INIT_FUNC_TRACE();
2742 }
2743
2744 static int
2745 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2746 {
2747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2748         struct i40e_vsi *vsi = pf->main_vsi;
2749         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2750         struct i40e_vsi_vlan_pvid_info info;
2751
2752         memset(&info, 0, sizeof(info));
2753         info.on = on;
2754         if (info.on)
2755                 info.config.pvid = pvid;
2756         else {
2757                 info.config.reject.tagged =
2758                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2759                 info.config.reject.untagged =
2760                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2761         }
2762
2763         return i40e_vsi_vlan_pvid_set(vsi, &info);
2764 }
2765
2766 static int
2767 i40e_dev_led_on(struct rte_eth_dev *dev)
2768 {
2769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         uint32_t mode = i40e_led_get(hw);
2771
2772         if (mode == 0)
2773                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2774
2775         return 0;
2776 }
2777
2778 static int
2779 i40e_dev_led_off(struct rte_eth_dev *dev)
2780 {
2781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         uint32_t mode = i40e_led_get(hw);
2783
2784         if (mode != 0)
2785                 i40e_led_set(hw, 0, false);
2786
2787         return 0;
2788 }
2789
2790 static int
2791 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2792 {
2793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2795
2796         fc_conf->pause_time = pf->fc_conf.pause_time;
2797         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2798         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2799
2800          /* Return current mode according to actual setting*/
2801         switch (hw->fc.current_mode) {
2802         case I40E_FC_FULL:
2803                 fc_conf->mode = RTE_FC_FULL;
2804                 break;
2805         case I40E_FC_TX_PAUSE:
2806                 fc_conf->mode = RTE_FC_TX_PAUSE;
2807                 break;
2808         case I40E_FC_RX_PAUSE:
2809                 fc_conf->mode = RTE_FC_RX_PAUSE;
2810                 break;
2811         case I40E_FC_NONE:
2812         default:
2813                 fc_conf->mode = RTE_FC_NONE;
2814         };
2815
2816         return 0;
2817 }
2818
2819 static int
2820 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2821 {
2822         uint32_t mflcn_reg, fctrl_reg, reg;
2823         uint32_t max_high_water;
2824         uint8_t i, aq_failure;
2825         int err;
2826         struct i40e_hw *hw;
2827         struct i40e_pf *pf;
2828         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2829                 [RTE_FC_NONE] = I40E_FC_NONE,
2830                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2831                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2832                 [RTE_FC_FULL] = I40E_FC_FULL
2833         };
2834
2835         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2836
2837         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2838         if ((fc_conf->high_water > max_high_water) ||
2839                         (fc_conf->high_water < fc_conf->low_water)) {
2840                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2841                         "High_water must <= %d.", max_high_water);
2842                 return -EINVAL;
2843         }
2844
2845         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2847         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2848
2849         pf->fc_conf.pause_time = fc_conf->pause_time;
2850         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2851         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2852
2853         PMD_INIT_FUNC_TRACE();
2854
2855         /* All the link flow control related enable/disable register
2856          * configuration is handle by the F/W
2857          */
2858         err = i40e_set_fc(hw, &aq_failure, true);
2859         if (err < 0)
2860                 return -ENOSYS;
2861
2862         if (i40e_is_40G_device(hw->device_id)) {
2863                 /* Configure flow control refresh threshold,
2864                  * the value for stat_tx_pause_refresh_timer[8]
2865                  * is used for global pause operation.
2866                  */
2867
2868                 I40E_WRITE_REG(hw,
2869                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2870                                pf->fc_conf.pause_time);
2871
2872                 /* configure the timer value included in transmitted pause
2873                  * frame,
2874                  * the value for stat_tx_pause_quanta[8] is used for global
2875                  * pause operation
2876                  */
2877                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2878                                pf->fc_conf.pause_time);
2879
2880                 fctrl_reg = I40E_READ_REG(hw,
2881                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2882
2883                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2884                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2885                 else
2886                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2887
2888                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2889                                fctrl_reg);
2890         } else {
2891                 /* Configure pause time (2 TCs per register) */
2892                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2893                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2894                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2895
2896                 /* Configure flow control refresh threshold value */
2897                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2898                                pf->fc_conf.pause_time / 2);
2899
2900                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2901
2902                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2903                  *depending on configuration
2904                  */
2905                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2906                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2907                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2908                 } else {
2909                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2910                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2911                 }
2912
2913                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2914         }
2915
2916         /* config the water marker both based on the packets and bytes */
2917         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2918                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2919                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2920         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2921                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2922                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2923         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2924                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2925                        << I40E_KILOSHIFT);
2926         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2927                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2928                        << I40E_KILOSHIFT);
2929
2930         I40E_WRITE_FLUSH(hw);
2931
2932         return 0;
2933 }
2934
2935 static int
2936 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2937                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2938 {
2939         PMD_INIT_FUNC_TRACE();
2940
2941         return -ENOSYS;
2942 }
2943
2944 /* Add a MAC address, and update filters */
2945 static void
2946 i40e_macaddr_add(struct rte_eth_dev *dev,
2947                  struct ether_addr *mac_addr,
2948                  __rte_unused uint32_t index,
2949                  uint32_t pool)
2950 {
2951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2952         struct i40e_mac_filter_info mac_filter;
2953         struct i40e_vsi *vsi;
2954         int ret;
2955
2956         /* If VMDQ not enabled or configured, return */
2957         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2958                           !pf->nb_cfg_vmdq_vsi)) {
2959                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2960                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2961                         pool);
2962                 return;
2963         }
2964
2965         if (pool > pf->nb_cfg_vmdq_vsi) {
2966                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2967                                 pool, pf->nb_cfg_vmdq_vsi);
2968                 return;
2969         }
2970
2971         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2972         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2973                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2974         else
2975                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2976
2977         if (pool == 0)
2978                 vsi = pf->main_vsi;
2979         else
2980                 vsi = pf->vmdq[pool - 1].vsi;
2981
2982         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2983         if (ret != I40E_SUCCESS) {
2984                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2985                 return;
2986         }
2987 }
2988
2989 /* Remove a MAC address, and update filters */
2990 static void
2991 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2992 {
2993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2994         struct i40e_vsi *vsi;
2995         struct rte_eth_dev_data *data = dev->data;
2996         struct ether_addr *macaddr;
2997         int ret;
2998         uint32_t i;
2999         uint64_t pool_sel;
3000
3001         macaddr = &(data->mac_addrs[index]);
3002
3003         pool_sel = dev->data->mac_pool_sel[index];
3004
3005         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3006                 if (pool_sel & (1ULL << i)) {
3007                         if (i == 0)
3008                                 vsi = pf->main_vsi;
3009                         else {
3010                                 /* No VMDQ pool enabled or configured */
3011                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3012                                         (i > pf->nb_cfg_vmdq_vsi)) {
3013                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3014                                                         "/configured");
3015                                         return;
3016                                 }
3017                                 vsi = pf->vmdq[i - 1].vsi;
3018                         }
3019                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3020
3021                         if (ret) {
3022                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3023                                 return;
3024                         }
3025                 }
3026         }
3027 }
3028
3029 /* Set perfect match or hash match of MAC and VLAN for a VF */
3030 static int
3031 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3032                  struct rte_eth_mac_filter *filter,
3033                  bool add)
3034 {
3035         struct i40e_hw *hw;
3036         struct i40e_mac_filter_info mac_filter;
3037         struct ether_addr old_mac;
3038         struct ether_addr *new_mac;
3039         struct i40e_pf_vf *vf = NULL;
3040         uint16_t vf_id;
3041         int ret;
3042
3043         if (pf == NULL) {
3044                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3045                 return -EINVAL;
3046         }
3047         hw = I40E_PF_TO_HW(pf);
3048
3049         if (filter == NULL) {
3050                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3051                 return -EINVAL;
3052         }
3053
3054         new_mac = &filter->mac_addr;
3055
3056         if (is_zero_ether_addr(new_mac)) {
3057                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3058                 return -EINVAL;
3059         }
3060
3061         vf_id = filter->dst_id;
3062
3063         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3064                 PMD_DRV_LOG(ERR, "Invalid argument.");
3065                 return -EINVAL;
3066         }
3067         vf = &pf->vfs[vf_id];
3068
3069         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3070                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3071                 return -EINVAL;
3072         }
3073
3074         if (add) {
3075                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3076                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3077                                 ETHER_ADDR_LEN);
3078                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3079                                  ETHER_ADDR_LEN);
3080
3081                 mac_filter.filter_type = filter->filter_type;
3082                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3083                 if (ret != I40E_SUCCESS) {
3084                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3085                         return -1;
3086                 }
3087                 ether_addr_copy(new_mac, &pf->dev_addr);
3088         } else {
3089                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3090                                 ETHER_ADDR_LEN);
3091                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3092                 if (ret != I40E_SUCCESS) {
3093                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3094                         return -1;
3095                 }
3096
3097                 /* Clear device address as it has been removed */
3098                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3099                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3100         }
3101
3102         return 0;
3103 }
3104
3105 /* MAC filter handle */
3106 static int
3107 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3108                 void *arg)
3109 {
3110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3111         struct rte_eth_mac_filter *filter;
3112         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3113         int ret = I40E_NOT_SUPPORTED;
3114
3115         filter = (struct rte_eth_mac_filter *)(arg);
3116
3117         switch (filter_op) {
3118         case RTE_ETH_FILTER_NOP:
3119                 ret = I40E_SUCCESS;
3120                 break;
3121         case RTE_ETH_FILTER_ADD:
3122                 i40e_pf_disable_irq0(hw);
3123                 if (filter->is_vf)
3124                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3125                 i40e_pf_enable_irq0(hw);
3126                 break;
3127         case RTE_ETH_FILTER_DELETE:
3128                 i40e_pf_disable_irq0(hw);
3129                 if (filter->is_vf)
3130                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3131                 i40e_pf_enable_irq0(hw);
3132                 break;
3133         default:
3134                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3135                 ret = I40E_ERR_PARAM;
3136                 break;
3137         }
3138
3139         return ret;
3140 }
3141
3142 static int
3143 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3144 {
3145         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3146         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3147         int ret;
3148
3149         if (!lut)
3150                 return -EINVAL;
3151
3152         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3153                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3154                                           lut, lut_size);
3155                 if (ret) {
3156                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3157                         return ret;
3158                 }
3159         } else {
3160                 uint32_t *lut_dw = (uint32_t *)lut;
3161                 uint16_t i, lut_size_dw = lut_size / 4;
3162
3163                 for (i = 0; i < lut_size_dw; i++)
3164                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3165         }
3166
3167         return 0;
3168 }
3169
3170 static int
3171 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3172 {
3173         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3174         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3175         int ret;
3176
3177         if (!vsi || !lut)
3178                 return -EINVAL;
3179
3180         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3181                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3182                                           lut, lut_size);
3183                 if (ret) {
3184                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3185                         return ret;
3186                 }
3187         } else {
3188                 uint32_t *lut_dw = (uint32_t *)lut;
3189                 uint16_t i, lut_size_dw = lut_size / 4;
3190
3191                 for (i = 0; i < lut_size_dw; i++)
3192                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3193                 I40E_WRITE_FLUSH(hw);
3194         }
3195
3196         return 0;
3197 }
3198
3199 static int
3200 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3201                          struct rte_eth_rss_reta_entry64 *reta_conf,
3202                          uint16_t reta_size)
3203 {
3204         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3205         uint16_t i, lut_size = pf->hash_lut_size;
3206         uint16_t idx, shift;
3207         uint8_t *lut;
3208         int ret;
3209
3210         if (reta_size != lut_size ||
3211                 reta_size > ETH_RSS_RETA_SIZE_512) {
3212                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3213                         "(%d) doesn't match the number hardware can supported "
3214                                         "(%d)\n", reta_size, lut_size);
3215                 return -EINVAL;
3216         }
3217
3218         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3219         if (!lut) {
3220                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3221                 return -ENOMEM;
3222         }
3223         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3224         if (ret)
3225                 goto out;
3226         for (i = 0; i < reta_size; i++) {
3227                 idx = i / RTE_RETA_GROUP_SIZE;
3228                 shift = i % RTE_RETA_GROUP_SIZE;
3229                 if (reta_conf[idx].mask & (1ULL << shift))
3230                         lut[i] = reta_conf[idx].reta[shift];
3231         }
3232         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3233
3234 out:
3235         rte_free(lut);
3236
3237         return ret;
3238 }
3239
3240 static int
3241 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3242                         struct rte_eth_rss_reta_entry64 *reta_conf,
3243                         uint16_t reta_size)
3244 {
3245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3246         uint16_t i, lut_size = pf->hash_lut_size;
3247         uint16_t idx, shift;
3248         uint8_t *lut;
3249         int ret;
3250
3251         if (reta_size != lut_size ||
3252                 reta_size > ETH_RSS_RETA_SIZE_512) {
3253                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3254                         "(%d) doesn't match the number hardware can supported "
3255                                         "(%d)\n", reta_size, lut_size);
3256                 return -EINVAL;
3257         }
3258
3259         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3260         if (!lut) {
3261                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3262                 return -ENOMEM;
3263         }
3264
3265         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3266         if (ret)
3267                 goto out;
3268         for (i = 0; i < reta_size; i++) {
3269                 idx = i / RTE_RETA_GROUP_SIZE;
3270                 shift = i % RTE_RETA_GROUP_SIZE;
3271                 if (reta_conf[idx].mask & (1ULL << shift))
3272                         reta_conf[idx].reta[shift] = lut[i];
3273         }
3274
3275 out:
3276         rte_free(lut);
3277
3278         return ret;
3279 }
3280
3281 /**
3282  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3283  * @hw:   pointer to the HW structure
3284  * @mem:  pointer to mem struct to fill out
3285  * @size: size of memory requested
3286  * @alignment: what to align the allocation to
3287  **/
3288 enum i40e_status_code
3289 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3290                         struct i40e_dma_mem *mem,
3291                         u64 size,
3292                         u32 alignment)
3293 {
3294         const struct rte_memzone *mz = NULL;
3295         char z_name[RTE_MEMZONE_NAMESIZE];
3296
3297         if (!mem)
3298                 return I40E_ERR_PARAM;
3299
3300         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3301         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3302                                          alignment, RTE_PGSIZE_2M);
3303         if (!mz)
3304                 return I40E_ERR_NO_MEMORY;
3305
3306         mem->size = size;
3307         mem->va = mz->addr;
3308         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3309         mem->zone = (const void *)mz;
3310         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3311                     "%"PRIu64, mz->name, mem->pa);
3312
3313         return I40E_SUCCESS;
3314 }
3315
3316 /**
3317  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3318  * @hw:   pointer to the HW structure
3319  * @mem:  ptr to mem struct to free
3320  **/
3321 enum i40e_status_code
3322 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3323                     struct i40e_dma_mem *mem)
3324 {
3325         if (!mem)
3326                 return I40E_ERR_PARAM;
3327
3328         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3329                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3330                     mem->pa);
3331         rte_memzone_free((const struct rte_memzone *)mem->zone);
3332         mem->zone = NULL;
3333         mem->va = NULL;
3334         mem->pa = (u64)0;
3335
3336         return I40E_SUCCESS;
3337 }
3338
3339 /**
3340  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3341  * @hw:   pointer to the HW structure
3342  * @mem:  pointer to mem struct to fill out
3343  * @size: size of memory requested
3344  **/
3345 enum i40e_status_code
3346 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3347                          struct i40e_virt_mem *mem,
3348                          u32 size)
3349 {
3350         if (!mem)
3351                 return I40E_ERR_PARAM;
3352
3353         mem->size = size;
3354         mem->va = rte_zmalloc("i40e", size, 0);
3355
3356         if (mem->va)
3357                 return I40E_SUCCESS;
3358         else
3359                 return I40E_ERR_NO_MEMORY;
3360 }
3361
3362 /**
3363  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3364  * @hw:   pointer to the HW structure
3365  * @mem:  pointer to mem struct to free
3366  **/
3367 enum i40e_status_code
3368 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3369                      struct i40e_virt_mem *mem)
3370 {
3371         if (!mem)
3372                 return I40E_ERR_PARAM;
3373
3374         rte_free(mem->va);
3375         mem->va = NULL;
3376
3377         return I40E_SUCCESS;
3378 }
3379
3380 void
3381 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3382 {
3383         rte_spinlock_init(&sp->spinlock);
3384 }
3385
3386 void
3387 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3388 {
3389         rte_spinlock_lock(&sp->spinlock);
3390 }
3391
3392 void
3393 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3394 {
3395         rte_spinlock_unlock(&sp->spinlock);
3396 }
3397
3398 void
3399 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3400 {
3401         return;
3402 }
3403
3404 /**
3405  * Get the hardware capabilities, which will be parsed
3406  * and saved into struct i40e_hw.
3407  */
3408 static int
3409 i40e_get_cap(struct i40e_hw *hw)
3410 {
3411         struct i40e_aqc_list_capabilities_element_resp *buf;
3412         uint16_t len, size = 0;
3413         int ret;
3414
3415         /* Calculate a huge enough buff for saving response data temporarily */
3416         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3417                                                 I40E_MAX_CAP_ELE_NUM;
3418         buf = rte_zmalloc("i40e", len, 0);
3419         if (!buf) {
3420                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3421                 return I40E_ERR_NO_MEMORY;
3422         }
3423
3424         /* Get, parse the capabilities and save it to hw */
3425         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3426                         i40e_aqc_opc_list_func_capabilities, NULL);
3427         if (ret != I40E_SUCCESS)
3428                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3429
3430         /* Free the temporary buffer after being used */
3431         rte_free(buf);
3432
3433         return ret;
3434 }
3435
3436 static int
3437 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3438 {
3439         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3440         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3441         uint16_t qp_count = 0, vsi_count = 0;
3442
3443         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3444                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3445                 return -EINVAL;
3446         }
3447         /* Add the parameter init for LFC */
3448         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3449         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3450         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3451
3452         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3453         pf->max_num_vsi = hw->func_caps.num_vsis;
3454         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3455         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3456         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3457
3458         /* FDir queue/VSI allocation */
3459         pf->fdir_qp_offset = 0;
3460         if (hw->func_caps.fd) {
3461                 pf->flags |= I40E_FLAG_FDIR;
3462                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3463         } else {
3464                 pf->fdir_nb_qps = 0;
3465         }
3466         qp_count += pf->fdir_nb_qps;
3467         vsi_count += 1;
3468
3469         /* LAN queue/VSI allocation */
3470         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3471         if (!hw->func_caps.rss) {
3472                 pf->lan_nb_qps = 1;
3473         } else {
3474                 pf->flags |= I40E_FLAG_RSS;
3475                 if (hw->mac.type == I40E_MAC_X722)
3476                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3477                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3478         }
3479         qp_count += pf->lan_nb_qps;
3480         vsi_count += 1;
3481
3482         /* VF queue/VSI allocation */
3483         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3484         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3485                 pf->flags |= I40E_FLAG_SRIOV;
3486                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3487                 pf->vf_num = dev->pci_dev->max_vfs;
3488                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3489                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3490                             pf->vf_nb_qps * pf->vf_num);
3491         } else {
3492                 pf->vf_nb_qps = 0;
3493                 pf->vf_num = 0;
3494         }
3495         qp_count += pf->vf_nb_qps * pf->vf_num;
3496         vsi_count += pf->vf_num;
3497
3498         /* VMDq queue/VSI allocation */
3499         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3500         pf->vmdq_nb_qps = 0;
3501         pf->max_nb_vmdq_vsi = 0;
3502         if (hw->func_caps.vmdq) {
3503                 if (qp_count < hw->func_caps.num_tx_qp &&
3504                         vsi_count < hw->func_caps.num_vsis) {
3505                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3506                                 qp_count) / pf->vmdq_nb_qp_max;
3507
3508                         /* Limit the maximum number of VMDq vsi to the maximum
3509                          * ethdev can support
3510                          */
3511                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3512                                 hw->func_caps.num_vsis - vsi_count);
3513                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3514                                 ETH_64_POOLS);
3515                         if (pf->max_nb_vmdq_vsi) {
3516                                 pf->flags |= I40E_FLAG_VMDQ;
3517                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3518                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3519                                             "per VMDQ VSI, in total %u queues",
3520                                             pf->max_nb_vmdq_vsi,
3521                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3522                                             pf->max_nb_vmdq_vsi);
3523                         } else {
3524                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3525                                             "VMDq");
3526                         }
3527                 } else {
3528                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3529                 }
3530         }
3531         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3532         vsi_count += pf->max_nb_vmdq_vsi;
3533
3534         if (hw->func_caps.dcb)
3535                 pf->flags |= I40E_FLAG_DCB;
3536
3537         if (qp_count > hw->func_caps.num_tx_qp) {
3538                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3539                             "the hardware maximum %u", qp_count,
3540                             hw->func_caps.num_tx_qp);
3541                 return -EINVAL;
3542         }
3543         if (vsi_count > hw->func_caps.num_vsis) {
3544                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3545                             "the hardware maximum %u", vsi_count,
3546                             hw->func_caps.num_vsis);
3547                 return -EINVAL;
3548         }
3549
3550         return 0;
3551 }
3552
3553 static int
3554 i40e_pf_get_switch_config(struct i40e_pf *pf)
3555 {
3556         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3557         struct i40e_aqc_get_switch_config_resp *switch_config;
3558         struct i40e_aqc_switch_config_element_resp *element;
3559         uint16_t start_seid = 0, num_reported;
3560         int ret;
3561
3562         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3563                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3564         if (!switch_config) {
3565                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3566                 return -ENOMEM;
3567         }
3568
3569         /* Get the switch configurations */
3570         ret = i40e_aq_get_switch_config(hw, switch_config,
3571                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3572         if (ret != I40E_SUCCESS) {
3573                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3574                 goto fail;
3575         }
3576         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3577         if (num_reported != 1) { /* The number should be 1 */
3578                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3579                 goto fail;
3580         }
3581
3582         /* Parse the switch configuration elements */
3583         element = &(switch_config->element[0]);
3584         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3585                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3586                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3587         } else
3588                 PMD_DRV_LOG(INFO, "Unknown element type");
3589
3590 fail:
3591         rte_free(switch_config);
3592
3593         return ret;
3594 }
3595
3596 static int
3597 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3598                         uint32_t num)
3599 {
3600         struct pool_entry *entry;
3601
3602         if (pool == NULL || num == 0)
3603                 return -EINVAL;
3604
3605         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3606         if (entry == NULL) {
3607                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3608                 return -ENOMEM;
3609         }
3610
3611         /* queue heap initialize */
3612         pool->num_free = num;
3613         pool->num_alloc = 0;
3614         pool->base = base;
3615         LIST_INIT(&pool->alloc_list);
3616         LIST_INIT(&pool->free_list);
3617
3618         /* Initialize element  */
3619         entry->base = 0;
3620         entry->len = num;
3621
3622         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3623         return 0;
3624 }
3625
3626 static void
3627 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3628 {
3629         struct pool_entry *entry, *next_entry;
3630
3631         if (pool == NULL)
3632                 return;
3633
3634         for (entry = LIST_FIRST(&pool->alloc_list);
3635                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3636                         entry = next_entry) {
3637                 LIST_REMOVE(entry, next);
3638                 rte_free(entry);
3639         }
3640
3641         for (entry = LIST_FIRST(&pool->free_list);
3642                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3643                         entry = next_entry) {
3644                 LIST_REMOVE(entry, next);
3645                 rte_free(entry);
3646         }
3647
3648         pool->num_free = 0;
3649         pool->num_alloc = 0;
3650         pool->base = 0;
3651         LIST_INIT(&pool->alloc_list);
3652         LIST_INIT(&pool->free_list);
3653 }
3654
3655 static int
3656 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3657                        uint32_t base)
3658 {
3659         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3660         uint32_t pool_offset;
3661         int insert;
3662
3663         if (pool == NULL) {
3664                 PMD_DRV_LOG(ERR, "Invalid parameter");
3665                 return -EINVAL;
3666         }
3667
3668         pool_offset = base - pool->base;
3669         /* Lookup in alloc list */
3670         LIST_FOREACH(entry, &pool->alloc_list, next) {
3671                 if (entry->base == pool_offset) {
3672                         valid_entry = entry;
3673                         LIST_REMOVE(entry, next);
3674                         break;
3675                 }
3676         }
3677
3678         /* Not find, return */
3679         if (valid_entry == NULL) {
3680                 PMD_DRV_LOG(ERR, "Failed to find entry");
3681                 return -EINVAL;
3682         }
3683
3684         /**
3685          * Found it, move it to free list  and try to merge.
3686          * In order to make merge easier, always sort it by qbase.
3687          * Find adjacent prev and last entries.
3688          */
3689         prev = next = NULL;
3690         LIST_FOREACH(entry, &pool->free_list, next) {
3691                 if (entry->base > valid_entry->base) {
3692                         next = entry;
3693                         break;
3694                 }
3695                 prev = entry;
3696         }
3697
3698         insert = 0;
3699         /* Try to merge with next one*/
3700         if (next != NULL) {
3701                 /* Merge with next one */
3702                 if (valid_entry->base + valid_entry->len == next->base) {
3703                         next->base = valid_entry->base;
3704                         next->len += valid_entry->len;
3705                         rte_free(valid_entry);
3706                         valid_entry = next;
3707                         insert = 1;
3708                 }
3709         }
3710
3711         if (prev != NULL) {
3712                 /* Merge with previous one */
3713                 if (prev->base + prev->len == valid_entry->base) {
3714                         prev->len += valid_entry->len;
3715                         /* If it merge with next one, remove next node */
3716                         if (insert == 1) {
3717                                 LIST_REMOVE(valid_entry, next);
3718                                 rte_free(valid_entry);
3719                         } else {
3720                                 rte_free(valid_entry);
3721                                 insert = 1;
3722                         }
3723                 }
3724         }
3725
3726         /* Not find any entry to merge, insert */
3727         if (insert == 0) {
3728                 if (prev != NULL)
3729                         LIST_INSERT_AFTER(prev, valid_entry, next);
3730                 else if (next != NULL)
3731                         LIST_INSERT_BEFORE(next, valid_entry, next);
3732                 else /* It's empty list, insert to head */
3733                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3734         }
3735
3736         pool->num_free += valid_entry->len;
3737         pool->num_alloc -= valid_entry->len;
3738
3739         return 0;
3740 }
3741
3742 static int
3743 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3744                        uint16_t num)
3745 {
3746         struct pool_entry *entry, *valid_entry;
3747
3748         if (pool == NULL || num == 0) {
3749                 PMD_DRV_LOG(ERR, "Invalid parameter");
3750                 return -EINVAL;
3751         }
3752
3753         if (pool->num_free < num) {
3754                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3755                             num, pool->num_free);
3756                 return -ENOMEM;
3757         }
3758
3759         valid_entry = NULL;
3760         /* Lookup  in free list and find most fit one */
3761         LIST_FOREACH(entry, &pool->free_list, next) {
3762                 if (entry->len >= num) {
3763                         /* Find best one */
3764                         if (entry->len == num) {
3765                                 valid_entry = entry;
3766                                 break;
3767                         }
3768                         if (valid_entry == NULL || valid_entry->len > entry->len)
3769                                 valid_entry = entry;
3770                 }
3771         }
3772
3773         /* Not find one to satisfy the request, return */
3774         if (valid_entry == NULL) {
3775                 PMD_DRV_LOG(ERR, "No valid entry found");
3776                 return -ENOMEM;
3777         }
3778         /**
3779          * The entry have equal queue number as requested,
3780          * remove it from alloc_list.
3781          */
3782         if (valid_entry->len == num) {
3783                 LIST_REMOVE(valid_entry, next);
3784         } else {
3785                 /**
3786                  * The entry have more numbers than requested,
3787                  * create a new entry for alloc_list and minus its
3788                  * queue base and number in free_list.
3789                  */
3790                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3791                 if (entry == NULL) {
3792                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3793                                     "resource pool");
3794                         return -ENOMEM;
3795                 }
3796                 entry->base = valid_entry->base;
3797                 entry->len = num;
3798                 valid_entry->base += num;
3799                 valid_entry->len -= num;
3800                 valid_entry = entry;
3801         }
3802
3803         /* Insert it into alloc list, not sorted */
3804         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3805
3806         pool->num_free -= valid_entry->len;
3807         pool->num_alloc += valid_entry->len;
3808
3809         return valid_entry->base + pool->base;
3810 }
3811
3812 /**
3813  * bitmap_is_subset - Check whether src2 is subset of src1
3814  **/
3815 static inline int
3816 bitmap_is_subset(uint8_t src1, uint8_t src2)
3817 {
3818         return !((src1 ^ src2) & src2);
3819 }
3820
3821 static enum i40e_status_code
3822 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3823 {
3824         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3825
3826         /* If DCB is not supported, only default TC is supported */
3827         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3828                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3829                 return I40E_NOT_SUPPORTED;
3830         }
3831
3832         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3833                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3834                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3835                             enabled_tcmap);
3836                 return I40E_NOT_SUPPORTED;
3837         }
3838         return I40E_SUCCESS;
3839 }
3840
3841 int
3842 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3843                                 struct i40e_vsi_vlan_pvid_info *info)
3844 {
3845         struct i40e_hw *hw;
3846         struct i40e_vsi_context ctxt;
3847         uint8_t vlan_flags = 0;
3848         int ret;
3849
3850         if (vsi == NULL || info == NULL) {
3851                 PMD_DRV_LOG(ERR, "invalid parameters");
3852                 return I40E_ERR_PARAM;
3853         }
3854
3855         if (info->on) {
3856                 vsi->info.pvid = info->config.pvid;
3857                 /**
3858                  * If insert pvid is enabled, only tagged pkts are
3859                  * allowed to be sent out.
3860                  */
3861                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3862                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3863         } else {
3864                 vsi->info.pvid = 0;
3865                 if (info->config.reject.tagged == 0)
3866                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3867
3868                 if (info->config.reject.untagged == 0)
3869                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3870         }
3871         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3872                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3873         vsi->info.port_vlan_flags |= vlan_flags;
3874         vsi->info.valid_sections =
3875                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3876         memset(&ctxt, 0, sizeof(ctxt));
3877         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3878         ctxt.seid = vsi->seid;
3879
3880         hw = I40E_VSI_TO_HW(vsi);
3881         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3882         if (ret != I40E_SUCCESS)
3883                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3884
3885         return ret;
3886 }
3887
3888 static int
3889 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3890 {
3891         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3892         int i, ret;
3893         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3894
3895         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3896         if (ret != I40E_SUCCESS)
3897                 return ret;
3898
3899         if (!vsi->seid) {
3900                 PMD_DRV_LOG(ERR, "seid not valid");
3901                 return -EINVAL;
3902         }
3903
3904         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3905         tc_bw_data.tc_valid_bits = enabled_tcmap;
3906         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3907                 tc_bw_data.tc_bw_credits[i] =
3908                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3909
3910         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3911         if (ret != I40E_SUCCESS) {
3912                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3913                 return ret;
3914         }
3915
3916         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3917                                         sizeof(vsi->info.qs_handle));
3918         return I40E_SUCCESS;
3919 }
3920
3921 static enum i40e_status_code
3922 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3923                                  struct i40e_aqc_vsi_properties_data *info,
3924                                  uint8_t enabled_tcmap)
3925 {
3926         enum i40e_status_code ret;
3927         int i, total_tc = 0;
3928         uint16_t qpnum_per_tc, bsf, qp_idx;
3929
3930         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3931         if (ret != I40E_SUCCESS)
3932                 return ret;
3933
3934         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3935                 if (enabled_tcmap & (1 << i))
3936                         total_tc++;
3937         vsi->enabled_tc = enabled_tcmap;
3938
3939         /* Number of queues per enabled TC */
3940         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3941         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3942         bsf = rte_bsf32(qpnum_per_tc);
3943
3944         /* Adjust the queue number to actual queues that can be applied */
3945         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3946                 vsi->nb_qps = qpnum_per_tc * total_tc;
3947
3948         /**
3949          * Configure TC and queue mapping parameters, for enabled TC,
3950          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3951          * default queue will serve it.
3952          */
3953         qp_idx = 0;
3954         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3955                 if (vsi->enabled_tc & (1 << i)) {
3956                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3957                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3958                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3959                         qp_idx += qpnum_per_tc;
3960                 } else
3961                         info->tc_mapping[i] = 0;
3962         }
3963
3964         /* Associate queue number with VSI */
3965         if (vsi->type == I40E_VSI_SRIOV) {
3966                 info->mapping_flags |=
3967                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3968                 for (i = 0; i < vsi->nb_qps; i++)
3969                         info->queue_mapping[i] =
3970                                 rte_cpu_to_le_16(vsi->base_queue + i);
3971         } else {
3972                 info->mapping_flags |=
3973                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3974                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3975         }
3976         info->valid_sections |=
3977                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3978
3979         return I40E_SUCCESS;
3980 }
3981
3982 static int
3983 i40e_veb_release(struct i40e_veb *veb)
3984 {
3985         struct i40e_vsi *vsi;
3986         struct i40e_hw *hw;
3987
3988         if (veb == NULL)
3989                 return -EINVAL;
3990
3991         if (!TAILQ_EMPTY(&veb->head)) {
3992                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3993                 return -EACCES;
3994         }
3995         /* associate_vsi field is NULL for floating VEB */
3996         if (veb->associate_vsi != NULL) {
3997                 vsi = veb->associate_vsi;
3998                 hw = I40E_VSI_TO_HW(vsi);
3999
4000                 vsi->uplink_seid = veb->uplink_seid;
4001                 vsi->veb = NULL;
4002         } else {
4003                 veb->associate_pf->main_vsi->floating_veb = NULL;
4004                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4005         }
4006
4007         i40e_aq_delete_element(hw, veb->seid, NULL);
4008         rte_free(veb);
4009         return I40E_SUCCESS;
4010 }
4011
4012 /* Setup a veb */
4013 static struct i40e_veb *
4014 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4015 {
4016         struct i40e_veb *veb;
4017         int ret;
4018         struct i40e_hw *hw;
4019
4020         if (pf == NULL) {
4021                 PMD_DRV_LOG(ERR,
4022                             "veb setup failed, associated PF shouldn't null");
4023                 return NULL;
4024         }
4025         hw = I40E_PF_TO_HW(pf);
4026
4027         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4028         if (!veb) {
4029                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4030                 goto fail;
4031         }
4032
4033         veb->associate_vsi = vsi;
4034         veb->associate_pf = pf;
4035         TAILQ_INIT(&veb->head);
4036         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4037
4038         /* create floating veb if vsi is NULL */
4039         if (vsi != NULL) {
4040                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4041                                       I40E_DEFAULT_TCMAP, false,
4042                                       &veb->seid, false, NULL);
4043         } else {
4044                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4045                                       true, &veb->seid, false, NULL);
4046         }
4047
4048         if (ret != I40E_SUCCESS) {
4049                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4050                             hw->aq.asq_last_status);
4051                 goto fail;
4052         }
4053
4054         /* get statistics index */
4055         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4056                                 &veb->stats_idx, NULL, NULL, NULL);
4057         if (ret != I40E_SUCCESS) {
4058                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4059                             hw->aq.asq_last_status);
4060                 goto fail;
4061         }
4062         /* Get VEB bandwidth, to be implemented */
4063         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4064         if (vsi)
4065                 vsi->uplink_seid = veb->seid;
4066
4067         return veb;
4068 fail:
4069         rte_free(veb);
4070         return NULL;
4071 }
4072
4073 int
4074 i40e_vsi_release(struct i40e_vsi *vsi)
4075 {
4076         struct i40e_pf *pf;
4077         struct i40e_hw *hw;
4078         struct i40e_vsi_list *vsi_list;
4079         int ret;
4080         struct i40e_mac_filter *f;
4081         uint16_t user_param = vsi->user_param;
4082
4083         if (!vsi)
4084                 return I40E_SUCCESS;
4085
4086         pf = I40E_VSI_TO_PF(vsi);
4087         hw = I40E_VSI_TO_HW(vsi);
4088
4089         /* VSI has child to attach, release child first */
4090         if (vsi->veb) {
4091                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
4092                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4093                                 return -1;
4094                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4095                 }
4096                 i40e_veb_release(vsi->veb);
4097         }
4098
4099         if (vsi->floating_veb) {
4100                 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
4101                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4102                                 return -1;
4103                         TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4104                 }
4105         }
4106
4107         /* Remove all macvlan filters of the VSI */
4108         i40e_vsi_remove_all_macvlan_filter(vsi);
4109         TAILQ_FOREACH(f, &vsi->mac_list, next)
4110                 rte_free(f);
4111
4112         if (vsi->type != I40E_VSI_MAIN &&
4113             ((vsi->type != I40E_VSI_SRIOV) ||
4114             !pf->floating_veb_list[user_param])) {
4115                 /* Remove vsi from parent's sibling list */
4116                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4117                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4118                         return I40E_ERR_PARAM;
4119                 }
4120                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4121                                 &vsi->sib_vsi_list, list);
4122
4123                 /* Remove all switch element of the VSI */
4124                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4125                 if (ret != I40E_SUCCESS)
4126                         PMD_DRV_LOG(ERR, "Failed to delete element");
4127         }
4128
4129         if ((vsi->type == I40E_VSI_SRIOV) &&
4130             pf->floating_veb_list[user_param]) {
4131                 /* Remove vsi from parent's sibling list */
4132                 if (vsi->parent_vsi == NULL ||
4133                     vsi->parent_vsi->floating_veb == NULL) {
4134                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4135                         return I40E_ERR_PARAM;
4136                 }
4137                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4138                              &vsi->sib_vsi_list, list);
4139
4140                 /* Remove all switch element of the VSI */
4141                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4142                 if (ret != I40E_SUCCESS)
4143                         PMD_DRV_LOG(ERR, "Failed to delete element");
4144         }
4145
4146         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4147
4148         if (vsi->type != I40E_VSI_SRIOV)
4149                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4150         rte_free(vsi);
4151
4152         return I40E_SUCCESS;
4153 }
4154
4155 static int
4156 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4157 {
4158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4159         struct i40e_aqc_remove_macvlan_element_data def_filter;
4160         struct i40e_mac_filter_info filter;
4161         int ret;
4162
4163         if (vsi->type != I40E_VSI_MAIN)
4164                 return I40E_ERR_CONFIG;
4165         memset(&def_filter, 0, sizeof(def_filter));
4166         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4167                                         ETH_ADDR_LEN);
4168         def_filter.vlan_tag = 0;
4169         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4170                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4171         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4172         if (ret != I40E_SUCCESS) {
4173                 struct i40e_mac_filter *f;
4174                 struct ether_addr *mac;
4175
4176                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4177                             "macvlan filter");
4178                 /* It needs to add the permanent mac into mac list */
4179                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4180                 if (f == NULL) {
4181                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4182                         return I40E_ERR_NO_MEMORY;
4183                 }
4184                 mac = &f->mac_info.mac_addr;
4185                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4186                                 ETH_ADDR_LEN);
4187                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4188                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4189                 vsi->mac_num++;
4190
4191                 return ret;
4192         }
4193         (void)rte_memcpy(&filter.mac_addr,
4194                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4195         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4196         return i40e_vsi_add_mac(vsi, &filter);
4197 }
4198
4199 /*
4200  * i40e_vsi_get_bw_config - Query VSI BW Information
4201  * @vsi: the VSI to be queried
4202  *
4203  * Returns 0 on success, negative value on failure
4204  */
4205 static enum i40e_status_code
4206 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4207 {
4208         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4209         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4210         struct i40e_hw *hw = &vsi->adapter->hw;
4211         i40e_status ret;
4212         int i;
4213         uint32_t bw_max;
4214
4215         memset(&bw_config, 0, sizeof(bw_config));
4216         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4217         if (ret != I40E_SUCCESS) {
4218                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4219                             hw->aq.asq_last_status);
4220                 return ret;
4221         }
4222
4223         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4224         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4225                                         &ets_sla_config, NULL);
4226         if (ret != I40E_SUCCESS) {
4227                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4228                             "configuration %u", hw->aq.asq_last_status);
4229                 return ret;
4230         }
4231
4232         /* store and print out BW info */
4233         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4234         vsi->bw_info.bw_max = bw_config.max_bw;
4235         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4236         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4237         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4238                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4239                      I40E_16_BIT_WIDTH);
4240         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4241                 vsi->bw_info.bw_ets_share_credits[i] =
4242                                 ets_sla_config.share_credits[i];
4243                 vsi->bw_info.bw_ets_credits[i] =
4244                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4245                 /* 4 bits per TC, 4th bit is reserved */
4246                 vsi->bw_info.bw_ets_max[i] =
4247                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4248                                   RTE_LEN2MASK(3, uint8_t));
4249                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4250                             vsi->bw_info.bw_ets_share_credits[i]);
4251                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4252                             vsi->bw_info.bw_ets_credits[i]);
4253                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4254                             vsi->bw_info.bw_ets_max[i]);
4255         }
4256
4257         return I40E_SUCCESS;
4258 }
4259
4260 /* i40e_enable_pf_lb
4261  * @pf: pointer to the pf structure
4262  *
4263  * allow loopback on pf
4264  */
4265 static inline void
4266 i40e_enable_pf_lb(struct i40e_pf *pf)
4267 {
4268         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4269         struct i40e_vsi_context ctxt;
4270         int ret;
4271
4272         /* Use the FW API if FW >= v5.0 */
4273         if (hw->aq.fw_maj_ver < 5) {
4274                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4275                 return;
4276         }
4277
4278         memset(&ctxt, 0, sizeof(ctxt));
4279         ctxt.seid = pf->main_vsi_seid;
4280         ctxt.pf_num = hw->pf_id;
4281         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4282         if (ret) {
4283                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4284                             ret, hw->aq.asq_last_status);
4285                 return;
4286         }
4287         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4288         ctxt.info.valid_sections =
4289                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4290         ctxt.info.switch_id |=
4291                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4292
4293         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4294         if (ret)
4295                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4296                             hw->aq.asq_last_status);
4297 }
4298
4299 /* Setup a VSI */
4300 struct i40e_vsi *
4301 i40e_vsi_setup(struct i40e_pf *pf,
4302                enum i40e_vsi_type type,
4303                struct i40e_vsi *uplink_vsi,
4304                uint16_t user_param)
4305 {
4306         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4307         struct i40e_vsi *vsi;
4308         struct i40e_mac_filter_info filter;
4309         int ret;
4310         struct i40e_vsi_context ctxt;
4311         struct ether_addr broadcast =
4312                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4313
4314         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4315             uplink_vsi == NULL) {
4316                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4317                             "VSI link shouldn't be NULL");
4318                 return NULL;
4319         }
4320
4321         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4322                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4323                             "uplink VSI should be NULL");
4324                 return NULL;
4325         }
4326
4327         /* two situations
4328          * 1.type is not MAIN and uplink vsi is not NULL
4329          * If uplink vsi didn't setup VEB, create one first under veb field
4330          * 2.type is SRIOV and the uplink is NULL
4331          * If floating VEB is NULL, create one veb under floating veb field
4332          */
4333
4334         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4335             uplink_vsi->veb == NULL) {
4336                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4337
4338                 if (uplink_vsi->veb == NULL) {
4339                         PMD_DRV_LOG(ERR, "VEB setup failed");
4340                         return NULL;
4341                 }
4342                 /* set ALLOWLOOPBACk on pf, when veb is created */
4343                 i40e_enable_pf_lb(pf);
4344         }
4345
4346         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4347             pf->main_vsi->floating_veb == NULL) {
4348                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4349
4350                 if (pf->main_vsi->floating_veb == NULL) {
4351                         PMD_DRV_LOG(ERR, "VEB setup failed");
4352                         return NULL;
4353                 }
4354         }
4355
4356         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4357         if (!vsi) {
4358                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4359                 return NULL;
4360         }
4361         TAILQ_INIT(&vsi->mac_list);
4362         vsi->type = type;
4363         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4364         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4365         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4366         vsi->user_param = user_param;
4367         /* Allocate queues */
4368         switch (vsi->type) {
4369         case I40E_VSI_MAIN  :
4370                 vsi->nb_qps = pf->lan_nb_qps;
4371                 break;
4372         case I40E_VSI_SRIOV :
4373                 vsi->nb_qps = pf->vf_nb_qps;
4374                 break;
4375         case I40E_VSI_VMDQ2:
4376                 vsi->nb_qps = pf->vmdq_nb_qps;
4377                 break;
4378         case I40E_VSI_FDIR:
4379                 vsi->nb_qps = pf->fdir_nb_qps;
4380                 break;
4381         default:
4382                 goto fail_mem;
4383         }
4384         /*
4385          * The filter status descriptor is reported in rx queue 0,
4386          * while the tx queue for fdir filter programming has no
4387          * such constraints, can be non-zero queues.
4388          * To simplify it, choose FDIR vsi use queue 0 pair.
4389          * To make sure it will use queue 0 pair, queue allocation
4390          * need be done before this function is called
4391          */
4392         if (type != I40E_VSI_FDIR) {
4393                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4394                         if (ret < 0) {
4395                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4396                                                 vsi->seid, ret);
4397                                 goto fail_mem;
4398                         }
4399                         vsi->base_queue = ret;
4400         } else
4401                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4402
4403         /* VF has MSIX interrupt in VF range, don't allocate here */
4404         if (type == I40E_VSI_MAIN) {
4405                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4406                                           RTE_MIN(vsi->nb_qps,
4407                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4408                 if (ret < 0) {
4409                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4410                                     vsi->seid, ret);
4411                         goto fail_queue_alloc;
4412                 }
4413                 vsi->msix_intr = ret;
4414                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4415         } else if (type != I40E_VSI_SRIOV) {
4416                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4417                 if (ret < 0) {
4418                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4419                         goto fail_queue_alloc;
4420                 }
4421                 vsi->msix_intr = ret;
4422                 vsi->nb_msix = 1;
4423         } else {
4424                 vsi->msix_intr = 0;
4425                 vsi->nb_msix = 0;
4426         }
4427
4428         /* Add VSI */
4429         if (type == I40E_VSI_MAIN) {
4430                 /* For main VSI, no need to add since it's default one */
4431                 vsi->uplink_seid = pf->mac_seid;
4432                 vsi->seid = pf->main_vsi_seid;
4433                 /* Bind queues with specific MSIX interrupt */
4434                 /**
4435                  * Needs 2 interrupt at least, one for misc cause which will
4436                  * enabled from OS side, Another for queues binding the
4437                  * interrupt from device side only.
4438                  */
4439
4440                 /* Get default VSI parameters from hardware */
4441                 memset(&ctxt, 0, sizeof(ctxt));
4442                 ctxt.seid = vsi->seid;
4443                 ctxt.pf_num = hw->pf_id;
4444                 ctxt.uplink_seid = vsi->uplink_seid;
4445                 ctxt.vf_num = 0;
4446                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4447                 if (ret != I40E_SUCCESS) {
4448                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4449                         goto fail_msix_alloc;
4450                 }
4451                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4452                         sizeof(struct i40e_aqc_vsi_properties_data));
4453                 vsi->vsi_id = ctxt.vsi_number;
4454                 vsi->info.valid_sections = 0;
4455
4456                 /* Configure tc, enabled TC0 only */
4457                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4458                         I40E_SUCCESS) {
4459                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4460                         goto fail_msix_alloc;
4461                 }
4462
4463                 /* TC, queue mapping */
4464                 memset(&ctxt, 0, sizeof(ctxt));
4465                 vsi->info.valid_sections |=
4466                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4467                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4468                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4469                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4470                         sizeof(struct i40e_aqc_vsi_properties_data));
4471                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4472                                                 I40E_DEFAULT_TCMAP);
4473                 if (ret != I40E_SUCCESS) {
4474                         PMD_DRV_LOG(ERR, "Failed to configure "
4475                                     "TC queue mapping");
4476                         goto fail_msix_alloc;
4477                 }
4478                 ctxt.seid = vsi->seid;
4479                 ctxt.pf_num = hw->pf_id;
4480                 ctxt.uplink_seid = vsi->uplink_seid;
4481                 ctxt.vf_num = 0;
4482
4483                 /* Update VSI parameters */
4484                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4485                 if (ret != I40E_SUCCESS) {
4486                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4487                         goto fail_msix_alloc;
4488                 }
4489
4490                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4491                                                 sizeof(vsi->info.tc_mapping));
4492                 (void)rte_memcpy(&vsi->info.queue_mapping,
4493                                 &ctxt.info.queue_mapping,
4494                         sizeof(vsi->info.queue_mapping));
4495                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4496                 vsi->info.valid_sections = 0;
4497
4498                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4499                                 ETH_ADDR_LEN);
4500
4501                 /**
4502                  * Updating default filter settings are necessary to prevent
4503                  * reception of tagged packets.
4504                  * Some old firmware configurations load a default macvlan
4505                  * filter which accepts both tagged and untagged packets.
4506                  * The updating is to use a normal filter instead if needed.
4507                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4508                  * The firmware with correct configurations load the default
4509                  * macvlan filter which is expected and cannot be removed.
4510                  */
4511                 i40e_update_default_filter_setting(vsi);
4512                 i40e_config_qinq(hw, vsi);
4513         } else if (type == I40E_VSI_SRIOV) {
4514                 memset(&ctxt, 0, sizeof(ctxt));
4515                 /**
4516                  * For other VSI, the uplink_seid equals to uplink VSI's
4517                  * uplink_seid since they share same VEB
4518                  */
4519                 if (uplink_vsi == NULL)
4520                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4521                 else
4522                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4523                 ctxt.pf_num = hw->pf_id;
4524                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4525                 ctxt.uplink_seid = vsi->uplink_seid;
4526                 ctxt.connection_type = 0x1;
4527                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4528
4529                 /* Use the VEB configuration if FW >= v5.0 */
4530                 if (hw->aq.fw_maj_ver >= 5) {
4531                         /* Configure switch ID */
4532                         ctxt.info.valid_sections |=
4533                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4534                         ctxt.info.switch_id =
4535                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4536                 }
4537
4538                 /* Configure port/vlan */
4539                 ctxt.info.valid_sections |=
4540                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4541                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4542                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4543                                                 I40E_DEFAULT_TCMAP);
4544                 if (ret != I40E_SUCCESS) {
4545                         PMD_DRV_LOG(ERR, "Failed to configure "
4546                                     "TC queue mapping");
4547                         goto fail_msix_alloc;
4548                 }
4549                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4550                 ctxt.info.valid_sections |=
4551                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4552                 /**
4553                  * Since VSI is not created yet, only configure parameter,
4554                  * will add vsi below.
4555                  */
4556
4557                 i40e_config_qinq(hw, vsi);
4558         } else if (type == I40E_VSI_VMDQ2) {
4559                 memset(&ctxt, 0, sizeof(ctxt));
4560                 /*
4561                  * For other VSI, the uplink_seid equals to uplink VSI's
4562                  * uplink_seid since they share same VEB
4563                  */
4564                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4565                 ctxt.pf_num = hw->pf_id;
4566                 ctxt.vf_num = 0;
4567                 ctxt.uplink_seid = vsi->uplink_seid;
4568                 ctxt.connection_type = 0x1;
4569                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4570
4571                 ctxt.info.valid_sections |=
4572                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4573                 /* user_param carries flag to enable loop back */
4574                 if (user_param) {
4575                         ctxt.info.switch_id =
4576                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4577                         ctxt.info.switch_id |=
4578                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4579                 }
4580
4581                 /* Configure port/vlan */
4582                 ctxt.info.valid_sections |=
4583                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4584                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4585                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4586                                                 I40E_DEFAULT_TCMAP);
4587                 if (ret != I40E_SUCCESS) {
4588                         PMD_DRV_LOG(ERR, "Failed to configure "
4589                                         "TC queue mapping");
4590                         goto fail_msix_alloc;
4591                 }
4592                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4593                 ctxt.info.valid_sections |=
4594                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4595         } else if (type == I40E_VSI_FDIR) {
4596                 memset(&ctxt, 0, sizeof(ctxt));
4597                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4598                 ctxt.pf_num = hw->pf_id;
4599                 ctxt.vf_num = 0;
4600                 ctxt.uplink_seid = vsi->uplink_seid;
4601                 ctxt.connection_type = 0x1;     /* regular data port */
4602                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4603                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4604                                                 I40E_DEFAULT_TCMAP);
4605                 if (ret != I40E_SUCCESS) {
4606                         PMD_DRV_LOG(ERR, "Failed to configure "
4607                                         "TC queue mapping.");
4608                         goto fail_msix_alloc;
4609                 }
4610                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4611                 ctxt.info.valid_sections |=
4612                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4613         } else {
4614                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4615                 goto fail_msix_alloc;
4616         }
4617
4618         if (vsi->type != I40E_VSI_MAIN) {
4619                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4620                 if (ret != I40E_SUCCESS) {
4621                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4622                                     hw->aq.asq_last_status);
4623                         goto fail_msix_alloc;
4624                 }
4625                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4626                 vsi->info.valid_sections = 0;
4627                 vsi->seid = ctxt.seid;
4628                 vsi->vsi_id = ctxt.vsi_number;
4629                 vsi->sib_vsi_list.vsi = vsi;
4630                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4631                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4632                                           &vsi->sib_vsi_list, list);
4633                 } else {
4634                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4635                                           &vsi->sib_vsi_list, list);
4636                 }
4637         }
4638
4639         /* MAC/VLAN configuration */
4640         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4641         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4642
4643         ret = i40e_vsi_add_mac(vsi, &filter);
4644         if (ret != I40E_SUCCESS) {
4645                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4646                 goto fail_msix_alloc;
4647         }
4648
4649         /* Get VSI BW information */
4650         i40e_vsi_get_bw_config(vsi);
4651         return vsi;
4652 fail_msix_alloc:
4653         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4654 fail_queue_alloc:
4655         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4656 fail_mem:
4657         rte_free(vsi);
4658         return NULL;
4659 }
4660
4661 /* Configure vlan filter on or off */
4662 int
4663 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4664 {
4665         int i, num;
4666         struct i40e_mac_filter *f;
4667         struct i40e_mac_filter_info *mac_filter;
4668         enum rte_mac_filter_type desired_filter;
4669         int ret = I40E_SUCCESS;
4670
4671         if (on) {
4672                 /* Filter to match MAC and VLAN */
4673                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4674         } else {
4675                 /* Filter to match only MAC */
4676                 desired_filter = RTE_MAC_PERFECT_MATCH;
4677         }
4678
4679         num = vsi->mac_num;
4680
4681         mac_filter = rte_zmalloc("mac_filter_info_data",
4682                                  num * sizeof(*mac_filter), 0);
4683         if (mac_filter == NULL) {
4684                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4685                 return I40E_ERR_NO_MEMORY;
4686         }
4687
4688         i = 0;
4689
4690         /* Remove all existing mac */
4691         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4692                 mac_filter[i] = f->mac_info;
4693                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4694                 if (ret) {
4695                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4696                                     on ? "enable" : "disable");
4697                         goto DONE;
4698                 }
4699                 i++;
4700         }
4701
4702         /* Override with new filter */
4703         for (i = 0; i < num; i++) {
4704                 mac_filter[i].filter_type = desired_filter;
4705                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4706                 if (ret) {
4707                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4708                                     on ? "enable" : "disable");
4709                         goto DONE;
4710                 }
4711         }
4712
4713 DONE:
4714         rte_free(mac_filter);
4715         return ret;
4716 }
4717
4718 /* Configure vlan stripping on or off */
4719 int
4720 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4721 {
4722         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4723         struct i40e_vsi_context ctxt;
4724         uint8_t vlan_flags;
4725         int ret = I40E_SUCCESS;
4726
4727         /* Check if it has been already on or off */
4728         if (vsi->info.valid_sections &
4729                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4730                 if (on) {
4731                         if ((vsi->info.port_vlan_flags &
4732                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4733                                 return 0; /* already on */
4734                 } else {
4735                         if ((vsi->info.port_vlan_flags &
4736                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4737                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4738                                 return 0; /* already off */
4739                 }
4740         }
4741
4742         if (on)
4743                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4744         else
4745                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4746         vsi->info.valid_sections =
4747                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4748         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4749         vsi->info.port_vlan_flags |= vlan_flags;
4750         ctxt.seid = vsi->seid;
4751         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4752         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4753         if (ret)
4754                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4755                             on ? "enable" : "disable");
4756
4757         return ret;
4758 }
4759
4760 static int
4761 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4762 {
4763         struct rte_eth_dev_data *data = dev->data;
4764         int ret;
4765         int mask = 0;
4766
4767         /* Apply vlan offload setting */
4768         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4769         i40e_vlan_offload_set(dev, mask);
4770
4771         /* Apply double-vlan setting, not implemented yet */
4772
4773         /* Apply pvid setting */
4774         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4775                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4776         if (ret)
4777                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4778
4779         return ret;
4780 }
4781
4782 static int
4783 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4784 {
4785         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4786
4787         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4788 }
4789
4790 static int
4791 i40e_update_flow_control(struct i40e_hw *hw)
4792 {
4793 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4794         struct i40e_link_status link_status;
4795         uint32_t rxfc = 0, txfc = 0, reg;
4796         uint8_t an_info;
4797         int ret;
4798
4799         memset(&link_status, 0, sizeof(link_status));
4800         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4801         if (ret != I40E_SUCCESS) {
4802                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4803                 goto write_reg; /* Disable flow control */
4804         }
4805
4806         an_info = hw->phy.link_info.an_info;
4807         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4808                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4809                 ret = I40E_ERR_NOT_READY;
4810                 goto write_reg; /* Disable flow control */
4811         }
4812         /**
4813          * If link auto negotiation is enabled, flow control needs to
4814          * be configured according to it
4815          */
4816         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4817         case I40E_LINK_PAUSE_RXTX:
4818                 rxfc = 1;
4819                 txfc = 1;
4820                 hw->fc.current_mode = I40E_FC_FULL;
4821                 break;
4822         case I40E_AQ_LINK_PAUSE_RX:
4823                 rxfc = 1;
4824                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4825                 break;
4826         case I40E_AQ_LINK_PAUSE_TX:
4827                 txfc = 1;
4828                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4829                 break;
4830         default:
4831                 hw->fc.current_mode = I40E_FC_NONE;
4832                 break;
4833         }
4834
4835 write_reg:
4836         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4837                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4838         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4839         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4840         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4841         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4842
4843         return ret;
4844 }
4845
4846 /* PF setup */
4847 static int
4848 i40e_pf_setup(struct i40e_pf *pf)
4849 {
4850         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4851         struct i40e_filter_control_settings settings;
4852         struct i40e_vsi *vsi;
4853         int ret;
4854
4855         /* Clear all stats counters */
4856         pf->offset_loaded = FALSE;
4857         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4858         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4859
4860         ret = i40e_pf_get_switch_config(pf);
4861         if (ret != I40E_SUCCESS) {
4862                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4863                 return ret;
4864         }
4865         if (pf->flags & I40E_FLAG_FDIR) {
4866                 /* make queue allocated first, let FDIR use queue pair 0*/
4867                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4868                 if (ret != I40E_FDIR_QUEUE_ID) {
4869                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4870                                     " ret =%d", ret);
4871                         pf->flags &= ~I40E_FLAG_FDIR;
4872                 }
4873         }
4874         /*  main VSI setup */
4875         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4876         if (!vsi) {
4877                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4878                 return I40E_ERR_NOT_READY;
4879         }
4880         pf->main_vsi = vsi;
4881
4882         /* Configure filter control */
4883         memset(&settings, 0, sizeof(settings));
4884         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4885                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4886         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4887                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4888         else {
4889                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4890                                                 hw->func_caps.rss_table_size);
4891                 return I40E_ERR_PARAM;
4892         }
4893         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4894                         "size: %u\n", hw->func_caps.rss_table_size);
4895         pf->hash_lut_size = hw->func_caps.rss_table_size;
4896
4897         /* Enable ethtype and macvlan filters */
4898         settings.enable_ethtype = TRUE;
4899         settings.enable_macvlan = TRUE;
4900         ret = i40e_set_filter_control(hw, &settings);
4901         if (ret)
4902                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4903                                                                 ret);
4904
4905         /* Update flow control according to the auto negotiation */
4906         i40e_update_flow_control(hw);
4907
4908         return I40E_SUCCESS;
4909 }
4910
4911 int
4912 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4913 {
4914         uint32_t reg;
4915         uint16_t j;
4916
4917         /**
4918          * Set or clear TX Queue Disable flags,
4919          * which is required by hardware.
4920          */
4921         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4922         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4923
4924         /* Wait until the request is finished */
4925         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4926                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4927                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4928                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4929                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4930                                                         & 0x1))) {
4931                         break;
4932                 }
4933         }
4934         if (on) {
4935                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4936                         return I40E_SUCCESS; /* already on, skip next steps */
4937
4938                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4939                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4940         } else {
4941                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4942                         return I40E_SUCCESS; /* already off, skip next steps */
4943                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4944         }
4945         /* Write the register */
4946         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4947         /* Check the result */
4948         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4949                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4950                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4951                 if (on) {
4952                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4953                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4954                                 break;
4955                 } else {
4956                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4957                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4958                                 break;
4959                 }
4960         }
4961         /* Check if it is timeout */
4962         if (j >= I40E_CHK_Q_ENA_COUNT) {
4963                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4964                             (on ? "enable" : "disable"), q_idx);
4965                 return I40E_ERR_TIMEOUT;
4966         }
4967
4968         return I40E_SUCCESS;
4969 }
4970
4971 /* Swith on or off the tx queues */
4972 static int
4973 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4974 {
4975         struct rte_eth_dev_data *dev_data = pf->dev_data;
4976         struct i40e_tx_queue *txq;
4977         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4978         uint16_t i;
4979         int ret;
4980
4981         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4982                 txq = dev_data->tx_queues[i];
4983                 /* Don't operate the queue if not configured or
4984                  * if starting only per queue */
4985                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4986                         continue;
4987                 if (on)
4988                         ret = i40e_dev_tx_queue_start(dev, i);
4989                 else
4990                         ret = i40e_dev_tx_queue_stop(dev, i);
4991                 if ( ret != I40E_SUCCESS)
4992                         return ret;
4993         }
4994
4995         return I40E_SUCCESS;
4996 }
4997
4998 int
4999 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5000 {
5001         uint32_t reg;
5002         uint16_t j;
5003
5004         /* Wait until the request is finished */
5005         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5006                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5007                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5008                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5009                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5010                         break;
5011         }
5012
5013         if (on) {
5014                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5015                         return I40E_SUCCESS; /* Already on, skip next steps */
5016                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5017         } else {
5018                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5019                         return I40E_SUCCESS; /* Already off, skip next steps */
5020                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5021         }
5022
5023         /* Write the register */
5024         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5025         /* Check the result */
5026         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5027                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5028                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5029                 if (on) {
5030                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5031                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5032                                 break;
5033                 } else {
5034                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5035                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5036                                 break;
5037                 }
5038         }
5039
5040         /* Check if it is timeout */
5041         if (j >= I40E_CHK_Q_ENA_COUNT) {
5042                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5043                             (on ? "enable" : "disable"), q_idx);
5044                 return I40E_ERR_TIMEOUT;
5045         }
5046
5047         return I40E_SUCCESS;
5048 }
5049 /* Switch on or off the rx queues */
5050 static int
5051 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5052 {
5053         struct rte_eth_dev_data *dev_data = pf->dev_data;
5054         struct i40e_rx_queue *rxq;
5055         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5056         uint16_t i;
5057         int ret;
5058
5059         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5060                 rxq = dev_data->rx_queues[i];
5061                 /* Don't operate the queue if not configured or
5062                  * if starting only per queue */
5063                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5064                         continue;
5065                 if (on)
5066                         ret = i40e_dev_rx_queue_start(dev, i);
5067                 else
5068                         ret = i40e_dev_rx_queue_stop(dev, i);
5069                 if (ret != I40E_SUCCESS)
5070                         return ret;
5071         }
5072
5073         return I40E_SUCCESS;
5074 }
5075
5076 /* Switch on or off all the rx/tx queues */
5077 int
5078 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5079 {
5080         int ret;
5081
5082         if (on) {
5083                 /* enable rx queues before enabling tx queues */
5084                 ret = i40e_dev_switch_rx_queues(pf, on);
5085                 if (ret) {
5086                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5087                         return ret;
5088                 }
5089                 ret = i40e_dev_switch_tx_queues(pf, on);
5090         } else {
5091                 /* Stop tx queues before stopping rx queues */
5092                 ret = i40e_dev_switch_tx_queues(pf, on);
5093                 if (ret) {
5094                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5095                         return ret;
5096                 }
5097                 ret = i40e_dev_switch_rx_queues(pf, on);
5098         }
5099
5100         return ret;
5101 }
5102
5103 /* Initialize VSI for TX */
5104 static int
5105 i40e_dev_tx_init(struct i40e_pf *pf)
5106 {
5107         struct rte_eth_dev_data *data = pf->dev_data;
5108         uint16_t i;
5109         uint32_t ret = I40E_SUCCESS;
5110         struct i40e_tx_queue *txq;
5111
5112         for (i = 0; i < data->nb_tx_queues; i++) {
5113                 txq = data->tx_queues[i];
5114                 if (!txq || !txq->q_set)
5115                         continue;
5116                 ret = i40e_tx_queue_init(txq);
5117                 if (ret != I40E_SUCCESS)
5118                         break;
5119         }
5120         if (ret == I40E_SUCCESS)
5121                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5122                                      ->eth_dev);
5123
5124         return ret;
5125 }
5126
5127 /* Initialize VSI for RX */
5128 static int
5129 i40e_dev_rx_init(struct i40e_pf *pf)
5130 {
5131         struct rte_eth_dev_data *data = pf->dev_data;
5132         int ret = I40E_SUCCESS;
5133         uint16_t i;
5134         struct i40e_rx_queue *rxq;
5135
5136         i40e_pf_config_mq_rx(pf);
5137         for (i = 0; i < data->nb_rx_queues; i++) {
5138                 rxq = data->rx_queues[i];
5139                 if (!rxq || !rxq->q_set)
5140                         continue;
5141
5142                 ret = i40e_rx_queue_init(rxq);
5143                 if (ret != I40E_SUCCESS) {
5144                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5145                                     "initialization");
5146                         break;
5147                 }
5148         }
5149         if (ret == I40E_SUCCESS)
5150                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5151                                      ->eth_dev);
5152
5153         return ret;
5154 }
5155
5156 static int
5157 i40e_dev_rxtx_init(struct i40e_pf *pf)
5158 {
5159         int err;
5160
5161         err = i40e_dev_tx_init(pf);
5162         if (err) {
5163                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5164                 return err;
5165         }
5166         err = i40e_dev_rx_init(pf);
5167         if (err) {
5168                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5169                 return err;
5170         }
5171
5172         return err;
5173 }
5174
5175 static int
5176 i40e_vmdq_setup(struct rte_eth_dev *dev)
5177 {
5178         struct rte_eth_conf *conf = &dev->data->dev_conf;
5179         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5180         int i, err, conf_vsis, j, loop;
5181         struct i40e_vsi *vsi;
5182         struct i40e_vmdq_info *vmdq_info;
5183         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5185
5186         /*
5187          * Disable interrupt to avoid message from VF. Furthermore, it will
5188          * avoid race condition in VSI creation/destroy.
5189          */
5190         i40e_pf_disable_irq0(hw);
5191
5192         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5193                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5194                 return -ENOTSUP;
5195         }
5196
5197         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5198         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5199                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5200                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5201                         pf->max_nb_vmdq_vsi);
5202                 return -ENOTSUP;
5203         }
5204
5205         if (pf->vmdq != NULL) {
5206                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5207                 return 0;
5208         }
5209
5210         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5211                                 sizeof(*vmdq_info) * conf_vsis, 0);
5212
5213         if (pf->vmdq == NULL) {
5214                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5215                 return -ENOMEM;
5216         }
5217
5218         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5219
5220         /* Create VMDQ VSI */
5221         for (i = 0; i < conf_vsis; i++) {
5222                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5223                                 vmdq_conf->enable_loop_back);
5224                 if (vsi == NULL) {
5225                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5226                         err = -1;
5227                         goto err_vsi_setup;
5228                 }
5229                 vmdq_info = &pf->vmdq[i];
5230                 vmdq_info->pf = pf;
5231                 vmdq_info->vsi = vsi;
5232         }
5233         pf->nb_cfg_vmdq_vsi = conf_vsis;
5234
5235         /* Configure Vlan */
5236         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5237         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5238                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5239                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5240                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5241                                         vmdq_conf->pool_map[i].vlan_id, j);
5242
5243                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5244                                                 vmdq_conf->pool_map[i].vlan_id);
5245                                 if (err) {
5246                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5247                                         err = -1;
5248                                         goto err_vsi_setup;
5249                                 }
5250                         }
5251                 }
5252         }
5253
5254         i40e_pf_enable_irq0(hw);
5255
5256         return 0;
5257
5258 err_vsi_setup:
5259         for (i = 0; i < conf_vsis; i++)
5260                 if (pf->vmdq[i].vsi == NULL)
5261                         break;
5262                 else
5263                         i40e_vsi_release(pf->vmdq[i].vsi);
5264
5265         rte_free(pf->vmdq);
5266         pf->vmdq = NULL;
5267         i40e_pf_enable_irq0(hw);
5268         return err;
5269 }
5270
5271 static void
5272 i40e_stat_update_32(struct i40e_hw *hw,
5273                    uint32_t reg,
5274                    bool offset_loaded,
5275                    uint64_t *offset,
5276                    uint64_t *stat)
5277 {
5278         uint64_t new_data;
5279
5280         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5281         if (!offset_loaded)
5282                 *offset = new_data;
5283
5284         if (new_data >= *offset)
5285                 *stat = (uint64_t)(new_data - *offset);
5286         else
5287                 *stat = (uint64_t)((new_data +
5288                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5289 }
5290
5291 static void
5292 i40e_stat_update_48(struct i40e_hw *hw,
5293                    uint32_t hireg,
5294                    uint32_t loreg,
5295                    bool offset_loaded,
5296                    uint64_t *offset,
5297                    uint64_t *stat)
5298 {
5299         uint64_t new_data;
5300
5301         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5302         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5303                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5304
5305         if (!offset_loaded)
5306                 *offset = new_data;
5307
5308         if (new_data >= *offset)
5309                 *stat = new_data - *offset;
5310         else
5311                 *stat = (uint64_t)((new_data +
5312                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5313
5314         *stat &= I40E_48_BIT_MASK;
5315 }
5316
5317 /* Disable IRQ0 */
5318 void
5319 i40e_pf_disable_irq0(struct i40e_hw *hw)
5320 {
5321         /* Disable all interrupt types */
5322         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5323         I40E_WRITE_FLUSH(hw);
5324 }
5325
5326 /* Enable IRQ0 */
5327 void
5328 i40e_pf_enable_irq0(struct i40e_hw *hw)
5329 {
5330         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5331                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5332                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5333                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5334         I40E_WRITE_FLUSH(hw);
5335 }
5336
5337 static void
5338 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5339 {
5340         /* read pending request and disable first */
5341         i40e_pf_disable_irq0(hw);
5342         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5343         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5344                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5345
5346         if (no_queue)
5347                 /* Link no queues with irq0 */
5348                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5349                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5350 }
5351
5352 static void
5353 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5354 {
5355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5357         int i;
5358         uint16_t abs_vf_id;
5359         uint32_t index, offset, val;
5360
5361         if (!pf->vfs)
5362                 return;
5363         /**
5364          * Try to find which VF trigger a reset, use absolute VF id to access
5365          * since the reg is global register.
5366          */
5367         for (i = 0; i < pf->vf_num; i++) {
5368                 abs_vf_id = hw->func_caps.vf_base_id + i;
5369                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5370                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5371                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5372                 /* VFR event occured */
5373                 if (val & (0x1 << offset)) {
5374                         int ret;
5375
5376                         /* Clear the event first */
5377                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5378                                                         (0x1 << offset));
5379                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5380                         /**
5381                          * Only notify a VF reset event occured,
5382                          * don't trigger another SW reset
5383                          */
5384                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5385                         if (ret != I40E_SUCCESS)
5386                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5387                 }
5388         }
5389 }
5390
5391 static void
5392 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5393 {
5394         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         struct i40e_arq_event_info info;
5396         uint16_t pending, opcode;
5397         int ret;
5398
5399         info.buf_len = I40E_AQ_BUF_SZ;
5400         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5401         if (!info.msg_buf) {
5402                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5403                 return;
5404         }
5405
5406         pending = 1;
5407         while (pending) {
5408                 ret = i40e_clean_arq_element(hw, &info, &pending);
5409
5410                 if (ret != I40E_SUCCESS) {
5411                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5412                                     "aq_err: %u", hw->aq.asq_last_status);
5413                         break;
5414                 }
5415                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5416
5417                 switch (opcode) {
5418                 case i40e_aqc_opc_send_msg_to_pf:
5419                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5420                         i40e_pf_host_handle_vf_msg(dev,
5421                                         rte_le_to_cpu_16(info.desc.retval),
5422                                         rte_le_to_cpu_32(info.desc.cookie_high),
5423                                         rte_le_to_cpu_32(info.desc.cookie_low),
5424                                         info.msg_buf,
5425                                         info.msg_len);
5426                         break;
5427                 default:
5428                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5429                                     opcode);
5430                         break;
5431                 }
5432         }
5433         rte_free(info.msg_buf);
5434 }
5435
5436 /*
5437  * Interrupt handler is registered as the alarm callback for handling LSC
5438  * interrupt in a definite of time, in order to wait the NIC into a stable
5439  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5440  * no need for link down interrupt.
5441  */
5442 static void
5443 i40e_dev_interrupt_delayed_handler(void *param)
5444 {
5445         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5446         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447         uint32_t icr0;
5448
5449         /* read interrupt causes again */
5450         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5451
5452 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5453         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5454                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5455         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5456                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5457         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5458                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5459         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5460                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5461         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5462                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5463                                                                 "state\n");
5464         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5465                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5466         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5467                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5468 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5469
5470         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5471                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5472                 i40e_dev_handle_vfr_event(dev);
5473         }
5474         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5475                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5476                 i40e_dev_handle_aq_msg(dev);
5477         }
5478
5479         /* handle the link up interrupt in an alarm callback */
5480         i40e_dev_link_update(dev, 0);
5481         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5482
5483         i40e_pf_enable_irq0(hw);
5484         rte_intr_enable(&(dev->pci_dev->intr_handle));
5485 }
5486
5487 /**
5488  * Interrupt handler triggered by NIC  for handling
5489  * specific interrupt.
5490  *
5491  * @param handle
5492  *  Pointer to interrupt handle.
5493  * @param param
5494  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5495  *
5496  * @return
5497  *  void
5498  */
5499 static void
5500 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5501                            void *param)
5502 {
5503         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5505         uint32_t icr0;
5506
5507         /* Disable interrupt */
5508         i40e_pf_disable_irq0(hw);
5509
5510         /* read out interrupt causes */
5511         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5512
5513         /* No interrupt event indicated */
5514         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5515                 PMD_DRV_LOG(INFO, "No interrupt event");
5516                 goto done;
5517         }
5518 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5519         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5520                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5521         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5522                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5523         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5524                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5525         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5526                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5527         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5528                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5529         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5530                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5531         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5532                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5533 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5534
5535         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5536                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5537                 i40e_dev_handle_vfr_event(dev);
5538         }
5539         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5540                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5541                 i40e_dev_handle_aq_msg(dev);
5542         }
5543
5544         /* Link Status Change interrupt */
5545         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5546 #define I40E_US_PER_SECOND 1000000
5547                 struct rte_eth_link link;
5548
5549                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5550                 memset(&link, 0, sizeof(link));
5551                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5552                 i40e_dev_link_update(dev, 0);
5553
5554                 /*
5555                  * For link up interrupt, it needs to wait 1 second to let the
5556                  * hardware be a stable state. Otherwise several consecutive
5557                  * interrupts can be observed.
5558                  * For link down interrupt, no need to wait.
5559                  */
5560                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5561                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5562                         return;
5563                 else
5564                         _rte_eth_dev_callback_process(dev,
5565                                 RTE_ETH_EVENT_INTR_LSC);
5566         }
5567
5568 done:
5569         /* Enable interrupt */
5570         i40e_pf_enable_irq0(hw);
5571         rte_intr_enable(&(dev->pci_dev->intr_handle));
5572 }
5573
5574 static int
5575 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5576                          struct i40e_macvlan_filter *filter,
5577                          int total)
5578 {
5579         int ele_num, ele_buff_size;
5580         int num, actual_num, i;
5581         uint16_t flags;
5582         int ret = I40E_SUCCESS;
5583         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5584         struct i40e_aqc_add_macvlan_element_data *req_list;
5585
5586         if (filter == NULL  || total == 0)
5587                 return I40E_ERR_PARAM;
5588         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5589         ele_buff_size = hw->aq.asq_buf_size;
5590
5591         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5592         if (req_list == NULL) {
5593                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5594                 return I40E_ERR_NO_MEMORY;
5595         }
5596
5597         num = 0;
5598         do {
5599                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5600                 memset(req_list, 0, ele_buff_size);
5601
5602                 for (i = 0; i < actual_num; i++) {
5603                         (void)rte_memcpy(req_list[i].mac_addr,
5604                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5605                         req_list[i].vlan_tag =
5606                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5607
5608                         switch (filter[num + i].filter_type) {
5609                         case RTE_MAC_PERFECT_MATCH:
5610                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5611                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5612                                 break;
5613                         case RTE_MACVLAN_PERFECT_MATCH:
5614                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5615                                 break;
5616                         case RTE_MAC_HASH_MATCH:
5617                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5618                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5619                                 break;
5620                         case RTE_MACVLAN_HASH_MATCH:
5621                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5622                                 break;
5623                         default:
5624                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5625                                 ret = I40E_ERR_PARAM;
5626                                 goto DONE;
5627                         }
5628
5629                         req_list[i].queue_number = 0;
5630
5631                         req_list[i].flags = rte_cpu_to_le_16(flags);
5632                 }
5633
5634                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5635                                                 actual_num, NULL);
5636                 if (ret != I40E_SUCCESS) {
5637                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5638                         goto DONE;
5639                 }
5640                 num += actual_num;
5641         } while (num < total);
5642
5643 DONE:
5644         rte_free(req_list);
5645         return ret;
5646 }
5647
5648 static int
5649 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5650                             struct i40e_macvlan_filter *filter,
5651                             int total)
5652 {
5653         int ele_num, ele_buff_size;
5654         int num, actual_num, i;
5655         uint16_t flags;
5656         int ret = I40E_SUCCESS;
5657         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5658         struct i40e_aqc_remove_macvlan_element_data *req_list;
5659
5660         if (filter == NULL  || total == 0)
5661                 return I40E_ERR_PARAM;
5662
5663         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5664         ele_buff_size = hw->aq.asq_buf_size;
5665
5666         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5667         if (req_list == NULL) {
5668                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5669                 return I40E_ERR_NO_MEMORY;
5670         }
5671
5672         num = 0;
5673         do {
5674                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5675                 memset(req_list, 0, ele_buff_size);
5676
5677                 for (i = 0; i < actual_num; i++) {
5678                         (void)rte_memcpy(req_list[i].mac_addr,
5679                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5680                         req_list[i].vlan_tag =
5681                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5682
5683                         switch (filter[num + i].filter_type) {
5684                         case RTE_MAC_PERFECT_MATCH:
5685                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5686                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5687                                 break;
5688                         case RTE_MACVLAN_PERFECT_MATCH:
5689                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5690                                 break;
5691                         case RTE_MAC_HASH_MATCH:
5692                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5693                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5694                                 break;
5695                         case RTE_MACVLAN_HASH_MATCH:
5696                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5697                                 break;
5698                         default:
5699                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5700                                 ret = I40E_ERR_PARAM;
5701                                 goto DONE;
5702                         }
5703                         req_list[i].flags = rte_cpu_to_le_16(flags);
5704                 }
5705
5706                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5707                                                 actual_num, NULL);
5708                 if (ret != I40E_SUCCESS) {
5709                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5710                         goto DONE;
5711                 }
5712                 num += actual_num;
5713         } while (num < total);
5714
5715 DONE:
5716         rte_free(req_list);
5717         return ret;
5718 }
5719
5720 /* Find out specific MAC filter */
5721 static struct i40e_mac_filter *
5722 i40e_find_mac_filter(struct i40e_vsi *vsi,
5723                          struct ether_addr *macaddr)
5724 {
5725         struct i40e_mac_filter *f;
5726
5727         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5728                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5729                         return f;
5730         }
5731
5732         return NULL;
5733 }
5734
5735 static bool
5736 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5737                          uint16_t vlan_id)
5738 {
5739         uint32_t vid_idx, vid_bit;
5740
5741         if (vlan_id > ETH_VLAN_ID_MAX)
5742                 return 0;
5743
5744         vid_idx = I40E_VFTA_IDX(vlan_id);
5745         vid_bit = I40E_VFTA_BIT(vlan_id);
5746
5747         if (vsi->vfta[vid_idx] & vid_bit)
5748                 return 1;
5749         else
5750                 return 0;
5751 }
5752
5753 static void
5754 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5755                          uint16_t vlan_id, bool on)
5756 {
5757         uint32_t vid_idx, vid_bit;
5758         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5759         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
5760         int ret;
5761
5762         if (vlan_id > ETH_VLAN_ID_MAX)
5763                 return;
5764
5765         vid_idx = I40E_VFTA_IDX(vlan_id);
5766         vid_bit = I40E_VFTA_BIT(vlan_id);
5767         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
5768
5769         if (on) {
5770                 ret = i40e_aq_add_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
5771                 if (ret != I40E_SUCCESS)
5772                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
5773                 vsi->vfta[vid_idx] |= vid_bit;
5774         } else {
5775                 ret = i40e_aq_remove_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
5776                 if (ret != I40E_SUCCESS)
5777                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
5778                 vsi->vfta[vid_idx] &= ~vid_bit;
5779         }
5780 }
5781
5782 /**
5783  * Find all vlan options for specific mac addr,
5784  * return with actual vlan found.
5785  */
5786 static inline int
5787 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5788                            struct i40e_macvlan_filter *mv_f,
5789                            int num, struct ether_addr *addr)
5790 {
5791         int i;
5792         uint32_t j, k;
5793
5794         /**
5795          * Not to use i40e_find_vlan_filter to decrease the loop time,
5796          * although the code looks complex.
5797           */
5798         if (num < vsi->vlan_num)
5799                 return I40E_ERR_PARAM;
5800
5801         i = 0;
5802         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5803                 if (vsi->vfta[j]) {
5804                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5805                                 if (vsi->vfta[j] & (1 << k)) {
5806                                         if (i > num - 1) {
5807                                                 PMD_DRV_LOG(ERR, "vlan number "
5808                                                             "not match");
5809                                                 return I40E_ERR_PARAM;
5810                                         }
5811                                         (void)rte_memcpy(&mv_f[i].macaddr,
5812                                                         addr, ETH_ADDR_LEN);
5813                                         mv_f[i].vlan_id =
5814                                                 j * I40E_UINT32_BIT_SIZE + k;
5815                                         i++;
5816                                 }
5817                         }
5818                 }
5819         }
5820         return I40E_SUCCESS;
5821 }
5822
5823 static inline int
5824 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5825                            struct i40e_macvlan_filter *mv_f,
5826                            int num,
5827                            uint16_t vlan)
5828 {
5829         int i = 0;
5830         struct i40e_mac_filter *f;
5831
5832         if (num < vsi->mac_num)
5833                 return I40E_ERR_PARAM;
5834
5835         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5836                 if (i > num - 1) {
5837                         PMD_DRV_LOG(ERR, "buffer number not match");
5838                         return I40E_ERR_PARAM;
5839                 }
5840                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5841                                 ETH_ADDR_LEN);
5842                 mv_f[i].vlan_id = vlan;
5843                 mv_f[i].filter_type = f->mac_info.filter_type;
5844                 i++;
5845         }
5846
5847         return I40E_SUCCESS;
5848 }
5849
5850 static int
5851 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5852 {
5853         int i, num;
5854         struct i40e_mac_filter *f;
5855         struct i40e_macvlan_filter *mv_f;
5856         int ret = I40E_SUCCESS;
5857
5858         if (vsi == NULL || vsi->mac_num == 0)
5859                 return I40E_ERR_PARAM;
5860
5861         /* Case that no vlan is set */
5862         if (vsi->vlan_num == 0)
5863                 num = vsi->mac_num;
5864         else
5865                 num = vsi->mac_num * vsi->vlan_num;
5866
5867         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5868         if (mv_f == NULL) {
5869                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5870                 return I40E_ERR_NO_MEMORY;
5871         }
5872
5873         i = 0;
5874         if (vsi->vlan_num == 0) {
5875                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5876                         (void)rte_memcpy(&mv_f[i].macaddr,
5877                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5878                         mv_f[i].vlan_id = 0;
5879                         i++;
5880                 }
5881         } else {
5882                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5883                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5884                                         vsi->vlan_num, &f->mac_info.mac_addr);
5885                         if (ret != I40E_SUCCESS)
5886                                 goto DONE;
5887                         i += vsi->vlan_num;
5888                 }
5889         }
5890
5891         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5892 DONE:
5893         rte_free(mv_f);
5894
5895         return ret;
5896 }
5897
5898 int
5899 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5900 {
5901         struct i40e_macvlan_filter *mv_f;
5902         int mac_num;
5903         int ret = I40E_SUCCESS;
5904
5905         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5906                 return I40E_ERR_PARAM;
5907
5908         /* If it's already set, just return */
5909         if (i40e_find_vlan_filter(vsi,vlan))
5910                 return I40E_SUCCESS;
5911
5912         mac_num = vsi->mac_num;
5913
5914         if (mac_num == 0) {
5915                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5916                 return I40E_ERR_PARAM;
5917         }
5918
5919         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5920
5921         if (mv_f == NULL) {
5922                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5923                 return I40E_ERR_NO_MEMORY;
5924         }
5925
5926         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5927
5928         if (ret != I40E_SUCCESS)
5929                 goto DONE;
5930
5931         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5932
5933         if (ret != I40E_SUCCESS)
5934                 goto DONE;
5935
5936         i40e_set_vlan_filter(vsi, vlan, 1);
5937
5938         vsi->vlan_num++;
5939         ret = I40E_SUCCESS;
5940 DONE:
5941         rte_free(mv_f);
5942         return ret;
5943 }
5944
5945 int
5946 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5947 {
5948         struct i40e_macvlan_filter *mv_f;
5949         int mac_num;
5950         int ret = I40E_SUCCESS;
5951
5952         /**
5953          * Vlan 0 is the generic filter for untagged packets
5954          * and can't be removed.
5955          */
5956         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5957                 return I40E_ERR_PARAM;
5958
5959         /* If can't find it, just return */
5960         if (!i40e_find_vlan_filter(vsi, vlan))
5961                 return I40E_ERR_PARAM;
5962
5963         mac_num = vsi->mac_num;
5964
5965         if (mac_num == 0) {
5966                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5967                 return I40E_ERR_PARAM;
5968         }
5969
5970         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5971
5972         if (mv_f == NULL) {
5973                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5974                 return I40E_ERR_NO_MEMORY;
5975         }
5976
5977         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5978
5979         if (ret != I40E_SUCCESS)
5980                 goto DONE;
5981
5982         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5983
5984         if (ret != I40E_SUCCESS)
5985                 goto DONE;
5986
5987         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5988         if (vsi->vlan_num == 1) {
5989                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5990                 if (ret != I40E_SUCCESS)
5991                         goto DONE;
5992
5993                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5994                 if (ret != I40E_SUCCESS)
5995                         goto DONE;
5996         }
5997
5998         i40e_set_vlan_filter(vsi, vlan, 0);
5999
6000         vsi->vlan_num--;
6001         ret = I40E_SUCCESS;
6002 DONE:
6003         rte_free(mv_f);
6004         return ret;
6005 }
6006
6007 int
6008 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6009 {
6010         struct i40e_mac_filter *f;
6011         struct i40e_macvlan_filter *mv_f;
6012         int i, vlan_num = 0;
6013         int ret = I40E_SUCCESS;
6014
6015         /* If it's add and we've config it, return */
6016         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6017         if (f != NULL)
6018                 return I40E_SUCCESS;
6019         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6020                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6021
6022                 /**
6023                  * If vlan_num is 0, that's the first time to add mac,
6024                  * set mask for vlan_id 0.
6025                  */
6026                 if (vsi->vlan_num == 0) {
6027                         i40e_set_vlan_filter(vsi, 0, 1);
6028                         vsi->vlan_num = 1;
6029                 }
6030                 vlan_num = vsi->vlan_num;
6031         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6032                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6033                 vlan_num = 1;
6034
6035         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6036         if (mv_f == NULL) {
6037                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6038                 return I40E_ERR_NO_MEMORY;
6039         }
6040
6041         for (i = 0; i < vlan_num; i++) {
6042                 mv_f[i].filter_type = mac_filter->filter_type;
6043                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6044                                 ETH_ADDR_LEN);
6045         }
6046
6047         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6048                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6049                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6050                                         &mac_filter->mac_addr);
6051                 if (ret != I40E_SUCCESS)
6052                         goto DONE;
6053         }
6054
6055         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6056         if (ret != I40E_SUCCESS)
6057                 goto DONE;
6058
6059         /* Add the mac addr into mac list */
6060         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6061         if (f == NULL) {
6062                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6063                 ret = I40E_ERR_NO_MEMORY;
6064                 goto DONE;
6065         }
6066         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6067                         ETH_ADDR_LEN);
6068         f->mac_info.filter_type = mac_filter->filter_type;
6069         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6070         vsi->mac_num++;
6071
6072         ret = I40E_SUCCESS;
6073 DONE:
6074         rte_free(mv_f);
6075
6076         return ret;
6077 }
6078
6079 int
6080 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6081 {
6082         struct i40e_mac_filter *f;
6083         struct i40e_macvlan_filter *mv_f;
6084         int i, vlan_num;
6085         enum rte_mac_filter_type filter_type;
6086         int ret = I40E_SUCCESS;
6087
6088         /* Can't find it, return an error */
6089         f = i40e_find_mac_filter(vsi, addr);
6090         if (f == NULL)
6091                 return I40E_ERR_PARAM;
6092
6093         vlan_num = vsi->vlan_num;
6094         filter_type = f->mac_info.filter_type;
6095         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6096                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6097                 if (vlan_num == 0) {
6098                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6099                         return I40E_ERR_PARAM;
6100                 }
6101         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6102                         filter_type == RTE_MAC_HASH_MATCH)
6103                 vlan_num = 1;
6104
6105         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6106         if (mv_f == NULL) {
6107                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6108                 return I40E_ERR_NO_MEMORY;
6109         }
6110
6111         for (i = 0; i < vlan_num; i++) {
6112                 mv_f[i].filter_type = filter_type;
6113                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6114                                 ETH_ADDR_LEN);
6115         }
6116         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6117                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6118                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6119                 if (ret != I40E_SUCCESS)
6120                         goto DONE;
6121         }
6122
6123         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6124         if (ret != I40E_SUCCESS)
6125                 goto DONE;
6126
6127         /* Remove the mac addr into mac list */
6128         TAILQ_REMOVE(&vsi->mac_list, f, next);
6129         rte_free(f);
6130         vsi->mac_num--;
6131
6132         ret = I40E_SUCCESS;
6133 DONE:
6134         rte_free(mv_f);
6135         return ret;
6136 }
6137
6138 /* Configure hash enable flags for RSS */
6139 uint64_t
6140 i40e_config_hena(uint64_t flags)
6141 {
6142         uint64_t hena = 0;
6143
6144         if (!flags)
6145                 return hena;
6146
6147         if (flags & ETH_RSS_FRAG_IPV4)
6148                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6149         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6150                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6151         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6152                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6153         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6154                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6155         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6156                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6157         if (flags & ETH_RSS_FRAG_IPV6)
6158                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6159         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6160                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6161         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6162                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6163         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6164                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6165         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6166                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6167         if (flags & ETH_RSS_L2_PAYLOAD)
6168                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6169
6170         return hena;
6171 }
6172
6173 /* Parse the hash enable flags */
6174 uint64_t
6175 i40e_parse_hena(uint64_t flags)
6176 {
6177         uint64_t rss_hf = 0;
6178
6179         if (!flags)
6180                 return rss_hf;
6181         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6182                 rss_hf |= ETH_RSS_FRAG_IPV4;
6183         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6184                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6185         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6186                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6187         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6188                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6189         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6190                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6191         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6192                 rss_hf |= ETH_RSS_FRAG_IPV6;
6193         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6194                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6195         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6196                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6197         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6198                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6199         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6200                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6201         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6202                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6203
6204         return rss_hf;
6205 }
6206
6207 /* Disable RSS */
6208 static void
6209 i40e_pf_disable_rss(struct i40e_pf *pf)
6210 {
6211         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6212         uint64_t hena;
6213
6214         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6215         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6216         hena &= ~I40E_RSS_HENA_ALL;
6217         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6218         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6219         I40E_WRITE_FLUSH(hw);
6220 }
6221
6222 static int
6223 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6224 {
6225         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6226         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6227         int ret = 0;
6228
6229         if (!key || key_len == 0) {
6230                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6231                 return 0;
6232         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6233                 sizeof(uint32_t)) {
6234                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6235                 return -EINVAL;
6236         }
6237
6238         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6239                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6240                         (struct i40e_aqc_get_set_rss_key_data *)key;
6241
6242                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6243                 if (ret)
6244                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6245                                      "via AQ");
6246         } else {
6247                 uint32_t *hash_key = (uint32_t *)key;
6248                 uint16_t i;
6249
6250                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6251                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6252                 I40E_WRITE_FLUSH(hw);
6253         }
6254
6255         return ret;
6256 }
6257
6258 static int
6259 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6260 {
6261         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6262         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6263         int ret;
6264
6265         if (!key || !key_len)
6266                 return -EINVAL;
6267
6268         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6269                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6270                         (struct i40e_aqc_get_set_rss_key_data *)key);
6271                 if (ret) {
6272                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6273                         return ret;
6274                 }
6275         } else {
6276                 uint32_t *key_dw = (uint32_t *)key;
6277                 uint16_t i;
6278
6279                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6280                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6281         }
6282         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6283
6284         return 0;
6285 }
6286
6287 static int
6288 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6289 {
6290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6291         uint64_t rss_hf;
6292         uint64_t hena;
6293         int ret;
6294
6295         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6296                                rss_conf->rss_key_len);
6297         if (ret)
6298                 return ret;
6299
6300         rss_hf = rss_conf->rss_hf;
6301         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6302         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6303         hena &= ~I40E_RSS_HENA_ALL;
6304         hena |= i40e_config_hena(rss_hf);
6305         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6306         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6307         I40E_WRITE_FLUSH(hw);
6308
6309         return 0;
6310 }
6311
6312 static int
6313 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6314                          struct rte_eth_rss_conf *rss_conf)
6315 {
6316         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6317         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6318         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6319         uint64_t hena;
6320
6321         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6322         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6323         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6324                 if (rss_hf != 0) /* Enable RSS */
6325                         return -EINVAL;
6326                 return 0; /* Nothing to do */
6327         }
6328         /* RSS enabled */
6329         if (rss_hf == 0) /* Disable RSS */
6330                 return -EINVAL;
6331
6332         return i40e_hw_rss_hash_set(pf, rss_conf);
6333 }
6334
6335 static int
6336 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6337                            struct rte_eth_rss_conf *rss_conf)
6338 {
6339         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6340         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6341         uint64_t hena;
6342
6343         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6344                          &rss_conf->rss_key_len);
6345
6346         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6347         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6348         rss_conf->rss_hf = i40e_parse_hena(hena);
6349
6350         return 0;
6351 }
6352
6353 static int
6354 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6355 {
6356         switch (filter_type) {
6357         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6358                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6359                 break;
6360         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6361                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6362                 break;
6363         case RTE_TUNNEL_FILTER_IMAC_TENID:
6364                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6365                 break;
6366         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6367                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6368                 break;
6369         case ETH_TUNNEL_FILTER_IMAC:
6370                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6371                 break;
6372         case ETH_TUNNEL_FILTER_OIP:
6373                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6374                 break;
6375         case ETH_TUNNEL_FILTER_IIP:
6376                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6377                 break;
6378         default:
6379                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6380                 return -EINVAL;
6381         }
6382
6383         return 0;
6384 }
6385
6386 static int
6387 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6388                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6389                         uint8_t add)
6390 {
6391         uint16_t ip_type;
6392         uint32_t ipv4_addr;
6393         uint8_t i, tun_type = 0;
6394         /* internal varialbe to convert ipv6 byte order */
6395         uint32_t convert_ipv6[4];
6396         int val, ret = 0;
6397         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6398         struct i40e_vsi *vsi = pf->main_vsi;
6399         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6400         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6401
6402         cld_filter = rte_zmalloc("tunnel_filter",
6403                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6404                 0);
6405
6406         if (NULL == cld_filter) {
6407                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6408                 return -EINVAL;
6409         }
6410         pfilter = cld_filter;
6411
6412         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6413         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6414
6415         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6416         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6417                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6418                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6419                 rte_memcpy(&pfilter->ipaddr.v4.data,
6420                                 &rte_cpu_to_le_32(ipv4_addr),
6421                                 sizeof(pfilter->ipaddr.v4.data));
6422         } else {
6423                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6424                 for (i = 0; i < 4; i++) {
6425                         convert_ipv6[i] =
6426                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6427                 }
6428                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6429                                 sizeof(pfilter->ipaddr.v6.data));
6430         }
6431
6432         /* check tunneled type */
6433         switch (tunnel_filter->tunnel_type) {
6434         case RTE_TUNNEL_TYPE_VXLAN:
6435                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6436                 break;
6437         case RTE_TUNNEL_TYPE_NVGRE:
6438                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6439                 break;
6440         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6441                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6442                 break;
6443         default:
6444                 /* Other tunnel types is not supported. */
6445                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6446                 rte_free(cld_filter);
6447                 return -EINVAL;
6448         }
6449
6450         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6451                                                 &pfilter->flags);
6452         if (val < 0) {
6453                 rte_free(cld_filter);
6454                 return -EINVAL;
6455         }
6456
6457         pfilter->flags |= rte_cpu_to_le_16(
6458                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6459                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6460         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6461         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6462
6463         if (add)
6464                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6465         else
6466                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6467                                                 cld_filter, 1);
6468
6469         rte_free(cld_filter);
6470         return ret;
6471 }
6472
6473 static int
6474 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6475 {
6476         uint8_t i;
6477
6478         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6479                 if (pf->vxlan_ports[i] == port)
6480                         return i;
6481         }
6482
6483         return -1;
6484 }
6485
6486 static int
6487 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6488 {
6489         int  idx, ret;
6490         uint8_t filter_idx;
6491         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6492
6493         idx = i40e_get_vxlan_port_idx(pf, port);
6494
6495         /* Check if port already exists */
6496         if (idx >= 0) {
6497                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6498                 return -EINVAL;
6499         }
6500
6501         /* Now check if there is space to add the new port */
6502         idx = i40e_get_vxlan_port_idx(pf, 0);
6503         if (idx < 0) {
6504                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6505                         "not adding port %d", port);
6506                 return -ENOSPC;
6507         }
6508
6509         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6510                                         &filter_idx, NULL);
6511         if (ret < 0) {
6512                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6513                 return -1;
6514         }
6515
6516         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6517                          port,  filter_idx);
6518
6519         /* New port: add it and mark its index in the bitmap */
6520         pf->vxlan_ports[idx] = port;
6521         pf->vxlan_bitmap |= (1 << idx);
6522
6523         if (!(pf->flags & I40E_FLAG_VXLAN))
6524                 pf->flags |= I40E_FLAG_VXLAN;
6525
6526         return 0;
6527 }
6528
6529 static int
6530 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6531 {
6532         int idx;
6533         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6534
6535         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6536                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6537                 return -EINVAL;
6538         }
6539
6540         idx = i40e_get_vxlan_port_idx(pf, port);
6541
6542         if (idx < 0) {
6543                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6544                 return -EINVAL;
6545         }
6546
6547         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6548                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6549                 return -1;
6550         }
6551
6552         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6553                         port, idx);
6554
6555         pf->vxlan_ports[idx] = 0;
6556         pf->vxlan_bitmap &= ~(1 << idx);
6557
6558         if (!pf->vxlan_bitmap)
6559                 pf->flags &= ~I40E_FLAG_VXLAN;
6560
6561         return 0;
6562 }
6563
6564 /* Add UDP tunneling port */
6565 static int
6566 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6567                              struct rte_eth_udp_tunnel *udp_tunnel)
6568 {
6569         int ret = 0;
6570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6571
6572         if (udp_tunnel == NULL)
6573                 return -EINVAL;
6574
6575         switch (udp_tunnel->prot_type) {
6576         case RTE_TUNNEL_TYPE_VXLAN:
6577                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6578                 break;
6579
6580         case RTE_TUNNEL_TYPE_GENEVE:
6581         case RTE_TUNNEL_TYPE_TEREDO:
6582                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6583                 ret = -1;
6584                 break;
6585
6586         default:
6587                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6588                 ret = -1;
6589                 break;
6590         }
6591
6592         return ret;
6593 }
6594
6595 /* Remove UDP tunneling port */
6596 static int
6597 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6598                              struct rte_eth_udp_tunnel *udp_tunnel)
6599 {
6600         int ret = 0;
6601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6602
6603         if (udp_tunnel == NULL)
6604                 return -EINVAL;
6605
6606         switch (udp_tunnel->prot_type) {
6607         case RTE_TUNNEL_TYPE_VXLAN:
6608                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6609                 break;
6610         case RTE_TUNNEL_TYPE_GENEVE:
6611         case RTE_TUNNEL_TYPE_TEREDO:
6612                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6613                 ret = -1;
6614                 break;
6615         default:
6616                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6617                 ret = -1;
6618                 break;
6619         }
6620
6621         return ret;
6622 }
6623
6624 /* Calculate the maximum number of contiguous PF queues that are configured */
6625 static int
6626 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6627 {
6628         struct rte_eth_dev_data *data = pf->dev_data;
6629         int i, num;
6630         struct i40e_rx_queue *rxq;
6631
6632         num = 0;
6633         for (i = 0; i < pf->lan_nb_qps; i++) {
6634                 rxq = data->rx_queues[i];
6635                 if (rxq && rxq->q_set)
6636                         num++;
6637                 else
6638                         break;
6639         }
6640
6641         return num;
6642 }
6643
6644 /* Configure RSS */
6645 static int
6646 i40e_pf_config_rss(struct i40e_pf *pf)
6647 {
6648         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6649         struct rte_eth_rss_conf rss_conf;
6650         uint32_t i, lut = 0;
6651         uint16_t j, num;
6652
6653         /*
6654          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6655          * It's necessary to calulate the actual PF queues that are configured.
6656          */
6657         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6658                 num = i40e_pf_calc_configured_queues_num(pf);
6659         else
6660                 num = pf->dev_data->nb_rx_queues;
6661
6662         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6663         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6664                         num);
6665
6666         if (num == 0) {
6667                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6668                 return -ENOTSUP;
6669         }
6670
6671         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6672                 if (j == num)
6673                         j = 0;
6674                 lut = (lut << 8) | (j & ((0x1 <<
6675                         hw->func_caps.rss_table_entry_width) - 1));
6676                 if ((i & 3) == 3)
6677                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6678         }
6679
6680         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6681         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6682                 i40e_pf_disable_rss(pf);
6683                 return 0;
6684         }
6685         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6686                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6687                 /* Random default keys */
6688                 static uint32_t rss_key_default[] = {0x6b793944,
6689                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6690                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6691                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6692
6693                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6694                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6695                                                         sizeof(uint32_t);
6696         }
6697
6698         return i40e_hw_rss_hash_set(pf, &rss_conf);
6699 }
6700
6701 static int
6702 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6703                                struct rte_eth_tunnel_filter_conf *filter)
6704 {
6705         if (pf == NULL || filter == NULL) {
6706                 PMD_DRV_LOG(ERR, "Invalid parameter");
6707                 return -EINVAL;
6708         }
6709
6710         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6711                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6712                 return -EINVAL;
6713         }
6714
6715         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6716                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6717                 return -EINVAL;
6718         }
6719
6720         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6721                 (is_zero_ether_addr(&filter->outer_mac))) {
6722                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6723                 return -EINVAL;
6724         }
6725
6726         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6727                 (is_zero_ether_addr(&filter->inner_mac))) {
6728                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6729                 return -EINVAL;
6730         }
6731
6732         return 0;
6733 }
6734
6735 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6736 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6737 static int
6738 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6739 {
6740         uint32_t val, reg;
6741         int ret = -EINVAL;
6742
6743         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6744         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6745
6746         if (len == 3) {
6747                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6748         } else if (len == 4) {
6749                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6750         } else {
6751                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6752                 return ret;
6753         }
6754
6755         if (reg != val) {
6756                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6757                                                    reg, NULL);
6758                 if (ret != 0)
6759                         return ret;
6760         } else {
6761                 ret = 0;
6762         }
6763         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6764                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6765
6766         return ret;
6767 }
6768
6769 static int
6770 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6771 {
6772         int ret = -EINVAL;
6773
6774         if (!hw || !cfg)
6775                 return -EINVAL;
6776
6777         switch (cfg->cfg_type) {
6778         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6779                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6780                 break;
6781         default:
6782                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6783                 break;
6784         }
6785
6786         return ret;
6787 }
6788
6789 static int
6790 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6791                                enum rte_filter_op filter_op,
6792                                void *arg)
6793 {
6794         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6795         int ret = I40E_ERR_PARAM;
6796
6797         switch (filter_op) {
6798         case RTE_ETH_FILTER_SET:
6799                 ret = i40e_dev_global_config_set(hw,
6800                         (struct rte_eth_global_cfg *)arg);
6801                 break;
6802         default:
6803                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6804                 break;
6805         }
6806
6807         return ret;
6808 }
6809
6810 static int
6811 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6812                           enum rte_filter_op filter_op,
6813                           void *arg)
6814 {
6815         struct rte_eth_tunnel_filter_conf *filter;
6816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6817         int ret = I40E_SUCCESS;
6818
6819         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6820
6821         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6822                 return I40E_ERR_PARAM;
6823
6824         switch (filter_op) {
6825         case RTE_ETH_FILTER_NOP:
6826                 if (!(pf->flags & I40E_FLAG_VXLAN))
6827                         ret = I40E_NOT_SUPPORTED;
6828                 break;
6829         case RTE_ETH_FILTER_ADD:
6830                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6831                 break;
6832         case RTE_ETH_FILTER_DELETE:
6833                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6834                 break;
6835         default:
6836                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6837                 ret = I40E_ERR_PARAM;
6838                 break;
6839         }
6840
6841         return ret;
6842 }
6843
6844 static int
6845 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6846 {
6847         int ret = 0;
6848         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6849
6850         /* RSS setup */
6851         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6852                 ret = i40e_pf_config_rss(pf);
6853         else
6854                 i40e_pf_disable_rss(pf);
6855
6856         return ret;
6857 }
6858
6859 /* Get the symmetric hash enable configurations per port */
6860 static void
6861 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6862 {
6863         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6864
6865         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6866 }
6867
6868 /* Set the symmetric hash enable configurations per port */
6869 static void
6870 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6871 {
6872         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6873
6874         if (enable > 0) {
6875                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6876                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6877                                                         "been enabled");
6878                         return;
6879                 }
6880                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6881         } else {
6882                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6883                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6884                                                         "been disabled");
6885                         return;
6886                 }
6887                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6888         }
6889         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6890         I40E_WRITE_FLUSH(hw);
6891 }
6892
6893 /*
6894  * Get global configurations of hash function type and symmetric hash enable
6895  * per flow type (pctype). Note that global configuration means it affects all
6896  * the ports on the same NIC.
6897  */
6898 static int
6899 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6900                                    struct rte_eth_hash_global_conf *g_cfg)
6901 {
6902         uint32_t reg, mask = I40E_FLOW_TYPES;
6903         uint16_t i;
6904         enum i40e_filter_pctype pctype;
6905
6906         memset(g_cfg, 0, sizeof(*g_cfg));
6907         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6908         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6909                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6910         else
6911                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6912         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6913                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6914
6915         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6916                 if (!(mask & (1UL << i)))
6917                         continue;
6918                 mask &= ~(1UL << i);
6919                 /* Bit set indicats the coresponding flow type is supported */
6920                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6921                 pctype = i40e_flowtype_to_pctype(i);
6922                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6923                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6924                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6925         }
6926
6927         return 0;
6928 }
6929
6930 static int
6931 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6932 {
6933         uint32_t i;
6934         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6935
6936         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6937                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6938                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6939                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6940                                                 g_cfg->hash_func);
6941                 return -EINVAL;
6942         }
6943
6944         /*
6945          * As i40e supports less than 32 flow types, only first 32 bits need to
6946          * be checked.
6947          */
6948         mask0 = g_cfg->valid_bit_mask[0];
6949         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6950                 if (i == 0) {
6951                         /* Check if any unsupported flow type configured */
6952                         if ((mask0 | i40e_mask) ^ i40e_mask)
6953                                 goto mask_err;
6954                 } else {
6955                         if (g_cfg->valid_bit_mask[i])
6956                                 goto mask_err;
6957                 }
6958         }
6959
6960         return 0;
6961
6962 mask_err:
6963         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6964
6965         return -EINVAL;
6966 }
6967
6968 /*
6969  * Set global configurations of hash function type and symmetric hash enable
6970  * per flow type (pctype). Note any modifying global configuration will affect
6971  * all the ports on the same NIC.
6972  */
6973 static int
6974 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6975                                    struct rte_eth_hash_global_conf *g_cfg)
6976 {
6977         int ret;
6978         uint16_t i;
6979         uint32_t reg;
6980         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6981         enum i40e_filter_pctype pctype;
6982
6983         /* Check the input parameters */
6984         ret = i40e_hash_global_config_check(g_cfg);
6985         if (ret < 0)
6986                 return ret;
6987
6988         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6989                 if (!(mask0 & (1UL << i)))
6990                         continue;
6991                 mask0 &= ~(1UL << i);
6992                 pctype = i40e_flowtype_to_pctype(i);
6993                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6994                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6995                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6996         }
6997
6998         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6999         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7000                 /* Toeplitz */
7001                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7002                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7003                                                                 "Toeplitz");
7004                         goto out;
7005                 }
7006                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7007         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7008                 /* Simple XOR */
7009                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7010                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7011                                                         "Simple XOR");
7012                         goto out;
7013                 }
7014                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7015         } else
7016                 /* Use the default, and keep it as it is */
7017                 goto out;
7018
7019         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7020
7021 out:
7022         I40E_WRITE_FLUSH(hw);
7023
7024         return 0;
7025 }
7026
7027 /**
7028  * Valid input sets for hash and flow director filters per PCTYPE
7029  */
7030 static uint64_t
7031 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7032                 enum rte_filter_type filter)
7033 {
7034         uint64_t valid;
7035
7036         static const uint64_t valid_hash_inset_table[] = {
7037                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7038                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7039                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7040                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7041                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7042                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7043                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7044                         I40E_INSET_FLEX_PAYLOAD,
7045                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7046                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7047                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7048                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7049                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7050                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7051                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7052                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7053                         I40E_INSET_FLEX_PAYLOAD,
7054                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7055                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7056                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7057                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7058                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7059                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7060                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7061                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7062                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7063                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7064                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7065                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7066                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7067                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7068                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7069                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7070                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7071                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7072                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7076                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7077                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7078                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7079                         I40E_INSET_FLEX_PAYLOAD,
7080                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7081                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7082                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7083                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7084                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7085                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7086                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7087                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7088                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7089                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7090                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7091                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7092                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7093                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7094                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7095                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7096                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7100                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7101                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7102                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7103                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7104                         I40E_INSET_FLEX_PAYLOAD,
7105                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7109                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7110                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7111                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7112                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7113                         I40E_INSET_FLEX_PAYLOAD,
7114                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7118                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7119                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7120                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7121                         I40E_INSET_FLEX_PAYLOAD,
7122                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7123                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7124                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7125                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7126                         I40E_INSET_FLEX_PAYLOAD,
7127         };
7128
7129         /**
7130          * Flow director supports only fields defined in
7131          * union rte_eth_fdir_flow.
7132          */
7133         static const uint64_t valid_fdir_inset_table[] = {
7134                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7135                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7137                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7138                 I40E_INSET_IPV4_TTL,
7139                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7140                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7141                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7142                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7143                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7144                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7145                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7146                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7147                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7148                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7149                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7150                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7151                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7152                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7153                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7154                 I40E_INSET_SCTP_VT,
7155                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7156                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7157                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7158                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7159                 I40E_INSET_IPV4_TTL,
7160                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7161                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7163                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7164                 I40E_INSET_IPV6_HOP_LIMIT,
7165                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7166                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7167                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7168                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7169                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7170                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7171                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7172                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7173                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7174                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7175                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7176                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7177                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7178                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7179                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7180                 I40E_INSET_SCTP_VT,
7181                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7183                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7184                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7185                 I40E_INSET_IPV6_HOP_LIMIT,
7186                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7187                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7188                 I40E_INSET_LAST_ETHER_TYPE,
7189         };
7190
7191         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7192                 return 0;
7193         if (filter == RTE_ETH_FILTER_HASH)
7194                 valid = valid_hash_inset_table[pctype];
7195         else
7196                 valid = valid_fdir_inset_table[pctype];
7197
7198         return valid;
7199 }
7200
7201 /**
7202  * Validate if the input set is allowed for a specific PCTYPE
7203  */
7204 static int
7205 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7206                 enum rte_filter_type filter, uint64_t inset)
7207 {
7208         uint64_t valid;
7209
7210         valid = i40e_get_valid_input_set(pctype, filter);
7211         if (inset & (~valid))
7212                 return -EINVAL;
7213
7214         return 0;
7215 }
7216
7217 /* default input set fields combination per pctype */
7218 static uint64_t
7219 i40e_get_default_input_set(uint16_t pctype)
7220 {
7221         static const uint64_t default_inset_table[] = {
7222                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7223                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7224                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7225                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7226                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7227                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7228                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7229                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7230                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7231                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7232                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7233                         I40E_INSET_SCTP_VT,
7234                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7235                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7236                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7237                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7238                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7239                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7240                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7241                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7242                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7243                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7244                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7245                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7246                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7247                         I40E_INSET_SCTP_VT,
7248                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7249                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7250                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7251                         I40E_INSET_LAST_ETHER_TYPE,
7252         };
7253
7254         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7255                 return 0;
7256
7257         return default_inset_table[pctype];
7258 }
7259
7260 /**
7261  * Parse the input set from index to logical bit masks
7262  */
7263 static int
7264 i40e_parse_input_set(uint64_t *inset,
7265                      enum i40e_filter_pctype pctype,
7266                      enum rte_eth_input_set_field *field,
7267                      uint16_t size)
7268 {
7269         uint16_t i, j;
7270         int ret = -EINVAL;
7271
7272         static const struct {
7273                 enum rte_eth_input_set_field field;
7274                 uint64_t inset;
7275         } inset_convert_table[] = {
7276                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7277                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7278                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7279                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7280                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7281                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7282                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7283                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7284                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7285                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7286                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7287                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7288                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7289                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7290                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7291                         I40E_INSET_IPV6_NEXT_HDR},
7292                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7293                         I40E_INSET_IPV6_HOP_LIMIT},
7294                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7295                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7296                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7297                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7298                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7299                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7300                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7301                         I40E_INSET_SCTP_VT},
7302                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7303                         I40E_INSET_TUNNEL_DMAC},
7304                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7305                         I40E_INSET_VLAN_TUNNEL},
7306                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7307                         I40E_INSET_TUNNEL_ID},
7308                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7309                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7310                         I40E_INSET_FLEX_PAYLOAD_W1},
7311                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7312                         I40E_INSET_FLEX_PAYLOAD_W2},
7313                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7314                         I40E_INSET_FLEX_PAYLOAD_W3},
7315                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7316                         I40E_INSET_FLEX_PAYLOAD_W4},
7317                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7318                         I40E_INSET_FLEX_PAYLOAD_W5},
7319                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7320                         I40E_INSET_FLEX_PAYLOAD_W6},
7321                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7322                         I40E_INSET_FLEX_PAYLOAD_W7},
7323                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7324                         I40E_INSET_FLEX_PAYLOAD_W8},
7325         };
7326
7327         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7328                 return ret;
7329
7330         /* Only one item allowed for default or all */
7331         if (size == 1) {
7332                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7333                         *inset = i40e_get_default_input_set(pctype);
7334                         return 0;
7335                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7336                         *inset = I40E_INSET_NONE;
7337                         return 0;
7338                 }
7339         }
7340
7341         for (i = 0, *inset = 0; i < size; i++) {
7342                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7343                         if (field[i] == inset_convert_table[j].field) {
7344                                 *inset |= inset_convert_table[j].inset;
7345                                 break;
7346                         }
7347                 }
7348
7349                 /* It contains unsupported input set, return immediately */
7350                 if (j == RTE_DIM(inset_convert_table))
7351                         return ret;
7352         }
7353
7354         return 0;
7355 }
7356
7357 /**
7358  * Translate the input set from bit masks to register aware bit masks
7359  * and vice versa
7360  */
7361 static uint64_t
7362 i40e_translate_input_set_reg(uint64_t input)
7363 {
7364         uint64_t val = 0;
7365         uint16_t i;
7366
7367         static const struct {
7368                 uint64_t inset;
7369                 uint64_t inset_reg;
7370         } inset_map[] = {
7371                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7372                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7373                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7374                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7375                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7376                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7377                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7378                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7379                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7380                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7381                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7382                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7383                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7384                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7385                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7386                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7387                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7388                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7389                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7390                 {I40E_INSET_TUNNEL_DMAC,
7391                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7392                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7393                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7394                 {I40E_INSET_TUNNEL_SRC_PORT,
7395                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7396                 {I40E_INSET_TUNNEL_DST_PORT,
7397                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7398                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7399                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7400                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7401                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7402                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7403                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7404                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7405                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7406                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7407         };
7408
7409         if (input == 0)
7410                 return val;
7411
7412         /* Translate input set to register aware inset */
7413         for (i = 0; i < RTE_DIM(inset_map); i++) {
7414                 if (input & inset_map[i].inset)
7415                         val |= inset_map[i].inset_reg;
7416         }
7417
7418         return val;
7419 }
7420
7421 static int
7422 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7423 {
7424         uint8_t i, idx = 0;
7425         uint64_t inset_need_mask = inset;
7426
7427         static const struct {
7428                 uint64_t inset;
7429                 uint32_t mask;
7430         } inset_mask_map[] = {
7431                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7432                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7433                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7434                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7435                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7436                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7437                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7438                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7439         };
7440
7441         if (!inset || !mask || !nb_elem)
7442                 return 0;
7443
7444         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7445                 /* Clear the inset bit, if no MASK is required,
7446                  * for example proto + ttl
7447                  */
7448                 if ((inset & inset_mask_map[i].inset) ==
7449                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7450                         inset_need_mask &= ~inset_mask_map[i].inset;
7451                 if (!inset_need_mask)
7452                         return 0;
7453         }
7454         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7455                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7456                     inset_mask_map[i].inset) {
7457                         if (idx >= nb_elem) {
7458                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7459                                 return -EINVAL;
7460                         }
7461                         mask[idx] = inset_mask_map[i].mask;
7462                         idx++;
7463                 }
7464         }
7465
7466         return idx;
7467 }
7468
7469 static void
7470 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7471 {
7472         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7473
7474         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7475         if (reg != val)
7476                 i40e_write_rx_ctl(hw, addr, val);
7477         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7478                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7479 }
7480
7481 static void
7482 i40e_filter_input_set_init(struct i40e_pf *pf)
7483 {
7484         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7485         enum i40e_filter_pctype pctype;
7486         uint64_t input_set, inset_reg;
7487         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7488         int num, i;
7489
7490         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7491              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7492                 if (!I40E_VALID_PCTYPE(pctype))
7493                         continue;
7494                 input_set = i40e_get_default_input_set(pctype);
7495
7496                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7497                                                    I40E_INSET_MASK_NUM_REG);
7498                 if (num < 0)
7499                         return;
7500                 inset_reg = i40e_translate_input_set_reg(input_set);
7501
7502                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7503                                       (uint32_t)(inset_reg & UINT32_MAX));
7504                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7505                                      (uint32_t)((inset_reg >>
7506                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7507                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7508                                       (uint32_t)(inset_reg & UINT32_MAX));
7509                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7510                                      (uint32_t)((inset_reg >>
7511                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7512
7513                 for (i = 0; i < num; i++) {
7514                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7515                                              mask_reg[i]);
7516                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7517                                              mask_reg[i]);
7518                 }
7519                 /*clear unused mask registers of the pctype */
7520                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7521                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7522                                              0);
7523                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7524                                              0);
7525                 }
7526                 I40E_WRITE_FLUSH(hw);
7527
7528                 /* store the default input set */
7529                 pf->hash_input_set[pctype] = input_set;
7530                 pf->fdir.input_set[pctype] = input_set;
7531         }
7532 }
7533
7534 int
7535 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7536                          struct rte_eth_input_set_conf *conf)
7537 {
7538         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7539         enum i40e_filter_pctype pctype;
7540         uint64_t input_set, inset_reg = 0;
7541         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7542         int ret, i, num;
7543
7544         if (!conf) {
7545                 PMD_DRV_LOG(ERR, "Invalid pointer");
7546                 return -EFAULT;
7547         }
7548         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7549             conf->op != RTE_ETH_INPUT_SET_ADD) {
7550                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7551                 return -EINVAL;
7552         }
7553
7554         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7555         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7556                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7557                             conf->flow_type);
7558                 return -EINVAL;
7559         }
7560
7561         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7562                                    conf->inset_size);
7563         if (ret) {
7564                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7565                 return -EINVAL;
7566         }
7567         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7568                                     input_set) != 0) {
7569                 PMD_DRV_LOG(ERR, "Invalid input set");
7570                 return -EINVAL;
7571         }
7572         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7573                 /* get inset value in register */
7574                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7575                 inset_reg <<= I40E_32_BIT_WIDTH;
7576                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7577                 input_set |= pf->hash_input_set[pctype];
7578         }
7579         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7580                                            I40E_INSET_MASK_NUM_REG);
7581         if (num < 0)
7582                 return -EINVAL;
7583
7584         inset_reg |= i40e_translate_input_set_reg(input_set);
7585
7586         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7587                               (uint32_t)(inset_reg & UINT32_MAX));
7588         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7589                              (uint32_t)((inset_reg >>
7590                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7591
7592         for (i = 0; i < num; i++)
7593                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7594                                      mask_reg[i]);
7595         /*clear unused mask registers of the pctype */
7596         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7597                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7598                                      0);
7599         I40E_WRITE_FLUSH(hw);
7600
7601         pf->hash_input_set[pctype] = input_set;
7602         return 0;
7603 }
7604
7605 int
7606 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7607                          struct rte_eth_input_set_conf *conf)
7608 {
7609         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7610         enum i40e_filter_pctype pctype;
7611         uint64_t input_set, inset_reg = 0;
7612         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7613         int ret, i, num;
7614
7615         if (!hw || !conf) {
7616                 PMD_DRV_LOG(ERR, "Invalid pointer");
7617                 return -EFAULT;
7618         }
7619         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7620             conf->op != RTE_ETH_INPUT_SET_ADD) {
7621                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7622                 return -EINVAL;
7623         }
7624
7625         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7626         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7627                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7628                             conf->flow_type);
7629                 return -EINVAL;
7630         }
7631         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7632                                    conf->inset_size);
7633         if (ret) {
7634                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7635                 return -EINVAL;
7636         }
7637         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7638                                     input_set) != 0) {
7639                 PMD_DRV_LOG(ERR, "Invalid input set");
7640                 return -EINVAL;
7641         }
7642
7643         /* get inset value in register */
7644         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7645         inset_reg <<= I40E_32_BIT_WIDTH;
7646         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7647
7648         /* Can not change the inset reg for flex payload for fdir,
7649          * it is done by writing I40E_PRTQF_FD_FLXINSET
7650          * in i40e_set_flex_mask_on_pctype.
7651          */
7652         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7653                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7654         else
7655                 input_set |= pf->fdir.input_set[pctype];
7656         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7657                                            I40E_INSET_MASK_NUM_REG);
7658         if (num < 0)
7659                 return -EINVAL;
7660
7661         inset_reg |= i40e_translate_input_set_reg(input_set);
7662
7663         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7664                               (uint32_t)(inset_reg & UINT32_MAX));
7665         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7666                              (uint32_t)((inset_reg >>
7667                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7668
7669         for (i = 0; i < num; i++)
7670                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7671                                      mask_reg[i]);
7672         /*clear unused mask registers of the pctype */
7673         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7674                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7675                                      0);
7676         I40E_WRITE_FLUSH(hw);
7677
7678         pf->fdir.input_set[pctype] = input_set;
7679         return 0;
7680 }
7681
7682 static int
7683 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7684 {
7685         int ret = 0;
7686
7687         if (!hw || !info) {
7688                 PMD_DRV_LOG(ERR, "Invalid pointer");
7689                 return -EFAULT;
7690         }
7691
7692         switch (info->info_type) {
7693         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7694                 i40e_get_symmetric_hash_enable_per_port(hw,
7695                                         &(info->info.enable));
7696                 break;
7697         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7698                 ret = i40e_get_hash_filter_global_config(hw,
7699                                 &(info->info.global_conf));
7700                 break;
7701         default:
7702                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7703                                                         info->info_type);
7704                 ret = -EINVAL;
7705                 break;
7706         }
7707
7708         return ret;
7709 }
7710
7711 static int
7712 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7713 {
7714         int ret = 0;
7715
7716         if (!hw || !info) {
7717                 PMD_DRV_LOG(ERR, "Invalid pointer");
7718                 return -EFAULT;
7719         }
7720
7721         switch (info->info_type) {
7722         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7723                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7724                 break;
7725         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7726                 ret = i40e_set_hash_filter_global_config(hw,
7727                                 &(info->info.global_conf));
7728                 break;
7729         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7730                 ret = i40e_hash_filter_inset_select(hw,
7731                                                &(info->info.input_set_conf));
7732                 break;
7733
7734         default:
7735                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7736                                                         info->info_type);
7737                 ret = -EINVAL;
7738                 break;
7739         }
7740
7741         return ret;
7742 }
7743
7744 /* Operations for hash function */
7745 static int
7746 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7747                       enum rte_filter_op filter_op,
7748                       void *arg)
7749 {
7750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7751         int ret = 0;
7752
7753         switch (filter_op) {
7754         case RTE_ETH_FILTER_NOP:
7755                 break;
7756         case RTE_ETH_FILTER_GET:
7757                 ret = i40e_hash_filter_get(hw,
7758                         (struct rte_eth_hash_filter_info *)arg);
7759                 break;
7760         case RTE_ETH_FILTER_SET:
7761                 ret = i40e_hash_filter_set(hw,
7762                         (struct rte_eth_hash_filter_info *)arg);
7763                 break;
7764         default:
7765                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7766                                                                 filter_op);
7767                 ret = -ENOTSUP;
7768                 break;
7769         }
7770
7771         return ret;
7772 }
7773
7774 /*
7775  * Configure ethertype filter, which can director packet by filtering
7776  * with mac address and ether_type or only ether_type
7777  */
7778 static int
7779 i40e_ethertype_filter_set(struct i40e_pf *pf,
7780                         struct rte_eth_ethertype_filter *filter,
7781                         bool add)
7782 {
7783         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7784         struct i40e_control_filter_stats stats;
7785         uint16_t flags = 0;
7786         int ret;
7787
7788         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7789                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7790                 return -EINVAL;
7791         }
7792         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7793                 filter->ether_type == ETHER_TYPE_IPv6) {
7794                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7795                         " control packet filter.", filter->ether_type);
7796                 return -EINVAL;
7797         }
7798         if (filter->ether_type == ETHER_TYPE_VLAN)
7799                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7800                         " not supported.");
7801
7802         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7803                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7804         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7805                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7806         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7807
7808         memset(&stats, 0, sizeof(stats));
7809         ret = i40e_aq_add_rem_control_packet_filter(hw,
7810                         filter->mac_addr.addr_bytes,
7811                         filter->ether_type, flags,
7812                         pf->main_vsi->seid,
7813                         filter->queue, add, &stats, NULL);
7814
7815         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7816                          " mac_etype_used = %u, etype_used = %u,"
7817                          " mac_etype_free = %u, etype_free = %u\n",
7818                          ret, stats.mac_etype_used, stats.etype_used,
7819                          stats.mac_etype_free, stats.etype_free);
7820         if (ret < 0)
7821                 return -ENOSYS;
7822         return 0;
7823 }
7824
7825 /*
7826  * Handle operations for ethertype filter.
7827  */
7828 static int
7829 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7830                                 enum rte_filter_op filter_op,
7831                                 void *arg)
7832 {
7833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7834         int ret = 0;
7835
7836         if (filter_op == RTE_ETH_FILTER_NOP)
7837                 return ret;
7838
7839         if (arg == NULL) {
7840                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7841                             filter_op);
7842                 return -EINVAL;
7843         }
7844
7845         switch (filter_op) {
7846         case RTE_ETH_FILTER_ADD:
7847                 ret = i40e_ethertype_filter_set(pf,
7848                         (struct rte_eth_ethertype_filter *)arg,
7849                         TRUE);
7850                 break;
7851         case RTE_ETH_FILTER_DELETE:
7852                 ret = i40e_ethertype_filter_set(pf,
7853                         (struct rte_eth_ethertype_filter *)arg,
7854                         FALSE);
7855                 break;
7856         default:
7857                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7858                 ret = -ENOSYS;
7859                 break;
7860         }
7861         return ret;
7862 }
7863
7864 static int
7865 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7866                      enum rte_filter_type filter_type,
7867                      enum rte_filter_op filter_op,
7868                      void *arg)
7869 {
7870         int ret = 0;
7871
7872         if (dev == NULL)
7873                 return -EINVAL;
7874
7875         switch (filter_type) {
7876         case RTE_ETH_FILTER_NONE:
7877                 /* For global configuration */
7878                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7879                 break;
7880         case RTE_ETH_FILTER_HASH:
7881                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7882                 break;
7883         case RTE_ETH_FILTER_MACVLAN:
7884                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7885                 break;
7886         case RTE_ETH_FILTER_ETHERTYPE:
7887                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7888                 break;
7889         case RTE_ETH_FILTER_TUNNEL:
7890                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7891                 break;
7892         case RTE_ETH_FILTER_FDIR:
7893                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7894                 break;
7895         default:
7896                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7897                                                         filter_type);
7898                 ret = -EINVAL;
7899                 break;
7900         }
7901
7902         return ret;
7903 }
7904
7905 /*
7906  * Check and enable Extended Tag.
7907  * Enabling Extended Tag is important for 40G performance.
7908  */
7909 static void
7910 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7911 {
7912         uint32_t buf = 0;
7913         int ret;
7914
7915         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7916                                       PCI_DEV_CAP_REG);
7917         if (ret < 0) {
7918                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7919                             PCI_DEV_CAP_REG);
7920                 return;
7921         }
7922         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7923                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7924                 return;
7925         }
7926
7927         buf = 0;
7928         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7929                                       PCI_DEV_CTRL_REG);
7930         if (ret < 0) {
7931                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7932                             PCI_DEV_CTRL_REG);
7933                 return;
7934         }
7935         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7936                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7937                 return;
7938         }
7939         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7940         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7941                                        PCI_DEV_CTRL_REG);
7942         if (ret < 0) {
7943                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7944                             PCI_DEV_CTRL_REG);
7945                 return;
7946         }
7947 }
7948
7949 /*
7950  * As some registers wouldn't be reset unless a global hardware reset,
7951  * hardware initialization is needed to put those registers into an
7952  * expected initial state.
7953  */
7954 static void
7955 i40e_hw_init(struct rte_eth_dev *dev)
7956 {
7957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7958
7959         i40e_enable_extended_tag(dev);
7960
7961         /* clear the PF Queue Filter control register */
7962         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7963
7964         /* Disable symmetric hash per port */
7965         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7966 }
7967
7968 enum i40e_filter_pctype
7969 i40e_flowtype_to_pctype(uint16_t flow_type)
7970 {
7971         static const enum i40e_filter_pctype pctype_table[] = {
7972                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7973                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7974                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7975                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7976                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7977                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7978                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7979                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7980                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7981                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7982                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7983                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7984                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7985                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7986                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7987                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7988                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7989                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7990                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7991         };
7992
7993         return pctype_table[flow_type];
7994 }
7995
7996 uint16_t
7997 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7998 {
7999         static const uint16_t flowtype_table[] = {
8000                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8001                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8002                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8003                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8004                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8005                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8006                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8007                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8008                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8009                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8010                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8011                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8012                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8013                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8014                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8015                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8016                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8017                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8018                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8019         };
8020
8021         return flowtype_table[pctype];
8022 }
8023
8024 /*
8025  * On X710, performance number is far from the expectation on recent firmware
8026  * versions; on XL710, performance number is also far from the expectation on
8027  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8028  * mode is enabled and port MAC address is equal to the packet destination MAC
8029  * address. The fix for this issue may not be integrated in the following
8030  * firmware version. So the workaround in software driver is needed. It needs
8031  * to modify the initial values of 3 internal only registers for both X710 and
8032  * XL710. Note that the values for X710 or XL710 could be different, and the
8033  * workaround can be removed when it is fixed in firmware in the future.
8034  */
8035
8036 /* For both X710 and XL710 */
8037 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8038 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8039
8040 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8041 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8042
8043 /* For X710 */
8044 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8045 /* For XL710 */
8046 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8047 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8048
8049 static void
8050 i40e_configure_registers(struct i40e_hw *hw)
8051 {
8052         static struct {
8053                 uint32_t addr;
8054                 uint64_t val;
8055         } reg_table[] = {
8056                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8057                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8058                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8059         };
8060         uint64_t reg;
8061         uint32_t i;
8062         int ret;
8063
8064         for (i = 0; i < RTE_DIM(reg_table); i++) {
8065                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8066                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8067                                 reg_table[i].val =
8068                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8069                         else /* For X710 */
8070                                 reg_table[i].val =
8071                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8072                 }
8073
8074                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8075                                                         &reg, NULL);
8076                 if (ret < 0) {
8077                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8078                                                         reg_table[i].addr);
8079                         break;
8080                 }
8081                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8082                                                 reg_table[i].addr, reg);
8083                 if (reg == reg_table[i].val)
8084                         continue;
8085
8086                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8087                                                 reg_table[i].val, NULL);
8088                 if (ret < 0) {
8089                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8090                                 "address of 0x%"PRIx32, reg_table[i].val,
8091                                                         reg_table[i].addr);
8092                         break;
8093                 }
8094                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8095                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8096         }
8097 }
8098
8099 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8100 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8101 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8102 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8103 static int
8104 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8105 {
8106         uint32_t reg;
8107         int ret;
8108
8109         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8110                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8111                 return -EINVAL;
8112         }
8113
8114         /* Configure for double VLAN RX stripping */
8115         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8116         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8117                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8118                 ret = i40e_aq_debug_write_register(hw,
8119                                                    I40E_VSI_TSR(vsi->vsi_id),
8120                                                    reg, NULL);
8121                 if (ret < 0) {
8122                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8123                                     vsi->vsi_id);
8124                         return I40E_ERR_CONFIG;
8125                 }
8126         }
8127
8128         /* Configure for double VLAN TX insertion */
8129         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8130         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8131                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8132                 ret = i40e_aq_debug_write_register(hw,
8133                                                    I40E_VSI_L2TAGSTXVALID(
8134                                                    vsi->vsi_id), reg, NULL);
8135                 if (ret < 0) {
8136                         PMD_DRV_LOG(ERR, "Failed to update "
8137                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8138                         return I40E_ERR_CONFIG;
8139                 }
8140         }
8141
8142         return 0;
8143 }
8144
8145 /**
8146  * i40e_aq_add_mirror_rule
8147  * @hw: pointer to the hardware structure
8148  * @seid: VEB seid to add mirror rule to
8149  * @dst_id: destination vsi seid
8150  * @entries: Buffer which contains the entities to be mirrored
8151  * @count: number of entities contained in the buffer
8152  * @rule_id:the rule_id of the rule to be added
8153  *
8154  * Add a mirror rule for a given veb.
8155  *
8156  **/
8157 static enum i40e_status_code
8158 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8159                         uint16_t seid, uint16_t dst_id,
8160                         uint16_t rule_type, uint16_t *entries,
8161                         uint16_t count, uint16_t *rule_id)
8162 {
8163         struct i40e_aq_desc desc;
8164         struct i40e_aqc_add_delete_mirror_rule cmd;
8165         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8166                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8167                 &desc.params.raw;
8168         uint16_t buff_len;
8169         enum i40e_status_code status;
8170
8171         i40e_fill_default_direct_cmd_desc(&desc,
8172                                           i40e_aqc_opc_add_mirror_rule);
8173         memset(&cmd, 0, sizeof(cmd));
8174
8175         buff_len = sizeof(uint16_t) * count;
8176         desc.datalen = rte_cpu_to_le_16(buff_len);
8177         if (buff_len > 0)
8178                 desc.flags |= rte_cpu_to_le_16(
8179                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8180         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8181                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8182         cmd.num_entries = rte_cpu_to_le_16(count);
8183         cmd.seid = rte_cpu_to_le_16(seid);
8184         cmd.destination = rte_cpu_to_le_16(dst_id);
8185
8186         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8187         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8188         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8189                          "rule_id = %u"
8190                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8191                          hw->aq.asq_last_status, resp->rule_id,
8192                          resp->mirror_rules_used, resp->mirror_rules_free);
8193         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8194
8195         return status;
8196 }
8197
8198 /**
8199  * i40e_aq_del_mirror_rule
8200  * @hw: pointer to the hardware structure
8201  * @seid: VEB seid to add mirror rule to
8202  * @entries: Buffer which contains the entities to be mirrored
8203  * @count: number of entities contained in the buffer
8204  * @rule_id:the rule_id of the rule to be delete
8205  *
8206  * Delete a mirror rule for a given veb.
8207  *
8208  **/
8209 static enum i40e_status_code
8210 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8211                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8212                 uint16_t count, uint16_t rule_id)
8213 {
8214         struct i40e_aq_desc desc;
8215         struct i40e_aqc_add_delete_mirror_rule cmd;
8216         uint16_t buff_len = 0;
8217         enum i40e_status_code status;
8218         void *buff = NULL;
8219
8220         i40e_fill_default_direct_cmd_desc(&desc,
8221                                           i40e_aqc_opc_delete_mirror_rule);
8222         memset(&cmd, 0, sizeof(cmd));
8223         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8224                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8225                                                           I40E_AQ_FLAG_RD));
8226                 cmd.num_entries = count;
8227                 buff_len = sizeof(uint16_t) * count;
8228                 desc.datalen = rte_cpu_to_le_16(buff_len);
8229                 buff = (void *)entries;
8230         } else
8231                 /* rule id is filled in destination field for deleting mirror rule */
8232                 cmd.destination = rte_cpu_to_le_16(rule_id);
8233
8234         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8235                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8236         cmd.seid = rte_cpu_to_le_16(seid);
8237
8238         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8239         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8240
8241         return status;
8242 }
8243
8244 /**
8245  * i40e_mirror_rule_set
8246  * @dev: pointer to the hardware structure
8247  * @mirror_conf: mirror rule info
8248  * @sw_id: mirror rule's sw_id
8249  * @on: enable/disable
8250  *
8251  * set a mirror rule.
8252  *
8253  **/
8254 static int
8255 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8256                         struct rte_eth_mirror_conf *mirror_conf,
8257                         uint8_t sw_id, uint8_t on)
8258 {
8259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8260         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8261         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8262         struct i40e_mirror_rule *parent = NULL;
8263         uint16_t seid, dst_seid, rule_id;
8264         uint16_t i, j = 0;
8265         int ret;
8266
8267         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8268
8269         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8270                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8271                         " without veb or vfs.");
8272                 return -ENOSYS;
8273         }
8274         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8275                 PMD_DRV_LOG(ERR, "mirror table is full.");
8276                 return -ENOSPC;
8277         }
8278         if (mirror_conf->dst_pool > pf->vf_num) {
8279                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8280                                  mirror_conf->dst_pool);
8281                 return -EINVAL;
8282         }
8283
8284         seid = pf->main_vsi->veb->seid;
8285
8286         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8287                 if (sw_id <= it->index) {
8288                         mirr_rule = it;
8289                         break;
8290                 }
8291                 parent = it;
8292         }
8293         if (mirr_rule && sw_id == mirr_rule->index) {
8294                 if (on) {
8295                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8296                         return -EEXIST;
8297                 } else {
8298                         ret = i40e_aq_del_mirror_rule(hw, seid,
8299                                         mirr_rule->rule_type,
8300                                         mirr_rule->entries,
8301                                         mirr_rule->num_entries, mirr_rule->id);
8302                         if (ret < 0) {
8303                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8304                                                    " ret = %d, aq_err = %d.",
8305                                                    ret, hw->aq.asq_last_status);
8306                                 return -ENOSYS;
8307                         }
8308                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8309                         rte_free(mirr_rule);
8310                         pf->nb_mirror_rule--;
8311                         return 0;
8312                 }
8313         } else if (!on) {
8314                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8315                 return -ENOENT;
8316         }
8317
8318         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8319                                 sizeof(struct i40e_mirror_rule) , 0);
8320         if (!mirr_rule) {
8321                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8322                 return I40E_ERR_NO_MEMORY;
8323         }
8324         switch (mirror_conf->rule_type) {
8325         case ETH_MIRROR_VLAN:
8326                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8327                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8328                                 mirr_rule->entries[j] =
8329                                         mirror_conf->vlan.vlan_id[i];
8330                                 j++;
8331                         }
8332                 }
8333                 if (j == 0) {
8334                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8335                         rte_free(mirr_rule);
8336                         return -EINVAL;
8337                 }
8338                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8339                 break;
8340         case ETH_MIRROR_VIRTUAL_POOL_UP:
8341         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8342                 /* check if the specified pool bit is out of range */
8343                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8344                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8345                         rte_free(mirr_rule);
8346                         return -EINVAL;
8347                 }
8348                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8349                         if (mirror_conf->pool_mask & (1ULL << i)) {
8350                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8351                                 j++;
8352                         }
8353                 }
8354                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8355                         /* add pf vsi to entries */
8356                         mirr_rule->entries[j] = pf->main_vsi_seid;
8357                         j++;
8358                 }
8359                 if (j == 0) {
8360                         PMD_DRV_LOG(ERR, "pool is not specified.");
8361                         rte_free(mirr_rule);
8362                         return -EINVAL;
8363                 }
8364                 /* egress and ingress in aq commands means from switch but not port */
8365                 mirr_rule->rule_type =
8366                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8367                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8368                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8369                 break;
8370         case ETH_MIRROR_UPLINK_PORT:
8371                 /* egress and ingress in aq commands means from switch but not port*/
8372                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8373                 break;
8374         case ETH_MIRROR_DOWNLINK_PORT:
8375                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8376                 break;
8377         default:
8378                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8379                         mirror_conf->rule_type);
8380                 rte_free(mirr_rule);
8381                 return -EINVAL;
8382         }
8383
8384         /* If the dst_pool is equal to vf_num, consider it as PF */
8385         if (mirror_conf->dst_pool == pf->vf_num)
8386                 dst_seid = pf->main_vsi_seid;
8387         else
8388                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8389
8390         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8391                                       mirr_rule->rule_type, mirr_rule->entries,
8392                                       j, &rule_id);
8393         if (ret < 0) {
8394                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8395                                    " ret = %d, aq_err = %d.",
8396                                    ret, hw->aq.asq_last_status);
8397                 rte_free(mirr_rule);
8398                 return -ENOSYS;
8399         }
8400
8401         mirr_rule->index = sw_id;
8402         mirr_rule->num_entries = j;
8403         mirr_rule->id = rule_id;
8404         mirr_rule->dst_vsi_seid = dst_seid;
8405
8406         if (parent)
8407                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8408         else
8409                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8410
8411         pf->nb_mirror_rule++;
8412         return 0;
8413 }
8414
8415 /**
8416  * i40e_mirror_rule_reset
8417  * @dev: pointer to the device
8418  * @sw_id: mirror rule's sw_id
8419  *
8420  * reset a mirror rule.
8421  *
8422  **/
8423 static int
8424 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8425 {
8426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8428         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8429         uint16_t seid;
8430         int ret;
8431
8432         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8433
8434         seid = pf->main_vsi->veb->seid;
8435
8436         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8437                 if (sw_id == it->index) {
8438                         mirr_rule = it;
8439                         break;
8440                 }
8441         }
8442         if (mirr_rule) {
8443                 ret = i40e_aq_del_mirror_rule(hw, seid,
8444                                 mirr_rule->rule_type,
8445                                 mirr_rule->entries,
8446                                 mirr_rule->num_entries, mirr_rule->id);
8447                 if (ret < 0) {
8448                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8449                                            " status = %d, aq_err = %d.",
8450                                            ret, hw->aq.asq_last_status);
8451                         return -ENOSYS;
8452                 }
8453                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8454                 rte_free(mirr_rule);
8455                 pf->nb_mirror_rule--;
8456         } else {
8457                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8458                 return -ENOENT;
8459         }
8460         return 0;
8461 }
8462
8463 static uint64_t
8464 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8465 {
8466         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8467         uint64_t systim_cycles;
8468
8469         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8470         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8471                         << 32;
8472
8473         return systim_cycles;
8474 }
8475
8476 static uint64_t
8477 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8478 {
8479         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8480         uint64_t rx_tstamp;
8481
8482         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8483         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8484                         << 32;
8485
8486         return rx_tstamp;
8487 }
8488
8489 static uint64_t
8490 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8491 {
8492         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8493         uint64_t tx_tstamp;
8494
8495         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8496         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8497                         << 32;
8498
8499         return tx_tstamp;
8500 }
8501
8502 static void
8503 i40e_start_timecounters(struct rte_eth_dev *dev)
8504 {
8505         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8506         struct i40e_adapter *adapter =
8507                         (struct i40e_adapter *)dev->data->dev_private;
8508         struct rte_eth_link link;
8509         uint32_t tsync_inc_l;
8510         uint32_t tsync_inc_h;
8511
8512         /* Get current link speed. */
8513         memset(&link, 0, sizeof(link));
8514         i40e_dev_link_update(dev, 1);
8515         rte_i40e_dev_atomic_read_link_status(dev, &link);
8516
8517         switch (link.link_speed) {
8518         case ETH_SPEED_NUM_40G:
8519                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8520                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8521                 break;
8522         case ETH_SPEED_NUM_10G:
8523                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8524                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8525                 break;
8526         case ETH_SPEED_NUM_1G:
8527                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8528                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8529                 break;
8530         default:
8531                 tsync_inc_l = 0x0;
8532                 tsync_inc_h = 0x0;
8533         }
8534
8535         /* Set the timesync increment value. */
8536         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8537         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8538
8539         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8540         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8541         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8542
8543         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8544         adapter->systime_tc.cc_shift = 0;
8545         adapter->systime_tc.nsec_mask = 0;
8546
8547         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8548         adapter->rx_tstamp_tc.cc_shift = 0;
8549         adapter->rx_tstamp_tc.nsec_mask = 0;
8550
8551         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8552         adapter->tx_tstamp_tc.cc_shift = 0;
8553         adapter->tx_tstamp_tc.nsec_mask = 0;
8554 }
8555
8556 static int
8557 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8558 {
8559         struct i40e_adapter *adapter =
8560                         (struct i40e_adapter *)dev->data->dev_private;
8561
8562         adapter->systime_tc.nsec += delta;
8563         adapter->rx_tstamp_tc.nsec += delta;
8564         adapter->tx_tstamp_tc.nsec += delta;
8565
8566         return 0;
8567 }
8568
8569 static int
8570 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8571 {
8572         uint64_t ns;
8573         struct i40e_adapter *adapter =
8574                         (struct i40e_adapter *)dev->data->dev_private;
8575
8576         ns = rte_timespec_to_ns(ts);
8577
8578         /* Set the timecounters to a new value. */
8579         adapter->systime_tc.nsec = ns;
8580         adapter->rx_tstamp_tc.nsec = ns;
8581         adapter->tx_tstamp_tc.nsec = ns;
8582
8583         return 0;
8584 }
8585
8586 static int
8587 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8588 {
8589         uint64_t ns, systime_cycles;
8590         struct i40e_adapter *adapter =
8591                         (struct i40e_adapter *)dev->data->dev_private;
8592
8593         systime_cycles = i40e_read_systime_cyclecounter(dev);
8594         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8595         *ts = rte_ns_to_timespec(ns);
8596
8597         return 0;
8598 }
8599
8600 static int
8601 i40e_timesync_enable(struct rte_eth_dev *dev)
8602 {
8603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8604         uint32_t tsync_ctl_l;
8605         uint32_t tsync_ctl_h;
8606
8607         /* Stop the timesync system time. */
8608         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8609         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8610         /* Reset the timesync system time value. */
8611         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8612         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8613
8614         i40e_start_timecounters(dev);
8615
8616         /* Clear timesync registers. */
8617         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8618         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8619         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8620         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8621         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8622         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8623
8624         /* Enable timestamping of PTP packets. */
8625         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8626         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8627
8628         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8629         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8630         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8631
8632         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8633         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8634
8635         return 0;
8636 }
8637
8638 static int
8639 i40e_timesync_disable(struct rte_eth_dev *dev)
8640 {
8641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8642         uint32_t tsync_ctl_l;
8643         uint32_t tsync_ctl_h;
8644
8645         /* Disable timestamping of transmitted PTP packets. */
8646         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8647         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8648
8649         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8650         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8651
8652         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8653         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8654
8655         /* Reset the timesync increment value. */
8656         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8657         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8658
8659         return 0;
8660 }
8661
8662 static int
8663 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8664                                 struct timespec *timestamp, uint32_t flags)
8665 {
8666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8667         struct i40e_adapter *adapter =
8668                 (struct i40e_adapter *)dev->data->dev_private;
8669
8670         uint32_t sync_status;
8671         uint32_t index = flags & 0x03;
8672         uint64_t rx_tstamp_cycles;
8673         uint64_t ns;
8674
8675         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8676         if ((sync_status & (1 << index)) == 0)
8677                 return -EINVAL;
8678
8679         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8680         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8681         *timestamp = rte_ns_to_timespec(ns);
8682
8683         return 0;
8684 }
8685
8686 static int
8687 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8688                                 struct timespec *timestamp)
8689 {
8690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8691         struct i40e_adapter *adapter =
8692                 (struct i40e_adapter *)dev->data->dev_private;
8693
8694         uint32_t sync_status;
8695         uint64_t tx_tstamp_cycles;
8696         uint64_t ns;
8697
8698         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8699         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8700                 return -EINVAL;
8701
8702         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8703         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8704         *timestamp = rte_ns_to_timespec(ns);
8705
8706         return 0;
8707 }
8708
8709 /*
8710  * i40e_parse_dcb_configure - parse dcb configure from user
8711  * @dev: the device being configured
8712  * @dcb_cfg: pointer of the result of parse
8713  * @*tc_map: bit map of enabled traffic classes
8714  *
8715  * Returns 0 on success, negative value on failure
8716  */
8717 static int
8718 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8719                          struct i40e_dcbx_config *dcb_cfg,
8720                          uint8_t *tc_map)
8721 {
8722         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8723         uint8_t i, tc_bw, bw_lf;
8724
8725         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8726
8727         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8728         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8729                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8730                 return -EINVAL;
8731         }
8732
8733         /* assume each tc has the same bw */
8734         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8735         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8736                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8737         /* to ensure the sum of tcbw is equal to 100 */
8738         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8739         for (i = 0; i < bw_lf; i++)
8740                 dcb_cfg->etscfg.tcbwtable[i]++;
8741
8742         /* assume each tc has the same Transmission Selection Algorithm */
8743         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8744                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8745
8746         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8747                 dcb_cfg->etscfg.prioritytable[i] =
8748                                 dcb_rx_conf->dcb_tc[i];
8749
8750         /* FW needs one App to configure HW */
8751         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8752         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8753         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8754         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8755
8756         if (dcb_rx_conf->nb_tcs == 0)
8757                 *tc_map = 1; /* tc0 only */
8758         else
8759                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8760
8761         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8762                 dcb_cfg->pfc.willing = 0;
8763                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8764                 dcb_cfg->pfc.pfcenable = *tc_map;
8765         }
8766         return 0;
8767 }
8768
8769
8770 static enum i40e_status_code
8771 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8772                               struct i40e_aqc_vsi_properties_data *info,
8773                               uint8_t enabled_tcmap)
8774 {
8775         enum i40e_status_code ret;
8776         int i, total_tc = 0;
8777         uint16_t qpnum_per_tc, bsf, qp_idx;
8778         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8779         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8780         uint16_t used_queues;
8781
8782         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8783         if (ret != I40E_SUCCESS)
8784                 return ret;
8785
8786         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8787                 if (enabled_tcmap & (1 << i))
8788                         total_tc++;
8789         }
8790         if (total_tc == 0)
8791                 total_tc = 1;
8792         vsi->enabled_tc = enabled_tcmap;
8793
8794         /* different VSI has different queues assigned */
8795         if (vsi->type == I40E_VSI_MAIN)
8796                 used_queues = dev_data->nb_rx_queues -
8797                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8798         else if (vsi->type == I40E_VSI_VMDQ2)
8799                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8800         else {
8801                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8802                 return I40E_ERR_NO_AVAILABLE_VSI;
8803         }
8804
8805         qpnum_per_tc = used_queues / total_tc;
8806         /* Number of queues per enabled TC */
8807         if (qpnum_per_tc == 0) {
8808                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8809                 return I40E_ERR_INVALID_QP_ID;
8810         }
8811         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8812                                 I40E_MAX_Q_PER_TC);
8813         bsf = rte_bsf32(qpnum_per_tc);
8814
8815         /**
8816          * Configure TC and queue mapping parameters, for enabled TC,
8817          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8818          * default queue will serve it.
8819          */
8820         qp_idx = 0;
8821         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8822                 if (vsi->enabled_tc & (1 << i)) {
8823                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8824                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8825                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8826                         qp_idx += qpnum_per_tc;
8827                 } else
8828                         info->tc_mapping[i] = 0;
8829         }
8830
8831         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8832         if (vsi->type == I40E_VSI_SRIOV) {
8833                 info->mapping_flags |=
8834                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8835                 for (i = 0; i < vsi->nb_qps; i++)
8836                         info->queue_mapping[i] =
8837                                 rte_cpu_to_le_16(vsi->base_queue + i);
8838         } else {
8839                 info->mapping_flags |=
8840                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8841                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8842         }
8843         info->valid_sections |=
8844                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8845
8846         return I40E_SUCCESS;
8847 }
8848
8849 /*
8850  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8851  * @veb: VEB to be configured
8852  * @tc_map: enabled TC bitmap
8853  *
8854  * Returns 0 on success, negative value on failure
8855  */
8856 static enum i40e_status_code
8857 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8858 {
8859         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8860         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8861         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8862         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8863         enum i40e_status_code ret = I40E_SUCCESS;
8864         int i;
8865         uint32_t bw_max;
8866
8867         /* Check if enabled_tc is same as existing or new TCs */
8868         if (veb->enabled_tc == tc_map)
8869                 return ret;
8870
8871         /* configure tc bandwidth */
8872         memset(&veb_bw, 0, sizeof(veb_bw));
8873         veb_bw.tc_valid_bits = tc_map;
8874         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8875         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8876                 if (tc_map & BIT_ULL(i))
8877                         veb_bw.tc_bw_share_credits[i] = 1;
8878         }
8879         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8880                                                    &veb_bw, NULL);
8881         if (ret) {
8882                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8883                                   " per TC failed = %d",
8884                                   hw->aq.asq_last_status);
8885                 return ret;
8886         }
8887
8888         memset(&ets_query, 0, sizeof(ets_query));
8889         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8890                                                    &ets_query, NULL);
8891         if (ret != I40E_SUCCESS) {
8892                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8893                                  " configuration %u", hw->aq.asq_last_status);
8894                 return ret;
8895         }
8896         memset(&bw_query, 0, sizeof(bw_query));
8897         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8898                                                   &bw_query, NULL);
8899         if (ret != I40E_SUCCESS) {
8900                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8901                                  " configuration %u", hw->aq.asq_last_status);
8902                 return ret;
8903         }
8904
8905         /* store and print out BW info */
8906         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8907         veb->bw_info.bw_max = ets_query.tc_bw_max;
8908         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8909         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8910         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8911                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8912                      I40E_16_BIT_WIDTH);
8913         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8914                 veb->bw_info.bw_ets_share_credits[i] =
8915                                 bw_query.tc_bw_share_credits[i];
8916                 veb->bw_info.bw_ets_credits[i] =
8917                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8918                 /* 4 bits per TC, 4th bit is reserved */
8919                 veb->bw_info.bw_ets_max[i] =
8920                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8921                                   RTE_LEN2MASK(3, uint8_t));
8922                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8923                             veb->bw_info.bw_ets_share_credits[i]);
8924                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8925                             veb->bw_info.bw_ets_credits[i]);
8926                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8927                             veb->bw_info.bw_ets_max[i]);
8928         }
8929
8930         veb->enabled_tc = tc_map;
8931
8932         return ret;
8933 }
8934
8935
8936 /*
8937  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8938  * @vsi: VSI to be configured
8939  * @tc_map: enabled TC bitmap
8940  *
8941  * Returns 0 on success, negative value on failure
8942  */
8943 static enum i40e_status_code
8944 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8945 {
8946         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8947         struct i40e_vsi_context ctxt;
8948         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8949         enum i40e_status_code ret = I40E_SUCCESS;
8950         int i;
8951
8952         /* Check if enabled_tc is same as existing or new TCs */
8953         if (vsi->enabled_tc == tc_map)
8954                 return ret;
8955
8956         /* configure tc bandwidth */
8957         memset(&bw_data, 0, sizeof(bw_data));
8958         bw_data.tc_valid_bits = tc_map;
8959         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8960         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8961                 if (tc_map & BIT_ULL(i))
8962                         bw_data.tc_bw_credits[i] = 1;
8963         }
8964         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8965         if (ret) {
8966                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8967                         " per TC failed = %d",
8968                         hw->aq.asq_last_status);
8969                 goto out;
8970         }
8971         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8972                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8973
8974         /* Update Queue Pairs Mapping for currently enabled UPs */
8975         ctxt.seid = vsi->seid;
8976         ctxt.pf_num = hw->pf_id;
8977         ctxt.vf_num = 0;
8978         ctxt.uplink_seid = vsi->uplink_seid;
8979         ctxt.info = vsi->info;
8980         i40e_get_cap(hw);
8981         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8982         if (ret)
8983                 goto out;
8984
8985         /* Update the VSI after updating the VSI queue-mapping information */
8986         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8987         if (ret) {
8988                 PMD_INIT_LOG(ERR, "Failed to configure "
8989                             "TC queue mapping = %d",
8990                             hw->aq.asq_last_status);
8991                 goto out;
8992         }
8993         /* update the local VSI info with updated queue map */
8994         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8995                                         sizeof(vsi->info.tc_mapping));
8996         (void)rte_memcpy(&vsi->info.queue_mapping,
8997                         &ctxt.info.queue_mapping,
8998                 sizeof(vsi->info.queue_mapping));
8999         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9000         vsi->info.valid_sections = 0;
9001
9002         /* query and update current VSI BW information */
9003         ret = i40e_vsi_get_bw_config(vsi);
9004         if (ret) {
9005                 PMD_INIT_LOG(ERR,
9006                          "Failed updating vsi bw info, err %s aq_err %s",
9007                          i40e_stat_str(hw, ret),
9008                          i40e_aq_str(hw, hw->aq.asq_last_status));
9009                 goto out;
9010         }
9011
9012         vsi->enabled_tc = tc_map;
9013
9014 out:
9015         return ret;
9016 }
9017
9018 /*
9019  * i40e_dcb_hw_configure - program the dcb setting to hw
9020  * @pf: pf the configuration is taken on
9021  * @new_cfg: new configuration
9022  * @tc_map: enabled TC bitmap
9023  *
9024  * Returns 0 on success, negative value on failure
9025  */
9026 static enum i40e_status_code
9027 i40e_dcb_hw_configure(struct i40e_pf *pf,
9028                       struct i40e_dcbx_config *new_cfg,
9029                       uint8_t tc_map)
9030 {
9031         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9032         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9033         struct i40e_vsi *main_vsi = pf->main_vsi;
9034         struct i40e_vsi_list *vsi_list;
9035         enum i40e_status_code ret;
9036         int i;
9037         uint32_t val;
9038
9039         /* Use the FW API if FW > v4.4*/
9040         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9041               (hw->aq.fw_maj_ver >= 5))) {
9042                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9043                                   " to configure DCB");
9044                 return I40E_ERR_FIRMWARE_API_VERSION;
9045         }
9046
9047         /* Check if need reconfiguration */
9048         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9049                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9050                 return I40E_SUCCESS;
9051         }
9052
9053         /* Copy the new config to the current config */
9054         *old_cfg = *new_cfg;
9055         old_cfg->etsrec = old_cfg->etscfg;
9056         ret = i40e_set_dcb_config(hw);
9057         if (ret) {
9058                 PMD_INIT_LOG(ERR,
9059                          "Set DCB Config failed, err %s aq_err %s\n",
9060                          i40e_stat_str(hw, ret),
9061                          i40e_aq_str(hw, hw->aq.asq_last_status));
9062                 return ret;
9063         }
9064         /* set receive Arbiter to RR mode and ETS scheme by default */
9065         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9066                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9067                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9068                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9069                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9070                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9071                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9072                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9073                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9074                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9075                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9076                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9077                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9078         }
9079         /* get local mib to check whether it is configured correctly */
9080         /* IEEE mode */
9081         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9082         /* Get Local DCB Config */
9083         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9084                                      &hw->local_dcbx_config);
9085
9086         /* if Veb is created, need to update TC of it at first */
9087         if (main_vsi->veb) {
9088                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9089                 if (ret)
9090                         PMD_INIT_LOG(WARNING,
9091                                  "Failed configuring TC for VEB seid=%d\n",
9092                                  main_vsi->veb->seid);
9093         }
9094         /* Update each VSI */
9095         i40e_vsi_config_tc(main_vsi, tc_map);
9096         if (main_vsi->veb) {
9097                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9098                         /* Beside main VSI and VMDQ VSIs, only enable default
9099                          * TC for other VSIs
9100                          */
9101                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9102                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9103                                                          tc_map);
9104                         else
9105                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9106                                                          I40E_DEFAULT_TCMAP);
9107                         if (ret)
9108                                 PMD_INIT_LOG(WARNING,
9109                                          "Failed configuring TC for VSI seid=%d\n",
9110                                          vsi_list->vsi->seid);
9111                         /* continue */
9112                 }
9113         }
9114         return I40E_SUCCESS;
9115 }
9116
9117 /*
9118  * i40e_dcb_init_configure - initial dcb config
9119  * @dev: device being configured
9120  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9121  *
9122  * Returns 0 on success, negative value on failure
9123  */
9124 static int
9125 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9126 {
9127         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9129         int ret = 0;
9130
9131         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9132                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9133                 return -ENOTSUP;
9134         }
9135
9136         /* DCB initialization:
9137          * Update DCB configuration from the Firmware and configure
9138          * LLDP MIB change event.
9139          */
9140         if (sw_dcb == TRUE) {
9141                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9142                 if (ret != I40E_SUCCESS)
9143                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9144
9145                 ret = i40e_init_dcb(hw);
9146                 /* if sw_dcb, lldp agent is stopped, the return from
9147                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9148                  * adminq status.
9149                  */
9150                 if (ret != I40E_SUCCESS &&
9151                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9152                         memset(&hw->local_dcbx_config, 0,
9153                                 sizeof(struct i40e_dcbx_config));
9154                         /* set dcb default configuration */
9155                         hw->local_dcbx_config.etscfg.willing = 0;
9156                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9157                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9158                         hw->local_dcbx_config.etscfg.tsatable[0] =
9159                                                 I40E_IEEE_TSA_ETS;
9160                         hw->local_dcbx_config.etsrec =
9161                                 hw->local_dcbx_config.etscfg;
9162                         hw->local_dcbx_config.pfc.willing = 0;
9163                         hw->local_dcbx_config.pfc.pfccap =
9164                                                 I40E_MAX_TRAFFIC_CLASS;
9165                         /* FW needs one App to configure HW */
9166                         hw->local_dcbx_config.numapps = 1;
9167                         hw->local_dcbx_config.app[0].selector =
9168                                                 I40E_APP_SEL_ETHTYPE;
9169                         hw->local_dcbx_config.app[0].priority = 3;
9170                         hw->local_dcbx_config.app[0].protocolid =
9171                                                 I40E_APP_PROTOID_FCOE;
9172                         ret = i40e_set_dcb_config(hw);
9173                         if (ret) {
9174                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9175                                         " err = %d, aq_err = %d.", ret,
9176                                           hw->aq.asq_last_status);
9177                                 return -ENOSYS;
9178                         }
9179                 } else {
9180                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9181                                           " aq_err = %d.", ret,
9182                                           hw->aq.asq_last_status);
9183                         return -ENOTSUP;
9184                 }
9185         } else {
9186                 ret = i40e_aq_start_lldp(hw, NULL);
9187                 if (ret != I40E_SUCCESS)
9188                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9189
9190                 ret = i40e_init_dcb(hw);
9191                 if (!ret) {
9192                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9193                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9194                                                   " DCBX offload.");
9195                                 return -ENOTSUP;
9196                         }
9197                 } else {
9198                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9199                                           " aq_err = %d.", ret,
9200                                           hw->aq.asq_last_status);
9201                         return -ENOTSUP;
9202                 }
9203         }
9204         return 0;
9205 }
9206
9207 /*
9208  * i40e_dcb_setup - setup dcb related config
9209  * @dev: device being configured
9210  *
9211  * Returns 0 on success, negative value on failure
9212  */
9213 static int
9214 i40e_dcb_setup(struct rte_eth_dev *dev)
9215 {
9216         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9217         struct i40e_dcbx_config dcb_cfg;
9218         uint8_t tc_map = 0;
9219         int ret = 0;
9220
9221         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9222                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9223                 return -ENOTSUP;
9224         }
9225
9226         if (pf->vf_num != 0)
9227                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9228
9229         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9230         if (ret) {
9231                 PMD_INIT_LOG(ERR, "invalid dcb config");
9232                 return -EINVAL;
9233         }
9234         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9235         if (ret) {
9236                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9237                 return -ENOSYS;
9238         }
9239
9240         return 0;
9241 }
9242
9243 static int
9244 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9245                       struct rte_eth_dcb_info *dcb_info)
9246 {
9247         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9248         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9249         struct i40e_vsi *vsi = pf->main_vsi;
9250         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9251         uint16_t bsf, tc_mapping;
9252         int i, j = 0;
9253
9254         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9255                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9256         else
9257                 dcb_info->nb_tcs = 1;
9258         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9259                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9260         for (i = 0; i < dcb_info->nb_tcs; i++)
9261                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9262
9263         /* get queue mapping if vmdq is disabled */
9264         if (!pf->nb_cfg_vmdq_vsi) {
9265                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9266                         if (!(vsi->enabled_tc & (1 << i)))
9267                                 continue;
9268                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9269                         dcb_info->tc_queue.tc_rxq[j][i].base =
9270                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9271                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9272                         dcb_info->tc_queue.tc_txq[j][i].base =
9273                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9274                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9275                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9276                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9277                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9278                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9279                 }
9280                 return 0;
9281         }
9282
9283         /* get queue mapping if vmdq is enabled */
9284         do {
9285                 vsi = pf->vmdq[j].vsi;
9286                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9287                         if (!(vsi->enabled_tc & (1 << i)))
9288                                 continue;
9289                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9290                         dcb_info->tc_queue.tc_rxq[j][i].base =
9291                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9292                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9293                         dcb_info->tc_queue.tc_txq[j][i].base =
9294                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9295                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9296                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9297                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9298                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9299                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9300                 }
9301                 j++;
9302         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9303         return 0;
9304 }
9305
9306 static int
9307 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9308 {
9309         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9310         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9311         uint16_t interval =
9312                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9313         uint16_t msix_intr;
9314
9315         msix_intr = intr_handle->intr_vec[queue_id];
9316         if (msix_intr == I40E_MISC_VEC_ID)
9317                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9318                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9319                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9320                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9321                                (interval <<
9322                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9323         else
9324                 I40E_WRITE_REG(hw,
9325                                I40E_PFINT_DYN_CTLN(msix_intr -
9326                                                    I40E_RX_VEC_START),
9327                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9328                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9329                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9330                                (interval <<
9331                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9332
9333         I40E_WRITE_FLUSH(hw);
9334         rte_intr_enable(&dev->pci_dev->intr_handle);
9335
9336         return 0;
9337 }
9338
9339 static int
9340 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9341 {
9342         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9343         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9344         uint16_t msix_intr;
9345
9346         msix_intr = intr_handle->intr_vec[queue_id];
9347         if (msix_intr == I40E_MISC_VEC_ID)
9348                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9349         else
9350                 I40E_WRITE_REG(hw,
9351                                I40E_PFINT_DYN_CTLN(msix_intr -
9352                                                    I40E_RX_VEC_START),
9353                                0);
9354         I40E_WRITE_FLUSH(hw);
9355
9356         return 0;
9357 }
9358
9359 static int i40e_get_regs(struct rte_eth_dev *dev,
9360                          struct rte_dev_reg_info *regs)
9361 {
9362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9363         uint32_t *ptr_data = regs->data;
9364         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9365         const struct i40e_reg_info *reg_info;
9366
9367         if (ptr_data == NULL) {
9368                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9369                 regs->width = sizeof(uint32_t);
9370                 return 0;
9371         }
9372
9373         /* The first few registers have to be read using AQ operations */
9374         reg_idx = 0;
9375         while (i40e_regs_adminq[reg_idx].name) {
9376                 reg_info = &i40e_regs_adminq[reg_idx++];
9377                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9378                         for (arr_idx2 = 0;
9379                                         arr_idx2 <= reg_info->count2;
9380                                         arr_idx2++) {
9381                                 reg_offset = arr_idx * reg_info->stride1 +
9382                                         arr_idx2 * reg_info->stride2;
9383                                 reg_offset += reg_info->base_addr;
9384                                 ptr_data[reg_offset >> 2] =
9385                                         i40e_read_rx_ctl(hw, reg_offset);
9386                         }
9387         }
9388
9389         /* The remaining registers can be read using primitives */
9390         reg_idx = 0;
9391         while (i40e_regs_others[reg_idx].name) {
9392                 reg_info = &i40e_regs_others[reg_idx++];
9393                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9394                         for (arr_idx2 = 0;
9395                                         arr_idx2 <= reg_info->count2;
9396                                         arr_idx2++) {
9397                                 reg_offset = arr_idx * reg_info->stride1 +
9398                                         arr_idx2 * reg_info->stride2;
9399                                 reg_offset += reg_info->base_addr;
9400                                 ptr_data[reg_offset >> 2] =
9401                                         I40E_READ_REG(hw, reg_offset);
9402                         }
9403         }
9404
9405         return 0;
9406 }
9407
9408 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9409 {
9410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9411
9412         /* Convert word count to byte count */
9413         return hw->nvm.sr_size << 1;
9414 }
9415
9416 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9417                            struct rte_dev_eeprom_info *eeprom)
9418 {
9419         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9420         uint16_t *data = eeprom->data;
9421         uint16_t offset, length, cnt_words;
9422         int ret_code;
9423
9424         offset = eeprom->offset >> 1;
9425         length = eeprom->length >> 1;
9426         cnt_words = length;
9427
9428         if (offset > hw->nvm.sr_size ||
9429                 offset + length > hw->nvm.sr_size) {
9430                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9431                 return -EINVAL;
9432         }
9433
9434         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9435
9436         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9437         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9438                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9439                 return -EIO;
9440         }
9441
9442         return 0;
9443 }
9444
9445 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9446                                       struct ether_addr *mac_addr)
9447 {
9448         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9449
9450         if (!is_valid_assigned_ether_addr(mac_addr)) {
9451                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9452                 return;
9453         }
9454
9455         /* Flags: 0x3 updates port address */
9456         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9457 }
9458
9459 static int
9460 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9461 {
9462         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9463         struct rte_eth_dev_data *dev_data = pf->dev_data;
9464         uint32_t frame_size = mtu + ETHER_HDR_LEN
9465                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9466         int ret = 0;
9467
9468         /* check if mtu is within the allowed range */
9469         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9470                 return -EINVAL;
9471
9472         /* mtu setting is forbidden if port is start */
9473         if (dev_data->dev_started) {
9474                 PMD_DRV_LOG(ERR,
9475                             "port %d must be stopped before configuration\n",
9476                             dev_data->port_id);
9477                 return -EBUSY;
9478         }
9479
9480         if (frame_size > ETHER_MAX_LEN)
9481                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9482         else
9483                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9484
9485         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9486
9487         return ret;
9488 }