1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
246 char *fw_version, size_t fw_size);
247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
248 struct rte_eth_dev_info *dev_info);
249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
253 enum rte_vlan_type vlan_type,
255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
263 struct rte_eth_fc_conf *fc_conf);
264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
265 struct rte_eth_fc_conf *fc_conf);
266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
267 struct rte_eth_pfc_conf *pfc_conf);
268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr,
272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
277 struct rte_eth_rss_reta_entry64 *reta_conf,
280 static int i40e_get_cap(struct i40e_hw *hw);
281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
282 static int i40e_pf_setup(struct i40e_pf *pf);
283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
287 bool offset_loaded, uint64_t *offset, uint64_t *stat);
288 static void i40e_stat_update_48(struct i40e_hw *hw,
294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
295 static void i40e_dev_interrupt_handler(void *param);
296 static void i40e_dev_alarm_handler(void *param);
297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
298 uint32_t base, uint32_t num);
299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
305 static int i40e_veb_release(struct i40e_veb *veb);
306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
307 struct i40e_vsi *vsi);
308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
311 struct i40e_macvlan_filter *mv_f,
314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
318 struct rte_eth_rss_conf *rss_conf);
319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
322 struct rte_eth_udp_tunnel *udp_tunnel);
323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
334 static void i40e_configure_registers(struct i40e_hw *hw);
335 static void i40e_hw_init(struct rte_eth_dev *dev);
336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
344 struct rte_eth_mirror_conf *mirror_conf,
345 uint8_t sw_id, uint8_t on);
346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp,
353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp);
355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
369 static int i40e_get_regs(struct rte_eth_dev *dev,
370 struct rte_dev_reg_info *regs);
372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *eeprom);
377 static int i40e_get_module_info(struct rte_eth_dev *dev,
378 struct rte_eth_dev_module_info *modinfo);
379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
380 struct rte_dev_eeprom_info *info);
382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
383 struct ether_addr *mac_addr);
385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
387 static int i40e_ethertype_filter_convert(
388 const struct rte_eth_ethertype_filter *input,
389 struct i40e_ethertype_filter *filter);
390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
391 struct i40e_ethertype_filter *filter);
393 static int i40e_tunnel_filter_convert(
394 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
397 struct i40e_tunnel_filter *tunnel_filter);
398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
402 static void i40e_filter_restore(struct i40e_pf *pf);
403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
405 int i40e_logtype_init;
406 int i40e_logtype_driver;
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
413 ETH_I40E_USE_LATEST_VEC,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
632 struct rte_pci_device *pci_dev)
634 char name[RTE_ETH_NAME_MAX_LEN];
635 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
638 if (pci_dev->device.devargs) {
639 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
645 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
646 sizeof(struct i40e_adapter),
647 eth_dev_pci_specific_init, pci_dev,
648 eth_i40e_dev_init, NULL);
650 if (retval || eth_da.nb_representor_ports < 1)
653 /* probe VF representor ports */
654 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
655 pci_dev->device.name);
657 if (pf_ethdev == NULL)
660 for (i = 0; i < eth_da.nb_representor_ports; i++) {
661 struct i40e_vf_representor representor = {
662 .vf_id = eth_da.representor_ports[i],
663 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
664 pf_ethdev->data->dev_private)->switch_domain_id,
665 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
666 pf_ethdev->data->dev_private)
669 /* representor port net_bdf_port */
670 snprintf(name, sizeof(name), "net_%s_representor_%d",
671 pci_dev->device.name, eth_da.representor_ports[i]);
673 retval = rte_eth_dev_create(&pci_dev->device, name,
674 sizeof(struct i40e_vf_representor), NULL, NULL,
675 i40e_vf_representor_init, &representor);
678 PMD_DRV_LOG(ERR, "failed to create i40e vf "
679 "representor %s.", name);
685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
687 struct rte_eth_dev *ethdev;
689 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
697 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
700 static struct rte_pci_driver rte_i40e_pmd = {
701 .id_table = pci_id_i40e_map,
702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
703 RTE_PCI_DRV_IOVA_AS_VA,
704 .probe = eth_i40e_pci_probe,
705 .remove = eth_i40e_pci_remove,
709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
712 uint32_t ori_reg_val;
713 struct rte_eth_dev *dev;
715 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
716 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
717 i40e_write_rx_ctl(hw, reg_addr, reg_val);
718 if (ori_reg_val != reg_val)
720 "i40e device %s changed global register [0x%08x]."
721 " original: 0x%08x, new: 0x%08x",
722 dev->device->name, reg_addr, ori_reg_val, reg_val);
725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
729 #ifndef I40E_GLQF_ORT
730 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
732 #ifndef I40E_GLQF_PIT
733 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
735 #ifndef I40E_GLQF_L3_MAP
736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
742 * Initialize registers for parsing packet type of QinQ
743 * This should be removed from code once proper
744 * configuration API is added to avoid configuration conflicts
745 * between ports of the same device.
747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
751 static inline void i40e_config_automask(struct i40e_pf *pf)
753 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
756 /* INTENA flag is not auto-cleared for interrupt */
757 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
758 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
759 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
761 /* If support multi-driver, PF will use INT0. */
762 if (!pf->support_multi_driver)
763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
765 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
768 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
771 * Add a ethertype filter to drop all flow control frames transmitted
775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
783 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
784 I40E_FLOW_CONTROL_ETHERTYPE, flags,
785 pf->main_vsi_seid, 0,
789 "Failed to add filter to drop flow control frames from VSIs.");
793 floating_veb_list_handler(__rte_unused const char *key,
794 const char *floating_veb_value,
798 unsigned int count = 0;
801 bool *vf_floating_veb = opaque;
803 while (isblank(*floating_veb_value))
804 floating_veb_value++;
806 /* Reset floating VEB configuration for VFs */
807 for (idx = 0; idx < I40E_MAX_VF; idx++)
808 vf_floating_veb[idx] = false;
812 while (isblank(*floating_veb_value))
813 floating_veb_value++;
814 if (*floating_veb_value == '\0')
817 idx = strtoul(floating_veb_value, &end, 10);
818 if (errno || end == NULL)
820 while (isblank(*end))
824 } else if ((*end == ';') || (*end == '\0')) {
826 if (min == I40E_MAX_VF)
828 if (max >= I40E_MAX_VF)
829 max = I40E_MAX_VF - 1;
830 for (idx = min; idx <= max; idx++) {
831 vf_floating_veb[idx] = true;
838 floating_veb_value = end + 1;
839 } while (*end != '\0');
848 config_vf_floating_veb(struct rte_devargs *devargs,
849 uint16_t floating_veb,
850 bool *vf_floating_veb)
852 struct rte_kvargs *kvlist;
854 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
858 /* All the VFs attach to the floating VEB by default
859 * when the floating VEB is enabled.
861 for (i = 0; i < I40E_MAX_VF; i++)
862 vf_floating_veb[i] = true;
867 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
871 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
872 rte_kvargs_free(kvlist);
875 /* When the floating_veb_list parameter exists, all the VFs
876 * will attach to the legacy VEB firstly, then configure VFs
877 * to the floating VEB according to the floating_veb_list.
879 if (rte_kvargs_process(kvlist, floating_veb_list,
880 floating_veb_list_handler,
881 vf_floating_veb) < 0) {
882 rte_kvargs_free(kvlist);
885 rte_kvargs_free(kvlist);
889 i40e_check_floating_handler(__rte_unused const char *key,
891 __rte_unused void *opaque)
893 if (strcmp(value, "1"))
900 is_floating_veb_supported(struct rte_devargs *devargs)
902 struct rte_kvargs *kvlist;
903 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
908 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
912 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
913 rte_kvargs_free(kvlist);
916 /* Floating VEB is enabled when there's key-value:
917 * enable_floating_veb=1
919 if (rte_kvargs_process(kvlist, floating_veb_key,
920 i40e_check_floating_handler, NULL) < 0) {
921 rte_kvargs_free(kvlist);
924 rte_kvargs_free(kvlist);
930 config_floating_veb(struct rte_eth_dev *dev)
932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
938 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
940 is_floating_veb_supported(pci_dev->device.devargs);
941 config_vf_floating_veb(pci_dev->device.devargs,
943 pf->floating_veb_list);
945 pf->floating_veb = false;
949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
957 char ethertype_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters ethertype_hash_params = {
961 .name = ethertype_hash_name,
962 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
963 .key_len = sizeof(struct i40e_ethertype_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize ethertype filter rule list and hash */
970 TAILQ_INIT(ðertype_rule->ethertype_list);
971 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
972 "ethertype_%s", dev->device->name);
973 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
974 if (!ethertype_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
978 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
979 sizeof(struct i40e_ethertype_filter *) *
980 I40E_MAX_ETHERTYPE_FILTER_NUM,
982 if (!ethertype_rule->hash_map) {
984 "Failed to allocate memory for ethertype hash map!");
986 goto err_ethertype_hash_map_alloc;
991 err_ethertype_hash_map_alloc:
992 rte_hash_free(ethertype_rule->hash_table);
998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters tunnel_hash_params = {
1006 .name = tunnel_hash_name,
1007 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize tunnel filter rule list and hash */
1015 TAILQ_INIT(&tunnel_rule->tunnel_list);
1016 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017 "tunnel_%s", dev->device->name);
1018 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019 if (!tunnel_rule->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024 sizeof(struct i40e_tunnel_filter *) *
1025 I40E_MAX_TUNNEL_FILTER_NUM,
1027 if (!tunnel_rule->hash_map) {
1029 "Failed to allocate memory for tunnel hash map!");
1031 goto err_tunnel_hash_map_alloc;
1036 err_tunnel_hash_map_alloc:
1037 rte_hash_free(tunnel_rule->hash_table);
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046 struct i40e_fdir_info *fdir_info = &pf->fdir;
1047 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 struct rte_hash_parameters fdir_hash_params = {
1051 .name = fdir_hash_name,
1052 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053 .key_len = sizeof(struct i40e_fdir_input),
1054 .hash_func = rte_hash_crc,
1055 .hash_func_init_val = 0,
1056 .socket_id = rte_socket_id(),
1059 /* Initialize flow director filter rule list and hash */
1060 TAILQ_INIT(&fdir_info->fdir_list);
1061 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062 "fdir_%s", dev->device->name);
1063 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064 if (!fdir_info->hash_table) {
1065 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069 sizeof(struct i40e_fdir_filter *) *
1070 I40E_MAX_FDIR_FILTER_NUM,
1072 if (!fdir_info->hash_map) {
1074 "Failed to allocate memory for fdir hash map!");
1076 goto err_fdir_hash_map_alloc;
1080 err_fdir_hash_map_alloc:
1081 rte_hash_free(fdir_info->hash_table);
1087 i40e_init_customized_info(struct i40e_pf *pf)
1091 /* Initialize customized pctype */
1092 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093 pf->customized_pctype[i].index = i;
1094 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095 pf->customized_pctype[i].valid = false;
1098 pf->gtp_support = false;
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106 struct i40e_queue_regions *info = &pf->queue_region;
1109 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1112 memset(info, 0, sizeof(struct i40e_queue_regions));
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1121 unsigned long support_multi_driver;
1124 pf = (struct i40e_pf *)opaque;
1127 support_multi_driver = strtoul(value, &end, 10);
1128 if (errno != 0 || end == value || *end != 0) {
1129 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1133 if (support_multi_driver == 1 || support_multi_driver == 0)
1134 pf->support_multi_driver = (bool)support_multi_driver;
1136 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137 "enable global configuration by default."
1138 ETH_I40E_SUPPORT_MULTI_DRIVER);
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146 struct rte_kvargs *kvlist;
1149 /* Enable global configuration by default */
1150 pf->support_multi_driver = false;
1152 if (!dev->device->devargs)
1155 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1159 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160 if (!kvargs_count) {
1161 rte_kvargs_free(kvlist);
1165 if (kvargs_count > 1)
1166 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167 "the first invalid or last valid one is used !",
1168 ETH_I40E_SUPPORT_MULTI_DRIVER);
1170 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171 i40e_parse_multi_drv_handler, pf) < 0) {
1172 rte_kvargs_free(kvlist);
1176 rte_kvargs_free(kvlist);
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182 uint32_t reg_addr, uint64_t reg_val,
1183 struct i40e_asq_cmd_details *cmd_details)
1185 uint64_t ori_reg_val;
1186 struct rte_eth_dev *dev;
1189 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190 if (ret != I40E_SUCCESS) {
1192 "Fail to debug read from 0x%08x",
1196 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1198 if (ori_reg_val != reg_val)
1199 PMD_DRV_LOG(WARNING,
1200 "i40e device %s changed global register [0x%08x]."
1201 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202 dev->device->name, reg_addr, ori_reg_val, reg_val);
1204 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1212 struct i40e_adapter *ad;
1215 ad = (struct i40e_adapter *)opaque;
1217 use_latest_vec = atoi(value);
1219 if (use_latest_vec != 0 && use_latest_vec != 1)
1220 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1222 ad->use_latest_vec = (uint8_t)use_latest_vec;
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1230 struct i40e_adapter *ad =
1231 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232 struct rte_kvargs *kvlist;
1235 ad->use_latest_vec = false;
1237 if (!dev->device->devargs)
1240 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1244 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245 if (!kvargs_count) {
1246 rte_kvargs_free(kvlist);
1250 if (kvargs_count > 1)
1251 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252 "the first invalid or last valid one is used !",
1253 ETH_I40E_USE_LATEST_VEC);
1255 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256 i40e_parse_latest_vec_handler, ad) < 0) {
1257 rte_kvargs_free(kvlist);
1261 rte_kvargs_free(kvlist);
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1270 struct rte_pci_device *pci_dev;
1271 struct rte_intr_handle *intr_handle;
1272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 struct i40e_vsi *vsi;
1277 uint8_t aq_fail = 0;
1279 PMD_INIT_FUNC_TRACE();
1281 dev->dev_ops = &i40e_eth_dev_ops;
1282 dev->rx_pkt_burst = i40e_recv_pkts;
1283 dev->tx_pkt_burst = i40e_xmit_pkts;
1284 dev->tx_pkt_prepare = i40e_prep_pkts;
1286 /* for secondary processes, we don't initialise any further as primary
1287 * has already done this work. Only check we don't need a different
1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290 i40e_set_rx_function(dev);
1291 i40e_set_tx_function(dev);
1294 i40e_set_default_ptype_table(dev);
1295 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296 intr_handle = &pci_dev->intr_handle;
1298 rte_eth_copy_pci_info(dev, pci_dev);
1300 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301 pf->adapter->eth_dev = dev;
1302 pf->dev_data = dev->data;
1304 hw->back = I40E_PF_TO_ADAPTER(pf);
1305 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308 "Hardware is not available, as address is NULL");
1312 hw->vendor_id = pci_dev->id.vendor_id;
1313 hw->device_id = pci_dev->id.device_id;
1314 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316 hw->bus.device = pci_dev->addr.devid;
1317 hw->bus.func = pci_dev->addr.function;
1318 hw->adapter_stopped = 0;
1321 * Switch Tag value should not be identical to either the First Tag
1322 * or Second Tag values. So set something other than common Ethertype
1323 * for internal switching.
1325 hw->switch_tag = 0xffff;
1327 /* Check if need to support multi-driver */
1328 i40e_support_multi_driver(dev);
1329 /* Check if users want the latest supported vec path */
1330 i40e_use_latest_vec(dev);
1332 /* Make sure all is clean before doing PF reset */
1335 /* Reset here to make sure all is clean for each PF */
1336 ret = i40e_pf_reset(hw);
1338 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1342 /* Initialize the shared code (base driver) */
1343 ret = i40e_init_shared_code(hw);
1345 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1349 /* Initialize the parameters for adminq */
1350 i40e_init_adminq_parameter(hw);
1351 ret = i40e_init_adminq(hw);
1352 if (ret != I40E_SUCCESS) {
1353 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1356 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1357 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1358 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1359 ((hw->nvm.version >> 12) & 0xf),
1360 ((hw->nvm.version >> 4) & 0xff),
1361 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1363 /* Initialize the hardware */
1366 i40e_config_automask(pf);
1368 i40e_set_default_pctype_table(dev);
1371 * To work around the NVM issue, initialize registers
1372 * for packet type of QinQ by software.
1373 * It should be removed once issues are fixed in NVM.
1375 if (!pf->support_multi_driver)
1376 i40e_GLQF_reg_init(hw);
1378 /* Initialize the input set for filters (hash and fd) to default value */
1379 i40e_filter_input_set_init(pf);
1381 /* initialise the L3_MAP register */
1382 if (!pf->support_multi_driver) {
1383 ret = i40e_aq_debug_write_global_register(hw,
1384 I40E_GLQF_L3_MAP(40),
1387 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1390 "Global register 0x%08x is changed with 0x28",
1391 I40E_GLQF_L3_MAP(40));
1394 /* Need the special FW version to support floating VEB */
1395 config_floating_veb(dev);
1396 /* Clear PXE mode */
1397 i40e_clear_pxe_mode(hw);
1398 i40e_dev_sync_phy_type(hw);
1401 * On X710, performance number is far from the expectation on recent
1402 * firmware versions. The fix for this issue may not be integrated in
1403 * the following firmware version. So the workaround in software driver
1404 * is needed. It needs to modify the initial values of 3 internal only
1405 * registers. Note that the workaround can be removed when it is fixed
1406 * in firmware in the future.
1408 i40e_configure_registers(hw);
1410 /* Get hw capabilities */
1411 ret = i40e_get_cap(hw);
1412 if (ret != I40E_SUCCESS) {
1413 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1414 goto err_get_capabilities;
1417 /* Initialize parameters for PF */
1418 ret = i40e_pf_parameter_init(dev);
1420 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1421 goto err_parameter_init;
1424 /* Initialize the queue management */
1425 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1427 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1428 goto err_qp_pool_init;
1430 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1431 hw->func_caps.num_msix_vectors - 1);
1433 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1434 goto err_msix_pool_init;
1437 /* Initialize lan hmc */
1438 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1439 hw->func_caps.num_rx_qp, 0, 0);
1440 if (ret != I40E_SUCCESS) {
1441 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1442 goto err_init_lan_hmc;
1445 /* Configure lan hmc */
1446 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1447 if (ret != I40E_SUCCESS) {
1448 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1449 goto err_configure_lan_hmc;
1452 /* Get and check the mac address */
1453 i40e_get_mac_addr(hw, hw->mac.addr);
1454 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1455 PMD_INIT_LOG(ERR, "mac address is not valid");
1457 goto err_get_mac_addr;
1459 /* Copy the permanent MAC address */
1460 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1461 (struct ether_addr *) hw->mac.perm_addr);
1463 /* Disable flow control */
1464 hw->fc.requested_mode = I40E_FC_NONE;
1465 i40e_set_fc(hw, &aq_fail, TRUE);
1467 /* Set the global registers with default ether type value */
1468 if (!pf->support_multi_driver) {
1469 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1471 if (ret != I40E_SUCCESS) {
1473 "Failed to set the default outer "
1475 goto err_setup_pf_switch;
1479 /* PF setup, which includes VSI setup */
1480 ret = i40e_pf_setup(pf);
1482 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1483 goto err_setup_pf_switch;
1486 /* reset all stats of the device, including pf and main vsi */
1487 i40e_dev_stats_reset(dev);
1491 /* Disable double vlan by default */
1492 i40e_vsi_config_double_vlan(vsi, FALSE);
1494 /* Disable S-TAG identification when floating_veb is disabled */
1495 if (!pf->floating_veb) {
1496 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1497 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1498 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1499 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1503 if (!vsi->max_macaddrs)
1504 len = ETHER_ADDR_LEN;
1506 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1508 /* Should be after VSI initialized */
1509 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1510 if (!dev->data->mac_addrs) {
1512 "Failed to allocated memory for storing mac address");
1515 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1516 &dev->data->mac_addrs[0]);
1518 /* Init dcb to sw mode by default */
1519 ret = i40e_dcb_init_configure(dev, TRUE);
1520 if (ret != I40E_SUCCESS) {
1521 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1522 pf->flags &= ~I40E_FLAG_DCB;
1524 /* Update HW struct after DCB configuration */
1527 /* initialize pf host driver to setup SRIOV resource if applicable */
1528 i40e_pf_host_init(dev);
1530 /* register callback func to eal lib */
1531 rte_intr_callback_register(intr_handle,
1532 i40e_dev_interrupt_handler, dev);
1534 /* configure and enable device interrupt */
1535 i40e_pf_config_irq0(hw, TRUE);
1536 i40e_pf_enable_irq0(hw);
1538 /* enable uio intr after callback register */
1539 rte_intr_enable(intr_handle);
1541 /* By default disable flexible payload in global configuration */
1542 if (!pf->support_multi_driver)
1543 i40e_flex_payload_reg_set_default(hw);
1546 * Add an ethertype filter to drop all flow control frames transmitted
1547 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1550 i40e_add_tx_flow_control_drop_filter(pf);
1552 /* Set the max frame size to 0x2600 by default,
1553 * in case other drivers changed the default value.
1555 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1557 /* initialize mirror rule list */
1558 TAILQ_INIT(&pf->mirror_list);
1560 /* initialize Traffic Manager configuration */
1561 i40e_tm_conf_init(dev);
1563 /* Initialize customized information */
1564 i40e_init_customized_info(pf);
1566 ret = i40e_init_ethtype_filter_list(dev);
1568 goto err_init_ethtype_filter_list;
1569 ret = i40e_init_tunnel_filter_list(dev);
1571 goto err_init_tunnel_filter_list;
1572 ret = i40e_init_fdir_filter_list(dev);
1574 goto err_init_fdir_filter_list;
1576 /* initialize queue region configuration */
1577 i40e_init_queue_region_conf(dev);
1579 /* initialize rss configuration from rte_flow */
1580 memset(&pf->rss_info, 0,
1581 sizeof(struct i40e_rte_flow_rss_conf));
1585 err_init_fdir_filter_list:
1586 rte_free(pf->tunnel.hash_table);
1587 rte_free(pf->tunnel.hash_map);
1588 err_init_tunnel_filter_list:
1589 rte_free(pf->ethertype.hash_table);
1590 rte_free(pf->ethertype.hash_map);
1591 err_init_ethtype_filter_list:
1592 rte_free(dev->data->mac_addrs);
1594 i40e_vsi_release(pf->main_vsi);
1595 err_setup_pf_switch:
1597 err_configure_lan_hmc:
1598 (void)i40e_shutdown_lan_hmc(hw);
1600 i40e_res_pool_destroy(&pf->msix_pool);
1602 i40e_res_pool_destroy(&pf->qp_pool);
1605 err_get_capabilities:
1606 (void)i40e_shutdown_adminq(hw);
1612 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1614 struct i40e_ethertype_filter *p_ethertype;
1615 struct i40e_ethertype_rule *ethertype_rule;
1617 ethertype_rule = &pf->ethertype;
1618 /* Remove all ethertype filter rules and hash */
1619 if (ethertype_rule->hash_map)
1620 rte_free(ethertype_rule->hash_map);
1621 if (ethertype_rule->hash_table)
1622 rte_hash_free(ethertype_rule->hash_table);
1624 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1625 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1626 p_ethertype, rules);
1627 rte_free(p_ethertype);
1632 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1634 struct i40e_tunnel_filter *p_tunnel;
1635 struct i40e_tunnel_rule *tunnel_rule;
1637 tunnel_rule = &pf->tunnel;
1638 /* Remove all tunnel director rules and hash */
1639 if (tunnel_rule->hash_map)
1640 rte_free(tunnel_rule->hash_map);
1641 if (tunnel_rule->hash_table)
1642 rte_hash_free(tunnel_rule->hash_table);
1644 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1645 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1651 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1653 struct i40e_fdir_filter *p_fdir;
1654 struct i40e_fdir_info *fdir_info;
1656 fdir_info = &pf->fdir;
1657 /* Remove all flow director rules and hash */
1658 if (fdir_info->hash_map)
1659 rte_free(fdir_info->hash_map);
1660 if (fdir_info->hash_table)
1661 rte_hash_free(fdir_info->hash_table);
1663 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1664 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1669 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1672 * Disable by default flexible payload
1673 * for corresponding L2/L3/L4 layers.
1675 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1676 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1677 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1681 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1684 struct rte_pci_device *pci_dev;
1685 struct rte_intr_handle *intr_handle;
1687 struct i40e_filter_control_settings settings;
1688 struct rte_flow *p_flow;
1690 uint8_t aq_fail = 0;
1693 PMD_INIT_FUNC_TRACE();
1695 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1698 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1701 intr_handle = &pci_dev->intr_handle;
1703 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1705 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1707 if (hw->adapter_stopped == 0)
1708 i40e_dev_close(dev);
1710 dev->dev_ops = NULL;
1711 dev->rx_pkt_burst = NULL;
1712 dev->tx_pkt_burst = NULL;
1714 /* Clear PXE mode */
1715 i40e_clear_pxe_mode(hw);
1717 /* Unconfigure filter control */
1718 memset(&settings, 0, sizeof(settings));
1719 ret = i40e_set_filter_control(hw, &settings);
1721 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1724 /* Disable flow control */
1725 hw->fc.requested_mode = I40E_FC_NONE;
1726 i40e_set_fc(hw, &aq_fail, TRUE);
1728 /* uninitialize pf host driver */
1729 i40e_pf_host_uninit(dev);
1731 /* disable uio intr before callback unregister */
1732 rte_intr_disable(intr_handle);
1734 /* unregister callback func to eal lib */
1736 ret = rte_intr_callback_unregister(intr_handle,
1737 i40e_dev_interrupt_handler, dev);
1740 } else if (ret != -EAGAIN) {
1742 "intr callback unregister failed: %d",
1746 i40e_msec_delay(500);
1747 } while (retries++ < 5);
1749 i40e_rm_ethtype_filter_list(pf);
1750 i40e_rm_tunnel_filter_list(pf);
1751 i40e_rm_fdir_filter_list(pf);
1753 /* Remove all flows */
1754 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1755 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1759 /* Remove all Traffic Manager configuration */
1760 i40e_tm_conf_uninit(dev);
1766 i40e_dev_configure(struct rte_eth_dev *dev)
1768 struct i40e_adapter *ad =
1769 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1775 ret = i40e_dev_sync_phy_type(hw);
1779 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1780 * bulk allocation or vector Rx preconditions we will reset it.
1782 ad->rx_bulk_alloc_allowed = true;
1783 ad->rx_vec_allowed = true;
1784 ad->tx_simple_allowed = true;
1785 ad->tx_vec_allowed = true;
1787 /* Only legacy filter API needs the following fdir config. So when the
1788 * legacy filter API is deprecated, the following codes should also be
1791 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1792 ret = i40e_fdir_setup(pf);
1793 if (ret != I40E_SUCCESS) {
1794 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1797 ret = i40e_fdir_configure(dev);
1799 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1803 i40e_fdir_teardown(pf);
1805 ret = i40e_dev_init_vlan(dev);
1810 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1811 * RSS setting have different requirements.
1812 * General PMD driver call sequence are NIC init, configure,
1813 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1814 * will try to lookup the VSI that specific queue belongs to if VMDQ
1815 * applicable. So, VMDQ setting has to be done before
1816 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1817 * For RSS setting, it will try to calculate actual configured RX queue
1818 * number, which will be available after rx_queue_setup(). dev_start()
1819 * function is good to place RSS setup.
1821 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1822 ret = i40e_vmdq_setup(dev);
1827 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1828 ret = i40e_dcb_setup(dev);
1830 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1835 TAILQ_INIT(&pf->flow_list);
1840 /* need to release vmdq resource if exists */
1841 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1842 i40e_vsi_release(pf->vmdq[i].vsi);
1843 pf->vmdq[i].vsi = NULL;
1848 /* Need to release fdir resource if exists.
1849 * Only legacy filter API needs the following fdir config. So when the
1850 * legacy filter API is deprecated, the following code should also be
1853 i40e_fdir_teardown(pf);
1858 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1860 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1861 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1862 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1863 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1864 uint16_t msix_vect = vsi->msix_intr;
1867 for (i = 0; i < vsi->nb_qps; i++) {
1868 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1869 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1873 if (vsi->type != I40E_VSI_SRIOV) {
1874 if (!rte_intr_allow_others(intr_handle)) {
1875 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1876 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1878 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1881 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1882 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1884 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1889 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1890 vsi->user_param + (msix_vect - 1);
1892 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1893 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1895 I40E_WRITE_FLUSH(hw);
1899 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1900 int base_queue, int nb_queue,
1905 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1906 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1908 /* Bind all RX queues to allocated MSIX interrupt */
1909 for (i = 0; i < nb_queue; i++) {
1910 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1911 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1912 ((base_queue + i + 1) <<
1913 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1914 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1915 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1917 if (i == nb_queue - 1)
1918 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1919 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1922 /* Write first RX queue to Link list register as the head element */
1923 if (vsi->type != I40E_VSI_SRIOV) {
1925 i40e_calc_itr_interval(1, pf->support_multi_driver);
1927 if (msix_vect == I40E_MISC_VEC_ID) {
1928 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1930 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1932 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1934 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1937 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1939 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1941 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1943 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1950 if (msix_vect == I40E_MISC_VEC_ID) {
1952 I40E_VPINT_LNKLST0(vsi->user_param),
1954 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1956 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1958 /* num_msix_vectors_vf needs to minus irq0 */
1959 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1960 vsi->user_param + (msix_vect - 1);
1962 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1964 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1966 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1970 I40E_WRITE_FLUSH(hw);
1974 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1976 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1977 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1978 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1979 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1980 uint16_t msix_vect = vsi->msix_intr;
1981 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1982 uint16_t queue_idx = 0;
1986 for (i = 0; i < vsi->nb_qps; i++) {
1987 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1988 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1991 /* VF bind interrupt */
1992 if (vsi->type == I40E_VSI_SRIOV) {
1993 __vsi_queues_bind_intr(vsi, msix_vect,
1994 vsi->base_queue, vsi->nb_qps,
1999 /* PF & VMDq bind interrupt */
2000 if (rte_intr_dp_is_en(intr_handle)) {
2001 if (vsi->type == I40E_VSI_MAIN) {
2004 } else if (vsi->type == I40E_VSI_VMDQ2) {
2005 struct i40e_vsi *main_vsi =
2006 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2007 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2012 for (i = 0; i < vsi->nb_used_qps; i++) {
2014 if (!rte_intr_allow_others(intr_handle))
2015 /* allow to share MISC_VEC_ID */
2016 msix_vect = I40E_MISC_VEC_ID;
2018 /* no enough msix_vect, map all to one */
2019 __vsi_queues_bind_intr(vsi, msix_vect,
2020 vsi->base_queue + i,
2021 vsi->nb_used_qps - i,
2023 for (; !!record && i < vsi->nb_used_qps; i++)
2024 intr_handle->intr_vec[queue_idx + i] =
2028 /* 1:1 queue/msix_vect mapping */
2029 __vsi_queues_bind_intr(vsi, msix_vect,
2030 vsi->base_queue + i, 1,
2033 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2041 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2043 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2044 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2045 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2046 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2047 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2048 uint16_t msix_intr, i;
2050 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2051 for (i = 0; i < vsi->nb_msix; i++) {
2052 msix_intr = vsi->msix_intr + i;
2053 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2054 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2055 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2056 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2059 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2060 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2061 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2062 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2064 I40E_WRITE_FLUSH(hw);
2068 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2070 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2071 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2072 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2073 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2074 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2075 uint16_t msix_intr, i;
2077 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2078 for (i = 0; i < vsi->nb_msix; i++) {
2079 msix_intr = vsi->msix_intr + i;
2080 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2081 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2084 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2085 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2087 I40E_WRITE_FLUSH(hw);
2090 static inline uint8_t
2091 i40e_parse_link_speeds(uint16_t link_speeds)
2093 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2095 if (link_speeds & ETH_LINK_SPEED_40G)
2096 link_speed |= I40E_LINK_SPEED_40GB;
2097 if (link_speeds & ETH_LINK_SPEED_25G)
2098 link_speed |= I40E_LINK_SPEED_25GB;
2099 if (link_speeds & ETH_LINK_SPEED_20G)
2100 link_speed |= I40E_LINK_SPEED_20GB;
2101 if (link_speeds & ETH_LINK_SPEED_10G)
2102 link_speed |= I40E_LINK_SPEED_10GB;
2103 if (link_speeds & ETH_LINK_SPEED_1G)
2104 link_speed |= I40E_LINK_SPEED_1GB;
2105 if (link_speeds & ETH_LINK_SPEED_100M)
2106 link_speed |= I40E_LINK_SPEED_100MB;
2112 i40e_phy_conf_link(struct i40e_hw *hw,
2114 uint8_t force_speed,
2117 enum i40e_status_code status;
2118 struct i40e_aq_get_phy_abilities_resp phy_ab;
2119 struct i40e_aq_set_phy_config phy_conf;
2120 enum i40e_aq_phy_type cnt;
2121 uint8_t avail_speed;
2122 uint32_t phy_type_mask = 0;
2124 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2125 I40E_AQ_PHY_FLAG_PAUSE_RX |
2126 I40E_AQ_PHY_FLAG_PAUSE_RX |
2127 I40E_AQ_PHY_FLAG_LOW_POWER;
2130 /* To get phy capabilities of available speeds. */
2131 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2134 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2138 avail_speed = phy_ab.link_speed;
2140 /* To get the current phy config. */
2141 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2144 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2149 /* If link needs to go up and it is in autoneg mode the speed is OK,
2150 * no need to set up again.
2152 if (is_up && phy_ab.phy_type != 0 &&
2153 abilities & I40E_AQ_PHY_AN_ENABLED &&
2154 phy_ab.link_speed != 0)
2155 return I40E_SUCCESS;
2157 memset(&phy_conf, 0, sizeof(phy_conf));
2159 /* bits 0-2 use the values from get_phy_abilities_resp */
2161 abilities |= phy_ab.abilities & mask;
2163 phy_conf.abilities = abilities;
2165 /* If link needs to go up, but the force speed is not supported,
2166 * Warn users and config the default available speeds.
2168 if (is_up && !(force_speed & avail_speed)) {
2169 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2170 phy_conf.link_speed = avail_speed;
2172 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2175 /* PHY type mask needs to include each type except PHY type extension */
2176 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2177 phy_type_mask |= 1 << cnt;
2179 /* use get_phy_abilities_resp value for the rest */
2180 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2181 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2182 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2183 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2184 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2185 phy_conf.eee_capability = phy_ab.eee_capability;
2186 phy_conf.eeer = phy_ab.eeer_val;
2187 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2189 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2190 phy_ab.abilities, phy_ab.link_speed);
2191 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2192 phy_conf.abilities, phy_conf.link_speed);
2194 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2198 return I40E_SUCCESS;
2202 i40e_apply_link_speed(struct rte_eth_dev *dev)
2205 uint8_t abilities = 0;
2206 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207 struct rte_eth_conf *conf = &dev->data->dev_conf;
2209 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2210 conf->link_speeds = ETH_LINK_SPEED_40G |
2211 ETH_LINK_SPEED_25G |
2212 ETH_LINK_SPEED_20G |
2213 ETH_LINK_SPEED_10G |
2215 ETH_LINK_SPEED_100M;
2217 speed = i40e_parse_link_speeds(conf->link_speeds);
2218 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2219 I40E_AQ_PHY_AN_ENABLED |
2220 I40E_AQ_PHY_LINK_ENABLED;
2222 return i40e_phy_conf_link(hw, abilities, speed, true);
2226 i40e_dev_start(struct rte_eth_dev *dev)
2228 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2229 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2230 struct i40e_vsi *main_vsi = pf->main_vsi;
2232 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2233 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2234 uint32_t intr_vector = 0;
2235 struct i40e_vsi *vsi;
2237 hw->adapter_stopped = 0;
2239 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2241 "Invalid link_speeds for port %u, autonegotiation disabled",
2242 dev->data->port_id);
2246 rte_intr_disable(intr_handle);
2248 if ((rte_intr_cap_multiple(intr_handle) ||
2249 !RTE_ETH_DEV_SRIOV(dev).active) &&
2250 dev->data->dev_conf.intr_conf.rxq != 0) {
2251 intr_vector = dev->data->nb_rx_queues;
2252 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2257 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2258 intr_handle->intr_vec =
2259 rte_zmalloc("intr_vec",
2260 dev->data->nb_rx_queues * sizeof(int),
2262 if (!intr_handle->intr_vec) {
2264 "Failed to allocate %d rx_queues intr_vec",
2265 dev->data->nb_rx_queues);
2270 /* Initialize VSI */
2271 ret = i40e_dev_rxtx_init(pf);
2272 if (ret != I40E_SUCCESS) {
2273 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2277 /* Map queues with MSIX interrupt */
2278 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2279 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2280 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2281 i40e_vsi_enable_queues_intr(main_vsi);
2283 /* Map VMDQ VSI queues with MSIX interrupt */
2284 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2285 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2286 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2287 I40E_ITR_INDEX_DEFAULT);
2288 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2291 /* enable FDIR MSIX interrupt */
2292 if (pf->fdir.fdir_vsi) {
2293 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2294 I40E_ITR_INDEX_NONE);
2295 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2298 /* Enable all queues which have been configured */
2299 ret = i40e_dev_switch_queues(pf, TRUE);
2300 if (ret != I40E_SUCCESS) {
2301 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2305 /* Enable receiving broadcast packets */
2306 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2307 if (ret != I40E_SUCCESS)
2308 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2310 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2311 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2313 if (ret != I40E_SUCCESS)
2314 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2317 /* Enable the VLAN promiscuous mode. */
2319 for (i = 0; i < pf->vf_num; i++) {
2320 vsi = pf->vfs[i].vsi;
2321 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2326 /* Enable mac loopback mode */
2327 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2328 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2329 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2330 if (ret != I40E_SUCCESS) {
2331 PMD_DRV_LOG(ERR, "fail to set loopback link");
2336 /* Apply link configure */
2337 ret = i40e_apply_link_speed(dev);
2338 if (I40E_SUCCESS != ret) {
2339 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2343 if (!rte_intr_allow_others(intr_handle)) {
2344 rte_intr_callback_unregister(intr_handle,
2345 i40e_dev_interrupt_handler,
2347 /* configure and enable device interrupt */
2348 i40e_pf_config_irq0(hw, FALSE);
2349 i40e_pf_enable_irq0(hw);
2351 if (dev->data->dev_conf.intr_conf.lsc != 0)
2353 "lsc won't enable because of no intr multiplex");
2355 ret = i40e_aq_set_phy_int_mask(hw,
2356 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2357 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2358 I40E_AQ_EVENT_MEDIA_NA), NULL);
2359 if (ret != I40E_SUCCESS)
2360 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2362 /* Call get_link_info aq commond to enable/disable LSE */
2363 i40e_dev_link_update(dev, 0);
2366 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2367 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2368 i40e_dev_alarm_handler, dev);
2370 /* enable uio intr after callback register */
2371 rte_intr_enable(intr_handle);
2374 i40e_filter_restore(pf);
2376 if (pf->tm_conf.root && !pf->tm_conf.committed)
2377 PMD_DRV_LOG(WARNING,
2378 "please call hierarchy_commit() "
2379 "before starting the port");
2381 return I40E_SUCCESS;
2384 i40e_dev_switch_queues(pf, FALSE);
2385 i40e_dev_clear_queues(dev);
2391 i40e_dev_stop(struct rte_eth_dev *dev)
2393 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2394 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395 struct i40e_vsi *main_vsi = pf->main_vsi;
2396 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2397 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2400 if (hw->adapter_stopped == 1)
2403 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2404 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2405 rte_intr_enable(intr_handle);
2408 /* Disable all queues */
2409 i40e_dev_switch_queues(pf, FALSE);
2411 /* un-map queues with interrupt registers */
2412 i40e_vsi_disable_queues_intr(main_vsi);
2413 i40e_vsi_queues_unbind_intr(main_vsi);
2415 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2416 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2417 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2420 if (pf->fdir.fdir_vsi) {
2421 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2422 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2424 /* Clear all queues and release memory */
2425 i40e_dev_clear_queues(dev);
2428 i40e_dev_set_link_down(dev);
2430 if (!rte_intr_allow_others(intr_handle))
2431 /* resume to the default handler */
2432 rte_intr_callback_register(intr_handle,
2433 i40e_dev_interrupt_handler,
2436 /* Clean datapath event and queue/vec mapping */
2437 rte_intr_efd_disable(intr_handle);
2438 if (intr_handle->intr_vec) {
2439 rte_free(intr_handle->intr_vec);
2440 intr_handle->intr_vec = NULL;
2443 /* reset hierarchy commit */
2444 pf->tm_conf.committed = false;
2446 hw->adapter_stopped = 1;
2450 i40e_dev_close(struct rte_eth_dev *dev)
2452 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2453 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2455 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2456 struct i40e_mirror_rule *p_mirror;
2461 PMD_INIT_FUNC_TRACE();
2465 /* Remove all mirror rules */
2466 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2467 ret = i40e_aq_del_mirror_rule(hw,
2468 pf->main_vsi->veb->seid,
2469 p_mirror->rule_type,
2471 p_mirror->num_entries,
2474 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2475 "status = %d, aq_err = %d.", ret,
2476 hw->aq.asq_last_status);
2478 /* remove mirror software resource anyway */
2479 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2481 pf->nb_mirror_rule--;
2484 i40e_dev_free_queues(dev);
2486 /* Disable interrupt */
2487 i40e_pf_disable_irq0(hw);
2488 rte_intr_disable(intr_handle);
2491 * Only legacy filter API needs the following fdir config. So when the
2492 * legacy filter API is deprecated, the following code should also be
2495 i40e_fdir_teardown(pf);
2497 /* shutdown and destroy the HMC */
2498 i40e_shutdown_lan_hmc(hw);
2500 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2501 i40e_vsi_release(pf->vmdq[i].vsi);
2502 pf->vmdq[i].vsi = NULL;
2507 /* release all the existing VSIs and VEBs */
2508 i40e_vsi_release(pf->main_vsi);
2510 /* shutdown the adminq */
2511 i40e_aq_queue_shutdown(hw, true);
2512 i40e_shutdown_adminq(hw);
2514 i40e_res_pool_destroy(&pf->qp_pool);
2515 i40e_res_pool_destroy(&pf->msix_pool);
2517 /* Disable flexible payload in global configuration */
2518 if (!pf->support_multi_driver)
2519 i40e_flex_payload_reg_set_default(hw);
2521 /* force a PF reset to clean anything leftover */
2522 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2523 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2524 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2525 I40E_WRITE_FLUSH(hw);
2529 * Reset PF device only to re-initialize resources in PMD layer
2532 i40e_dev_reset(struct rte_eth_dev *dev)
2536 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2537 * its VF to make them align with it. The detailed notification
2538 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2539 * To avoid unexpected behavior in VF, currently reset of PF with
2540 * SR-IOV activation is not supported. It might be supported later.
2542 if (dev->data->sriov.active)
2545 ret = eth_i40e_dev_uninit(dev);
2549 ret = eth_i40e_dev_init(dev, NULL);
2555 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559 struct i40e_vsi *vsi = pf->main_vsi;
2562 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2564 if (status != I40E_SUCCESS)
2565 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2567 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2569 if (status != I40E_SUCCESS)
2570 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2575 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2577 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2578 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579 struct i40e_vsi *vsi = pf->main_vsi;
2582 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2584 if (status != I40E_SUCCESS)
2585 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2587 /* must remain in all_multicast mode */
2588 if (dev->data->all_multicast == 1)
2591 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2593 if (status != I40E_SUCCESS)
2594 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2598 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2602 struct i40e_vsi *vsi = pf->main_vsi;
2605 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2606 if (ret != I40E_SUCCESS)
2607 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2611 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 struct i40e_vsi *vsi = pf->main_vsi;
2618 if (dev->data->promiscuous == 1)
2619 return; /* must remain in all_multicast mode */
2621 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2622 vsi->seid, FALSE, NULL);
2623 if (ret != I40E_SUCCESS)
2624 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2628 * Set device link up.
2631 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2633 /* re-apply link speed setting */
2634 return i40e_apply_link_speed(dev);
2638 * Set device link down.
2641 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2643 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2644 uint8_t abilities = 0;
2645 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2648 return i40e_phy_conf_link(hw, abilities, speed, false);
2651 static __rte_always_inline void
2652 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2654 /* Link status registers and values*/
2655 #define I40E_PRTMAC_LINKSTA 0x001E2420
2656 #define I40E_REG_LINK_UP 0x40000080
2657 #define I40E_PRTMAC_MACC 0x001E24E0
2658 #define I40E_REG_MACC_25GB 0x00020000
2659 #define I40E_REG_SPEED_MASK 0x38000000
2660 #define I40E_REG_SPEED_100MB 0x00000000
2661 #define I40E_REG_SPEED_1GB 0x08000000
2662 #define I40E_REG_SPEED_10GB 0x10000000
2663 #define I40E_REG_SPEED_20GB 0x20000000
2664 #define I40E_REG_SPEED_25_40GB 0x18000000
2665 uint32_t link_speed;
2668 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2669 link_speed = reg_val & I40E_REG_SPEED_MASK;
2670 reg_val &= I40E_REG_LINK_UP;
2671 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2673 if (unlikely(link->link_status == 0))
2676 /* Parse the link status */
2677 switch (link_speed) {
2678 case I40E_REG_SPEED_100MB:
2679 link->link_speed = ETH_SPEED_NUM_100M;
2681 case I40E_REG_SPEED_1GB:
2682 link->link_speed = ETH_SPEED_NUM_1G;
2684 case I40E_REG_SPEED_10GB:
2685 link->link_speed = ETH_SPEED_NUM_10G;
2687 case I40E_REG_SPEED_20GB:
2688 link->link_speed = ETH_SPEED_NUM_20G;
2690 case I40E_REG_SPEED_25_40GB:
2691 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2693 if (reg_val & I40E_REG_MACC_25GB)
2694 link->link_speed = ETH_SPEED_NUM_25G;
2696 link->link_speed = ETH_SPEED_NUM_40G;
2700 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2705 static __rte_always_inline void
2706 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2707 bool enable_lse, int wait_to_complete)
2709 #define CHECK_INTERVAL 100 /* 100ms */
2710 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2711 uint32_t rep_cnt = MAX_REPEAT_TIME;
2712 struct i40e_link_status link_status;
2715 memset(&link_status, 0, sizeof(link_status));
2718 memset(&link_status, 0, sizeof(link_status));
2720 /* Get link status information from hardware */
2721 status = i40e_aq_get_link_info(hw, enable_lse,
2722 &link_status, NULL);
2723 if (unlikely(status != I40E_SUCCESS)) {
2724 link->link_speed = ETH_SPEED_NUM_100M;
2725 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2726 PMD_DRV_LOG(ERR, "Failed to get link info");
2730 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2731 if (!wait_to_complete || link->link_status)
2734 rte_delay_ms(CHECK_INTERVAL);
2735 } while (--rep_cnt);
2737 /* Parse the link status */
2738 switch (link_status.link_speed) {
2739 case I40E_LINK_SPEED_100MB:
2740 link->link_speed = ETH_SPEED_NUM_100M;
2742 case I40E_LINK_SPEED_1GB:
2743 link->link_speed = ETH_SPEED_NUM_1G;
2745 case I40E_LINK_SPEED_10GB:
2746 link->link_speed = ETH_SPEED_NUM_10G;
2748 case I40E_LINK_SPEED_20GB:
2749 link->link_speed = ETH_SPEED_NUM_20G;
2751 case I40E_LINK_SPEED_25GB:
2752 link->link_speed = ETH_SPEED_NUM_25G;
2754 case I40E_LINK_SPEED_40GB:
2755 link->link_speed = ETH_SPEED_NUM_40G;
2758 link->link_speed = ETH_SPEED_NUM_100M;
2764 i40e_dev_link_update(struct rte_eth_dev *dev,
2765 int wait_to_complete)
2767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768 struct rte_eth_link link;
2769 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2772 memset(&link, 0, sizeof(link));
2774 /* i40e uses full duplex only */
2775 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2776 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2777 ETH_LINK_SPEED_FIXED);
2779 if (!wait_to_complete && !enable_lse)
2780 update_link_reg(hw, &link);
2782 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2784 ret = rte_eth_linkstatus_set(dev, &link);
2785 i40e_notify_all_vfs_link_status(dev);
2790 /* Get all the statistics of a VSI */
2792 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2794 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2795 struct i40e_eth_stats *nes = &vsi->eth_stats;
2796 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2797 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2799 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2800 vsi->offset_loaded, &oes->rx_bytes,
2802 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2803 vsi->offset_loaded, &oes->rx_unicast,
2805 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2806 vsi->offset_loaded, &oes->rx_multicast,
2807 &nes->rx_multicast);
2808 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2809 vsi->offset_loaded, &oes->rx_broadcast,
2810 &nes->rx_broadcast);
2811 /* exclude CRC bytes */
2812 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2813 nes->rx_broadcast) * ETHER_CRC_LEN;
2815 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2816 &oes->rx_discards, &nes->rx_discards);
2817 /* GLV_REPC not supported */
2818 /* GLV_RMPC not supported */
2819 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2820 &oes->rx_unknown_protocol,
2821 &nes->rx_unknown_protocol);
2822 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2823 vsi->offset_loaded, &oes->tx_bytes,
2825 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2826 vsi->offset_loaded, &oes->tx_unicast,
2828 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2829 vsi->offset_loaded, &oes->tx_multicast,
2830 &nes->tx_multicast);
2831 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2832 vsi->offset_loaded, &oes->tx_broadcast,
2833 &nes->tx_broadcast);
2834 /* GLV_TDPC not supported */
2835 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2836 &oes->tx_errors, &nes->tx_errors);
2837 vsi->offset_loaded = true;
2839 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2841 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2842 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2843 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2844 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2845 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2846 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2847 nes->rx_unknown_protocol);
2848 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2849 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2850 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2851 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2852 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2853 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2854 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2859 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2862 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2863 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2865 /* Get rx/tx bytes of internal transfer packets */
2866 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2867 I40E_GLV_GORCL(hw->port),
2869 &pf->internal_stats_offset.rx_bytes,
2870 &pf->internal_stats.rx_bytes);
2872 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2873 I40E_GLV_GOTCL(hw->port),
2875 &pf->internal_stats_offset.tx_bytes,
2876 &pf->internal_stats.tx_bytes);
2877 /* Get total internal rx packet count */
2878 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2879 I40E_GLV_UPRCL(hw->port),
2881 &pf->internal_stats_offset.rx_unicast,
2882 &pf->internal_stats.rx_unicast);
2883 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2884 I40E_GLV_MPRCL(hw->port),
2886 &pf->internal_stats_offset.rx_multicast,
2887 &pf->internal_stats.rx_multicast);
2888 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2889 I40E_GLV_BPRCL(hw->port),
2891 &pf->internal_stats_offset.rx_broadcast,
2892 &pf->internal_stats.rx_broadcast);
2893 /* Get total internal tx packet count */
2894 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2895 I40E_GLV_UPTCL(hw->port),
2897 &pf->internal_stats_offset.tx_unicast,
2898 &pf->internal_stats.tx_unicast);
2899 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2900 I40E_GLV_MPTCL(hw->port),
2902 &pf->internal_stats_offset.tx_multicast,
2903 &pf->internal_stats.tx_multicast);
2904 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2905 I40E_GLV_BPTCL(hw->port),
2907 &pf->internal_stats_offset.tx_broadcast,
2908 &pf->internal_stats.tx_broadcast);
2910 /* exclude CRC size */
2911 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2912 pf->internal_stats.rx_multicast +
2913 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2915 /* Get statistics of struct i40e_eth_stats */
2916 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2917 I40E_GLPRT_GORCL(hw->port),
2918 pf->offset_loaded, &os->eth.rx_bytes,
2920 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2921 I40E_GLPRT_UPRCL(hw->port),
2922 pf->offset_loaded, &os->eth.rx_unicast,
2923 &ns->eth.rx_unicast);
2924 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2925 I40E_GLPRT_MPRCL(hw->port),
2926 pf->offset_loaded, &os->eth.rx_multicast,
2927 &ns->eth.rx_multicast);
2928 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2929 I40E_GLPRT_BPRCL(hw->port),
2930 pf->offset_loaded, &os->eth.rx_broadcast,
2931 &ns->eth.rx_broadcast);
2932 /* Workaround: CRC size should not be included in byte statistics,
2933 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2935 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2936 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2938 /* exclude internal rx bytes
2939 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2940 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2942 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2944 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2945 ns->eth.rx_bytes = 0;
2947 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2949 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2950 ns->eth.rx_unicast = 0;
2952 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2954 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2955 ns->eth.rx_multicast = 0;
2957 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2959 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2960 ns->eth.rx_broadcast = 0;
2962 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2964 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2965 pf->offset_loaded, &os->eth.rx_discards,
2966 &ns->eth.rx_discards);
2967 /* GLPRT_REPC not supported */
2968 /* GLPRT_RMPC not supported */
2969 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2971 &os->eth.rx_unknown_protocol,
2972 &ns->eth.rx_unknown_protocol);
2973 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2974 I40E_GLPRT_GOTCL(hw->port),
2975 pf->offset_loaded, &os->eth.tx_bytes,
2977 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2978 I40E_GLPRT_UPTCL(hw->port),
2979 pf->offset_loaded, &os->eth.tx_unicast,
2980 &ns->eth.tx_unicast);
2981 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2982 I40E_GLPRT_MPTCL(hw->port),
2983 pf->offset_loaded, &os->eth.tx_multicast,
2984 &ns->eth.tx_multicast);
2985 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2986 I40E_GLPRT_BPTCL(hw->port),
2987 pf->offset_loaded, &os->eth.tx_broadcast,
2988 &ns->eth.tx_broadcast);
2989 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2990 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2992 /* exclude internal tx bytes
2993 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2994 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2996 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2998 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2999 ns->eth.tx_bytes = 0;
3001 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3003 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3004 ns->eth.tx_unicast = 0;
3006 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3008 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3009 ns->eth.tx_multicast = 0;
3011 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3013 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3014 ns->eth.tx_broadcast = 0;
3016 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3018 /* GLPRT_TEPC not supported */
3020 /* additional port specific stats */
3021 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3022 pf->offset_loaded, &os->tx_dropped_link_down,
3023 &ns->tx_dropped_link_down);
3024 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3025 pf->offset_loaded, &os->crc_errors,
3027 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3028 pf->offset_loaded, &os->illegal_bytes,
3029 &ns->illegal_bytes);
3030 /* GLPRT_ERRBC not supported */
3031 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3032 pf->offset_loaded, &os->mac_local_faults,
3033 &ns->mac_local_faults);
3034 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3035 pf->offset_loaded, &os->mac_remote_faults,
3036 &ns->mac_remote_faults);
3037 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3038 pf->offset_loaded, &os->rx_length_errors,
3039 &ns->rx_length_errors);
3040 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3041 pf->offset_loaded, &os->link_xon_rx,
3043 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3044 pf->offset_loaded, &os->link_xoff_rx,
3046 for (i = 0; i < 8; i++) {
3047 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3049 &os->priority_xon_rx[i],
3050 &ns->priority_xon_rx[i]);
3051 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3053 &os->priority_xoff_rx[i],
3054 &ns->priority_xoff_rx[i]);
3056 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3057 pf->offset_loaded, &os->link_xon_tx,
3059 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3060 pf->offset_loaded, &os->link_xoff_tx,
3062 for (i = 0; i < 8; i++) {
3063 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3065 &os->priority_xon_tx[i],
3066 &ns->priority_xon_tx[i]);
3067 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3069 &os->priority_xoff_tx[i],
3070 &ns->priority_xoff_tx[i]);
3071 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3073 &os->priority_xon_2_xoff[i],
3074 &ns->priority_xon_2_xoff[i]);
3076 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3077 I40E_GLPRT_PRC64L(hw->port),
3078 pf->offset_loaded, &os->rx_size_64,
3080 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3081 I40E_GLPRT_PRC127L(hw->port),
3082 pf->offset_loaded, &os->rx_size_127,
3084 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3085 I40E_GLPRT_PRC255L(hw->port),
3086 pf->offset_loaded, &os->rx_size_255,
3088 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3089 I40E_GLPRT_PRC511L(hw->port),
3090 pf->offset_loaded, &os->rx_size_511,
3092 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3093 I40E_GLPRT_PRC1023L(hw->port),
3094 pf->offset_loaded, &os->rx_size_1023,
3096 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3097 I40E_GLPRT_PRC1522L(hw->port),
3098 pf->offset_loaded, &os->rx_size_1522,
3100 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3101 I40E_GLPRT_PRC9522L(hw->port),
3102 pf->offset_loaded, &os->rx_size_big,
3104 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3105 pf->offset_loaded, &os->rx_undersize,
3107 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3108 pf->offset_loaded, &os->rx_fragments,
3110 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3111 pf->offset_loaded, &os->rx_oversize,
3113 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3114 pf->offset_loaded, &os->rx_jabber,
3116 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3117 I40E_GLPRT_PTC64L(hw->port),
3118 pf->offset_loaded, &os->tx_size_64,
3120 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3121 I40E_GLPRT_PTC127L(hw->port),
3122 pf->offset_loaded, &os->tx_size_127,
3124 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3125 I40E_GLPRT_PTC255L(hw->port),
3126 pf->offset_loaded, &os->tx_size_255,
3128 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3129 I40E_GLPRT_PTC511L(hw->port),
3130 pf->offset_loaded, &os->tx_size_511,
3132 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3133 I40E_GLPRT_PTC1023L(hw->port),
3134 pf->offset_loaded, &os->tx_size_1023,
3136 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3137 I40E_GLPRT_PTC1522L(hw->port),
3138 pf->offset_loaded, &os->tx_size_1522,
3140 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3141 I40E_GLPRT_PTC9522L(hw->port),
3142 pf->offset_loaded, &os->tx_size_big,
3144 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3146 &os->fd_sb_match, &ns->fd_sb_match);
3147 /* GLPRT_MSPDC not supported */
3148 /* GLPRT_XEC not supported */
3150 pf->offset_loaded = true;
3153 i40e_update_vsi_stats(pf->main_vsi);
3156 /* Get all statistics of a port */
3158 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3160 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3161 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3165 /* call read registers - updates values, now write them to struct */
3166 i40e_read_stats_registers(pf, hw);
3168 stats->ipackets = ns->eth.rx_unicast +
3169 ns->eth.rx_multicast +
3170 ns->eth.rx_broadcast -
3171 ns->eth.rx_discards -
3172 pf->main_vsi->eth_stats.rx_discards;
3173 stats->opackets = ns->eth.tx_unicast +
3174 ns->eth.tx_multicast +
3175 ns->eth.tx_broadcast;
3176 stats->ibytes = ns->eth.rx_bytes;
3177 stats->obytes = ns->eth.tx_bytes;
3178 stats->oerrors = ns->eth.tx_errors +
3179 pf->main_vsi->eth_stats.tx_errors;
3182 stats->imissed = ns->eth.rx_discards +
3183 pf->main_vsi->eth_stats.rx_discards;
3184 stats->ierrors = ns->crc_errors +
3185 ns->rx_length_errors + ns->rx_undersize +
3186 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3188 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3189 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3190 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3191 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3192 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3193 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3194 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3195 ns->eth.rx_unknown_protocol);
3196 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3197 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3198 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3199 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3200 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3201 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3203 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3204 ns->tx_dropped_link_down);
3205 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3206 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3208 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3209 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3210 ns->mac_local_faults);
3211 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3212 ns->mac_remote_faults);
3213 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3214 ns->rx_length_errors);
3215 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3216 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3217 for (i = 0; i < 8; i++) {
3218 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3219 i, ns->priority_xon_rx[i]);
3220 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3221 i, ns->priority_xoff_rx[i]);
3223 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3224 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3225 for (i = 0; i < 8; i++) {
3226 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3227 i, ns->priority_xon_tx[i]);
3228 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3229 i, ns->priority_xoff_tx[i]);
3230 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3231 i, ns->priority_xon_2_xoff[i]);
3233 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3234 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3235 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3236 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3237 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3238 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3239 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3240 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3241 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3242 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3243 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3244 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3245 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3246 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3247 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3248 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3249 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3250 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3251 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3252 ns->mac_short_packet_dropped);
3253 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3254 ns->checksum_error);
3255 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3256 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3260 /* Reset the statistics */
3262 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3264 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3265 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3267 /* Mark PF and VSI stats to update the offset, aka "reset" */
3268 pf->offset_loaded = false;
3270 pf->main_vsi->offset_loaded = false;
3272 /* read the stats, reading current register values into offset */
3273 i40e_read_stats_registers(pf, hw);
3277 i40e_xstats_calc_num(void)
3279 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3280 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3281 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3284 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3285 struct rte_eth_xstat_name *xstats_names,
3286 __rte_unused unsigned limit)
3291 if (xstats_names == NULL)
3292 return i40e_xstats_calc_num();
3294 /* Note: limit checked in rte_eth_xstats_names() */
3296 /* Get stats from i40e_eth_stats struct */
3297 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3298 snprintf(xstats_names[count].name,
3299 sizeof(xstats_names[count].name),
3300 "%s", rte_i40e_stats_strings[i].name);
3304 /* Get individiual stats from i40e_hw_port struct */
3305 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3306 snprintf(xstats_names[count].name,
3307 sizeof(xstats_names[count].name),
3308 "%s", rte_i40e_hw_port_strings[i].name);
3312 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3313 for (prio = 0; prio < 8; prio++) {
3314 snprintf(xstats_names[count].name,
3315 sizeof(xstats_names[count].name),
3316 "rx_priority%u_%s", prio,
3317 rte_i40e_rxq_prio_strings[i].name);
3322 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3323 for (prio = 0; prio < 8; prio++) {
3324 snprintf(xstats_names[count].name,
3325 sizeof(xstats_names[count].name),
3326 "tx_priority%u_%s", prio,
3327 rte_i40e_txq_prio_strings[i].name);
3335 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3338 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340 unsigned i, count, prio;
3341 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3343 count = i40e_xstats_calc_num();
3347 i40e_read_stats_registers(pf, hw);
3354 /* Get stats from i40e_eth_stats struct */
3355 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3356 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3357 rte_i40e_stats_strings[i].offset);
3358 xstats[count].id = count;
3362 /* Get individiual stats from i40e_hw_port struct */
3363 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3364 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3365 rte_i40e_hw_port_strings[i].offset);
3366 xstats[count].id = count;
3370 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3371 for (prio = 0; prio < 8; prio++) {
3372 xstats[count].value =
3373 *(uint64_t *)(((char *)hw_stats) +
3374 rte_i40e_rxq_prio_strings[i].offset +
3375 (sizeof(uint64_t) * prio));
3376 xstats[count].id = count;
3381 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3382 for (prio = 0; prio < 8; prio++) {
3383 xstats[count].value =
3384 *(uint64_t *)(((char *)hw_stats) +
3385 rte_i40e_txq_prio_strings[i].offset +
3386 (sizeof(uint64_t) * prio));
3387 xstats[count].id = count;
3396 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3397 __rte_unused uint16_t queue_id,
3398 __rte_unused uint8_t stat_idx,
3399 __rte_unused uint8_t is_rx)
3401 PMD_INIT_FUNC_TRACE();
3407 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3409 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415 full_ver = hw->nvm.oem_ver;
3416 ver = (u8)(full_ver >> 24);
3417 build = (u16)((full_ver >> 8) & 0xffff);
3418 patch = (u8)(full_ver & 0xff);
3420 ret = snprintf(fw_version, fw_size,
3421 "%d.%d%d 0x%08x %d.%d.%d",
3422 ((hw->nvm.version >> 12) & 0xf),
3423 ((hw->nvm.version >> 4) & 0xff),
3424 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3427 ret += 1; /* add the size of '\0' */
3428 if (fw_size < (u32)ret)
3435 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3437 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439 struct i40e_vsi *vsi = pf->main_vsi;
3440 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3442 dev_info->max_rx_queues = vsi->nb_qps;
3443 dev_info->max_tx_queues = vsi->nb_qps;
3444 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3445 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3446 dev_info->max_mac_addrs = vsi->max_macaddrs;
3447 dev_info->max_vfs = pci_dev->max_vfs;
3448 dev_info->rx_queue_offload_capa = 0;
3449 dev_info->rx_offload_capa =
3450 DEV_RX_OFFLOAD_VLAN_STRIP |
3451 DEV_RX_OFFLOAD_QINQ_STRIP |
3452 DEV_RX_OFFLOAD_IPV4_CKSUM |
3453 DEV_RX_OFFLOAD_UDP_CKSUM |
3454 DEV_RX_OFFLOAD_TCP_CKSUM |
3455 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3456 DEV_RX_OFFLOAD_KEEP_CRC |
3457 DEV_RX_OFFLOAD_SCATTER |
3458 DEV_RX_OFFLOAD_VLAN_EXTEND |
3459 DEV_RX_OFFLOAD_VLAN_FILTER |
3460 DEV_RX_OFFLOAD_JUMBO_FRAME;
3462 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3463 dev_info->tx_offload_capa =
3464 DEV_TX_OFFLOAD_VLAN_INSERT |
3465 DEV_TX_OFFLOAD_QINQ_INSERT |
3466 DEV_TX_OFFLOAD_IPV4_CKSUM |
3467 DEV_TX_OFFLOAD_UDP_CKSUM |
3468 DEV_TX_OFFLOAD_TCP_CKSUM |
3469 DEV_TX_OFFLOAD_SCTP_CKSUM |
3470 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3471 DEV_TX_OFFLOAD_TCP_TSO |
3472 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3473 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3474 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3475 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3476 DEV_TX_OFFLOAD_MULTI_SEGS |
3477 dev_info->tx_queue_offload_capa;
3478 dev_info->dev_capa =
3479 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3480 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3482 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3484 dev_info->reta_size = pf->hash_lut_size;
3485 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3487 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3489 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3490 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3491 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3493 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3498 dev_info->default_txconf = (struct rte_eth_txconf) {
3500 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3501 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3502 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3504 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3505 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3509 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3510 .nb_max = I40E_MAX_RING_DESC,
3511 .nb_min = I40E_MIN_RING_DESC,
3512 .nb_align = I40E_ALIGN_RING_DESC,
3515 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3516 .nb_max = I40E_MAX_RING_DESC,
3517 .nb_min = I40E_MIN_RING_DESC,
3518 .nb_align = I40E_ALIGN_RING_DESC,
3519 .nb_seg_max = I40E_TX_MAX_SEG,
3520 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3523 if (pf->flags & I40E_FLAG_VMDQ) {
3524 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3525 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3526 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3527 pf->max_nb_vmdq_vsi;
3528 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3529 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3530 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3533 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3535 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3536 dev_info->default_rxportconf.nb_queues = 2;
3537 dev_info->default_txportconf.nb_queues = 2;
3538 if (dev->data->nb_rx_queues == 1)
3539 dev_info->default_rxportconf.ring_size = 2048;
3541 dev_info->default_rxportconf.ring_size = 1024;
3542 if (dev->data->nb_tx_queues == 1)
3543 dev_info->default_txportconf.ring_size = 1024;
3545 dev_info->default_txportconf.ring_size = 512;
3547 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3549 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3550 dev_info->default_rxportconf.nb_queues = 1;
3551 dev_info->default_txportconf.nb_queues = 1;
3552 dev_info->default_rxportconf.ring_size = 256;
3553 dev_info->default_txportconf.ring_size = 256;
3556 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3557 dev_info->default_rxportconf.nb_queues = 1;
3558 dev_info->default_txportconf.nb_queues = 1;
3559 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3560 dev_info->default_rxportconf.ring_size = 512;
3561 dev_info->default_txportconf.ring_size = 256;
3563 dev_info->default_rxportconf.ring_size = 256;
3564 dev_info->default_txportconf.ring_size = 256;
3567 dev_info->default_rxportconf.burst_size = 32;
3568 dev_info->default_txportconf.burst_size = 32;
3572 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3575 struct i40e_vsi *vsi = pf->main_vsi;
3576 PMD_INIT_FUNC_TRACE();
3579 return i40e_vsi_add_vlan(vsi, vlan_id);
3581 return i40e_vsi_delete_vlan(vsi, vlan_id);
3585 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3586 enum rte_vlan_type vlan_type,
3587 uint16_t tpid, int qinq)
3589 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592 uint16_t reg_id = 3;
3596 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3600 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3602 if (ret != I40E_SUCCESS) {
3604 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3609 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3612 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3613 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3614 if (reg_r == reg_w) {
3615 PMD_DRV_LOG(DEBUG, "No need to write");
3619 ret = i40e_aq_debug_write_global_register(hw,
3620 I40E_GL_SWT_L2TAGCTRL(reg_id),
3622 if (ret != I40E_SUCCESS) {
3624 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3629 "Global register 0x%08x is changed with value 0x%08x",
3630 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3636 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3637 enum rte_vlan_type vlan_type,
3640 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3642 int qinq = dev->data->dev_conf.rxmode.offloads &
3643 DEV_RX_OFFLOAD_VLAN_EXTEND;
3646 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3647 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3648 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3650 "Unsupported vlan type.");
3654 if (pf->support_multi_driver) {
3655 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3659 /* 802.1ad frames ability is added in NVM API 1.7*/
3660 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3662 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3663 hw->first_tag = rte_cpu_to_le_16(tpid);
3664 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3665 hw->second_tag = rte_cpu_to_le_16(tpid);
3667 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3668 hw->second_tag = rte_cpu_to_le_16(tpid);
3670 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3671 if (ret != I40E_SUCCESS) {
3673 "Set switch config failed aq_err: %d",
3674 hw->aq.asq_last_status);
3678 /* If NVM API < 1.7, keep the register setting */
3679 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3686 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3688 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3689 struct i40e_vsi *vsi = pf->main_vsi;
3690 struct rte_eth_rxmode *rxmode;
3692 rxmode = &dev->data->dev_conf.rxmode;
3693 if (mask & ETH_VLAN_FILTER_MASK) {
3694 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3695 i40e_vsi_config_vlan_filter(vsi, TRUE);
3697 i40e_vsi_config_vlan_filter(vsi, FALSE);
3700 if (mask & ETH_VLAN_STRIP_MASK) {
3701 /* Enable or disable VLAN stripping */
3702 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3703 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3705 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3708 if (mask & ETH_VLAN_EXTEND_MASK) {
3709 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3710 i40e_vsi_config_double_vlan(vsi, TRUE);
3711 /* Set global registers with default ethertype. */
3712 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3714 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3718 i40e_vsi_config_double_vlan(vsi, FALSE);
3725 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3726 __rte_unused uint16_t queue,
3727 __rte_unused int on)
3729 PMD_INIT_FUNC_TRACE();
3733 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3735 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3736 struct i40e_vsi *vsi = pf->main_vsi;
3737 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3738 struct i40e_vsi_vlan_pvid_info info;
3740 memset(&info, 0, sizeof(info));
3743 info.config.pvid = pvid;
3745 info.config.reject.tagged =
3746 data->dev_conf.txmode.hw_vlan_reject_tagged;
3747 info.config.reject.untagged =
3748 data->dev_conf.txmode.hw_vlan_reject_untagged;
3751 return i40e_vsi_vlan_pvid_set(vsi, &info);
3755 i40e_dev_led_on(struct rte_eth_dev *dev)
3757 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758 uint32_t mode = i40e_led_get(hw);
3761 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3767 i40e_dev_led_off(struct rte_eth_dev *dev)
3769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770 uint32_t mode = i40e_led_get(hw);
3773 i40e_led_set(hw, 0, false);
3779 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3784 fc_conf->pause_time = pf->fc_conf.pause_time;
3786 /* read out from register, in case they are modified by other port */
3787 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3788 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3789 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3790 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3792 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3793 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3795 /* Return current mode according to actual setting*/
3796 switch (hw->fc.current_mode) {
3798 fc_conf->mode = RTE_FC_FULL;
3800 case I40E_FC_TX_PAUSE:
3801 fc_conf->mode = RTE_FC_TX_PAUSE;
3803 case I40E_FC_RX_PAUSE:
3804 fc_conf->mode = RTE_FC_RX_PAUSE;
3808 fc_conf->mode = RTE_FC_NONE;
3815 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3817 uint32_t mflcn_reg, fctrl_reg, reg;
3818 uint32_t max_high_water;
3819 uint8_t i, aq_failure;
3823 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3824 [RTE_FC_NONE] = I40E_FC_NONE,
3825 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3826 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3827 [RTE_FC_FULL] = I40E_FC_FULL
3830 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3832 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3833 if ((fc_conf->high_water > max_high_water) ||
3834 (fc_conf->high_water < fc_conf->low_water)) {
3836 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3841 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3843 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3845 pf->fc_conf.pause_time = fc_conf->pause_time;
3846 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3847 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3849 PMD_INIT_FUNC_TRACE();
3851 /* All the link flow control related enable/disable register
3852 * configuration is handle by the F/W
3854 err = i40e_set_fc(hw, &aq_failure, true);
3858 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3859 /* Configure flow control refresh threshold,
3860 * the value for stat_tx_pause_refresh_timer[8]
3861 * is used for global pause operation.
3865 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3866 pf->fc_conf.pause_time);
3868 /* configure the timer value included in transmitted pause
3870 * the value for stat_tx_pause_quanta[8] is used for global
3873 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3874 pf->fc_conf.pause_time);
3876 fctrl_reg = I40E_READ_REG(hw,
3877 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3879 if (fc_conf->mac_ctrl_frame_fwd != 0)
3880 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3882 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3884 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3887 /* Configure pause time (2 TCs per register) */
3888 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3889 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3890 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3892 /* Configure flow control refresh threshold value */
3893 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3894 pf->fc_conf.pause_time / 2);
3896 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3898 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3899 *depending on configuration
3901 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3902 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3903 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3905 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3906 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3909 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3912 if (!pf->support_multi_driver) {
3913 /* config water marker both based on the packets and bytes */
3914 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3915 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3916 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3917 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3918 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3919 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3920 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3921 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3923 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3924 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3928 "Water marker configuration is not supported.");
3931 I40E_WRITE_FLUSH(hw);
3937 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3938 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3940 PMD_INIT_FUNC_TRACE();
3945 /* Add a MAC address, and update filters */
3947 i40e_macaddr_add(struct rte_eth_dev *dev,
3948 struct ether_addr *mac_addr,
3949 __rte_unused uint32_t index,
3952 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3953 struct i40e_mac_filter_info mac_filter;
3954 struct i40e_vsi *vsi;
3955 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3958 /* If VMDQ not enabled or configured, return */
3959 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3960 !pf->nb_cfg_vmdq_vsi)) {
3961 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3962 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3967 if (pool > pf->nb_cfg_vmdq_vsi) {
3968 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3969 pool, pf->nb_cfg_vmdq_vsi);
3973 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3974 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3975 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3977 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3982 vsi = pf->vmdq[pool - 1].vsi;
3984 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3985 if (ret != I40E_SUCCESS) {
3986 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3992 /* Remove a MAC address, and update filters */
3994 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3997 struct i40e_vsi *vsi;
3998 struct rte_eth_dev_data *data = dev->data;
3999 struct ether_addr *macaddr;
4004 macaddr = &(data->mac_addrs[index]);
4006 pool_sel = dev->data->mac_pool_sel[index];
4008 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4009 if (pool_sel & (1ULL << i)) {
4013 /* No VMDQ pool enabled or configured */
4014 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4015 (i > pf->nb_cfg_vmdq_vsi)) {
4017 "No VMDQ pool enabled/configured");
4020 vsi = pf->vmdq[i - 1].vsi;
4022 ret = i40e_vsi_delete_mac(vsi, macaddr);
4025 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4032 /* Set perfect match or hash match of MAC and VLAN for a VF */
4034 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4035 struct rte_eth_mac_filter *filter,
4039 struct i40e_mac_filter_info mac_filter;
4040 struct ether_addr old_mac;
4041 struct ether_addr *new_mac;
4042 struct i40e_pf_vf *vf = NULL;
4047 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4050 hw = I40E_PF_TO_HW(pf);
4052 if (filter == NULL) {
4053 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4057 new_mac = &filter->mac_addr;
4059 if (is_zero_ether_addr(new_mac)) {
4060 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4064 vf_id = filter->dst_id;
4066 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4067 PMD_DRV_LOG(ERR, "Invalid argument.");
4070 vf = &pf->vfs[vf_id];
4072 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4073 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4078 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4079 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4081 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4084 mac_filter.filter_type = filter->filter_type;
4085 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4086 if (ret != I40E_SUCCESS) {
4087 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4090 ether_addr_copy(new_mac, &pf->dev_addr);
4092 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4094 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4095 if (ret != I40E_SUCCESS) {
4096 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4100 /* Clear device address as it has been removed */
4101 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4102 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4108 /* MAC filter handle */
4110 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4113 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4114 struct rte_eth_mac_filter *filter;
4115 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4116 int ret = I40E_NOT_SUPPORTED;
4118 filter = (struct rte_eth_mac_filter *)(arg);
4120 switch (filter_op) {
4121 case RTE_ETH_FILTER_NOP:
4124 case RTE_ETH_FILTER_ADD:
4125 i40e_pf_disable_irq0(hw);
4127 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4128 i40e_pf_enable_irq0(hw);
4130 case RTE_ETH_FILTER_DELETE:
4131 i40e_pf_disable_irq0(hw);
4133 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4134 i40e_pf_enable_irq0(hw);
4137 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4138 ret = I40E_ERR_PARAM;
4146 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4148 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4149 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4156 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4157 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4160 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4164 uint32_t *lut_dw = (uint32_t *)lut;
4165 uint16_t i, lut_size_dw = lut_size / 4;
4167 if (vsi->type == I40E_VSI_SRIOV) {
4168 for (i = 0; i <= lut_size_dw; i++) {
4169 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4170 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4173 for (i = 0; i < lut_size_dw; i++)
4174 lut_dw[i] = I40E_READ_REG(hw,
4183 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4192 pf = I40E_VSI_TO_PF(vsi);
4193 hw = I40E_VSI_TO_HW(vsi);
4195 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4196 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4199 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4203 uint32_t *lut_dw = (uint32_t *)lut;
4204 uint16_t i, lut_size_dw = lut_size / 4;
4206 if (vsi->type == I40E_VSI_SRIOV) {
4207 for (i = 0; i < lut_size_dw; i++)
4210 I40E_VFQF_HLUT1(i, vsi->user_param),
4213 for (i = 0; i < lut_size_dw; i++)
4214 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4217 I40E_WRITE_FLUSH(hw);
4224 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4225 struct rte_eth_rss_reta_entry64 *reta_conf,
4228 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4229 uint16_t i, lut_size = pf->hash_lut_size;
4230 uint16_t idx, shift;
4234 if (reta_size != lut_size ||
4235 reta_size > ETH_RSS_RETA_SIZE_512) {
4237 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4238 reta_size, lut_size);
4242 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4244 PMD_DRV_LOG(ERR, "No memory can be allocated");
4247 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4250 for (i = 0; i < reta_size; i++) {
4251 idx = i / RTE_RETA_GROUP_SIZE;
4252 shift = i % RTE_RETA_GROUP_SIZE;
4253 if (reta_conf[idx].mask & (1ULL << shift))
4254 lut[i] = reta_conf[idx].reta[shift];
4256 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4265 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4266 struct rte_eth_rss_reta_entry64 *reta_conf,
4269 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4270 uint16_t i, lut_size = pf->hash_lut_size;
4271 uint16_t idx, shift;
4275 if (reta_size != lut_size ||
4276 reta_size > ETH_RSS_RETA_SIZE_512) {
4278 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4279 reta_size, lut_size);
4283 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4285 PMD_DRV_LOG(ERR, "No memory can be allocated");
4289 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4292 for (i = 0; i < reta_size; i++) {
4293 idx = i / RTE_RETA_GROUP_SIZE;
4294 shift = i % RTE_RETA_GROUP_SIZE;
4295 if (reta_conf[idx].mask & (1ULL << shift))
4296 reta_conf[idx].reta[shift] = lut[i];
4306 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4307 * @hw: pointer to the HW structure
4308 * @mem: pointer to mem struct to fill out
4309 * @size: size of memory requested
4310 * @alignment: what to align the allocation to
4312 enum i40e_status_code
4313 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4314 struct i40e_dma_mem *mem,
4318 const struct rte_memzone *mz = NULL;
4319 char z_name[RTE_MEMZONE_NAMESIZE];
4322 return I40E_ERR_PARAM;
4324 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4325 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4326 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4328 return I40E_ERR_NO_MEMORY;
4333 mem->zone = (const void *)mz;
4335 "memzone %s allocated with physical address: %"PRIu64,
4338 return I40E_SUCCESS;
4342 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4343 * @hw: pointer to the HW structure
4344 * @mem: ptr to mem struct to free
4346 enum i40e_status_code
4347 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4348 struct i40e_dma_mem *mem)
4351 return I40E_ERR_PARAM;
4354 "memzone %s to be freed with physical address: %"PRIu64,
4355 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4356 rte_memzone_free((const struct rte_memzone *)mem->zone);
4361 return I40E_SUCCESS;
4365 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4366 * @hw: pointer to the HW structure
4367 * @mem: pointer to mem struct to fill out
4368 * @size: size of memory requested
4370 enum i40e_status_code
4371 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4372 struct i40e_virt_mem *mem,
4376 return I40E_ERR_PARAM;
4379 mem->va = rte_zmalloc("i40e", size, 0);
4382 return I40E_SUCCESS;
4384 return I40E_ERR_NO_MEMORY;
4388 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4389 * @hw: pointer to the HW structure
4390 * @mem: pointer to mem struct to free
4392 enum i40e_status_code
4393 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4394 struct i40e_virt_mem *mem)
4397 return I40E_ERR_PARAM;
4402 return I40E_SUCCESS;
4406 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4408 rte_spinlock_init(&sp->spinlock);
4412 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4414 rte_spinlock_lock(&sp->spinlock);
4418 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4420 rte_spinlock_unlock(&sp->spinlock);
4424 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4430 * Get the hardware capabilities, which will be parsed
4431 * and saved into struct i40e_hw.
4434 i40e_get_cap(struct i40e_hw *hw)
4436 struct i40e_aqc_list_capabilities_element_resp *buf;
4437 uint16_t len, size = 0;
4440 /* Calculate a huge enough buff for saving response data temporarily */
4441 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4442 I40E_MAX_CAP_ELE_NUM;
4443 buf = rte_zmalloc("i40e", len, 0);
4445 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4446 return I40E_ERR_NO_MEMORY;
4449 /* Get, parse the capabilities and save it to hw */
4450 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4451 i40e_aqc_opc_list_func_capabilities, NULL);
4452 if (ret != I40E_SUCCESS)
4453 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4455 /* Free the temporary buffer after being used */
4461 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4463 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4471 pf = (struct i40e_pf *)opaque;
4475 num = strtoul(value, &end, 0);
4476 if (errno != 0 || end == value || *end != 0) {
4477 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4478 "kept the value = %hu", value, pf->vf_nb_qp_max);
4482 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4483 pf->vf_nb_qp_max = (uint16_t)num;
4485 /* here return 0 to make next valid same argument work */
4486 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4487 "power of 2 and equal or less than 16 !, Now it is "
4488 "kept the value = %hu", num, pf->vf_nb_qp_max);
4493 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4495 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4496 struct rte_kvargs *kvlist;
4499 /* set default queue number per VF as 4 */
4500 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4502 if (dev->device->devargs == NULL)
4505 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4509 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4510 if (!kvargs_count) {
4511 rte_kvargs_free(kvlist);
4515 if (kvargs_count > 1)
4516 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4517 "the first invalid or last valid one is used !",
4518 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4520 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4521 i40e_pf_parse_vf_queue_number_handler, pf);
4523 rte_kvargs_free(kvlist);
4529 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4531 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4532 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4533 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4534 uint16_t qp_count = 0, vsi_count = 0;
4536 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4537 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4541 i40e_pf_config_vf_rxq_number(dev);
4543 /* Add the parameter init for LFC */
4544 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4545 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4546 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4548 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4549 pf->max_num_vsi = hw->func_caps.num_vsis;
4550 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4551 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4553 /* FDir queue/VSI allocation */
4554 pf->fdir_qp_offset = 0;
4555 if (hw->func_caps.fd) {
4556 pf->flags |= I40E_FLAG_FDIR;
4557 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4559 pf->fdir_nb_qps = 0;
4561 qp_count += pf->fdir_nb_qps;
4564 /* LAN queue/VSI allocation */
4565 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4566 if (!hw->func_caps.rss) {
4569 pf->flags |= I40E_FLAG_RSS;
4570 if (hw->mac.type == I40E_MAC_X722)
4571 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4572 pf->lan_nb_qps = pf->lan_nb_qp_max;
4574 qp_count += pf->lan_nb_qps;
4577 /* VF queue/VSI allocation */
4578 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4579 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4580 pf->flags |= I40E_FLAG_SRIOV;
4581 pf->vf_nb_qps = pf->vf_nb_qp_max;
4582 pf->vf_num = pci_dev->max_vfs;
4584 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4585 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4590 qp_count += pf->vf_nb_qps * pf->vf_num;
4591 vsi_count += pf->vf_num;
4593 /* VMDq queue/VSI allocation */
4594 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4595 pf->vmdq_nb_qps = 0;
4596 pf->max_nb_vmdq_vsi = 0;
4597 if (hw->func_caps.vmdq) {
4598 if (qp_count < hw->func_caps.num_tx_qp &&
4599 vsi_count < hw->func_caps.num_vsis) {
4600 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4601 qp_count) / pf->vmdq_nb_qp_max;
4603 /* Limit the maximum number of VMDq vsi to the maximum
4604 * ethdev can support
4606 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4607 hw->func_caps.num_vsis - vsi_count);
4608 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4610 if (pf->max_nb_vmdq_vsi) {
4611 pf->flags |= I40E_FLAG_VMDQ;
4612 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4614 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4615 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4616 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4619 "No enough queues left for VMDq");
4622 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4625 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4626 vsi_count += pf->max_nb_vmdq_vsi;
4628 if (hw->func_caps.dcb)
4629 pf->flags |= I40E_FLAG_DCB;
4631 if (qp_count > hw->func_caps.num_tx_qp) {
4633 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4634 qp_count, hw->func_caps.num_tx_qp);
4637 if (vsi_count > hw->func_caps.num_vsis) {
4639 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4640 vsi_count, hw->func_caps.num_vsis);
4648 i40e_pf_get_switch_config(struct i40e_pf *pf)
4650 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4651 struct i40e_aqc_get_switch_config_resp *switch_config;
4652 struct i40e_aqc_switch_config_element_resp *element;
4653 uint16_t start_seid = 0, num_reported;
4656 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4657 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4658 if (!switch_config) {
4659 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4663 /* Get the switch configurations */
4664 ret = i40e_aq_get_switch_config(hw, switch_config,
4665 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4666 if (ret != I40E_SUCCESS) {
4667 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4670 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4671 if (num_reported != 1) { /* The number should be 1 */
4672 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4676 /* Parse the switch configuration elements */
4677 element = &(switch_config->element[0]);
4678 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4679 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4680 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4682 PMD_DRV_LOG(INFO, "Unknown element type");
4685 rte_free(switch_config);
4691 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4694 struct pool_entry *entry;
4696 if (pool == NULL || num == 0)
4699 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4700 if (entry == NULL) {
4701 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4705 /* queue heap initialize */
4706 pool->num_free = num;
4707 pool->num_alloc = 0;
4709 LIST_INIT(&pool->alloc_list);
4710 LIST_INIT(&pool->free_list);
4712 /* Initialize element */
4716 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4721 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4723 struct pool_entry *entry, *next_entry;
4728 for (entry = LIST_FIRST(&pool->alloc_list);
4729 entry && (next_entry = LIST_NEXT(entry, next), 1);
4730 entry = next_entry) {
4731 LIST_REMOVE(entry, next);
4735 for (entry = LIST_FIRST(&pool->free_list);
4736 entry && (next_entry = LIST_NEXT(entry, next), 1);
4737 entry = next_entry) {
4738 LIST_REMOVE(entry, next);
4743 pool->num_alloc = 0;
4745 LIST_INIT(&pool->alloc_list);
4746 LIST_INIT(&pool->free_list);
4750 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4753 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4754 uint32_t pool_offset;
4758 PMD_DRV_LOG(ERR, "Invalid parameter");
4762 pool_offset = base - pool->base;
4763 /* Lookup in alloc list */
4764 LIST_FOREACH(entry, &pool->alloc_list, next) {
4765 if (entry->base == pool_offset) {
4766 valid_entry = entry;
4767 LIST_REMOVE(entry, next);
4772 /* Not find, return */
4773 if (valid_entry == NULL) {
4774 PMD_DRV_LOG(ERR, "Failed to find entry");
4779 * Found it, move it to free list and try to merge.
4780 * In order to make merge easier, always sort it by qbase.
4781 * Find adjacent prev and last entries.
4784 LIST_FOREACH(entry, &pool->free_list, next) {
4785 if (entry->base > valid_entry->base) {
4793 /* Try to merge with next one*/
4795 /* Merge with next one */
4796 if (valid_entry->base + valid_entry->len == next->base) {
4797 next->base = valid_entry->base;
4798 next->len += valid_entry->len;
4799 rte_free(valid_entry);
4806 /* Merge with previous one */
4807 if (prev->base + prev->len == valid_entry->base) {
4808 prev->len += valid_entry->len;
4809 /* If it merge with next one, remove next node */
4811 LIST_REMOVE(valid_entry, next);
4812 rte_free(valid_entry);
4814 rte_free(valid_entry);
4820 /* Not find any entry to merge, insert */
4823 LIST_INSERT_AFTER(prev, valid_entry, next);
4824 else if (next != NULL)
4825 LIST_INSERT_BEFORE(next, valid_entry, next);
4826 else /* It's empty list, insert to head */
4827 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4830 pool->num_free += valid_entry->len;
4831 pool->num_alloc -= valid_entry->len;
4837 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4840 struct pool_entry *entry, *valid_entry;
4842 if (pool == NULL || num == 0) {
4843 PMD_DRV_LOG(ERR, "Invalid parameter");
4847 if (pool->num_free < num) {
4848 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4849 num, pool->num_free);
4854 /* Lookup in free list and find most fit one */
4855 LIST_FOREACH(entry, &pool->free_list, next) {
4856 if (entry->len >= num) {
4858 if (entry->len == num) {
4859 valid_entry = entry;
4862 if (valid_entry == NULL || valid_entry->len > entry->len)
4863 valid_entry = entry;
4867 /* Not find one to satisfy the request, return */
4868 if (valid_entry == NULL) {
4869 PMD_DRV_LOG(ERR, "No valid entry found");
4873 * The entry have equal queue number as requested,
4874 * remove it from alloc_list.
4876 if (valid_entry->len == num) {
4877 LIST_REMOVE(valid_entry, next);
4880 * The entry have more numbers than requested,
4881 * create a new entry for alloc_list and minus its
4882 * queue base and number in free_list.
4884 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4885 if (entry == NULL) {
4887 "Failed to allocate memory for resource pool");
4890 entry->base = valid_entry->base;
4892 valid_entry->base += num;
4893 valid_entry->len -= num;
4894 valid_entry = entry;
4897 /* Insert it into alloc list, not sorted */
4898 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4900 pool->num_free -= valid_entry->len;
4901 pool->num_alloc += valid_entry->len;
4903 return valid_entry->base + pool->base;
4907 * bitmap_is_subset - Check whether src2 is subset of src1
4910 bitmap_is_subset(uint8_t src1, uint8_t src2)
4912 return !((src1 ^ src2) & src2);
4915 static enum i40e_status_code
4916 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4918 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4920 /* If DCB is not supported, only default TC is supported */
4921 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4922 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4923 return I40E_NOT_SUPPORTED;
4926 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4928 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4929 hw->func_caps.enabled_tcmap, enabled_tcmap);
4930 return I40E_NOT_SUPPORTED;
4932 return I40E_SUCCESS;
4936 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4937 struct i40e_vsi_vlan_pvid_info *info)
4940 struct i40e_vsi_context ctxt;
4941 uint8_t vlan_flags = 0;
4944 if (vsi == NULL || info == NULL) {
4945 PMD_DRV_LOG(ERR, "invalid parameters");
4946 return I40E_ERR_PARAM;
4950 vsi->info.pvid = info->config.pvid;
4952 * If insert pvid is enabled, only tagged pkts are
4953 * allowed to be sent out.
4955 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4956 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4959 if (info->config.reject.tagged == 0)
4960 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4962 if (info->config.reject.untagged == 0)
4963 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4965 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4966 I40E_AQ_VSI_PVLAN_MODE_MASK);
4967 vsi->info.port_vlan_flags |= vlan_flags;
4968 vsi->info.valid_sections =
4969 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4970 memset(&ctxt, 0, sizeof(ctxt));
4971 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4972 ctxt.seid = vsi->seid;
4974 hw = I40E_VSI_TO_HW(vsi);
4975 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4976 if (ret != I40E_SUCCESS)
4977 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4983 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4985 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4987 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4989 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4990 if (ret != I40E_SUCCESS)
4994 PMD_DRV_LOG(ERR, "seid not valid");
4998 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4999 tc_bw_data.tc_valid_bits = enabled_tcmap;
5000 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5001 tc_bw_data.tc_bw_credits[i] =
5002 (enabled_tcmap & (1 << i)) ? 1 : 0;
5004 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5005 if (ret != I40E_SUCCESS) {
5006 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5010 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5011 sizeof(vsi->info.qs_handle));
5012 return I40E_SUCCESS;
5015 static enum i40e_status_code
5016 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5017 struct i40e_aqc_vsi_properties_data *info,
5018 uint8_t enabled_tcmap)
5020 enum i40e_status_code ret;
5021 int i, total_tc = 0;
5022 uint16_t qpnum_per_tc, bsf, qp_idx;
5024 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5025 if (ret != I40E_SUCCESS)
5028 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5029 if (enabled_tcmap & (1 << i))
5033 vsi->enabled_tc = enabled_tcmap;
5035 /* Number of queues per enabled TC */
5036 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5037 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5038 bsf = rte_bsf32(qpnum_per_tc);
5040 /* Adjust the queue number to actual queues that can be applied */
5041 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5042 vsi->nb_qps = qpnum_per_tc * total_tc;
5045 * Configure TC and queue mapping parameters, for enabled TC,
5046 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5047 * default queue will serve it.
5050 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5051 if (vsi->enabled_tc & (1 << i)) {
5052 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5053 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5054 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5055 qp_idx += qpnum_per_tc;
5057 info->tc_mapping[i] = 0;
5060 /* Associate queue number with VSI */
5061 if (vsi->type == I40E_VSI_SRIOV) {
5062 info->mapping_flags |=
5063 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5064 for (i = 0; i < vsi->nb_qps; i++)
5065 info->queue_mapping[i] =
5066 rte_cpu_to_le_16(vsi->base_queue + i);
5068 info->mapping_flags |=
5069 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5070 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5072 info->valid_sections |=
5073 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5075 return I40E_SUCCESS;
5079 i40e_veb_release(struct i40e_veb *veb)
5081 struct i40e_vsi *vsi;
5087 if (!TAILQ_EMPTY(&veb->head)) {
5088 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5091 /* associate_vsi field is NULL for floating VEB */
5092 if (veb->associate_vsi != NULL) {
5093 vsi = veb->associate_vsi;
5094 hw = I40E_VSI_TO_HW(vsi);
5096 vsi->uplink_seid = veb->uplink_seid;
5099 veb->associate_pf->main_vsi->floating_veb = NULL;
5100 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5103 i40e_aq_delete_element(hw, veb->seid, NULL);
5105 return I40E_SUCCESS;
5109 static struct i40e_veb *
5110 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5112 struct i40e_veb *veb;
5118 "veb setup failed, associated PF shouldn't null");
5121 hw = I40E_PF_TO_HW(pf);
5123 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5125 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5129 veb->associate_vsi = vsi;
5130 veb->associate_pf = pf;
5131 TAILQ_INIT(&veb->head);
5132 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5134 /* create floating veb if vsi is NULL */
5136 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5137 I40E_DEFAULT_TCMAP, false,
5138 &veb->seid, false, NULL);
5140 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5141 true, &veb->seid, false, NULL);
5144 if (ret != I40E_SUCCESS) {
5145 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5146 hw->aq.asq_last_status);
5149 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5151 /* get statistics index */
5152 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5153 &veb->stats_idx, NULL, NULL, NULL);
5154 if (ret != I40E_SUCCESS) {
5155 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5156 hw->aq.asq_last_status);
5159 /* Get VEB bandwidth, to be implemented */
5160 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5162 vsi->uplink_seid = veb->seid;
5171 i40e_vsi_release(struct i40e_vsi *vsi)
5175 struct i40e_vsi_list *vsi_list;
5178 struct i40e_mac_filter *f;
5179 uint16_t user_param;
5182 return I40E_SUCCESS;
5187 user_param = vsi->user_param;
5189 pf = I40E_VSI_TO_PF(vsi);
5190 hw = I40E_VSI_TO_HW(vsi);
5192 /* VSI has child to attach, release child first */
5194 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5195 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5198 i40e_veb_release(vsi->veb);
5201 if (vsi->floating_veb) {
5202 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5203 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5208 /* Remove all macvlan filters of the VSI */
5209 i40e_vsi_remove_all_macvlan_filter(vsi);
5210 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5213 if (vsi->type != I40E_VSI_MAIN &&
5214 ((vsi->type != I40E_VSI_SRIOV) ||
5215 !pf->floating_veb_list[user_param])) {
5216 /* Remove vsi from parent's sibling list */
5217 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5218 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5219 return I40E_ERR_PARAM;
5221 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5222 &vsi->sib_vsi_list, list);
5224 /* Remove all switch element of the VSI */
5225 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5226 if (ret != I40E_SUCCESS)
5227 PMD_DRV_LOG(ERR, "Failed to delete element");
5230 if ((vsi->type == I40E_VSI_SRIOV) &&
5231 pf->floating_veb_list[user_param]) {
5232 /* Remove vsi from parent's sibling list */
5233 if (vsi->parent_vsi == NULL ||
5234 vsi->parent_vsi->floating_veb == NULL) {
5235 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5236 return I40E_ERR_PARAM;
5238 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5239 &vsi->sib_vsi_list, list);
5241 /* Remove all switch element of the VSI */
5242 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5243 if (ret != I40E_SUCCESS)
5244 PMD_DRV_LOG(ERR, "Failed to delete element");
5247 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5249 if (vsi->type != I40E_VSI_SRIOV)
5250 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5253 return I40E_SUCCESS;
5257 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5259 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5260 struct i40e_aqc_remove_macvlan_element_data def_filter;
5261 struct i40e_mac_filter_info filter;
5264 if (vsi->type != I40E_VSI_MAIN)
5265 return I40E_ERR_CONFIG;
5266 memset(&def_filter, 0, sizeof(def_filter));
5267 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5269 def_filter.vlan_tag = 0;
5270 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5271 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5272 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5273 if (ret != I40E_SUCCESS) {
5274 struct i40e_mac_filter *f;
5275 struct ether_addr *mac;
5278 "Cannot remove the default macvlan filter");
5279 /* It needs to add the permanent mac into mac list */
5280 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5282 PMD_DRV_LOG(ERR, "failed to allocate memory");
5283 return I40E_ERR_NO_MEMORY;
5285 mac = &f->mac_info.mac_addr;
5286 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5288 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5289 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5294 rte_memcpy(&filter.mac_addr,
5295 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5296 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5297 return i40e_vsi_add_mac(vsi, &filter);
5301 * i40e_vsi_get_bw_config - Query VSI BW Information
5302 * @vsi: the VSI to be queried
5304 * Returns 0 on success, negative value on failure
5306 static enum i40e_status_code
5307 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5309 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5310 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5311 struct i40e_hw *hw = &vsi->adapter->hw;
5316 memset(&bw_config, 0, sizeof(bw_config));
5317 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5318 if (ret != I40E_SUCCESS) {
5319 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5320 hw->aq.asq_last_status);
5324 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5325 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5326 &ets_sla_config, NULL);
5327 if (ret != I40E_SUCCESS) {
5329 "VSI failed to get TC bandwdith configuration %u",
5330 hw->aq.asq_last_status);
5334 /* store and print out BW info */
5335 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5336 vsi->bw_info.bw_max = bw_config.max_bw;
5337 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5338 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5339 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5340 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5342 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5343 vsi->bw_info.bw_ets_share_credits[i] =
5344 ets_sla_config.share_credits[i];
5345 vsi->bw_info.bw_ets_credits[i] =
5346 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5347 /* 4 bits per TC, 4th bit is reserved */
5348 vsi->bw_info.bw_ets_max[i] =
5349 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5350 RTE_LEN2MASK(3, uint8_t));
5351 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5352 vsi->bw_info.bw_ets_share_credits[i]);
5353 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5354 vsi->bw_info.bw_ets_credits[i]);
5355 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5356 vsi->bw_info.bw_ets_max[i]);
5359 return I40E_SUCCESS;
5362 /* i40e_enable_pf_lb
5363 * @pf: pointer to the pf structure
5365 * allow loopback on pf
5368 i40e_enable_pf_lb(struct i40e_pf *pf)
5370 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5371 struct i40e_vsi_context ctxt;
5374 /* Use the FW API if FW >= v5.0 */
5375 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5376 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5380 memset(&ctxt, 0, sizeof(ctxt));
5381 ctxt.seid = pf->main_vsi_seid;
5382 ctxt.pf_num = hw->pf_id;
5383 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5385 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5386 ret, hw->aq.asq_last_status);
5389 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5390 ctxt.info.valid_sections =
5391 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5392 ctxt.info.switch_id |=
5393 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5395 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5397 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5398 hw->aq.asq_last_status);
5403 i40e_vsi_setup(struct i40e_pf *pf,
5404 enum i40e_vsi_type type,
5405 struct i40e_vsi *uplink_vsi,
5406 uint16_t user_param)
5408 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5409 struct i40e_vsi *vsi;
5410 struct i40e_mac_filter_info filter;
5412 struct i40e_vsi_context ctxt;
5413 struct ether_addr broadcast =
5414 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5416 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5417 uplink_vsi == NULL) {
5419 "VSI setup failed, VSI link shouldn't be NULL");
5423 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5425 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5430 * 1.type is not MAIN and uplink vsi is not NULL
5431 * If uplink vsi didn't setup VEB, create one first under veb field
5432 * 2.type is SRIOV and the uplink is NULL
5433 * If floating VEB is NULL, create one veb under floating veb field
5436 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5437 uplink_vsi->veb == NULL) {
5438 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5440 if (uplink_vsi->veb == NULL) {
5441 PMD_DRV_LOG(ERR, "VEB setup failed");
5444 /* set ALLOWLOOPBACk on pf, when veb is created */
5445 i40e_enable_pf_lb(pf);
5448 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5449 pf->main_vsi->floating_veb == NULL) {
5450 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5452 if (pf->main_vsi->floating_veb == NULL) {
5453 PMD_DRV_LOG(ERR, "VEB setup failed");
5458 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5460 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5463 TAILQ_INIT(&vsi->mac_list);
5465 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5466 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5467 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5468 vsi->user_param = user_param;
5469 vsi->vlan_anti_spoof_on = 0;
5470 vsi->vlan_filter_on = 0;
5471 /* Allocate queues */
5472 switch (vsi->type) {
5473 case I40E_VSI_MAIN :
5474 vsi->nb_qps = pf->lan_nb_qps;
5476 case I40E_VSI_SRIOV :
5477 vsi->nb_qps = pf->vf_nb_qps;
5479 case I40E_VSI_VMDQ2:
5480 vsi->nb_qps = pf->vmdq_nb_qps;
5483 vsi->nb_qps = pf->fdir_nb_qps;
5489 * The filter status descriptor is reported in rx queue 0,
5490 * while the tx queue for fdir filter programming has no
5491 * such constraints, can be non-zero queues.
5492 * To simplify it, choose FDIR vsi use queue 0 pair.
5493 * To make sure it will use queue 0 pair, queue allocation
5494 * need be done before this function is called
5496 if (type != I40E_VSI_FDIR) {
5497 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5499 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5503 vsi->base_queue = ret;
5505 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5507 /* VF has MSIX interrupt in VF range, don't allocate here */
5508 if (type == I40E_VSI_MAIN) {
5509 if (pf->support_multi_driver) {
5510 /* If support multi-driver, need to use INT0 instead of
5511 * allocating from msix pool. The Msix pool is init from
5512 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5513 * to 1 without calling i40e_res_pool_alloc.
5518 ret = i40e_res_pool_alloc(&pf->msix_pool,
5519 RTE_MIN(vsi->nb_qps,
5520 RTE_MAX_RXTX_INTR_VEC_ID));
5523 "VSI MAIN %d get heap failed %d",
5525 goto fail_queue_alloc;
5527 vsi->msix_intr = ret;
5528 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5529 RTE_MAX_RXTX_INTR_VEC_ID);
5531 } else if (type != I40E_VSI_SRIOV) {
5532 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5534 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5535 goto fail_queue_alloc;
5537 vsi->msix_intr = ret;
5545 if (type == I40E_VSI_MAIN) {
5546 /* For main VSI, no need to add since it's default one */
5547 vsi->uplink_seid = pf->mac_seid;
5548 vsi->seid = pf->main_vsi_seid;
5549 /* Bind queues with specific MSIX interrupt */
5551 * Needs 2 interrupt at least, one for misc cause which will
5552 * enabled from OS side, Another for queues binding the
5553 * interrupt from device side only.
5556 /* Get default VSI parameters from hardware */
5557 memset(&ctxt, 0, sizeof(ctxt));
5558 ctxt.seid = vsi->seid;
5559 ctxt.pf_num = hw->pf_id;
5560 ctxt.uplink_seid = vsi->uplink_seid;
5562 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5563 if (ret != I40E_SUCCESS) {
5564 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5565 goto fail_msix_alloc;
5567 rte_memcpy(&vsi->info, &ctxt.info,
5568 sizeof(struct i40e_aqc_vsi_properties_data));
5569 vsi->vsi_id = ctxt.vsi_number;
5570 vsi->info.valid_sections = 0;
5572 /* Configure tc, enabled TC0 only */
5573 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5575 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5576 goto fail_msix_alloc;
5579 /* TC, queue mapping */
5580 memset(&ctxt, 0, sizeof(ctxt));
5581 vsi->info.valid_sections |=
5582 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5583 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5584 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5585 rte_memcpy(&ctxt.info, &vsi->info,
5586 sizeof(struct i40e_aqc_vsi_properties_data));
5587 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5588 I40E_DEFAULT_TCMAP);
5589 if (ret != I40E_SUCCESS) {
5591 "Failed to configure TC queue mapping");
5592 goto fail_msix_alloc;
5594 ctxt.seid = vsi->seid;
5595 ctxt.pf_num = hw->pf_id;
5596 ctxt.uplink_seid = vsi->uplink_seid;
5599 /* Update VSI parameters */
5600 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5601 if (ret != I40E_SUCCESS) {
5602 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5603 goto fail_msix_alloc;
5606 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5607 sizeof(vsi->info.tc_mapping));
5608 rte_memcpy(&vsi->info.queue_mapping,
5609 &ctxt.info.queue_mapping,
5610 sizeof(vsi->info.queue_mapping));
5611 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5612 vsi->info.valid_sections = 0;
5614 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5618 * Updating default filter settings are necessary to prevent
5619 * reception of tagged packets.
5620 * Some old firmware configurations load a default macvlan
5621 * filter which accepts both tagged and untagged packets.
5622 * The updating is to use a normal filter instead if needed.
5623 * For NVM 4.2.2 or after, the updating is not needed anymore.
5624 * The firmware with correct configurations load the default
5625 * macvlan filter which is expected and cannot be removed.
5627 i40e_update_default_filter_setting(vsi);
5628 i40e_config_qinq(hw, vsi);
5629 } else if (type == I40E_VSI_SRIOV) {
5630 memset(&ctxt, 0, sizeof(ctxt));
5632 * For other VSI, the uplink_seid equals to uplink VSI's
5633 * uplink_seid since they share same VEB
5635 if (uplink_vsi == NULL)
5636 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5638 vsi->uplink_seid = uplink_vsi->uplink_seid;
5639 ctxt.pf_num = hw->pf_id;
5640 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5641 ctxt.uplink_seid = vsi->uplink_seid;
5642 ctxt.connection_type = 0x1;
5643 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5645 /* Use the VEB configuration if FW >= v5.0 */
5646 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5647 /* Configure switch ID */
5648 ctxt.info.valid_sections |=
5649 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5650 ctxt.info.switch_id =
5651 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5654 /* Configure port/vlan */
5655 ctxt.info.valid_sections |=
5656 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5657 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5658 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5659 hw->func_caps.enabled_tcmap);
5660 if (ret != I40E_SUCCESS) {
5662 "Failed to configure TC queue mapping");
5663 goto fail_msix_alloc;
5666 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5667 ctxt.info.valid_sections |=
5668 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5670 * Since VSI is not created yet, only configure parameter,
5671 * will add vsi below.
5674 i40e_config_qinq(hw, vsi);
5675 } else if (type == I40E_VSI_VMDQ2) {
5676 memset(&ctxt, 0, sizeof(ctxt));
5678 * For other VSI, the uplink_seid equals to uplink VSI's
5679 * uplink_seid since they share same VEB
5681 vsi->uplink_seid = uplink_vsi->uplink_seid;
5682 ctxt.pf_num = hw->pf_id;
5684 ctxt.uplink_seid = vsi->uplink_seid;
5685 ctxt.connection_type = 0x1;
5686 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5688 ctxt.info.valid_sections |=
5689 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5690 /* user_param carries flag to enable loop back */
5692 ctxt.info.switch_id =
5693 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5694 ctxt.info.switch_id |=
5695 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5698 /* Configure port/vlan */
5699 ctxt.info.valid_sections |=
5700 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5701 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5702 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5703 I40E_DEFAULT_TCMAP);
5704 if (ret != I40E_SUCCESS) {
5706 "Failed to configure TC queue mapping");
5707 goto fail_msix_alloc;
5709 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5710 ctxt.info.valid_sections |=
5711 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5712 } else if (type == I40E_VSI_FDIR) {
5713 memset(&ctxt, 0, sizeof(ctxt));
5714 vsi->uplink_seid = uplink_vsi->uplink_seid;
5715 ctxt.pf_num = hw->pf_id;
5717 ctxt.uplink_seid = vsi->uplink_seid;
5718 ctxt.connection_type = 0x1; /* regular data port */
5719 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5720 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5721 I40E_DEFAULT_TCMAP);
5722 if (ret != I40E_SUCCESS) {
5724 "Failed to configure TC queue mapping.");
5725 goto fail_msix_alloc;
5727 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5728 ctxt.info.valid_sections |=
5729 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5731 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5732 goto fail_msix_alloc;
5735 if (vsi->type != I40E_VSI_MAIN) {
5736 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5737 if (ret != I40E_SUCCESS) {
5738 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5739 hw->aq.asq_last_status);
5740 goto fail_msix_alloc;
5742 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5743 vsi->info.valid_sections = 0;
5744 vsi->seid = ctxt.seid;
5745 vsi->vsi_id = ctxt.vsi_number;
5746 vsi->sib_vsi_list.vsi = vsi;
5747 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5748 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5749 &vsi->sib_vsi_list, list);
5751 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5752 &vsi->sib_vsi_list, list);
5756 /* MAC/VLAN configuration */
5757 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5758 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5760 ret = i40e_vsi_add_mac(vsi, &filter);
5761 if (ret != I40E_SUCCESS) {
5762 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5763 goto fail_msix_alloc;
5766 /* Get VSI BW information */
5767 i40e_vsi_get_bw_config(vsi);
5770 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5772 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5778 /* Configure vlan filter on or off */
5780 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5783 struct i40e_mac_filter *f;
5785 struct i40e_mac_filter_info *mac_filter;
5786 enum rte_mac_filter_type desired_filter;
5787 int ret = I40E_SUCCESS;
5790 /* Filter to match MAC and VLAN */
5791 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5793 /* Filter to match only MAC */
5794 desired_filter = RTE_MAC_PERFECT_MATCH;
5799 mac_filter = rte_zmalloc("mac_filter_info_data",
5800 num * sizeof(*mac_filter), 0);
5801 if (mac_filter == NULL) {
5802 PMD_DRV_LOG(ERR, "failed to allocate memory");
5803 return I40E_ERR_NO_MEMORY;
5808 /* Remove all existing mac */
5809 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5810 mac_filter[i] = f->mac_info;
5811 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5813 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5814 on ? "enable" : "disable");
5820 /* Override with new filter */
5821 for (i = 0; i < num; i++) {
5822 mac_filter[i].filter_type = desired_filter;
5823 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5825 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5826 on ? "enable" : "disable");
5832 rte_free(mac_filter);
5836 /* Configure vlan stripping on or off */
5838 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5840 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5841 struct i40e_vsi_context ctxt;
5843 int ret = I40E_SUCCESS;
5845 /* Check if it has been already on or off */
5846 if (vsi->info.valid_sections &
5847 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5849 if ((vsi->info.port_vlan_flags &
5850 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5851 return 0; /* already on */
5853 if ((vsi->info.port_vlan_flags &
5854 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5855 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5856 return 0; /* already off */
5861 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5863 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5864 vsi->info.valid_sections =
5865 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5866 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5867 vsi->info.port_vlan_flags |= vlan_flags;
5868 ctxt.seid = vsi->seid;
5869 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5870 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5872 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5873 on ? "enable" : "disable");
5879 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5881 struct rte_eth_dev_data *data = dev->data;
5885 /* Apply vlan offload setting */
5886 mask = ETH_VLAN_STRIP_MASK |
5887 ETH_VLAN_FILTER_MASK |
5888 ETH_VLAN_EXTEND_MASK;
5889 ret = i40e_vlan_offload_set(dev, mask);
5891 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5895 /* Apply pvid setting */
5896 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5897 data->dev_conf.txmode.hw_vlan_insert_pvid);
5899 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5905 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5907 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5909 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5913 i40e_update_flow_control(struct i40e_hw *hw)
5915 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5916 struct i40e_link_status link_status;
5917 uint32_t rxfc = 0, txfc = 0, reg;
5921 memset(&link_status, 0, sizeof(link_status));
5922 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5923 if (ret != I40E_SUCCESS) {
5924 PMD_DRV_LOG(ERR, "Failed to get link status information");
5925 goto write_reg; /* Disable flow control */
5928 an_info = hw->phy.link_info.an_info;
5929 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5930 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5931 ret = I40E_ERR_NOT_READY;
5932 goto write_reg; /* Disable flow control */
5935 * If link auto negotiation is enabled, flow control needs to
5936 * be configured according to it
5938 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5939 case I40E_LINK_PAUSE_RXTX:
5942 hw->fc.current_mode = I40E_FC_FULL;
5944 case I40E_AQ_LINK_PAUSE_RX:
5946 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5948 case I40E_AQ_LINK_PAUSE_TX:
5950 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5953 hw->fc.current_mode = I40E_FC_NONE;
5958 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5959 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5960 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5961 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5962 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5963 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5970 i40e_pf_setup(struct i40e_pf *pf)
5972 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5973 struct i40e_filter_control_settings settings;
5974 struct i40e_vsi *vsi;
5977 /* Clear all stats counters */
5978 pf->offset_loaded = FALSE;
5979 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5980 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5981 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5982 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5984 ret = i40e_pf_get_switch_config(pf);
5985 if (ret != I40E_SUCCESS) {
5986 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5990 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5992 PMD_INIT_LOG(WARNING,
5993 "failed to allocate switch domain for device %d", ret);
5995 if (pf->flags & I40E_FLAG_FDIR) {
5996 /* make queue allocated first, let FDIR use queue pair 0*/
5997 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5998 if (ret != I40E_FDIR_QUEUE_ID) {
6000 "queue allocation fails for FDIR: ret =%d",
6002 pf->flags &= ~I40E_FLAG_FDIR;
6005 /* main VSI setup */
6006 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6008 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6009 return I40E_ERR_NOT_READY;
6013 /* Configure filter control */
6014 memset(&settings, 0, sizeof(settings));
6015 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6016 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6017 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6018 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6020 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6021 hw->func_caps.rss_table_size);
6022 return I40E_ERR_PARAM;
6024 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6025 hw->func_caps.rss_table_size);
6026 pf->hash_lut_size = hw->func_caps.rss_table_size;
6028 /* Enable ethtype and macvlan filters */
6029 settings.enable_ethtype = TRUE;
6030 settings.enable_macvlan = TRUE;
6031 ret = i40e_set_filter_control(hw, &settings);
6033 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6036 /* Update flow control according to the auto negotiation */
6037 i40e_update_flow_control(hw);
6039 return I40E_SUCCESS;
6043 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6049 * Set or clear TX Queue Disable flags,
6050 * which is required by hardware.
6052 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6053 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6055 /* Wait until the request is finished */
6056 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6057 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6058 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6059 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6060 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6066 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6067 return I40E_SUCCESS; /* already on, skip next steps */
6069 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6070 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6072 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6073 return I40E_SUCCESS; /* already off, skip next steps */
6074 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6076 /* Write the register */
6077 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6078 /* Check the result */
6079 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6080 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6081 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6083 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6084 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6087 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6088 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6092 /* Check if it is timeout */
6093 if (j >= I40E_CHK_Q_ENA_COUNT) {
6094 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6095 (on ? "enable" : "disable"), q_idx);
6096 return I40E_ERR_TIMEOUT;
6099 return I40E_SUCCESS;
6102 /* Swith on or off the tx queues */
6104 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6106 struct rte_eth_dev_data *dev_data = pf->dev_data;
6107 struct i40e_tx_queue *txq;
6108 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6112 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6113 txq = dev_data->tx_queues[i];
6114 /* Don't operate the queue if not configured or
6115 * if starting only per queue */
6116 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6119 ret = i40e_dev_tx_queue_start(dev, i);
6121 ret = i40e_dev_tx_queue_stop(dev, i);
6122 if ( ret != I40E_SUCCESS)
6126 return I40E_SUCCESS;
6130 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6135 /* Wait until the request is finished */
6136 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6137 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6138 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6139 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6140 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6145 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6146 return I40E_SUCCESS; /* Already on, skip next steps */
6147 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6149 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6150 return I40E_SUCCESS; /* Already off, skip next steps */
6151 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6154 /* Write the register */
6155 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6156 /* Check the result */
6157 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6158 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6159 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6161 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6162 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6165 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6166 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6171 /* Check if it is timeout */
6172 if (j >= I40E_CHK_Q_ENA_COUNT) {
6173 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6174 (on ? "enable" : "disable"), q_idx);
6175 return I40E_ERR_TIMEOUT;
6178 return I40E_SUCCESS;
6180 /* Switch on or off the rx queues */
6182 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6184 struct rte_eth_dev_data *dev_data = pf->dev_data;
6185 struct i40e_rx_queue *rxq;
6186 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6190 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6191 rxq = dev_data->rx_queues[i];
6192 /* Don't operate the queue if not configured or
6193 * if starting only per queue */
6194 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6197 ret = i40e_dev_rx_queue_start(dev, i);
6199 ret = i40e_dev_rx_queue_stop(dev, i);
6200 if (ret != I40E_SUCCESS)
6204 return I40E_SUCCESS;
6207 /* Switch on or off all the rx/tx queues */
6209 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6214 /* enable rx queues before enabling tx queues */
6215 ret = i40e_dev_switch_rx_queues(pf, on);
6217 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6220 ret = i40e_dev_switch_tx_queues(pf, on);
6222 /* Stop tx queues before stopping rx queues */
6223 ret = i40e_dev_switch_tx_queues(pf, on);
6225 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6228 ret = i40e_dev_switch_rx_queues(pf, on);
6234 /* Initialize VSI for TX */
6236 i40e_dev_tx_init(struct i40e_pf *pf)
6238 struct rte_eth_dev_data *data = pf->dev_data;
6240 uint32_t ret = I40E_SUCCESS;
6241 struct i40e_tx_queue *txq;
6243 for (i = 0; i < data->nb_tx_queues; i++) {
6244 txq = data->tx_queues[i];
6245 if (!txq || !txq->q_set)
6247 ret = i40e_tx_queue_init(txq);
6248 if (ret != I40E_SUCCESS)
6251 if (ret == I40E_SUCCESS)
6252 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6258 /* Initialize VSI for RX */
6260 i40e_dev_rx_init(struct i40e_pf *pf)
6262 struct rte_eth_dev_data *data = pf->dev_data;
6263 int ret = I40E_SUCCESS;
6265 struct i40e_rx_queue *rxq;
6267 i40e_pf_config_mq_rx(pf);
6268 for (i = 0; i < data->nb_rx_queues; i++) {
6269 rxq = data->rx_queues[i];
6270 if (!rxq || !rxq->q_set)
6273 ret = i40e_rx_queue_init(rxq);
6274 if (ret != I40E_SUCCESS) {
6276 "Failed to do RX queue initialization");
6280 if (ret == I40E_SUCCESS)
6281 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6288 i40e_dev_rxtx_init(struct i40e_pf *pf)
6292 err = i40e_dev_tx_init(pf);
6294 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6297 err = i40e_dev_rx_init(pf);
6299 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6307 i40e_vmdq_setup(struct rte_eth_dev *dev)
6309 struct rte_eth_conf *conf = &dev->data->dev_conf;
6310 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6311 int i, err, conf_vsis, j, loop;
6312 struct i40e_vsi *vsi;
6313 struct i40e_vmdq_info *vmdq_info;
6314 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6315 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6318 * Disable interrupt to avoid message from VF. Furthermore, it will
6319 * avoid race condition in VSI creation/destroy.
6321 i40e_pf_disable_irq0(hw);
6323 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6324 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6328 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6329 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6330 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6331 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6332 pf->max_nb_vmdq_vsi);
6336 if (pf->vmdq != NULL) {
6337 PMD_INIT_LOG(INFO, "VMDQ already configured");
6341 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6342 sizeof(*vmdq_info) * conf_vsis, 0);
6344 if (pf->vmdq == NULL) {
6345 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6349 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6351 /* Create VMDQ VSI */
6352 for (i = 0; i < conf_vsis; i++) {
6353 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6354 vmdq_conf->enable_loop_back);
6356 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6360 vmdq_info = &pf->vmdq[i];
6362 vmdq_info->vsi = vsi;
6364 pf->nb_cfg_vmdq_vsi = conf_vsis;
6366 /* Configure Vlan */
6367 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6368 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6369 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6370 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6371 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6372 vmdq_conf->pool_map[i].vlan_id, j);
6374 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6375 vmdq_conf->pool_map[i].vlan_id);
6377 PMD_INIT_LOG(ERR, "Failed to add vlan");
6385 i40e_pf_enable_irq0(hw);
6390 for (i = 0; i < conf_vsis; i++)
6391 if (pf->vmdq[i].vsi == NULL)
6394 i40e_vsi_release(pf->vmdq[i].vsi);
6398 i40e_pf_enable_irq0(hw);
6403 i40e_stat_update_32(struct i40e_hw *hw,
6411 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6415 if (new_data >= *offset)
6416 *stat = (uint64_t)(new_data - *offset);
6418 *stat = (uint64_t)((new_data +
6419 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6423 i40e_stat_update_48(struct i40e_hw *hw,
6432 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6433 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6434 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6439 if (new_data >= *offset)
6440 *stat = new_data - *offset;
6442 *stat = (uint64_t)((new_data +
6443 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6445 *stat &= I40E_48_BIT_MASK;
6450 i40e_pf_disable_irq0(struct i40e_hw *hw)
6452 /* Disable all interrupt types */
6453 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6454 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6455 I40E_WRITE_FLUSH(hw);
6460 i40e_pf_enable_irq0(struct i40e_hw *hw)
6462 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6463 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6464 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6465 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6466 I40E_WRITE_FLUSH(hw);
6470 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6472 /* read pending request and disable first */
6473 i40e_pf_disable_irq0(hw);
6474 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6475 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6476 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6479 /* Link no queues with irq0 */
6480 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6481 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6485 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6487 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6488 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6491 uint32_t index, offset, val;
6496 * Try to find which VF trigger a reset, use absolute VF id to access
6497 * since the reg is global register.
6499 for (i = 0; i < pf->vf_num; i++) {
6500 abs_vf_id = hw->func_caps.vf_base_id + i;
6501 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6502 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6503 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6504 /* VFR event occurred */
6505 if (val & (0x1 << offset)) {
6508 /* Clear the event first */
6509 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6511 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6513 * Only notify a VF reset event occurred,
6514 * don't trigger another SW reset
6516 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6517 if (ret != I40E_SUCCESS)
6518 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6524 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6526 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6529 for (i = 0; i < pf->vf_num; i++)
6530 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6534 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6536 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6537 struct i40e_arq_event_info info;
6538 uint16_t pending, opcode;
6541 info.buf_len = I40E_AQ_BUF_SZ;
6542 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6543 if (!info.msg_buf) {
6544 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6550 ret = i40e_clean_arq_element(hw, &info, &pending);
6552 if (ret != I40E_SUCCESS) {
6554 "Failed to read msg from AdminQ, aq_err: %u",
6555 hw->aq.asq_last_status);
6558 opcode = rte_le_to_cpu_16(info.desc.opcode);
6561 case i40e_aqc_opc_send_msg_to_pf:
6562 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6563 i40e_pf_host_handle_vf_msg(dev,
6564 rte_le_to_cpu_16(info.desc.retval),
6565 rte_le_to_cpu_32(info.desc.cookie_high),
6566 rte_le_to_cpu_32(info.desc.cookie_low),
6570 case i40e_aqc_opc_get_link_status:
6571 ret = i40e_dev_link_update(dev, 0);
6573 _rte_eth_dev_callback_process(dev,
6574 RTE_ETH_EVENT_INTR_LSC, NULL);
6577 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6582 rte_free(info.msg_buf);
6586 * Interrupt handler triggered by NIC for handling
6587 * specific interrupt.
6590 * Pointer to interrupt handle.
6592 * The address of parameter (struct rte_eth_dev *) regsitered before.
6598 i40e_dev_interrupt_handler(void *param)
6600 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604 /* Disable interrupt */
6605 i40e_pf_disable_irq0(hw);
6607 /* read out interrupt causes */
6608 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6610 /* No interrupt event indicated */
6611 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6612 PMD_DRV_LOG(INFO, "No interrupt event");
6615 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6616 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6617 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6618 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6619 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6620 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6621 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6622 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6623 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6624 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6625 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6626 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6627 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6628 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6630 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6631 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6632 i40e_dev_handle_vfr_event(dev);
6634 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6635 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6636 i40e_dev_handle_aq_msg(dev);
6640 /* Enable interrupt */
6641 i40e_pf_enable_irq0(hw);
6645 i40e_dev_alarm_handler(void *param)
6647 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6651 /* Disable interrupt */
6652 i40e_pf_disable_irq0(hw);
6654 /* read out interrupt causes */
6655 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6657 /* No interrupt event indicated */
6658 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6660 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6661 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6662 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6663 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6664 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6665 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6666 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6667 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6668 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6669 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6670 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6671 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6672 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6673 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6675 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6676 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6677 i40e_dev_handle_vfr_event(dev);
6679 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6680 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6681 i40e_dev_handle_aq_msg(dev);
6685 /* Enable interrupt */
6686 i40e_pf_enable_irq0(hw);
6687 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6688 i40e_dev_alarm_handler, dev);
6692 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6693 struct i40e_macvlan_filter *filter,
6696 int ele_num, ele_buff_size;
6697 int num, actual_num, i;
6699 int ret = I40E_SUCCESS;
6700 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6701 struct i40e_aqc_add_macvlan_element_data *req_list;
6703 if (filter == NULL || total == 0)
6704 return I40E_ERR_PARAM;
6705 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6706 ele_buff_size = hw->aq.asq_buf_size;
6708 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6709 if (req_list == NULL) {
6710 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6711 return I40E_ERR_NO_MEMORY;
6716 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6717 memset(req_list, 0, ele_buff_size);
6719 for (i = 0; i < actual_num; i++) {
6720 rte_memcpy(req_list[i].mac_addr,
6721 &filter[num + i].macaddr, ETH_ADDR_LEN);
6722 req_list[i].vlan_tag =
6723 rte_cpu_to_le_16(filter[num + i].vlan_id);
6725 switch (filter[num + i].filter_type) {
6726 case RTE_MAC_PERFECT_MATCH:
6727 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6728 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6730 case RTE_MACVLAN_PERFECT_MATCH:
6731 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6733 case RTE_MAC_HASH_MATCH:
6734 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6735 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6737 case RTE_MACVLAN_HASH_MATCH:
6738 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6741 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6742 ret = I40E_ERR_PARAM;
6746 req_list[i].queue_number = 0;
6748 req_list[i].flags = rte_cpu_to_le_16(flags);
6751 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6753 if (ret != I40E_SUCCESS) {
6754 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6758 } while (num < total);
6766 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6767 struct i40e_macvlan_filter *filter,
6770 int ele_num, ele_buff_size;
6771 int num, actual_num, i;
6773 int ret = I40E_SUCCESS;
6774 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6775 struct i40e_aqc_remove_macvlan_element_data *req_list;
6777 if (filter == NULL || total == 0)
6778 return I40E_ERR_PARAM;
6780 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6781 ele_buff_size = hw->aq.asq_buf_size;
6783 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6784 if (req_list == NULL) {
6785 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6786 return I40E_ERR_NO_MEMORY;
6791 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6792 memset(req_list, 0, ele_buff_size);
6794 for (i = 0; i < actual_num; i++) {
6795 rte_memcpy(req_list[i].mac_addr,
6796 &filter[num + i].macaddr, ETH_ADDR_LEN);
6797 req_list[i].vlan_tag =
6798 rte_cpu_to_le_16(filter[num + i].vlan_id);
6800 switch (filter[num + i].filter_type) {
6801 case RTE_MAC_PERFECT_MATCH:
6802 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6803 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6805 case RTE_MACVLAN_PERFECT_MATCH:
6806 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6808 case RTE_MAC_HASH_MATCH:
6809 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6810 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6812 case RTE_MACVLAN_HASH_MATCH:
6813 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6816 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6817 ret = I40E_ERR_PARAM;
6820 req_list[i].flags = rte_cpu_to_le_16(flags);
6823 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6825 if (ret != I40E_SUCCESS) {
6826 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6830 } while (num < total);
6837 /* Find out specific MAC filter */
6838 static struct i40e_mac_filter *
6839 i40e_find_mac_filter(struct i40e_vsi *vsi,
6840 struct ether_addr *macaddr)
6842 struct i40e_mac_filter *f;
6844 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6845 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6853 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6856 uint32_t vid_idx, vid_bit;
6858 if (vlan_id > ETH_VLAN_ID_MAX)
6861 vid_idx = I40E_VFTA_IDX(vlan_id);
6862 vid_bit = I40E_VFTA_BIT(vlan_id);
6864 if (vsi->vfta[vid_idx] & vid_bit)
6871 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6872 uint16_t vlan_id, bool on)
6874 uint32_t vid_idx, vid_bit;
6876 vid_idx = I40E_VFTA_IDX(vlan_id);
6877 vid_bit = I40E_VFTA_BIT(vlan_id);
6880 vsi->vfta[vid_idx] |= vid_bit;
6882 vsi->vfta[vid_idx] &= ~vid_bit;
6886 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6887 uint16_t vlan_id, bool on)
6889 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6890 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6893 if (vlan_id > ETH_VLAN_ID_MAX)
6896 i40e_store_vlan_filter(vsi, vlan_id, on);
6898 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6901 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6904 ret = i40e_aq_add_vlan(hw, vsi->seid,
6905 &vlan_data, 1, NULL);
6906 if (ret != I40E_SUCCESS)
6907 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6909 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6910 &vlan_data, 1, NULL);
6911 if (ret != I40E_SUCCESS)
6913 "Failed to remove vlan filter");
6918 * Find all vlan options for specific mac addr,
6919 * return with actual vlan found.
6922 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6923 struct i40e_macvlan_filter *mv_f,
6924 int num, struct ether_addr *addr)
6930 * Not to use i40e_find_vlan_filter to decrease the loop time,
6931 * although the code looks complex.
6933 if (num < vsi->vlan_num)
6934 return I40E_ERR_PARAM;
6937 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6939 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6940 if (vsi->vfta[j] & (1 << k)) {
6943 "vlan number doesn't match");
6944 return I40E_ERR_PARAM;
6946 rte_memcpy(&mv_f[i].macaddr,
6947 addr, ETH_ADDR_LEN);
6949 j * I40E_UINT32_BIT_SIZE + k;
6955 return I40E_SUCCESS;
6959 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6960 struct i40e_macvlan_filter *mv_f,
6965 struct i40e_mac_filter *f;
6967 if (num < vsi->mac_num)
6968 return I40E_ERR_PARAM;
6970 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6972 PMD_DRV_LOG(ERR, "buffer number not match");
6973 return I40E_ERR_PARAM;
6975 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6977 mv_f[i].vlan_id = vlan;
6978 mv_f[i].filter_type = f->mac_info.filter_type;
6982 return I40E_SUCCESS;
6986 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6989 struct i40e_mac_filter *f;
6990 struct i40e_macvlan_filter *mv_f;
6991 int ret = I40E_SUCCESS;
6993 if (vsi == NULL || vsi->mac_num == 0)
6994 return I40E_ERR_PARAM;
6996 /* Case that no vlan is set */
6997 if (vsi->vlan_num == 0)
7000 num = vsi->mac_num * vsi->vlan_num;
7002 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7004 PMD_DRV_LOG(ERR, "failed to allocate memory");
7005 return I40E_ERR_NO_MEMORY;
7009 if (vsi->vlan_num == 0) {
7010 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7011 rte_memcpy(&mv_f[i].macaddr,
7012 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7013 mv_f[i].filter_type = f->mac_info.filter_type;
7014 mv_f[i].vlan_id = 0;
7018 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7019 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7020 vsi->vlan_num, &f->mac_info.mac_addr);
7021 if (ret != I40E_SUCCESS)
7023 for (j = i; j < i + vsi->vlan_num; j++)
7024 mv_f[j].filter_type = f->mac_info.filter_type;
7029 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7037 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7039 struct i40e_macvlan_filter *mv_f;
7041 int ret = I40E_SUCCESS;
7043 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7044 return I40E_ERR_PARAM;
7046 /* If it's already set, just return */
7047 if (i40e_find_vlan_filter(vsi,vlan))
7048 return I40E_SUCCESS;
7050 mac_num = vsi->mac_num;
7053 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7054 return I40E_ERR_PARAM;
7057 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7060 PMD_DRV_LOG(ERR, "failed to allocate memory");
7061 return I40E_ERR_NO_MEMORY;
7064 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7066 if (ret != I40E_SUCCESS)
7069 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7071 if (ret != I40E_SUCCESS)
7074 i40e_set_vlan_filter(vsi, vlan, 1);
7084 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7086 struct i40e_macvlan_filter *mv_f;
7088 int ret = I40E_SUCCESS;
7091 * Vlan 0 is the generic filter for untagged packets
7092 * and can't be removed.
7094 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7095 return I40E_ERR_PARAM;
7097 /* If can't find it, just return */
7098 if (!i40e_find_vlan_filter(vsi, vlan))
7099 return I40E_ERR_PARAM;
7101 mac_num = vsi->mac_num;
7104 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7105 return I40E_ERR_PARAM;
7108 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7111 PMD_DRV_LOG(ERR, "failed to allocate memory");
7112 return I40E_ERR_NO_MEMORY;
7115 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7117 if (ret != I40E_SUCCESS)
7120 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7122 if (ret != I40E_SUCCESS)
7125 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7126 if (vsi->vlan_num == 1) {
7127 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7128 if (ret != I40E_SUCCESS)
7131 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7132 if (ret != I40E_SUCCESS)
7136 i40e_set_vlan_filter(vsi, vlan, 0);
7146 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7148 struct i40e_mac_filter *f;
7149 struct i40e_macvlan_filter *mv_f;
7150 int i, vlan_num = 0;
7151 int ret = I40E_SUCCESS;
7153 /* If it's add and we've config it, return */
7154 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7156 return I40E_SUCCESS;
7157 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7158 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7161 * If vlan_num is 0, that's the first time to add mac,
7162 * set mask for vlan_id 0.
7164 if (vsi->vlan_num == 0) {
7165 i40e_set_vlan_filter(vsi, 0, 1);
7168 vlan_num = vsi->vlan_num;
7169 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7170 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7173 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7175 PMD_DRV_LOG(ERR, "failed to allocate memory");
7176 return I40E_ERR_NO_MEMORY;
7179 for (i = 0; i < vlan_num; i++) {
7180 mv_f[i].filter_type = mac_filter->filter_type;
7181 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7185 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7186 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7187 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7188 &mac_filter->mac_addr);
7189 if (ret != I40E_SUCCESS)
7193 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7194 if (ret != I40E_SUCCESS)
7197 /* Add the mac addr into mac list */
7198 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7200 PMD_DRV_LOG(ERR, "failed to allocate memory");
7201 ret = I40E_ERR_NO_MEMORY;
7204 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7206 f->mac_info.filter_type = mac_filter->filter_type;
7207 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7218 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7220 struct i40e_mac_filter *f;
7221 struct i40e_macvlan_filter *mv_f;
7223 enum rte_mac_filter_type filter_type;
7224 int ret = I40E_SUCCESS;
7226 /* Can't find it, return an error */
7227 f = i40e_find_mac_filter(vsi, addr);
7229 return I40E_ERR_PARAM;
7231 vlan_num = vsi->vlan_num;
7232 filter_type = f->mac_info.filter_type;
7233 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7234 filter_type == RTE_MACVLAN_HASH_MATCH) {
7235 if (vlan_num == 0) {
7236 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7237 return I40E_ERR_PARAM;
7239 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7240 filter_type == RTE_MAC_HASH_MATCH)
7243 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7245 PMD_DRV_LOG(ERR, "failed to allocate memory");
7246 return I40E_ERR_NO_MEMORY;
7249 for (i = 0; i < vlan_num; i++) {
7250 mv_f[i].filter_type = filter_type;
7251 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7254 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7255 filter_type == RTE_MACVLAN_HASH_MATCH) {
7256 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7257 if (ret != I40E_SUCCESS)
7261 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7262 if (ret != I40E_SUCCESS)
7265 /* Remove the mac addr into mac list */
7266 TAILQ_REMOVE(&vsi->mac_list, f, next);
7276 /* Configure hash enable flags for RSS */
7278 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7286 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7287 if (flags & (1ULL << i))
7288 hena |= adapter->pctypes_tbl[i];
7294 /* Parse the hash enable flags */
7296 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7298 uint64_t rss_hf = 0;
7304 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7305 if (flags & adapter->pctypes_tbl[i])
7306 rss_hf |= (1ULL << i);
7313 i40e_pf_disable_rss(struct i40e_pf *pf)
7315 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7317 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7318 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7319 I40E_WRITE_FLUSH(hw);
7323 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7325 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7326 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7327 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7328 I40E_VFQF_HKEY_MAX_INDEX :
7329 I40E_PFQF_HKEY_MAX_INDEX;
7332 if (!key || key_len == 0) {
7333 PMD_DRV_LOG(DEBUG, "No key to be configured");
7335 } else if (key_len != (key_idx + 1) *
7337 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7341 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7342 struct i40e_aqc_get_set_rss_key_data *key_dw =
7343 (struct i40e_aqc_get_set_rss_key_data *)key;
7345 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7347 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7349 uint32_t *hash_key = (uint32_t *)key;
7352 if (vsi->type == I40E_VSI_SRIOV) {
7353 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7356 I40E_VFQF_HKEY1(i, vsi->user_param),
7360 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7361 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7364 I40E_WRITE_FLUSH(hw);
7371 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7373 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7374 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7378 if (!key || !key_len)
7381 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7382 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7383 (struct i40e_aqc_get_set_rss_key_data *)key);
7385 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7389 uint32_t *key_dw = (uint32_t *)key;
7392 if (vsi->type == I40E_VSI_SRIOV) {
7393 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7394 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7395 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7397 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7400 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7401 reg = I40E_PFQF_HKEY(i);
7402 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7404 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7412 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7414 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7418 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7419 rss_conf->rss_key_len);
7423 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7424 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7425 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7426 I40E_WRITE_FLUSH(hw);
7432 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7433 struct rte_eth_rss_conf *rss_conf)
7435 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7436 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7437 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7440 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7441 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7443 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7444 if (rss_hf != 0) /* Enable RSS */
7446 return 0; /* Nothing to do */
7449 if (rss_hf == 0) /* Disable RSS */
7452 return i40e_hw_rss_hash_set(pf, rss_conf);
7456 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7457 struct rte_eth_rss_conf *rss_conf)
7459 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7460 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7463 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7464 &rss_conf->rss_key_len);
7466 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7467 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7468 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7474 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7476 switch (filter_type) {
7477 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7478 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7480 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7481 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7483 case RTE_TUNNEL_FILTER_IMAC_TENID:
7484 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7486 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7487 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7489 case ETH_TUNNEL_FILTER_IMAC:
7490 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7492 case ETH_TUNNEL_FILTER_OIP:
7493 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7495 case ETH_TUNNEL_FILTER_IIP:
7496 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7499 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7506 /* Convert tunnel filter structure */
7508 i40e_tunnel_filter_convert(
7509 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7510 struct i40e_tunnel_filter *tunnel_filter)
7512 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7513 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7514 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7515 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7516 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7517 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7518 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7519 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7520 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7522 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7523 tunnel_filter->input.flags = cld_filter->element.flags;
7524 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7525 tunnel_filter->queue = cld_filter->element.queue_number;
7526 rte_memcpy(tunnel_filter->input.general_fields,
7527 cld_filter->general_fields,
7528 sizeof(cld_filter->general_fields));
7533 /* Check if there exists the tunnel filter */
7534 struct i40e_tunnel_filter *
7535 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7536 const struct i40e_tunnel_filter_input *input)
7540 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7544 return tunnel_rule->hash_map[ret];
7547 /* Add a tunnel filter into the SW list */
7549 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7550 struct i40e_tunnel_filter *tunnel_filter)
7552 struct i40e_tunnel_rule *rule = &pf->tunnel;
7555 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7558 "Failed to insert tunnel filter to hash table %d!",
7562 rule->hash_map[ret] = tunnel_filter;
7564 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7569 /* Delete a tunnel filter from the SW list */
7571 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7572 struct i40e_tunnel_filter_input *input)
7574 struct i40e_tunnel_rule *rule = &pf->tunnel;
7575 struct i40e_tunnel_filter *tunnel_filter;
7578 ret = rte_hash_del_key(rule->hash_table, input);
7581 "Failed to delete tunnel filter to hash table %d!",
7585 tunnel_filter = rule->hash_map[ret];
7586 rule->hash_map[ret] = NULL;
7588 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7589 rte_free(tunnel_filter);
7595 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7596 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7600 uint32_t ipv4_addr, ipv4_addr_le;
7601 uint8_t i, tun_type = 0;
7602 /* internal varialbe to convert ipv6 byte order */
7603 uint32_t convert_ipv6[4];
7605 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7606 struct i40e_vsi *vsi = pf->main_vsi;
7607 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7608 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7609 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7610 struct i40e_tunnel_filter *tunnel, *node;
7611 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7613 cld_filter = rte_zmalloc("tunnel_filter",
7614 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7617 if (NULL == cld_filter) {
7618 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7621 pfilter = cld_filter;
7623 ether_addr_copy(&tunnel_filter->outer_mac,
7624 (struct ether_addr *)&pfilter->element.outer_mac);
7625 ether_addr_copy(&tunnel_filter->inner_mac,
7626 (struct ether_addr *)&pfilter->element.inner_mac);
7628 pfilter->element.inner_vlan =
7629 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7630 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7631 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7632 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7633 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7634 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7636 sizeof(pfilter->element.ipaddr.v4.data));
7638 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7639 for (i = 0; i < 4; i++) {
7641 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7643 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7645 sizeof(pfilter->element.ipaddr.v6.data));
7648 /* check tunneled type */
7649 switch (tunnel_filter->tunnel_type) {
7650 case RTE_TUNNEL_TYPE_VXLAN:
7651 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7653 case RTE_TUNNEL_TYPE_NVGRE:
7654 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7656 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7657 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7660 /* Other tunnel types is not supported. */
7661 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7662 rte_free(cld_filter);
7666 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7667 &pfilter->element.flags);
7669 rte_free(cld_filter);
7673 pfilter->element.flags |= rte_cpu_to_le_16(
7674 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7675 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7676 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7677 pfilter->element.queue_number =
7678 rte_cpu_to_le_16(tunnel_filter->queue_id);
7680 /* Check if there is the filter in SW list */
7681 memset(&check_filter, 0, sizeof(check_filter));
7682 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7683 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7685 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7686 rte_free(cld_filter);
7690 if (!add && !node) {
7691 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7692 rte_free(cld_filter);
7697 ret = i40e_aq_add_cloud_filters(hw,
7698 vsi->seid, &cld_filter->element, 1);
7700 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7701 rte_free(cld_filter);
7704 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7705 if (tunnel == NULL) {
7706 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7707 rte_free(cld_filter);
7711 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7712 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7716 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7717 &cld_filter->element, 1);
7719 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7720 rte_free(cld_filter);
7723 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7726 rte_free(cld_filter);
7730 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7731 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7732 #define I40E_TR_GENEVE_KEY_MASK 0x8
7733 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7734 #define I40E_TR_GRE_KEY_MASK 0x400
7735 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7736 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7739 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7741 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7742 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7743 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7744 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7745 enum i40e_status_code status = I40E_SUCCESS;
7747 if (pf->support_multi_driver) {
7748 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7749 return I40E_NOT_SUPPORTED;
7752 memset(&filter_replace, 0,
7753 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7754 memset(&filter_replace_buf, 0,
7755 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7757 /* create L1 filter */
7758 filter_replace.old_filter_type =
7759 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7760 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7761 filter_replace.tr_bit = 0;
7763 /* Prepare the buffer, 3 entries */
7764 filter_replace_buf.data[0] =
7765 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7766 filter_replace_buf.data[0] |=
7767 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7768 filter_replace_buf.data[2] = 0xFF;
7769 filter_replace_buf.data[3] = 0xFF;
7770 filter_replace_buf.data[4] =
7771 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7772 filter_replace_buf.data[4] |=
7773 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7774 filter_replace_buf.data[7] = 0xF0;
7775 filter_replace_buf.data[8]
7776 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7777 filter_replace_buf.data[8] |=
7778 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7779 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7780 I40E_TR_GENEVE_KEY_MASK |
7781 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7782 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7783 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7784 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7786 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7787 &filter_replace_buf);
7788 if (!status && (filter_replace.old_filter_type !=
7789 filter_replace.new_filter_type))
7790 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7791 " original: 0x%x, new: 0x%x",
7793 filter_replace.old_filter_type,
7794 filter_replace.new_filter_type);
7800 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7802 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7803 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7804 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7805 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7806 enum i40e_status_code status = I40E_SUCCESS;
7808 if (pf->support_multi_driver) {
7809 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7810 return I40E_NOT_SUPPORTED;
7814 memset(&filter_replace, 0,
7815 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7816 memset(&filter_replace_buf, 0,
7817 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7818 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7819 I40E_AQC_MIRROR_CLOUD_FILTER;
7820 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7821 filter_replace.new_filter_type =
7822 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7823 /* Prepare the buffer, 2 entries */
7824 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7825 filter_replace_buf.data[0] |=
7826 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7827 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7828 filter_replace_buf.data[4] |=
7829 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7830 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7831 &filter_replace_buf);
7834 if (filter_replace.old_filter_type !=
7835 filter_replace.new_filter_type)
7836 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7837 " original: 0x%x, new: 0x%x",
7839 filter_replace.old_filter_type,
7840 filter_replace.new_filter_type);
7843 memset(&filter_replace, 0,
7844 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7845 memset(&filter_replace_buf, 0,
7846 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7848 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7849 I40E_AQC_MIRROR_CLOUD_FILTER;
7850 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7851 filter_replace.new_filter_type =
7852 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7853 /* Prepare the buffer, 2 entries */
7854 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7855 filter_replace_buf.data[0] |=
7856 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7857 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7858 filter_replace_buf.data[4] |=
7859 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7861 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7862 &filter_replace_buf);
7863 if (!status && (filter_replace.old_filter_type !=
7864 filter_replace.new_filter_type))
7865 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7866 " original: 0x%x, new: 0x%x",
7868 filter_replace.old_filter_type,
7869 filter_replace.new_filter_type);
7874 static enum i40e_status_code
7875 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7877 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7878 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7879 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7880 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7881 enum i40e_status_code status = I40E_SUCCESS;
7883 if (pf->support_multi_driver) {
7884 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7885 return I40E_NOT_SUPPORTED;
7889 memset(&filter_replace, 0,
7890 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7891 memset(&filter_replace_buf, 0,
7892 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7893 /* create L1 filter */
7894 filter_replace.old_filter_type =
7895 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7896 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7897 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7898 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7899 /* Prepare the buffer, 2 entries */
7900 filter_replace_buf.data[0] =
7901 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7902 filter_replace_buf.data[0] |=
7903 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7904 filter_replace_buf.data[2] = 0xFF;
7905 filter_replace_buf.data[3] = 0xFF;
7906 filter_replace_buf.data[4] =
7907 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7908 filter_replace_buf.data[4] |=
7909 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7910 filter_replace_buf.data[6] = 0xFF;
7911 filter_replace_buf.data[7] = 0xFF;
7912 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7913 &filter_replace_buf);
7916 if (filter_replace.old_filter_type !=
7917 filter_replace.new_filter_type)
7918 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7919 " original: 0x%x, new: 0x%x",
7921 filter_replace.old_filter_type,
7922 filter_replace.new_filter_type);
7925 memset(&filter_replace, 0,
7926 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7927 memset(&filter_replace_buf, 0,
7928 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7929 /* create L1 filter */
7930 filter_replace.old_filter_type =
7931 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7932 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7933 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7934 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7935 /* Prepare the buffer, 2 entries */
7936 filter_replace_buf.data[0] =
7937 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7938 filter_replace_buf.data[0] |=
7939 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7940 filter_replace_buf.data[2] = 0xFF;
7941 filter_replace_buf.data[3] = 0xFF;
7942 filter_replace_buf.data[4] =
7943 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7944 filter_replace_buf.data[4] |=
7945 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7946 filter_replace_buf.data[6] = 0xFF;
7947 filter_replace_buf.data[7] = 0xFF;
7949 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7950 &filter_replace_buf);
7951 if (!status && (filter_replace.old_filter_type !=
7952 filter_replace.new_filter_type))
7953 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7954 " original: 0x%x, new: 0x%x",
7956 filter_replace.old_filter_type,
7957 filter_replace.new_filter_type);
7963 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7965 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7966 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7967 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7968 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7969 enum i40e_status_code status = I40E_SUCCESS;
7971 if (pf->support_multi_driver) {
7972 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7973 return I40E_NOT_SUPPORTED;
7977 memset(&filter_replace, 0,
7978 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7979 memset(&filter_replace_buf, 0,
7980 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7981 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7982 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7983 filter_replace.new_filter_type =
7984 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7985 /* Prepare the buffer, 2 entries */
7986 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7987 filter_replace_buf.data[0] |=
7988 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7989 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7990 filter_replace_buf.data[4] |=
7991 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7992 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7993 &filter_replace_buf);
7996 if (filter_replace.old_filter_type !=
7997 filter_replace.new_filter_type)
7998 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7999 " original: 0x%x, new: 0x%x",
8001 filter_replace.old_filter_type,
8002 filter_replace.new_filter_type);
8005 memset(&filter_replace, 0,
8006 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8007 memset(&filter_replace_buf, 0,
8008 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8009 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8010 filter_replace.old_filter_type =
8011 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8012 filter_replace.new_filter_type =
8013 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8014 /* Prepare the buffer, 2 entries */
8015 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8016 filter_replace_buf.data[0] |=
8017 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8018 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8019 filter_replace_buf.data[4] |=
8020 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8022 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8023 &filter_replace_buf);
8024 if (!status && (filter_replace.old_filter_type !=
8025 filter_replace.new_filter_type))
8026 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8027 " original: 0x%x, new: 0x%x",
8029 filter_replace.old_filter_type,
8030 filter_replace.new_filter_type);
8036 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8037 struct i40e_tunnel_filter_conf *tunnel_filter,
8041 uint32_t ipv4_addr, ipv4_addr_le;
8042 uint8_t i, tun_type = 0;
8043 /* internal variable to convert ipv6 byte order */
8044 uint32_t convert_ipv6[4];
8046 struct i40e_pf_vf *vf = NULL;
8047 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8048 struct i40e_vsi *vsi;
8049 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8050 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8051 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8052 struct i40e_tunnel_filter *tunnel, *node;
8053 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8055 bool big_buffer = 0;
8057 cld_filter = rte_zmalloc("tunnel_filter",
8058 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8061 if (cld_filter == NULL) {
8062 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8065 pfilter = cld_filter;
8067 ether_addr_copy(&tunnel_filter->outer_mac,
8068 (struct ether_addr *)&pfilter->element.outer_mac);
8069 ether_addr_copy(&tunnel_filter->inner_mac,
8070 (struct ether_addr *)&pfilter->element.inner_mac);
8072 pfilter->element.inner_vlan =
8073 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8074 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8075 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8076 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8077 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8078 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8080 sizeof(pfilter->element.ipaddr.v4.data));
8082 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8083 for (i = 0; i < 4; i++) {
8085 rte_cpu_to_le_32(rte_be_to_cpu_32(
8086 tunnel_filter->ip_addr.ipv6_addr[i]));
8088 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8090 sizeof(pfilter->element.ipaddr.v6.data));
8093 /* check tunneled type */
8094 switch (tunnel_filter->tunnel_type) {
8095 case I40E_TUNNEL_TYPE_VXLAN:
8096 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8098 case I40E_TUNNEL_TYPE_NVGRE:
8099 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8101 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8102 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8104 case I40E_TUNNEL_TYPE_MPLSoUDP:
8105 if (!pf->mpls_replace_flag) {
8106 i40e_replace_mpls_l1_filter(pf);
8107 i40e_replace_mpls_cloud_filter(pf);
8108 pf->mpls_replace_flag = 1;
8110 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8111 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8113 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8114 (teid_le & 0xF) << 12;
8115 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8118 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8120 case I40E_TUNNEL_TYPE_MPLSoGRE:
8121 if (!pf->mpls_replace_flag) {
8122 i40e_replace_mpls_l1_filter(pf);
8123 i40e_replace_mpls_cloud_filter(pf);
8124 pf->mpls_replace_flag = 1;
8126 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8127 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8129 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8130 (teid_le & 0xF) << 12;
8131 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8134 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8136 case I40E_TUNNEL_TYPE_GTPC:
8137 if (!pf->gtp_replace_flag) {
8138 i40e_replace_gtp_l1_filter(pf);
8139 i40e_replace_gtp_cloud_filter(pf);
8140 pf->gtp_replace_flag = 1;
8142 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8143 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8144 (teid_le >> 16) & 0xFFFF;
8145 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8147 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8151 case I40E_TUNNEL_TYPE_GTPU:
8152 if (!pf->gtp_replace_flag) {
8153 i40e_replace_gtp_l1_filter(pf);
8154 i40e_replace_gtp_cloud_filter(pf);
8155 pf->gtp_replace_flag = 1;
8157 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8158 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8159 (teid_le >> 16) & 0xFFFF;
8160 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8162 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8166 case I40E_TUNNEL_TYPE_QINQ:
8167 if (!pf->qinq_replace_flag) {
8168 ret = i40e_cloud_filter_qinq_create(pf);
8171 "QinQ tunnel filter already created.");
8172 pf->qinq_replace_flag = 1;
8174 /* Add in the General fields the values of
8175 * the Outer and Inner VLAN
8176 * Big Buffer should be set, see changes in
8177 * i40e_aq_add_cloud_filters
8179 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8180 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8184 /* Other tunnel types is not supported. */
8185 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8186 rte_free(cld_filter);
8190 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8191 pfilter->element.flags =
8192 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8193 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8194 pfilter->element.flags =
8195 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8196 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8197 pfilter->element.flags =
8198 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8199 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8200 pfilter->element.flags =
8201 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8202 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8203 pfilter->element.flags |=
8204 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8206 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8207 &pfilter->element.flags);
8209 rte_free(cld_filter);
8214 pfilter->element.flags |= rte_cpu_to_le_16(
8215 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8216 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8217 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8218 pfilter->element.queue_number =
8219 rte_cpu_to_le_16(tunnel_filter->queue_id);
8221 if (!tunnel_filter->is_to_vf)
8224 if (tunnel_filter->vf_id >= pf->vf_num) {
8225 PMD_DRV_LOG(ERR, "Invalid argument.");
8226 rte_free(cld_filter);
8229 vf = &pf->vfs[tunnel_filter->vf_id];
8233 /* Check if there is the filter in SW list */
8234 memset(&check_filter, 0, sizeof(check_filter));
8235 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8236 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8237 check_filter.vf_id = tunnel_filter->vf_id;
8238 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8240 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8241 rte_free(cld_filter);
8245 if (!add && !node) {
8246 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8247 rte_free(cld_filter);
8253 ret = i40e_aq_add_cloud_filters_bb(hw,
8254 vsi->seid, cld_filter, 1);
8256 ret = i40e_aq_add_cloud_filters(hw,
8257 vsi->seid, &cld_filter->element, 1);
8259 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8260 rte_free(cld_filter);
8263 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8264 if (tunnel == NULL) {
8265 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8266 rte_free(cld_filter);
8270 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8271 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8276 ret = i40e_aq_rem_cloud_filters_bb(
8277 hw, vsi->seid, cld_filter, 1);
8279 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8280 &cld_filter->element, 1);
8282 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8283 rte_free(cld_filter);
8286 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8289 rte_free(cld_filter);
8294 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8298 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8299 if (pf->vxlan_ports[i] == port)
8307 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8311 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8313 idx = i40e_get_vxlan_port_idx(pf, port);
8315 /* Check if port already exists */
8317 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8321 /* Now check if there is space to add the new port */
8322 idx = i40e_get_vxlan_port_idx(pf, 0);
8325 "Maximum number of UDP ports reached, not adding port %d",
8330 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8333 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8337 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8340 /* New port: add it and mark its index in the bitmap */
8341 pf->vxlan_ports[idx] = port;
8342 pf->vxlan_bitmap |= (1 << idx);
8344 if (!(pf->flags & I40E_FLAG_VXLAN))
8345 pf->flags |= I40E_FLAG_VXLAN;
8351 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8354 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8356 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8357 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8361 idx = i40e_get_vxlan_port_idx(pf, port);
8364 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8368 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8369 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8373 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8376 pf->vxlan_ports[idx] = 0;
8377 pf->vxlan_bitmap &= ~(1 << idx);
8379 if (!pf->vxlan_bitmap)
8380 pf->flags &= ~I40E_FLAG_VXLAN;
8385 /* Add UDP tunneling port */
8387 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8388 struct rte_eth_udp_tunnel *udp_tunnel)
8391 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8393 if (udp_tunnel == NULL)
8396 switch (udp_tunnel->prot_type) {
8397 case RTE_TUNNEL_TYPE_VXLAN:
8398 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8401 case RTE_TUNNEL_TYPE_GENEVE:
8402 case RTE_TUNNEL_TYPE_TEREDO:
8403 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8408 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8416 /* Remove UDP tunneling port */
8418 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8419 struct rte_eth_udp_tunnel *udp_tunnel)
8422 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8424 if (udp_tunnel == NULL)
8427 switch (udp_tunnel->prot_type) {
8428 case RTE_TUNNEL_TYPE_VXLAN:
8429 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8431 case RTE_TUNNEL_TYPE_GENEVE:
8432 case RTE_TUNNEL_TYPE_TEREDO:
8433 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8437 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8445 /* Calculate the maximum number of contiguous PF queues that are configured */
8447 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8449 struct rte_eth_dev_data *data = pf->dev_data;
8451 struct i40e_rx_queue *rxq;
8454 for (i = 0; i < pf->lan_nb_qps; i++) {
8455 rxq = data->rx_queues[i];
8456 if (rxq && rxq->q_set)
8467 i40e_pf_config_rss(struct i40e_pf *pf)
8469 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8470 struct rte_eth_rss_conf rss_conf;
8471 uint32_t i, lut = 0;
8475 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8476 * It's necessary to calculate the actual PF queues that are configured.
8478 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8479 num = i40e_pf_calc_configured_queues_num(pf);
8481 num = pf->dev_data->nb_rx_queues;
8483 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8484 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8488 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8492 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8495 lut = (lut << 8) | (j & ((0x1 <<
8496 hw->func_caps.rss_table_entry_width) - 1));
8498 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8501 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8502 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8503 i40e_pf_disable_rss(pf);
8506 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8507 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8508 /* Random default keys */
8509 static uint32_t rss_key_default[] = {0x6b793944,
8510 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8511 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8512 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8514 rss_conf.rss_key = (uint8_t *)rss_key_default;
8515 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8519 return i40e_hw_rss_hash_set(pf, &rss_conf);
8523 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8524 struct rte_eth_tunnel_filter_conf *filter)
8526 if (pf == NULL || filter == NULL) {
8527 PMD_DRV_LOG(ERR, "Invalid parameter");
8531 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8532 PMD_DRV_LOG(ERR, "Invalid queue ID");
8536 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8537 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8541 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8542 (is_zero_ether_addr(&filter->outer_mac))) {
8543 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8547 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8548 (is_zero_ether_addr(&filter->inner_mac))) {
8549 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8556 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8557 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8559 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8561 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8565 if (pf->support_multi_driver) {
8566 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8570 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8571 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8574 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8575 } else if (len == 4) {
8576 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8578 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8583 ret = i40e_aq_debug_write_global_register(hw,
8584 I40E_GL_PRS_FVBM(2),
8588 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8589 "with value 0x%08x",
8590 I40E_GL_PRS_FVBM(2), reg);
8594 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8595 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8601 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8608 switch (cfg->cfg_type) {
8609 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8610 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8613 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8621 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8622 enum rte_filter_op filter_op,
8625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8626 int ret = I40E_ERR_PARAM;
8628 switch (filter_op) {
8629 case RTE_ETH_FILTER_SET:
8630 ret = i40e_dev_global_config_set(hw,
8631 (struct rte_eth_global_cfg *)arg);
8634 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8642 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8643 enum rte_filter_op filter_op,
8646 struct rte_eth_tunnel_filter_conf *filter;
8647 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8648 int ret = I40E_SUCCESS;
8650 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8652 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8653 return I40E_ERR_PARAM;
8655 switch (filter_op) {
8656 case RTE_ETH_FILTER_NOP:
8657 if (!(pf->flags & I40E_FLAG_VXLAN))
8658 ret = I40E_NOT_SUPPORTED;
8660 case RTE_ETH_FILTER_ADD:
8661 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8663 case RTE_ETH_FILTER_DELETE:
8664 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8667 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8668 ret = I40E_ERR_PARAM;
8676 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8679 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8682 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8683 ret = i40e_pf_config_rss(pf);
8685 i40e_pf_disable_rss(pf);
8690 /* Get the symmetric hash enable configurations per port */
8692 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8694 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8696 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8699 /* Set the symmetric hash enable configurations per port */
8701 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8703 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8706 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8708 "Symmetric hash has already been enabled");
8711 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8713 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8715 "Symmetric hash has already been disabled");
8718 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8720 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8721 I40E_WRITE_FLUSH(hw);
8725 * Get global configurations of hash function type and symmetric hash enable
8726 * per flow type (pctype). Note that global configuration means it affects all
8727 * the ports on the same NIC.
8730 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8731 struct rte_eth_hash_global_conf *g_cfg)
8733 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8737 memset(g_cfg, 0, sizeof(*g_cfg));
8738 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8739 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8740 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8742 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8743 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8744 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8747 * As i40e supports less than 64 flow types, only first 64 bits need to
8750 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8751 g_cfg->valid_bit_mask[i] = 0ULL;
8752 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8755 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8757 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8758 if (!adapter->pctypes_tbl[i])
8760 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8761 j < I40E_FILTER_PCTYPE_MAX; j++) {
8762 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8763 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8764 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8765 g_cfg->sym_hash_enable_mask[0] |=
8776 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8777 const struct rte_eth_hash_global_conf *g_cfg)
8780 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8782 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8783 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8784 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8785 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8791 * As i40e supports less than 64 flow types, only first 64 bits need to
8794 mask0 = g_cfg->valid_bit_mask[0];
8795 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8797 /* Check if any unsupported flow type configured */
8798 if ((mask0 | i40e_mask) ^ i40e_mask)
8801 if (g_cfg->valid_bit_mask[i])
8809 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8815 * Set global configurations of hash function type and symmetric hash enable
8816 * per flow type (pctype). Note any modifying global configuration will affect
8817 * all the ports on the same NIC.
8820 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8821 struct rte_eth_hash_global_conf *g_cfg)
8823 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8824 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8828 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8830 if (pf->support_multi_driver) {
8831 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8835 /* Check the input parameters */
8836 ret = i40e_hash_global_config_check(adapter, g_cfg);
8841 * As i40e supports less than 64 flow types, only first 64 bits need to
8844 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8845 if (mask0 & (1UL << i)) {
8846 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8847 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8849 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8850 j < I40E_FILTER_PCTYPE_MAX; j++) {
8851 if (adapter->pctypes_tbl[i] & (1ULL << j))
8852 i40e_write_global_rx_ctl(hw,
8859 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8860 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8862 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8864 "Hash function already set to Toeplitz");
8867 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8868 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8870 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8872 "Hash function already set to Simple XOR");
8875 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8877 /* Use the default, and keep it as it is */
8880 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8883 I40E_WRITE_FLUSH(hw);
8889 * Valid input sets for hash and flow director filters per PCTYPE
8892 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8893 enum rte_filter_type filter)
8897 static const uint64_t valid_hash_inset_table[] = {
8898 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8899 I40E_INSET_DMAC | I40E_INSET_SMAC |
8900 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8901 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8902 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8903 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8904 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8905 I40E_INSET_FLEX_PAYLOAD,
8906 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8907 I40E_INSET_DMAC | I40E_INSET_SMAC |
8908 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8909 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8910 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8911 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8912 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8913 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8914 I40E_INSET_FLEX_PAYLOAD,
8915 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8916 I40E_INSET_DMAC | I40E_INSET_SMAC |
8917 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8918 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8919 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8920 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8921 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8922 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8923 I40E_INSET_FLEX_PAYLOAD,
8924 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8925 I40E_INSET_DMAC | I40E_INSET_SMAC |
8926 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8927 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8928 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8929 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8930 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8931 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8932 I40E_INSET_FLEX_PAYLOAD,
8933 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8934 I40E_INSET_DMAC | I40E_INSET_SMAC |
8935 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8936 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8937 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8938 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8939 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8940 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8941 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8942 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8943 I40E_INSET_DMAC | I40E_INSET_SMAC |
8944 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8945 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8946 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8947 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8948 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8949 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8950 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8951 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8952 I40E_INSET_DMAC | I40E_INSET_SMAC |
8953 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8954 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8955 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8956 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8957 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8958 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8959 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8960 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8961 I40E_INSET_DMAC | I40E_INSET_SMAC |
8962 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8963 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8964 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8965 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8966 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8967 I40E_INSET_FLEX_PAYLOAD,
8968 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8969 I40E_INSET_DMAC | I40E_INSET_SMAC |
8970 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8971 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8972 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8973 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8974 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8975 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8976 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8977 I40E_INSET_DMAC | I40E_INSET_SMAC |
8978 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8979 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8980 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8981 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8982 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8983 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8984 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8985 I40E_INSET_DMAC | I40E_INSET_SMAC |
8986 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8987 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8988 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8989 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8990 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8991 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8992 I40E_INSET_FLEX_PAYLOAD,
8993 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8994 I40E_INSET_DMAC | I40E_INSET_SMAC |
8995 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8996 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8997 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8998 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8999 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9000 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9001 I40E_INSET_FLEX_PAYLOAD,
9002 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9003 I40E_INSET_DMAC | I40E_INSET_SMAC |
9004 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9005 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9006 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9007 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9008 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9009 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9010 I40E_INSET_FLEX_PAYLOAD,
9011 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9012 I40E_INSET_DMAC | I40E_INSET_SMAC |
9013 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9014 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9015 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9016 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9017 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9018 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9019 I40E_INSET_FLEX_PAYLOAD,
9020 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9021 I40E_INSET_DMAC | I40E_INSET_SMAC |
9022 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9023 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9024 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9025 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9026 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9027 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9028 I40E_INSET_FLEX_PAYLOAD,
9029 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9030 I40E_INSET_DMAC | I40E_INSET_SMAC |
9031 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9032 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9033 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9034 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9035 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9036 I40E_INSET_FLEX_PAYLOAD,
9037 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9038 I40E_INSET_DMAC | I40E_INSET_SMAC |
9039 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9040 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9041 I40E_INSET_FLEX_PAYLOAD,
9045 * Flow director supports only fields defined in
9046 * union rte_eth_fdir_flow.
9048 static const uint64_t valid_fdir_inset_table[] = {
9049 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9051 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9052 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9053 I40E_INSET_IPV4_TTL,
9054 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9055 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9056 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9057 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9058 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9059 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9060 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9061 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9062 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9063 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9064 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9065 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9066 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9067 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9068 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9069 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9070 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9071 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9072 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9073 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9074 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9075 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9076 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9077 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9078 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9079 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9080 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9081 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9082 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9083 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9085 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9086 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9087 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9088 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9089 I40E_INSET_IPV4_TTL,
9090 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9091 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9092 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9093 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9094 I40E_INSET_IPV6_HOP_LIMIT,
9095 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9096 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9097 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9098 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9099 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9100 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9102 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9103 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9104 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9105 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9106 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9107 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9108 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9109 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9110 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9112 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9113 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9114 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9115 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9116 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9117 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9118 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9119 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9120 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9121 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9122 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9123 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9124 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9126 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9127 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9128 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9129 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9130 I40E_INSET_IPV6_HOP_LIMIT,
9131 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9132 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9133 I40E_INSET_LAST_ETHER_TYPE,
9136 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9138 if (filter == RTE_ETH_FILTER_HASH)
9139 valid = valid_hash_inset_table[pctype];
9141 valid = valid_fdir_inset_table[pctype];
9147 * Validate if the input set is allowed for a specific PCTYPE
9150 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9151 enum rte_filter_type filter, uint64_t inset)
9155 valid = i40e_get_valid_input_set(pctype, filter);
9156 if (inset & (~valid))
9162 /* default input set fields combination per pctype */
9164 i40e_get_default_input_set(uint16_t pctype)
9166 static const uint64_t default_inset_table[] = {
9167 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9168 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9169 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9170 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9171 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9172 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9173 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9175 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9176 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9177 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9178 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9179 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9180 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9181 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9182 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9183 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9184 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9188 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9189 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9190 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9191 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9192 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9193 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9194 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9195 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9196 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9198 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9199 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9200 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9201 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9202 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9203 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9204 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9205 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9206 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9207 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9208 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9211 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9212 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9213 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9214 I40E_INSET_LAST_ETHER_TYPE,
9217 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9220 return default_inset_table[pctype];
9224 * Parse the input set from index to logical bit masks
9227 i40e_parse_input_set(uint64_t *inset,
9228 enum i40e_filter_pctype pctype,
9229 enum rte_eth_input_set_field *field,
9235 static const struct {
9236 enum rte_eth_input_set_field field;
9238 } inset_convert_table[] = {
9239 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9240 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9241 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9242 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9243 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9244 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9245 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9246 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9247 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9248 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9249 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9250 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9251 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9252 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9253 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9254 I40E_INSET_IPV6_NEXT_HDR},
9255 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9256 I40E_INSET_IPV6_HOP_LIMIT},
9257 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9258 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9259 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9260 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9261 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9262 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9263 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9264 I40E_INSET_SCTP_VT},
9265 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9266 I40E_INSET_TUNNEL_DMAC},
9267 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9268 I40E_INSET_VLAN_TUNNEL},
9269 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9270 I40E_INSET_TUNNEL_ID},
9271 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9272 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9273 I40E_INSET_FLEX_PAYLOAD_W1},
9274 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9275 I40E_INSET_FLEX_PAYLOAD_W2},
9276 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9277 I40E_INSET_FLEX_PAYLOAD_W3},
9278 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9279 I40E_INSET_FLEX_PAYLOAD_W4},
9280 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9281 I40E_INSET_FLEX_PAYLOAD_W5},
9282 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9283 I40E_INSET_FLEX_PAYLOAD_W6},
9284 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9285 I40E_INSET_FLEX_PAYLOAD_W7},
9286 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9287 I40E_INSET_FLEX_PAYLOAD_W8},
9290 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9293 /* Only one item allowed for default or all */
9295 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9296 *inset = i40e_get_default_input_set(pctype);
9298 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9299 *inset = I40E_INSET_NONE;
9304 for (i = 0, *inset = 0; i < size; i++) {
9305 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9306 if (field[i] == inset_convert_table[j].field) {
9307 *inset |= inset_convert_table[j].inset;
9312 /* It contains unsupported input set, return immediately */
9313 if (j == RTE_DIM(inset_convert_table))
9321 * Translate the input set from bit masks to register aware bit masks
9325 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9335 static const struct inset_map inset_map_common[] = {
9336 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9337 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9338 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9339 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9340 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9341 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9342 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9343 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9344 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9345 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9346 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9347 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9348 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9349 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9350 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9351 {I40E_INSET_TUNNEL_DMAC,
9352 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9353 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9354 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9355 {I40E_INSET_TUNNEL_SRC_PORT,
9356 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9357 {I40E_INSET_TUNNEL_DST_PORT,
9358 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9359 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9360 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9361 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9362 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9363 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9364 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9365 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9366 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9367 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9370 /* some different registers map in x722*/
9371 static const struct inset_map inset_map_diff_x722[] = {
9372 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9373 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9374 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9375 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9378 static const struct inset_map inset_map_diff_not_x722[] = {
9379 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9380 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9381 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9382 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9388 /* Translate input set to register aware inset */
9389 if (type == I40E_MAC_X722) {
9390 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9391 if (input & inset_map_diff_x722[i].inset)
9392 val |= inset_map_diff_x722[i].inset_reg;
9395 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9396 if (input & inset_map_diff_not_x722[i].inset)
9397 val |= inset_map_diff_not_x722[i].inset_reg;
9401 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9402 if (input & inset_map_common[i].inset)
9403 val |= inset_map_common[i].inset_reg;
9410 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9413 uint64_t inset_need_mask = inset;
9415 static const struct {
9418 } inset_mask_map[] = {
9419 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9420 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9421 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9422 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9423 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9424 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9425 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9426 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9429 if (!inset || !mask || !nb_elem)
9432 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9433 /* Clear the inset bit, if no MASK is required,
9434 * for example proto + ttl
9436 if ((inset & inset_mask_map[i].inset) ==
9437 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9438 inset_need_mask &= ~inset_mask_map[i].inset;
9439 if (!inset_need_mask)
9442 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9443 if ((inset_need_mask & inset_mask_map[i].inset) ==
9444 inset_mask_map[i].inset) {
9445 if (idx >= nb_elem) {
9446 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9449 mask[idx] = inset_mask_map[i].mask;
9458 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9460 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9462 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9464 i40e_write_rx_ctl(hw, addr, val);
9465 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9466 (uint32_t)i40e_read_rx_ctl(hw, addr));
9470 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9472 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9473 struct rte_eth_dev *dev;
9475 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9477 i40e_write_rx_ctl(hw, addr, val);
9478 PMD_DRV_LOG(WARNING,
9479 "i40e device %s changed global register [0x%08x]."
9480 " original: 0x%08x, new: 0x%08x",
9481 dev->device->name, addr, reg,
9482 (uint32_t)i40e_read_rx_ctl(hw, addr));
9487 i40e_filter_input_set_init(struct i40e_pf *pf)
9489 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9490 enum i40e_filter_pctype pctype;
9491 uint64_t input_set, inset_reg;
9492 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9496 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9497 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9498 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9500 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9503 input_set = i40e_get_default_input_set(pctype);
9505 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9506 I40E_INSET_MASK_NUM_REG);
9509 if (pf->support_multi_driver && num > 0) {
9510 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9513 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9516 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9517 (uint32_t)(inset_reg & UINT32_MAX));
9518 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9519 (uint32_t)((inset_reg >>
9520 I40E_32_BIT_WIDTH) & UINT32_MAX));
9521 if (!pf->support_multi_driver) {
9522 i40e_check_write_global_reg(hw,
9523 I40E_GLQF_HASH_INSET(0, pctype),
9524 (uint32_t)(inset_reg & UINT32_MAX));
9525 i40e_check_write_global_reg(hw,
9526 I40E_GLQF_HASH_INSET(1, pctype),
9527 (uint32_t)((inset_reg >>
9528 I40E_32_BIT_WIDTH) & UINT32_MAX));
9530 for (i = 0; i < num; i++) {
9531 i40e_check_write_global_reg(hw,
9532 I40E_GLQF_FD_MSK(i, pctype),
9534 i40e_check_write_global_reg(hw,
9535 I40E_GLQF_HASH_MSK(i, pctype),
9538 /*clear unused mask registers of the pctype */
9539 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9540 i40e_check_write_global_reg(hw,
9541 I40E_GLQF_FD_MSK(i, pctype),
9543 i40e_check_write_global_reg(hw,
9544 I40E_GLQF_HASH_MSK(i, pctype),
9548 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9550 I40E_WRITE_FLUSH(hw);
9552 /* store the default input set */
9553 if (!pf->support_multi_driver)
9554 pf->hash_input_set[pctype] = input_set;
9555 pf->fdir.input_set[pctype] = input_set;
9560 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9561 struct rte_eth_input_set_conf *conf)
9563 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9564 enum i40e_filter_pctype pctype;
9565 uint64_t input_set, inset_reg = 0;
9566 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9570 PMD_DRV_LOG(ERR, "Invalid pointer");
9573 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9574 conf->op != RTE_ETH_INPUT_SET_ADD) {
9575 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9579 if (pf->support_multi_driver) {
9580 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9584 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9585 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9586 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9590 if (hw->mac.type == I40E_MAC_X722) {
9591 /* get translated pctype value in fd pctype register */
9592 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9593 I40E_GLQF_FD_PCTYPES((int)pctype));
9596 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9599 PMD_DRV_LOG(ERR, "Failed to parse input set");
9603 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9604 /* get inset value in register */
9605 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9606 inset_reg <<= I40E_32_BIT_WIDTH;
9607 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9608 input_set |= pf->hash_input_set[pctype];
9610 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9611 I40E_INSET_MASK_NUM_REG);
9615 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9617 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9618 (uint32_t)(inset_reg & UINT32_MAX));
9619 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9620 (uint32_t)((inset_reg >>
9621 I40E_32_BIT_WIDTH) & UINT32_MAX));
9623 for (i = 0; i < num; i++)
9624 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9626 /*clear unused mask registers of the pctype */
9627 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9628 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9630 I40E_WRITE_FLUSH(hw);
9632 pf->hash_input_set[pctype] = input_set;
9637 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9638 struct rte_eth_input_set_conf *conf)
9640 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9641 enum i40e_filter_pctype pctype;
9642 uint64_t input_set, inset_reg = 0;
9643 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9647 PMD_DRV_LOG(ERR, "Invalid pointer");
9650 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9651 conf->op != RTE_ETH_INPUT_SET_ADD) {
9652 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9656 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9658 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9659 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9663 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9666 PMD_DRV_LOG(ERR, "Failed to parse input set");
9670 /* get inset value in register */
9671 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9672 inset_reg <<= I40E_32_BIT_WIDTH;
9673 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9675 /* Can not change the inset reg for flex payload for fdir,
9676 * it is done by writing I40E_PRTQF_FD_FLXINSET
9677 * in i40e_set_flex_mask_on_pctype.
9679 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9680 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9682 input_set |= pf->fdir.input_set[pctype];
9683 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9684 I40E_INSET_MASK_NUM_REG);
9687 if (pf->support_multi_driver && num > 0) {
9688 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9692 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9694 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9695 (uint32_t)(inset_reg & UINT32_MAX));
9696 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9697 (uint32_t)((inset_reg >>
9698 I40E_32_BIT_WIDTH) & UINT32_MAX));
9700 if (!pf->support_multi_driver) {
9701 for (i = 0; i < num; i++)
9702 i40e_check_write_global_reg(hw,
9703 I40E_GLQF_FD_MSK(i, pctype),
9705 /*clear unused mask registers of the pctype */
9706 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9707 i40e_check_write_global_reg(hw,
9708 I40E_GLQF_FD_MSK(i, pctype),
9711 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9713 I40E_WRITE_FLUSH(hw);
9715 pf->fdir.input_set[pctype] = input_set;
9720 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9725 PMD_DRV_LOG(ERR, "Invalid pointer");
9729 switch (info->info_type) {
9730 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9731 i40e_get_symmetric_hash_enable_per_port(hw,
9732 &(info->info.enable));
9734 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9735 ret = i40e_get_hash_filter_global_config(hw,
9736 &(info->info.global_conf));
9739 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9749 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9754 PMD_DRV_LOG(ERR, "Invalid pointer");
9758 switch (info->info_type) {
9759 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9760 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9762 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9763 ret = i40e_set_hash_filter_global_config(hw,
9764 &(info->info.global_conf));
9766 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9767 ret = i40e_hash_filter_inset_select(hw,
9768 &(info->info.input_set_conf));
9772 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9781 /* Operations for hash function */
9783 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9784 enum rte_filter_op filter_op,
9787 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9790 switch (filter_op) {
9791 case RTE_ETH_FILTER_NOP:
9793 case RTE_ETH_FILTER_GET:
9794 ret = i40e_hash_filter_get(hw,
9795 (struct rte_eth_hash_filter_info *)arg);
9797 case RTE_ETH_FILTER_SET:
9798 ret = i40e_hash_filter_set(hw,
9799 (struct rte_eth_hash_filter_info *)arg);
9802 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9811 /* Convert ethertype filter structure */
9813 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9814 struct i40e_ethertype_filter *filter)
9816 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9817 filter->input.ether_type = input->ether_type;
9818 filter->flags = input->flags;
9819 filter->queue = input->queue;
9824 /* Check if there exists the ehtertype filter */
9825 struct i40e_ethertype_filter *
9826 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9827 const struct i40e_ethertype_filter_input *input)
9831 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9835 return ethertype_rule->hash_map[ret];
9838 /* Add ethertype filter in SW list */
9840 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9841 struct i40e_ethertype_filter *filter)
9843 struct i40e_ethertype_rule *rule = &pf->ethertype;
9846 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9849 "Failed to insert ethertype filter"
9850 " to hash table %d!",
9854 rule->hash_map[ret] = filter;
9856 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9861 /* Delete ethertype filter in SW list */
9863 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9864 struct i40e_ethertype_filter_input *input)
9866 struct i40e_ethertype_rule *rule = &pf->ethertype;
9867 struct i40e_ethertype_filter *filter;
9870 ret = rte_hash_del_key(rule->hash_table, input);
9873 "Failed to delete ethertype filter"
9874 " to hash table %d!",
9878 filter = rule->hash_map[ret];
9879 rule->hash_map[ret] = NULL;
9881 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9888 * Configure ethertype filter, which can director packet by filtering
9889 * with mac address and ether_type or only ether_type
9892 i40e_ethertype_filter_set(struct i40e_pf *pf,
9893 struct rte_eth_ethertype_filter *filter,
9896 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9897 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9898 struct i40e_ethertype_filter *ethertype_filter, *node;
9899 struct i40e_ethertype_filter check_filter;
9900 struct i40e_control_filter_stats stats;
9904 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9905 PMD_DRV_LOG(ERR, "Invalid queue ID");
9908 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9909 filter->ether_type == ETHER_TYPE_IPv6) {
9911 "unsupported ether_type(0x%04x) in control packet filter.",
9912 filter->ether_type);
9915 if (filter->ether_type == ETHER_TYPE_VLAN)
9916 PMD_DRV_LOG(WARNING,
9917 "filter vlan ether_type in first tag is not supported.");
9919 /* Check if there is the filter in SW list */
9920 memset(&check_filter, 0, sizeof(check_filter));
9921 i40e_ethertype_filter_convert(filter, &check_filter);
9922 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9923 &check_filter.input);
9925 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9929 if (!add && !node) {
9930 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9934 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9935 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9936 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9937 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9938 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9940 memset(&stats, 0, sizeof(stats));
9941 ret = i40e_aq_add_rem_control_packet_filter(hw,
9942 filter->mac_addr.addr_bytes,
9943 filter->ether_type, flags,
9945 filter->queue, add, &stats, NULL);
9948 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9949 ret, stats.mac_etype_used, stats.etype_used,
9950 stats.mac_etype_free, stats.etype_free);
9954 /* Add or delete a filter in SW list */
9956 ethertype_filter = rte_zmalloc("ethertype_filter",
9957 sizeof(*ethertype_filter), 0);
9958 if (ethertype_filter == NULL) {
9959 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9963 rte_memcpy(ethertype_filter, &check_filter,
9964 sizeof(check_filter));
9965 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9967 rte_free(ethertype_filter);
9969 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9976 * Handle operations for ethertype filter.
9979 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9980 enum rte_filter_op filter_op,
9983 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9986 if (filter_op == RTE_ETH_FILTER_NOP)
9990 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9995 switch (filter_op) {
9996 case RTE_ETH_FILTER_ADD:
9997 ret = i40e_ethertype_filter_set(pf,
9998 (struct rte_eth_ethertype_filter *)arg,
10001 case RTE_ETH_FILTER_DELETE:
10002 ret = i40e_ethertype_filter_set(pf,
10003 (struct rte_eth_ethertype_filter *)arg,
10007 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10015 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10016 enum rte_filter_type filter_type,
10017 enum rte_filter_op filter_op,
10025 switch (filter_type) {
10026 case RTE_ETH_FILTER_NONE:
10027 /* For global configuration */
10028 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10030 case RTE_ETH_FILTER_HASH:
10031 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10033 case RTE_ETH_FILTER_MACVLAN:
10034 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10036 case RTE_ETH_FILTER_ETHERTYPE:
10037 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10039 case RTE_ETH_FILTER_TUNNEL:
10040 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10042 case RTE_ETH_FILTER_FDIR:
10043 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10045 case RTE_ETH_FILTER_GENERIC:
10046 if (filter_op != RTE_ETH_FILTER_GET)
10048 *(const void **)arg = &i40e_flow_ops;
10051 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10061 * Check and enable Extended Tag.
10062 * Enabling Extended Tag is important for 40G performance.
10065 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10067 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10071 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10074 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10078 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10079 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10084 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10087 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10091 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10092 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10095 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10096 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10099 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10106 * As some registers wouldn't be reset unless a global hardware reset,
10107 * hardware initialization is needed to put those registers into an
10108 * expected initial state.
10111 i40e_hw_init(struct rte_eth_dev *dev)
10113 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10115 i40e_enable_extended_tag(dev);
10117 /* clear the PF Queue Filter control register */
10118 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10120 /* Disable symmetric hash per port */
10121 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10125 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10126 * however this function will return only one highest pctype index,
10127 * which is not quite correct. This is known problem of i40e driver
10128 * and needs to be fixed later.
10130 enum i40e_filter_pctype
10131 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10134 uint64_t pctype_mask;
10136 if (flow_type < I40E_FLOW_TYPE_MAX) {
10137 pctype_mask = adapter->pctypes_tbl[flow_type];
10138 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10139 if (pctype_mask & (1ULL << i))
10140 return (enum i40e_filter_pctype)i;
10143 return I40E_FILTER_PCTYPE_INVALID;
10147 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10148 enum i40e_filter_pctype pctype)
10151 uint64_t pctype_mask = 1ULL << pctype;
10153 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10155 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10159 return RTE_ETH_FLOW_UNKNOWN;
10163 * On X710, performance number is far from the expectation on recent firmware
10164 * versions; on XL710, performance number is also far from the expectation on
10165 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10166 * mode is enabled and port MAC address is equal to the packet destination MAC
10167 * address. The fix for this issue may not be integrated in the following
10168 * firmware version. So the workaround in software driver is needed. It needs
10169 * to modify the initial values of 3 internal only registers for both X710 and
10170 * XL710. Note that the values for X710 or XL710 could be different, and the
10171 * workaround can be removed when it is fixed in firmware in the future.
10174 /* For both X710 and XL710 */
10175 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10176 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10177 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10179 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10180 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10183 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10184 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10187 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10189 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10190 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10193 * GL_SWR_PM_UP_THR:
10194 * The value is not impacted from the link speed, its value is set according
10195 * to the total number of ports for a better pipe-monitor configuration.
10198 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10200 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10201 .device_id = (dev), \
10202 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10204 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10205 .device_id = (dev), \
10206 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10208 static const struct {
10209 uint16_t device_id;
10211 } swr_pm_table[] = {
10212 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10213 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10214 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10215 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10217 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10218 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10219 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10220 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10221 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10222 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10223 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10227 if (value == NULL) {
10228 PMD_DRV_LOG(ERR, "value is NULL");
10232 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10233 if (hw->device_id == swr_pm_table[i].device_id) {
10234 *value = swr_pm_table[i].val;
10236 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10238 hw->device_id, *value);
10247 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10249 enum i40e_status_code status;
10250 struct i40e_aq_get_phy_abilities_resp phy_ab;
10251 int ret = -ENOTSUP;
10254 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10258 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10261 rte_delay_us(100000);
10263 status = i40e_aq_get_phy_capabilities(hw, false,
10264 true, &phy_ab, NULL);
10272 i40e_configure_registers(struct i40e_hw *hw)
10278 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10279 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10280 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10286 for (i = 0; i < RTE_DIM(reg_table); i++) {
10287 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10288 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10290 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10291 else /* For X710/XL710/XXV710 */
10292 if (hw->aq.fw_maj_ver < 6)
10294 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10297 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10300 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10301 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10303 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10304 else /* For X710/XL710/XXV710 */
10306 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10309 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10312 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10313 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10314 "GL_SWR_PM_UP_THR value fixup",
10319 reg_table[i].val = cfg_val;
10322 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10325 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10326 reg_table[i].addr);
10329 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10330 reg_table[i].addr, reg);
10331 if (reg == reg_table[i].val)
10334 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10335 reg_table[i].val, NULL);
10338 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10339 reg_table[i].val, reg_table[i].addr);
10342 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10343 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10347 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10348 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10349 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10350 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10352 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10357 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10358 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10362 /* Configure for double VLAN RX stripping */
10363 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10364 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10365 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10366 ret = i40e_aq_debug_write_register(hw,
10367 I40E_VSI_TSR(vsi->vsi_id),
10370 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10372 return I40E_ERR_CONFIG;
10376 /* Configure for double VLAN TX insertion */
10377 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10378 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10379 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10380 ret = i40e_aq_debug_write_register(hw,
10381 I40E_VSI_L2TAGSTXVALID(
10382 vsi->vsi_id), reg, NULL);
10385 "Failed to update VSI_L2TAGSTXVALID[%d]",
10387 return I40E_ERR_CONFIG;
10395 * i40e_aq_add_mirror_rule
10396 * @hw: pointer to the hardware structure
10397 * @seid: VEB seid to add mirror rule to
10398 * @dst_id: destination vsi seid
10399 * @entries: Buffer which contains the entities to be mirrored
10400 * @count: number of entities contained in the buffer
10401 * @rule_id:the rule_id of the rule to be added
10403 * Add a mirror rule for a given veb.
10406 static enum i40e_status_code
10407 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10408 uint16_t seid, uint16_t dst_id,
10409 uint16_t rule_type, uint16_t *entries,
10410 uint16_t count, uint16_t *rule_id)
10412 struct i40e_aq_desc desc;
10413 struct i40e_aqc_add_delete_mirror_rule cmd;
10414 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10415 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10418 enum i40e_status_code status;
10420 i40e_fill_default_direct_cmd_desc(&desc,
10421 i40e_aqc_opc_add_mirror_rule);
10422 memset(&cmd, 0, sizeof(cmd));
10424 buff_len = sizeof(uint16_t) * count;
10425 desc.datalen = rte_cpu_to_le_16(buff_len);
10427 desc.flags |= rte_cpu_to_le_16(
10428 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10429 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10430 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10431 cmd.num_entries = rte_cpu_to_le_16(count);
10432 cmd.seid = rte_cpu_to_le_16(seid);
10433 cmd.destination = rte_cpu_to_le_16(dst_id);
10435 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10436 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10438 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10439 hw->aq.asq_last_status, resp->rule_id,
10440 resp->mirror_rules_used, resp->mirror_rules_free);
10441 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10447 * i40e_aq_del_mirror_rule
10448 * @hw: pointer to the hardware structure
10449 * @seid: VEB seid to add mirror rule to
10450 * @entries: Buffer which contains the entities to be mirrored
10451 * @count: number of entities contained in the buffer
10452 * @rule_id:the rule_id of the rule to be delete
10454 * Delete a mirror rule for a given veb.
10457 static enum i40e_status_code
10458 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10459 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10460 uint16_t count, uint16_t rule_id)
10462 struct i40e_aq_desc desc;
10463 struct i40e_aqc_add_delete_mirror_rule cmd;
10464 uint16_t buff_len = 0;
10465 enum i40e_status_code status;
10468 i40e_fill_default_direct_cmd_desc(&desc,
10469 i40e_aqc_opc_delete_mirror_rule);
10470 memset(&cmd, 0, sizeof(cmd));
10471 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10472 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10474 cmd.num_entries = count;
10475 buff_len = sizeof(uint16_t) * count;
10476 desc.datalen = rte_cpu_to_le_16(buff_len);
10477 buff = (void *)entries;
10479 /* rule id is filled in destination field for deleting mirror rule */
10480 cmd.destination = rte_cpu_to_le_16(rule_id);
10482 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10483 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10484 cmd.seid = rte_cpu_to_le_16(seid);
10486 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10487 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10493 * i40e_mirror_rule_set
10494 * @dev: pointer to the hardware structure
10495 * @mirror_conf: mirror rule info
10496 * @sw_id: mirror rule's sw_id
10497 * @on: enable/disable
10499 * set a mirror rule.
10503 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10504 struct rte_eth_mirror_conf *mirror_conf,
10505 uint8_t sw_id, uint8_t on)
10507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10508 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10509 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10510 struct i40e_mirror_rule *parent = NULL;
10511 uint16_t seid, dst_seid, rule_id;
10515 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10517 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10519 "mirror rule can not be configured without veb or vfs.");
10522 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10523 PMD_DRV_LOG(ERR, "mirror table is full.");
10526 if (mirror_conf->dst_pool > pf->vf_num) {
10527 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10528 mirror_conf->dst_pool);
10532 seid = pf->main_vsi->veb->seid;
10534 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10535 if (sw_id <= it->index) {
10541 if (mirr_rule && sw_id == mirr_rule->index) {
10543 PMD_DRV_LOG(ERR, "mirror rule exists.");
10546 ret = i40e_aq_del_mirror_rule(hw, seid,
10547 mirr_rule->rule_type,
10548 mirr_rule->entries,
10549 mirr_rule->num_entries, mirr_rule->id);
10552 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10553 ret, hw->aq.asq_last_status);
10556 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10557 rte_free(mirr_rule);
10558 pf->nb_mirror_rule--;
10562 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10566 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10567 sizeof(struct i40e_mirror_rule) , 0);
10569 PMD_DRV_LOG(ERR, "failed to allocate memory");
10570 return I40E_ERR_NO_MEMORY;
10572 switch (mirror_conf->rule_type) {
10573 case ETH_MIRROR_VLAN:
10574 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10575 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10576 mirr_rule->entries[j] =
10577 mirror_conf->vlan.vlan_id[i];
10582 PMD_DRV_LOG(ERR, "vlan is not specified.");
10583 rte_free(mirr_rule);
10586 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10588 case ETH_MIRROR_VIRTUAL_POOL_UP:
10589 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10590 /* check if the specified pool bit is out of range */
10591 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10592 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10593 rte_free(mirr_rule);
10596 for (i = 0, j = 0; i < pf->vf_num; i++) {
10597 if (mirror_conf->pool_mask & (1ULL << i)) {
10598 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10602 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10603 /* add pf vsi to entries */
10604 mirr_rule->entries[j] = pf->main_vsi_seid;
10608 PMD_DRV_LOG(ERR, "pool is not specified.");
10609 rte_free(mirr_rule);
10612 /* egress and ingress in aq commands means from switch but not port */
10613 mirr_rule->rule_type =
10614 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10615 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10616 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10618 case ETH_MIRROR_UPLINK_PORT:
10619 /* egress and ingress in aq commands means from switch but not port*/
10620 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10622 case ETH_MIRROR_DOWNLINK_PORT:
10623 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10626 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10627 mirror_conf->rule_type);
10628 rte_free(mirr_rule);
10632 /* If the dst_pool is equal to vf_num, consider it as PF */
10633 if (mirror_conf->dst_pool == pf->vf_num)
10634 dst_seid = pf->main_vsi_seid;
10636 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10638 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10639 mirr_rule->rule_type, mirr_rule->entries,
10643 "failed to add mirror rule: ret = %d, aq_err = %d.",
10644 ret, hw->aq.asq_last_status);
10645 rte_free(mirr_rule);
10649 mirr_rule->index = sw_id;
10650 mirr_rule->num_entries = j;
10651 mirr_rule->id = rule_id;
10652 mirr_rule->dst_vsi_seid = dst_seid;
10655 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10657 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10659 pf->nb_mirror_rule++;
10664 * i40e_mirror_rule_reset
10665 * @dev: pointer to the device
10666 * @sw_id: mirror rule's sw_id
10668 * reset a mirror rule.
10672 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10674 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10676 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10680 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10682 seid = pf->main_vsi->veb->seid;
10684 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10685 if (sw_id == it->index) {
10691 ret = i40e_aq_del_mirror_rule(hw, seid,
10692 mirr_rule->rule_type,
10693 mirr_rule->entries,
10694 mirr_rule->num_entries, mirr_rule->id);
10697 "failed to remove mirror rule: status = %d, aq_err = %d.",
10698 ret, hw->aq.asq_last_status);
10701 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10702 rte_free(mirr_rule);
10703 pf->nb_mirror_rule--;
10705 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10712 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10715 uint64_t systim_cycles;
10717 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10718 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10721 return systim_cycles;
10725 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10727 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10728 uint64_t rx_tstamp;
10730 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10731 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10738 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10740 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10741 uint64_t tx_tstamp;
10743 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10744 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10751 i40e_start_timecounters(struct rte_eth_dev *dev)
10753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10754 struct i40e_adapter *adapter =
10755 (struct i40e_adapter *)dev->data->dev_private;
10756 struct rte_eth_link link;
10757 uint32_t tsync_inc_l;
10758 uint32_t tsync_inc_h;
10760 /* Get current link speed. */
10761 i40e_dev_link_update(dev, 1);
10762 rte_eth_linkstatus_get(dev, &link);
10764 switch (link.link_speed) {
10765 case ETH_SPEED_NUM_40G:
10766 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10767 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10769 case ETH_SPEED_NUM_10G:
10770 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10771 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10773 case ETH_SPEED_NUM_1G:
10774 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10775 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10782 /* Set the timesync increment value. */
10783 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10784 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10786 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10787 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10788 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10790 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10791 adapter->systime_tc.cc_shift = 0;
10792 adapter->systime_tc.nsec_mask = 0;
10794 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10795 adapter->rx_tstamp_tc.cc_shift = 0;
10796 adapter->rx_tstamp_tc.nsec_mask = 0;
10798 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10799 adapter->tx_tstamp_tc.cc_shift = 0;
10800 adapter->tx_tstamp_tc.nsec_mask = 0;
10804 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10806 struct i40e_adapter *adapter =
10807 (struct i40e_adapter *)dev->data->dev_private;
10809 adapter->systime_tc.nsec += delta;
10810 adapter->rx_tstamp_tc.nsec += delta;
10811 adapter->tx_tstamp_tc.nsec += delta;
10817 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10820 struct i40e_adapter *adapter =
10821 (struct i40e_adapter *)dev->data->dev_private;
10823 ns = rte_timespec_to_ns(ts);
10825 /* Set the timecounters to a new value. */
10826 adapter->systime_tc.nsec = ns;
10827 adapter->rx_tstamp_tc.nsec = ns;
10828 adapter->tx_tstamp_tc.nsec = ns;
10834 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10836 uint64_t ns, systime_cycles;
10837 struct i40e_adapter *adapter =
10838 (struct i40e_adapter *)dev->data->dev_private;
10840 systime_cycles = i40e_read_systime_cyclecounter(dev);
10841 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10842 *ts = rte_ns_to_timespec(ns);
10848 i40e_timesync_enable(struct rte_eth_dev *dev)
10850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10851 uint32_t tsync_ctl_l;
10852 uint32_t tsync_ctl_h;
10854 /* Stop the timesync system time. */
10855 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10856 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10857 /* Reset the timesync system time value. */
10858 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10859 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10861 i40e_start_timecounters(dev);
10863 /* Clear timesync registers. */
10864 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10865 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10866 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10867 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10868 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10869 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10871 /* Enable timestamping of PTP packets. */
10872 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10873 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10875 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10876 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10877 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10879 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10880 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10886 i40e_timesync_disable(struct rte_eth_dev *dev)
10888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10889 uint32_t tsync_ctl_l;
10890 uint32_t tsync_ctl_h;
10892 /* Disable timestamping of transmitted PTP packets. */
10893 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10894 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10896 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10897 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10899 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10900 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10902 /* Reset the timesync increment value. */
10903 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10904 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10910 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10911 struct timespec *timestamp, uint32_t flags)
10913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10914 struct i40e_adapter *adapter =
10915 (struct i40e_adapter *)dev->data->dev_private;
10917 uint32_t sync_status;
10918 uint32_t index = flags & 0x03;
10919 uint64_t rx_tstamp_cycles;
10922 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10923 if ((sync_status & (1 << index)) == 0)
10926 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10927 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10928 *timestamp = rte_ns_to_timespec(ns);
10934 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10935 struct timespec *timestamp)
10937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10938 struct i40e_adapter *adapter =
10939 (struct i40e_adapter *)dev->data->dev_private;
10941 uint32_t sync_status;
10942 uint64_t tx_tstamp_cycles;
10945 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10946 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10949 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10950 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10951 *timestamp = rte_ns_to_timespec(ns);
10957 * i40e_parse_dcb_configure - parse dcb configure from user
10958 * @dev: the device being configured
10959 * @dcb_cfg: pointer of the result of parse
10960 * @*tc_map: bit map of enabled traffic classes
10962 * Returns 0 on success, negative value on failure
10965 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10966 struct i40e_dcbx_config *dcb_cfg,
10969 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10970 uint8_t i, tc_bw, bw_lf;
10972 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10974 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10975 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10976 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10980 /* assume each tc has the same bw */
10981 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10982 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10983 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10984 /* to ensure the sum of tcbw is equal to 100 */
10985 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10986 for (i = 0; i < bw_lf; i++)
10987 dcb_cfg->etscfg.tcbwtable[i]++;
10989 /* assume each tc has the same Transmission Selection Algorithm */
10990 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10991 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10993 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10994 dcb_cfg->etscfg.prioritytable[i] =
10995 dcb_rx_conf->dcb_tc[i];
10997 /* FW needs one App to configure HW */
10998 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10999 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11000 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11001 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11003 if (dcb_rx_conf->nb_tcs == 0)
11004 *tc_map = 1; /* tc0 only */
11006 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11008 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11009 dcb_cfg->pfc.willing = 0;
11010 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11011 dcb_cfg->pfc.pfcenable = *tc_map;
11017 static enum i40e_status_code
11018 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11019 struct i40e_aqc_vsi_properties_data *info,
11020 uint8_t enabled_tcmap)
11022 enum i40e_status_code ret;
11023 int i, total_tc = 0;
11024 uint16_t qpnum_per_tc, bsf, qp_idx;
11025 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11026 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11027 uint16_t used_queues;
11029 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11030 if (ret != I40E_SUCCESS)
11033 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11034 if (enabled_tcmap & (1 << i))
11039 vsi->enabled_tc = enabled_tcmap;
11041 /* different VSI has different queues assigned */
11042 if (vsi->type == I40E_VSI_MAIN)
11043 used_queues = dev_data->nb_rx_queues -
11044 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11045 else if (vsi->type == I40E_VSI_VMDQ2)
11046 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11048 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11049 return I40E_ERR_NO_AVAILABLE_VSI;
11052 qpnum_per_tc = used_queues / total_tc;
11053 /* Number of queues per enabled TC */
11054 if (qpnum_per_tc == 0) {
11055 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11056 return I40E_ERR_INVALID_QP_ID;
11058 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11059 I40E_MAX_Q_PER_TC);
11060 bsf = rte_bsf32(qpnum_per_tc);
11063 * Configure TC and queue mapping parameters, for enabled TC,
11064 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11065 * default queue will serve it.
11068 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11069 if (vsi->enabled_tc & (1 << i)) {
11070 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11071 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11072 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11073 qp_idx += qpnum_per_tc;
11075 info->tc_mapping[i] = 0;
11078 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11079 if (vsi->type == I40E_VSI_SRIOV) {
11080 info->mapping_flags |=
11081 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11082 for (i = 0; i < vsi->nb_qps; i++)
11083 info->queue_mapping[i] =
11084 rte_cpu_to_le_16(vsi->base_queue + i);
11086 info->mapping_flags |=
11087 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11088 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11090 info->valid_sections |=
11091 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11093 return I40E_SUCCESS;
11097 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11098 * @veb: VEB to be configured
11099 * @tc_map: enabled TC bitmap
11101 * Returns 0 on success, negative value on failure
11103 static enum i40e_status_code
11104 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11106 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11107 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11108 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11109 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11110 enum i40e_status_code ret = I40E_SUCCESS;
11114 /* Check if enabled_tc is same as existing or new TCs */
11115 if (veb->enabled_tc == tc_map)
11118 /* configure tc bandwidth */
11119 memset(&veb_bw, 0, sizeof(veb_bw));
11120 veb_bw.tc_valid_bits = tc_map;
11121 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11122 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11123 if (tc_map & BIT_ULL(i))
11124 veb_bw.tc_bw_share_credits[i] = 1;
11126 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11130 "AQ command Config switch_comp BW allocation per TC failed = %d",
11131 hw->aq.asq_last_status);
11135 memset(&ets_query, 0, sizeof(ets_query));
11136 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11138 if (ret != I40E_SUCCESS) {
11140 "Failed to get switch_comp ETS configuration %u",
11141 hw->aq.asq_last_status);
11144 memset(&bw_query, 0, sizeof(bw_query));
11145 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11147 if (ret != I40E_SUCCESS) {
11149 "Failed to get switch_comp bandwidth configuration %u",
11150 hw->aq.asq_last_status);
11154 /* store and print out BW info */
11155 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11156 veb->bw_info.bw_max = ets_query.tc_bw_max;
11157 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11158 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11159 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11160 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11161 I40E_16_BIT_WIDTH);
11162 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11163 veb->bw_info.bw_ets_share_credits[i] =
11164 bw_query.tc_bw_share_credits[i];
11165 veb->bw_info.bw_ets_credits[i] =
11166 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11167 /* 4 bits per TC, 4th bit is reserved */
11168 veb->bw_info.bw_ets_max[i] =
11169 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11170 RTE_LEN2MASK(3, uint8_t));
11171 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11172 veb->bw_info.bw_ets_share_credits[i]);
11173 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11174 veb->bw_info.bw_ets_credits[i]);
11175 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11176 veb->bw_info.bw_ets_max[i]);
11179 veb->enabled_tc = tc_map;
11186 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11187 * @vsi: VSI to be configured
11188 * @tc_map: enabled TC bitmap
11190 * Returns 0 on success, negative value on failure
11192 static enum i40e_status_code
11193 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11195 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11196 struct i40e_vsi_context ctxt;
11197 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11198 enum i40e_status_code ret = I40E_SUCCESS;
11201 /* Check if enabled_tc is same as existing or new TCs */
11202 if (vsi->enabled_tc == tc_map)
11205 /* configure tc bandwidth */
11206 memset(&bw_data, 0, sizeof(bw_data));
11207 bw_data.tc_valid_bits = tc_map;
11208 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11209 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11210 if (tc_map & BIT_ULL(i))
11211 bw_data.tc_bw_credits[i] = 1;
11213 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11216 "AQ command Config VSI BW allocation per TC failed = %d",
11217 hw->aq.asq_last_status);
11220 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11221 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11223 /* Update Queue Pairs Mapping for currently enabled UPs */
11224 ctxt.seid = vsi->seid;
11225 ctxt.pf_num = hw->pf_id;
11227 ctxt.uplink_seid = vsi->uplink_seid;
11228 ctxt.info = vsi->info;
11230 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11234 /* Update the VSI after updating the VSI queue-mapping information */
11235 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11237 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11238 hw->aq.asq_last_status);
11241 /* update the local VSI info with updated queue map */
11242 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11243 sizeof(vsi->info.tc_mapping));
11244 rte_memcpy(&vsi->info.queue_mapping,
11245 &ctxt.info.queue_mapping,
11246 sizeof(vsi->info.queue_mapping));
11247 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11248 vsi->info.valid_sections = 0;
11250 /* query and update current VSI BW information */
11251 ret = i40e_vsi_get_bw_config(vsi);
11254 "Failed updating vsi bw info, err %s aq_err %s",
11255 i40e_stat_str(hw, ret),
11256 i40e_aq_str(hw, hw->aq.asq_last_status));
11260 vsi->enabled_tc = tc_map;
11267 * i40e_dcb_hw_configure - program the dcb setting to hw
11268 * @pf: pf the configuration is taken on
11269 * @new_cfg: new configuration
11270 * @tc_map: enabled TC bitmap
11272 * Returns 0 on success, negative value on failure
11274 static enum i40e_status_code
11275 i40e_dcb_hw_configure(struct i40e_pf *pf,
11276 struct i40e_dcbx_config *new_cfg,
11279 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11280 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11281 struct i40e_vsi *main_vsi = pf->main_vsi;
11282 struct i40e_vsi_list *vsi_list;
11283 enum i40e_status_code ret;
11287 /* Use the FW API if FW > v4.4*/
11288 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11289 (hw->aq.fw_maj_ver >= 5))) {
11291 "FW < v4.4, can not use FW LLDP API to configure DCB");
11292 return I40E_ERR_FIRMWARE_API_VERSION;
11295 /* Check if need reconfiguration */
11296 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11297 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11298 return I40E_SUCCESS;
11301 /* Copy the new config to the current config */
11302 *old_cfg = *new_cfg;
11303 old_cfg->etsrec = old_cfg->etscfg;
11304 ret = i40e_set_dcb_config(hw);
11306 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11307 i40e_stat_str(hw, ret),
11308 i40e_aq_str(hw, hw->aq.asq_last_status));
11311 /* set receive Arbiter to RR mode and ETS scheme by default */
11312 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11313 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11314 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11315 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11316 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11317 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11318 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11319 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11320 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11321 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11322 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11323 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11324 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11326 /* get local mib to check whether it is configured correctly */
11328 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11329 /* Get Local DCB Config */
11330 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11331 &hw->local_dcbx_config);
11333 /* if Veb is created, need to update TC of it at first */
11334 if (main_vsi->veb) {
11335 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11337 PMD_INIT_LOG(WARNING,
11338 "Failed configuring TC for VEB seid=%d",
11339 main_vsi->veb->seid);
11341 /* Update each VSI */
11342 i40e_vsi_config_tc(main_vsi, tc_map);
11343 if (main_vsi->veb) {
11344 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11345 /* Beside main VSI and VMDQ VSIs, only enable default
11346 * TC for other VSIs
11348 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11349 ret = i40e_vsi_config_tc(vsi_list->vsi,
11352 ret = i40e_vsi_config_tc(vsi_list->vsi,
11353 I40E_DEFAULT_TCMAP);
11355 PMD_INIT_LOG(WARNING,
11356 "Failed configuring TC for VSI seid=%d",
11357 vsi_list->vsi->seid);
11361 return I40E_SUCCESS;
11365 * i40e_dcb_init_configure - initial dcb config
11366 * @dev: device being configured
11367 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11369 * Returns 0 on success, negative value on failure
11372 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11374 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11375 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11378 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11379 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11383 /* DCB initialization:
11384 * Update DCB configuration from the Firmware and configure
11385 * LLDP MIB change event.
11387 if (sw_dcb == TRUE) {
11388 /* When using NVM 6.01 or later, the RX data path does
11389 * not hang if the FW LLDP is stopped.
11391 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11392 ((hw->nvm.version >> 4) & 0xff) >= 1) {
11393 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11394 if (ret != I40E_SUCCESS)
11395 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11398 ret = i40e_init_dcb(hw);
11399 /* If lldp agent is stopped, the return value from
11400 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11401 * adminq status. Otherwise, it should return success.
11403 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11404 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11405 memset(&hw->local_dcbx_config, 0,
11406 sizeof(struct i40e_dcbx_config));
11407 /* set dcb default configuration */
11408 hw->local_dcbx_config.etscfg.willing = 0;
11409 hw->local_dcbx_config.etscfg.maxtcs = 0;
11410 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11411 hw->local_dcbx_config.etscfg.tsatable[0] =
11413 /* all UPs mapping to TC0 */
11414 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11415 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11416 hw->local_dcbx_config.etsrec =
11417 hw->local_dcbx_config.etscfg;
11418 hw->local_dcbx_config.pfc.willing = 0;
11419 hw->local_dcbx_config.pfc.pfccap =
11420 I40E_MAX_TRAFFIC_CLASS;
11421 /* FW needs one App to configure HW */
11422 hw->local_dcbx_config.numapps = 1;
11423 hw->local_dcbx_config.app[0].selector =
11424 I40E_APP_SEL_ETHTYPE;
11425 hw->local_dcbx_config.app[0].priority = 3;
11426 hw->local_dcbx_config.app[0].protocolid =
11427 I40E_APP_PROTOID_FCOE;
11428 ret = i40e_set_dcb_config(hw);
11431 "default dcb config fails. err = %d, aq_err = %d.",
11432 ret, hw->aq.asq_last_status);
11437 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11438 ret, hw->aq.asq_last_status);
11442 ret = i40e_aq_start_lldp(hw, NULL);
11443 if (ret != I40E_SUCCESS)
11444 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11446 ret = i40e_init_dcb(hw);
11448 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11450 "HW doesn't support DCBX offload.");
11455 "DCBX configuration failed, err = %d, aq_err = %d.",
11456 ret, hw->aq.asq_last_status);
11464 * i40e_dcb_setup - setup dcb related config
11465 * @dev: device being configured
11467 * Returns 0 on success, negative value on failure
11470 i40e_dcb_setup(struct rte_eth_dev *dev)
11472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11473 struct i40e_dcbx_config dcb_cfg;
11474 uint8_t tc_map = 0;
11477 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11478 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11482 if (pf->vf_num != 0)
11483 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11485 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11487 PMD_INIT_LOG(ERR, "invalid dcb config");
11490 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11492 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11500 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11501 struct rte_eth_dcb_info *dcb_info)
11503 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11505 struct i40e_vsi *vsi = pf->main_vsi;
11506 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11507 uint16_t bsf, tc_mapping;
11510 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11511 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11513 dcb_info->nb_tcs = 1;
11514 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11515 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11516 for (i = 0; i < dcb_info->nb_tcs; i++)
11517 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11519 /* get queue mapping if vmdq is disabled */
11520 if (!pf->nb_cfg_vmdq_vsi) {
11521 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11522 if (!(vsi->enabled_tc & (1 << i)))
11524 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11525 dcb_info->tc_queue.tc_rxq[j][i].base =
11526 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11527 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11528 dcb_info->tc_queue.tc_txq[j][i].base =
11529 dcb_info->tc_queue.tc_rxq[j][i].base;
11530 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11531 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11532 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11533 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11534 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11539 /* get queue mapping if vmdq is enabled */
11541 vsi = pf->vmdq[j].vsi;
11542 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11543 if (!(vsi->enabled_tc & (1 << i)))
11545 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11546 dcb_info->tc_queue.tc_rxq[j][i].base =
11547 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11548 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11549 dcb_info->tc_queue.tc_txq[j][i].base =
11550 dcb_info->tc_queue.tc_rxq[j][i].base;
11551 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11552 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11553 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11554 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11555 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11558 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11563 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11565 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11566 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11568 uint16_t msix_intr;
11570 msix_intr = intr_handle->intr_vec[queue_id];
11571 if (msix_intr == I40E_MISC_VEC_ID)
11572 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11573 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11574 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11575 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11578 I40E_PFINT_DYN_CTLN(msix_intr -
11579 I40E_RX_VEC_START),
11580 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11581 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11582 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11584 I40E_WRITE_FLUSH(hw);
11585 rte_intr_enable(&pci_dev->intr_handle);
11591 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11593 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11594 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11595 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11596 uint16_t msix_intr;
11598 msix_intr = intr_handle->intr_vec[queue_id];
11599 if (msix_intr == I40E_MISC_VEC_ID)
11600 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11601 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11604 I40E_PFINT_DYN_CTLN(msix_intr -
11605 I40E_RX_VEC_START),
11606 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11607 I40E_WRITE_FLUSH(hw);
11612 static int i40e_get_regs(struct rte_eth_dev *dev,
11613 struct rte_dev_reg_info *regs)
11615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11616 uint32_t *ptr_data = regs->data;
11617 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11618 const struct i40e_reg_info *reg_info;
11620 if (ptr_data == NULL) {
11621 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11622 regs->width = sizeof(uint32_t);
11626 /* The first few registers have to be read using AQ operations */
11628 while (i40e_regs_adminq[reg_idx].name) {
11629 reg_info = &i40e_regs_adminq[reg_idx++];
11630 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11632 arr_idx2 <= reg_info->count2;
11634 reg_offset = arr_idx * reg_info->stride1 +
11635 arr_idx2 * reg_info->stride2;
11636 reg_offset += reg_info->base_addr;
11637 ptr_data[reg_offset >> 2] =
11638 i40e_read_rx_ctl(hw, reg_offset);
11642 /* The remaining registers can be read using primitives */
11644 while (i40e_regs_others[reg_idx].name) {
11645 reg_info = &i40e_regs_others[reg_idx++];
11646 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11648 arr_idx2 <= reg_info->count2;
11650 reg_offset = arr_idx * reg_info->stride1 +
11651 arr_idx2 * reg_info->stride2;
11652 reg_offset += reg_info->base_addr;
11653 ptr_data[reg_offset >> 2] =
11654 I40E_READ_REG(hw, reg_offset);
11661 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11665 /* Convert word count to byte count */
11666 return hw->nvm.sr_size << 1;
11669 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11670 struct rte_dev_eeprom_info *eeprom)
11672 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11673 uint16_t *data = eeprom->data;
11674 uint16_t offset, length, cnt_words;
11677 offset = eeprom->offset >> 1;
11678 length = eeprom->length >> 1;
11679 cnt_words = length;
11681 if (offset > hw->nvm.sr_size ||
11682 offset + length > hw->nvm.sr_size) {
11683 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11687 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11689 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11690 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11691 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11698 static int i40e_get_module_info(struct rte_eth_dev *dev,
11699 struct rte_eth_dev_module_info *modinfo)
11701 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11702 uint32_t sff8472_comp = 0;
11703 uint32_t sff8472_swap = 0;
11704 uint32_t sff8636_rev = 0;
11705 i40e_status status;
11708 /* Check if firmware supports reading module EEPROM. */
11709 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11711 "Module EEPROM memory read not supported. "
11712 "Please update the NVM image.\n");
11716 status = i40e_update_link_info(hw);
11720 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11722 "Cannot read module EEPROM memory. "
11723 "No module connected.\n");
11727 type = hw->phy.link_info.module_type[0];
11730 case I40E_MODULE_TYPE_SFP:
11731 status = i40e_aq_get_phy_register(hw,
11732 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11733 I40E_I2C_EEPROM_DEV_ADDR, 1,
11734 I40E_MODULE_SFF_8472_COMP,
11735 &sff8472_comp, NULL);
11739 status = i40e_aq_get_phy_register(hw,
11740 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11741 I40E_I2C_EEPROM_DEV_ADDR, 1,
11742 I40E_MODULE_SFF_8472_SWAP,
11743 &sff8472_swap, NULL);
11747 /* Check if the module requires address swap to access
11748 * the other EEPROM memory page.
11750 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11751 PMD_DRV_LOG(WARNING,
11752 "Module address swap to access "
11753 "page 0xA2 is not supported.\n");
11754 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11755 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11756 } else if (sff8472_comp == 0x00) {
11757 /* Module is not SFF-8472 compliant */
11758 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11759 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11761 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11762 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11765 case I40E_MODULE_TYPE_QSFP_PLUS:
11766 /* Read from memory page 0. */
11767 status = i40e_aq_get_phy_register(hw,
11768 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11770 I40E_MODULE_REVISION_ADDR,
11771 &sff8636_rev, NULL);
11774 /* Determine revision compliance byte */
11775 if (sff8636_rev > 0x02) {
11776 /* Module is SFF-8636 compliant */
11777 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11778 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11780 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11781 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11784 case I40E_MODULE_TYPE_QSFP28:
11785 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11786 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11789 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11795 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11796 struct rte_dev_eeprom_info *info)
11798 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11799 bool is_sfp = false;
11800 i40e_status status;
11801 uint8_t *data = info->data;
11802 uint32_t value = 0;
11805 if (!info || !info->length || !data)
11808 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11811 for (i = 0; i < info->length; i++) {
11812 u32 offset = i + info->offset;
11813 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11815 /* Check if we need to access the other memory page */
11817 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11818 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11819 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11822 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11823 /* Compute memory page number and offset. */
11824 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11828 status = i40e_aq_get_phy_register(hw,
11829 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11830 addr, offset, 1, &value, NULL);
11833 data[i] = (uint8_t)value;
11838 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11839 struct ether_addr *mac_addr)
11841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11842 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11843 struct i40e_vsi *vsi = pf->main_vsi;
11844 struct i40e_mac_filter_info mac_filter;
11845 struct i40e_mac_filter *f;
11848 if (!is_valid_assigned_ether_addr(mac_addr)) {
11849 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11853 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11854 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11859 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11863 mac_filter = f->mac_info;
11864 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11865 if (ret != I40E_SUCCESS) {
11866 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11869 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11870 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11871 if (ret != I40E_SUCCESS) {
11872 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11875 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11877 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11878 mac_addr->addr_bytes, NULL);
11879 if (ret != I40E_SUCCESS) {
11880 PMD_DRV_LOG(ERR, "Failed to change mac");
11888 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11891 struct rte_eth_dev_data *dev_data = pf->dev_data;
11892 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11895 /* check if mtu is within the allowed range */
11896 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11899 /* mtu setting is forbidden if port is start */
11900 if (dev_data->dev_started) {
11901 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11902 dev_data->port_id);
11906 if (frame_size > ETHER_MAX_LEN)
11907 dev_data->dev_conf.rxmode.offloads |=
11908 DEV_RX_OFFLOAD_JUMBO_FRAME;
11910 dev_data->dev_conf.rxmode.offloads &=
11911 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11913 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11918 /* Restore ethertype filter */
11920 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11922 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11923 struct i40e_ethertype_filter_list
11924 *ethertype_list = &pf->ethertype.ethertype_list;
11925 struct i40e_ethertype_filter *f;
11926 struct i40e_control_filter_stats stats;
11929 TAILQ_FOREACH(f, ethertype_list, rules) {
11931 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11932 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11933 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11934 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11935 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11937 memset(&stats, 0, sizeof(stats));
11938 i40e_aq_add_rem_control_packet_filter(hw,
11939 f->input.mac_addr.addr_bytes,
11940 f->input.ether_type,
11941 flags, pf->main_vsi->seid,
11942 f->queue, 1, &stats, NULL);
11944 PMD_DRV_LOG(INFO, "Ethertype filter:"
11945 " mac_etype_used = %u, etype_used = %u,"
11946 " mac_etype_free = %u, etype_free = %u",
11947 stats.mac_etype_used, stats.etype_used,
11948 stats.mac_etype_free, stats.etype_free);
11951 /* Restore tunnel filter */
11953 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11955 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11956 struct i40e_vsi *vsi;
11957 struct i40e_pf_vf *vf;
11958 struct i40e_tunnel_filter_list
11959 *tunnel_list = &pf->tunnel.tunnel_list;
11960 struct i40e_tunnel_filter *f;
11961 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11962 bool big_buffer = 0;
11964 TAILQ_FOREACH(f, tunnel_list, rules) {
11966 vsi = pf->main_vsi;
11968 vf = &pf->vfs[f->vf_id];
11971 memset(&cld_filter, 0, sizeof(cld_filter));
11972 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11973 (struct ether_addr *)&cld_filter.element.outer_mac);
11974 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11975 (struct ether_addr *)&cld_filter.element.inner_mac);
11976 cld_filter.element.inner_vlan = f->input.inner_vlan;
11977 cld_filter.element.flags = f->input.flags;
11978 cld_filter.element.tenant_id = f->input.tenant_id;
11979 cld_filter.element.queue_number = f->queue;
11980 rte_memcpy(cld_filter.general_fields,
11981 f->input.general_fields,
11982 sizeof(f->input.general_fields));
11984 if (((f->input.flags &
11985 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11986 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11988 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11989 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11991 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11992 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11996 i40e_aq_add_cloud_filters_bb(hw,
11997 vsi->seid, &cld_filter, 1);
11999 i40e_aq_add_cloud_filters(hw, vsi->seid,
12000 &cld_filter.element, 1);
12004 /* Restore rss filter */
12006 i40e_rss_filter_restore(struct i40e_pf *pf)
12008 struct i40e_rte_flow_rss_conf *conf =
12010 if (conf->conf.queue_num)
12011 i40e_config_rss_filter(pf, conf, TRUE);
12015 i40e_filter_restore(struct i40e_pf *pf)
12017 i40e_ethertype_filter_restore(pf);
12018 i40e_tunnel_filter_restore(pf);
12019 i40e_fdir_filter_restore(pf);
12020 i40e_rss_filter_restore(pf);
12024 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12026 if (strcmp(dev->device->driver->name, drv->driver.name))
12033 is_i40e_supported(struct rte_eth_dev *dev)
12035 return is_device_supported(dev, &rte_i40e_pmd);
12038 struct i40e_customized_pctype*
12039 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12043 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12044 if (pf->customized_pctype[i].index == index)
12045 return &pf->customized_pctype[i];
12051 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12052 uint32_t pkg_size, uint32_t proto_num,
12053 struct rte_pmd_i40e_proto_info *proto,
12054 enum rte_pmd_i40e_package_op op)
12056 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12057 uint32_t pctype_num;
12058 struct rte_pmd_i40e_ptype_info *pctype;
12059 uint32_t buff_size;
12060 struct i40e_customized_pctype *new_pctype = NULL;
12062 uint8_t pctype_value;
12067 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12068 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12069 PMD_DRV_LOG(ERR, "Unsupported operation.");
12073 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12074 (uint8_t *)&pctype_num, sizeof(pctype_num),
12075 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12077 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12081 PMD_DRV_LOG(INFO, "No new pctype added");
12085 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12086 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12088 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12091 /* get information about new pctype list */
12092 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12093 (uint8_t *)pctype, buff_size,
12094 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12096 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12101 /* Update customized pctype. */
12102 for (i = 0; i < pctype_num; i++) {
12103 pctype_value = pctype[i].ptype_id;
12104 memset(name, 0, sizeof(name));
12105 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12106 proto_id = pctype[i].protocols[j];
12107 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12109 for (n = 0; n < proto_num; n++) {
12110 if (proto[n].proto_id != proto_id)
12112 strcat(name, proto[n].name);
12117 name[strlen(name) - 1] = '\0';
12118 if (!strcmp(name, "GTPC"))
12120 i40e_find_customized_pctype(pf,
12121 I40E_CUSTOMIZED_GTPC);
12122 else if (!strcmp(name, "GTPU_IPV4"))
12124 i40e_find_customized_pctype(pf,
12125 I40E_CUSTOMIZED_GTPU_IPV4);
12126 else if (!strcmp(name, "GTPU_IPV6"))
12128 i40e_find_customized_pctype(pf,
12129 I40E_CUSTOMIZED_GTPU_IPV6);
12130 else if (!strcmp(name, "GTPU"))
12132 i40e_find_customized_pctype(pf,
12133 I40E_CUSTOMIZED_GTPU);
12135 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12136 new_pctype->pctype = pctype_value;
12137 new_pctype->valid = true;
12139 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12140 new_pctype->valid = false;
12150 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12151 uint32_t pkg_size, uint32_t proto_num,
12152 struct rte_pmd_i40e_proto_info *proto,
12153 enum rte_pmd_i40e_package_op op)
12155 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12156 uint16_t port_id = dev->data->port_id;
12157 uint32_t ptype_num;
12158 struct rte_pmd_i40e_ptype_info *ptype;
12159 uint32_t buff_size;
12161 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12166 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12167 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12168 PMD_DRV_LOG(ERR, "Unsupported operation.");
12172 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12173 rte_pmd_i40e_ptype_mapping_reset(port_id);
12177 /* get information about new ptype num */
12178 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12179 (uint8_t *)&ptype_num, sizeof(ptype_num),
12180 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12182 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12186 PMD_DRV_LOG(INFO, "No new ptype added");
12190 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12191 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12193 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12197 /* get information about new ptype list */
12198 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12199 (uint8_t *)ptype, buff_size,
12200 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12202 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12207 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12208 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12209 if (!ptype_mapping) {
12210 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12215 /* Update ptype mapping table. */
12216 for (i = 0; i < ptype_num; i++) {
12217 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12218 ptype_mapping[i].sw_ptype = 0;
12220 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12221 proto_id = ptype[i].protocols[j];
12222 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12224 for (n = 0; n < proto_num; n++) {
12225 if (proto[n].proto_id != proto_id)
12227 memset(name, 0, sizeof(name));
12228 strcpy(name, proto[n].name);
12229 if (!strncasecmp(name, "PPPOE", 5))
12230 ptype_mapping[i].sw_ptype |=
12231 RTE_PTYPE_L2_ETHER_PPPOE;
12232 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12234 ptype_mapping[i].sw_ptype |=
12235 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12236 ptype_mapping[i].sw_ptype |=
12238 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12240 ptype_mapping[i].sw_ptype |=
12241 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12242 ptype_mapping[i].sw_ptype |=
12243 RTE_PTYPE_INNER_L4_FRAG;
12244 } else if (!strncasecmp(name, "OIPV4", 5)) {
12245 ptype_mapping[i].sw_ptype |=
12246 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12248 } else if (!strncasecmp(name, "IPV4", 4) &&
12250 ptype_mapping[i].sw_ptype |=
12251 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12252 else if (!strncasecmp(name, "IPV4", 4) &&
12254 ptype_mapping[i].sw_ptype |=
12255 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12256 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12258 ptype_mapping[i].sw_ptype |=
12259 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12260 ptype_mapping[i].sw_ptype |=
12262 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12264 ptype_mapping[i].sw_ptype |=
12265 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12266 ptype_mapping[i].sw_ptype |=
12267 RTE_PTYPE_INNER_L4_FRAG;
12268 } else if (!strncasecmp(name, "OIPV6", 5)) {
12269 ptype_mapping[i].sw_ptype |=
12270 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12272 } else if (!strncasecmp(name, "IPV6", 4) &&
12274 ptype_mapping[i].sw_ptype |=
12275 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12276 else if (!strncasecmp(name, "IPV6", 4) &&
12278 ptype_mapping[i].sw_ptype |=
12279 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12280 else if (!strncasecmp(name, "UDP", 3) &&
12282 ptype_mapping[i].sw_ptype |=
12284 else if (!strncasecmp(name, "UDP", 3) &&
12286 ptype_mapping[i].sw_ptype |=
12287 RTE_PTYPE_INNER_L4_UDP;
12288 else if (!strncasecmp(name, "TCP", 3) &&
12290 ptype_mapping[i].sw_ptype |=
12292 else if (!strncasecmp(name, "TCP", 3) &&
12294 ptype_mapping[i].sw_ptype |=
12295 RTE_PTYPE_INNER_L4_TCP;
12296 else if (!strncasecmp(name, "SCTP", 4) &&
12298 ptype_mapping[i].sw_ptype |=
12300 else if (!strncasecmp(name, "SCTP", 4) &&
12302 ptype_mapping[i].sw_ptype |=
12303 RTE_PTYPE_INNER_L4_SCTP;
12304 else if ((!strncasecmp(name, "ICMP", 4) ||
12305 !strncasecmp(name, "ICMPV6", 6)) &&
12307 ptype_mapping[i].sw_ptype |=
12309 else if ((!strncasecmp(name, "ICMP", 4) ||
12310 !strncasecmp(name, "ICMPV6", 6)) &&
12312 ptype_mapping[i].sw_ptype |=
12313 RTE_PTYPE_INNER_L4_ICMP;
12314 else if (!strncasecmp(name, "GTPC", 4)) {
12315 ptype_mapping[i].sw_ptype |=
12316 RTE_PTYPE_TUNNEL_GTPC;
12318 } else if (!strncasecmp(name, "GTPU", 4)) {
12319 ptype_mapping[i].sw_ptype |=
12320 RTE_PTYPE_TUNNEL_GTPU;
12322 } else if (!strncasecmp(name, "GRENAT", 6)) {
12323 ptype_mapping[i].sw_ptype |=
12324 RTE_PTYPE_TUNNEL_GRENAT;
12326 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12327 !strncasecmp(name, "L2TPV2", 6)) {
12328 ptype_mapping[i].sw_ptype |=
12329 RTE_PTYPE_TUNNEL_L2TP;
12338 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12341 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12343 rte_free(ptype_mapping);
12349 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12350 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12353 uint32_t proto_num;
12354 struct rte_pmd_i40e_proto_info *proto;
12355 uint32_t buff_size;
12359 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12360 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12361 PMD_DRV_LOG(ERR, "Unsupported operation.");
12365 /* get information about protocol number */
12366 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12367 (uint8_t *)&proto_num, sizeof(proto_num),
12368 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12370 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12374 PMD_DRV_LOG(INFO, "No new protocol added");
12378 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12379 proto = rte_zmalloc("new_proto", buff_size, 0);
12381 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12385 /* get information about protocol list */
12386 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12387 (uint8_t *)proto, buff_size,
12388 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12390 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12395 /* Check if GTP is supported. */
12396 for (i = 0; i < proto_num; i++) {
12397 if (!strncmp(proto[i].name, "GTP", 3)) {
12398 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12399 pf->gtp_support = true;
12401 pf->gtp_support = false;
12406 /* Update customized pctype info */
12407 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12408 proto_num, proto, op);
12410 PMD_DRV_LOG(INFO, "No pctype is updated.");
12412 /* Update customized ptype info */
12413 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12414 proto_num, proto, op);
12416 PMD_DRV_LOG(INFO, "No ptype is updated.");
12421 /* Create a QinQ cloud filter
12423 * The Fortville NIC has limited resources for tunnel filters,
12424 * so we can only reuse existing filters.
12426 * In step 1 we define which Field Vector fields can be used for
12428 * As we do not have the inner tag defined as a field,
12429 * we have to define it first, by reusing one of L1 entries.
12431 * In step 2 we are replacing one of existing filter types with
12432 * a new one for QinQ.
12433 * As we reusing L1 and replacing L2, some of the default filter
12434 * types will disappear,which depends on L1 and L2 entries we reuse.
12436 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12438 * 1. Create L1 filter of outer vlan (12b) which will be in use
12439 * later when we define the cloud filter.
12440 * a. Valid_flags.replace_cloud = 0
12441 * b. Old_filter = 10 (Stag_Inner_Vlan)
12442 * c. New_filter = 0x10
12443 * d. TR bit = 0xff (optional, not used here)
12444 * e. Buffer – 2 entries:
12445 * i. Byte 0 = 8 (outer vlan FV index).
12447 * Byte 2-3 = 0x0fff
12448 * ii. Byte 0 = 37 (inner vlan FV index).
12450 * Byte 2-3 = 0x0fff
12453 * 2. Create cloud filter using two L1 filters entries: stag and
12454 * new filter(outer vlan+ inner vlan)
12455 * a. Valid_flags.replace_cloud = 1
12456 * b. Old_filter = 1 (instead of outer IP)
12457 * c. New_filter = 0x10
12458 * d. Buffer – 2 entries:
12459 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12460 * Byte 1-3 = 0 (rsv)
12461 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12462 * Byte 9-11 = 0 (rsv)
12465 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12467 int ret = -ENOTSUP;
12468 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12469 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12470 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12471 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12473 if (pf->support_multi_driver) {
12474 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12479 memset(&filter_replace, 0,
12480 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12481 memset(&filter_replace_buf, 0,
12482 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12484 /* create L1 filter */
12485 filter_replace.old_filter_type =
12486 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12487 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12488 filter_replace.tr_bit = 0;
12490 /* Prepare the buffer, 2 entries */
12491 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12492 filter_replace_buf.data[0] |=
12493 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12494 /* Field Vector 12b mask */
12495 filter_replace_buf.data[2] = 0xff;
12496 filter_replace_buf.data[3] = 0x0f;
12497 filter_replace_buf.data[4] =
12498 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12499 filter_replace_buf.data[4] |=
12500 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12501 /* Field Vector 12b mask */
12502 filter_replace_buf.data[6] = 0xff;
12503 filter_replace_buf.data[7] = 0x0f;
12504 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12505 &filter_replace_buf);
12506 if (ret != I40E_SUCCESS)
12509 if (filter_replace.old_filter_type !=
12510 filter_replace.new_filter_type)
12511 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12512 " original: 0x%x, new: 0x%x",
12514 filter_replace.old_filter_type,
12515 filter_replace.new_filter_type);
12517 /* Apply the second L2 cloud filter */
12518 memset(&filter_replace, 0,
12519 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12520 memset(&filter_replace_buf, 0,
12521 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12523 /* create L2 filter, input for L2 filter will be L1 filter */
12524 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12525 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12526 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12528 /* Prepare the buffer, 2 entries */
12529 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12530 filter_replace_buf.data[0] |=
12531 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12532 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12533 filter_replace_buf.data[4] |=
12534 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12535 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12536 &filter_replace_buf);
12537 if (!ret && (filter_replace.old_filter_type !=
12538 filter_replace.new_filter_type))
12539 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12540 " original: 0x%x, new: 0x%x",
12542 filter_replace.old_filter_type,
12543 filter_replace.new_filter_type);
12549 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12550 const struct rte_flow_action_rss *in)
12552 if (in->key_len > RTE_DIM(out->key) ||
12553 in->queue_num > RTE_DIM(out->queue))
12555 out->conf = (struct rte_flow_action_rss){
12557 .level = in->level,
12558 .types = in->types,
12559 .key_len = in->key_len,
12560 .queue_num = in->queue_num,
12561 .key = memcpy(out->key, in->key, in->key_len),
12562 .queue = memcpy(out->queue, in->queue,
12563 sizeof(*in->queue) * in->queue_num),
12569 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12570 const struct rte_flow_action_rss *with)
12572 return (comp->func == with->func &&
12573 comp->level == with->level &&
12574 comp->types == with->types &&
12575 comp->key_len == with->key_len &&
12576 comp->queue_num == with->queue_num &&
12577 !memcmp(comp->key, with->key, with->key_len) &&
12578 !memcmp(comp->queue, with->queue,
12579 sizeof(*with->queue) * with->queue_num));
12583 i40e_config_rss_filter(struct i40e_pf *pf,
12584 struct i40e_rte_flow_rss_conf *conf, bool add)
12586 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12587 uint32_t i, lut = 0;
12589 struct rte_eth_rss_conf rss_conf = {
12590 .rss_key = conf->conf.key_len ?
12591 (void *)(uintptr_t)conf->conf.key : NULL,
12592 .rss_key_len = conf->conf.key_len,
12593 .rss_hf = conf->conf.types,
12595 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12598 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12599 i40e_pf_disable_rss(pf);
12600 memset(rss_info, 0,
12601 sizeof(struct i40e_rte_flow_rss_conf));
12607 if (rss_info->conf.queue_num)
12610 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12611 * It's necessary to calculate the actual PF queues that are configured.
12613 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12614 num = i40e_pf_calc_configured_queues_num(pf);
12616 num = pf->dev_data->nb_rx_queues;
12618 num = RTE_MIN(num, conf->conf.queue_num);
12619 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12623 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12627 /* Fill in redirection table */
12628 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12631 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12632 hw->func_caps.rss_table_entry_width) - 1));
12634 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12637 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12638 i40e_pf_disable_rss(pf);
12641 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12642 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12643 /* Random default keys */
12644 static uint32_t rss_key_default[] = {0x6b793944,
12645 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12646 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12647 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12649 rss_conf.rss_key = (uint8_t *)rss_key_default;
12650 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12654 i40e_hw_rss_hash_set(pf, &rss_conf);
12656 if (i40e_rss_conf_init(rss_info, &conf->conf))
12662 RTE_INIT(i40e_init_log)
12664 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12665 if (i40e_logtype_init >= 0)
12666 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12667 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12668 if (i40e_logtype_driver >= 0)
12669 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12672 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12673 ETH_I40E_FLOATING_VEB_ARG "=1"
12674 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12675 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12676 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12677 ETH_I40E_USE_LATEST_VEC "=0|1");