1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
404 static const struct rte_pci_id pci_id_i40e_map[] = {
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
425 { .vendor_id = 0, /* sentinel */ },
428 static const struct eth_dev_ops i40e_eth_dev_ops = {
429 .dev_configure = i40e_dev_configure,
430 .dev_start = i40e_dev_start,
431 .dev_stop = i40e_dev_stop,
432 .dev_close = i40e_dev_close,
433 .dev_reset = i40e_dev_reset,
434 .promiscuous_enable = i40e_dev_promiscuous_enable,
435 .promiscuous_disable = i40e_dev_promiscuous_disable,
436 .allmulticast_enable = i40e_dev_allmulticast_enable,
437 .allmulticast_disable = i40e_dev_allmulticast_disable,
438 .dev_set_link_up = i40e_dev_set_link_up,
439 .dev_set_link_down = i40e_dev_set_link_down,
440 .link_update = i40e_dev_link_update,
441 .stats_get = i40e_dev_stats_get,
442 .xstats_get = i40e_dev_xstats_get,
443 .xstats_get_names = i40e_dev_xstats_get_names,
444 .stats_reset = i40e_dev_stats_reset,
445 .xstats_reset = i40e_dev_stats_reset,
446 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
447 .fw_version_get = i40e_fw_version_get,
448 .dev_infos_get = i40e_dev_info_get,
449 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
450 .vlan_filter_set = i40e_vlan_filter_set,
451 .vlan_tpid_set = i40e_vlan_tpid_set,
452 .vlan_offload_set = i40e_vlan_offload_set,
453 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
454 .vlan_pvid_set = i40e_vlan_pvid_set,
455 .rx_queue_start = i40e_dev_rx_queue_start,
456 .rx_queue_stop = i40e_dev_rx_queue_stop,
457 .tx_queue_start = i40e_dev_tx_queue_start,
458 .tx_queue_stop = i40e_dev_tx_queue_stop,
459 .rx_queue_setup = i40e_dev_rx_queue_setup,
460 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
461 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
462 .rx_queue_release = i40e_dev_rx_queue_release,
463 .rx_queue_count = i40e_dev_rx_queue_count,
464 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
465 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
466 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
467 .tx_queue_setup = i40e_dev_tx_queue_setup,
468 .tx_queue_release = i40e_dev_tx_queue_release,
469 .dev_led_on = i40e_dev_led_on,
470 .dev_led_off = i40e_dev_led_off,
471 .flow_ctrl_get = i40e_flow_ctrl_get,
472 .flow_ctrl_set = i40e_flow_ctrl_set,
473 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
474 .mac_addr_add = i40e_macaddr_add,
475 .mac_addr_remove = i40e_macaddr_remove,
476 .reta_update = i40e_dev_rss_reta_update,
477 .reta_query = i40e_dev_rss_reta_query,
478 .rss_hash_update = i40e_dev_rss_hash_update,
479 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
480 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
481 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
482 .filter_ctrl = i40e_dev_filter_ctrl,
483 .rxq_info_get = i40e_rxq_info_get,
484 .txq_info_get = i40e_txq_info_get,
485 .mirror_rule_set = i40e_mirror_rule_set,
486 .mirror_rule_reset = i40e_mirror_rule_reset,
487 .timesync_enable = i40e_timesync_enable,
488 .timesync_disable = i40e_timesync_disable,
489 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
490 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
491 .get_dcb_info = i40e_dev_get_dcb_info,
492 .timesync_adjust_time = i40e_timesync_adjust_time,
493 .timesync_read_time = i40e_timesync_read_time,
494 .timesync_write_time = i40e_timesync_write_time,
495 .get_reg = i40e_get_regs,
496 .get_eeprom_length = i40e_get_eeprom_length,
497 .get_eeprom = i40e_get_eeprom,
498 .get_module_info = i40e_get_module_info,
499 .get_module_eeprom = i40e_get_module_eeprom,
500 .mac_addr_set = i40e_set_default_mac_addr,
501 .mtu_set = i40e_dev_mtu_set,
502 .tm_ops_get = i40e_tm_ops_get,
505 /* store statistics names and its offset in stats structure */
506 struct rte_i40e_xstats_name_off {
507 char name[RTE_ETH_XSTATS_NAME_SIZE];
511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
512 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
513 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
514 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
515 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
516 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
517 rx_unknown_protocol)},
518 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
519 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
520 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
521 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
525 sizeof(rte_i40e_stats_strings[0]))
527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
528 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
529 tx_dropped_link_down)},
530 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
531 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
533 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
534 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
536 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
538 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
540 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
541 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
542 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
543 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
544 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
545 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
547 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
549 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
551 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
553 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
555 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
557 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
562 mac_short_packet_dropped)},
563 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
566 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
567 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
569 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
571 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
573 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
575 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
577 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_flow_director_atr_match_packets",
580 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
581 {"rx_flow_director_sb_match_packets",
582 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
583 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
585 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
587 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
589 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
594 sizeof(rte_i40e_hw_port_strings[0]))
596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
597 {"xon_packets", offsetof(struct i40e_hw_port_stats,
599 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
604 sizeof(rte_i40e_rxq_prio_strings[0]))
606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
607 {"xon_packets", offsetof(struct i40e_hw_port_stats,
609 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
611 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
612 priority_xon_2_xoff)},
615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
616 sizeof(rte_i40e_txq_prio_strings[0]))
619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
620 struct rte_pci_device *pci_dev)
622 char name[RTE_ETH_NAME_MAX_LEN];
623 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
626 if (pci_dev->device.devargs) {
627 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
633 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
634 sizeof(struct i40e_adapter),
635 eth_dev_pci_specific_init, pci_dev,
636 eth_i40e_dev_init, NULL);
638 if (retval || eth_da.nb_representor_ports < 1)
641 /* probe VF representor ports */
642 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
643 pci_dev->device.name);
645 if (pf_ethdev == NULL)
648 for (i = 0; i < eth_da.nb_representor_ports; i++) {
649 struct i40e_vf_representor representor = {
650 .vf_id = eth_da.representor_ports[i],
651 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
652 pf_ethdev->data->dev_private)->switch_domain_id,
653 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
654 pf_ethdev->data->dev_private)
657 /* representor port net_bdf_port */
658 snprintf(name, sizeof(name), "net_%s_representor_%d",
659 pci_dev->device.name, eth_da.representor_ports[i]);
661 retval = rte_eth_dev_create(&pci_dev->device, name,
662 sizeof(struct i40e_vf_representor), NULL, NULL,
663 i40e_vf_representor_init, &representor);
666 PMD_DRV_LOG(ERR, "failed to create i40e vf "
667 "representor %s.", name);
673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
675 struct rte_eth_dev *ethdev;
677 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
682 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
683 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
685 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
688 static struct rte_pci_driver rte_i40e_pmd = {
689 .id_table = pci_id_i40e_map,
690 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
691 RTE_PCI_DRV_IOVA_AS_VA,
692 .probe = eth_i40e_pci_probe,
693 .remove = eth_i40e_pci_remove,
697 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
700 uint32_t ori_reg_val;
701 struct rte_eth_dev *dev;
703 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
704 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
705 i40e_write_rx_ctl(hw, reg_addr, reg_val);
706 if (ori_reg_val != reg_val)
708 "i40e device %s changed global register [0x%08x]."
709 " original: 0x%08x, new: 0x%08x",
710 dev->device->name, reg_addr, ori_reg_val, reg_val);
713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
715 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
717 #ifndef I40E_GLQF_ORT
718 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
720 #ifndef I40E_GLQF_PIT
721 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
723 #ifndef I40E_GLQF_L3_MAP
724 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
727 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
730 * Initialize registers for parsing packet type of QinQ
731 * This should be removed from code once proper
732 * configuration API is added to avoid configuration conflicts
733 * between ports of the same device.
735 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
736 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
737 i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
740 static inline void i40e_config_automask(struct i40e_pf *pf)
742 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
745 /* INTENA flag is not auto-cleared for interrupt */
746 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
747 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
748 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
750 /* If support multi-driver, PF will use INT0. */
751 if (!pf->support_multi_driver)
752 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
754 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
757 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
760 * Add a ethertype filter to drop all flow control frames transmitted
764 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
766 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
767 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
768 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
769 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
772 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
773 I40E_FLOW_CONTROL_ETHERTYPE, flags,
774 pf->main_vsi_seid, 0,
778 "Failed to add filter to drop flow control frames from VSIs.");
782 floating_veb_list_handler(__rte_unused const char *key,
783 const char *floating_veb_value,
787 unsigned int count = 0;
790 bool *vf_floating_veb = opaque;
792 while (isblank(*floating_veb_value))
793 floating_veb_value++;
795 /* Reset floating VEB configuration for VFs */
796 for (idx = 0; idx < I40E_MAX_VF; idx++)
797 vf_floating_veb[idx] = false;
801 while (isblank(*floating_veb_value))
802 floating_veb_value++;
803 if (*floating_veb_value == '\0')
806 idx = strtoul(floating_veb_value, &end, 10);
807 if (errno || end == NULL)
809 while (isblank(*end))
813 } else if ((*end == ';') || (*end == '\0')) {
815 if (min == I40E_MAX_VF)
817 if (max >= I40E_MAX_VF)
818 max = I40E_MAX_VF - 1;
819 for (idx = min; idx <= max; idx++) {
820 vf_floating_veb[idx] = true;
827 floating_veb_value = end + 1;
828 } while (*end != '\0');
837 config_vf_floating_veb(struct rte_devargs *devargs,
838 uint16_t floating_veb,
839 bool *vf_floating_veb)
841 struct rte_kvargs *kvlist;
843 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
847 /* All the VFs attach to the floating VEB by default
848 * when the floating VEB is enabled.
850 for (i = 0; i < I40E_MAX_VF; i++)
851 vf_floating_veb[i] = true;
856 kvlist = rte_kvargs_parse(devargs->args, NULL);
860 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
861 rte_kvargs_free(kvlist);
864 /* When the floating_veb_list parameter exists, all the VFs
865 * will attach to the legacy VEB firstly, then configure VFs
866 * to the floating VEB according to the floating_veb_list.
868 if (rte_kvargs_process(kvlist, floating_veb_list,
869 floating_veb_list_handler,
870 vf_floating_veb) < 0) {
871 rte_kvargs_free(kvlist);
874 rte_kvargs_free(kvlist);
878 i40e_check_floating_handler(__rte_unused const char *key,
880 __rte_unused void *opaque)
882 if (strcmp(value, "1"))
889 is_floating_veb_supported(struct rte_devargs *devargs)
891 struct rte_kvargs *kvlist;
892 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
897 kvlist = rte_kvargs_parse(devargs->args, NULL);
901 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
902 rte_kvargs_free(kvlist);
905 /* Floating VEB is enabled when there's key-value:
906 * enable_floating_veb=1
908 if (rte_kvargs_process(kvlist, floating_veb_key,
909 i40e_check_floating_handler, NULL) < 0) {
910 rte_kvargs_free(kvlist);
913 rte_kvargs_free(kvlist);
919 config_floating_veb(struct rte_eth_dev *dev)
921 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
922 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
923 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
925 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
927 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
929 is_floating_veb_supported(pci_dev->device.devargs);
930 config_vf_floating_veb(pci_dev->device.devargs,
932 pf->floating_veb_list);
934 pf->floating_veb = false;
938 #define I40E_L2_TAGS_S_TAG_SHIFT 1
939 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
942 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
944 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
945 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
946 char ethertype_hash_name[RTE_HASH_NAMESIZE];
949 struct rte_hash_parameters ethertype_hash_params = {
950 .name = ethertype_hash_name,
951 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
952 .key_len = sizeof(struct i40e_ethertype_filter_input),
953 .hash_func = rte_hash_crc,
954 .hash_func_init_val = 0,
955 .socket_id = rte_socket_id(),
958 /* Initialize ethertype filter rule list and hash */
959 TAILQ_INIT(ðertype_rule->ethertype_list);
960 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
961 "ethertype_%s", dev->device->name);
962 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
963 if (!ethertype_rule->hash_table) {
964 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
967 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
968 sizeof(struct i40e_ethertype_filter *) *
969 I40E_MAX_ETHERTYPE_FILTER_NUM,
971 if (!ethertype_rule->hash_map) {
973 "Failed to allocate memory for ethertype hash map!");
975 goto err_ethertype_hash_map_alloc;
980 err_ethertype_hash_map_alloc:
981 rte_hash_free(ethertype_rule->hash_table);
987 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
989 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
990 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
991 char tunnel_hash_name[RTE_HASH_NAMESIZE];
994 struct rte_hash_parameters tunnel_hash_params = {
995 .name = tunnel_hash_name,
996 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
997 .key_len = sizeof(struct i40e_tunnel_filter_input),
998 .hash_func = rte_hash_crc,
999 .hash_func_init_val = 0,
1000 .socket_id = rte_socket_id(),
1003 /* Initialize tunnel filter rule list and hash */
1004 TAILQ_INIT(&tunnel_rule->tunnel_list);
1005 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1006 "tunnel_%s", dev->device->name);
1007 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1008 if (!tunnel_rule->hash_table) {
1009 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1012 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1013 sizeof(struct i40e_tunnel_filter *) *
1014 I40E_MAX_TUNNEL_FILTER_NUM,
1016 if (!tunnel_rule->hash_map) {
1018 "Failed to allocate memory for tunnel hash map!");
1020 goto err_tunnel_hash_map_alloc;
1025 err_tunnel_hash_map_alloc:
1026 rte_hash_free(tunnel_rule->hash_table);
1032 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1034 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1035 struct i40e_fdir_info *fdir_info = &pf->fdir;
1036 char fdir_hash_name[RTE_HASH_NAMESIZE];
1039 struct rte_hash_parameters fdir_hash_params = {
1040 .name = fdir_hash_name,
1041 .entries = I40E_MAX_FDIR_FILTER_NUM,
1042 .key_len = sizeof(struct i40e_fdir_input),
1043 .hash_func = rte_hash_crc,
1044 .hash_func_init_val = 0,
1045 .socket_id = rte_socket_id(),
1048 /* Initialize flow director filter rule list and hash */
1049 TAILQ_INIT(&fdir_info->fdir_list);
1050 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1051 "fdir_%s", dev->device->name);
1052 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1053 if (!fdir_info->hash_table) {
1054 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1057 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1058 sizeof(struct i40e_fdir_filter *) *
1059 I40E_MAX_FDIR_FILTER_NUM,
1061 if (!fdir_info->hash_map) {
1063 "Failed to allocate memory for fdir hash map!");
1065 goto err_fdir_hash_map_alloc;
1069 err_fdir_hash_map_alloc:
1070 rte_hash_free(fdir_info->hash_table);
1076 i40e_init_customized_info(struct i40e_pf *pf)
1080 /* Initialize customized pctype */
1081 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1082 pf->customized_pctype[i].index = i;
1083 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1084 pf->customized_pctype[i].valid = false;
1087 pf->gtp_support = false;
1091 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1093 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1094 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1095 struct i40e_queue_regions *info = &pf->queue_region;
1098 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1099 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1101 memset(info, 0, sizeof(struct i40e_queue_regions));
1104 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
1107 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1112 unsigned long support_multi_driver;
1115 pf = (struct i40e_pf *)opaque;
1118 support_multi_driver = strtoul(value, &end, 10);
1119 if (errno != 0 || end == value || *end != 0) {
1120 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1124 if (support_multi_driver == 1 || support_multi_driver == 0)
1125 pf->support_multi_driver = (bool)support_multi_driver;
1127 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1128 "enable global configuration by default."
1129 ETH_I40E_SUPPORT_MULTI_DRIVER);
1134 i40e_support_multi_driver(struct rte_eth_dev *dev)
1136 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1137 static const char *const valid_keys[] = {
1138 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1139 struct rte_kvargs *kvlist;
1141 /* Enable global configuration by default */
1142 pf->support_multi_driver = false;
1144 if (!dev->device->devargs)
1147 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1151 if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1152 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1153 "the first invalid or last valid one is used !",
1154 ETH_I40E_SUPPORT_MULTI_DRIVER);
1156 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1157 i40e_parse_multi_drv_handler, pf) < 0) {
1158 rte_kvargs_free(kvlist);
1162 rte_kvargs_free(kvlist);
1167 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1168 uint32_t reg_addr, uint64_t reg_val,
1169 struct i40e_asq_cmd_details *cmd_details)
1171 uint64_t ori_reg_val;
1172 struct rte_eth_dev *dev;
1175 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1176 if (ret != I40E_SUCCESS) {
1178 "Fail to debug read from 0x%08x",
1182 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1184 if (ori_reg_val != reg_val)
1185 PMD_DRV_LOG(WARNING,
1186 "i40e device %s changed global register [0x%08x]."
1187 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1188 dev->device->name, reg_addr, ori_reg_val, reg_val);
1190 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1194 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1196 struct rte_pci_device *pci_dev;
1197 struct rte_intr_handle *intr_handle;
1198 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1199 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200 struct i40e_vsi *vsi;
1203 uint8_t aq_fail = 0;
1205 PMD_INIT_FUNC_TRACE();
1207 dev->dev_ops = &i40e_eth_dev_ops;
1208 dev->rx_pkt_burst = i40e_recv_pkts;
1209 dev->tx_pkt_burst = i40e_xmit_pkts;
1210 dev->tx_pkt_prepare = i40e_prep_pkts;
1212 /* for secondary processes, we don't initialise any further as primary
1213 * has already done this work. Only check we don't need a different
1215 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1216 i40e_set_rx_function(dev);
1217 i40e_set_tx_function(dev);
1220 i40e_set_default_ptype_table(dev);
1221 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1222 intr_handle = &pci_dev->intr_handle;
1224 rte_eth_copy_pci_info(dev, pci_dev);
1226 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1227 pf->adapter->eth_dev = dev;
1228 pf->dev_data = dev->data;
1230 hw->back = I40E_PF_TO_ADAPTER(pf);
1231 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1234 "Hardware is not available, as address is NULL");
1238 hw->vendor_id = pci_dev->id.vendor_id;
1239 hw->device_id = pci_dev->id.device_id;
1240 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1241 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1242 hw->bus.device = pci_dev->addr.devid;
1243 hw->bus.func = pci_dev->addr.function;
1244 hw->adapter_stopped = 0;
1246 /* Check if need to support multi-driver */
1247 i40e_support_multi_driver(dev);
1249 /* Make sure all is clean before doing PF reset */
1252 /* Initialize the hardware */
1255 /* Reset here to make sure all is clean for each PF */
1256 ret = i40e_pf_reset(hw);
1258 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1262 /* Initialize the shared code (base driver) */
1263 ret = i40e_init_shared_code(hw);
1265 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1269 i40e_config_automask(pf);
1271 i40e_set_default_pctype_table(dev);
1274 * To work around the NVM issue, initialize registers
1275 * for packet type of QinQ by software.
1276 * It should be removed once issues are fixed in NVM.
1278 if (!pf->support_multi_driver)
1279 i40e_GLQF_reg_init(hw);
1281 /* Initialize the input set for filters (hash and fd) to default value */
1282 i40e_filter_input_set_init(pf);
1284 /* Initialize the parameters for adminq */
1285 i40e_init_adminq_parameter(hw);
1286 ret = i40e_init_adminq(hw);
1287 if (ret != I40E_SUCCESS) {
1288 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1291 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1292 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1293 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1294 ((hw->nvm.version >> 12) & 0xf),
1295 ((hw->nvm.version >> 4) & 0xff),
1296 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1298 /* initialise the L3_MAP register */
1299 if (!pf->support_multi_driver) {
1300 ret = i40e_aq_debug_write_global_register(hw,
1301 I40E_GLQF_L3_MAP(40),
1304 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1307 "Global register 0x%08x is changed with 0x28",
1308 I40E_GLQF_L3_MAP(40));
1309 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1312 /* Need the special FW version to support floating VEB */
1313 config_floating_veb(dev);
1314 /* Clear PXE mode */
1315 i40e_clear_pxe_mode(hw);
1316 i40e_dev_sync_phy_type(hw);
1319 * On X710, performance number is far from the expectation on recent
1320 * firmware versions. The fix for this issue may not be integrated in
1321 * the following firmware version. So the workaround in software driver
1322 * is needed. It needs to modify the initial values of 3 internal only
1323 * registers. Note that the workaround can be removed when it is fixed
1324 * in firmware in the future.
1326 i40e_configure_registers(hw);
1328 /* Get hw capabilities */
1329 ret = i40e_get_cap(hw);
1330 if (ret != I40E_SUCCESS) {
1331 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1332 goto err_get_capabilities;
1335 /* Initialize parameters for PF */
1336 ret = i40e_pf_parameter_init(dev);
1338 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1339 goto err_parameter_init;
1342 /* Initialize the queue management */
1343 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1345 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1346 goto err_qp_pool_init;
1348 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1349 hw->func_caps.num_msix_vectors - 1);
1351 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1352 goto err_msix_pool_init;
1355 /* Initialize lan hmc */
1356 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1357 hw->func_caps.num_rx_qp, 0, 0);
1358 if (ret != I40E_SUCCESS) {
1359 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1360 goto err_init_lan_hmc;
1363 /* Configure lan hmc */
1364 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1365 if (ret != I40E_SUCCESS) {
1366 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1367 goto err_configure_lan_hmc;
1370 /* Get and check the mac address */
1371 i40e_get_mac_addr(hw, hw->mac.addr);
1372 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1373 PMD_INIT_LOG(ERR, "mac address is not valid");
1375 goto err_get_mac_addr;
1377 /* Copy the permanent MAC address */
1378 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1379 (struct ether_addr *) hw->mac.perm_addr);
1381 /* Disable flow control */
1382 hw->fc.requested_mode = I40E_FC_NONE;
1383 i40e_set_fc(hw, &aq_fail, TRUE);
1385 /* Set the global registers with default ether type value */
1386 if (!pf->support_multi_driver) {
1387 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1389 if (ret != I40E_SUCCESS) {
1391 "Failed to set the default outer "
1393 goto err_setup_pf_switch;
1397 /* PF setup, which includes VSI setup */
1398 ret = i40e_pf_setup(pf);
1400 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1401 goto err_setup_pf_switch;
1404 /* reset all stats of the device, including pf and main vsi */
1405 i40e_dev_stats_reset(dev);
1409 /* Disable double vlan by default */
1410 i40e_vsi_config_double_vlan(vsi, FALSE);
1412 /* Disable S-TAG identification when floating_veb is disabled */
1413 if (!pf->floating_veb) {
1414 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1415 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1416 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1417 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1421 if (!vsi->max_macaddrs)
1422 len = ETHER_ADDR_LEN;
1424 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1426 /* Should be after VSI initialized */
1427 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1428 if (!dev->data->mac_addrs) {
1430 "Failed to allocated memory for storing mac address");
1433 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1434 &dev->data->mac_addrs[0]);
1436 /* Init dcb to sw mode by default */
1437 ret = i40e_dcb_init_configure(dev, TRUE);
1438 if (ret != I40E_SUCCESS) {
1439 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1440 pf->flags &= ~I40E_FLAG_DCB;
1442 /* Update HW struct after DCB configuration */
1445 /* initialize pf host driver to setup SRIOV resource if applicable */
1446 i40e_pf_host_init(dev);
1448 /* register callback func to eal lib */
1449 rte_intr_callback_register(intr_handle,
1450 i40e_dev_interrupt_handler, dev);
1452 /* configure and enable device interrupt */
1453 i40e_pf_config_irq0(hw, TRUE);
1454 i40e_pf_enable_irq0(hw);
1456 /* enable uio intr after callback register */
1457 rte_intr_enable(intr_handle);
1459 /* By default disable flexible payload in global configuration */
1460 if (!pf->support_multi_driver)
1461 i40e_flex_payload_reg_set_default(hw);
1464 * Add an ethertype filter to drop all flow control frames transmitted
1465 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1468 i40e_add_tx_flow_control_drop_filter(pf);
1470 /* Set the max frame size to 0x2600 by default,
1471 * in case other drivers changed the default value.
1473 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1475 /* initialize mirror rule list */
1476 TAILQ_INIT(&pf->mirror_list);
1478 /* initialize Traffic Manager configuration */
1479 i40e_tm_conf_init(dev);
1481 /* Initialize customized information */
1482 i40e_init_customized_info(pf);
1484 ret = i40e_init_ethtype_filter_list(dev);
1486 goto err_init_ethtype_filter_list;
1487 ret = i40e_init_tunnel_filter_list(dev);
1489 goto err_init_tunnel_filter_list;
1490 ret = i40e_init_fdir_filter_list(dev);
1492 goto err_init_fdir_filter_list;
1494 /* initialize queue region configuration */
1495 i40e_init_queue_region_conf(dev);
1497 /* initialize rss configuration from rte_flow */
1498 memset(&pf->rss_info, 0,
1499 sizeof(struct i40e_rte_flow_rss_conf));
1503 err_init_fdir_filter_list:
1504 rte_free(pf->tunnel.hash_table);
1505 rte_free(pf->tunnel.hash_map);
1506 err_init_tunnel_filter_list:
1507 rte_free(pf->ethertype.hash_table);
1508 rte_free(pf->ethertype.hash_map);
1509 err_init_ethtype_filter_list:
1510 rte_free(dev->data->mac_addrs);
1512 i40e_vsi_release(pf->main_vsi);
1513 err_setup_pf_switch:
1515 err_configure_lan_hmc:
1516 (void)i40e_shutdown_lan_hmc(hw);
1518 i40e_res_pool_destroy(&pf->msix_pool);
1520 i40e_res_pool_destroy(&pf->qp_pool);
1523 err_get_capabilities:
1524 (void)i40e_shutdown_adminq(hw);
1530 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1532 struct i40e_ethertype_filter *p_ethertype;
1533 struct i40e_ethertype_rule *ethertype_rule;
1535 ethertype_rule = &pf->ethertype;
1536 /* Remove all ethertype filter rules and hash */
1537 if (ethertype_rule->hash_map)
1538 rte_free(ethertype_rule->hash_map);
1539 if (ethertype_rule->hash_table)
1540 rte_hash_free(ethertype_rule->hash_table);
1542 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1543 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1544 p_ethertype, rules);
1545 rte_free(p_ethertype);
1550 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1552 struct i40e_tunnel_filter *p_tunnel;
1553 struct i40e_tunnel_rule *tunnel_rule;
1555 tunnel_rule = &pf->tunnel;
1556 /* Remove all tunnel director rules and hash */
1557 if (tunnel_rule->hash_map)
1558 rte_free(tunnel_rule->hash_map);
1559 if (tunnel_rule->hash_table)
1560 rte_hash_free(tunnel_rule->hash_table);
1562 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1563 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1569 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1571 struct i40e_fdir_filter *p_fdir;
1572 struct i40e_fdir_info *fdir_info;
1574 fdir_info = &pf->fdir;
1575 /* Remove all flow director rules and hash */
1576 if (fdir_info->hash_map)
1577 rte_free(fdir_info->hash_map);
1578 if (fdir_info->hash_table)
1579 rte_hash_free(fdir_info->hash_table);
1581 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1582 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1587 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1590 * Disable by default flexible payload
1591 * for corresponding L2/L3/L4 layers.
1593 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1594 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1595 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1596 i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1600 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1603 struct rte_pci_device *pci_dev;
1604 struct rte_intr_handle *intr_handle;
1606 struct i40e_filter_control_settings settings;
1607 struct rte_flow *p_flow;
1609 uint8_t aq_fail = 0;
1612 PMD_INIT_FUNC_TRACE();
1614 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1617 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1618 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1620 intr_handle = &pci_dev->intr_handle;
1622 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1624 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1626 if (hw->adapter_stopped == 0)
1627 i40e_dev_close(dev);
1629 dev->dev_ops = NULL;
1630 dev->rx_pkt_burst = NULL;
1631 dev->tx_pkt_burst = NULL;
1633 /* Clear PXE mode */
1634 i40e_clear_pxe_mode(hw);
1636 /* Unconfigure filter control */
1637 memset(&settings, 0, sizeof(settings));
1638 ret = i40e_set_filter_control(hw, &settings);
1640 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1643 /* Disable flow control */
1644 hw->fc.requested_mode = I40E_FC_NONE;
1645 i40e_set_fc(hw, &aq_fail, TRUE);
1647 /* uninitialize pf host driver */
1648 i40e_pf_host_uninit(dev);
1650 rte_free(dev->data->mac_addrs);
1651 dev->data->mac_addrs = NULL;
1653 /* disable uio intr before callback unregister */
1654 rte_intr_disable(intr_handle);
1656 /* unregister callback func to eal lib */
1658 ret = rte_intr_callback_unregister(intr_handle,
1659 i40e_dev_interrupt_handler, dev);
1662 } else if (ret != -EAGAIN) {
1664 "intr callback unregister failed: %d",
1668 i40e_msec_delay(500);
1669 } while (retries++ < 5);
1671 i40e_rm_ethtype_filter_list(pf);
1672 i40e_rm_tunnel_filter_list(pf);
1673 i40e_rm_fdir_filter_list(pf);
1675 /* Remove all flows */
1676 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1677 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1681 /* Remove all Traffic Manager configuration */
1682 i40e_tm_conf_uninit(dev);
1688 i40e_dev_configure(struct rte_eth_dev *dev)
1690 struct i40e_adapter *ad =
1691 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1694 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1697 ret = i40e_dev_sync_phy_type(hw);
1701 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1702 * bulk allocation or vector Rx preconditions we will reset it.
1704 ad->rx_bulk_alloc_allowed = true;
1705 ad->rx_vec_allowed = true;
1706 ad->tx_simple_allowed = true;
1707 ad->tx_vec_allowed = true;
1709 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1710 ret = i40e_fdir_setup(pf);
1711 if (ret != I40E_SUCCESS) {
1712 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1715 ret = i40e_fdir_configure(dev);
1717 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1721 i40e_fdir_teardown(pf);
1723 ret = i40e_dev_init_vlan(dev);
1728 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1729 * RSS setting have different requirements.
1730 * General PMD driver call sequence are NIC init, configure,
1731 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1732 * will try to lookup the VSI that specific queue belongs to if VMDQ
1733 * applicable. So, VMDQ setting has to be done before
1734 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1735 * For RSS setting, it will try to calculate actual configured RX queue
1736 * number, which will be available after rx_queue_setup(). dev_start()
1737 * function is good to place RSS setup.
1739 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1740 ret = i40e_vmdq_setup(dev);
1745 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1746 ret = i40e_dcb_setup(dev);
1748 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1753 TAILQ_INIT(&pf->flow_list);
1758 /* need to release vmdq resource if exists */
1759 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1760 i40e_vsi_release(pf->vmdq[i].vsi);
1761 pf->vmdq[i].vsi = NULL;
1766 /* need to release fdir resource if exists */
1767 i40e_fdir_teardown(pf);
1772 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1774 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1775 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1776 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1777 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1778 uint16_t msix_vect = vsi->msix_intr;
1781 for (i = 0; i < vsi->nb_qps; i++) {
1782 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1783 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1787 if (vsi->type != I40E_VSI_SRIOV) {
1788 if (!rte_intr_allow_others(intr_handle)) {
1789 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1790 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1792 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1795 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1796 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1798 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1803 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1804 vsi->user_param + (msix_vect - 1);
1806 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1807 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1809 I40E_WRITE_FLUSH(hw);
1813 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1814 int base_queue, int nb_queue,
1819 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1820 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1822 /* Bind all RX queues to allocated MSIX interrupt */
1823 for (i = 0; i < nb_queue; i++) {
1824 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1825 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1826 ((base_queue + i + 1) <<
1827 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1828 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1829 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1831 if (i == nb_queue - 1)
1832 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1833 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1836 /* Write first RX queue to Link list register as the head element */
1837 if (vsi->type != I40E_VSI_SRIOV) {
1839 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1840 pf->support_multi_driver);
1842 if (msix_vect == I40E_MISC_VEC_ID) {
1843 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1845 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1847 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1849 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1852 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1854 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1856 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1858 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1865 if (msix_vect == I40E_MISC_VEC_ID) {
1867 I40E_VPINT_LNKLST0(vsi->user_param),
1869 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1871 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1873 /* num_msix_vectors_vf needs to minus irq0 */
1874 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1875 vsi->user_param + (msix_vect - 1);
1877 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1879 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1881 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1885 I40E_WRITE_FLUSH(hw);
1889 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1891 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1892 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1893 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1894 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1895 uint16_t msix_vect = vsi->msix_intr;
1896 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1897 uint16_t queue_idx = 0;
1901 for (i = 0; i < vsi->nb_qps; i++) {
1902 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1903 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1906 /* VF bind interrupt */
1907 if (vsi->type == I40E_VSI_SRIOV) {
1908 __vsi_queues_bind_intr(vsi, msix_vect,
1909 vsi->base_queue, vsi->nb_qps,
1914 /* PF & VMDq bind interrupt */
1915 if (rte_intr_dp_is_en(intr_handle)) {
1916 if (vsi->type == I40E_VSI_MAIN) {
1919 } else if (vsi->type == I40E_VSI_VMDQ2) {
1920 struct i40e_vsi *main_vsi =
1921 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1922 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1927 for (i = 0; i < vsi->nb_used_qps; i++) {
1929 if (!rte_intr_allow_others(intr_handle))
1930 /* allow to share MISC_VEC_ID */
1931 msix_vect = I40E_MISC_VEC_ID;
1933 /* no enough msix_vect, map all to one */
1934 __vsi_queues_bind_intr(vsi, msix_vect,
1935 vsi->base_queue + i,
1936 vsi->nb_used_qps - i,
1938 for (; !!record && i < vsi->nb_used_qps; i++)
1939 intr_handle->intr_vec[queue_idx + i] =
1943 /* 1:1 queue/msix_vect mapping */
1944 __vsi_queues_bind_intr(vsi, msix_vect,
1945 vsi->base_queue + i, 1,
1948 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1956 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1958 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1959 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1960 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1961 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1962 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1963 uint16_t msix_intr, i;
1965 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1966 for (i = 0; i < vsi->nb_msix; i++) {
1967 msix_intr = vsi->msix_intr + i;
1968 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1969 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1970 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1971 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1974 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1975 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1976 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1977 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1979 I40E_WRITE_FLUSH(hw);
1983 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1985 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1990 uint16_t msix_intr, i;
1992 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1993 for (i = 0; i < vsi->nb_msix; i++) {
1994 msix_intr = vsi->msix_intr + i;
1995 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1996 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1999 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2000 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2002 I40E_WRITE_FLUSH(hw);
2005 static inline uint8_t
2006 i40e_parse_link_speeds(uint16_t link_speeds)
2008 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2010 if (link_speeds & ETH_LINK_SPEED_40G)
2011 link_speed |= I40E_LINK_SPEED_40GB;
2012 if (link_speeds & ETH_LINK_SPEED_25G)
2013 link_speed |= I40E_LINK_SPEED_25GB;
2014 if (link_speeds & ETH_LINK_SPEED_20G)
2015 link_speed |= I40E_LINK_SPEED_20GB;
2016 if (link_speeds & ETH_LINK_SPEED_10G)
2017 link_speed |= I40E_LINK_SPEED_10GB;
2018 if (link_speeds & ETH_LINK_SPEED_1G)
2019 link_speed |= I40E_LINK_SPEED_1GB;
2020 if (link_speeds & ETH_LINK_SPEED_100M)
2021 link_speed |= I40E_LINK_SPEED_100MB;
2027 i40e_phy_conf_link(struct i40e_hw *hw,
2029 uint8_t force_speed,
2032 enum i40e_status_code status;
2033 struct i40e_aq_get_phy_abilities_resp phy_ab;
2034 struct i40e_aq_set_phy_config phy_conf;
2035 enum i40e_aq_phy_type cnt;
2036 uint32_t phy_type_mask = 0;
2038 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2039 I40E_AQ_PHY_FLAG_PAUSE_RX |
2040 I40E_AQ_PHY_FLAG_PAUSE_RX |
2041 I40E_AQ_PHY_FLAG_LOW_POWER;
2042 const uint8_t advt = I40E_LINK_SPEED_40GB |
2043 I40E_LINK_SPEED_25GB |
2044 I40E_LINK_SPEED_10GB |
2045 I40E_LINK_SPEED_1GB |
2046 I40E_LINK_SPEED_100MB;
2050 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2055 /* If link already up, no need to set up again */
2056 if (is_up && phy_ab.phy_type != 0)
2057 return I40E_SUCCESS;
2059 memset(&phy_conf, 0, sizeof(phy_conf));
2061 /* bits 0-2 use the values from get_phy_abilities_resp */
2063 abilities |= phy_ab.abilities & mask;
2065 /* update ablities and speed */
2066 if (abilities & I40E_AQ_PHY_AN_ENABLED)
2067 phy_conf.link_speed = advt;
2069 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2071 phy_conf.abilities = abilities;
2075 /* PHY type mask needs to include each type except PHY type extension */
2076 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2077 phy_type_mask |= 1 << cnt;
2079 /* use get_phy_abilities_resp value for the rest */
2080 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2081 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2082 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2083 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2084 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2085 phy_conf.eee_capability = phy_ab.eee_capability;
2086 phy_conf.eeer = phy_ab.eeer_val;
2087 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2089 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2090 phy_ab.abilities, phy_ab.link_speed);
2091 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2092 phy_conf.abilities, phy_conf.link_speed);
2094 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2098 return I40E_SUCCESS;
2102 i40e_apply_link_speed(struct rte_eth_dev *dev)
2105 uint8_t abilities = 0;
2106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107 struct rte_eth_conf *conf = &dev->data->dev_conf;
2109 speed = i40e_parse_link_speeds(conf->link_speeds);
2110 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2111 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2112 abilities |= I40E_AQ_PHY_AN_ENABLED;
2113 abilities |= I40E_AQ_PHY_LINK_ENABLED;
2115 return i40e_phy_conf_link(hw, abilities, speed, true);
2119 i40e_dev_start(struct rte_eth_dev *dev)
2121 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123 struct i40e_vsi *main_vsi = pf->main_vsi;
2125 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2126 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2127 uint32_t intr_vector = 0;
2128 struct i40e_vsi *vsi;
2130 hw->adapter_stopped = 0;
2132 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2134 "Invalid link_speeds for port %u, autonegotiation disabled",
2135 dev->data->port_id);
2139 rte_intr_disable(intr_handle);
2141 if ((rte_intr_cap_multiple(intr_handle) ||
2142 !RTE_ETH_DEV_SRIOV(dev).active) &&
2143 dev->data->dev_conf.intr_conf.rxq != 0) {
2144 intr_vector = dev->data->nb_rx_queues;
2145 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2150 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2151 intr_handle->intr_vec =
2152 rte_zmalloc("intr_vec",
2153 dev->data->nb_rx_queues * sizeof(int),
2155 if (!intr_handle->intr_vec) {
2157 "Failed to allocate %d rx_queues intr_vec",
2158 dev->data->nb_rx_queues);
2163 /* Initialize VSI */
2164 ret = i40e_dev_rxtx_init(pf);
2165 if (ret != I40E_SUCCESS) {
2166 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2170 /* Map queues with MSIX interrupt */
2171 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2172 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2173 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2174 i40e_vsi_enable_queues_intr(main_vsi);
2176 /* Map VMDQ VSI queues with MSIX interrupt */
2177 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2178 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2179 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2180 I40E_ITR_INDEX_DEFAULT);
2181 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2184 /* enable FDIR MSIX interrupt */
2185 if (pf->fdir.fdir_vsi) {
2186 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2187 I40E_ITR_INDEX_NONE);
2188 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2191 /* Enable all queues which have been configured */
2192 ret = i40e_dev_switch_queues(pf, TRUE);
2193 if (ret != I40E_SUCCESS) {
2194 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2198 /* Enable receiving broadcast packets */
2199 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2200 if (ret != I40E_SUCCESS)
2201 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2203 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2204 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2206 if (ret != I40E_SUCCESS)
2207 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2210 /* Enable the VLAN promiscuous mode. */
2212 for (i = 0; i < pf->vf_num; i++) {
2213 vsi = pf->vfs[i].vsi;
2214 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2219 /* Enable mac loopback mode */
2220 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2221 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2222 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2223 if (ret != I40E_SUCCESS) {
2224 PMD_DRV_LOG(ERR, "fail to set loopback link");
2229 /* Apply link configure */
2230 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2231 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2232 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2233 ETH_LINK_SPEED_40G)) {
2234 PMD_DRV_LOG(ERR, "Invalid link setting");
2237 ret = i40e_apply_link_speed(dev);
2238 if (I40E_SUCCESS != ret) {
2239 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2243 if (!rte_intr_allow_others(intr_handle)) {
2244 rte_intr_callback_unregister(intr_handle,
2245 i40e_dev_interrupt_handler,
2247 /* configure and enable device interrupt */
2248 i40e_pf_config_irq0(hw, FALSE);
2249 i40e_pf_enable_irq0(hw);
2251 if (dev->data->dev_conf.intr_conf.lsc != 0)
2253 "lsc won't enable because of no intr multiplex");
2255 ret = i40e_aq_set_phy_int_mask(hw,
2256 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2257 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2258 I40E_AQ_EVENT_MEDIA_NA), NULL);
2259 if (ret != I40E_SUCCESS)
2260 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2262 /* Call get_link_info aq commond to enable/disable LSE */
2263 i40e_dev_link_update(dev, 0);
2266 /* enable uio intr after callback register */
2267 rte_intr_enable(intr_handle);
2269 i40e_filter_restore(pf);
2271 if (pf->tm_conf.root && !pf->tm_conf.committed)
2272 PMD_DRV_LOG(WARNING,
2273 "please call hierarchy_commit() "
2274 "before starting the port");
2276 return I40E_SUCCESS;
2279 i40e_dev_switch_queues(pf, FALSE);
2280 i40e_dev_clear_queues(dev);
2286 i40e_dev_stop(struct rte_eth_dev *dev)
2288 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2289 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2290 struct i40e_vsi *main_vsi = pf->main_vsi;
2291 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2292 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2295 if (hw->adapter_stopped == 1)
2297 /* Disable all queues */
2298 i40e_dev_switch_queues(pf, FALSE);
2300 /* un-map queues with interrupt registers */
2301 i40e_vsi_disable_queues_intr(main_vsi);
2302 i40e_vsi_queues_unbind_intr(main_vsi);
2304 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2305 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2306 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2309 if (pf->fdir.fdir_vsi) {
2310 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2311 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2313 /* Clear all queues and release memory */
2314 i40e_dev_clear_queues(dev);
2317 i40e_dev_set_link_down(dev);
2319 if (!rte_intr_allow_others(intr_handle))
2320 /* resume to the default handler */
2321 rte_intr_callback_register(intr_handle,
2322 i40e_dev_interrupt_handler,
2325 /* Clean datapath event and queue/vec mapping */
2326 rte_intr_efd_disable(intr_handle);
2327 if (intr_handle->intr_vec) {
2328 rte_free(intr_handle->intr_vec);
2329 intr_handle->intr_vec = NULL;
2332 /* reset hierarchy commit */
2333 pf->tm_conf.committed = false;
2335 hw->adapter_stopped = 1;
2339 i40e_dev_close(struct rte_eth_dev *dev)
2341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2344 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2345 struct i40e_mirror_rule *p_mirror;
2350 PMD_INIT_FUNC_TRACE();
2354 /* Remove all mirror rules */
2355 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2356 ret = i40e_aq_del_mirror_rule(hw,
2357 pf->main_vsi->veb->seid,
2358 p_mirror->rule_type,
2360 p_mirror->num_entries,
2363 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2364 "status = %d, aq_err = %d.", ret,
2365 hw->aq.asq_last_status);
2367 /* remove mirror software resource anyway */
2368 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2370 pf->nb_mirror_rule--;
2373 i40e_dev_free_queues(dev);
2375 /* Disable interrupt */
2376 i40e_pf_disable_irq0(hw);
2377 rte_intr_disable(intr_handle);
2379 i40e_fdir_teardown(pf);
2381 /* shutdown and destroy the HMC */
2382 i40e_shutdown_lan_hmc(hw);
2384 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2385 i40e_vsi_release(pf->vmdq[i].vsi);
2386 pf->vmdq[i].vsi = NULL;
2391 /* release all the existing VSIs and VEBs */
2392 i40e_vsi_release(pf->main_vsi);
2394 /* shutdown the adminq */
2395 i40e_aq_queue_shutdown(hw, true);
2396 i40e_shutdown_adminq(hw);
2398 i40e_res_pool_destroy(&pf->qp_pool);
2399 i40e_res_pool_destroy(&pf->msix_pool);
2401 /* Disable flexible payload in global configuration */
2402 if (!pf->support_multi_driver)
2403 i40e_flex_payload_reg_set_default(hw);
2405 /* force a PF reset to clean anything leftover */
2406 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2407 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2408 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2409 I40E_WRITE_FLUSH(hw);
2413 * Reset PF device only to re-initialize resources in PMD layer
2416 i40e_dev_reset(struct rte_eth_dev *dev)
2420 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2421 * its VF to make them align with it. The detailed notification
2422 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2423 * To avoid unexpected behavior in VF, currently reset of PF with
2424 * SR-IOV activation is not supported. It might be supported later.
2426 if (dev->data->sriov.active)
2429 ret = eth_i40e_dev_uninit(dev);
2433 ret = eth_i40e_dev_init(dev, NULL);
2439 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2441 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443 struct i40e_vsi *vsi = pf->main_vsi;
2446 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2448 if (status != I40E_SUCCESS)
2449 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2451 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2453 if (status != I40E_SUCCESS)
2454 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2459 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2461 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2462 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463 struct i40e_vsi *vsi = pf->main_vsi;
2466 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2468 if (status != I40E_SUCCESS)
2469 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2471 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2473 if (status != I40E_SUCCESS)
2474 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2478 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2481 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482 struct i40e_vsi *vsi = pf->main_vsi;
2485 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2486 if (ret != I40E_SUCCESS)
2487 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2491 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2494 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495 struct i40e_vsi *vsi = pf->main_vsi;
2498 if (dev->data->promiscuous == 1)
2499 return; /* must remain in all_multicast mode */
2501 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2502 vsi->seid, FALSE, NULL);
2503 if (ret != I40E_SUCCESS)
2504 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2508 * Set device link up.
2511 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2513 /* re-apply link speed setting */
2514 return i40e_apply_link_speed(dev);
2518 * Set device link down.
2521 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2523 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2524 uint8_t abilities = 0;
2525 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2528 return i40e_phy_conf_link(hw, abilities, speed, false);
2531 static __rte_always_inline void
2532 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2534 /* Link status registers and values*/
2535 #define I40E_PRTMAC_LINKSTA 0x001E2420
2536 #define I40E_REG_LINK_UP 0x40000080
2537 #define I40E_PRTMAC_MACC 0x001E24E0
2538 #define I40E_REG_MACC_25GB 0x00020000
2539 #define I40E_REG_SPEED_MASK 0x38000000
2540 #define I40E_REG_SPEED_100MB 0x00000000
2541 #define I40E_REG_SPEED_1GB 0x08000000
2542 #define I40E_REG_SPEED_10GB 0x10000000
2543 #define I40E_REG_SPEED_20GB 0x20000000
2544 #define I40E_REG_SPEED_25_40GB 0x18000000
2545 uint32_t link_speed;
2548 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2549 link_speed = reg_val & I40E_REG_SPEED_MASK;
2550 reg_val &= I40E_REG_LINK_UP;
2551 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2553 if (unlikely(link->link_status == 0))
2556 /* Parse the link status */
2557 switch (link_speed) {
2558 case I40E_REG_SPEED_100MB:
2559 link->link_speed = ETH_SPEED_NUM_100M;
2561 case I40E_REG_SPEED_1GB:
2562 link->link_speed = ETH_SPEED_NUM_1G;
2564 case I40E_REG_SPEED_10GB:
2565 link->link_speed = ETH_SPEED_NUM_10G;
2567 case I40E_REG_SPEED_20GB:
2568 link->link_speed = ETH_SPEED_NUM_20G;
2570 case I40E_REG_SPEED_25_40GB:
2571 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2573 if (reg_val & I40E_REG_MACC_25GB)
2574 link->link_speed = ETH_SPEED_NUM_25G;
2576 link->link_speed = ETH_SPEED_NUM_40G;
2580 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2585 static __rte_always_inline void
2586 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2587 bool enable_lse, int wait_to_complete)
2589 #define CHECK_INTERVAL 100 /* 100ms */
2590 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2591 uint32_t rep_cnt = MAX_REPEAT_TIME;
2592 struct i40e_link_status link_status;
2595 memset(&link_status, 0, sizeof(link_status));
2598 memset(&link_status, 0, sizeof(link_status));
2600 /* Get link status information from hardware */
2601 status = i40e_aq_get_link_info(hw, enable_lse,
2602 &link_status, NULL);
2603 if (unlikely(status != I40E_SUCCESS)) {
2604 link->link_speed = ETH_SPEED_NUM_100M;
2605 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2606 PMD_DRV_LOG(ERR, "Failed to get link info");
2610 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2611 if (!wait_to_complete || link->link_status)
2614 rte_delay_ms(CHECK_INTERVAL);
2615 } while (--rep_cnt);
2617 /* Parse the link status */
2618 switch (link_status.link_speed) {
2619 case I40E_LINK_SPEED_100MB:
2620 link->link_speed = ETH_SPEED_NUM_100M;
2622 case I40E_LINK_SPEED_1GB:
2623 link->link_speed = ETH_SPEED_NUM_1G;
2625 case I40E_LINK_SPEED_10GB:
2626 link->link_speed = ETH_SPEED_NUM_10G;
2628 case I40E_LINK_SPEED_20GB:
2629 link->link_speed = ETH_SPEED_NUM_20G;
2631 case I40E_LINK_SPEED_25GB:
2632 link->link_speed = ETH_SPEED_NUM_25G;
2634 case I40E_LINK_SPEED_40GB:
2635 link->link_speed = ETH_SPEED_NUM_40G;
2638 link->link_speed = ETH_SPEED_NUM_100M;
2644 i40e_dev_link_update(struct rte_eth_dev *dev,
2645 int wait_to_complete)
2647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648 struct rte_eth_link link;
2649 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2652 memset(&link, 0, sizeof(link));
2654 /* i40e uses full duplex only */
2655 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2656 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2657 ETH_LINK_SPEED_FIXED);
2659 if (!wait_to_complete && !enable_lse)
2660 update_link_reg(hw, &link);
2662 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2664 ret = rte_eth_linkstatus_set(dev, &link);
2665 i40e_notify_all_vfs_link_status(dev);
2670 /* Get all the statistics of a VSI */
2672 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2674 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2675 struct i40e_eth_stats *nes = &vsi->eth_stats;
2676 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2677 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2679 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2680 vsi->offset_loaded, &oes->rx_bytes,
2682 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2683 vsi->offset_loaded, &oes->rx_unicast,
2685 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2686 vsi->offset_loaded, &oes->rx_multicast,
2687 &nes->rx_multicast);
2688 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2689 vsi->offset_loaded, &oes->rx_broadcast,
2690 &nes->rx_broadcast);
2691 /* exclude CRC bytes */
2692 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2693 nes->rx_broadcast) * ETHER_CRC_LEN;
2695 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2696 &oes->rx_discards, &nes->rx_discards);
2697 /* GLV_REPC not supported */
2698 /* GLV_RMPC not supported */
2699 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2700 &oes->rx_unknown_protocol,
2701 &nes->rx_unknown_protocol);
2702 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2703 vsi->offset_loaded, &oes->tx_bytes,
2705 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2706 vsi->offset_loaded, &oes->tx_unicast,
2708 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2709 vsi->offset_loaded, &oes->tx_multicast,
2710 &nes->tx_multicast);
2711 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2712 vsi->offset_loaded, &oes->tx_broadcast,
2713 &nes->tx_broadcast);
2714 /* GLV_TDPC not supported */
2715 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2716 &oes->tx_errors, &nes->tx_errors);
2717 vsi->offset_loaded = true;
2719 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2721 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2722 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2723 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2724 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2725 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2726 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2727 nes->rx_unknown_protocol);
2728 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2729 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2730 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2731 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2732 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2733 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2734 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2739 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2742 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2743 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2745 /* Get rx/tx bytes of internal transfer packets */
2746 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2747 I40E_GLV_GORCL(hw->port),
2749 &pf->internal_stats_offset.rx_bytes,
2750 &pf->internal_stats.rx_bytes);
2752 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2753 I40E_GLV_GOTCL(hw->port),
2755 &pf->internal_stats_offset.tx_bytes,
2756 &pf->internal_stats.tx_bytes);
2757 /* Get total internal rx packet count */
2758 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2759 I40E_GLV_UPRCL(hw->port),
2761 &pf->internal_stats_offset.rx_unicast,
2762 &pf->internal_stats.rx_unicast);
2763 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2764 I40E_GLV_MPRCL(hw->port),
2766 &pf->internal_stats_offset.rx_multicast,
2767 &pf->internal_stats.rx_multicast);
2768 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2769 I40E_GLV_BPRCL(hw->port),
2771 &pf->internal_stats_offset.rx_broadcast,
2772 &pf->internal_stats.rx_broadcast);
2773 /* Get total internal tx packet count */
2774 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2775 I40E_GLV_UPTCL(hw->port),
2777 &pf->internal_stats_offset.tx_unicast,
2778 &pf->internal_stats.tx_unicast);
2779 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2780 I40E_GLV_MPTCL(hw->port),
2782 &pf->internal_stats_offset.tx_multicast,
2783 &pf->internal_stats.tx_multicast);
2784 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2785 I40E_GLV_BPTCL(hw->port),
2787 &pf->internal_stats_offset.tx_broadcast,
2788 &pf->internal_stats.tx_broadcast);
2790 /* exclude CRC size */
2791 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2792 pf->internal_stats.rx_multicast +
2793 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2795 /* Get statistics of struct i40e_eth_stats */
2796 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2797 I40E_GLPRT_GORCL(hw->port),
2798 pf->offset_loaded, &os->eth.rx_bytes,
2800 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2801 I40E_GLPRT_UPRCL(hw->port),
2802 pf->offset_loaded, &os->eth.rx_unicast,
2803 &ns->eth.rx_unicast);
2804 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2805 I40E_GLPRT_MPRCL(hw->port),
2806 pf->offset_loaded, &os->eth.rx_multicast,
2807 &ns->eth.rx_multicast);
2808 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2809 I40E_GLPRT_BPRCL(hw->port),
2810 pf->offset_loaded, &os->eth.rx_broadcast,
2811 &ns->eth.rx_broadcast);
2812 /* Workaround: CRC size should not be included in byte statistics,
2813 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2815 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2816 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2818 /* exclude internal rx bytes
2819 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2820 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2822 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2824 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2825 ns->eth.rx_bytes = 0;
2827 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2829 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2830 ns->eth.rx_unicast = 0;
2832 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2834 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2835 ns->eth.rx_multicast = 0;
2837 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2839 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2840 ns->eth.rx_broadcast = 0;
2842 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2844 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2845 pf->offset_loaded, &os->eth.rx_discards,
2846 &ns->eth.rx_discards);
2847 /* GLPRT_REPC not supported */
2848 /* GLPRT_RMPC not supported */
2849 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2851 &os->eth.rx_unknown_protocol,
2852 &ns->eth.rx_unknown_protocol);
2853 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2854 I40E_GLPRT_GOTCL(hw->port),
2855 pf->offset_loaded, &os->eth.tx_bytes,
2857 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2858 I40E_GLPRT_UPTCL(hw->port),
2859 pf->offset_loaded, &os->eth.tx_unicast,
2860 &ns->eth.tx_unicast);
2861 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2862 I40E_GLPRT_MPTCL(hw->port),
2863 pf->offset_loaded, &os->eth.tx_multicast,
2864 &ns->eth.tx_multicast);
2865 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2866 I40E_GLPRT_BPTCL(hw->port),
2867 pf->offset_loaded, &os->eth.tx_broadcast,
2868 &ns->eth.tx_broadcast);
2869 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2870 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2872 /* exclude internal tx bytes
2873 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2874 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2876 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2878 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2879 ns->eth.tx_bytes = 0;
2881 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2883 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2884 ns->eth.tx_unicast = 0;
2886 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2888 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2889 ns->eth.tx_multicast = 0;
2891 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2893 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2894 ns->eth.tx_broadcast = 0;
2896 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2898 /* GLPRT_TEPC not supported */
2900 /* additional port specific stats */
2901 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2902 pf->offset_loaded, &os->tx_dropped_link_down,
2903 &ns->tx_dropped_link_down);
2904 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2905 pf->offset_loaded, &os->crc_errors,
2907 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2908 pf->offset_loaded, &os->illegal_bytes,
2909 &ns->illegal_bytes);
2910 /* GLPRT_ERRBC not supported */
2911 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2912 pf->offset_loaded, &os->mac_local_faults,
2913 &ns->mac_local_faults);
2914 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2915 pf->offset_loaded, &os->mac_remote_faults,
2916 &ns->mac_remote_faults);
2917 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2918 pf->offset_loaded, &os->rx_length_errors,
2919 &ns->rx_length_errors);
2920 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2921 pf->offset_loaded, &os->link_xon_rx,
2923 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2924 pf->offset_loaded, &os->link_xoff_rx,
2926 for (i = 0; i < 8; i++) {
2927 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2929 &os->priority_xon_rx[i],
2930 &ns->priority_xon_rx[i]);
2931 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2933 &os->priority_xoff_rx[i],
2934 &ns->priority_xoff_rx[i]);
2936 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2937 pf->offset_loaded, &os->link_xon_tx,
2939 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2940 pf->offset_loaded, &os->link_xoff_tx,
2942 for (i = 0; i < 8; i++) {
2943 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2945 &os->priority_xon_tx[i],
2946 &ns->priority_xon_tx[i]);
2947 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2949 &os->priority_xoff_tx[i],
2950 &ns->priority_xoff_tx[i]);
2951 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2953 &os->priority_xon_2_xoff[i],
2954 &ns->priority_xon_2_xoff[i]);
2956 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2957 I40E_GLPRT_PRC64L(hw->port),
2958 pf->offset_loaded, &os->rx_size_64,
2960 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2961 I40E_GLPRT_PRC127L(hw->port),
2962 pf->offset_loaded, &os->rx_size_127,
2964 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2965 I40E_GLPRT_PRC255L(hw->port),
2966 pf->offset_loaded, &os->rx_size_255,
2968 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2969 I40E_GLPRT_PRC511L(hw->port),
2970 pf->offset_loaded, &os->rx_size_511,
2972 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2973 I40E_GLPRT_PRC1023L(hw->port),
2974 pf->offset_loaded, &os->rx_size_1023,
2976 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2977 I40E_GLPRT_PRC1522L(hw->port),
2978 pf->offset_loaded, &os->rx_size_1522,
2980 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2981 I40E_GLPRT_PRC9522L(hw->port),
2982 pf->offset_loaded, &os->rx_size_big,
2984 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2985 pf->offset_loaded, &os->rx_undersize,
2987 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2988 pf->offset_loaded, &os->rx_fragments,
2990 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2991 pf->offset_loaded, &os->rx_oversize,
2993 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2994 pf->offset_loaded, &os->rx_jabber,
2996 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2997 I40E_GLPRT_PTC64L(hw->port),
2998 pf->offset_loaded, &os->tx_size_64,
3000 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3001 I40E_GLPRT_PTC127L(hw->port),
3002 pf->offset_loaded, &os->tx_size_127,
3004 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3005 I40E_GLPRT_PTC255L(hw->port),
3006 pf->offset_loaded, &os->tx_size_255,
3008 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3009 I40E_GLPRT_PTC511L(hw->port),
3010 pf->offset_loaded, &os->tx_size_511,
3012 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3013 I40E_GLPRT_PTC1023L(hw->port),
3014 pf->offset_loaded, &os->tx_size_1023,
3016 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3017 I40E_GLPRT_PTC1522L(hw->port),
3018 pf->offset_loaded, &os->tx_size_1522,
3020 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3021 I40E_GLPRT_PTC9522L(hw->port),
3022 pf->offset_loaded, &os->tx_size_big,
3024 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3026 &os->fd_sb_match, &ns->fd_sb_match);
3027 /* GLPRT_MSPDC not supported */
3028 /* GLPRT_XEC not supported */
3030 pf->offset_loaded = true;
3033 i40e_update_vsi_stats(pf->main_vsi);
3036 /* Get all statistics of a port */
3038 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3041 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3045 /* call read registers - updates values, now write them to struct */
3046 i40e_read_stats_registers(pf, hw);
3048 stats->ipackets = ns->eth.rx_unicast +
3049 ns->eth.rx_multicast +
3050 ns->eth.rx_broadcast -
3051 ns->eth.rx_discards -
3052 pf->main_vsi->eth_stats.rx_discards;
3053 stats->opackets = ns->eth.tx_unicast +
3054 ns->eth.tx_multicast +
3055 ns->eth.tx_broadcast;
3056 stats->ibytes = ns->eth.rx_bytes;
3057 stats->obytes = ns->eth.tx_bytes;
3058 stats->oerrors = ns->eth.tx_errors +
3059 pf->main_vsi->eth_stats.tx_errors;
3062 stats->imissed = ns->eth.rx_discards +
3063 pf->main_vsi->eth_stats.rx_discards;
3064 stats->ierrors = ns->crc_errors +
3065 ns->rx_length_errors + ns->rx_undersize +
3066 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3068 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3069 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3070 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3071 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3072 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3073 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3074 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3075 ns->eth.rx_unknown_protocol);
3076 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3077 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3078 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3079 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3080 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3081 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3083 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3084 ns->tx_dropped_link_down);
3085 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3086 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3088 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3089 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3090 ns->mac_local_faults);
3091 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3092 ns->mac_remote_faults);
3093 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3094 ns->rx_length_errors);
3095 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3096 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3097 for (i = 0; i < 8; i++) {
3098 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3099 i, ns->priority_xon_rx[i]);
3100 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3101 i, ns->priority_xoff_rx[i]);
3103 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3104 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3105 for (i = 0; i < 8; i++) {
3106 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3107 i, ns->priority_xon_tx[i]);
3108 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3109 i, ns->priority_xoff_tx[i]);
3110 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3111 i, ns->priority_xon_2_xoff[i]);
3113 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3114 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3115 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3116 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3117 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3118 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3119 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3120 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3121 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3122 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3123 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3124 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3125 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3126 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3127 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3128 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3129 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3130 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3131 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3132 ns->mac_short_packet_dropped);
3133 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3134 ns->checksum_error);
3135 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3136 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3140 /* Reset the statistics */
3142 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3144 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3145 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3147 /* Mark PF and VSI stats to update the offset, aka "reset" */
3148 pf->offset_loaded = false;
3150 pf->main_vsi->offset_loaded = false;
3152 /* read the stats, reading current register values into offset */
3153 i40e_read_stats_registers(pf, hw);
3157 i40e_xstats_calc_num(void)
3159 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3160 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3161 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3164 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3165 struct rte_eth_xstat_name *xstats_names,
3166 __rte_unused unsigned limit)
3171 if (xstats_names == NULL)
3172 return i40e_xstats_calc_num();
3174 /* Note: limit checked in rte_eth_xstats_names() */
3176 /* Get stats from i40e_eth_stats struct */
3177 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3178 snprintf(xstats_names[count].name,
3179 sizeof(xstats_names[count].name),
3180 "%s", rte_i40e_stats_strings[i].name);
3184 /* Get individiual stats from i40e_hw_port struct */
3185 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3186 snprintf(xstats_names[count].name,
3187 sizeof(xstats_names[count].name),
3188 "%s", rte_i40e_hw_port_strings[i].name);
3192 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3193 for (prio = 0; prio < 8; prio++) {
3194 snprintf(xstats_names[count].name,
3195 sizeof(xstats_names[count].name),
3196 "rx_priority%u_%s", prio,
3197 rte_i40e_rxq_prio_strings[i].name);
3202 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3203 for (prio = 0; prio < 8; prio++) {
3204 snprintf(xstats_names[count].name,
3205 sizeof(xstats_names[count].name),
3206 "tx_priority%u_%s", prio,
3207 rte_i40e_txq_prio_strings[i].name);
3215 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3218 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3219 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3220 unsigned i, count, prio;
3221 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3223 count = i40e_xstats_calc_num();
3227 i40e_read_stats_registers(pf, hw);
3234 /* Get stats from i40e_eth_stats struct */
3235 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3236 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3237 rte_i40e_stats_strings[i].offset);
3238 xstats[count].id = count;
3242 /* Get individiual stats from i40e_hw_port struct */
3243 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3244 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3245 rte_i40e_hw_port_strings[i].offset);
3246 xstats[count].id = count;
3250 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3251 for (prio = 0; prio < 8; prio++) {
3252 xstats[count].value =
3253 *(uint64_t *)(((char *)hw_stats) +
3254 rte_i40e_rxq_prio_strings[i].offset +
3255 (sizeof(uint64_t) * prio));
3256 xstats[count].id = count;
3261 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3262 for (prio = 0; prio < 8; prio++) {
3263 xstats[count].value =
3264 *(uint64_t *)(((char *)hw_stats) +
3265 rte_i40e_txq_prio_strings[i].offset +
3266 (sizeof(uint64_t) * prio));
3267 xstats[count].id = count;
3276 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3277 __rte_unused uint16_t queue_id,
3278 __rte_unused uint8_t stat_idx,
3279 __rte_unused uint8_t is_rx)
3281 PMD_INIT_FUNC_TRACE();
3287 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3289 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295 full_ver = hw->nvm.oem_ver;
3296 ver = (u8)(full_ver >> 24);
3297 build = (u16)((full_ver >> 8) & 0xffff);
3298 patch = (u8)(full_ver & 0xff);
3300 ret = snprintf(fw_version, fw_size,
3301 "%d.%d%d 0x%08x %d.%d.%d",
3302 ((hw->nvm.version >> 12) & 0xf),
3303 ((hw->nvm.version >> 4) & 0xff),
3304 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3307 ret += 1; /* add the size of '\0' */
3308 if (fw_size < (u32)ret)
3315 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3317 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319 struct i40e_vsi *vsi = pf->main_vsi;
3320 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3322 dev_info->max_rx_queues = vsi->nb_qps;
3323 dev_info->max_tx_queues = vsi->nb_qps;
3324 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3325 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3326 dev_info->max_mac_addrs = vsi->max_macaddrs;
3327 dev_info->max_vfs = pci_dev->max_vfs;
3328 dev_info->rx_queue_offload_capa = 0;
3329 dev_info->rx_offload_capa =
3330 DEV_RX_OFFLOAD_VLAN_STRIP |
3331 DEV_RX_OFFLOAD_QINQ_STRIP |
3332 DEV_RX_OFFLOAD_IPV4_CKSUM |
3333 DEV_RX_OFFLOAD_UDP_CKSUM |
3334 DEV_RX_OFFLOAD_TCP_CKSUM |
3335 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3336 DEV_RX_OFFLOAD_CRC_STRIP |
3337 DEV_RX_OFFLOAD_VLAN_EXTEND |
3338 DEV_RX_OFFLOAD_VLAN_FILTER |
3339 DEV_RX_OFFLOAD_JUMBO_FRAME;
3341 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3342 dev_info->tx_offload_capa =
3343 DEV_TX_OFFLOAD_VLAN_INSERT |
3344 DEV_TX_OFFLOAD_QINQ_INSERT |
3345 DEV_TX_OFFLOAD_IPV4_CKSUM |
3346 DEV_TX_OFFLOAD_UDP_CKSUM |
3347 DEV_TX_OFFLOAD_TCP_CKSUM |
3348 DEV_TX_OFFLOAD_SCTP_CKSUM |
3349 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3350 DEV_TX_OFFLOAD_TCP_TSO |
3351 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3352 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3353 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3354 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3355 DEV_TX_OFFLOAD_MULTI_SEGS |
3356 dev_info->tx_queue_offload_capa;
3357 dev_info->dev_capa =
3358 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3359 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3361 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3363 dev_info->reta_size = pf->hash_lut_size;
3364 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3366 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3368 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3369 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3370 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3372 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3377 dev_info->default_txconf = (struct rte_eth_txconf) {
3379 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3380 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3381 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3383 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3384 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3388 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3389 .nb_max = I40E_MAX_RING_DESC,
3390 .nb_min = I40E_MIN_RING_DESC,
3391 .nb_align = I40E_ALIGN_RING_DESC,
3394 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3395 .nb_max = I40E_MAX_RING_DESC,
3396 .nb_min = I40E_MIN_RING_DESC,
3397 .nb_align = I40E_ALIGN_RING_DESC,
3398 .nb_seg_max = I40E_TX_MAX_SEG,
3399 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3402 if (pf->flags & I40E_FLAG_VMDQ) {
3403 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3404 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3405 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3406 pf->max_nb_vmdq_vsi;
3407 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3408 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3409 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3412 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3414 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3415 dev_info->default_rxportconf.nb_queues = 2;
3416 dev_info->default_txportconf.nb_queues = 2;
3417 if (dev->data->nb_rx_queues == 1)
3418 dev_info->default_rxportconf.ring_size = 2048;
3420 dev_info->default_rxportconf.ring_size = 1024;
3421 if (dev->data->nb_tx_queues == 1)
3422 dev_info->default_txportconf.ring_size = 1024;
3424 dev_info->default_txportconf.ring_size = 512;
3426 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3428 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3429 dev_info->default_rxportconf.nb_queues = 1;
3430 dev_info->default_txportconf.nb_queues = 1;
3431 dev_info->default_rxportconf.ring_size = 256;
3432 dev_info->default_txportconf.ring_size = 256;
3435 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3436 dev_info->default_rxportconf.nb_queues = 1;
3437 dev_info->default_txportconf.nb_queues = 1;
3438 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3439 dev_info->default_rxportconf.ring_size = 512;
3440 dev_info->default_txportconf.ring_size = 256;
3442 dev_info->default_rxportconf.ring_size = 256;
3443 dev_info->default_txportconf.ring_size = 256;
3446 dev_info->default_rxportconf.burst_size = 32;
3447 dev_info->default_txportconf.burst_size = 32;
3451 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3453 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3454 struct i40e_vsi *vsi = pf->main_vsi;
3455 PMD_INIT_FUNC_TRACE();
3458 return i40e_vsi_add_vlan(vsi, vlan_id);
3460 return i40e_vsi_delete_vlan(vsi, vlan_id);
3464 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3465 enum rte_vlan_type vlan_type,
3466 uint16_t tpid, int qinq)
3468 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3471 uint16_t reg_id = 3;
3475 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3479 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3481 if (ret != I40E_SUCCESS) {
3483 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3488 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3491 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3492 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3493 if (reg_r == reg_w) {
3494 PMD_DRV_LOG(DEBUG, "No need to write");
3498 ret = i40e_aq_debug_write_global_register(hw,
3499 I40E_GL_SWT_L2TAGCTRL(reg_id),
3501 if (ret != I40E_SUCCESS) {
3503 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3508 "Global register 0x%08x is changed with value 0x%08x",
3509 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3511 i40e_global_cfg_warning(I40E_WARNING_TPID);
3517 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3518 enum rte_vlan_type vlan_type,
3521 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3523 int qinq = dev->data->dev_conf.rxmode.offloads &
3524 DEV_RX_OFFLOAD_VLAN_EXTEND;
3527 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3528 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3529 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3531 "Unsupported vlan type.");
3535 if (pf->support_multi_driver) {
3536 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3540 /* 802.1ad frames ability is added in NVM API 1.7*/
3541 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3543 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3544 hw->first_tag = rte_cpu_to_le_16(tpid);
3545 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3546 hw->second_tag = rte_cpu_to_le_16(tpid);
3548 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3549 hw->second_tag = rte_cpu_to_le_16(tpid);
3551 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3552 if (ret != I40E_SUCCESS) {
3554 "Set switch config failed aq_err: %d",
3555 hw->aq.asq_last_status);
3559 /* If NVM API < 1.7, keep the register setting */
3560 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3567 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3569 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3570 struct i40e_vsi *vsi = pf->main_vsi;
3571 struct rte_eth_rxmode *rxmode;
3573 rxmode = &dev->data->dev_conf.rxmode;
3574 if (mask & ETH_VLAN_FILTER_MASK) {
3575 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3576 i40e_vsi_config_vlan_filter(vsi, TRUE);
3578 i40e_vsi_config_vlan_filter(vsi, FALSE);
3581 if (mask & ETH_VLAN_STRIP_MASK) {
3582 /* Enable or disable VLAN stripping */
3583 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3584 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3586 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3589 if (mask & ETH_VLAN_EXTEND_MASK) {
3590 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3591 i40e_vsi_config_double_vlan(vsi, TRUE);
3592 /* Set global registers with default ethertype. */
3593 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3595 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3599 i40e_vsi_config_double_vlan(vsi, FALSE);
3606 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3607 __rte_unused uint16_t queue,
3608 __rte_unused int on)
3610 PMD_INIT_FUNC_TRACE();
3614 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3616 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3617 struct i40e_vsi *vsi = pf->main_vsi;
3618 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3619 struct i40e_vsi_vlan_pvid_info info;
3621 memset(&info, 0, sizeof(info));
3624 info.config.pvid = pvid;
3626 info.config.reject.tagged =
3627 data->dev_conf.txmode.hw_vlan_reject_tagged;
3628 info.config.reject.untagged =
3629 data->dev_conf.txmode.hw_vlan_reject_untagged;
3632 return i40e_vsi_vlan_pvid_set(vsi, &info);
3636 i40e_dev_led_on(struct rte_eth_dev *dev)
3638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639 uint32_t mode = i40e_led_get(hw);
3642 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3648 i40e_dev_led_off(struct rte_eth_dev *dev)
3650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651 uint32_t mode = i40e_led_get(hw);
3654 i40e_led_set(hw, 0, false);
3660 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3663 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3665 fc_conf->pause_time = pf->fc_conf.pause_time;
3667 /* read out from register, in case they are modified by other port */
3668 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3669 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3670 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3671 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3673 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3674 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3676 /* Return current mode according to actual setting*/
3677 switch (hw->fc.current_mode) {
3679 fc_conf->mode = RTE_FC_FULL;
3681 case I40E_FC_TX_PAUSE:
3682 fc_conf->mode = RTE_FC_TX_PAUSE;
3684 case I40E_FC_RX_PAUSE:
3685 fc_conf->mode = RTE_FC_RX_PAUSE;
3689 fc_conf->mode = RTE_FC_NONE;
3696 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3698 uint32_t mflcn_reg, fctrl_reg, reg;
3699 uint32_t max_high_water;
3700 uint8_t i, aq_failure;
3704 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3705 [RTE_FC_NONE] = I40E_FC_NONE,
3706 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3707 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3708 [RTE_FC_FULL] = I40E_FC_FULL
3711 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3713 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3714 if ((fc_conf->high_water > max_high_water) ||
3715 (fc_conf->high_water < fc_conf->low_water)) {
3717 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3722 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3723 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3724 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3726 pf->fc_conf.pause_time = fc_conf->pause_time;
3727 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3728 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3730 PMD_INIT_FUNC_TRACE();
3732 /* All the link flow control related enable/disable register
3733 * configuration is handle by the F/W
3735 err = i40e_set_fc(hw, &aq_failure, true);
3739 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3740 /* Configure flow control refresh threshold,
3741 * the value for stat_tx_pause_refresh_timer[8]
3742 * is used for global pause operation.
3746 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3747 pf->fc_conf.pause_time);
3749 /* configure the timer value included in transmitted pause
3751 * the value for stat_tx_pause_quanta[8] is used for global
3754 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3755 pf->fc_conf.pause_time);
3757 fctrl_reg = I40E_READ_REG(hw,
3758 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3760 if (fc_conf->mac_ctrl_frame_fwd != 0)
3761 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3763 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3765 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3768 /* Configure pause time (2 TCs per register) */
3769 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3770 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3771 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3773 /* Configure flow control refresh threshold value */
3774 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3775 pf->fc_conf.pause_time / 2);
3777 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3779 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3780 *depending on configuration
3782 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3783 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3784 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3786 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3787 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3790 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3793 if (!pf->support_multi_driver) {
3794 /* config water marker both based on the packets and bytes */
3795 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3796 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3797 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3798 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3799 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3800 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3801 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3802 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3804 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3805 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3807 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3810 "Water marker configuration is not supported.");
3813 I40E_WRITE_FLUSH(hw);
3819 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3820 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3822 PMD_INIT_FUNC_TRACE();
3827 /* Add a MAC address, and update filters */
3829 i40e_macaddr_add(struct rte_eth_dev *dev,
3830 struct ether_addr *mac_addr,
3831 __rte_unused uint32_t index,
3834 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3835 struct i40e_mac_filter_info mac_filter;
3836 struct i40e_vsi *vsi;
3837 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3840 /* If VMDQ not enabled or configured, return */
3841 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3842 !pf->nb_cfg_vmdq_vsi)) {
3843 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3844 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3849 if (pool > pf->nb_cfg_vmdq_vsi) {
3850 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3851 pool, pf->nb_cfg_vmdq_vsi);
3855 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3856 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3857 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3859 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3864 vsi = pf->vmdq[pool - 1].vsi;
3866 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3867 if (ret != I40E_SUCCESS) {
3868 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3874 /* Remove a MAC address, and update filters */
3876 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3878 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3879 struct i40e_vsi *vsi;
3880 struct rte_eth_dev_data *data = dev->data;
3881 struct ether_addr *macaddr;
3886 macaddr = &(data->mac_addrs[index]);
3888 pool_sel = dev->data->mac_pool_sel[index];
3890 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3891 if (pool_sel & (1ULL << i)) {
3895 /* No VMDQ pool enabled or configured */
3896 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3897 (i > pf->nb_cfg_vmdq_vsi)) {
3899 "No VMDQ pool enabled/configured");
3902 vsi = pf->vmdq[i - 1].vsi;
3904 ret = i40e_vsi_delete_mac(vsi, macaddr);
3907 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3914 /* Set perfect match or hash match of MAC and VLAN for a VF */
3916 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3917 struct rte_eth_mac_filter *filter,
3921 struct i40e_mac_filter_info mac_filter;
3922 struct ether_addr old_mac;
3923 struct ether_addr *new_mac;
3924 struct i40e_pf_vf *vf = NULL;
3929 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3932 hw = I40E_PF_TO_HW(pf);
3934 if (filter == NULL) {
3935 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3939 new_mac = &filter->mac_addr;
3941 if (is_zero_ether_addr(new_mac)) {
3942 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3946 vf_id = filter->dst_id;
3948 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3949 PMD_DRV_LOG(ERR, "Invalid argument.");
3952 vf = &pf->vfs[vf_id];
3954 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3955 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3960 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3961 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3963 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3966 mac_filter.filter_type = filter->filter_type;
3967 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3968 if (ret != I40E_SUCCESS) {
3969 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3972 ether_addr_copy(new_mac, &pf->dev_addr);
3974 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3976 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3977 if (ret != I40E_SUCCESS) {
3978 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3982 /* Clear device address as it has been removed */
3983 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3984 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3990 /* MAC filter handle */
3992 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3996 struct rte_eth_mac_filter *filter;
3997 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3998 int ret = I40E_NOT_SUPPORTED;
4000 filter = (struct rte_eth_mac_filter *)(arg);
4002 switch (filter_op) {
4003 case RTE_ETH_FILTER_NOP:
4006 case RTE_ETH_FILTER_ADD:
4007 i40e_pf_disable_irq0(hw);
4009 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4010 i40e_pf_enable_irq0(hw);
4012 case RTE_ETH_FILTER_DELETE:
4013 i40e_pf_disable_irq0(hw);
4015 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4016 i40e_pf_enable_irq0(hw);
4019 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4020 ret = I40E_ERR_PARAM;
4028 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4030 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4031 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4038 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4039 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4042 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4046 uint32_t *lut_dw = (uint32_t *)lut;
4047 uint16_t i, lut_size_dw = lut_size / 4;
4049 if (vsi->type == I40E_VSI_SRIOV) {
4050 for (i = 0; i <= lut_size_dw; i++) {
4051 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4052 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4055 for (i = 0; i < lut_size_dw; i++)
4056 lut_dw[i] = I40E_READ_REG(hw,
4065 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4074 pf = I40E_VSI_TO_PF(vsi);
4075 hw = I40E_VSI_TO_HW(vsi);
4077 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4078 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4081 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4085 uint32_t *lut_dw = (uint32_t *)lut;
4086 uint16_t i, lut_size_dw = lut_size / 4;
4088 if (vsi->type == I40E_VSI_SRIOV) {
4089 for (i = 0; i < lut_size_dw; i++)
4092 I40E_VFQF_HLUT1(i, vsi->user_param),
4095 for (i = 0; i < lut_size_dw; i++)
4096 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4099 I40E_WRITE_FLUSH(hw);
4106 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4107 struct rte_eth_rss_reta_entry64 *reta_conf,
4110 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4111 uint16_t i, lut_size = pf->hash_lut_size;
4112 uint16_t idx, shift;
4116 if (reta_size != lut_size ||
4117 reta_size > ETH_RSS_RETA_SIZE_512) {
4119 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4120 reta_size, lut_size);
4124 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4126 PMD_DRV_LOG(ERR, "No memory can be allocated");
4129 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4132 for (i = 0; i < reta_size; i++) {
4133 idx = i / RTE_RETA_GROUP_SIZE;
4134 shift = i % RTE_RETA_GROUP_SIZE;
4135 if (reta_conf[idx].mask & (1ULL << shift))
4136 lut[i] = reta_conf[idx].reta[shift];
4138 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4147 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4148 struct rte_eth_rss_reta_entry64 *reta_conf,
4151 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4152 uint16_t i, lut_size = pf->hash_lut_size;
4153 uint16_t idx, shift;
4157 if (reta_size != lut_size ||
4158 reta_size > ETH_RSS_RETA_SIZE_512) {
4160 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4161 reta_size, lut_size);
4165 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4167 PMD_DRV_LOG(ERR, "No memory can be allocated");
4171 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4174 for (i = 0; i < reta_size; i++) {
4175 idx = i / RTE_RETA_GROUP_SIZE;
4176 shift = i % RTE_RETA_GROUP_SIZE;
4177 if (reta_conf[idx].mask & (1ULL << shift))
4178 reta_conf[idx].reta[shift] = lut[i];
4188 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4189 * @hw: pointer to the HW structure
4190 * @mem: pointer to mem struct to fill out
4191 * @size: size of memory requested
4192 * @alignment: what to align the allocation to
4194 enum i40e_status_code
4195 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4196 struct i40e_dma_mem *mem,
4200 const struct rte_memzone *mz = NULL;
4201 char z_name[RTE_MEMZONE_NAMESIZE];
4204 return I40E_ERR_PARAM;
4206 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4207 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4208 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4210 return I40E_ERR_NO_MEMORY;
4215 mem->zone = (const void *)mz;
4217 "memzone %s allocated with physical address: %"PRIu64,
4220 return I40E_SUCCESS;
4224 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4225 * @hw: pointer to the HW structure
4226 * @mem: ptr to mem struct to free
4228 enum i40e_status_code
4229 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4230 struct i40e_dma_mem *mem)
4233 return I40E_ERR_PARAM;
4236 "memzone %s to be freed with physical address: %"PRIu64,
4237 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4238 rte_memzone_free((const struct rte_memzone *)mem->zone);
4243 return I40E_SUCCESS;
4247 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4248 * @hw: pointer to the HW structure
4249 * @mem: pointer to mem struct to fill out
4250 * @size: size of memory requested
4252 enum i40e_status_code
4253 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4254 struct i40e_virt_mem *mem,
4258 return I40E_ERR_PARAM;
4261 mem->va = rte_zmalloc("i40e", size, 0);
4264 return I40E_SUCCESS;
4266 return I40E_ERR_NO_MEMORY;
4270 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4271 * @hw: pointer to the HW structure
4272 * @mem: pointer to mem struct to free
4274 enum i40e_status_code
4275 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4276 struct i40e_virt_mem *mem)
4279 return I40E_ERR_PARAM;
4284 return I40E_SUCCESS;
4288 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4290 rte_spinlock_init(&sp->spinlock);
4294 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4296 rte_spinlock_lock(&sp->spinlock);
4300 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4302 rte_spinlock_unlock(&sp->spinlock);
4306 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4312 * Get the hardware capabilities, which will be parsed
4313 * and saved into struct i40e_hw.
4316 i40e_get_cap(struct i40e_hw *hw)
4318 struct i40e_aqc_list_capabilities_element_resp *buf;
4319 uint16_t len, size = 0;
4322 /* Calculate a huge enough buff for saving response data temporarily */
4323 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4324 I40E_MAX_CAP_ELE_NUM;
4325 buf = rte_zmalloc("i40e", len, 0);
4327 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4328 return I40E_ERR_NO_MEMORY;
4331 /* Get, parse the capabilities and save it to hw */
4332 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4333 i40e_aqc_opc_list_func_capabilities, NULL);
4334 if (ret != I40E_SUCCESS)
4335 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4337 /* Free the temporary buffer after being used */
4343 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4344 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4346 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4354 pf = (struct i40e_pf *)opaque;
4358 num = strtoul(value, &end, 0);
4359 if (errno != 0 || end == value || *end != 0) {
4360 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4361 "kept the value = %hu", value, pf->vf_nb_qp_max);
4365 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4366 pf->vf_nb_qp_max = (uint16_t)num;
4368 /* here return 0 to make next valid same argument work */
4369 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4370 "power of 2 and equal or less than 16 !, Now it is "
4371 "kept the value = %hu", num, pf->vf_nb_qp_max);
4376 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4378 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4379 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4380 struct rte_kvargs *kvlist;
4382 /* set default queue number per VF as 4 */
4383 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4385 if (dev->device->devargs == NULL)
4388 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4392 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4393 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4394 "the first invalid or last valid one is used !",
4395 QUEUE_NUM_PER_VF_ARG);
4397 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4398 i40e_pf_parse_vf_queue_number_handler, pf);
4400 rte_kvargs_free(kvlist);
4406 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4408 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4409 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4410 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4411 uint16_t qp_count = 0, vsi_count = 0;
4413 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4414 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4418 i40e_pf_config_vf_rxq_number(dev);
4420 /* Add the parameter init for LFC */
4421 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4422 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4423 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4425 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4426 pf->max_num_vsi = hw->func_caps.num_vsis;
4427 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4428 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4430 /* FDir queue/VSI allocation */
4431 pf->fdir_qp_offset = 0;
4432 if (hw->func_caps.fd) {
4433 pf->flags |= I40E_FLAG_FDIR;
4434 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4436 pf->fdir_nb_qps = 0;
4438 qp_count += pf->fdir_nb_qps;
4441 /* LAN queue/VSI allocation */
4442 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4443 if (!hw->func_caps.rss) {
4446 pf->flags |= I40E_FLAG_RSS;
4447 if (hw->mac.type == I40E_MAC_X722)
4448 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4449 pf->lan_nb_qps = pf->lan_nb_qp_max;
4451 qp_count += pf->lan_nb_qps;
4454 /* VF queue/VSI allocation */
4455 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4456 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4457 pf->flags |= I40E_FLAG_SRIOV;
4458 pf->vf_nb_qps = pf->vf_nb_qp_max;
4459 pf->vf_num = pci_dev->max_vfs;
4461 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4462 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4467 qp_count += pf->vf_nb_qps * pf->vf_num;
4468 vsi_count += pf->vf_num;
4470 /* VMDq queue/VSI allocation */
4471 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4472 pf->vmdq_nb_qps = 0;
4473 pf->max_nb_vmdq_vsi = 0;
4474 if (hw->func_caps.vmdq) {
4475 if (qp_count < hw->func_caps.num_tx_qp &&
4476 vsi_count < hw->func_caps.num_vsis) {
4477 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4478 qp_count) / pf->vmdq_nb_qp_max;
4480 /* Limit the maximum number of VMDq vsi to the maximum
4481 * ethdev can support
4483 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4484 hw->func_caps.num_vsis - vsi_count);
4485 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4487 if (pf->max_nb_vmdq_vsi) {
4488 pf->flags |= I40E_FLAG_VMDQ;
4489 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4491 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4492 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4493 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4496 "No enough queues left for VMDq");
4499 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4502 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4503 vsi_count += pf->max_nb_vmdq_vsi;
4505 if (hw->func_caps.dcb)
4506 pf->flags |= I40E_FLAG_DCB;
4508 if (qp_count > hw->func_caps.num_tx_qp) {
4510 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4511 qp_count, hw->func_caps.num_tx_qp);
4514 if (vsi_count > hw->func_caps.num_vsis) {
4516 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4517 vsi_count, hw->func_caps.num_vsis);
4525 i40e_pf_get_switch_config(struct i40e_pf *pf)
4527 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4528 struct i40e_aqc_get_switch_config_resp *switch_config;
4529 struct i40e_aqc_switch_config_element_resp *element;
4530 uint16_t start_seid = 0, num_reported;
4533 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4534 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4535 if (!switch_config) {
4536 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4540 /* Get the switch configurations */
4541 ret = i40e_aq_get_switch_config(hw, switch_config,
4542 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4543 if (ret != I40E_SUCCESS) {
4544 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4547 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4548 if (num_reported != 1) { /* The number should be 1 */
4549 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4553 /* Parse the switch configuration elements */
4554 element = &(switch_config->element[0]);
4555 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4556 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4557 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4559 PMD_DRV_LOG(INFO, "Unknown element type");
4562 rte_free(switch_config);
4568 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4571 struct pool_entry *entry;
4573 if (pool == NULL || num == 0)
4576 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4577 if (entry == NULL) {
4578 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4582 /* queue heap initialize */
4583 pool->num_free = num;
4584 pool->num_alloc = 0;
4586 LIST_INIT(&pool->alloc_list);
4587 LIST_INIT(&pool->free_list);
4589 /* Initialize element */
4593 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4598 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4600 struct pool_entry *entry, *next_entry;
4605 for (entry = LIST_FIRST(&pool->alloc_list);
4606 entry && (next_entry = LIST_NEXT(entry, next), 1);
4607 entry = next_entry) {
4608 LIST_REMOVE(entry, next);
4612 for (entry = LIST_FIRST(&pool->free_list);
4613 entry && (next_entry = LIST_NEXT(entry, next), 1);
4614 entry = next_entry) {
4615 LIST_REMOVE(entry, next);
4620 pool->num_alloc = 0;
4622 LIST_INIT(&pool->alloc_list);
4623 LIST_INIT(&pool->free_list);
4627 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4630 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4631 uint32_t pool_offset;
4635 PMD_DRV_LOG(ERR, "Invalid parameter");
4639 pool_offset = base - pool->base;
4640 /* Lookup in alloc list */
4641 LIST_FOREACH(entry, &pool->alloc_list, next) {
4642 if (entry->base == pool_offset) {
4643 valid_entry = entry;
4644 LIST_REMOVE(entry, next);
4649 /* Not find, return */
4650 if (valid_entry == NULL) {
4651 PMD_DRV_LOG(ERR, "Failed to find entry");
4656 * Found it, move it to free list and try to merge.
4657 * In order to make merge easier, always sort it by qbase.
4658 * Find adjacent prev and last entries.
4661 LIST_FOREACH(entry, &pool->free_list, next) {
4662 if (entry->base > valid_entry->base) {
4670 /* Try to merge with next one*/
4672 /* Merge with next one */
4673 if (valid_entry->base + valid_entry->len == next->base) {
4674 next->base = valid_entry->base;
4675 next->len += valid_entry->len;
4676 rte_free(valid_entry);
4683 /* Merge with previous one */
4684 if (prev->base + prev->len == valid_entry->base) {
4685 prev->len += valid_entry->len;
4686 /* If it merge with next one, remove next node */
4688 LIST_REMOVE(valid_entry, next);
4689 rte_free(valid_entry);
4691 rte_free(valid_entry);
4697 /* Not find any entry to merge, insert */
4700 LIST_INSERT_AFTER(prev, valid_entry, next);
4701 else if (next != NULL)
4702 LIST_INSERT_BEFORE(next, valid_entry, next);
4703 else /* It's empty list, insert to head */
4704 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4707 pool->num_free += valid_entry->len;
4708 pool->num_alloc -= valid_entry->len;
4714 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4717 struct pool_entry *entry, *valid_entry;
4719 if (pool == NULL || num == 0) {
4720 PMD_DRV_LOG(ERR, "Invalid parameter");
4724 if (pool->num_free < num) {
4725 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4726 num, pool->num_free);
4731 /* Lookup in free list and find most fit one */
4732 LIST_FOREACH(entry, &pool->free_list, next) {
4733 if (entry->len >= num) {
4735 if (entry->len == num) {
4736 valid_entry = entry;
4739 if (valid_entry == NULL || valid_entry->len > entry->len)
4740 valid_entry = entry;
4744 /* Not find one to satisfy the request, return */
4745 if (valid_entry == NULL) {
4746 PMD_DRV_LOG(ERR, "No valid entry found");
4750 * The entry have equal queue number as requested,
4751 * remove it from alloc_list.
4753 if (valid_entry->len == num) {
4754 LIST_REMOVE(valid_entry, next);
4757 * The entry have more numbers than requested,
4758 * create a new entry for alloc_list and minus its
4759 * queue base and number in free_list.
4761 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4762 if (entry == NULL) {
4764 "Failed to allocate memory for resource pool");
4767 entry->base = valid_entry->base;
4769 valid_entry->base += num;
4770 valid_entry->len -= num;
4771 valid_entry = entry;
4774 /* Insert it into alloc list, not sorted */
4775 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4777 pool->num_free -= valid_entry->len;
4778 pool->num_alloc += valid_entry->len;
4780 return valid_entry->base + pool->base;
4784 * bitmap_is_subset - Check whether src2 is subset of src1
4787 bitmap_is_subset(uint8_t src1, uint8_t src2)
4789 return !((src1 ^ src2) & src2);
4792 static enum i40e_status_code
4793 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4795 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4797 /* If DCB is not supported, only default TC is supported */
4798 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4799 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4800 return I40E_NOT_SUPPORTED;
4803 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4805 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4806 hw->func_caps.enabled_tcmap, enabled_tcmap);
4807 return I40E_NOT_SUPPORTED;
4809 return I40E_SUCCESS;
4813 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4814 struct i40e_vsi_vlan_pvid_info *info)
4817 struct i40e_vsi_context ctxt;
4818 uint8_t vlan_flags = 0;
4821 if (vsi == NULL || info == NULL) {
4822 PMD_DRV_LOG(ERR, "invalid parameters");
4823 return I40E_ERR_PARAM;
4827 vsi->info.pvid = info->config.pvid;
4829 * If insert pvid is enabled, only tagged pkts are
4830 * allowed to be sent out.
4832 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4833 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4836 if (info->config.reject.tagged == 0)
4837 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4839 if (info->config.reject.untagged == 0)
4840 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4842 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4843 I40E_AQ_VSI_PVLAN_MODE_MASK);
4844 vsi->info.port_vlan_flags |= vlan_flags;
4845 vsi->info.valid_sections =
4846 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4847 memset(&ctxt, 0, sizeof(ctxt));
4848 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4849 ctxt.seid = vsi->seid;
4851 hw = I40E_VSI_TO_HW(vsi);
4852 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4853 if (ret != I40E_SUCCESS)
4854 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4860 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4862 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4864 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4866 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4867 if (ret != I40E_SUCCESS)
4871 PMD_DRV_LOG(ERR, "seid not valid");
4875 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4876 tc_bw_data.tc_valid_bits = enabled_tcmap;
4877 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4878 tc_bw_data.tc_bw_credits[i] =
4879 (enabled_tcmap & (1 << i)) ? 1 : 0;
4881 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4882 if (ret != I40E_SUCCESS) {
4883 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4887 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4888 sizeof(vsi->info.qs_handle));
4889 return I40E_SUCCESS;
4892 static enum i40e_status_code
4893 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4894 struct i40e_aqc_vsi_properties_data *info,
4895 uint8_t enabled_tcmap)
4897 enum i40e_status_code ret;
4898 int i, total_tc = 0;
4899 uint16_t qpnum_per_tc, bsf, qp_idx;
4901 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4902 if (ret != I40E_SUCCESS)
4905 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4906 if (enabled_tcmap & (1 << i))
4910 vsi->enabled_tc = enabled_tcmap;
4912 /* Number of queues per enabled TC */
4913 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4914 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4915 bsf = rte_bsf32(qpnum_per_tc);
4917 /* Adjust the queue number to actual queues that can be applied */
4918 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4919 vsi->nb_qps = qpnum_per_tc * total_tc;
4922 * Configure TC and queue mapping parameters, for enabled TC,
4923 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4924 * default queue will serve it.
4927 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4928 if (vsi->enabled_tc & (1 << i)) {
4929 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4930 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4931 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4932 qp_idx += qpnum_per_tc;
4934 info->tc_mapping[i] = 0;
4937 /* Associate queue number with VSI */
4938 if (vsi->type == I40E_VSI_SRIOV) {
4939 info->mapping_flags |=
4940 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4941 for (i = 0; i < vsi->nb_qps; i++)
4942 info->queue_mapping[i] =
4943 rte_cpu_to_le_16(vsi->base_queue + i);
4945 info->mapping_flags |=
4946 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4947 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4949 info->valid_sections |=
4950 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4952 return I40E_SUCCESS;
4956 i40e_veb_release(struct i40e_veb *veb)
4958 struct i40e_vsi *vsi;
4964 if (!TAILQ_EMPTY(&veb->head)) {
4965 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4968 /* associate_vsi field is NULL for floating VEB */
4969 if (veb->associate_vsi != NULL) {
4970 vsi = veb->associate_vsi;
4971 hw = I40E_VSI_TO_HW(vsi);
4973 vsi->uplink_seid = veb->uplink_seid;
4976 veb->associate_pf->main_vsi->floating_veb = NULL;
4977 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4980 i40e_aq_delete_element(hw, veb->seid, NULL);
4982 return I40E_SUCCESS;
4986 static struct i40e_veb *
4987 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4989 struct i40e_veb *veb;
4995 "veb setup failed, associated PF shouldn't null");
4998 hw = I40E_PF_TO_HW(pf);
5000 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5002 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5006 veb->associate_vsi = vsi;
5007 veb->associate_pf = pf;
5008 TAILQ_INIT(&veb->head);
5009 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5011 /* create floating veb if vsi is NULL */
5013 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5014 I40E_DEFAULT_TCMAP, false,
5015 &veb->seid, false, NULL);
5017 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5018 true, &veb->seid, false, NULL);
5021 if (ret != I40E_SUCCESS) {
5022 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5023 hw->aq.asq_last_status);
5026 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5028 /* get statistics index */
5029 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5030 &veb->stats_idx, NULL, NULL, NULL);
5031 if (ret != I40E_SUCCESS) {
5032 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5033 hw->aq.asq_last_status);
5036 /* Get VEB bandwidth, to be implemented */
5037 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5039 vsi->uplink_seid = veb->seid;
5048 i40e_vsi_release(struct i40e_vsi *vsi)
5052 struct i40e_vsi_list *vsi_list;
5055 struct i40e_mac_filter *f;
5056 uint16_t user_param;
5059 return I40E_SUCCESS;
5064 user_param = vsi->user_param;
5066 pf = I40E_VSI_TO_PF(vsi);
5067 hw = I40E_VSI_TO_HW(vsi);
5069 /* VSI has child to attach, release child first */
5071 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5072 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5075 i40e_veb_release(vsi->veb);
5078 if (vsi->floating_veb) {
5079 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5080 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5085 /* Remove all macvlan filters of the VSI */
5086 i40e_vsi_remove_all_macvlan_filter(vsi);
5087 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5090 if (vsi->type != I40E_VSI_MAIN &&
5091 ((vsi->type != I40E_VSI_SRIOV) ||
5092 !pf->floating_veb_list[user_param])) {
5093 /* Remove vsi from parent's sibling list */
5094 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5095 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5096 return I40E_ERR_PARAM;
5098 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5099 &vsi->sib_vsi_list, list);
5101 /* Remove all switch element of the VSI */
5102 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5103 if (ret != I40E_SUCCESS)
5104 PMD_DRV_LOG(ERR, "Failed to delete element");
5107 if ((vsi->type == I40E_VSI_SRIOV) &&
5108 pf->floating_veb_list[user_param]) {
5109 /* Remove vsi from parent's sibling list */
5110 if (vsi->parent_vsi == NULL ||
5111 vsi->parent_vsi->floating_veb == NULL) {
5112 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5113 return I40E_ERR_PARAM;
5115 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5116 &vsi->sib_vsi_list, list);
5118 /* Remove all switch element of the VSI */
5119 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5120 if (ret != I40E_SUCCESS)
5121 PMD_DRV_LOG(ERR, "Failed to delete element");
5124 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5126 if (vsi->type != I40E_VSI_SRIOV)
5127 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5130 return I40E_SUCCESS;
5134 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5136 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5137 struct i40e_aqc_remove_macvlan_element_data def_filter;
5138 struct i40e_mac_filter_info filter;
5141 if (vsi->type != I40E_VSI_MAIN)
5142 return I40E_ERR_CONFIG;
5143 memset(&def_filter, 0, sizeof(def_filter));
5144 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5146 def_filter.vlan_tag = 0;
5147 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5148 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5149 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5150 if (ret != I40E_SUCCESS) {
5151 struct i40e_mac_filter *f;
5152 struct ether_addr *mac;
5155 "Cannot remove the default macvlan filter");
5156 /* It needs to add the permanent mac into mac list */
5157 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5159 PMD_DRV_LOG(ERR, "failed to allocate memory");
5160 return I40E_ERR_NO_MEMORY;
5162 mac = &f->mac_info.mac_addr;
5163 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5165 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5166 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5171 rte_memcpy(&filter.mac_addr,
5172 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5173 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5174 return i40e_vsi_add_mac(vsi, &filter);
5178 * i40e_vsi_get_bw_config - Query VSI BW Information
5179 * @vsi: the VSI to be queried
5181 * Returns 0 on success, negative value on failure
5183 static enum i40e_status_code
5184 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5186 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5187 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5188 struct i40e_hw *hw = &vsi->adapter->hw;
5193 memset(&bw_config, 0, sizeof(bw_config));
5194 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5195 if (ret != I40E_SUCCESS) {
5196 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5197 hw->aq.asq_last_status);
5201 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5202 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5203 &ets_sla_config, NULL);
5204 if (ret != I40E_SUCCESS) {
5206 "VSI failed to get TC bandwdith configuration %u",
5207 hw->aq.asq_last_status);
5211 /* store and print out BW info */
5212 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5213 vsi->bw_info.bw_max = bw_config.max_bw;
5214 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5215 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5216 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5217 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5219 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5220 vsi->bw_info.bw_ets_share_credits[i] =
5221 ets_sla_config.share_credits[i];
5222 vsi->bw_info.bw_ets_credits[i] =
5223 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5224 /* 4 bits per TC, 4th bit is reserved */
5225 vsi->bw_info.bw_ets_max[i] =
5226 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5227 RTE_LEN2MASK(3, uint8_t));
5228 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5229 vsi->bw_info.bw_ets_share_credits[i]);
5230 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5231 vsi->bw_info.bw_ets_credits[i]);
5232 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5233 vsi->bw_info.bw_ets_max[i]);
5236 return I40E_SUCCESS;
5239 /* i40e_enable_pf_lb
5240 * @pf: pointer to the pf structure
5242 * allow loopback on pf
5245 i40e_enable_pf_lb(struct i40e_pf *pf)
5247 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5248 struct i40e_vsi_context ctxt;
5251 /* Use the FW API if FW >= v5.0 */
5252 if (hw->aq.fw_maj_ver < 5) {
5253 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5257 memset(&ctxt, 0, sizeof(ctxt));
5258 ctxt.seid = pf->main_vsi_seid;
5259 ctxt.pf_num = hw->pf_id;
5260 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5262 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5263 ret, hw->aq.asq_last_status);
5266 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5267 ctxt.info.valid_sections =
5268 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5269 ctxt.info.switch_id |=
5270 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5272 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5274 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5275 hw->aq.asq_last_status);
5280 i40e_vsi_setup(struct i40e_pf *pf,
5281 enum i40e_vsi_type type,
5282 struct i40e_vsi *uplink_vsi,
5283 uint16_t user_param)
5285 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5286 struct i40e_vsi *vsi;
5287 struct i40e_mac_filter_info filter;
5289 struct i40e_vsi_context ctxt;
5290 struct ether_addr broadcast =
5291 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5293 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5294 uplink_vsi == NULL) {
5296 "VSI setup failed, VSI link shouldn't be NULL");
5300 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5302 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5307 * 1.type is not MAIN and uplink vsi is not NULL
5308 * If uplink vsi didn't setup VEB, create one first under veb field
5309 * 2.type is SRIOV and the uplink is NULL
5310 * If floating VEB is NULL, create one veb under floating veb field
5313 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5314 uplink_vsi->veb == NULL) {
5315 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5317 if (uplink_vsi->veb == NULL) {
5318 PMD_DRV_LOG(ERR, "VEB setup failed");
5321 /* set ALLOWLOOPBACk on pf, when veb is created */
5322 i40e_enable_pf_lb(pf);
5325 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5326 pf->main_vsi->floating_veb == NULL) {
5327 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5329 if (pf->main_vsi->floating_veb == NULL) {
5330 PMD_DRV_LOG(ERR, "VEB setup failed");
5335 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5337 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5340 TAILQ_INIT(&vsi->mac_list);
5342 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5343 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5344 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5345 vsi->user_param = user_param;
5346 vsi->vlan_anti_spoof_on = 0;
5347 vsi->vlan_filter_on = 0;
5348 /* Allocate queues */
5349 switch (vsi->type) {
5350 case I40E_VSI_MAIN :
5351 vsi->nb_qps = pf->lan_nb_qps;
5353 case I40E_VSI_SRIOV :
5354 vsi->nb_qps = pf->vf_nb_qps;
5356 case I40E_VSI_VMDQ2:
5357 vsi->nb_qps = pf->vmdq_nb_qps;
5360 vsi->nb_qps = pf->fdir_nb_qps;
5366 * The filter status descriptor is reported in rx queue 0,
5367 * while the tx queue for fdir filter programming has no
5368 * such constraints, can be non-zero queues.
5369 * To simplify it, choose FDIR vsi use queue 0 pair.
5370 * To make sure it will use queue 0 pair, queue allocation
5371 * need be done before this function is called
5373 if (type != I40E_VSI_FDIR) {
5374 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5376 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5380 vsi->base_queue = ret;
5382 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5384 /* VF has MSIX interrupt in VF range, don't allocate here */
5385 if (type == I40E_VSI_MAIN) {
5386 if (pf->support_multi_driver) {
5387 /* If support multi-driver, need to use INT0 instead of
5388 * allocating from msix pool. The Msix pool is init from
5389 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5390 * to 1 without calling i40e_res_pool_alloc.
5395 ret = i40e_res_pool_alloc(&pf->msix_pool,
5396 RTE_MIN(vsi->nb_qps,
5397 RTE_MAX_RXTX_INTR_VEC_ID));
5400 "VSI MAIN %d get heap failed %d",
5402 goto fail_queue_alloc;
5404 vsi->msix_intr = ret;
5405 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5406 RTE_MAX_RXTX_INTR_VEC_ID);
5408 } else if (type != I40E_VSI_SRIOV) {
5409 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5411 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5412 goto fail_queue_alloc;
5414 vsi->msix_intr = ret;
5422 if (type == I40E_VSI_MAIN) {
5423 /* For main VSI, no need to add since it's default one */
5424 vsi->uplink_seid = pf->mac_seid;
5425 vsi->seid = pf->main_vsi_seid;
5426 /* Bind queues with specific MSIX interrupt */
5428 * Needs 2 interrupt at least, one for misc cause which will
5429 * enabled from OS side, Another for queues binding the
5430 * interrupt from device side only.
5433 /* Get default VSI parameters from hardware */
5434 memset(&ctxt, 0, sizeof(ctxt));
5435 ctxt.seid = vsi->seid;
5436 ctxt.pf_num = hw->pf_id;
5437 ctxt.uplink_seid = vsi->uplink_seid;
5439 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5440 if (ret != I40E_SUCCESS) {
5441 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5442 goto fail_msix_alloc;
5444 rte_memcpy(&vsi->info, &ctxt.info,
5445 sizeof(struct i40e_aqc_vsi_properties_data));
5446 vsi->vsi_id = ctxt.vsi_number;
5447 vsi->info.valid_sections = 0;
5449 /* Configure tc, enabled TC0 only */
5450 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5452 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5453 goto fail_msix_alloc;
5456 /* TC, queue mapping */
5457 memset(&ctxt, 0, sizeof(ctxt));
5458 vsi->info.valid_sections |=
5459 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5460 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5461 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5462 rte_memcpy(&ctxt.info, &vsi->info,
5463 sizeof(struct i40e_aqc_vsi_properties_data));
5464 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5465 I40E_DEFAULT_TCMAP);
5466 if (ret != I40E_SUCCESS) {
5468 "Failed to configure TC queue mapping");
5469 goto fail_msix_alloc;
5471 ctxt.seid = vsi->seid;
5472 ctxt.pf_num = hw->pf_id;
5473 ctxt.uplink_seid = vsi->uplink_seid;
5476 /* Update VSI parameters */
5477 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5478 if (ret != I40E_SUCCESS) {
5479 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5480 goto fail_msix_alloc;
5483 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5484 sizeof(vsi->info.tc_mapping));
5485 rte_memcpy(&vsi->info.queue_mapping,
5486 &ctxt.info.queue_mapping,
5487 sizeof(vsi->info.queue_mapping));
5488 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5489 vsi->info.valid_sections = 0;
5491 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5495 * Updating default filter settings are necessary to prevent
5496 * reception of tagged packets.
5497 * Some old firmware configurations load a default macvlan
5498 * filter which accepts both tagged and untagged packets.
5499 * The updating is to use a normal filter instead if needed.
5500 * For NVM 4.2.2 or after, the updating is not needed anymore.
5501 * The firmware with correct configurations load the default
5502 * macvlan filter which is expected and cannot be removed.
5504 i40e_update_default_filter_setting(vsi);
5505 i40e_config_qinq(hw, vsi);
5506 } else if (type == I40E_VSI_SRIOV) {
5507 memset(&ctxt, 0, sizeof(ctxt));
5509 * For other VSI, the uplink_seid equals to uplink VSI's
5510 * uplink_seid since they share same VEB
5512 if (uplink_vsi == NULL)
5513 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5515 vsi->uplink_seid = uplink_vsi->uplink_seid;
5516 ctxt.pf_num = hw->pf_id;
5517 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5518 ctxt.uplink_seid = vsi->uplink_seid;
5519 ctxt.connection_type = 0x1;
5520 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5522 /* Use the VEB configuration if FW >= v5.0 */
5523 if (hw->aq.fw_maj_ver >= 5) {
5524 /* Configure switch ID */
5525 ctxt.info.valid_sections |=
5526 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5527 ctxt.info.switch_id =
5528 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5531 /* Configure port/vlan */
5532 ctxt.info.valid_sections |=
5533 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5534 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5535 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5536 hw->func_caps.enabled_tcmap);
5537 if (ret != I40E_SUCCESS) {
5539 "Failed to configure TC queue mapping");
5540 goto fail_msix_alloc;
5543 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5544 ctxt.info.valid_sections |=
5545 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5547 * Since VSI is not created yet, only configure parameter,
5548 * will add vsi below.
5551 i40e_config_qinq(hw, vsi);
5552 } else if (type == I40E_VSI_VMDQ2) {
5553 memset(&ctxt, 0, sizeof(ctxt));
5555 * For other VSI, the uplink_seid equals to uplink VSI's
5556 * uplink_seid since they share same VEB
5558 vsi->uplink_seid = uplink_vsi->uplink_seid;
5559 ctxt.pf_num = hw->pf_id;
5561 ctxt.uplink_seid = vsi->uplink_seid;
5562 ctxt.connection_type = 0x1;
5563 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5565 ctxt.info.valid_sections |=
5566 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5567 /* user_param carries flag to enable loop back */
5569 ctxt.info.switch_id =
5570 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5571 ctxt.info.switch_id |=
5572 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5575 /* Configure port/vlan */
5576 ctxt.info.valid_sections |=
5577 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5578 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5579 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5580 I40E_DEFAULT_TCMAP);
5581 if (ret != I40E_SUCCESS) {
5583 "Failed to configure TC queue mapping");
5584 goto fail_msix_alloc;
5586 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5587 ctxt.info.valid_sections |=
5588 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5589 } else if (type == I40E_VSI_FDIR) {
5590 memset(&ctxt, 0, sizeof(ctxt));
5591 vsi->uplink_seid = uplink_vsi->uplink_seid;
5592 ctxt.pf_num = hw->pf_id;
5594 ctxt.uplink_seid = vsi->uplink_seid;
5595 ctxt.connection_type = 0x1; /* regular data port */
5596 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5597 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5598 I40E_DEFAULT_TCMAP);
5599 if (ret != I40E_SUCCESS) {
5601 "Failed to configure TC queue mapping.");
5602 goto fail_msix_alloc;
5604 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5605 ctxt.info.valid_sections |=
5606 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5608 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5609 goto fail_msix_alloc;
5612 if (vsi->type != I40E_VSI_MAIN) {
5613 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5614 if (ret != I40E_SUCCESS) {
5615 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5616 hw->aq.asq_last_status);
5617 goto fail_msix_alloc;
5619 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5620 vsi->info.valid_sections = 0;
5621 vsi->seid = ctxt.seid;
5622 vsi->vsi_id = ctxt.vsi_number;
5623 vsi->sib_vsi_list.vsi = vsi;
5624 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5625 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5626 &vsi->sib_vsi_list, list);
5628 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5629 &vsi->sib_vsi_list, list);
5633 /* MAC/VLAN configuration */
5634 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5635 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5637 ret = i40e_vsi_add_mac(vsi, &filter);
5638 if (ret != I40E_SUCCESS) {
5639 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5640 goto fail_msix_alloc;
5643 /* Get VSI BW information */
5644 i40e_vsi_get_bw_config(vsi);
5647 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5649 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5655 /* Configure vlan filter on or off */
5657 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5660 struct i40e_mac_filter *f;
5662 struct i40e_mac_filter_info *mac_filter;
5663 enum rte_mac_filter_type desired_filter;
5664 int ret = I40E_SUCCESS;
5667 /* Filter to match MAC and VLAN */
5668 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5670 /* Filter to match only MAC */
5671 desired_filter = RTE_MAC_PERFECT_MATCH;
5676 mac_filter = rte_zmalloc("mac_filter_info_data",
5677 num * sizeof(*mac_filter), 0);
5678 if (mac_filter == NULL) {
5679 PMD_DRV_LOG(ERR, "failed to allocate memory");
5680 return I40E_ERR_NO_MEMORY;
5685 /* Remove all existing mac */
5686 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5687 mac_filter[i] = f->mac_info;
5688 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5690 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5691 on ? "enable" : "disable");
5697 /* Override with new filter */
5698 for (i = 0; i < num; i++) {
5699 mac_filter[i].filter_type = desired_filter;
5700 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5702 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5703 on ? "enable" : "disable");
5709 rte_free(mac_filter);
5713 /* Configure vlan stripping on or off */
5715 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5717 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5718 struct i40e_vsi_context ctxt;
5720 int ret = I40E_SUCCESS;
5722 /* Check if it has been already on or off */
5723 if (vsi->info.valid_sections &
5724 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5726 if ((vsi->info.port_vlan_flags &
5727 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5728 return 0; /* already on */
5730 if ((vsi->info.port_vlan_flags &
5731 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5732 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5733 return 0; /* already off */
5738 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5740 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5741 vsi->info.valid_sections =
5742 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5743 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5744 vsi->info.port_vlan_flags |= vlan_flags;
5745 ctxt.seid = vsi->seid;
5746 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5747 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5749 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5750 on ? "enable" : "disable");
5756 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5758 struct rte_eth_dev_data *data = dev->data;
5762 /* Apply vlan offload setting */
5763 mask = ETH_VLAN_STRIP_MASK |
5764 ETH_VLAN_FILTER_MASK |
5765 ETH_VLAN_EXTEND_MASK;
5766 ret = i40e_vlan_offload_set(dev, mask);
5768 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5772 /* Apply pvid setting */
5773 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5774 data->dev_conf.txmode.hw_vlan_insert_pvid);
5776 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5782 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5784 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5786 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5790 i40e_update_flow_control(struct i40e_hw *hw)
5792 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5793 struct i40e_link_status link_status;
5794 uint32_t rxfc = 0, txfc = 0, reg;
5798 memset(&link_status, 0, sizeof(link_status));
5799 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5800 if (ret != I40E_SUCCESS) {
5801 PMD_DRV_LOG(ERR, "Failed to get link status information");
5802 goto write_reg; /* Disable flow control */
5805 an_info = hw->phy.link_info.an_info;
5806 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5807 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5808 ret = I40E_ERR_NOT_READY;
5809 goto write_reg; /* Disable flow control */
5812 * If link auto negotiation is enabled, flow control needs to
5813 * be configured according to it
5815 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5816 case I40E_LINK_PAUSE_RXTX:
5819 hw->fc.current_mode = I40E_FC_FULL;
5821 case I40E_AQ_LINK_PAUSE_RX:
5823 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5825 case I40E_AQ_LINK_PAUSE_TX:
5827 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5830 hw->fc.current_mode = I40E_FC_NONE;
5835 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5836 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5837 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5838 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5839 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5840 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5847 i40e_pf_setup(struct i40e_pf *pf)
5849 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5850 struct i40e_filter_control_settings settings;
5851 struct i40e_vsi *vsi;
5854 /* Clear all stats counters */
5855 pf->offset_loaded = FALSE;
5856 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5857 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5858 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5859 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5861 ret = i40e_pf_get_switch_config(pf);
5862 if (ret != I40E_SUCCESS) {
5863 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5867 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5869 PMD_INIT_LOG(WARNING,
5870 "failed to allocate switch domain for device %d", ret);
5872 if (pf->flags & I40E_FLAG_FDIR) {
5873 /* make queue allocated first, let FDIR use queue pair 0*/
5874 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5875 if (ret != I40E_FDIR_QUEUE_ID) {
5877 "queue allocation fails for FDIR: ret =%d",
5879 pf->flags &= ~I40E_FLAG_FDIR;
5882 /* main VSI setup */
5883 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5885 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5886 return I40E_ERR_NOT_READY;
5890 /* Configure filter control */
5891 memset(&settings, 0, sizeof(settings));
5892 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5893 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5894 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5895 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5897 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5898 hw->func_caps.rss_table_size);
5899 return I40E_ERR_PARAM;
5901 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5902 hw->func_caps.rss_table_size);
5903 pf->hash_lut_size = hw->func_caps.rss_table_size;
5905 /* Enable ethtype and macvlan filters */
5906 settings.enable_ethtype = TRUE;
5907 settings.enable_macvlan = TRUE;
5908 ret = i40e_set_filter_control(hw, &settings);
5910 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5913 /* Update flow control according to the auto negotiation */
5914 i40e_update_flow_control(hw);
5916 return I40E_SUCCESS;
5920 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5926 * Set or clear TX Queue Disable flags,
5927 * which is required by hardware.
5929 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5930 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5932 /* Wait until the request is finished */
5933 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5934 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5935 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5936 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5937 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5943 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5944 return I40E_SUCCESS; /* already on, skip next steps */
5946 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5947 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5949 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5950 return I40E_SUCCESS; /* already off, skip next steps */
5951 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5953 /* Write the register */
5954 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5955 /* Check the result */
5956 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5957 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5958 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5960 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5961 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5964 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5965 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5969 /* Check if it is timeout */
5970 if (j >= I40E_CHK_Q_ENA_COUNT) {
5971 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5972 (on ? "enable" : "disable"), q_idx);
5973 return I40E_ERR_TIMEOUT;
5976 return I40E_SUCCESS;
5979 /* Swith on or off the tx queues */
5981 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5983 struct rte_eth_dev_data *dev_data = pf->dev_data;
5984 struct i40e_tx_queue *txq;
5985 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5989 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5990 txq = dev_data->tx_queues[i];
5991 /* Don't operate the queue if not configured or
5992 * if starting only per queue */
5993 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5996 ret = i40e_dev_tx_queue_start(dev, i);
5998 ret = i40e_dev_tx_queue_stop(dev, i);
5999 if ( ret != I40E_SUCCESS)
6003 return I40E_SUCCESS;
6007 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6012 /* Wait until the request is finished */
6013 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6014 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6015 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6016 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6017 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6022 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6023 return I40E_SUCCESS; /* Already on, skip next steps */
6024 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6026 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6027 return I40E_SUCCESS; /* Already off, skip next steps */
6028 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6031 /* Write the register */
6032 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6033 /* Check the result */
6034 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6035 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6036 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6038 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6039 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6042 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6043 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6048 /* Check if it is timeout */
6049 if (j >= I40E_CHK_Q_ENA_COUNT) {
6050 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6051 (on ? "enable" : "disable"), q_idx);
6052 return I40E_ERR_TIMEOUT;
6055 return I40E_SUCCESS;
6057 /* Switch on or off the rx queues */
6059 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6061 struct rte_eth_dev_data *dev_data = pf->dev_data;
6062 struct i40e_rx_queue *rxq;
6063 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6067 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6068 rxq = dev_data->rx_queues[i];
6069 /* Don't operate the queue if not configured or
6070 * if starting only per queue */
6071 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6074 ret = i40e_dev_rx_queue_start(dev, i);
6076 ret = i40e_dev_rx_queue_stop(dev, i);
6077 if (ret != I40E_SUCCESS)
6081 return I40E_SUCCESS;
6084 /* Switch on or off all the rx/tx queues */
6086 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6091 /* enable rx queues before enabling tx queues */
6092 ret = i40e_dev_switch_rx_queues(pf, on);
6094 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6097 ret = i40e_dev_switch_tx_queues(pf, on);
6099 /* Stop tx queues before stopping rx queues */
6100 ret = i40e_dev_switch_tx_queues(pf, on);
6102 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6105 ret = i40e_dev_switch_rx_queues(pf, on);
6111 /* Initialize VSI for TX */
6113 i40e_dev_tx_init(struct i40e_pf *pf)
6115 struct rte_eth_dev_data *data = pf->dev_data;
6117 uint32_t ret = I40E_SUCCESS;
6118 struct i40e_tx_queue *txq;
6120 for (i = 0; i < data->nb_tx_queues; i++) {
6121 txq = data->tx_queues[i];
6122 if (!txq || !txq->q_set)
6124 ret = i40e_tx_queue_init(txq);
6125 if (ret != I40E_SUCCESS)
6128 if (ret == I40E_SUCCESS)
6129 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6135 /* Initialize VSI for RX */
6137 i40e_dev_rx_init(struct i40e_pf *pf)
6139 struct rte_eth_dev_data *data = pf->dev_data;
6140 int ret = I40E_SUCCESS;
6142 struct i40e_rx_queue *rxq;
6144 i40e_pf_config_mq_rx(pf);
6145 for (i = 0; i < data->nb_rx_queues; i++) {
6146 rxq = data->rx_queues[i];
6147 if (!rxq || !rxq->q_set)
6150 ret = i40e_rx_queue_init(rxq);
6151 if (ret != I40E_SUCCESS) {
6153 "Failed to do RX queue initialization");
6157 if (ret == I40E_SUCCESS)
6158 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6165 i40e_dev_rxtx_init(struct i40e_pf *pf)
6169 err = i40e_dev_tx_init(pf);
6171 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6174 err = i40e_dev_rx_init(pf);
6176 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6184 i40e_vmdq_setup(struct rte_eth_dev *dev)
6186 struct rte_eth_conf *conf = &dev->data->dev_conf;
6187 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6188 int i, err, conf_vsis, j, loop;
6189 struct i40e_vsi *vsi;
6190 struct i40e_vmdq_info *vmdq_info;
6191 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6192 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6195 * Disable interrupt to avoid message from VF. Furthermore, it will
6196 * avoid race condition in VSI creation/destroy.
6198 i40e_pf_disable_irq0(hw);
6200 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6201 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6205 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6206 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6207 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6208 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6209 pf->max_nb_vmdq_vsi);
6213 if (pf->vmdq != NULL) {
6214 PMD_INIT_LOG(INFO, "VMDQ already configured");
6218 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6219 sizeof(*vmdq_info) * conf_vsis, 0);
6221 if (pf->vmdq == NULL) {
6222 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6226 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6228 /* Create VMDQ VSI */
6229 for (i = 0; i < conf_vsis; i++) {
6230 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6231 vmdq_conf->enable_loop_back);
6233 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6237 vmdq_info = &pf->vmdq[i];
6239 vmdq_info->vsi = vsi;
6241 pf->nb_cfg_vmdq_vsi = conf_vsis;
6243 /* Configure Vlan */
6244 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6245 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6246 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6247 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6248 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6249 vmdq_conf->pool_map[i].vlan_id, j);
6251 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6252 vmdq_conf->pool_map[i].vlan_id);
6254 PMD_INIT_LOG(ERR, "Failed to add vlan");
6262 i40e_pf_enable_irq0(hw);
6267 for (i = 0; i < conf_vsis; i++)
6268 if (pf->vmdq[i].vsi == NULL)
6271 i40e_vsi_release(pf->vmdq[i].vsi);
6275 i40e_pf_enable_irq0(hw);
6280 i40e_stat_update_32(struct i40e_hw *hw,
6288 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6292 if (new_data >= *offset)
6293 *stat = (uint64_t)(new_data - *offset);
6295 *stat = (uint64_t)((new_data +
6296 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6300 i40e_stat_update_48(struct i40e_hw *hw,
6309 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6310 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6311 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6316 if (new_data >= *offset)
6317 *stat = new_data - *offset;
6319 *stat = (uint64_t)((new_data +
6320 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6322 *stat &= I40E_48_BIT_MASK;
6327 i40e_pf_disable_irq0(struct i40e_hw *hw)
6329 /* Disable all interrupt types */
6330 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6331 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6332 I40E_WRITE_FLUSH(hw);
6337 i40e_pf_enable_irq0(struct i40e_hw *hw)
6339 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6340 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6341 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6342 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6343 I40E_WRITE_FLUSH(hw);
6347 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6349 /* read pending request and disable first */
6350 i40e_pf_disable_irq0(hw);
6351 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6352 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6353 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6356 /* Link no queues with irq0 */
6357 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6358 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6362 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6364 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6365 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6368 uint32_t index, offset, val;
6373 * Try to find which VF trigger a reset, use absolute VF id to access
6374 * since the reg is global register.
6376 for (i = 0; i < pf->vf_num; i++) {
6377 abs_vf_id = hw->func_caps.vf_base_id + i;
6378 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6379 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6380 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6381 /* VFR event occurred */
6382 if (val & (0x1 << offset)) {
6385 /* Clear the event first */
6386 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6388 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6390 * Only notify a VF reset event occurred,
6391 * don't trigger another SW reset
6393 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6394 if (ret != I40E_SUCCESS)
6395 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6401 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6403 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6406 for (i = 0; i < pf->vf_num; i++)
6407 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6411 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6413 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6414 struct i40e_arq_event_info info;
6415 uint16_t pending, opcode;
6418 info.buf_len = I40E_AQ_BUF_SZ;
6419 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6420 if (!info.msg_buf) {
6421 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6427 ret = i40e_clean_arq_element(hw, &info, &pending);
6429 if (ret != I40E_SUCCESS) {
6431 "Failed to read msg from AdminQ, aq_err: %u",
6432 hw->aq.asq_last_status);
6435 opcode = rte_le_to_cpu_16(info.desc.opcode);
6438 case i40e_aqc_opc_send_msg_to_pf:
6439 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6440 i40e_pf_host_handle_vf_msg(dev,
6441 rte_le_to_cpu_16(info.desc.retval),
6442 rte_le_to_cpu_32(info.desc.cookie_high),
6443 rte_le_to_cpu_32(info.desc.cookie_low),
6447 case i40e_aqc_opc_get_link_status:
6448 ret = i40e_dev_link_update(dev, 0);
6450 _rte_eth_dev_callback_process(dev,
6451 RTE_ETH_EVENT_INTR_LSC, NULL);
6454 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6459 rte_free(info.msg_buf);
6463 * Interrupt handler triggered by NIC for handling
6464 * specific interrupt.
6467 * Pointer to interrupt handle.
6469 * The address of parameter (struct rte_eth_dev *) regsitered before.
6475 i40e_dev_interrupt_handler(void *param)
6477 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6478 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6481 /* Disable interrupt */
6482 i40e_pf_disable_irq0(hw);
6484 /* read out interrupt causes */
6485 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6487 /* No interrupt event indicated */
6488 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6489 PMD_DRV_LOG(INFO, "No interrupt event");
6492 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6493 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6494 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6495 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6496 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6497 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6498 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6499 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6500 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6501 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6502 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6503 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6504 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6505 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6507 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6508 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6509 i40e_dev_handle_vfr_event(dev);
6511 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6512 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6513 i40e_dev_handle_aq_msg(dev);
6517 /* Enable interrupt */
6518 i40e_pf_enable_irq0(hw);
6519 rte_intr_enable(dev->intr_handle);
6523 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6524 struct i40e_macvlan_filter *filter,
6527 int ele_num, ele_buff_size;
6528 int num, actual_num, i;
6530 int ret = I40E_SUCCESS;
6531 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6532 struct i40e_aqc_add_macvlan_element_data *req_list;
6534 if (filter == NULL || total == 0)
6535 return I40E_ERR_PARAM;
6536 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6537 ele_buff_size = hw->aq.asq_buf_size;
6539 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6540 if (req_list == NULL) {
6541 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6542 return I40E_ERR_NO_MEMORY;
6547 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6548 memset(req_list, 0, ele_buff_size);
6550 for (i = 0; i < actual_num; i++) {
6551 rte_memcpy(req_list[i].mac_addr,
6552 &filter[num + i].macaddr, ETH_ADDR_LEN);
6553 req_list[i].vlan_tag =
6554 rte_cpu_to_le_16(filter[num + i].vlan_id);
6556 switch (filter[num + i].filter_type) {
6557 case RTE_MAC_PERFECT_MATCH:
6558 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6559 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6561 case RTE_MACVLAN_PERFECT_MATCH:
6562 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6564 case RTE_MAC_HASH_MATCH:
6565 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6566 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6568 case RTE_MACVLAN_HASH_MATCH:
6569 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6572 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6573 ret = I40E_ERR_PARAM;
6577 req_list[i].queue_number = 0;
6579 req_list[i].flags = rte_cpu_to_le_16(flags);
6582 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6584 if (ret != I40E_SUCCESS) {
6585 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6589 } while (num < total);
6597 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6598 struct i40e_macvlan_filter *filter,
6601 int ele_num, ele_buff_size;
6602 int num, actual_num, i;
6604 int ret = I40E_SUCCESS;
6605 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6606 struct i40e_aqc_remove_macvlan_element_data *req_list;
6608 if (filter == NULL || total == 0)
6609 return I40E_ERR_PARAM;
6611 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6612 ele_buff_size = hw->aq.asq_buf_size;
6614 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6615 if (req_list == NULL) {
6616 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6617 return I40E_ERR_NO_MEMORY;
6622 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6623 memset(req_list, 0, ele_buff_size);
6625 for (i = 0; i < actual_num; i++) {
6626 rte_memcpy(req_list[i].mac_addr,
6627 &filter[num + i].macaddr, ETH_ADDR_LEN);
6628 req_list[i].vlan_tag =
6629 rte_cpu_to_le_16(filter[num + i].vlan_id);
6631 switch (filter[num + i].filter_type) {
6632 case RTE_MAC_PERFECT_MATCH:
6633 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6634 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6636 case RTE_MACVLAN_PERFECT_MATCH:
6637 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6639 case RTE_MAC_HASH_MATCH:
6640 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6641 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6643 case RTE_MACVLAN_HASH_MATCH:
6644 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6647 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6648 ret = I40E_ERR_PARAM;
6651 req_list[i].flags = rte_cpu_to_le_16(flags);
6654 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6656 if (ret != I40E_SUCCESS) {
6657 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6661 } while (num < total);
6668 /* Find out specific MAC filter */
6669 static struct i40e_mac_filter *
6670 i40e_find_mac_filter(struct i40e_vsi *vsi,
6671 struct ether_addr *macaddr)
6673 struct i40e_mac_filter *f;
6675 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6676 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6684 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6687 uint32_t vid_idx, vid_bit;
6689 if (vlan_id > ETH_VLAN_ID_MAX)
6692 vid_idx = I40E_VFTA_IDX(vlan_id);
6693 vid_bit = I40E_VFTA_BIT(vlan_id);
6695 if (vsi->vfta[vid_idx] & vid_bit)
6702 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6703 uint16_t vlan_id, bool on)
6705 uint32_t vid_idx, vid_bit;
6707 vid_idx = I40E_VFTA_IDX(vlan_id);
6708 vid_bit = I40E_VFTA_BIT(vlan_id);
6711 vsi->vfta[vid_idx] |= vid_bit;
6713 vsi->vfta[vid_idx] &= ~vid_bit;
6717 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6718 uint16_t vlan_id, bool on)
6720 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6721 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6724 if (vlan_id > ETH_VLAN_ID_MAX)
6727 i40e_store_vlan_filter(vsi, vlan_id, on);
6729 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6732 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6735 ret = i40e_aq_add_vlan(hw, vsi->seid,
6736 &vlan_data, 1, NULL);
6737 if (ret != I40E_SUCCESS)
6738 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6740 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6741 &vlan_data, 1, NULL);
6742 if (ret != I40E_SUCCESS)
6744 "Failed to remove vlan filter");
6749 * Find all vlan options for specific mac addr,
6750 * return with actual vlan found.
6753 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6754 struct i40e_macvlan_filter *mv_f,
6755 int num, struct ether_addr *addr)
6761 * Not to use i40e_find_vlan_filter to decrease the loop time,
6762 * although the code looks complex.
6764 if (num < vsi->vlan_num)
6765 return I40E_ERR_PARAM;
6768 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6770 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6771 if (vsi->vfta[j] & (1 << k)) {
6774 "vlan number doesn't match");
6775 return I40E_ERR_PARAM;
6777 rte_memcpy(&mv_f[i].macaddr,
6778 addr, ETH_ADDR_LEN);
6780 j * I40E_UINT32_BIT_SIZE + k;
6786 return I40E_SUCCESS;
6790 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6791 struct i40e_macvlan_filter *mv_f,
6796 struct i40e_mac_filter *f;
6798 if (num < vsi->mac_num)
6799 return I40E_ERR_PARAM;
6801 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6803 PMD_DRV_LOG(ERR, "buffer number not match");
6804 return I40E_ERR_PARAM;
6806 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6808 mv_f[i].vlan_id = vlan;
6809 mv_f[i].filter_type = f->mac_info.filter_type;
6813 return I40E_SUCCESS;
6817 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6820 struct i40e_mac_filter *f;
6821 struct i40e_macvlan_filter *mv_f;
6822 int ret = I40E_SUCCESS;
6824 if (vsi == NULL || vsi->mac_num == 0)
6825 return I40E_ERR_PARAM;
6827 /* Case that no vlan is set */
6828 if (vsi->vlan_num == 0)
6831 num = vsi->mac_num * vsi->vlan_num;
6833 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6835 PMD_DRV_LOG(ERR, "failed to allocate memory");
6836 return I40E_ERR_NO_MEMORY;
6840 if (vsi->vlan_num == 0) {
6841 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6842 rte_memcpy(&mv_f[i].macaddr,
6843 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6844 mv_f[i].filter_type = f->mac_info.filter_type;
6845 mv_f[i].vlan_id = 0;
6849 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6850 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6851 vsi->vlan_num, &f->mac_info.mac_addr);
6852 if (ret != I40E_SUCCESS)
6854 for (j = i; j < i + vsi->vlan_num; j++)
6855 mv_f[j].filter_type = f->mac_info.filter_type;
6860 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6868 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6870 struct i40e_macvlan_filter *mv_f;
6872 int ret = I40E_SUCCESS;
6874 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6875 return I40E_ERR_PARAM;
6877 /* If it's already set, just return */
6878 if (i40e_find_vlan_filter(vsi,vlan))
6879 return I40E_SUCCESS;
6881 mac_num = vsi->mac_num;
6884 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6885 return I40E_ERR_PARAM;
6888 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6891 PMD_DRV_LOG(ERR, "failed to allocate memory");
6892 return I40E_ERR_NO_MEMORY;
6895 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6897 if (ret != I40E_SUCCESS)
6900 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6902 if (ret != I40E_SUCCESS)
6905 i40e_set_vlan_filter(vsi, vlan, 1);
6915 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6917 struct i40e_macvlan_filter *mv_f;
6919 int ret = I40E_SUCCESS;
6922 * Vlan 0 is the generic filter for untagged packets
6923 * and can't be removed.
6925 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6926 return I40E_ERR_PARAM;
6928 /* If can't find it, just return */
6929 if (!i40e_find_vlan_filter(vsi, vlan))
6930 return I40E_ERR_PARAM;
6932 mac_num = vsi->mac_num;
6935 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6936 return I40E_ERR_PARAM;
6939 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6942 PMD_DRV_LOG(ERR, "failed to allocate memory");
6943 return I40E_ERR_NO_MEMORY;
6946 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6948 if (ret != I40E_SUCCESS)
6951 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6953 if (ret != I40E_SUCCESS)
6956 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6957 if (vsi->vlan_num == 1) {
6958 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6959 if (ret != I40E_SUCCESS)
6962 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6963 if (ret != I40E_SUCCESS)
6967 i40e_set_vlan_filter(vsi, vlan, 0);
6977 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6979 struct i40e_mac_filter *f;
6980 struct i40e_macvlan_filter *mv_f;
6981 int i, vlan_num = 0;
6982 int ret = I40E_SUCCESS;
6984 /* If it's add and we've config it, return */
6985 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6987 return I40E_SUCCESS;
6988 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6989 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6992 * If vlan_num is 0, that's the first time to add mac,
6993 * set mask for vlan_id 0.
6995 if (vsi->vlan_num == 0) {
6996 i40e_set_vlan_filter(vsi, 0, 1);
6999 vlan_num = vsi->vlan_num;
7000 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7001 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7004 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7006 PMD_DRV_LOG(ERR, "failed to allocate memory");
7007 return I40E_ERR_NO_MEMORY;
7010 for (i = 0; i < vlan_num; i++) {
7011 mv_f[i].filter_type = mac_filter->filter_type;
7012 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7016 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7017 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7018 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7019 &mac_filter->mac_addr);
7020 if (ret != I40E_SUCCESS)
7024 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7025 if (ret != I40E_SUCCESS)
7028 /* Add the mac addr into mac list */
7029 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7031 PMD_DRV_LOG(ERR, "failed to allocate memory");
7032 ret = I40E_ERR_NO_MEMORY;
7035 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7037 f->mac_info.filter_type = mac_filter->filter_type;
7038 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7049 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7051 struct i40e_mac_filter *f;
7052 struct i40e_macvlan_filter *mv_f;
7054 enum rte_mac_filter_type filter_type;
7055 int ret = I40E_SUCCESS;
7057 /* Can't find it, return an error */
7058 f = i40e_find_mac_filter(vsi, addr);
7060 return I40E_ERR_PARAM;
7062 vlan_num = vsi->vlan_num;
7063 filter_type = f->mac_info.filter_type;
7064 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7065 filter_type == RTE_MACVLAN_HASH_MATCH) {
7066 if (vlan_num == 0) {
7067 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7068 return I40E_ERR_PARAM;
7070 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7071 filter_type == RTE_MAC_HASH_MATCH)
7074 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7076 PMD_DRV_LOG(ERR, "failed to allocate memory");
7077 return I40E_ERR_NO_MEMORY;
7080 for (i = 0; i < vlan_num; i++) {
7081 mv_f[i].filter_type = filter_type;
7082 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7085 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7086 filter_type == RTE_MACVLAN_HASH_MATCH) {
7087 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7088 if (ret != I40E_SUCCESS)
7092 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7093 if (ret != I40E_SUCCESS)
7096 /* Remove the mac addr into mac list */
7097 TAILQ_REMOVE(&vsi->mac_list, f, next);
7107 /* Configure hash enable flags for RSS */
7109 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7117 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7118 if (flags & (1ULL << i))
7119 hena |= adapter->pctypes_tbl[i];
7125 /* Parse the hash enable flags */
7127 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7129 uint64_t rss_hf = 0;
7135 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7136 if (flags & adapter->pctypes_tbl[i])
7137 rss_hf |= (1ULL << i);
7144 i40e_pf_disable_rss(struct i40e_pf *pf)
7146 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7148 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7149 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7150 I40E_WRITE_FLUSH(hw);
7154 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7156 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7157 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7158 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7159 I40E_VFQF_HKEY_MAX_INDEX :
7160 I40E_PFQF_HKEY_MAX_INDEX;
7163 if (!key || key_len == 0) {
7164 PMD_DRV_LOG(DEBUG, "No key to be configured");
7166 } else if (key_len != (key_idx + 1) *
7168 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7172 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7173 struct i40e_aqc_get_set_rss_key_data *key_dw =
7174 (struct i40e_aqc_get_set_rss_key_data *)key;
7176 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7178 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7180 uint32_t *hash_key = (uint32_t *)key;
7183 if (vsi->type == I40E_VSI_SRIOV) {
7184 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7187 I40E_VFQF_HKEY1(i, vsi->user_param),
7191 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7192 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7195 I40E_WRITE_FLUSH(hw);
7202 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7204 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7205 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7209 if (!key || !key_len)
7212 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7213 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7214 (struct i40e_aqc_get_set_rss_key_data *)key);
7216 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7220 uint32_t *key_dw = (uint32_t *)key;
7223 if (vsi->type == I40E_VSI_SRIOV) {
7224 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7225 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7226 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7228 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7231 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7232 reg = I40E_PFQF_HKEY(i);
7233 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7235 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7243 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7245 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7249 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7250 rss_conf->rss_key_len);
7254 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7255 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7256 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7257 I40E_WRITE_FLUSH(hw);
7263 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7264 struct rte_eth_rss_conf *rss_conf)
7266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7268 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7271 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7272 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7274 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7275 if (rss_hf != 0) /* Enable RSS */
7277 return 0; /* Nothing to do */
7280 if (rss_hf == 0) /* Disable RSS */
7283 return i40e_hw_rss_hash_set(pf, rss_conf);
7287 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7288 struct rte_eth_rss_conf *rss_conf)
7290 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7291 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7295 &rss_conf->rss_key_len);
7297 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7298 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7299 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7305 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7307 switch (filter_type) {
7308 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7309 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7311 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7312 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7314 case RTE_TUNNEL_FILTER_IMAC_TENID:
7315 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7317 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7318 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7320 case ETH_TUNNEL_FILTER_IMAC:
7321 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7323 case ETH_TUNNEL_FILTER_OIP:
7324 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7326 case ETH_TUNNEL_FILTER_IIP:
7327 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7330 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7337 /* Convert tunnel filter structure */
7339 i40e_tunnel_filter_convert(
7340 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7341 struct i40e_tunnel_filter *tunnel_filter)
7343 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7344 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7345 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7346 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7347 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7348 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7349 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7350 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7351 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7353 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7354 tunnel_filter->input.flags = cld_filter->element.flags;
7355 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7356 tunnel_filter->queue = cld_filter->element.queue_number;
7357 rte_memcpy(tunnel_filter->input.general_fields,
7358 cld_filter->general_fields,
7359 sizeof(cld_filter->general_fields));
7364 /* Check if there exists the tunnel filter */
7365 struct i40e_tunnel_filter *
7366 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7367 const struct i40e_tunnel_filter_input *input)
7371 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7375 return tunnel_rule->hash_map[ret];
7378 /* Add a tunnel filter into the SW list */
7380 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7381 struct i40e_tunnel_filter *tunnel_filter)
7383 struct i40e_tunnel_rule *rule = &pf->tunnel;
7386 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7389 "Failed to insert tunnel filter to hash table %d!",
7393 rule->hash_map[ret] = tunnel_filter;
7395 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7400 /* Delete a tunnel filter from the SW list */
7402 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7403 struct i40e_tunnel_filter_input *input)
7405 struct i40e_tunnel_rule *rule = &pf->tunnel;
7406 struct i40e_tunnel_filter *tunnel_filter;
7409 ret = rte_hash_del_key(rule->hash_table, input);
7412 "Failed to delete tunnel filter to hash table %d!",
7416 tunnel_filter = rule->hash_map[ret];
7417 rule->hash_map[ret] = NULL;
7419 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7420 rte_free(tunnel_filter);
7426 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7427 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7431 uint32_t ipv4_addr, ipv4_addr_le;
7432 uint8_t i, tun_type = 0;
7433 /* internal varialbe to convert ipv6 byte order */
7434 uint32_t convert_ipv6[4];
7436 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7437 struct i40e_vsi *vsi = pf->main_vsi;
7438 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7439 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7440 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7441 struct i40e_tunnel_filter *tunnel, *node;
7442 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7444 cld_filter = rte_zmalloc("tunnel_filter",
7445 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7448 if (NULL == cld_filter) {
7449 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7452 pfilter = cld_filter;
7454 ether_addr_copy(&tunnel_filter->outer_mac,
7455 (struct ether_addr *)&pfilter->element.outer_mac);
7456 ether_addr_copy(&tunnel_filter->inner_mac,
7457 (struct ether_addr *)&pfilter->element.inner_mac);
7459 pfilter->element.inner_vlan =
7460 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7461 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7462 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7463 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7464 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7465 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7467 sizeof(pfilter->element.ipaddr.v4.data));
7469 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7470 for (i = 0; i < 4; i++) {
7472 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7474 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7476 sizeof(pfilter->element.ipaddr.v6.data));
7479 /* check tunneled type */
7480 switch (tunnel_filter->tunnel_type) {
7481 case RTE_TUNNEL_TYPE_VXLAN:
7482 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7484 case RTE_TUNNEL_TYPE_NVGRE:
7485 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7487 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7488 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7491 /* Other tunnel types is not supported. */
7492 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7493 rte_free(cld_filter);
7497 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7498 &pfilter->element.flags);
7500 rte_free(cld_filter);
7504 pfilter->element.flags |= rte_cpu_to_le_16(
7505 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7506 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7507 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7508 pfilter->element.queue_number =
7509 rte_cpu_to_le_16(tunnel_filter->queue_id);
7511 /* Check if there is the filter in SW list */
7512 memset(&check_filter, 0, sizeof(check_filter));
7513 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7514 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7516 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7517 rte_free(cld_filter);
7521 if (!add && !node) {
7522 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7523 rte_free(cld_filter);
7528 ret = i40e_aq_add_cloud_filters(hw,
7529 vsi->seid, &cld_filter->element, 1);
7531 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7532 rte_free(cld_filter);
7535 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7536 if (tunnel == NULL) {
7537 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7538 rte_free(cld_filter);
7542 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7543 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7547 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7548 &cld_filter->element, 1);
7550 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7551 rte_free(cld_filter);
7554 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7557 rte_free(cld_filter);
7561 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7562 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7563 #define I40E_TR_GENEVE_KEY_MASK 0x8
7564 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7565 #define I40E_TR_GRE_KEY_MASK 0x400
7566 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7567 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7570 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7572 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7573 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7574 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7575 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7576 enum i40e_status_code status = I40E_SUCCESS;
7578 if (pf->support_multi_driver) {
7579 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7580 return I40E_NOT_SUPPORTED;
7583 memset(&filter_replace, 0,
7584 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7585 memset(&filter_replace_buf, 0,
7586 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7588 /* create L1 filter */
7589 filter_replace.old_filter_type =
7590 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7591 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7592 filter_replace.tr_bit = 0;
7594 /* Prepare the buffer, 3 entries */
7595 filter_replace_buf.data[0] =
7596 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7597 filter_replace_buf.data[0] |=
7598 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7599 filter_replace_buf.data[2] = 0xFF;
7600 filter_replace_buf.data[3] = 0xFF;
7601 filter_replace_buf.data[4] =
7602 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7603 filter_replace_buf.data[4] |=
7604 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7605 filter_replace_buf.data[7] = 0xF0;
7606 filter_replace_buf.data[8]
7607 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7608 filter_replace_buf.data[8] |=
7609 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7610 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7611 I40E_TR_GENEVE_KEY_MASK |
7612 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7613 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7614 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7615 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7617 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7618 &filter_replace_buf);
7619 if (!status && (filter_replace.old_filter_type !=
7620 filter_replace.new_filter_type)) {
7621 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7622 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7623 " original: 0x%x, new: 0x%x",
7625 filter_replace.old_filter_type,
7626 filter_replace.new_filter_type);
7632 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7634 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7635 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7636 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7637 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7638 enum i40e_status_code status = I40E_SUCCESS;
7640 if (pf->support_multi_driver) {
7641 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7642 return I40E_NOT_SUPPORTED;
7646 memset(&filter_replace, 0,
7647 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7648 memset(&filter_replace_buf, 0,
7649 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7650 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7651 I40E_AQC_MIRROR_CLOUD_FILTER;
7652 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7653 filter_replace.new_filter_type =
7654 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7655 /* Prepare the buffer, 2 entries */
7656 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7657 filter_replace_buf.data[0] |=
7658 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7659 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7660 filter_replace_buf.data[4] |=
7661 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7662 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7663 &filter_replace_buf);
7666 if (filter_replace.old_filter_type !=
7667 filter_replace.new_filter_type)
7668 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7669 " original: 0x%x, new: 0x%x",
7671 filter_replace.old_filter_type,
7672 filter_replace.new_filter_type);
7675 memset(&filter_replace, 0,
7676 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7677 memset(&filter_replace_buf, 0,
7678 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7680 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7681 I40E_AQC_MIRROR_CLOUD_FILTER;
7682 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7683 filter_replace.new_filter_type =
7684 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7685 /* Prepare the buffer, 2 entries */
7686 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7687 filter_replace_buf.data[0] |=
7688 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7689 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7690 filter_replace_buf.data[4] |=
7691 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7693 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7694 &filter_replace_buf);
7695 if (!status && (filter_replace.old_filter_type !=
7696 filter_replace.new_filter_type)) {
7697 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7698 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7699 " original: 0x%x, new: 0x%x",
7701 filter_replace.old_filter_type,
7702 filter_replace.new_filter_type);
7707 static enum i40e_status_code
7708 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7710 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7711 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7712 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7713 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7714 enum i40e_status_code status = I40E_SUCCESS;
7716 if (pf->support_multi_driver) {
7717 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7718 return I40E_NOT_SUPPORTED;
7722 memset(&filter_replace, 0,
7723 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7724 memset(&filter_replace_buf, 0,
7725 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7726 /* create L1 filter */
7727 filter_replace.old_filter_type =
7728 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7729 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7730 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7731 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7732 /* Prepare the buffer, 2 entries */
7733 filter_replace_buf.data[0] =
7734 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7735 filter_replace_buf.data[0] |=
7736 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7737 filter_replace_buf.data[2] = 0xFF;
7738 filter_replace_buf.data[3] = 0xFF;
7739 filter_replace_buf.data[4] =
7740 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7741 filter_replace_buf.data[4] |=
7742 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7743 filter_replace_buf.data[6] = 0xFF;
7744 filter_replace_buf.data[7] = 0xFF;
7745 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7746 &filter_replace_buf);
7749 if (filter_replace.old_filter_type !=
7750 filter_replace.new_filter_type)
7751 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7752 " original: 0x%x, new: 0x%x",
7754 filter_replace.old_filter_type,
7755 filter_replace.new_filter_type);
7758 memset(&filter_replace, 0,
7759 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7760 memset(&filter_replace_buf, 0,
7761 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7762 /* create L1 filter */
7763 filter_replace.old_filter_type =
7764 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7765 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7766 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7767 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7768 /* Prepare the buffer, 2 entries */
7769 filter_replace_buf.data[0] =
7770 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7771 filter_replace_buf.data[0] |=
7772 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7773 filter_replace_buf.data[2] = 0xFF;
7774 filter_replace_buf.data[3] = 0xFF;
7775 filter_replace_buf.data[4] =
7776 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7777 filter_replace_buf.data[4] |=
7778 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7779 filter_replace_buf.data[6] = 0xFF;
7780 filter_replace_buf.data[7] = 0xFF;
7782 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7783 &filter_replace_buf);
7784 if (!status && (filter_replace.old_filter_type !=
7785 filter_replace.new_filter_type)) {
7786 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7787 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7788 " original: 0x%x, new: 0x%x",
7790 filter_replace.old_filter_type,
7791 filter_replace.new_filter_type);
7797 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7799 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7800 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7801 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7802 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7803 enum i40e_status_code status = I40E_SUCCESS;
7805 if (pf->support_multi_driver) {
7806 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7807 return I40E_NOT_SUPPORTED;
7811 memset(&filter_replace, 0,
7812 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7813 memset(&filter_replace_buf, 0,
7814 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7815 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7816 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7817 filter_replace.new_filter_type =
7818 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7819 /* Prepare the buffer, 2 entries */
7820 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7821 filter_replace_buf.data[0] |=
7822 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7823 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7824 filter_replace_buf.data[4] |=
7825 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7826 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7827 &filter_replace_buf);
7830 if (filter_replace.old_filter_type !=
7831 filter_replace.new_filter_type)
7832 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7833 " original: 0x%x, new: 0x%x",
7835 filter_replace.old_filter_type,
7836 filter_replace.new_filter_type);
7839 memset(&filter_replace, 0,
7840 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7841 memset(&filter_replace_buf, 0,
7842 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7843 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7844 filter_replace.old_filter_type =
7845 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7846 filter_replace.new_filter_type =
7847 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7848 /* Prepare the buffer, 2 entries */
7849 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7850 filter_replace_buf.data[0] |=
7851 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7852 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7853 filter_replace_buf.data[4] |=
7854 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7856 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7857 &filter_replace_buf);
7858 if (!status && (filter_replace.old_filter_type !=
7859 filter_replace.new_filter_type)) {
7860 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7861 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7862 " original: 0x%x, new: 0x%x",
7864 filter_replace.old_filter_type,
7865 filter_replace.new_filter_type);
7871 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7872 struct i40e_tunnel_filter_conf *tunnel_filter,
7876 uint32_t ipv4_addr, ipv4_addr_le;
7877 uint8_t i, tun_type = 0;
7878 /* internal variable to convert ipv6 byte order */
7879 uint32_t convert_ipv6[4];
7881 struct i40e_pf_vf *vf = NULL;
7882 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7883 struct i40e_vsi *vsi;
7884 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7885 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7886 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7887 struct i40e_tunnel_filter *tunnel, *node;
7888 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7890 bool big_buffer = 0;
7892 cld_filter = rte_zmalloc("tunnel_filter",
7893 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7896 if (cld_filter == NULL) {
7897 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7900 pfilter = cld_filter;
7902 ether_addr_copy(&tunnel_filter->outer_mac,
7903 (struct ether_addr *)&pfilter->element.outer_mac);
7904 ether_addr_copy(&tunnel_filter->inner_mac,
7905 (struct ether_addr *)&pfilter->element.inner_mac);
7907 pfilter->element.inner_vlan =
7908 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7909 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7910 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7911 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7912 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7913 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7915 sizeof(pfilter->element.ipaddr.v4.data));
7917 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7918 for (i = 0; i < 4; i++) {
7920 rte_cpu_to_le_32(rte_be_to_cpu_32(
7921 tunnel_filter->ip_addr.ipv6_addr[i]));
7923 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7925 sizeof(pfilter->element.ipaddr.v6.data));
7928 /* check tunneled type */
7929 switch (tunnel_filter->tunnel_type) {
7930 case I40E_TUNNEL_TYPE_VXLAN:
7931 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7933 case I40E_TUNNEL_TYPE_NVGRE:
7934 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7936 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7937 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7939 case I40E_TUNNEL_TYPE_MPLSoUDP:
7940 if (!pf->mpls_replace_flag) {
7941 i40e_replace_mpls_l1_filter(pf);
7942 i40e_replace_mpls_cloud_filter(pf);
7943 pf->mpls_replace_flag = 1;
7945 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7946 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7948 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7949 (teid_le & 0xF) << 12;
7950 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7953 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7955 case I40E_TUNNEL_TYPE_MPLSoGRE:
7956 if (!pf->mpls_replace_flag) {
7957 i40e_replace_mpls_l1_filter(pf);
7958 i40e_replace_mpls_cloud_filter(pf);
7959 pf->mpls_replace_flag = 1;
7961 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7962 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7964 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7965 (teid_le & 0xF) << 12;
7966 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7969 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7971 case I40E_TUNNEL_TYPE_GTPC:
7972 if (!pf->gtp_replace_flag) {
7973 i40e_replace_gtp_l1_filter(pf);
7974 i40e_replace_gtp_cloud_filter(pf);
7975 pf->gtp_replace_flag = 1;
7977 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7978 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7979 (teid_le >> 16) & 0xFFFF;
7980 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7982 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7986 case I40E_TUNNEL_TYPE_GTPU:
7987 if (!pf->gtp_replace_flag) {
7988 i40e_replace_gtp_l1_filter(pf);
7989 i40e_replace_gtp_cloud_filter(pf);
7990 pf->gtp_replace_flag = 1;
7992 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7993 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7994 (teid_le >> 16) & 0xFFFF;
7995 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7997 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8001 case I40E_TUNNEL_TYPE_QINQ:
8002 if (!pf->qinq_replace_flag) {
8003 ret = i40e_cloud_filter_qinq_create(pf);
8006 "QinQ tunnel filter already created.");
8007 pf->qinq_replace_flag = 1;
8009 /* Add in the General fields the values of
8010 * the Outer and Inner VLAN
8011 * Big Buffer should be set, see changes in
8012 * i40e_aq_add_cloud_filters
8014 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8015 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8019 /* Other tunnel types is not supported. */
8020 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8021 rte_free(cld_filter);
8025 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8026 pfilter->element.flags =
8027 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8028 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8029 pfilter->element.flags =
8030 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8031 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8032 pfilter->element.flags =
8033 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8034 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8035 pfilter->element.flags =
8036 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8037 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8038 pfilter->element.flags |=
8039 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8041 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8042 &pfilter->element.flags);
8044 rte_free(cld_filter);
8049 pfilter->element.flags |= rte_cpu_to_le_16(
8050 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8051 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8052 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8053 pfilter->element.queue_number =
8054 rte_cpu_to_le_16(tunnel_filter->queue_id);
8056 if (!tunnel_filter->is_to_vf)
8059 if (tunnel_filter->vf_id >= pf->vf_num) {
8060 PMD_DRV_LOG(ERR, "Invalid argument.");
8061 rte_free(cld_filter);
8064 vf = &pf->vfs[tunnel_filter->vf_id];
8068 /* Check if there is the filter in SW list */
8069 memset(&check_filter, 0, sizeof(check_filter));
8070 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8071 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8072 check_filter.vf_id = tunnel_filter->vf_id;
8073 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8075 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8076 rte_free(cld_filter);
8080 if (!add && !node) {
8081 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8082 rte_free(cld_filter);
8088 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8089 vsi->seid, cld_filter, 1);
8091 ret = i40e_aq_add_cloud_filters(hw,
8092 vsi->seid, &cld_filter->element, 1);
8094 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8095 rte_free(cld_filter);
8098 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8099 if (tunnel == NULL) {
8100 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8101 rte_free(cld_filter);
8105 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8106 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8111 ret = i40e_aq_remove_cloud_filters_big_buffer(
8112 hw, vsi->seid, cld_filter, 1);
8114 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8115 &cld_filter->element, 1);
8117 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8118 rte_free(cld_filter);
8121 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8124 rte_free(cld_filter);
8129 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8133 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8134 if (pf->vxlan_ports[i] == port)
8142 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8146 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8148 idx = i40e_get_vxlan_port_idx(pf, port);
8150 /* Check if port already exists */
8152 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8156 /* Now check if there is space to add the new port */
8157 idx = i40e_get_vxlan_port_idx(pf, 0);
8160 "Maximum number of UDP ports reached, not adding port %d",
8165 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8168 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8172 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8175 /* New port: add it and mark its index in the bitmap */
8176 pf->vxlan_ports[idx] = port;
8177 pf->vxlan_bitmap |= (1 << idx);
8179 if (!(pf->flags & I40E_FLAG_VXLAN))
8180 pf->flags |= I40E_FLAG_VXLAN;
8186 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8189 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8191 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8192 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8196 idx = i40e_get_vxlan_port_idx(pf, port);
8199 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8203 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8204 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8208 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8211 pf->vxlan_ports[idx] = 0;
8212 pf->vxlan_bitmap &= ~(1 << idx);
8214 if (!pf->vxlan_bitmap)
8215 pf->flags &= ~I40E_FLAG_VXLAN;
8220 /* Add UDP tunneling port */
8222 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8223 struct rte_eth_udp_tunnel *udp_tunnel)
8226 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8228 if (udp_tunnel == NULL)
8231 switch (udp_tunnel->prot_type) {
8232 case RTE_TUNNEL_TYPE_VXLAN:
8233 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8236 case RTE_TUNNEL_TYPE_GENEVE:
8237 case RTE_TUNNEL_TYPE_TEREDO:
8238 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8243 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8251 /* Remove UDP tunneling port */
8253 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8254 struct rte_eth_udp_tunnel *udp_tunnel)
8257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8259 if (udp_tunnel == NULL)
8262 switch (udp_tunnel->prot_type) {
8263 case RTE_TUNNEL_TYPE_VXLAN:
8264 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8266 case RTE_TUNNEL_TYPE_GENEVE:
8267 case RTE_TUNNEL_TYPE_TEREDO:
8268 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8272 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8280 /* Calculate the maximum number of contiguous PF queues that are configured */
8282 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8284 struct rte_eth_dev_data *data = pf->dev_data;
8286 struct i40e_rx_queue *rxq;
8289 for (i = 0; i < pf->lan_nb_qps; i++) {
8290 rxq = data->rx_queues[i];
8291 if (rxq && rxq->q_set)
8302 i40e_pf_config_rss(struct i40e_pf *pf)
8304 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8305 struct rte_eth_rss_conf rss_conf;
8306 uint32_t i, lut = 0;
8310 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8311 * It's necessary to calculate the actual PF queues that are configured.
8313 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8314 num = i40e_pf_calc_configured_queues_num(pf);
8316 num = pf->dev_data->nb_rx_queues;
8318 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8319 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8323 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8327 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8330 lut = (lut << 8) | (j & ((0x1 <<
8331 hw->func_caps.rss_table_entry_width) - 1));
8333 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8336 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8337 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8338 i40e_pf_disable_rss(pf);
8341 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8342 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8343 /* Random default keys */
8344 static uint32_t rss_key_default[] = {0x6b793944,
8345 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8346 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8347 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8349 rss_conf.rss_key = (uint8_t *)rss_key_default;
8350 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8354 return i40e_hw_rss_hash_set(pf, &rss_conf);
8358 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8359 struct rte_eth_tunnel_filter_conf *filter)
8361 if (pf == NULL || filter == NULL) {
8362 PMD_DRV_LOG(ERR, "Invalid parameter");
8366 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8367 PMD_DRV_LOG(ERR, "Invalid queue ID");
8371 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8372 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8376 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8377 (is_zero_ether_addr(&filter->outer_mac))) {
8378 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8382 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8383 (is_zero_ether_addr(&filter->inner_mac))) {
8384 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8391 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8392 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8394 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8396 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8400 if (pf->support_multi_driver) {
8401 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8405 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8406 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8409 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8410 } else if (len == 4) {
8411 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8413 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8418 ret = i40e_aq_debug_write_global_register(hw,
8419 I40E_GL_PRS_FVBM(2),
8423 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8424 "with value 0x%08x",
8425 I40E_GL_PRS_FVBM(2), reg);
8426 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8430 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8431 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8437 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8444 switch (cfg->cfg_type) {
8445 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8446 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8449 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8457 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8458 enum rte_filter_op filter_op,
8461 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8462 int ret = I40E_ERR_PARAM;
8464 switch (filter_op) {
8465 case RTE_ETH_FILTER_SET:
8466 ret = i40e_dev_global_config_set(hw,
8467 (struct rte_eth_global_cfg *)arg);
8470 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8478 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8479 enum rte_filter_op filter_op,
8482 struct rte_eth_tunnel_filter_conf *filter;
8483 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8484 int ret = I40E_SUCCESS;
8486 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8488 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8489 return I40E_ERR_PARAM;
8491 switch (filter_op) {
8492 case RTE_ETH_FILTER_NOP:
8493 if (!(pf->flags & I40E_FLAG_VXLAN))
8494 ret = I40E_NOT_SUPPORTED;
8496 case RTE_ETH_FILTER_ADD:
8497 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8499 case RTE_ETH_FILTER_DELETE:
8500 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8503 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8504 ret = I40E_ERR_PARAM;
8512 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8515 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8518 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8519 ret = i40e_pf_config_rss(pf);
8521 i40e_pf_disable_rss(pf);
8526 /* Get the symmetric hash enable configurations per port */
8528 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8530 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8532 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8535 /* Set the symmetric hash enable configurations per port */
8537 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8539 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8542 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8544 "Symmetric hash has already been enabled");
8547 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8549 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8551 "Symmetric hash has already been disabled");
8554 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8556 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8557 I40E_WRITE_FLUSH(hw);
8561 * Get global configurations of hash function type and symmetric hash enable
8562 * per flow type (pctype). Note that global configuration means it affects all
8563 * the ports on the same NIC.
8566 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8567 struct rte_eth_hash_global_conf *g_cfg)
8569 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8573 memset(g_cfg, 0, sizeof(*g_cfg));
8574 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8575 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8576 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8578 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8579 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8580 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8583 * As i40e supports less than 64 flow types, only first 64 bits need to
8586 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8587 g_cfg->valid_bit_mask[i] = 0ULL;
8588 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8591 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8593 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8594 if (!adapter->pctypes_tbl[i])
8596 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8597 j < I40E_FILTER_PCTYPE_MAX; j++) {
8598 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8599 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8600 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8601 g_cfg->sym_hash_enable_mask[0] |=
8612 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8613 const struct rte_eth_hash_global_conf *g_cfg)
8616 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8618 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8619 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8620 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8621 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8627 * As i40e supports less than 64 flow types, only first 64 bits need to
8630 mask0 = g_cfg->valid_bit_mask[0];
8631 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8633 /* Check if any unsupported flow type configured */
8634 if ((mask0 | i40e_mask) ^ i40e_mask)
8637 if (g_cfg->valid_bit_mask[i])
8645 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8651 * Set global configurations of hash function type and symmetric hash enable
8652 * per flow type (pctype). Note any modifying global configuration will affect
8653 * all the ports on the same NIC.
8656 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8657 struct rte_eth_hash_global_conf *g_cfg)
8659 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8660 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8664 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8666 if (pf->support_multi_driver) {
8667 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8671 /* Check the input parameters */
8672 ret = i40e_hash_global_config_check(adapter, g_cfg);
8677 * As i40e supports less than 64 flow types, only first 64 bits need to
8680 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8681 if (mask0 & (1UL << i)) {
8682 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8683 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8685 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8686 j < I40E_FILTER_PCTYPE_MAX; j++) {
8687 if (adapter->pctypes_tbl[i] & (1ULL << j))
8688 i40e_write_global_rx_ctl(hw,
8692 i40e_global_cfg_warning(I40E_WARNING_HSYM);
8696 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8697 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8699 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8701 "Hash function already set to Toeplitz");
8704 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8705 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8707 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8709 "Hash function already set to Simple XOR");
8712 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8714 /* Use the default, and keep it as it is */
8717 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8718 i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8721 I40E_WRITE_FLUSH(hw);
8727 * Valid input sets for hash and flow director filters per PCTYPE
8730 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8731 enum rte_filter_type filter)
8735 static const uint64_t valid_hash_inset_table[] = {
8736 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8737 I40E_INSET_DMAC | I40E_INSET_SMAC |
8738 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8739 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8740 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8741 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8742 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8743 I40E_INSET_FLEX_PAYLOAD,
8744 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8745 I40E_INSET_DMAC | I40E_INSET_SMAC |
8746 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8747 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8748 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8749 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8750 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8751 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8752 I40E_INSET_FLEX_PAYLOAD,
8753 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8754 I40E_INSET_DMAC | I40E_INSET_SMAC |
8755 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8756 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8757 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8758 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8759 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8760 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8761 I40E_INSET_FLEX_PAYLOAD,
8762 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8763 I40E_INSET_DMAC | I40E_INSET_SMAC |
8764 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8765 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8766 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8767 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8768 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8769 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8770 I40E_INSET_FLEX_PAYLOAD,
8771 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8772 I40E_INSET_DMAC | I40E_INSET_SMAC |
8773 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8774 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8775 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8776 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8777 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8778 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8779 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8780 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8781 I40E_INSET_DMAC | I40E_INSET_SMAC |
8782 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8783 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8784 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8785 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8786 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8787 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8788 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8789 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8790 I40E_INSET_DMAC | I40E_INSET_SMAC |
8791 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8792 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8793 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8794 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8795 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8796 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8797 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8798 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8799 I40E_INSET_DMAC | I40E_INSET_SMAC |
8800 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8801 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8802 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8803 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8804 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8805 I40E_INSET_FLEX_PAYLOAD,
8806 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8807 I40E_INSET_DMAC | I40E_INSET_SMAC |
8808 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8809 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8810 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8811 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8812 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8813 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8814 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8815 I40E_INSET_DMAC | I40E_INSET_SMAC |
8816 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8817 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8818 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8819 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8820 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8821 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8822 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8823 I40E_INSET_DMAC | I40E_INSET_SMAC |
8824 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8825 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8826 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8827 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8828 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8829 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8830 I40E_INSET_FLEX_PAYLOAD,
8831 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8832 I40E_INSET_DMAC | I40E_INSET_SMAC |
8833 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8834 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8835 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8836 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8837 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8838 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8839 I40E_INSET_FLEX_PAYLOAD,
8840 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8841 I40E_INSET_DMAC | I40E_INSET_SMAC |
8842 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8843 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8844 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8845 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8846 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8847 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8848 I40E_INSET_FLEX_PAYLOAD,
8849 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8850 I40E_INSET_DMAC | I40E_INSET_SMAC |
8851 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8852 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8853 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8854 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8855 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8856 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8857 I40E_INSET_FLEX_PAYLOAD,
8858 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8859 I40E_INSET_DMAC | I40E_INSET_SMAC |
8860 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8861 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8862 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8863 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8864 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8865 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8866 I40E_INSET_FLEX_PAYLOAD,
8867 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8868 I40E_INSET_DMAC | I40E_INSET_SMAC |
8869 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8870 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8871 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8872 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8873 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8874 I40E_INSET_FLEX_PAYLOAD,
8875 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8876 I40E_INSET_DMAC | I40E_INSET_SMAC |
8877 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8878 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8879 I40E_INSET_FLEX_PAYLOAD,
8883 * Flow director supports only fields defined in
8884 * union rte_eth_fdir_flow.
8886 static const uint64_t valid_fdir_inset_table[] = {
8887 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8888 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8889 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8890 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8891 I40E_INSET_IPV4_TTL,
8892 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8893 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8894 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8895 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8896 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8897 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8898 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8899 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8900 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8901 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8902 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8903 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8904 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8905 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8906 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8907 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8908 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8909 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8910 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8911 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8912 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8913 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8914 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8915 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8916 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8917 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8918 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8919 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8920 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8921 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8923 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8924 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8925 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8926 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8927 I40E_INSET_IPV4_TTL,
8928 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8929 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8930 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8931 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8932 I40E_INSET_IPV6_HOP_LIMIT,
8933 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8934 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8935 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8936 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8937 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8938 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8939 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8940 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8941 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8942 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8943 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8944 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8945 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8946 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8947 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8948 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8949 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8950 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8951 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8952 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8953 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8954 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8955 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8956 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8957 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8958 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8959 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8960 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8961 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8962 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8964 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8965 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8966 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8967 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8968 I40E_INSET_IPV6_HOP_LIMIT,
8969 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8970 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8971 I40E_INSET_LAST_ETHER_TYPE,
8974 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8976 if (filter == RTE_ETH_FILTER_HASH)
8977 valid = valid_hash_inset_table[pctype];
8979 valid = valid_fdir_inset_table[pctype];
8985 * Validate if the input set is allowed for a specific PCTYPE
8988 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8989 enum rte_filter_type filter, uint64_t inset)
8993 valid = i40e_get_valid_input_set(pctype, filter);
8994 if (inset & (~valid))
9000 /* default input set fields combination per pctype */
9002 i40e_get_default_input_set(uint16_t pctype)
9004 static const uint64_t default_inset_table[] = {
9005 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9006 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9007 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9008 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9009 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9010 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9011 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9012 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9013 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9014 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9015 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9016 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9017 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9018 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9019 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9020 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9021 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9022 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9023 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9024 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9026 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9027 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9028 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9029 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9030 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9031 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9032 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9033 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9034 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9035 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9036 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9037 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9038 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9039 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9040 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9041 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9042 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9043 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9044 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9045 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9046 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9047 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9049 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9050 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9051 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9052 I40E_INSET_LAST_ETHER_TYPE,
9055 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9058 return default_inset_table[pctype];
9062 * Parse the input set from index to logical bit masks
9065 i40e_parse_input_set(uint64_t *inset,
9066 enum i40e_filter_pctype pctype,
9067 enum rte_eth_input_set_field *field,
9073 static const struct {
9074 enum rte_eth_input_set_field field;
9076 } inset_convert_table[] = {
9077 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9078 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9079 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9080 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9081 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9082 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9083 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9084 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9085 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9086 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9087 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9088 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9089 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9090 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9091 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9092 I40E_INSET_IPV6_NEXT_HDR},
9093 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9094 I40E_INSET_IPV6_HOP_LIMIT},
9095 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9096 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9097 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9098 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9099 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9100 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9101 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9102 I40E_INSET_SCTP_VT},
9103 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9104 I40E_INSET_TUNNEL_DMAC},
9105 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9106 I40E_INSET_VLAN_TUNNEL},
9107 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9108 I40E_INSET_TUNNEL_ID},
9109 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9110 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9111 I40E_INSET_FLEX_PAYLOAD_W1},
9112 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9113 I40E_INSET_FLEX_PAYLOAD_W2},
9114 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9115 I40E_INSET_FLEX_PAYLOAD_W3},
9116 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9117 I40E_INSET_FLEX_PAYLOAD_W4},
9118 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9119 I40E_INSET_FLEX_PAYLOAD_W5},
9120 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9121 I40E_INSET_FLEX_PAYLOAD_W6},
9122 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9123 I40E_INSET_FLEX_PAYLOAD_W7},
9124 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9125 I40E_INSET_FLEX_PAYLOAD_W8},
9128 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9131 /* Only one item allowed for default or all */
9133 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9134 *inset = i40e_get_default_input_set(pctype);
9136 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9137 *inset = I40E_INSET_NONE;
9142 for (i = 0, *inset = 0; i < size; i++) {
9143 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9144 if (field[i] == inset_convert_table[j].field) {
9145 *inset |= inset_convert_table[j].inset;
9150 /* It contains unsupported input set, return immediately */
9151 if (j == RTE_DIM(inset_convert_table))
9159 * Translate the input set from bit masks to register aware bit masks
9163 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9173 static const struct inset_map inset_map_common[] = {
9174 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9175 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9176 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9177 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9178 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9179 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9180 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9181 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9182 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9183 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9184 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9185 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9186 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9187 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9188 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9189 {I40E_INSET_TUNNEL_DMAC,
9190 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9191 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9192 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9193 {I40E_INSET_TUNNEL_SRC_PORT,
9194 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9195 {I40E_INSET_TUNNEL_DST_PORT,
9196 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9197 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9198 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9199 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9200 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9201 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9202 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9203 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9204 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9205 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9208 /* some different registers map in x722*/
9209 static const struct inset_map inset_map_diff_x722[] = {
9210 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9211 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9212 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9213 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9216 static const struct inset_map inset_map_diff_not_x722[] = {
9217 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9218 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9219 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9220 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9226 /* Translate input set to register aware inset */
9227 if (type == I40E_MAC_X722) {
9228 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9229 if (input & inset_map_diff_x722[i].inset)
9230 val |= inset_map_diff_x722[i].inset_reg;
9233 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9234 if (input & inset_map_diff_not_x722[i].inset)
9235 val |= inset_map_diff_not_x722[i].inset_reg;
9239 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9240 if (input & inset_map_common[i].inset)
9241 val |= inset_map_common[i].inset_reg;
9248 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9251 uint64_t inset_need_mask = inset;
9253 static const struct {
9256 } inset_mask_map[] = {
9257 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9258 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9259 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9260 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9261 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9262 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9263 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9264 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9267 if (!inset || !mask || !nb_elem)
9270 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9271 /* Clear the inset bit, if no MASK is required,
9272 * for example proto + ttl
9274 if ((inset & inset_mask_map[i].inset) ==
9275 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9276 inset_need_mask &= ~inset_mask_map[i].inset;
9277 if (!inset_need_mask)
9280 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9281 if ((inset_need_mask & inset_mask_map[i].inset) ==
9282 inset_mask_map[i].inset) {
9283 if (idx >= nb_elem) {
9284 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9287 mask[idx] = inset_mask_map[i].mask;
9296 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9298 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9300 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9302 i40e_write_rx_ctl(hw, addr, val);
9303 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9304 (uint32_t)i40e_read_rx_ctl(hw, addr));
9308 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9310 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9311 struct rte_eth_dev *dev;
9313 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9315 i40e_write_rx_ctl(hw, addr, val);
9316 PMD_DRV_LOG(WARNING,
9317 "i40e device %s changed global register [0x%08x]."
9318 " original: 0x%08x, new: 0x%08x",
9319 dev->device->name, addr, reg,
9320 (uint32_t)i40e_read_rx_ctl(hw, addr));
9325 i40e_filter_input_set_init(struct i40e_pf *pf)
9327 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9328 enum i40e_filter_pctype pctype;
9329 uint64_t input_set, inset_reg;
9330 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9334 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9335 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9336 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9338 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9341 input_set = i40e_get_default_input_set(pctype);
9343 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9344 I40E_INSET_MASK_NUM_REG);
9347 if (pf->support_multi_driver && num > 0) {
9348 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9351 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9354 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9355 (uint32_t)(inset_reg & UINT32_MAX));
9356 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9357 (uint32_t)((inset_reg >>
9358 I40E_32_BIT_WIDTH) & UINT32_MAX));
9359 if (!pf->support_multi_driver) {
9360 i40e_check_write_global_reg(hw,
9361 I40E_GLQF_HASH_INSET(0, pctype),
9362 (uint32_t)(inset_reg & UINT32_MAX));
9363 i40e_check_write_global_reg(hw,
9364 I40E_GLQF_HASH_INSET(1, pctype),
9365 (uint32_t)((inset_reg >>
9366 I40E_32_BIT_WIDTH) & UINT32_MAX));
9368 for (i = 0; i < num; i++) {
9369 i40e_check_write_global_reg(hw,
9370 I40E_GLQF_FD_MSK(i, pctype),
9372 i40e_check_write_global_reg(hw,
9373 I40E_GLQF_HASH_MSK(i, pctype),
9376 /*clear unused mask registers of the pctype */
9377 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9378 i40e_check_write_global_reg(hw,
9379 I40E_GLQF_FD_MSK(i, pctype),
9381 i40e_check_write_global_reg(hw,
9382 I40E_GLQF_HASH_MSK(i, pctype),
9386 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9388 I40E_WRITE_FLUSH(hw);
9390 /* store the default input set */
9391 if (!pf->support_multi_driver)
9392 pf->hash_input_set[pctype] = input_set;
9393 pf->fdir.input_set[pctype] = input_set;
9396 if (!pf->support_multi_driver) {
9397 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9398 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9399 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9404 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9405 struct rte_eth_input_set_conf *conf)
9407 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9408 enum i40e_filter_pctype pctype;
9409 uint64_t input_set, inset_reg = 0;
9410 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9414 PMD_DRV_LOG(ERR, "Invalid pointer");
9417 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9418 conf->op != RTE_ETH_INPUT_SET_ADD) {
9419 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9423 if (pf->support_multi_driver) {
9424 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9428 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9429 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9430 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9434 if (hw->mac.type == I40E_MAC_X722) {
9435 /* get translated pctype value in fd pctype register */
9436 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9437 I40E_GLQF_FD_PCTYPES((int)pctype));
9440 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9443 PMD_DRV_LOG(ERR, "Failed to parse input set");
9447 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9448 /* get inset value in register */
9449 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9450 inset_reg <<= I40E_32_BIT_WIDTH;
9451 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9452 input_set |= pf->hash_input_set[pctype];
9454 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9455 I40E_INSET_MASK_NUM_REG);
9459 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9461 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9462 (uint32_t)(inset_reg & UINT32_MAX));
9463 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9464 (uint32_t)((inset_reg >>
9465 I40E_32_BIT_WIDTH) & UINT32_MAX));
9466 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9468 for (i = 0; i < num; i++)
9469 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9471 /*clear unused mask registers of the pctype */
9472 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9473 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9475 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9476 I40E_WRITE_FLUSH(hw);
9478 pf->hash_input_set[pctype] = input_set;
9483 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9484 struct rte_eth_input_set_conf *conf)
9486 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9487 enum i40e_filter_pctype pctype;
9488 uint64_t input_set, inset_reg = 0;
9489 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9493 PMD_DRV_LOG(ERR, "Invalid pointer");
9496 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9497 conf->op != RTE_ETH_INPUT_SET_ADD) {
9498 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9502 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9504 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9505 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9509 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9512 PMD_DRV_LOG(ERR, "Failed to parse input set");
9516 /* get inset value in register */
9517 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9518 inset_reg <<= I40E_32_BIT_WIDTH;
9519 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9521 /* Can not change the inset reg for flex payload for fdir,
9522 * it is done by writing I40E_PRTQF_FD_FLXINSET
9523 * in i40e_set_flex_mask_on_pctype.
9525 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9526 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9528 input_set |= pf->fdir.input_set[pctype];
9529 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9530 I40E_INSET_MASK_NUM_REG);
9533 if (pf->support_multi_driver && num > 0) {
9534 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9538 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9540 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9541 (uint32_t)(inset_reg & UINT32_MAX));
9542 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9543 (uint32_t)((inset_reg >>
9544 I40E_32_BIT_WIDTH) & UINT32_MAX));
9546 if (!pf->support_multi_driver) {
9547 for (i = 0; i < num; i++)
9548 i40e_check_write_global_reg(hw,
9549 I40E_GLQF_FD_MSK(i, pctype),
9551 /*clear unused mask registers of the pctype */
9552 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9553 i40e_check_write_global_reg(hw,
9554 I40E_GLQF_FD_MSK(i, pctype),
9556 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9558 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9560 I40E_WRITE_FLUSH(hw);
9562 pf->fdir.input_set[pctype] = input_set;
9567 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9572 PMD_DRV_LOG(ERR, "Invalid pointer");
9576 switch (info->info_type) {
9577 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9578 i40e_get_symmetric_hash_enable_per_port(hw,
9579 &(info->info.enable));
9581 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9582 ret = i40e_get_hash_filter_global_config(hw,
9583 &(info->info.global_conf));
9586 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9596 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9601 PMD_DRV_LOG(ERR, "Invalid pointer");
9605 switch (info->info_type) {
9606 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9607 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9609 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9610 ret = i40e_set_hash_filter_global_config(hw,
9611 &(info->info.global_conf));
9613 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9614 ret = i40e_hash_filter_inset_select(hw,
9615 &(info->info.input_set_conf));
9619 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9628 /* Operations for hash function */
9630 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9631 enum rte_filter_op filter_op,
9634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9637 switch (filter_op) {
9638 case RTE_ETH_FILTER_NOP:
9640 case RTE_ETH_FILTER_GET:
9641 ret = i40e_hash_filter_get(hw,
9642 (struct rte_eth_hash_filter_info *)arg);
9644 case RTE_ETH_FILTER_SET:
9645 ret = i40e_hash_filter_set(hw,
9646 (struct rte_eth_hash_filter_info *)arg);
9649 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9658 /* Convert ethertype filter structure */
9660 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9661 struct i40e_ethertype_filter *filter)
9663 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9664 filter->input.ether_type = input->ether_type;
9665 filter->flags = input->flags;
9666 filter->queue = input->queue;
9671 /* Check if there exists the ehtertype filter */
9672 struct i40e_ethertype_filter *
9673 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9674 const struct i40e_ethertype_filter_input *input)
9678 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9682 return ethertype_rule->hash_map[ret];
9685 /* Add ethertype filter in SW list */
9687 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9688 struct i40e_ethertype_filter *filter)
9690 struct i40e_ethertype_rule *rule = &pf->ethertype;
9693 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9696 "Failed to insert ethertype filter"
9697 " to hash table %d!",
9701 rule->hash_map[ret] = filter;
9703 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9708 /* Delete ethertype filter in SW list */
9710 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9711 struct i40e_ethertype_filter_input *input)
9713 struct i40e_ethertype_rule *rule = &pf->ethertype;
9714 struct i40e_ethertype_filter *filter;
9717 ret = rte_hash_del_key(rule->hash_table, input);
9720 "Failed to delete ethertype filter"
9721 " to hash table %d!",
9725 filter = rule->hash_map[ret];
9726 rule->hash_map[ret] = NULL;
9728 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9735 * Configure ethertype filter, which can director packet by filtering
9736 * with mac address and ether_type or only ether_type
9739 i40e_ethertype_filter_set(struct i40e_pf *pf,
9740 struct rte_eth_ethertype_filter *filter,
9743 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9744 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9745 struct i40e_ethertype_filter *ethertype_filter, *node;
9746 struct i40e_ethertype_filter check_filter;
9747 struct i40e_control_filter_stats stats;
9751 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9752 PMD_DRV_LOG(ERR, "Invalid queue ID");
9755 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9756 filter->ether_type == ETHER_TYPE_IPv6) {
9758 "unsupported ether_type(0x%04x) in control packet filter.",
9759 filter->ether_type);
9762 if (filter->ether_type == ETHER_TYPE_VLAN)
9763 PMD_DRV_LOG(WARNING,
9764 "filter vlan ether_type in first tag is not supported.");
9766 /* Check if there is the filter in SW list */
9767 memset(&check_filter, 0, sizeof(check_filter));
9768 i40e_ethertype_filter_convert(filter, &check_filter);
9769 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9770 &check_filter.input);
9772 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9776 if (!add && !node) {
9777 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9781 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9782 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9783 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9784 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9785 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9787 memset(&stats, 0, sizeof(stats));
9788 ret = i40e_aq_add_rem_control_packet_filter(hw,
9789 filter->mac_addr.addr_bytes,
9790 filter->ether_type, flags,
9792 filter->queue, add, &stats, NULL);
9795 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9796 ret, stats.mac_etype_used, stats.etype_used,
9797 stats.mac_etype_free, stats.etype_free);
9801 /* Add or delete a filter in SW list */
9803 ethertype_filter = rte_zmalloc("ethertype_filter",
9804 sizeof(*ethertype_filter), 0);
9805 if (ethertype_filter == NULL) {
9806 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9810 rte_memcpy(ethertype_filter, &check_filter,
9811 sizeof(check_filter));
9812 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9814 rte_free(ethertype_filter);
9816 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9823 * Handle operations for ethertype filter.
9826 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9827 enum rte_filter_op filter_op,
9830 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9833 if (filter_op == RTE_ETH_FILTER_NOP)
9837 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9842 switch (filter_op) {
9843 case RTE_ETH_FILTER_ADD:
9844 ret = i40e_ethertype_filter_set(pf,
9845 (struct rte_eth_ethertype_filter *)arg,
9848 case RTE_ETH_FILTER_DELETE:
9849 ret = i40e_ethertype_filter_set(pf,
9850 (struct rte_eth_ethertype_filter *)arg,
9854 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9862 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9863 enum rte_filter_type filter_type,
9864 enum rte_filter_op filter_op,
9872 switch (filter_type) {
9873 case RTE_ETH_FILTER_NONE:
9874 /* For global configuration */
9875 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9877 case RTE_ETH_FILTER_HASH:
9878 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9880 case RTE_ETH_FILTER_MACVLAN:
9881 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9883 case RTE_ETH_FILTER_ETHERTYPE:
9884 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9886 case RTE_ETH_FILTER_TUNNEL:
9887 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9889 case RTE_ETH_FILTER_FDIR:
9890 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9892 case RTE_ETH_FILTER_GENERIC:
9893 if (filter_op != RTE_ETH_FILTER_GET)
9895 *(const void **)arg = &i40e_flow_ops;
9898 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9908 * Check and enable Extended Tag.
9909 * Enabling Extended Tag is important for 40G performance.
9912 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9914 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9918 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9921 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9925 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9926 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9931 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9934 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9938 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9939 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9942 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9943 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9946 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9953 * As some registers wouldn't be reset unless a global hardware reset,
9954 * hardware initialization is needed to put those registers into an
9955 * expected initial state.
9958 i40e_hw_init(struct rte_eth_dev *dev)
9960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9962 i40e_enable_extended_tag(dev);
9964 /* clear the PF Queue Filter control register */
9965 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9967 /* Disable symmetric hash per port */
9968 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9972 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9973 * however this function will return only one highest pctype index,
9974 * which is not quite correct. This is known problem of i40e driver
9975 * and needs to be fixed later.
9977 enum i40e_filter_pctype
9978 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9981 uint64_t pctype_mask;
9983 if (flow_type < I40E_FLOW_TYPE_MAX) {
9984 pctype_mask = adapter->pctypes_tbl[flow_type];
9985 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9986 if (pctype_mask & (1ULL << i))
9987 return (enum i40e_filter_pctype)i;
9990 return I40E_FILTER_PCTYPE_INVALID;
9994 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9995 enum i40e_filter_pctype pctype)
9998 uint64_t pctype_mask = 1ULL << pctype;
10000 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10002 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10006 return RTE_ETH_FLOW_UNKNOWN;
10010 * On X710, performance number is far from the expectation on recent firmware
10011 * versions; on XL710, performance number is also far from the expectation on
10012 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10013 * mode is enabled and port MAC address is equal to the packet destination MAC
10014 * address. The fix for this issue may not be integrated in the following
10015 * firmware version. So the workaround in software driver is needed. It needs
10016 * to modify the initial values of 3 internal only registers for both X710 and
10017 * XL710. Note that the values for X710 or XL710 could be different, and the
10018 * workaround can be removed when it is fixed in firmware in the future.
10021 /* For both X710 and XL710 */
10022 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10023 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10024 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10026 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10027 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10030 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10031 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10034 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10036 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10037 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10040 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10042 enum i40e_status_code status;
10043 struct i40e_aq_get_phy_abilities_resp phy_ab;
10044 int ret = -ENOTSUP;
10047 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10051 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10054 rte_delay_us(100000);
10056 status = i40e_aq_get_phy_capabilities(hw, false,
10057 true, &phy_ab, NULL);
10065 i40e_configure_registers(struct i40e_hw *hw)
10071 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10072 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10073 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10079 for (i = 0; i < RTE_DIM(reg_table); i++) {
10080 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10081 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10083 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10084 else /* For X710/XL710/XXV710 */
10085 if (hw->aq.fw_maj_ver < 6)
10087 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10090 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10093 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10094 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10096 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10097 else /* For X710/XL710/XXV710 */
10099 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10102 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10103 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
10104 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
10106 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
10107 else /* For X710 */
10109 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
10112 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10115 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10116 reg_table[i].addr);
10119 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10120 reg_table[i].addr, reg);
10121 if (reg == reg_table[i].val)
10124 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10125 reg_table[i].val, NULL);
10128 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10129 reg_table[i].val, reg_table[i].addr);
10132 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10133 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10137 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10138 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10139 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10140 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10142 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10147 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10148 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10152 /* Configure for double VLAN RX stripping */
10153 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10154 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10155 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10156 ret = i40e_aq_debug_write_register(hw,
10157 I40E_VSI_TSR(vsi->vsi_id),
10160 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10162 return I40E_ERR_CONFIG;
10166 /* Configure for double VLAN TX insertion */
10167 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10168 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10169 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10170 ret = i40e_aq_debug_write_register(hw,
10171 I40E_VSI_L2TAGSTXVALID(
10172 vsi->vsi_id), reg, NULL);
10175 "Failed to update VSI_L2TAGSTXVALID[%d]",
10177 return I40E_ERR_CONFIG;
10185 * i40e_aq_add_mirror_rule
10186 * @hw: pointer to the hardware structure
10187 * @seid: VEB seid to add mirror rule to
10188 * @dst_id: destination vsi seid
10189 * @entries: Buffer which contains the entities to be mirrored
10190 * @count: number of entities contained in the buffer
10191 * @rule_id:the rule_id of the rule to be added
10193 * Add a mirror rule for a given veb.
10196 static enum i40e_status_code
10197 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10198 uint16_t seid, uint16_t dst_id,
10199 uint16_t rule_type, uint16_t *entries,
10200 uint16_t count, uint16_t *rule_id)
10202 struct i40e_aq_desc desc;
10203 struct i40e_aqc_add_delete_mirror_rule cmd;
10204 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10205 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10208 enum i40e_status_code status;
10210 i40e_fill_default_direct_cmd_desc(&desc,
10211 i40e_aqc_opc_add_mirror_rule);
10212 memset(&cmd, 0, sizeof(cmd));
10214 buff_len = sizeof(uint16_t) * count;
10215 desc.datalen = rte_cpu_to_le_16(buff_len);
10217 desc.flags |= rte_cpu_to_le_16(
10218 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10219 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10220 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10221 cmd.num_entries = rte_cpu_to_le_16(count);
10222 cmd.seid = rte_cpu_to_le_16(seid);
10223 cmd.destination = rte_cpu_to_le_16(dst_id);
10225 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10226 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10228 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10229 hw->aq.asq_last_status, resp->rule_id,
10230 resp->mirror_rules_used, resp->mirror_rules_free);
10231 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10237 * i40e_aq_del_mirror_rule
10238 * @hw: pointer to the hardware structure
10239 * @seid: VEB seid to add mirror rule to
10240 * @entries: Buffer which contains the entities to be mirrored
10241 * @count: number of entities contained in the buffer
10242 * @rule_id:the rule_id of the rule to be delete
10244 * Delete a mirror rule for a given veb.
10247 static enum i40e_status_code
10248 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10249 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10250 uint16_t count, uint16_t rule_id)
10252 struct i40e_aq_desc desc;
10253 struct i40e_aqc_add_delete_mirror_rule cmd;
10254 uint16_t buff_len = 0;
10255 enum i40e_status_code status;
10258 i40e_fill_default_direct_cmd_desc(&desc,
10259 i40e_aqc_opc_delete_mirror_rule);
10260 memset(&cmd, 0, sizeof(cmd));
10261 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10262 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10264 cmd.num_entries = count;
10265 buff_len = sizeof(uint16_t) * count;
10266 desc.datalen = rte_cpu_to_le_16(buff_len);
10267 buff = (void *)entries;
10269 /* rule id is filled in destination field for deleting mirror rule */
10270 cmd.destination = rte_cpu_to_le_16(rule_id);
10272 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10273 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10274 cmd.seid = rte_cpu_to_le_16(seid);
10276 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10277 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10283 * i40e_mirror_rule_set
10284 * @dev: pointer to the hardware structure
10285 * @mirror_conf: mirror rule info
10286 * @sw_id: mirror rule's sw_id
10287 * @on: enable/disable
10289 * set a mirror rule.
10293 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10294 struct rte_eth_mirror_conf *mirror_conf,
10295 uint8_t sw_id, uint8_t on)
10297 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10298 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10299 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10300 struct i40e_mirror_rule *parent = NULL;
10301 uint16_t seid, dst_seid, rule_id;
10305 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10307 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10309 "mirror rule can not be configured without veb or vfs.");
10312 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10313 PMD_DRV_LOG(ERR, "mirror table is full.");
10316 if (mirror_conf->dst_pool > pf->vf_num) {
10317 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10318 mirror_conf->dst_pool);
10322 seid = pf->main_vsi->veb->seid;
10324 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10325 if (sw_id <= it->index) {
10331 if (mirr_rule && sw_id == mirr_rule->index) {
10333 PMD_DRV_LOG(ERR, "mirror rule exists.");
10336 ret = i40e_aq_del_mirror_rule(hw, seid,
10337 mirr_rule->rule_type,
10338 mirr_rule->entries,
10339 mirr_rule->num_entries, mirr_rule->id);
10342 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10343 ret, hw->aq.asq_last_status);
10346 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10347 rte_free(mirr_rule);
10348 pf->nb_mirror_rule--;
10352 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10356 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10357 sizeof(struct i40e_mirror_rule) , 0);
10359 PMD_DRV_LOG(ERR, "failed to allocate memory");
10360 return I40E_ERR_NO_MEMORY;
10362 switch (mirror_conf->rule_type) {
10363 case ETH_MIRROR_VLAN:
10364 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10365 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10366 mirr_rule->entries[j] =
10367 mirror_conf->vlan.vlan_id[i];
10372 PMD_DRV_LOG(ERR, "vlan is not specified.");
10373 rte_free(mirr_rule);
10376 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10378 case ETH_MIRROR_VIRTUAL_POOL_UP:
10379 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10380 /* check if the specified pool bit is out of range */
10381 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10382 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10383 rte_free(mirr_rule);
10386 for (i = 0, j = 0; i < pf->vf_num; i++) {
10387 if (mirror_conf->pool_mask & (1ULL << i)) {
10388 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10392 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10393 /* add pf vsi to entries */
10394 mirr_rule->entries[j] = pf->main_vsi_seid;
10398 PMD_DRV_LOG(ERR, "pool is not specified.");
10399 rte_free(mirr_rule);
10402 /* egress and ingress in aq commands means from switch but not port */
10403 mirr_rule->rule_type =
10404 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10405 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10406 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10408 case ETH_MIRROR_UPLINK_PORT:
10409 /* egress and ingress in aq commands means from switch but not port*/
10410 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10412 case ETH_MIRROR_DOWNLINK_PORT:
10413 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10416 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10417 mirror_conf->rule_type);
10418 rte_free(mirr_rule);
10422 /* If the dst_pool is equal to vf_num, consider it as PF */
10423 if (mirror_conf->dst_pool == pf->vf_num)
10424 dst_seid = pf->main_vsi_seid;
10426 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10428 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10429 mirr_rule->rule_type, mirr_rule->entries,
10433 "failed to add mirror rule: ret = %d, aq_err = %d.",
10434 ret, hw->aq.asq_last_status);
10435 rte_free(mirr_rule);
10439 mirr_rule->index = sw_id;
10440 mirr_rule->num_entries = j;
10441 mirr_rule->id = rule_id;
10442 mirr_rule->dst_vsi_seid = dst_seid;
10445 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10447 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10449 pf->nb_mirror_rule++;
10454 * i40e_mirror_rule_reset
10455 * @dev: pointer to the device
10456 * @sw_id: mirror rule's sw_id
10458 * reset a mirror rule.
10462 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10464 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10465 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10466 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10470 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10472 seid = pf->main_vsi->veb->seid;
10474 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10475 if (sw_id == it->index) {
10481 ret = i40e_aq_del_mirror_rule(hw, seid,
10482 mirr_rule->rule_type,
10483 mirr_rule->entries,
10484 mirr_rule->num_entries, mirr_rule->id);
10487 "failed to remove mirror rule: status = %d, aq_err = %d.",
10488 ret, hw->aq.asq_last_status);
10491 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10492 rte_free(mirr_rule);
10493 pf->nb_mirror_rule--;
10495 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10502 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10505 uint64_t systim_cycles;
10507 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10508 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10511 return systim_cycles;
10515 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10517 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10518 uint64_t rx_tstamp;
10520 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10521 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10528 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10530 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10531 uint64_t tx_tstamp;
10533 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10534 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10541 i40e_start_timecounters(struct rte_eth_dev *dev)
10543 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10544 struct i40e_adapter *adapter =
10545 (struct i40e_adapter *)dev->data->dev_private;
10546 struct rte_eth_link link;
10547 uint32_t tsync_inc_l;
10548 uint32_t tsync_inc_h;
10550 /* Get current link speed. */
10551 i40e_dev_link_update(dev, 1);
10552 rte_eth_linkstatus_get(dev, &link);
10554 switch (link.link_speed) {
10555 case ETH_SPEED_NUM_40G:
10556 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10557 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10559 case ETH_SPEED_NUM_10G:
10560 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10561 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10563 case ETH_SPEED_NUM_1G:
10564 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10565 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10572 /* Set the timesync increment value. */
10573 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10574 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10576 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10577 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10578 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10580 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10581 adapter->systime_tc.cc_shift = 0;
10582 adapter->systime_tc.nsec_mask = 0;
10584 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10585 adapter->rx_tstamp_tc.cc_shift = 0;
10586 adapter->rx_tstamp_tc.nsec_mask = 0;
10588 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10589 adapter->tx_tstamp_tc.cc_shift = 0;
10590 adapter->tx_tstamp_tc.nsec_mask = 0;
10594 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10596 struct i40e_adapter *adapter =
10597 (struct i40e_adapter *)dev->data->dev_private;
10599 adapter->systime_tc.nsec += delta;
10600 adapter->rx_tstamp_tc.nsec += delta;
10601 adapter->tx_tstamp_tc.nsec += delta;
10607 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10610 struct i40e_adapter *adapter =
10611 (struct i40e_adapter *)dev->data->dev_private;
10613 ns = rte_timespec_to_ns(ts);
10615 /* Set the timecounters to a new value. */
10616 adapter->systime_tc.nsec = ns;
10617 adapter->rx_tstamp_tc.nsec = ns;
10618 adapter->tx_tstamp_tc.nsec = ns;
10624 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10626 uint64_t ns, systime_cycles;
10627 struct i40e_adapter *adapter =
10628 (struct i40e_adapter *)dev->data->dev_private;
10630 systime_cycles = i40e_read_systime_cyclecounter(dev);
10631 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10632 *ts = rte_ns_to_timespec(ns);
10638 i40e_timesync_enable(struct rte_eth_dev *dev)
10640 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10641 uint32_t tsync_ctl_l;
10642 uint32_t tsync_ctl_h;
10644 /* Stop the timesync system time. */
10645 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10646 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10647 /* Reset the timesync system time value. */
10648 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10649 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10651 i40e_start_timecounters(dev);
10653 /* Clear timesync registers. */
10654 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10655 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10656 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10657 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10658 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10659 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10661 /* Enable timestamping of PTP packets. */
10662 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10663 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10665 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10666 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10667 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10669 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10670 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10676 i40e_timesync_disable(struct rte_eth_dev *dev)
10678 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10679 uint32_t tsync_ctl_l;
10680 uint32_t tsync_ctl_h;
10682 /* Disable timestamping of transmitted PTP packets. */
10683 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10684 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10686 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10687 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10689 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10690 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10692 /* Reset the timesync increment value. */
10693 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10694 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10700 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10701 struct timespec *timestamp, uint32_t flags)
10703 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10704 struct i40e_adapter *adapter =
10705 (struct i40e_adapter *)dev->data->dev_private;
10707 uint32_t sync_status;
10708 uint32_t index = flags & 0x03;
10709 uint64_t rx_tstamp_cycles;
10712 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10713 if ((sync_status & (1 << index)) == 0)
10716 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10717 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10718 *timestamp = rte_ns_to_timespec(ns);
10724 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10725 struct timespec *timestamp)
10727 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10728 struct i40e_adapter *adapter =
10729 (struct i40e_adapter *)dev->data->dev_private;
10731 uint32_t sync_status;
10732 uint64_t tx_tstamp_cycles;
10735 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10736 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10739 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10740 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10741 *timestamp = rte_ns_to_timespec(ns);
10747 * i40e_parse_dcb_configure - parse dcb configure from user
10748 * @dev: the device being configured
10749 * @dcb_cfg: pointer of the result of parse
10750 * @*tc_map: bit map of enabled traffic classes
10752 * Returns 0 on success, negative value on failure
10755 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10756 struct i40e_dcbx_config *dcb_cfg,
10759 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10760 uint8_t i, tc_bw, bw_lf;
10762 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10764 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10765 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10766 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10770 /* assume each tc has the same bw */
10771 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10772 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10773 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10774 /* to ensure the sum of tcbw is equal to 100 */
10775 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10776 for (i = 0; i < bw_lf; i++)
10777 dcb_cfg->etscfg.tcbwtable[i]++;
10779 /* assume each tc has the same Transmission Selection Algorithm */
10780 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10781 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10783 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10784 dcb_cfg->etscfg.prioritytable[i] =
10785 dcb_rx_conf->dcb_tc[i];
10787 /* FW needs one App to configure HW */
10788 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10789 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10790 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10791 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10793 if (dcb_rx_conf->nb_tcs == 0)
10794 *tc_map = 1; /* tc0 only */
10796 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10798 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10799 dcb_cfg->pfc.willing = 0;
10800 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10801 dcb_cfg->pfc.pfcenable = *tc_map;
10807 static enum i40e_status_code
10808 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10809 struct i40e_aqc_vsi_properties_data *info,
10810 uint8_t enabled_tcmap)
10812 enum i40e_status_code ret;
10813 int i, total_tc = 0;
10814 uint16_t qpnum_per_tc, bsf, qp_idx;
10815 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10816 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10817 uint16_t used_queues;
10819 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10820 if (ret != I40E_SUCCESS)
10823 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10824 if (enabled_tcmap & (1 << i))
10829 vsi->enabled_tc = enabled_tcmap;
10831 /* different VSI has different queues assigned */
10832 if (vsi->type == I40E_VSI_MAIN)
10833 used_queues = dev_data->nb_rx_queues -
10834 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10835 else if (vsi->type == I40E_VSI_VMDQ2)
10836 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10838 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10839 return I40E_ERR_NO_AVAILABLE_VSI;
10842 qpnum_per_tc = used_queues / total_tc;
10843 /* Number of queues per enabled TC */
10844 if (qpnum_per_tc == 0) {
10845 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10846 return I40E_ERR_INVALID_QP_ID;
10848 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10849 I40E_MAX_Q_PER_TC);
10850 bsf = rte_bsf32(qpnum_per_tc);
10853 * Configure TC and queue mapping parameters, for enabled TC,
10854 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10855 * default queue will serve it.
10858 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10859 if (vsi->enabled_tc & (1 << i)) {
10860 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10861 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10862 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10863 qp_idx += qpnum_per_tc;
10865 info->tc_mapping[i] = 0;
10868 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10869 if (vsi->type == I40E_VSI_SRIOV) {
10870 info->mapping_flags |=
10871 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10872 for (i = 0; i < vsi->nb_qps; i++)
10873 info->queue_mapping[i] =
10874 rte_cpu_to_le_16(vsi->base_queue + i);
10876 info->mapping_flags |=
10877 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10878 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10880 info->valid_sections |=
10881 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10883 return I40E_SUCCESS;
10887 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10888 * @veb: VEB to be configured
10889 * @tc_map: enabled TC bitmap
10891 * Returns 0 on success, negative value on failure
10893 static enum i40e_status_code
10894 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10896 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10897 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10898 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10899 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10900 enum i40e_status_code ret = I40E_SUCCESS;
10904 /* Check if enabled_tc is same as existing or new TCs */
10905 if (veb->enabled_tc == tc_map)
10908 /* configure tc bandwidth */
10909 memset(&veb_bw, 0, sizeof(veb_bw));
10910 veb_bw.tc_valid_bits = tc_map;
10911 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10912 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10913 if (tc_map & BIT_ULL(i))
10914 veb_bw.tc_bw_share_credits[i] = 1;
10916 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10920 "AQ command Config switch_comp BW allocation per TC failed = %d",
10921 hw->aq.asq_last_status);
10925 memset(&ets_query, 0, sizeof(ets_query));
10926 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10928 if (ret != I40E_SUCCESS) {
10930 "Failed to get switch_comp ETS configuration %u",
10931 hw->aq.asq_last_status);
10934 memset(&bw_query, 0, sizeof(bw_query));
10935 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10937 if (ret != I40E_SUCCESS) {
10939 "Failed to get switch_comp bandwidth configuration %u",
10940 hw->aq.asq_last_status);
10944 /* store and print out BW info */
10945 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10946 veb->bw_info.bw_max = ets_query.tc_bw_max;
10947 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10948 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10949 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10950 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10951 I40E_16_BIT_WIDTH);
10952 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10953 veb->bw_info.bw_ets_share_credits[i] =
10954 bw_query.tc_bw_share_credits[i];
10955 veb->bw_info.bw_ets_credits[i] =
10956 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10957 /* 4 bits per TC, 4th bit is reserved */
10958 veb->bw_info.bw_ets_max[i] =
10959 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10960 RTE_LEN2MASK(3, uint8_t));
10961 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10962 veb->bw_info.bw_ets_share_credits[i]);
10963 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10964 veb->bw_info.bw_ets_credits[i]);
10965 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10966 veb->bw_info.bw_ets_max[i]);
10969 veb->enabled_tc = tc_map;
10976 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10977 * @vsi: VSI to be configured
10978 * @tc_map: enabled TC bitmap
10980 * Returns 0 on success, negative value on failure
10982 static enum i40e_status_code
10983 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10985 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10986 struct i40e_vsi_context ctxt;
10987 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10988 enum i40e_status_code ret = I40E_SUCCESS;
10991 /* Check if enabled_tc is same as existing or new TCs */
10992 if (vsi->enabled_tc == tc_map)
10995 /* configure tc bandwidth */
10996 memset(&bw_data, 0, sizeof(bw_data));
10997 bw_data.tc_valid_bits = tc_map;
10998 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10999 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11000 if (tc_map & BIT_ULL(i))
11001 bw_data.tc_bw_credits[i] = 1;
11003 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11006 "AQ command Config VSI BW allocation per TC failed = %d",
11007 hw->aq.asq_last_status);
11010 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11011 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11013 /* Update Queue Pairs Mapping for currently enabled UPs */
11014 ctxt.seid = vsi->seid;
11015 ctxt.pf_num = hw->pf_id;
11017 ctxt.uplink_seid = vsi->uplink_seid;
11018 ctxt.info = vsi->info;
11020 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11024 /* Update the VSI after updating the VSI queue-mapping information */
11025 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11027 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11028 hw->aq.asq_last_status);
11031 /* update the local VSI info with updated queue map */
11032 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11033 sizeof(vsi->info.tc_mapping));
11034 rte_memcpy(&vsi->info.queue_mapping,
11035 &ctxt.info.queue_mapping,
11036 sizeof(vsi->info.queue_mapping));
11037 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11038 vsi->info.valid_sections = 0;
11040 /* query and update current VSI BW information */
11041 ret = i40e_vsi_get_bw_config(vsi);
11044 "Failed updating vsi bw info, err %s aq_err %s",
11045 i40e_stat_str(hw, ret),
11046 i40e_aq_str(hw, hw->aq.asq_last_status));
11050 vsi->enabled_tc = tc_map;
11057 * i40e_dcb_hw_configure - program the dcb setting to hw
11058 * @pf: pf the configuration is taken on
11059 * @new_cfg: new configuration
11060 * @tc_map: enabled TC bitmap
11062 * Returns 0 on success, negative value on failure
11064 static enum i40e_status_code
11065 i40e_dcb_hw_configure(struct i40e_pf *pf,
11066 struct i40e_dcbx_config *new_cfg,
11069 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11070 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11071 struct i40e_vsi *main_vsi = pf->main_vsi;
11072 struct i40e_vsi_list *vsi_list;
11073 enum i40e_status_code ret;
11077 /* Use the FW API if FW > v4.4*/
11078 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11079 (hw->aq.fw_maj_ver >= 5))) {
11081 "FW < v4.4, can not use FW LLDP API to configure DCB");
11082 return I40E_ERR_FIRMWARE_API_VERSION;
11085 /* Check if need reconfiguration */
11086 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11087 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11088 return I40E_SUCCESS;
11091 /* Copy the new config to the current config */
11092 *old_cfg = *new_cfg;
11093 old_cfg->etsrec = old_cfg->etscfg;
11094 ret = i40e_set_dcb_config(hw);
11096 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11097 i40e_stat_str(hw, ret),
11098 i40e_aq_str(hw, hw->aq.asq_last_status));
11101 /* set receive Arbiter to RR mode and ETS scheme by default */
11102 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11103 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11104 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11105 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11106 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11107 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11108 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11109 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11110 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11111 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11112 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11113 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11114 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11116 /* get local mib to check whether it is configured correctly */
11118 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11119 /* Get Local DCB Config */
11120 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11121 &hw->local_dcbx_config);
11123 /* if Veb is created, need to update TC of it at first */
11124 if (main_vsi->veb) {
11125 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11127 PMD_INIT_LOG(WARNING,
11128 "Failed configuring TC for VEB seid=%d",
11129 main_vsi->veb->seid);
11131 /* Update each VSI */
11132 i40e_vsi_config_tc(main_vsi, tc_map);
11133 if (main_vsi->veb) {
11134 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11135 /* Beside main VSI and VMDQ VSIs, only enable default
11136 * TC for other VSIs
11138 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11139 ret = i40e_vsi_config_tc(vsi_list->vsi,
11142 ret = i40e_vsi_config_tc(vsi_list->vsi,
11143 I40E_DEFAULT_TCMAP);
11145 PMD_INIT_LOG(WARNING,
11146 "Failed configuring TC for VSI seid=%d",
11147 vsi_list->vsi->seid);
11151 return I40E_SUCCESS;
11155 * i40e_dcb_init_configure - initial dcb config
11156 * @dev: device being configured
11157 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11159 * Returns 0 on success, negative value on failure
11162 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11164 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11165 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11168 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11169 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11173 /* DCB initialization:
11174 * Update DCB configuration from the Firmware and configure
11175 * LLDP MIB change event.
11177 if (sw_dcb == TRUE) {
11178 ret = i40e_init_dcb(hw);
11179 /* If lldp agent is stopped, the return value from
11180 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11181 * adminq status. Otherwise, it should return success.
11183 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11184 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11185 memset(&hw->local_dcbx_config, 0,
11186 sizeof(struct i40e_dcbx_config));
11187 /* set dcb default configuration */
11188 hw->local_dcbx_config.etscfg.willing = 0;
11189 hw->local_dcbx_config.etscfg.maxtcs = 0;
11190 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11191 hw->local_dcbx_config.etscfg.tsatable[0] =
11193 /* all UPs mapping to TC0 */
11194 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11195 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11196 hw->local_dcbx_config.etsrec =
11197 hw->local_dcbx_config.etscfg;
11198 hw->local_dcbx_config.pfc.willing = 0;
11199 hw->local_dcbx_config.pfc.pfccap =
11200 I40E_MAX_TRAFFIC_CLASS;
11201 /* FW needs one App to configure HW */
11202 hw->local_dcbx_config.numapps = 1;
11203 hw->local_dcbx_config.app[0].selector =
11204 I40E_APP_SEL_ETHTYPE;
11205 hw->local_dcbx_config.app[0].priority = 3;
11206 hw->local_dcbx_config.app[0].protocolid =
11207 I40E_APP_PROTOID_FCOE;
11208 ret = i40e_set_dcb_config(hw);
11211 "default dcb config fails. err = %d, aq_err = %d.",
11212 ret, hw->aq.asq_last_status);
11217 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11218 ret, hw->aq.asq_last_status);
11222 ret = i40e_aq_start_lldp(hw, NULL);
11223 if (ret != I40E_SUCCESS)
11224 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11226 ret = i40e_init_dcb(hw);
11228 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11230 "HW doesn't support DCBX offload.");
11235 "DCBX configuration failed, err = %d, aq_err = %d.",
11236 ret, hw->aq.asq_last_status);
11244 * i40e_dcb_setup - setup dcb related config
11245 * @dev: device being configured
11247 * Returns 0 on success, negative value on failure
11250 i40e_dcb_setup(struct rte_eth_dev *dev)
11252 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11253 struct i40e_dcbx_config dcb_cfg;
11254 uint8_t tc_map = 0;
11257 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11258 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11262 if (pf->vf_num != 0)
11263 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11265 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11267 PMD_INIT_LOG(ERR, "invalid dcb config");
11270 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11272 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11280 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11281 struct rte_eth_dcb_info *dcb_info)
11283 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11284 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11285 struct i40e_vsi *vsi = pf->main_vsi;
11286 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11287 uint16_t bsf, tc_mapping;
11290 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11291 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11293 dcb_info->nb_tcs = 1;
11294 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11295 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11296 for (i = 0; i < dcb_info->nb_tcs; i++)
11297 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11299 /* get queue mapping if vmdq is disabled */
11300 if (!pf->nb_cfg_vmdq_vsi) {
11301 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11302 if (!(vsi->enabled_tc & (1 << i)))
11304 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11305 dcb_info->tc_queue.tc_rxq[j][i].base =
11306 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11307 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11308 dcb_info->tc_queue.tc_txq[j][i].base =
11309 dcb_info->tc_queue.tc_rxq[j][i].base;
11310 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11311 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11312 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11313 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11314 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11319 /* get queue mapping if vmdq is enabled */
11321 vsi = pf->vmdq[j].vsi;
11322 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11323 if (!(vsi->enabled_tc & (1 << i)))
11325 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11326 dcb_info->tc_queue.tc_rxq[j][i].base =
11327 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11328 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11329 dcb_info->tc_queue.tc_txq[j][i].base =
11330 dcb_info->tc_queue.tc_rxq[j][i].base;
11331 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11332 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11333 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11334 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11335 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11338 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11343 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11345 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11346 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11348 uint16_t msix_intr;
11350 msix_intr = intr_handle->intr_vec[queue_id];
11351 if (msix_intr == I40E_MISC_VEC_ID)
11352 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11353 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11354 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11355 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11358 I40E_PFINT_DYN_CTLN(msix_intr -
11359 I40E_RX_VEC_START),
11360 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11361 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11362 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11364 I40E_WRITE_FLUSH(hw);
11365 rte_intr_enable(&pci_dev->intr_handle);
11371 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11373 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11374 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11375 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11376 uint16_t msix_intr;
11378 msix_intr = intr_handle->intr_vec[queue_id];
11379 if (msix_intr == I40E_MISC_VEC_ID)
11380 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11381 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11384 I40E_PFINT_DYN_CTLN(msix_intr -
11385 I40E_RX_VEC_START),
11386 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11387 I40E_WRITE_FLUSH(hw);
11392 static int i40e_get_regs(struct rte_eth_dev *dev,
11393 struct rte_dev_reg_info *regs)
11395 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11396 uint32_t *ptr_data = regs->data;
11397 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11398 const struct i40e_reg_info *reg_info;
11400 if (ptr_data == NULL) {
11401 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11402 regs->width = sizeof(uint32_t);
11406 /* The first few registers have to be read using AQ operations */
11408 while (i40e_regs_adminq[reg_idx].name) {
11409 reg_info = &i40e_regs_adminq[reg_idx++];
11410 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11412 arr_idx2 <= reg_info->count2;
11414 reg_offset = arr_idx * reg_info->stride1 +
11415 arr_idx2 * reg_info->stride2;
11416 reg_offset += reg_info->base_addr;
11417 ptr_data[reg_offset >> 2] =
11418 i40e_read_rx_ctl(hw, reg_offset);
11422 /* The remaining registers can be read using primitives */
11424 while (i40e_regs_others[reg_idx].name) {
11425 reg_info = &i40e_regs_others[reg_idx++];
11426 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11428 arr_idx2 <= reg_info->count2;
11430 reg_offset = arr_idx * reg_info->stride1 +
11431 arr_idx2 * reg_info->stride2;
11432 reg_offset += reg_info->base_addr;
11433 ptr_data[reg_offset >> 2] =
11434 I40E_READ_REG(hw, reg_offset);
11441 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11443 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11445 /* Convert word count to byte count */
11446 return hw->nvm.sr_size << 1;
11449 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11450 struct rte_dev_eeprom_info *eeprom)
11452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11453 uint16_t *data = eeprom->data;
11454 uint16_t offset, length, cnt_words;
11457 offset = eeprom->offset >> 1;
11458 length = eeprom->length >> 1;
11459 cnt_words = length;
11461 if (offset > hw->nvm.sr_size ||
11462 offset + length > hw->nvm.sr_size) {
11463 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11467 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11469 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11470 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11471 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11478 static int i40e_get_module_info(struct rte_eth_dev *dev,
11479 struct rte_eth_dev_module_info *modinfo)
11481 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11482 uint32_t sff8472_comp = 0;
11483 uint32_t sff8472_swap = 0;
11484 uint32_t sff8636_rev = 0;
11485 i40e_status status;
11488 /* Check if firmware supports reading module EEPROM. */
11489 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11491 "Module EEPROM memory read not supported. "
11492 "Please update the NVM image.\n");
11496 status = i40e_update_link_info(hw);
11500 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11502 "Cannot read module EEPROM memory. "
11503 "No module connected.\n");
11507 type = hw->phy.link_info.module_type[0];
11510 case I40E_MODULE_TYPE_SFP:
11511 status = i40e_aq_get_phy_register(hw,
11512 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11513 I40E_I2C_EEPROM_DEV_ADDR,
11514 I40E_MODULE_SFF_8472_COMP,
11515 &sff8472_comp, NULL);
11519 status = i40e_aq_get_phy_register(hw,
11520 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11521 I40E_I2C_EEPROM_DEV_ADDR,
11522 I40E_MODULE_SFF_8472_SWAP,
11523 &sff8472_swap, NULL);
11527 /* Check if the module requires address swap to access
11528 * the other EEPROM memory page.
11530 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11531 PMD_DRV_LOG(WARNING,
11532 "Module address swap to access "
11533 "page 0xA2 is not supported.\n");
11534 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11535 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11536 } else if (sff8472_comp == 0x00) {
11537 /* Module is not SFF-8472 compliant */
11538 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11539 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11541 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11542 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11545 case I40E_MODULE_TYPE_QSFP_PLUS:
11546 /* Read from memory page 0. */
11547 status = i40e_aq_get_phy_register(hw,
11548 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11550 I40E_MODULE_REVISION_ADDR,
11551 &sff8636_rev, NULL);
11554 /* Determine revision compliance byte */
11555 if (sff8636_rev > 0x02) {
11556 /* Module is SFF-8636 compliant */
11557 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11558 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11560 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11561 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11564 case I40E_MODULE_TYPE_QSFP28:
11565 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11566 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11569 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11575 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11576 struct rte_dev_eeprom_info *info)
11578 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11579 bool is_sfp = false;
11580 i40e_status status;
11581 uint8_t *data = info->data;
11582 uint32_t value = 0;
11585 if (!info || !info->length || !data)
11588 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11591 for (i = 0; i < info->length; i++) {
11592 u32 offset = i + info->offset;
11593 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11595 /* Check if we need to access the other memory page */
11597 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11598 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11599 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11602 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11603 /* Compute memory page number and offset. */
11604 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11608 status = i40e_aq_get_phy_register(hw,
11609 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11610 addr, offset, &value, NULL);
11613 data[i] = (uint8_t)value;
11618 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11619 struct ether_addr *mac_addr)
11621 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11622 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11623 struct i40e_vsi *vsi = pf->main_vsi;
11624 struct i40e_mac_filter_info mac_filter;
11625 struct i40e_mac_filter *f;
11628 if (!is_valid_assigned_ether_addr(mac_addr)) {
11629 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11633 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11634 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11639 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11643 mac_filter = f->mac_info;
11644 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11645 if (ret != I40E_SUCCESS) {
11646 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11649 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11650 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11651 if (ret != I40E_SUCCESS) {
11652 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11655 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11657 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11658 mac_addr->addr_bytes, NULL);
11659 if (ret != I40E_SUCCESS) {
11660 PMD_DRV_LOG(ERR, "Failed to change mac");
11668 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11670 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11671 struct rte_eth_dev_data *dev_data = pf->dev_data;
11672 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11675 /* check if mtu is within the allowed range */
11676 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11679 /* mtu setting is forbidden if port is start */
11680 if (dev_data->dev_started) {
11681 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11682 dev_data->port_id);
11686 if (frame_size > ETHER_MAX_LEN)
11687 dev_data->dev_conf.rxmode.offloads |=
11688 DEV_RX_OFFLOAD_JUMBO_FRAME;
11690 dev_data->dev_conf.rxmode.offloads &=
11691 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11693 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11698 /* Restore ethertype filter */
11700 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11702 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11703 struct i40e_ethertype_filter_list
11704 *ethertype_list = &pf->ethertype.ethertype_list;
11705 struct i40e_ethertype_filter *f;
11706 struct i40e_control_filter_stats stats;
11709 TAILQ_FOREACH(f, ethertype_list, rules) {
11711 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11712 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11713 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11714 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11715 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11717 memset(&stats, 0, sizeof(stats));
11718 i40e_aq_add_rem_control_packet_filter(hw,
11719 f->input.mac_addr.addr_bytes,
11720 f->input.ether_type,
11721 flags, pf->main_vsi->seid,
11722 f->queue, 1, &stats, NULL);
11724 PMD_DRV_LOG(INFO, "Ethertype filter:"
11725 " mac_etype_used = %u, etype_used = %u,"
11726 " mac_etype_free = %u, etype_free = %u",
11727 stats.mac_etype_used, stats.etype_used,
11728 stats.mac_etype_free, stats.etype_free);
11731 /* Restore tunnel filter */
11733 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11735 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11736 struct i40e_vsi *vsi;
11737 struct i40e_pf_vf *vf;
11738 struct i40e_tunnel_filter_list
11739 *tunnel_list = &pf->tunnel.tunnel_list;
11740 struct i40e_tunnel_filter *f;
11741 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11742 bool big_buffer = 0;
11744 TAILQ_FOREACH(f, tunnel_list, rules) {
11746 vsi = pf->main_vsi;
11748 vf = &pf->vfs[f->vf_id];
11751 memset(&cld_filter, 0, sizeof(cld_filter));
11752 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11753 (struct ether_addr *)&cld_filter.element.outer_mac);
11754 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11755 (struct ether_addr *)&cld_filter.element.inner_mac);
11756 cld_filter.element.inner_vlan = f->input.inner_vlan;
11757 cld_filter.element.flags = f->input.flags;
11758 cld_filter.element.tenant_id = f->input.tenant_id;
11759 cld_filter.element.queue_number = f->queue;
11760 rte_memcpy(cld_filter.general_fields,
11761 f->input.general_fields,
11762 sizeof(f->input.general_fields));
11764 if (((f->input.flags &
11765 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11766 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11768 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11769 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11771 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11772 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11776 i40e_aq_add_cloud_filters_big_buffer(hw,
11777 vsi->seid, &cld_filter, 1);
11779 i40e_aq_add_cloud_filters(hw, vsi->seid,
11780 &cld_filter.element, 1);
11784 /* Restore rss filter */
11786 i40e_rss_filter_restore(struct i40e_pf *pf)
11788 struct i40e_rte_flow_rss_conf *conf =
11790 if (conf->conf.queue_num)
11791 i40e_config_rss_filter(pf, conf, TRUE);
11795 i40e_filter_restore(struct i40e_pf *pf)
11797 i40e_ethertype_filter_restore(pf);
11798 i40e_tunnel_filter_restore(pf);
11799 i40e_fdir_filter_restore(pf);
11800 i40e_rss_filter_restore(pf);
11804 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11806 if (strcmp(dev->device->driver->name, drv->driver.name))
11813 is_i40e_supported(struct rte_eth_dev *dev)
11815 return is_device_supported(dev, &rte_i40e_pmd);
11818 struct i40e_customized_pctype*
11819 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11823 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11824 if (pf->customized_pctype[i].index == index)
11825 return &pf->customized_pctype[i];
11831 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11832 uint32_t pkg_size, uint32_t proto_num,
11833 struct rte_pmd_i40e_proto_info *proto,
11834 enum rte_pmd_i40e_package_op op)
11836 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11837 uint32_t pctype_num;
11838 struct rte_pmd_i40e_ptype_info *pctype;
11839 uint32_t buff_size;
11840 struct i40e_customized_pctype *new_pctype = NULL;
11842 uint8_t pctype_value;
11847 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11848 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11849 PMD_DRV_LOG(ERR, "Unsupported operation.");
11853 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11854 (uint8_t *)&pctype_num, sizeof(pctype_num),
11855 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11857 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11861 PMD_DRV_LOG(INFO, "No new pctype added");
11865 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11866 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11868 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11871 /* get information about new pctype list */
11872 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11873 (uint8_t *)pctype, buff_size,
11874 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11876 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11881 /* Update customized pctype. */
11882 for (i = 0; i < pctype_num; i++) {
11883 pctype_value = pctype[i].ptype_id;
11884 memset(name, 0, sizeof(name));
11885 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11886 proto_id = pctype[i].protocols[j];
11887 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11889 for (n = 0; n < proto_num; n++) {
11890 if (proto[n].proto_id != proto_id)
11892 strcat(name, proto[n].name);
11897 name[strlen(name) - 1] = '\0';
11898 if (!strcmp(name, "GTPC"))
11900 i40e_find_customized_pctype(pf,
11901 I40E_CUSTOMIZED_GTPC);
11902 else if (!strcmp(name, "GTPU_IPV4"))
11904 i40e_find_customized_pctype(pf,
11905 I40E_CUSTOMIZED_GTPU_IPV4);
11906 else if (!strcmp(name, "GTPU_IPV6"))
11908 i40e_find_customized_pctype(pf,
11909 I40E_CUSTOMIZED_GTPU_IPV6);
11910 else if (!strcmp(name, "GTPU"))
11912 i40e_find_customized_pctype(pf,
11913 I40E_CUSTOMIZED_GTPU);
11915 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11916 new_pctype->pctype = pctype_value;
11917 new_pctype->valid = true;
11919 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11920 new_pctype->valid = false;
11930 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11931 uint32_t pkg_size, uint32_t proto_num,
11932 struct rte_pmd_i40e_proto_info *proto,
11933 enum rte_pmd_i40e_package_op op)
11935 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11936 uint16_t port_id = dev->data->port_id;
11937 uint32_t ptype_num;
11938 struct rte_pmd_i40e_ptype_info *ptype;
11939 uint32_t buff_size;
11941 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11946 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11947 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11948 PMD_DRV_LOG(ERR, "Unsupported operation.");
11952 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11953 rte_pmd_i40e_ptype_mapping_reset(port_id);
11957 /* get information about new ptype num */
11958 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11959 (uint8_t *)&ptype_num, sizeof(ptype_num),
11960 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11962 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11966 PMD_DRV_LOG(INFO, "No new ptype added");
11970 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11971 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11973 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11977 /* get information about new ptype list */
11978 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11979 (uint8_t *)ptype, buff_size,
11980 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11982 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11987 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11988 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11989 if (!ptype_mapping) {
11990 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11995 /* Update ptype mapping table. */
11996 for (i = 0; i < ptype_num; i++) {
11997 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11998 ptype_mapping[i].sw_ptype = 0;
12000 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12001 proto_id = ptype[i].protocols[j];
12002 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12004 for (n = 0; n < proto_num; n++) {
12005 if (proto[n].proto_id != proto_id)
12007 memset(name, 0, sizeof(name));
12008 strcpy(name, proto[n].name);
12009 if (!strncasecmp(name, "PPPOE", 5))
12010 ptype_mapping[i].sw_ptype |=
12011 RTE_PTYPE_L2_ETHER_PPPOE;
12012 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12014 ptype_mapping[i].sw_ptype |=
12015 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12016 ptype_mapping[i].sw_ptype |=
12018 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12020 ptype_mapping[i].sw_ptype |=
12021 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12022 ptype_mapping[i].sw_ptype |=
12023 RTE_PTYPE_INNER_L4_FRAG;
12024 } else if (!strncasecmp(name, "OIPV4", 5)) {
12025 ptype_mapping[i].sw_ptype |=
12026 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12028 } else if (!strncasecmp(name, "IPV4", 4) &&
12030 ptype_mapping[i].sw_ptype |=
12031 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12032 else if (!strncasecmp(name, "IPV4", 4) &&
12034 ptype_mapping[i].sw_ptype |=
12035 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12036 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12038 ptype_mapping[i].sw_ptype |=
12039 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12040 ptype_mapping[i].sw_ptype |=
12042 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12044 ptype_mapping[i].sw_ptype |=
12045 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12046 ptype_mapping[i].sw_ptype |=
12047 RTE_PTYPE_INNER_L4_FRAG;
12048 } else if (!strncasecmp(name, "OIPV6", 5)) {
12049 ptype_mapping[i].sw_ptype |=
12050 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12052 } else if (!strncasecmp(name, "IPV6", 4) &&
12054 ptype_mapping[i].sw_ptype |=
12055 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12056 else if (!strncasecmp(name, "IPV6", 4) &&
12058 ptype_mapping[i].sw_ptype |=
12059 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12060 else if (!strncasecmp(name, "UDP", 3) &&
12062 ptype_mapping[i].sw_ptype |=
12064 else if (!strncasecmp(name, "UDP", 3) &&
12066 ptype_mapping[i].sw_ptype |=
12067 RTE_PTYPE_INNER_L4_UDP;
12068 else if (!strncasecmp(name, "TCP", 3) &&
12070 ptype_mapping[i].sw_ptype |=
12072 else if (!strncasecmp(name, "TCP", 3) &&
12074 ptype_mapping[i].sw_ptype |=
12075 RTE_PTYPE_INNER_L4_TCP;
12076 else if (!strncasecmp(name, "SCTP", 4) &&
12078 ptype_mapping[i].sw_ptype |=
12080 else if (!strncasecmp(name, "SCTP", 4) &&
12082 ptype_mapping[i].sw_ptype |=
12083 RTE_PTYPE_INNER_L4_SCTP;
12084 else if ((!strncasecmp(name, "ICMP", 4) ||
12085 !strncasecmp(name, "ICMPV6", 6)) &&
12087 ptype_mapping[i].sw_ptype |=
12089 else if ((!strncasecmp(name, "ICMP", 4) ||
12090 !strncasecmp(name, "ICMPV6", 6)) &&
12092 ptype_mapping[i].sw_ptype |=
12093 RTE_PTYPE_INNER_L4_ICMP;
12094 else if (!strncasecmp(name, "GTPC", 4)) {
12095 ptype_mapping[i].sw_ptype |=
12096 RTE_PTYPE_TUNNEL_GTPC;
12098 } else if (!strncasecmp(name, "GTPU", 4)) {
12099 ptype_mapping[i].sw_ptype |=
12100 RTE_PTYPE_TUNNEL_GTPU;
12102 } else if (!strncasecmp(name, "GRENAT", 6)) {
12103 ptype_mapping[i].sw_ptype |=
12104 RTE_PTYPE_TUNNEL_GRENAT;
12106 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
12107 ptype_mapping[i].sw_ptype |=
12108 RTE_PTYPE_TUNNEL_L2TP;
12117 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12120 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12122 rte_free(ptype_mapping);
12128 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12129 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12131 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12132 uint32_t proto_num;
12133 struct rte_pmd_i40e_proto_info *proto;
12134 uint32_t buff_size;
12138 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12139 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12140 PMD_DRV_LOG(ERR, "Unsupported operation.");
12144 /* get information about protocol number */
12145 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12146 (uint8_t *)&proto_num, sizeof(proto_num),
12147 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12149 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12153 PMD_DRV_LOG(INFO, "No new protocol added");
12157 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12158 proto = rte_zmalloc("new_proto", buff_size, 0);
12160 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12164 /* get information about protocol list */
12165 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12166 (uint8_t *)proto, buff_size,
12167 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12169 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12174 /* Check if GTP is supported. */
12175 for (i = 0; i < proto_num; i++) {
12176 if (!strncmp(proto[i].name, "GTP", 3)) {
12177 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12178 pf->gtp_support = true;
12180 pf->gtp_support = false;
12185 /* Update customized pctype info */
12186 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12187 proto_num, proto, op);
12189 PMD_DRV_LOG(INFO, "No pctype is updated.");
12191 /* Update customized ptype info */
12192 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12193 proto_num, proto, op);
12195 PMD_DRV_LOG(INFO, "No ptype is updated.");
12200 /* Create a QinQ cloud filter
12202 * The Fortville NIC has limited resources for tunnel filters,
12203 * so we can only reuse existing filters.
12205 * In step 1 we define which Field Vector fields can be used for
12207 * As we do not have the inner tag defined as a field,
12208 * we have to define it first, by reusing one of L1 entries.
12210 * In step 2 we are replacing one of existing filter types with
12211 * a new one for QinQ.
12212 * As we reusing L1 and replacing L2, some of the default filter
12213 * types will disappear,which depends on L1 and L2 entries we reuse.
12215 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12217 * 1. Create L1 filter of outer vlan (12b) which will be in use
12218 * later when we define the cloud filter.
12219 * a. Valid_flags.replace_cloud = 0
12220 * b. Old_filter = 10 (Stag_Inner_Vlan)
12221 * c. New_filter = 0x10
12222 * d. TR bit = 0xff (optional, not used here)
12223 * e. Buffer – 2 entries:
12224 * i. Byte 0 = 8 (outer vlan FV index).
12226 * Byte 2-3 = 0x0fff
12227 * ii. Byte 0 = 37 (inner vlan FV index).
12229 * Byte 2-3 = 0x0fff
12232 * 2. Create cloud filter using two L1 filters entries: stag and
12233 * new filter(outer vlan+ inner vlan)
12234 * a. Valid_flags.replace_cloud = 1
12235 * b. Old_filter = 1 (instead of outer IP)
12236 * c. New_filter = 0x10
12237 * d. Buffer – 2 entries:
12238 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12239 * Byte 1-3 = 0 (rsv)
12240 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12241 * Byte 9-11 = 0 (rsv)
12244 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12246 int ret = -ENOTSUP;
12247 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12248 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12249 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12250 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12252 if (pf->support_multi_driver) {
12253 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12258 memset(&filter_replace, 0,
12259 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12260 memset(&filter_replace_buf, 0,
12261 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12263 /* create L1 filter */
12264 filter_replace.old_filter_type =
12265 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12266 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12267 filter_replace.tr_bit = 0;
12269 /* Prepare the buffer, 2 entries */
12270 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12271 filter_replace_buf.data[0] |=
12272 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12273 /* Field Vector 12b mask */
12274 filter_replace_buf.data[2] = 0xff;
12275 filter_replace_buf.data[3] = 0x0f;
12276 filter_replace_buf.data[4] =
12277 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12278 filter_replace_buf.data[4] |=
12279 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12280 /* Field Vector 12b mask */
12281 filter_replace_buf.data[6] = 0xff;
12282 filter_replace_buf.data[7] = 0x0f;
12283 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12284 &filter_replace_buf);
12285 if (ret != I40E_SUCCESS)
12288 if (filter_replace.old_filter_type !=
12289 filter_replace.new_filter_type)
12290 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12291 " original: 0x%x, new: 0x%x",
12293 filter_replace.old_filter_type,
12294 filter_replace.new_filter_type);
12296 /* Apply the second L2 cloud filter */
12297 memset(&filter_replace, 0,
12298 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12299 memset(&filter_replace_buf, 0,
12300 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12302 /* create L2 filter, input for L2 filter will be L1 filter */
12303 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12304 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12305 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12307 /* Prepare the buffer, 2 entries */
12308 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12309 filter_replace_buf.data[0] |=
12310 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12311 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12312 filter_replace_buf.data[4] |=
12313 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12314 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12315 &filter_replace_buf);
12316 if (!ret && (filter_replace.old_filter_type !=
12317 filter_replace.new_filter_type)) {
12318 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12319 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12320 " original: 0x%x, new: 0x%x",
12322 filter_replace.old_filter_type,
12323 filter_replace.new_filter_type);
12329 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12330 const struct rte_flow_action_rss *in)
12332 if (in->key_len > RTE_DIM(out->key) ||
12333 in->queue_num > RTE_DIM(out->queue))
12335 out->conf = (struct rte_flow_action_rss){
12337 .level = in->level,
12338 .types = in->types,
12339 .key_len = in->key_len,
12340 .queue_num = in->queue_num,
12341 .key = memcpy(out->key, in->key, in->key_len),
12342 .queue = memcpy(out->queue, in->queue,
12343 sizeof(*in->queue) * in->queue_num),
12349 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12350 const struct rte_flow_action_rss *with)
12352 return (comp->func == with->func &&
12353 comp->level == with->level &&
12354 comp->types == with->types &&
12355 comp->key_len == with->key_len &&
12356 comp->queue_num == with->queue_num &&
12357 !memcmp(comp->key, with->key, with->key_len) &&
12358 !memcmp(comp->queue, with->queue,
12359 sizeof(*with->queue) * with->queue_num));
12363 i40e_config_rss_filter(struct i40e_pf *pf,
12364 struct i40e_rte_flow_rss_conf *conf, bool add)
12366 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12367 uint32_t i, lut = 0;
12369 struct rte_eth_rss_conf rss_conf = {
12370 .rss_key = conf->conf.key_len ?
12371 (void *)(uintptr_t)conf->conf.key : NULL,
12372 .rss_key_len = conf->conf.key_len,
12373 .rss_hf = conf->conf.types,
12375 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12378 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12379 i40e_pf_disable_rss(pf);
12380 memset(rss_info, 0,
12381 sizeof(struct i40e_rte_flow_rss_conf));
12387 if (rss_info->conf.queue_num)
12390 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12391 * It's necessary to calculate the actual PF queues that are configured.
12393 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12394 num = i40e_pf_calc_configured_queues_num(pf);
12396 num = pf->dev_data->nb_rx_queues;
12398 num = RTE_MIN(num, conf->conf.queue_num);
12399 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12403 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12407 /* Fill in redirection table */
12408 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12411 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12412 hw->func_caps.rss_table_entry_width) - 1));
12414 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12417 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12418 i40e_pf_disable_rss(pf);
12421 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12422 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12423 /* Random default keys */
12424 static uint32_t rss_key_default[] = {0x6b793944,
12425 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12426 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12427 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12429 rss_conf.rss_key = (uint8_t *)rss_key_default;
12430 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12434 i40e_hw_rss_hash_set(pf, &rss_conf);
12436 if (i40e_rss_conf_init(rss_info, &conf->conf))
12442 RTE_INIT(i40e_init_log);
12444 i40e_init_log(void)
12446 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12447 if (i40e_logtype_init >= 0)
12448 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12449 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12450 if (i40e_logtype_driver >= 0)
12451 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12454 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12455 QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12456 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");