4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
80 /* Flow control default timer */
81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
83 /* Flow control default high water */
84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
86 /* Flow control default low water */
87 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Receive Average Packet Size in Byte*/
99 #define I40E_PACKET_AVERAGE_SIZE 128
101 /* Mask of PF interrupt causes */
102 #define I40E_PFINT_ICR0_ENA_MASK ( \
103 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
104 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
105 I40E_PFINT_ICR0_ENA_GRST_MASK | \
106 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
107 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
109 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
111 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
112 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
114 #define I40E_FLOW_TYPES ( \
115 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
116 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
125 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
127 /* Additional timesync values. */
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
133 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
135 #define I40E_MAX_PERCENT 100
136 #define I40E_DEFAULT_DCB_APP_NUM 1
137 #define I40E_DEFAULT_DCB_APP_PRIO 3
139 #define I40E_INSET_NONE 0x00000000000000000ULL
142 #define I40E_INSET_DMAC 0x0000000000000001ULL
143 #define I40E_INSET_SMAC 0x0000000000000002ULL
144 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
145 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
146 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
149 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
150 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
151 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
152 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
153 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
154 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
155 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
157 /* bit 16 ~ bit 31 */
158 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
159 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
160 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
161 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
162 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
163 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
164 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
165 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
167 /* bit 32 ~ bit 47, tunnel fields */
168 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
169 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
170 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
171 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
172 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
173 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
175 /* bit 48 ~ bit 55 */
176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
178 /* bit 56 ~ bit 63, Flex Payload */
179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD \
188 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
189 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
190 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
191 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
194 * Below are values for writing un-exposed registers suggested
197 /* Destination MAC address */
198 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
199 /* Source MAC address */
200 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
202 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
205 /* Single VLAN tag in the inner L2 header */
206 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
207 /* Source IPv4 address */
208 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
209 /* Destination IPv4 address */
210 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
211 /* IPv4 Type of Service (TOS) */
212 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
214 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
215 /* IPv4 Time to Live */
216 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
217 /* Source IPv6 address */
218 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
219 /* Destination IPv6 address */
220 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
221 /* IPv6 Traffic Class (TC) */
222 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
223 /* IPv6 Next Header */
224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
228 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
229 /* Destination L4 port */
230 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
231 /* SCTP verification tag */
232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
235 /* Source port of tunneling UDP */
236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
237 /* Destination port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
239 /* UDP Tunneling ID, NVGRE/GRE key */
240 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
241 /* Last ether type */
242 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
243 /* Tunneling outer destination IPv4 address */
244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
245 /* Tunneling outer destination IPv6 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
247 /* 1st word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
249 /* 2nd word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
251 /* 3rd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
253 /* 4th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
255 /* 5th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
257 /* 6th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
259 /* 7th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
261 /* 8th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
263 /* all 8 words flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
265 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
267 #define I40E_TRANSLATE_INSET 0
268 #define I40E_TRANSLATE_REG 1
270 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
271 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
272 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
273 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
275 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
277 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
280 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
282 /* PCI offset for querying capability */
283 #define PCI_DEV_CAP_REG 0xA4
284 /* PCI offset for enabling/disabling Extended Tag */
285 #define PCI_DEV_CTRL_REG 0xA8
286 /* Bit mask of Extended Tag capability */
287 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
288 /* Bit shift of Extended Tag enable/disable */
289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
290 /* Bit mask of Extended Tag enable/disable */
291 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
295 static int i40e_dev_configure(struct rte_eth_dev *dev);
296 static int i40e_dev_start(struct rte_eth_dev *dev);
297 static void i40e_dev_stop(struct rte_eth_dev *dev);
298 static void i40e_dev_close(struct rte_eth_dev *dev);
299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
306 struct rte_eth_stats *stats);
307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
308 struct rte_eth_xstats *xstats, unsigned n);
309 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
310 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
314 static void i40e_dev_info_get(struct rte_eth_dev *dev,
315 struct rte_eth_dev_info *dev_info);
316 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
319 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
320 enum rte_vlan_type vlan_type,
322 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
323 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
326 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
327 static int i40e_dev_led_on(struct rte_eth_dev *dev);
328 static int i40e_dev_led_off(struct rte_eth_dev *dev);
329 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
330 struct rte_eth_fc_conf *fc_conf);
331 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
332 struct rte_eth_fc_conf *fc_conf);
333 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
334 struct rte_eth_pfc_conf *pfc_conf);
335 static void i40e_macaddr_add(struct rte_eth_dev *dev,
336 struct ether_addr *mac_addr,
339 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
340 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
341 struct rte_eth_rss_reta_entry64 *reta_conf,
343 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
344 struct rte_eth_rss_reta_entry64 *reta_conf,
347 static int i40e_get_cap(struct i40e_hw *hw);
348 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
349 static int i40e_pf_setup(struct i40e_pf *pf);
350 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
351 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
352 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
353 static int i40e_dcb_setup(struct rte_eth_dev *dev);
354 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
355 bool offset_loaded, uint64_t *offset, uint64_t *stat);
356 static void i40e_stat_update_48(struct i40e_hw *hw,
362 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
363 static void i40e_dev_interrupt_handler(
364 __rte_unused struct rte_intr_handle *handle, void *param);
365 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
366 uint32_t base, uint32_t num);
367 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
368 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
370 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
372 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
373 static int i40e_veb_release(struct i40e_veb *veb);
374 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
375 struct i40e_vsi *vsi);
376 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
377 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
378 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
379 struct i40e_macvlan_filter *mv_f,
381 struct ether_addr *addr);
382 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
383 struct i40e_macvlan_filter *mv_f,
386 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
387 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
388 struct rte_eth_rss_conf *rss_conf);
389 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
390 struct rte_eth_rss_conf *rss_conf);
391 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
392 struct rte_eth_udp_tunnel *udp_tunnel);
393 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
394 struct rte_eth_udp_tunnel *udp_tunnel);
395 static void i40e_filter_input_set_init(struct i40e_pf *pf);
396 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
397 struct rte_eth_ethertype_filter *filter,
399 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
400 enum rte_filter_op filter_op,
402 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
403 enum rte_filter_type filter_type,
404 enum rte_filter_op filter_op,
406 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
407 struct rte_eth_dcb_info *dcb_info);
408 static void i40e_configure_registers(struct i40e_hw *hw);
409 static void i40e_hw_init(struct rte_eth_dev *dev);
410 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
411 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
412 struct rte_eth_mirror_conf *mirror_conf,
413 uint8_t sw_id, uint8_t on);
414 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
416 static int i40e_timesync_enable(struct rte_eth_dev *dev);
417 static int i40e_timesync_disable(struct rte_eth_dev *dev);
418 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
419 struct timespec *timestamp,
421 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
422 struct timespec *timestamp);
423 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
425 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
427 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
428 struct timespec *timestamp);
429 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
430 const struct timespec *timestamp);
432 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
434 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
437 static int i40e_get_reg_length(struct rte_eth_dev *dev);
439 static int i40e_get_regs(struct rte_eth_dev *dev,
440 struct rte_dev_reg_info *regs);
442 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
444 static int i40e_get_eeprom(struct rte_eth_dev *dev,
445 struct rte_dev_eeprom_info *eeprom);
447 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
448 struct ether_addr *mac_addr);
450 static const struct rte_pci_id pci_id_i40e_map[] = {
451 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
452 #include "rte_pci_dev_ids.h"
453 { .vendor_id = 0, /* sentinel */ },
456 static const struct eth_dev_ops i40e_eth_dev_ops = {
457 .dev_configure = i40e_dev_configure,
458 .dev_start = i40e_dev_start,
459 .dev_stop = i40e_dev_stop,
460 .dev_close = i40e_dev_close,
461 .promiscuous_enable = i40e_dev_promiscuous_enable,
462 .promiscuous_disable = i40e_dev_promiscuous_disable,
463 .allmulticast_enable = i40e_dev_allmulticast_enable,
464 .allmulticast_disable = i40e_dev_allmulticast_disable,
465 .dev_set_link_up = i40e_dev_set_link_up,
466 .dev_set_link_down = i40e_dev_set_link_down,
467 .link_update = i40e_dev_link_update,
468 .stats_get = i40e_dev_stats_get,
469 .xstats_get = i40e_dev_xstats_get,
470 .stats_reset = i40e_dev_stats_reset,
471 .xstats_reset = i40e_dev_stats_reset,
472 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
473 .dev_infos_get = i40e_dev_info_get,
474 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
475 .vlan_filter_set = i40e_vlan_filter_set,
476 .vlan_tpid_set = i40e_vlan_tpid_set,
477 .vlan_offload_set = i40e_vlan_offload_set,
478 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
479 .vlan_pvid_set = i40e_vlan_pvid_set,
480 .rx_queue_start = i40e_dev_rx_queue_start,
481 .rx_queue_stop = i40e_dev_rx_queue_stop,
482 .tx_queue_start = i40e_dev_tx_queue_start,
483 .tx_queue_stop = i40e_dev_tx_queue_stop,
484 .rx_queue_setup = i40e_dev_rx_queue_setup,
485 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
486 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
487 .rx_queue_release = i40e_dev_rx_queue_release,
488 .rx_queue_count = i40e_dev_rx_queue_count,
489 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .filter_ctrl = i40e_dev_filter_ctrl,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .mirror_rule_set = i40e_mirror_rule_set,
509 .mirror_rule_reset = i40e_mirror_rule_reset,
510 .timesync_enable = i40e_timesync_enable,
511 .timesync_disable = i40e_timesync_disable,
512 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
513 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
514 .get_dcb_info = i40e_dev_get_dcb_info,
515 .timesync_adjust_time = i40e_timesync_adjust_time,
516 .timesync_read_time = i40e_timesync_read_time,
517 .timesync_write_time = i40e_timesync_write_time,
518 .get_reg_length = i40e_get_reg_length,
519 .get_reg = i40e_get_regs,
520 .get_eeprom_length = i40e_get_eeprom_length,
521 .get_eeprom = i40e_get_eeprom,
522 .mac_addr_set = i40e_set_default_mac_addr,
525 /* store statistics names and its offset in stats structure */
526 struct rte_i40e_xstats_name_off {
527 char name[RTE_ETH_XSTATS_NAME_SIZE];
531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
532 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
533 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
534 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
535 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
536 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
537 rx_unknown_protocol)},
538 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
539 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
540 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
541 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
545 sizeof(rte_i40e_stats_strings[0]))
547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
548 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
549 tx_dropped_link_down)},
550 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
551 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
554 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
556 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
560 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
561 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
562 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
563 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
564 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
565 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
581 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
582 mac_short_packet_dropped)},
583 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
586 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
587 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
599 {"rx_flow_director_atr_match_packets",
600 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
601 {"rx_flow_director_sb_match_packets",
602 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
603 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
605 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
607 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
614 sizeof(rte_i40e_hw_port_strings[0]))
616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
617 {"xon_packets", offsetof(struct i40e_hw_port_stats,
619 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
624 sizeof(rte_i40e_rxq_prio_strings[0]))
626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
627 {"xon_packets", offsetof(struct i40e_hw_port_stats,
629 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
631 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
632 priority_xon_2_xoff)},
635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
636 sizeof(rte_i40e_txq_prio_strings[0]))
638 static struct eth_driver rte_i40e_pmd = {
640 .name = "rte_i40e_pmd",
641 .id_table = pci_id_i40e_map,
642 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
643 RTE_PCI_DRV_DETACHABLE,
645 .eth_dev_init = eth_i40e_dev_init,
646 .eth_dev_uninit = eth_i40e_dev_uninit,
647 .dev_private_size = sizeof(struct i40e_adapter),
651 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
652 struct rte_eth_link *link)
654 struct rte_eth_link *dst = link;
655 struct rte_eth_link *src = &(dev->data->dev_link);
657 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
658 *(uint64_t *)src) == 0)
665 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
666 struct rte_eth_link *link)
668 struct rte_eth_link *dst = &(dev->data->dev_link);
669 struct rte_eth_link *src = link;
671 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
672 *(uint64_t *)src) == 0)
679 * Driver initialization routine.
680 * Invoked once at EAL init time.
681 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
684 rte_i40e_pmd_init(const char *name __rte_unused,
685 const char *params __rte_unused)
687 PMD_INIT_FUNC_TRACE();
688 rte_eth_driver_register(&rte_i40e_pmd);
693 static struct rte_driver rte_i40e_driver = {
695 .init = rte_i40e_pmd_init,
698 PMD_REGISTER_DRIVER(rte_i40e_driver);
701 * Initialize registers for flexible payload, which should be set by NVM.
702 * This should be removed from code once it is fixed in NVM.
704 #ifndef I40E_GLQF_ORT
705 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
707 #ifndef I40E_GLQF_PIT
708 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
711 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
724 /* GLQF_PIT Registers */
725 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
726 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
729 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
732 * Add a ethertype filter to drop all flow control frames transmitted
736 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
739 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
740 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
741 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
744 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
745 I40E_FLOW_CONTROL_ETHERTYPE, flags,
746 pf->main_vsi_seid, 0,
749 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
750 " frames from VSIs.");
754 eth_i40e_dev_init(struct rte_eth_dev *dev)
756 struct rte_pci_device *pci_dev;
757 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
759 struct i40e_vsi *vsi;
764 PMD_INIT_FUNC_TRACE();
766 dev->dev_ops = &i40e_eth_dev_ops;
767 dev->rx_pkt_burst = i40e_recv_pkts;
768 dev->tx_pkt_burst = i40e_xmit_pkts;
770 /* for secondary processes, we don't initialise any further as primary
771 * has already done this work. Only check we don't need a different
773 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
774 i40e_set_rx_function(dev);
775 i40e_set_tx_function(dev);
778 pci_dev = dev->pci_dev;
780 rte_eth_copy_pci_info(dev, pci_dev);
782 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
783 pf->adapter->eth_dev = dev;
784 pf->dev_data = dev->data;
786 hw->back = I40E_PF_TO_ADAPTER(pf);
787 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
789 PMD_INIT_LOG(ERR, "Hardware is not available, "
790 "as address is NULL");
794 hw->vendor_id = pci_dev->id.vendor_id;
795 hw->device_id = pci_dev->id.device_id;
796 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
797 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
798 hw->bus.device = pci_dev->addr.devid;
799 hw->bus.func = pci_dev->addr.function;
800 hw->adapter_stopped = 0;
802 /* Make sure all is clean before doing PF reset */
805 /* Initialize the hardware */
808 /* Reset here to make sure all is clean for each PF */
809 ret = i40e_pf_reset(hw);
811 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
815 /* Initialize the shared code (base driver) */
816 ret = i40e_init_shared_code(hw);
818 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
823 * To work around the NVM issue,initialize registers
824 * for flexible payload by software.
825 * It should be removed once issues are fixed in NVM.
827 i40e_flex_payload_reg_init(hw);
829 /* Initialize the input set for filters (hash and fd) to default value */
830 i40e_filter_input_set_init(pf);
832 /* Initialize the parameters for adminq */
833 i40e_init_adminq_parameter(hw);
834 ret = i40e_init_adminq(hw);
835 if (ret != I40E_SUCCESS) {
836 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
839 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
840 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
841 hw->aq.api_maj_ver, hw->aq.api_min_ver,
842 ((hw->nvm.version >> 12) & 0xf),
843 ((hw->nvm.version >> 4) & 0xff),
844 (hw->nvm.version & 0xf), hw->nvm.eetrack);
847 i40e_clear_pxe_mode(hw);
850 * On X710, performance number is far from the expectation on recent
851 * firmware versions. The fix for this issue may not be integrated in
852 * the following firmware version. So the workaround in software driver
853 * is needed. It needs to modify the initial values of 3 internal only
854 * registers. Note that the workaround can be removed when it is fixed
855 * in firmware in the future.
857 i40e_configure_registers(hw);
859 /* Get hw capabilities */
860 ret = i40e_get_cap(hw);
861 if (ret != I40E_SUCCESS) {
862 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
863 goto err_get_capabilities;
866 /* Initialize parameters for PF */
867 ret = i40e_pf_parameter_init(dev);
869 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
870 goto err_parameter_init;
873 /* Initialize the queue management */
874 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
876 PMD_INIT_LOG(ERR, "Failed to init queue pool");
877 goto err_qp_pool_init;
879 ret = i40e_res_pool_init(&pf->msix_pool, 1,
880 hw->func_caps.num_msix_vectors - 1);
882 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
883 goto err_msix_pool_init;
886 /* Initialize lan hmc */
887 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
888 hw->func_caps.num_rx_qp, 0, 0);
889 if (ret != I40E_SUCCESS) {
890 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
891 goto err_init_lan_hmc;
894 /* Configure lan hmc */
895 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
896 if (ret != I40E_SUCCESS) {
897 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
898 goto err_configure_lan_hmc;
901 /* Get and check the mac address */
902 i40e_get_mac_addr(hw, hw->mac.addr);
903 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
904 PMD_INIT_LOG(ERR, "mac address is not valid");
906 goto err_get_mac_addr;
908 /* Copy the permanent MAC address */
909 ether_addr_copy((struct ether_addr *) hw->mac.addr,
910 (struct ether_addr *) hw->mac.perm_addr);
912 /* Disable flow control */
913 hw->fc.requested_mode = I40E_FC_NONE;
914 i40e_set_fc(hw, &aq_fail, TRUE);
916 /* Set the global registers with default ether type value */
917 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
918 if (ret != I40E_SUCCESS) {
919 PMD_INIT_LOG(ERR, "Failed to set the default outer "
921 goto err_setup_pf_switch;
923 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
924 if (ret != I40E_SUCCESS) {
925 PMD_INIT_LOG(ERR, "Failed to set the default outer "
927 goto err_setup_pf_switch;
930 /* PF setup, which includes VSI setup */
931 ret = i40e_pf_setup(pf);
933 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
934 goto err_setup_pf_switch;
937 /* reset all stats of the device, including pf and main vsi */
938 i40e_dev_stats_reset(dev);
942 /* Disable double vlan by default */
943 i40e_vsi_config_double_vlan(vsi, FALSE);
945 if (!vsi->max_macaddrs)
946 len = ETHER_ADDR_LEN;
948 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
950 /* Should be after VSI initialized */
951 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
952 if (!dev->data->mac_addrs) {
953 PMD_INIT_LOG(ERR, "Failed to allocated memory "
954 "for storing mac address");
957 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
958 &dev->data->mac_addrs[0]);
960 /* initialize pf host driver to setup SRIOV resource if applicable */
961 i40e_pf_host_init(dev);
963 /* register callback func to eal lib */
964 rte_intr_callback_register(&(pci_dev->intr_handle),
965 i40e_dev_interrupt_handler, (void *)dev);
967 /* configure and enable device interrupt */
968 i40e_pf_config_irq0(hw, TRUE);
969 i40e_pf_enable_irq0(hw);
971 /* enable uio intr after callback register */
972 rte_intr_enable(&(pci_dev->intr_handle));
974 * Add an ethertype filter to drop all flow control frames transmitted
975 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
978 i40e_add_tx_flow_control_drop_filter(pf);
980 /* Set the max frame size to 0x2600 by default,
981 * in case other drivers changed the default value.
983 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
985 /* initialize mirror rule list */
986 TAILQ_INIT(&pf->mirror_list);
988 /* Init dcb to sw mode by default */
989 ret = i40e_dcb_init_configure(dev, TRUE);
990 if (ret != I40E_SUCCESS) {
991 PMD_INIT_LOG(INFO, "Failed to init dcb.");
992 pf->flags &= ~I40E_FLAG_DCB;
998 i40e_vsi_release(pf->main_vsi);
1001 err_configure_lan_hmc:
1002 (void)i40e_shutdown_lan_hmc(hw);
1004 i40e_res_pool_destroy(&pf->msix_pool);
1006 i40e_res_pool_destroy(&pf->qp_pool);
1009 err_get_capabilities:
1010 (void)i40e_shutdown_adminq(hw);
1016 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1018 struct rte_pci_device *pci_dev;
1020 struct i40e_filter_control_settings settings;
1022 uint8_t aq_fail = 0;
1024 PMD_INIT_FUNC_TRACE();
1026 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1029 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 pci_dev = dev->pci_dev;
1032 if (hw->adapter_stopped == 0)
1033 i40e_dev_close(dev);
1035 dev->dev_ops = NULL;
1036 dev->rx_pkt_burst = NULL;
1037 dev->tx_pkt_burst = NULL;
1040 ret = i40e_aq_stop_lldp(hw, true, NULL);
1041 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1042 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1044 /* Clear PXE mode */
1045 i40e_clear_pxe_mode(hw);
1047 /* Unconfigure filter control */
1048 memset(&settings, 0, sizeof(settings));
1049 ret = i40e_set_filter_control(hw, &settings);
1051 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1054 /* Disable flow control */
1055 hw->fc.requested_mode = I40E_FC_NONE;
1056 i40e_set_fc(hw, &aq_fail, TRUE);
1058 /* uninitialize pf host driver */
1059 i40e_pf_host_uninit(dev);
1061 rte_free(dev->data->mac_addrs);
1062 dev->data->mac_addrs = NULL;
1064 /* disable uio intr before callback unregister */
1065 rte_intr_disable(&(pci_dev->intr_handle));
1067 /* register callback func to eal lib */
1068 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1069 i40e_dev_interrupt_handler, (void *)dev);
1075 i40e_dev_configure(struct rte_eth_dev *dev)
1077 struct i40e_adapter *ad =
1078 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1080 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1083 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1084 * bulk allocation or vector Rx preconditions we will reset it.
1086 ad->rx_bulk_alloc_allowed = true;
1087 ad->rx_vec_allowed = true;
1088 ad->tx_simple_allowed = true;
1089 ad->tx_vec_allowed = true;
1091 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1092 ret = i40e_fdir_setup(pf);
1093 if (ret != I40E_SUCCESS) {
1094 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1097 ret = i40e_fdir_configure(dev);
1099 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1103 i40e_fdir_teardown(pf);
1105 ret = i40e_dev_init_vlan(dev);
1110 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1111 * RSS setting have different requirements.
1112 * General PMD driver call sequence are NIC init, configure,
1113 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1114 * will try to lookup the VSI that specific queue belongs to if VMDQ
1115 * applicable. So, VMDQ setting has to be done before
1116 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1117 * For RSS setting, it will try to calculate actual configured RX queue
1118 * number, which will be available after rx_queue_setup(). dev_start()
1119 * function is good to place RSS setup.
1121 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1122 ret = i40e_vmdq_setup(dev);
1127 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1128 ret = i40e_dcb_setup(dev);
1130 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1138 /* need to release vmdq resource if exists */
1139 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1140 i40e_vsi_release(pf->vmdq[i].vsi);
1141 pf->vmdq[i].vsi = NULL;
1146 /* need to release fdir resource if exists */
1147 i40e_fdir_teardown(pf);
1152 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1154 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1155 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1156 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1157 uint16_t msix_vect = vsi->msix_intr;
1160 for (i = 0; i < vsi->nb_qps; i++) {
1161 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1162 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1166 if (vsi->type != I40E_VSI_SRIOV) {
1167 if (!rte_intr_allow_others(intr_handle)) {
1168 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1169 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1171 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1174 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1175 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1177 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1182 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1183 vsi->user_param + (msix_vect - 1);
1185 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1186 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1188 I40E_WRITE_FLUSH(hw);
1192 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1193 int base_queue, int nb_queue)
1197 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1199 /* Bind all RX queues to allocated MSIX interrupt */
1200 for (i = 0; i < nb_queue; i++) {
1201 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1202 I40E_QINT_RQCTL_ITR_INDX_MASK |
1203 ((base_queue + i + 1) <<
1204 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1205 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1206 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1208 if (i == nb_queue - 1)
1209 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1210 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1213 /* Write first RX queue to Link list register as the head element */
1214 if (vsi->type != I40E_VSI_SRIOV) {
1216 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1218 if (msix_vect == I40E_MISC_VEC_ID) {
1219 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1221 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1223 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1225 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1228 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1230 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1232 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1234 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1241 if (msix_vect == I40E_MISC_VEC_ID) {
1243 I40E_VPINT_LNKLST0(vsi->user_param),
1245 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1247 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1249 /* num_msix_vectors_vf needs to minus irq0 */
1250 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1251 vsi->user_param + (msix_vect - 1);
1253 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1255 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1257 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1261 I40E_WRITE_FLUSH(hw);
1265 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1267 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1268 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1269 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1270 uint16_t msix_vect = vsi->msix_intr;
1271 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1272 uint16_t queue_idx = 0;
1277 for (i = 0; i < vsi->nb_qps; i++) {
1278 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1279 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1282 /* INTENA flag is not auto-cleared for interrupt */
1283 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1284 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1285 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1286 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1287 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1289 /* VF bind interrupt */
1290 if (vsi->type == I40E_VSI_SRIOV) {
1291 __vsi_queues_bind_intr(vsi, msix_vect,
1292 vsi->base_queue, vsi->nb_qps);
1296 /* PF & VMDq bind interrupt */
1297 if (rte_intr_dp_is_en(intr_handle)) {
1298 if (vsi->type == I40E_VSI_MAIN) {
1301 } else if (vsi->type == I40E_VSI_VMDQ2) {
1302 struct i40e_vsi *main_vsi =
1303 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1304 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1309 for (i = 0; i < vsi->nb_used_qps; i++) {
1311 if (!rte_intr_allow_others(intr_handle))
1312 /* allow to share MISC_VEC_ID */
1313 msix_vect = I40E_MISC_VEC_ID;
1315 /* no enough msix_vect, map all to one */
1316 __vsi_queues_bind_intr(vsi, msix_vect,
1317 vsi->base_queue + i,
1318 vsi->nb_used_qps - i);
1319 for (; !!record && i < vsi->nb_used_qps; i++)
1320 intr_handle->intr_vec[queue_idx + i] =
1324 /* 1:1 queue/msix_vect mapping */
1325 __vsi_queues_bind_intr(vsi, msix_vect,
1326 vsi->base_queue + i, 1);
1328 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1336 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1338 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1339 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1340 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1341 uint16_t interval = i40e_calc_itr_interval(\
1342 RTE_LIBRTE_I40E_ITR_INTERVAL);
1343 uint16_t msix_intr, i;
1345 if (rte_intr_allow_others(intr_handle))
1346 for (i = 0; i < vsi->nb_msix; i++) {
1347 msix_intr = vsi->msix_intr + i;
1348 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1349 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1350 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1351 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1353 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1356 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1357 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1358 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1359 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1361 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1363 I40E_WRITE_FLUSH(hw);
1367 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1369 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1370 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1371 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1372 uint16_t msix_intr, i;
1374 if (rte_intr_allow_others(intr_handle))
1375 for (i = 0; i < vsi->nb_msix; i++) {
1376 msix_intr = vsi->msix_intr + i;
1377 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1381 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1383 I40E_WRITE_FLUSH(hw);
1386 static inline uint8_t
1387 i40e_parse_link_speeds(uint16_t link_speeds)
1389 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1391 if (link_speeds & ETH_LINK_SPEED_40G)
1392 link_speed |= I40E_LINK_SPEED_40GB;
1393 if (link_speeds & ETH_LINK_SPEED_20G)
1394 link_speed |= I40E_LINK_SPEED_20GB;
1395 if (link_speeds & ETH_LINK_SPEED_10G)
1396 link_speed |= I40E_LINK_SPEED_10GB;
1397 if (link_speeds & ETH_LINK_SPEED_1G)
1398 link_speed |= I40E_LINK_SPEED_1GB;
1399 if (link_speeds & ETH_LINK_SPEED_100M)
1400 link_speed |= I40E_LINK_SPEED_100MB;
1406 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1407 __rte_unused uint8_t abilities,
1408 __rte_unused uint8_t force_speed)
1410 /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1411 * for the link control limitation of that all link control should be
1412 * handled by firmware. It should follow up if link control will be
1413 * opened to software driver in future firmware versions.
1415 return I40E_SUCCESS;
1419 i40e_apply_link_speed(struct rte_eth_dev *dev)
1422 uint8_t abilities = 0;
1423 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1424 struct rte_eth_conf *conf = &dev->data->dev_conf;
1426 speed = i40e_parse_link_speeds(conf->link_speeds);
1427 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1428 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1429 abilities |= I40E_AQ_PHY_AN_ENABLED;
1431 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1433 return i40e_phy_conf_link(hw, abilities, speed);
1437 i40e_dev_start(struct rte_eth_dev *dev)
1439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441 struct i40e_vsi *main_vsi = pf->main_vsi;
1443 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1444 uint32_t intr_vector = 0;
1446 hw->adapter_stopped = 0;
1448 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1449 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1450 dev->data->port_id);
1454 rte_intr_disable(intr_handle);
1456 if ((rte_intr_cap_multiple(intr_handle) ||
1457 !RTE_ETH_DEV_SRIOV(dev).active) &&
1458 dev->data->dev_conf.intr_conf.rxq != 0) {
1459 intr_vector = dev->data->nb_rx_queues;
1460 if (rte_intr_efd_enable(intr_handle, intr_vector))
1464 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1465 intr_handle->intr_vec =
1466 rte_zmalloc("intr_vec",
1467 dev->data->nb_rx_queues * sizeof(int),
1469 if (!intr_handle->intr_vec) {
1470 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1471 " intr_vec\n", dev->data->nb_rx_queues);
1476 /* Initialize VSI */
1477 ret = i40e_dev_rxtx_init(pf);
1478 if (ret != I40E_SUCCESS) {
1479 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1483 /* Map queues with MSIX interrupt */
1484 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1485 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1486 i40e_vsi_queues_bind_intr(main_vsi);
1487 i40e_vsi_enable_queues_intr(main_vsi);
1489 /* Map VMDQ VSI queues with MSIX interrupt */
1490 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1491 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1492 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1493 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1496 /* enable FDIR MSIX interrupt */
1497 if (pf->fdir.fdir_vsi) {
1498 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1499 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1502 /* Enable all queues which have been configured */
1503 ret = i40e_dev_switch_queues(pf, TRUE);
1504 if (ret != I40E_SUCCESS) {
1505 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1509 /* Enable receiving broadcast packets */
1510 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1511 if (ret != I40E_SUCCESS)
1512 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1514 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1515 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1517 if (ret != I40E_SUCCESS)
1518 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1521 /* Apply link configure */
1522 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1523 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1524 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1525 PMD_DRV_LOG(ERR, "Invalid link setting");
1528 ret = i40e_apply_link_speed(dev);
1529 if (I40E_SUCCESS != ret) {
1530 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1534 if (!rte_intr_allow_others(intr_handle)) {
1535 rte_intr_callback_unregister(intr_handle,
1536 i40e_dev_interrupt_handler,
1538 /* configure and enable device interrupt */
1539 i40e_pf_config_irq0(hw, FALSE);
1540 i40e_pf_enable_irq0(hw);
1542 if (dev->data->dev_conf.intr_conf.lsc != 0)
1543 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1544 " no intr multiplex\n");
1547 /* enable uio intr after callback register */
1548 rte_intr_enable(intr_handle);
1550 return I40E_SUCCESS;
1553 i40e_dev_switch_queues(pf, FALSE);
1554 i40e_dev_clear_queues(dev);
1560 i40e_dev_stop(struct rte_eth_dev *dev)
1562 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1563 struct i40e_vsi *main_vsi = pf->main_vsi;
1564 struct i40e_mirror_rule *p_mirror;
1565 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1568 /* Disable all queues */
1569 i40e_dev_switch_queues(pf, FALSE);
1571 /* un-map queues with interrupt registers */
1572 i40e_vsi_disable_queues_intr(main_vsi);
1573 i40e_vsi_queues_unbind_intr(main_vsi);
1575 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1576 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1577 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1580 if (pf->fdir.fdir_vsi) {
1581 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1582 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1584 /* Clear all queues and release memory */
1585 i40e_dev_clear_queues(dev);
1588 i40e_dev_set_link_down(dev);
1590 /* Remove all mirror rules */
1591 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1592 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1595 pf->nb_mirror_rule = 0;
1597 if (!rte_intr_allow_others(intr_handle))
1598 /* resume to the default handler */
1599 rte_intr_callback_register(intr_handle,
1600 i40e_dev_interrupt_handler,
1603 /* Clean datapath event and queue/vec mapping */
1604 rte_intr_efd_disable(intr_handle);
1605 if (intr_handle->intr_vec) {
1606 rte_free(intr_handle->intr_vec);
1607 intr_handle->intr_vec = NULL;
1612 i40e_dev_close(struct rte_eth_dev *dev)
1614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619 PMD_INIT_FUNC_TRACE();
1622 hw->adapter_stopped = 1;
1623 i40e_dev_free_queues(dev);
1625 /* Disable interrupt */
1626 i40e_pf_disable_irq0(hw);
1627 rte_intr_disable(&(dev->pci_dev->intr_handle));
1629 /* shutdown and destroy the HMC */
1630 i40e_shutdown_lan_hmc(hw);
1632 /* release all the existing VSIs and VEBs */
1633 i40e_fdir_teardown(pf);
1634 i40e_vsi_release(pf->main_vsi);
1636 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1637 i40e_vsi_release(pf->vmdq[i].vsi);
1638 pf->vmdq[i].vsi = NULL;
1644 /* shutdown the adminq */
1645 i40e_aq_queue_shutdown(hw, true);
1646 i40e_shutdown_adminq(hw);
1648 i40e_res_pool_destroy(&pf->qp_pool);
1649 i40e_res_pool_destroy(&pf->msix_pool);
1651 /* force a PF reset to clean anything leftover */
1652 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1653 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1654 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1655 I40E_WRITE_FLUSH(hw);
1659 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1661 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 struct i40e_vsi *vsi = pf->main_vsi;
1666 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1668 if (status != I40E_SUCCESS)
1669 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1671 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1673 if (status != I40E_SUCCESS)
1674 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1679 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1681 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683 struct i40e_vsi *vsi = pf->main_vsi;
1686 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1688 if (status != I40E_SUCCESS)
1689 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1691 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1693 if (status != I40E_SUCCESS)
1694 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1698 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1700 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1701 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702 struct i40e_vsi *vsi = pf->main_vsi;
1705 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1706 if (ret != I40E_SUCCESS)
1707 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1711 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1713 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715 struct i40e_vsi *vsi = pf->main_vsi;
1718 if (dev->data->promiscuous == 1)
1719 return; /* must remain in all_multicast mode */
1721 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1722 vsi->seid, FALSE, NULL);
1723 if (ret != I40E_SUCCESS)
1724 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1728 * Set device link up.
1731 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1733 /* re-apply link speed setting */
1734 return i40e_apply_link_speed(dev);
1738 * Set device link down.
1741 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1743 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1744 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747 return i40e_phy_conf_link(hw, abilities, speed);
1751 i40e_dev_link_update(struct rte_eth_dev *dev,
1752 int wait_to_complete)
1754 #define CHECK_INTERVAL 100 /* 100ms */
1755 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757 struct i40e_link_status link_status;
1758 struct rte_eth_link link, old;
1760 unsigned rep_cnt = MAX_REPEAT_TIME;
1762 memset(&link, 0, sizeof(link));
1763 memset(&old, 0, sizeof(old));
1764 memset(&link_status, 0, sizeof(link_status));
1765 rte_i40e_dev_atomic_read_link_status(dev, &old);
1768 /* Get link status information from hardware */
1769 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1770 if (status != I40E_SUCCESS) {
1771 link.link_speed = ETH_SPEED_NUM_100M;
1772 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1773 PMD_DRV_LOG(ERR, "Failed to get link info");
1777 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1778 if (!wait_to_complete)
1781 rte_delay_ms(CHECK_INTERVAL);
1782 } while (!link.link_status && rep_cnt--);
1784 if (!link.link_status)
1787 /* i40e uses full duplex only */
1788 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1790 /* Parse the link status */
1791 switch (link_status.link_speed) {
1792 case I40E_LINK_SPEED_100MB:
1793 link.link_speed = ETH_SPEED_NUM_100M;
1795 case I40E_LINK_SPEED_1GB:
1796 link.link_speed = ETH_SPEED_NUM_1G;
1798 case I40E_LINK_SPEED_10GB:
1799 link.link_speed = ETH_SPEED_NUM_10G;
1801 case I40E_LINK_SPEED_20GB:
1802 link.link_speed = ETH_SPEED_NUM_20G;
1804 case I40E_LINK_SPEED_40GB:
1805 link.link_speed = ETH_SPEED_NUM_40G;
1808 link.link_speed = ETH_SPEED_NUM_100M;
1812 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1813 ETH_LINK_SPEED_FIXED);
1816 rte_i40e_dev_atomic_write_link_status(dev, &link);
1817 if (link.link_status == old.link_status)
1823 /* Get all the statistics of a VSI */
1825 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1827 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1828 struct i40e_eth_stats *nes = &vsi->eth_stats;
1829 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1830 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1832 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1833 vsi->offset_loaded, &oes->rx_bytes,
1835 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1836 vsi->offset_loaded, &oes->rx_unicast,
1838 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1839 vsi->offset_loaded, &oes->rx_multicast,
1840 &nes->rx_multicast);
1841 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1842 vsi->offset_loaded, &oes->rx_broadcast,
1843 &nes->rx_broadcast);
1844 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1845 &oes->rx_discards, &nes->rx_discards);
1846 /* GLV_REPC not supported */
1847 /* GLV_RMPC not supported */
1848 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1849 &oes->rx_unknown_protocol,
1850 &nes->rx_unknown_protocol);
1851 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1852 vsi->offset_loaded, &oes->tx_bytes,
1854 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1855 vsi->offset_loaded, &oes->tx_unicast,
1857 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1858 vsi->offset_loaded, &oes->tx_multicast,
1859 &nes->tx_multicast);
1860 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1861 vsi->offset_loaded, &oes->tx_broadcast,
1862 &nes->tx_broadcast);
1863 /* GLV_TDPC not supported */
1864 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1865 &oes->tx_errors, &nes->tx_errors);
1866 vsi->offset_loaded = true;
1868 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1870 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1871 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1872 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1873 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1874 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1875 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1876 nes->rx_unknown_protocol);
1877 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1878 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1879 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1880 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1881 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1882 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1883 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1888 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1891 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1892 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1894 /* Get statistics of struct i40e_eth_stats */
1895 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1896 I40E_GLPRT_GORCL(hw->port),
1897 pf->offset_loaded, &os->eth.rx_bytes,
1899 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1900 I40E_GLPRT_UPRCL(hw->port),
1901 pf->offset_loaded, &os->eth.rx_unicast,
1902 &ns->eth.rx_unicast);
1903 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1904 I40E_GLPRT_MPRCL(hw->port),
1905 pf->offset_loaded, &os->eth.rx_multicast,
1906 &ns->eth.rx_multicast);
1907 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1908 I40E_GLPRT_BPRCL(hw->port),
1909 pf->offset_loaded, &os->eth.rx_broadcast,
1910 &ns->eth.rx_broadcast);
1911 /* Workaround: CRC size should not be included in byte statistics,
1912 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1914 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1915 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1917 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1918 pf->offset_loaded, &os->eth.rx_discards,
1919 &ns->eth.rx_discards);
1920 /* GLPRT_REPC not supported */
1921 /* GLPRT_RMPC not supported */
1922 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1924 &os->eth.rx_unknown_protocol,
1925 &ns->eth.rx_unknown_protocol);
1926 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1927 I40E_GLPRT_GOTCL(hw->port),
1928 pf->offset_loaded, &os->eth.tx_bytes,
1930 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1931 I40E_GLPRT_UPTCL(hw->port),
1932 pf->offset_loaded, &os->eth.tx_unicast,
1933 &ns->eth.tx_unicast);
1934 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1935 I40E_GLPRT_MPTCL(hw->port),
1936 pf->offset_loaded, &os->eth.tx_multicast,
1937 &ns->eth.tx_multicast);
1938 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1939 I40E_GLPRT_BPTCL(hw->port),
1940 pf->offset_loaded, &os->eth.tx_broadcast,
1941 &ns->eth.tx_broadcast);
1942 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1943 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1944 /* GLPRT_TEPC not supported */
1946 /* additional port specific stats */
1947 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1948 pf->offset_loaded, &os->tx_dropped_link_down,
1949 &ns->tx_dropped_link_down);
1950 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1951 pf->offset_loaded, &os->crc_errors,
1953 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1954 pf->offset_loaded, &os->illegal_bytes,
1955 &ns->illegal_bytes);
1956 /* GLPRT_ERRBC not supported */
1957 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1958 pf->offset_loaded, &os->mac_local_faults,
1959 &ns->mac_local_faults);
1960 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1961 pf->offset_loaded, &os->mac_remote_faults,
1962 &ns->mac_remote_faults);
1963 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1964 pf->offset_loaded, &os->rx_length_errors,
1965 &ns->rx_length_errors);
1966 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1967 pf->offset_loaded, &os->link_xon_rx,
1969 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1970 pf->offset_loaded, &os->link_xoff_rx,
1972 for (i = 0; i < 8; i++) {
1973 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1975 &os->priority_xon_rx[i],
1976 &ns->priority_xon_rx[i]);
1977 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1979 &os->priority_xoff_rx[i],
1980 &ns->priority_xoff_rx[i]);
1982 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1983 pf->offset_loaded, &os->link_xon_tx,
1985 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1986 pf->offset_loaded, &os->link_xoff_tx,
1988 for (i = 0; i < 8; i++) {
1989 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1991 &os->priority_xon_tx[i],
1992 &ns->priority_xon_tx[i]);
1993 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1995 &os->priority_xoff_tx[i],
1996 &ns->priority_xoff_tx[i]);
1997 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1999 &os->priority_xon_2_xoff[i],
2000 &ns->priority_xon_2_xoff[i]);
2002 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2003 I40E_GLPRT_PRC64L(hw->port),
2004 pf->offset_loaded, &os->rx_size_64,
2006 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2007 I40E_GLPRT_PRC127L(hw->port),
2008 pf->offset_loaded, &os->rx_size_127,
2010 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2011 I40E_GLPRT_PRC255L(hw->port),
2012 pf->offset_loaded, &os->rx_size_255,
2014 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2015 I40E_GLPRT_PRC511L(hw->port),
2016 pf->offset_loaded, &os->rx_size_511,
2018 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2019 I40E_GLPRT_PRC1023L(hw->port),
2020 pf->offset_loaded, &os->rx_size_1023,
2022 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2023 I40E_GLPRT_PRC1522L(hw->port),
2024 pf->offset_loaded, &os->rx_size_1522,
2026 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2027 I40E_GLPRT_PRC9522L(hw->port),
2028 pf->offset_loaded, &os->rx_size_big,
2030 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2031 pf->offset_loaded, &os->rx_undersize,
2033 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2034 pf->offset_loaded, &os->rx_fragments,
2036 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2037 pf->offset_loaded, &os->rx_oversize,
2039 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2040 pf->offset_loaded, &os->rx_jabber,
2042 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2043 I40E_GLPRT_PTC64L(hw->port),
2044 pf->offset_loaded, &os->tx_size_64,
2046 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2047 I40E_GLPRT_PTC127L(hw->port),
2048 pf->offset_loaded, &os->tx_size_127,
2050 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2051 I40E_GLPRT_PTC255L(hw->port),
2052 pf->offset_loaded, &os->tx_size_255,
2054 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2055 I40E_GLPRT_PTC511L(hw->port),
2056 pf->offset_loaded, &os->tx_size_511,
2058 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2059 I40E_GLPRT_PTC1023L(hw->port),
2060 pf->offset_loaded, &os->tx_size_1023,
2062 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2063 I40E_GLPRT_PTC1522L(hw->port),
2064 pf->offset_loaded, &os->tx_size_1522,
2066 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2067 I40E_GLPRT_PTC9522L(hw->port),
2068 pf->offset_loaded, &os->tx_size_big,
2070 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2072 &os->fd_sb_match, &ns->fd_sb_match);
2073 /* GLPRT_MSPDC not supported */
2074 /* GLPRT_XEC not supported */
2076 pf->offset_loaded = true;
2079 i40e_update_vsi_stats(pf->main_vsi);
2082 /* Get all statistics of a port */
2084 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2086 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2087 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2091 /* call read registers - updates values, now write them to struct */
2092 i40e_read_stats_registers(pf, hw);
2094 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2095 pf->main_vsi->eth_stats.rx_multicast +
2096 pf->main_vsi->eth_stats.rx_broadcast -
2097 pf->main_vsi->eth_stats.rx_discards;
2098 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2099 pf->main_vsi->eth_stats.tx_multicast +
2100 pf->main_vsi->eth_stats.tx_broadcast;
2101 stats->ibytes = ns->eth.rx_bytes;
2102 stats->obytes = ns->eth.tx_bytes;
2103 stats->oerrors = ns->eth.tx_errors +
2104 pf->main_vsi->eth_stats.tx_errors;
2107 stats->imissed = ns->eth.rx_discards +
2108 pf->main_vsi->eth_stats.rx_discards;
2109 stats->ierrors = ns->crc_errors +
2110 ns->rx_length_errors + ns->rx_undersize +
2111 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2113 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2114 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2115 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2116 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2117 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2118 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2119 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2120 ns->eth.rx_unknown_protocol);
2121 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2122 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2123 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2124 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2125 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2126 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2128 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2129 ns->tx_dropped_link_down);
2130 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2131 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2133 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2134 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2135 ns->mac_local_faults);
2136 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2137 ns->mac_remote_faults);
2138 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2139 ns->rx_length_errors);
2140 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2141 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2142 for (i = 0; i < 8; i++) {
2143 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2144 i, ns->priority_xon_rx[i]);
2145 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2146 i, ns->priority_xoff_rx[i]);
2148 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2149 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2150 for (i = 0; i < 8; i++) {
2151 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2152 i, ns->priority_xon_tx[i]);
2153 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2154 i, ns->priority_xoff_tx[i]);
2155 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2156 i, ns->priority_xon_2_xoff[i]);
2158 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2159 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2160 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2161 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2162 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2163 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2164 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2165 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2166 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2167 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2168 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2169 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2170 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2171 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2172 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2173 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2174 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2175 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2176 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2177 ns->mac_short_packet_dropped);
2178 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2179 ns->checksum_error);
2180 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2181 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2184 /* Reset the statistics */
2186 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2188 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2189 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2191 /* Mark PF and VSI stats to update the offset, aka "reset" */
2192 pf->offset_loaded = false;
2194 pf->main_vsi->offset_loaded = false;
2196 /* read the stats, reading current register values into offset */
2197 i40e_read_stats_registers(pf, hw);
2201 i40e_xstats_calc_num(void)
2203 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2204 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2205 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2209 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2212 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2213 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214 unsigned i, count, prio;
2215 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2217 count = i40e_xstats_calc_num();
2221 i40e_read_stats_registers(pf, hw);
2228 /* Get stats from i40e_eth_stats struct */
2229 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2230 snprintf(xstats[count].name, sizeof(xstats[count].name),
2231 "%s", rte_i40e_stats_strings[i].name);
2232 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2233 rte_i40e_stats_strings[i].offset);
2237 /* Get individiual stats from i40e_hw_port struct */
2238 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2239 snprintf(xstats[count].name, sizeof(xstats[count].name),
2240 "%s", rte_i40e_hw_port_strings[i].name);
2241 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2242 rte_i40e_hw_port_strings[i].offset);
2246 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2247 for (prio = 0; prio < 8; prio++) {
2248 snprintf(xstats[count].name,
2249 sizeof(xstats[count].name),
2250 "rx_priority%u_%s", prio,
2251 rte_i40e_rxq_prio_strings[i].name);
2252 xstats[count].value =
2253 *(uint64_t *)(((char *)hw_stats) +
2254 rte_i40e_rxq_prio_strings[i].offset +
2255 (sizeof(uint64_t) * prio));
2260 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2261 for (prio = 0; prio < 8; prio++) {
2262 snprintf(xstats[count].name,
2263 sizeof(xstats[count].name),
2264 "tx_priority%u_%s", prio,
2265 rte_i40e_txq_prio_strings[i].name);
2266 xstats[count].value =
2267 *(uint64_t *)(((char *)hw_stats) +
2268 rte_i40e_txq_prio_strings[i].offset +
2269 (sizeof(uint64_t) * prio));
2278 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2279 __rte_unused uint16_t queue_id,
2280 __rte_unused uint8_t stat_idx,
2281 __rte_unused uint8_t is_rx)
2283 PMD_INIT_FUNC_TRACE();
2289 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2291 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2292 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293 struct i40e_vsi *vsi = pf->main_vsi;
2295 dev_info->max_rx_queues = vsi->nb_qps;
2296 dev_info->max_tx_queues = vsi->nb_qps;
2297 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2298 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2299 dev_info->max_mac_addrs = vsi->max_macaddrs;
2300 dev_info->max_vfs = dev->pci_dev->max_vfs;
2301 dev_info->rx_offload_capa =
2302 DEV_RX_OFFLOAD_VLAN_STRIP |
2303 DEV_RX_OFFLOAD_QINQ_STRIP |
2304 DEV_RX_OFFLOAD_IPV4_CKSUM |
2305 DEV_RX_OFFLOAD_UDP_CKSUM |
2306 DEV_RX_OFFLOAD_TCP_CKSUM;
2307 dev_info->tx_offload_capa =
2308 DEV_TX_OFFLOAD_VLAN_INSERT |
2309 DEV_TX_OFFLOAD_QINQ_INSERT |
2310 DEV_TX_OFFLOAD_IPV4_CKSUM |
2311 DEV_TX_OFFLOAD_UDP_CKSUM |
2312 DEV_TX_OFFLOAD_TCP_CKSUM |
2313 DEV_TX_OFFLOAD_SCTP_CKSUM |
2314 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2315 DEV_TX_OFFLOAD_TCP_TSO;
2316 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2318 dev_info->reta_size = pf->hash_lut_size;
2319 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2321 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2323 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2324 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2325 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2327 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2331 dev_info->default_txconf = (struct rte_eth_txconf) {
2333 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2334 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2335 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2337 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2338 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2339 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2340 ETH_TXQ_FLAGS_NOOFFLOADS,
2343 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2344 .nb_max = I40E_MAX_RING_DESC,
2345 .nb_min = I40E_MIN_RING_DESC,
2346 .nb_align = I40E_ALIGN_RING_DESC,
2349 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2350 .nb_max = I40E_MAX_RING_DESC,
2351 .nb_min = I40E_MIN_RING_DESC,
2352 .nb_align = I40E_ALIGN_RING_DESC,
2355 if (pf->flags & I40E_FLAG_VMDQ) {
2356 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2357 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2358 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2359 pf->max_nb_vmdq_vsi;
2360 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2361 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2362 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2365 if (i40e_is_40G_device(hw->device_id))
2367 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2370 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2374 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2376 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2377 struct i40e_vsi *vsi = pf->main_vsi;
2378 PMD_INIT_FUNC_TRACE();
2381 return i40e_vsi_add_vlan(vsi, vlan_id);
2383 return i40e_vsi_delete_vlan(vsi, vlan_id);
2387 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2388 enum rte_vlan_type vlan_type,
2391 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392 uint64_t reg_r = 0, reg_w = 0;
2393 uint16_t reg_id = 0;
2396 switch (vlan_type) {
2397 case ETH_VLAN_TYPE_OUTER:
2400 case ETH_VLAN_TYPE_INNER:
2405 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2408 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2410 if (ret != I40E_SUCCESS) {
2411 PMD_DRV_LOG(ERR, "Fail to debug read from "
2412 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2416 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2417 "0x%08"PRIx64"", reg_id, reg_r);
2419 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2420 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2421 if (reg_r == reg_w) {
2423 PMD_DRV_LOG(DEBUG, "No need to write");
2427 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2429 if (ret != I40E_SUCCESS) {
2431 PMD_DRV_LOG(ERR, "Fail to debug write to "
2432 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2435 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2436 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2442 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2445 struct i40e_vsi *vsi = pf->main_vsi;
2447 if (mask & ETH_VLAN_FILTER_MASK) {
2448 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2449 i40e_vsi_config_vlan_filter(vsi, TRUE);
2451 i40e_vsi_config_vlan_filter(vsi, FALSE);
2454 if (mask & ETH_VLAN_STRIP_MASK) {
2455 /* Enable or disable VLAN stripping */
2456 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2457 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2459 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2462 if (mask & ETH_VLAN_EXTEND_MASK) {
2463 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2464 i40e_vsi_config_double_vlan(vsi, TRUE);
2466 i40e_vsi_config_double_vlan(vsi, FALSE);
2471 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2472 __rte_unused uint16_t queue,
2473 __rte_unused int on)
2475 PMD_INIT_FUNC_TRACE();
2479 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2481 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2482 struct i40e_vsi *vsi = pf->main_vsi;
2483 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2484 struct i40e_vsi_vlan_pvid_info info;
2486 memset(&info, 0, sizeof(info));
2489 info.config.pvid = pvid;
2491 info.config.reject.tagged =
2492 data->dev_conf.txmode.hw_vlan_reject_tagged;
2493 info.config.reject.untagged =
2494 data->dev_conf.txmode.hw_vlan_reject_untagged;
2497 return i40e_vsi_vlan_pvid_set(vsi, &info);
2501 i40e_dev_led_on(struct rte_eth_dev *dev)
2503 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504 uint32_t mode = i40e_led_get(hw);
2507 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2513 i40e_dev_led_off(struct rte_eth_dev *dev)
2515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516 uint32_t mode = i40e_led_get(hw);
2519 i40e_led_set(hw, 0, false);
2525 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2527 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2530 fc_conf->pause_time = pf->fc_conf.pause_time;
2531 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2532 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2534 /* Return current mode according to actual setting*/
2535 switch (hw->fc.current_mode) {
2537 fc_conf->mode = RTE_FC_FULL;
2539 case I40E_FC_TX_PAUSE:
2540 fc_conf->mode = RTE_FC_TX_PAUSE;
2542 case I40E_FC_RX_PAUSE:
2543 fc_conf->mode = RTE_FC_RX_PAUSE;
2547 fc_conf->mode = RTE_FC_NONE;
2554 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2556 uint32_t mflcn_reg, fctrl_reg, reg;
2557 uint32_t max_high_water;
2558 uint8_t i, aq_failure;
2562 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2563 [RTE_FC_NONE] = I40E_FC_NONE,
2564 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2565 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2566 [RTE_FC_FULL] = I40E_FC_FULL
2569 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2571 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2572 if ((fc_conf->high_water > max_high_water) ||
2573 (fc_conf->high_water < fc_conf->low_water)) {
2574 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2575 "High_water must <= %d.", max_high_water);
2579 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2580 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2581 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2583 pf->fc_conf.pause_time = fc_conf->pause_time;
2584 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2585 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2587 PMD_INIT_FUNC_TRACE();
2589 /* All the link flow control related enable/disable register
2590 * configuration is handle by the F/W
2592 err = i40e_set_fc(hw, &aq_failure, true);
2596 if (i40e_is_40G_device(hw->device_id)) {
2597 /* Configure flow control refresh threshold,
2598 * the value for stat_tx_pause_refresh_timer[8]
2599 * is used for global pause operation.
2603 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2604 pf->fc_conf.pause_time);
2606 /* configure the timer value included in transmitted pause
2608 * the value for stat_tx_pause_quanta[8] is used for global
2611 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2612 pf->fc_conf.pause_time);
2614 fctrl_reg = I40E_READ_REG(hw,
2615 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2617 if (fc_conf->mac_ctrl_frame_fwd != 0)
2618 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2620 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2622 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2625 /* Configure pause time (2 TCs per register) */
2626 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2627 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2628 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2630 /* Configure flow control refresh threshold value */
2631 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2632 pf->fc_conf.pause_time / 2);
2634 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2636 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2637 *depending on configuration
2639 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2640 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2641 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2643 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2644 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2647 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2650 /* config the water marker both based on the packets and bytes */
2651 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2652 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2653 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2654 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2655 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2656 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2657 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2658 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2660 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2661 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2664 I40E_WRITE_FLUSH(hw);
2670 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2671 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2673 PMD_INIT_FUNC_TRACE();
2678 /* Add a MAC address, and update filters */
2680 i40e_macaddr_add(struct rte_eth_dev *dev,
2681 struct ether_addr *mac_addr,
2682 __rte_unused uint32_t index,
2685 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2686 struct i40e_mac_filter_info mac_filter;
2687 struct i40e_vsi *vsi;
2690 /* If VMDQ not enabled or configured, return */
2691 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2692 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2693 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2698 if (pool > pf->nb_cfg_vmdq_vsi) {
2699 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2700 pool, pf->nb_cfg_vmdq_vsi);
2704 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2705 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2706 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2708 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2713 vsi = pf->vmdq[pool - 1].vsi;
2715 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2716 if (ret != I40E_SUCCESS) {
2717 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2722 /* Remove a MAC address, and update filters */
2724 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2726 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2727 struct i40e_vsi *vsi;
2728 struct rte_eth_dev_data *data = dev->data;
2729 struct ether_addr *macaddr;
2734 macaddr = &(data->mac_addrs[index]);
2736 pool_sel = dev->data->mac_pool_sel[index];
2738 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2739 if (pool_sel & (1ULL << i)) {
2743 /* No VMDQ pool enabled or configured */
2744 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2745 (i > pf->nb_cfg_vmdq_vsi)) {
2746 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2750 vsi = pf->vmdq[i - 1].vsi;
2752 ret = i40e_vsi_delete_mac(vsi, macaddr);
2755 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2762 /* Set perfect match or hash match of MAC and VLAN for a VF */
2764 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2765 struct rte_eth_mac_filter *filter,
2769 struct i40e_mac_filter_info mac_filter;
2770 struct ether_addr old_mac;
2771 struct ether_addr *new_mac;
2772 struct i40e_pf_vf *vf = NULL;
2777 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2780 hw = I40E_PF_TO_HW(pf);
2782 if (filter == NULL) {
2783 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2787 new_mac = &filter->mac_addr;
2789 if (is_zero_ether_addr(new_mac)) {
2790 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2794 vf_id = filter->dst_id;
2796 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2797 PMD_DRV_LOG(ERR, "Invalid argument.");
2800 vf = &pf->vfs[vf_id];
2802 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2803 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2808 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2809 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2811 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2814 mac_filter.filter_type = filter->filter_type;
2815 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2816 if (ret != I40E_SUCCESS) {
2817 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2820 ether_addr_copy(new_mac, &pf->dev_addr);
2822 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2824 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2825 if (ret != I40E_SUCCESS) {
2826 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2830 /* Clear device address as it has been removed */
2831 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2832 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2838 /* MAC filter handle */
2840 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2844 struct rte_eth_mac_filter *filter;
2845 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2846 int ret = I40E_NOT_SUPPORTED;
2848 filter = (struct rte_eth_mac_filter *)(arg);
2850 switch (filter_op) {
2851 case RTE_ETH_FILTER_NOP:
2854 case RTE_ETH_FILTER_ADD:
2855 i40e_pf_disable_irq0(hw);
2857 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2858 i40e_pf_enable_irq0(hw);
2860 case RTE_ETH_FILTER_DELETE:
2861 i40e_pf_disable_irq0(hw);
2863 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2864 i40e_pf_enable_irq0(hw);
2867 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2868 ret = I40E_ERR_PARAM;
2876 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2878 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2879 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2885 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2886 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2889 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2893 uint32_t *lut_dw = (uint32_t *)lut;
2894 uint16_t i, lut_size_dw = lut_size / 4;
2896 for (i = 0; i < lut_size_dw; i++)
2897 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2904 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2906 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2907 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2913 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2914 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2917 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2921 uint32_t *lut_dw = (uint32_t *)lut;
2922 uint16_t i, lut_size_dw = lut_size / 4;
2924 for (i = 0; i < lut_size_dw; i++)
2925 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2926 I40E_WRITE_FLUSH(hw);
2933 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2934 struct rte_eth_rss_reta_entry64 *reta_conf,
2937 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2938 uint16_t i, lut_size = pf->hash_lut_size;
2939 uint16_t idx, shift;
2943 if (reta_size != lut_size ||
2944 reta_size > ETH_RSS_RETA_SIZE_512) {
2945 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2946 "(%d) doesn't match the number hardware can supported "
2947 "(%d)\n", reta_size, lut_size);
2951 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2953 PMD_DRV_LOG(ERR, "No memory can be allocated");
2956 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2959 for (i = 0; i < reta_size; i++) {
2960 idx = i / RTE_RETA_GROUP_SIZE;
2961 shift = i % RTE_RETA_GROUP_SIZE;
2962 if (reta_conf[idx].mask & (1ULL << shift))
2963 lut[i] = reta_conf[idx].reta[shift];
2965 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2974 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2975 struct rte_eth_rss_reta_entry64 *reta_conf,
2978 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2979 uint16_t i, lut_size = pf->hash_lut_size;
2980 uint16_t idx, shift;
2984 if (reta_size != lut_size ||
2985 reta_size > ETH_RSS_RETA_SIZE_512) {
2986 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2987 "(%d) doesn't match the number hardware can supported "
2988 "(%d)\n", reta_size, lut_size);
2992 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2994 PMD_DRV_LOG(ERR, "No memory can be allocated");
2998 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3001 for (i = 0; i < reta_size; i++) {
3002 idx = i / RTE_RETA_GROUP_SIZE;
3003 shift = i % RTE_RETA_GROUP_SIZE;
3004 if (reta_conf[idx].mask & (1ULL << shift))
3005 reta_conf[idx].reta[shift] = lut[i];
3015 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3016 * @hw: pointer to the HW structure
3017 * @mem: pointer to mem struct to fill out
3018 * @size: size of memory requested
3019 * @alignment: what to align the allocation to
3021 enum i40e_status_code
3022 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3023 struct i40e_dma_mem *mem,
3027 const struct rte_memzone *mz = NULL;
3028 char z_name[RTE_MEMZONE_NAMESIZE];
3031 return I40E_ERR_PARAM;
3033 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3034 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3035 alignment, RTE_PGSIZE_2M);
3037 return I40E_ERR_NO_MEMORY;
3041 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3042 mem->zone = (const void *)mz;
3043 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3044 "%"PRIu64, mz->name, mem->pa);
3046 return I40E_SUCCESS;
3050 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3051 * @hw: pointer to the HW structure
3052 * @mem: ptr to mem struct to free
3054 enum i40e_status_code
3055 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3056 struct i40e_dma_mem *mem)
3059 return I40E_ERR_PARAM;
3061 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3062 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3064 rte_memzone_free((const struct rte_memzone *)mem->zone);
3069 return I40E_SUCCESS;
3073 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3074 * @hw: pointer to the HW structure
3075 * @mem: pointer to mem struct to fill out
3076 * @size: size of memory requested
3078 enum i40e_status_code
3079 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3080 struct i40e_virt_mem *mem,
3084 return I40E_ERR_PARAM;
3087 mem->va = rte_zmalloc("i40e", size, 0);
3090 return I40E_SUCCESS;
3092 return I40E_ERR_NO_MEMORY;
3096 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3097 * @hw: pointer to the HW structure
3098 * @mem: pointer to mem struct to free
3100 enum i40e_status_code
3101 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3102 struct i40e_virt_mem *mem)
3105 return I40E_ERR_PARAM;
3110 return I40E_SUCCESS;
3114 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3116 rte_spinlock_init(&sp->spinlock);
3120 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3122 rte_spinlock_lock(&sp->spinlock);
3126 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3128 rte_spinlock_unlock(&sp->spinlock);
3132 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3138 * Get the hardware capabilities, which will be parsed
3139 * and saved into struct i40e_hw.
3142 i40e_get_cap(struct i40e_hw *hw)
3144 struct i40e_aqc_list_capabilities_element_resp *buf;
3145 uint16_t len, size = 0;
3148 /* Calculate a huge enough buff for saving response data temporarily */
3149 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3150 I40E_MAX_CAP_ELE_NUM;
3151 buf = rte_zmalloc("i40e", len, 0);
3153 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3154 return I40E_ERR_NO_MEMORY;
3157 /* Get, parse the capabilities and save it to hw */
3158 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3159 i40e_aqc_opc_list_func_capabilities, NULL);
3160 if (ret != I40E_SUCCESS)
3161 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3163 /* Free the temporary buffer after being used */
3170 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3172 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3173 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3174 uint16_t qp_count = 0, vsi_count = 0;
3176 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3177 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3180 /* Add the parameter init for LFC */
3181 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3182 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3183 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3185 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3186 pf->max_num_vsi = hw->func_caps.num_vsis;
3187 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3188 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3189 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3191 /* FDir queue/VSI allocation */
3192 pf->fdir_qp_offset = 0;
3193 if (hw->func_caps.fd) {
3194 pf->flags |= I40E_FLAG_FDIR;
3195 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3197 pf->fdir_nb_qps = 0;
3199 qp_count += pf->fdir_nb_qps;
3202 /* LAN queue/VSI allocation */
3203 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3204 if (!hw->func_caps.rss) {
3207 pf->flags |= I40E_FLAG_RSS;
3208 if (hw->mac.type == I40E_MAC_X722)
3209 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3210 pf->lan_nb_qps = pf->lan_nb_qp_max;
3212 qp_count += pf->lan_nb_qps;
3215 /* VF queue/VSI allocation */
3216 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3217 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3218 pf->flags |= I40E_FLAG_SRIOV;
3219 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3220 pf->vf_num = dev->pci_dev->max_vfs;
3221 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3222 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3223 pf->vf_nb_qps * pf->vf_num);
3228 qp_count += pf->vf_nb_qps * pf->vf_num;
3229 vsi_count += pf->vf_num;
3231 /* VMDq queue/VSI allocation */
3232 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3233 pf->vmdq_nb_qps = 0;
3234 pf->max_nb_vmdq_vsi = 0;
3235 if (hw->func_caps.vmdq) {
3236 if (qp_count < hw->func_caps.num_tx_qp &&
3237 vsi_count < hw->func_caps.num_vsis) {
3238 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3239 qp_count) / pf->vmdq_nb_qp_max;
3241 /* Limit the maximum number of VMDq vsi to the maximum
3242 * ethdev can support
3244 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3245 hw->func_caps.num_vsis - vsi_count);
3246 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3248 if (pf->max_nb_vmdq_vsi) {
3249 pf->flags |= I40E_FLAG_VMDQ;
3250 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3251 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3252 "per VMDQ VSI, in total %u queues",
3253 pf->max_nb_vmdq_vsi,
3254 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3255 pf->max_nb_vmdq_vsi);
3257 PMD_DRV_LOG(INFO, "No enough queues left for "
3261 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3264 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3265 vsi_count += pf->max_nb_vmdq_vsi;
3267 if (hw->func_caps.dcb)
3268 pf->flags |= I40E_FLAG_DCB;
3270 if (qp_count > hw->func_caps.num_tx_qp) {
3271 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3272 "the hardware maximum %u", qp_count,
3273 hw->func_caps.num_tx_qp);
3276 if (vsi_count > hw->func_caps.num_vsis) {
3277 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3278 "the hardware maximum %u", vsi_count,
3279 hw->func_caps.num_vsis);
3287 i40e_pf_get_switch_config(struct i40e_pf *pf)
3289 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3290 struct i40e_aqc_get_switch_config_resp *switch_config;
3291 struct i40e_aqc_switch_config_element_resp *element;
3292 uint16_t start_seid = 0, num_reported;
3295 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3296 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3297 if (!switch_config) {
3298 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3302 /* Get the switch configurations */
3303 ret = i40e_aq_get_switch_config(hw, switch_config,
3304 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3305 if (ret != I40E_SUCCESS) {
3306 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3309 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3310 if (num_reported != 1) { /* The number should be 1 */
3311 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3315 /* Parse the switch configuration elements */
3316 element = &(switch_config->element[0]);
3317 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3318 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3319 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3321 PMD_DRV_LOG(INFO, "Unknown element type");
3324 rte_free(switch_config);
3330 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3333 struct pool_entry *entry;
3335 if (pool == NULL || num == 0)
3338 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3339 if (entry == NULL) {
3340 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3344 /* queue heap initialize */
3345 pool->num_free = num;
3346 pool->num_alloc = 0;
3348 LIST_INIT(&pool->alloc_list);
3349 LIST_INIT(&pool->free_list);
3351 /* Initialize element */
3355 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3360 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3362 struct pool_entry *entry, *next_entry;
3367 for (entry = LIST_FIRST(&pool->alloc_list);
3368 entry && (next_entry = LIST_NEXT(entry, next), 1);
3369 entry = next_entry) {
3370 LIST_REMOVE(entry, next);
3374 for (entry = LIST_FIRST(&pool->free_list);
3375 entry && (next_entry = LIST_NEXT(entry, next), 1);
3376 entry = next_entry) {
3377 LIST_REMOVE(entry, next);
3382 pool->num_alloc = 0;
3384 LIST_INIT(&pool->alloc_list);
3385 LIST_INIT(&pool->free_list);
3389 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3392 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3393 uint32_t pool_offset;
3397 PMD_DRV_LOG(ERR, "Invalid parameter");
3401 pool_offset = base - pool->base;
3402 /* Lookup in alloc list */
3403 LIST_FOREACH(entry, &pool->alloc_list, next) {
3404 if (entry->base == pool_offset) {
3405 valid_entry = entry;
3406 LIST_REMOVE(entry, next);
3411 /* Not find, return */
3412 if (valid_entry == NULL) {
3413 PMD_DRV_LOG(ERR, "Failed to find entry");
3418 * Found it, move it to free list and try to merge.
3419 * In order to make merge easier, always sort it by qbase.
3420 * Find adjacent prev and last entries.
3423 LIST_FOREACH(entry, &pool->free_list, next) {
3424 if (entry->base > valid_entry->base) {
3432 /* Try to merge with next one*/
3434 /* Merge with next one */
3435 if (valid_entry->base + valid_entry->len == next->base) {
3436 next->base = valid_entry->base;
3437 next->len += valid_entry->len;
3438 rte_free(valid_entry);
3445 /* Merge with previous one */
3446 if (prev->base + prev->len == valid_entry->base) {
3447 prev->len += valid_entry->len;
3448 /* If it merge with next one, remove next node */
3450 LIST_REMOVE(valid_entry, next);
3451 rte_free(valid_entry);
3453 rte_free(valid_entry);
3459 /* Not find any entry to merge, insert */
3462 LIST_INSERT_AFTER(prev, valid_entry, next);
3463 else if (next != NULL)
3464 LIST_INSERT_BEFORE(next, valid_entry, next);
3465 else /* It's empty list, insert to head */
3466 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3469 pool->num_free += valid_entry->len;
3470 pool->num_alloc -= valid_entry->len;
3476 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3479 struct pool_entry *entry, *valid_entry;
3481 if (pool == NULL || num == 0) {
3482 PMD_DRV_LOG(ERR, "Invalid parameter");
3486 if (pool->num_free < num) {
3487 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3488 num, pool->num_free);
3493 /* Lookup in free list and find most fit one */
3494 LIST_FOREACH(entry, &pool->free_list, next) {
3495 if (entry->len >= num) {
3497 if (entry->len == num) {
3498 valid_entry = entry;
3501 if (valid_entry == NULL || valid_entry->len > entry->len)
3502 valid_entry = entry;
3506 /* Not find one to satisfy the request, return */
3507 if (valid_entry == NULL) {
3508 PMD_DRV_LOG(ERR, "No valid entry found");
3512 * The entry have equal queue number as requested,
3513 * remove it from alloc_list.
3515 if (valid_entry->len == num) {
3516 LIST_REMOVE(valid_entry, next);
3519 * The entry have more numbers than requested,
3520 * create a new entry for alloc_list and minus its
3521 * queue base and number in free_list.
3523 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3524 if (entry == NULL) {
3525 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3529 entry->base = valid_entry->base;
3531 valid_entry->base += num;
3532 valid_entry->len -= num;
3533 valid_entry = entry;
3536 /* Insert it into alloc list, not sorted */
3537 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3539 pool->num_free -= valid_entry->len;
3540 pool->num_alloc += valid_entry->len;
3542 return valid_entry->base + pool->base;
3546 * bitmap_is_subset - Check whether src2 is subset of src1
3549 bitmap_is_subset(uint8_t src1, uint8_t src2)
3551 return !((src1 ^ src2) & src2);
3554 static enum i40e_status_code
3555 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3557 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3559 /* If DCB is not supported, only default TC is supported */
3560 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3561 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3562 return I40E_NOT_SUPPORTED;
3565 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3566 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3567 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3569 return I40E_NOT_SUPPORTED;
3571 return I40E_SUCCESS;
3575 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3576 struct i40e_vsi_vlan_pvid_info *info)
3579 struct i40e_vsi_context ctxt;
3580 uint8_t vlan_flags = 0;
3583 if (vsi == NULL || info == NULL) {
3584 PMD_DRV_LOG(ERR, "invalid parameters");
3585 return I40E_ERR_PARAM;
3589 vsi->info.pvid = info->config.pvid;
3591 * If insert pvid is enabled, only tagged pkts are
3592 * allowed to be sent out.
3594 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3595 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3598 if (info->config.reject.tagged == 0)
3599 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3601 if (info->config.reject.untagged == 0)
3602 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3604 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3605 I40E_AQ_VSI_PVLAN_MODE_MASK);
3606 vsi->info.port_vlan_flags |= vlan_flags;
3607 vsi->info.valid_sections =
3608 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3609 memset(&ctxt, 0, sizeof(ctxt));
3610 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3611 ctxt.seid = vsi->seid;
3613 hw = I40E_VSI_TO_HW(vsi);
3614 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3615 if (ret != I40E_SUCCESS)
3616 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3622 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3624 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3626 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3628 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3629 if (ret != I40E_SUCCESS)
3633 PMD_DRV_LOG(ERR, "seid not valid");
3637 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3638 tc_bw_data.tc_valid_bits = enabled_tcmap;
3639 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3640 tc_bw_data.tc_bw_credits[i] =
3641 (enabled_tcmap & (1 << i)) ? 1 : 0;
3643 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3644 if (ret != I40E_SUCCESS) {
3645 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3649 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3650 sizeof(vsi->info.qs_handle));
3651 return I40E_SUCCESS;
3654 static enum i40e_status_code
3655 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3656 struct i40e_aqc_vsi_properties_data *info,
3657 uint8_t enabled_tcmap)
3659 enum i40e_status_code ret;
3660 int i, total_tc = 0;
3661 uint16_t qpnum_per_tc, bsf, qp_idx;
3663 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3664 if (ret != I40E_SUCCESS)
3667 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3668 if (enabled_tcmap & (1 << i))
3670 vsi->enabled_tc = enabled_tcmap;
3672 /* Number of queues per enabled TC */
3673 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3674 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3675 bsf = rte_bsf32(qpnum_per_tc);
3677 /* Adjust the queue number to actual queues that can be applied */
3678 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3679 vsi->nb_qps = qpnum_per_tc * total_tc;
3682 * Configure TC and queue mapping parameters, for enabled TC,
3683 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3684 * default queue will serve it.
3687 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3688 if (vsi->enabled_tc & (1 << i)) {
3689 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3690 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3691 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3692 qp_idx += qpnum_per_tc;
3694 info->tc_mapping[i] = 0;
3697 /* Associate queue number with VSI */
3698 if (vsi->type == I40E_VSI_SRIOV) {
3699 info->mapping_flags |=
3700 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3701 for (i = 0; i < vsi->nb_qps; i++)
3702 info->queue_mapping[i] =
3703 rte_cpu_to_le_16(vsi->base_queue + i);
3705 info->mapping_flags |=
3706 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3707 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3709 info->valid_sections |=
3710 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3712 return I40E_SUCCESS;
3716 i40e_veb_release(struct i40e_veb *veb)
3718 struct i40e_vsi *vsi;
3721 if (veb == NULL || veb->associate_vsi == NULL)
3724 if (!TAILQ_EMPTY(&veb->head)) {
3725 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3729 vsi = veb->associate_vsi;
3730 hw = I40E_VSI_TO_HW(vsi);
3732 vsi->uplink_seid = veb->uplink_seid;
3733 i40e_aq_delete_element(hw, veb->seid, NULL);
3736 return I40E_SUCCESS;
3740 static struct i40e_veb *
3741 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3743 struct i40e_veb *veb;
3747 if (NULL == pf || vsi == NULL) {
3748 PMD_DRV_LOG(ERR, "veb setup failed, "
3749 "associated VSI shouldn't null");
3752 hw = I40E_PF_TO_HW(pf);
3754 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3756 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3760 veb->associate_vsi = vsi;
3761 TAILQ_INIT(&veb->head);
3762 veb->uplink_seid = vsi->uplink_seid;
3764 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3765 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3767 if (ret != I40E_SUCCESS) {
3768 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3769 hw->aq.asq_last_status);
3773 /* get statistics index */
3774 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3775 &veb->stats_idx, NULL, NULL, NULL);
3776 if (ret != I40E_SUCCESS) {
3777 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3778 hw->aq.asq_last_status);
3782 /* Get VEB bandwidth, to be implemented */
3783 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3784 vsi->uplink_seid = veb->seid;
3793 i40e_vsi_release(struct i40e_vsi *vsi)
3797 struct i40e_vsi_list *vsi_list;
3799 struct i40e_mac_filter *f;
3802 return I40E_SUCCESS;
3804 pf = I40E_VSI_TO_PF(vsi);
3805 hw = I40E_VSI_TO_HW(vsi);
3807 /* VSI has child to attach, release child first */
3809 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3810 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3812 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3814 i40e_veb_release(vsi->veb);
3817 /* Remove all macvlan filters of the VSI */
3818 i40e_vsi_remove_all_macvlan_filter(vsi);
3819 TAILQ_FOREACH(f, &vsi->mac_list, next)
3822 if (vsi->type != I40E_VSI_MAIN) {
3823 /* Remove vsi from parent's sibling list */
3824 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3825 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3826 return I40E_ERR_PARAM;
3828 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3829 &vsi->sib_vsi_list, list);
3831 /* Remove all switch element of the VSI */
3832 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3833 if (ret != I40E_SUCCESS)
3834 PMD_DRV_LOG(ERR, "Failed to delete element");
3836 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3838 if (vsi->type != I40E_VSI_SRIOV)
3839 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3842 return I40E_SUCCESS;
3846 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3848 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3849 struct i40e_aqc_remove_macvlan_element_data def_filter;
3850 struct i40e_mac_filter_info filter;
3853 if (vsi->type != I40E_VSI_MAIN)
3854 return I40E_ERR_CONFIG;
3855 memset(&def_filter, 0, sizeof(def_filter));
3856 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3858 def_filter.vlan_tag = 0;
3859 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3860 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3861 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3862 if (ret != I40E_SUCCESS) {
3863 struct i40e_mac_filter *f;
3864 struct ether_addr *mac;
3866 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3868 /* It needs to add the permanent mac into mac list */
3869 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3871 PMD_DRV_LOG(ERR, "failed to allocate memory");
3872 return I40E_ERR_NO_MEMORY;
3874 mac = &f->mac_info.mac_addr;
3875 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3877 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3878 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3883 (void)rte_memcpy(&filter.mac_addr,
3884 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3885 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3886 return i40e_vsi_add_mac(vsi, &filter);
3890 * i40e_vsi_get_bw_config - Query VSI BW Information
3891 * @vsi: the VSI to be queried
3893 * Returns 0 on success, negative value on failure
3895 static enum i40e_status_code
3896 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3898 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3899 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3900 struct i40e_hw *hw = &vsi->adapter->hw;
3905 memset(&bw_config, 0, sizeof(bw_config));
3906 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3907 if (ret != I40E_SUCCESS) {
3908 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3909 hw->aq.asq_last_status);
3913 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3914 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3915 &ets_sla_config, NULL);
3916 if (ret != I40E_SUCCESS) {
3917 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3918 "configuration %u", hw->aq.asq_last_status);
3922 /* store and print out BW info */
3923 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3924 vsi->bw_info.bw_max = bw_config.max_bw;
3925 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3926 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3927 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3928 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3930 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3931 vsi->bw_info.bw_ets_share_credits[i] =
3932 ets_sla_config.share_credits[i];
3933 vsi->bw_info.bw_ets_credits[i] =
3934 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3935 /* 4 bits per TC, 4th bit is reserved */
3936 vsi->bw_info.bw_ets_max[i] =
3937 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3938 RTE_LEN2MASK(3, uint8_t));
3939 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3940 vsi->bw_info.bw_ets_share_credits[i]);
3941 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3942 vsi->bw_info.bw_ets_credits[i]);
3943 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3944 vsi->bw_info.bw_ets_max[i]);
3947 return I40E_SUCCESS;
3950 /* i40e_enable_pf_lb
3951 * @pf: pointer to the pf structure
3953 * allow loopback on pf
3956 i40e_enable_pf_lb(struct i40e_pf *pf)
3958 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3959 struct i40e_vsi_context ctxt;
3962 /* Use the FW API if FW >= v5.0 */
3963 if (hw->aq.fw_maj_ver < 5) {
3964 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3968 memset(&ctxt, 0, sizeof(ctxt));
3969 ctxt.seid = pf->main_vsi_seid;
3970 ctxt.pf_num = hw->pf_id;
3971 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3973 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3974 ret, hw->aq.asq_last_status);
3977 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3978 ctxt.info.valid_sections =
3979 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3980 ctxt.info.switch_id |=
3981 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3983 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3985 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3986 hw->aq.asq_last_status);
3991 i40e_vsi_setup(struct i40e_pf *pf,
3992 enum i40e_vsi_type type,
3993 struct i40e_vsi *uplink_vsi,
3994 uint16_t user_param)
3996 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3997 struct i40e_vsi *vsi;
3998 struct i40e_mac_filter_info filter;
4000 struct i40e_vsi_context ctxt;
4001 struct ether_addr broadcast =
4002 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4004 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4005 PMD_DRV_LOG(ERR, "VSI setup failed, "
4006 "VSI link shouldn't be NULL");
4010 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4011 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4012 "uplink VSI should be NULL");
4016 /* If uplink vsi didn't setup VEB, create one first */
4017 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4018 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4020 if (NULL == uplink_vsi->veb) {
4021 PMD_DRV_LOG(ERR, "VEB setup failed");
4024 /* set ALLOWLOOPBACk on pf, when veb is created */
4025 i40e_enable_pf_lb(pf);
4028 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4030 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4033 TAILQ_INIT(&vsi->mac_list);
4035 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4036 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4037 vsi->parent_vsi = uplink_vsi;
4038 vsi->user_param = user_param;
4039 /* Allocate queues */
4040 switch (vsi->type) {
4041 case I40E_VSI_MAIN :
4042 vsi->nb_qps = pf->lan_nb_qps;
4044 case I40E_VSI_SRIOV :
4045 vsi->nb_qps = pf->vf_nb_qps;
4047 case I40E_VSI_VMDQ2:
4048 vsi->nb_qps = pf->vmdq_nb_qps;
4051 vsi->nb_qps = pf->fdir_nb_qps;
4057 * The filter status descriptor is reported in rx queue 0,
4058 * while the tx queue for fdir filter programming has no
4059 * such constraints, can be non-zero queues.
4060 * To simplify it, choose FDIR vsi use queue 0 pair.
4061 * To make sure it will use queue 0 pair, queue allocation
4062 * need be done before this function is called
4064 if (type != I40E_VSI_FDIR) {
4065 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4067 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4071 vsi->base_queue = ret;
4073 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4075 /* VF has MSIX interrupt in VF range, don't allocate here */
4076 if (type == I40E_VSI_MAIN) {
4077 ret = i40e_res_pool_alloc(&pf->msix_pool,
4078 RTE_MIN(vsi->nb_qps,
4079 RTE_MAX_RXTX_INTR_VEC_ID));
4081 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4083 goto fail_queue_alloc;
4085 vsi->msix_intr = ret;
4086 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4087 } else if (type != I40E_VSI_SRIOV) {
4088 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4090 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4091 goto fail_queue_alloc;
4093 vsi->msix_intr = ret;
4101 if (type == I40E_VSI_MAIN) {
4102 /* For main VSI, no need to add since it's default one */
4103 vsi->uplink_seid = pf->mac_seid;
4104 vsi->seid = pf->main_vsi_seid;
4105 /* Bind queues with specific MSIX interrupt */
4107 * Needs 2 interrupt at least, one for misc cause which will
4108 * enabled from OS side, Another for queues binding the
4109 * interrupt from device side only.
4112 /* Get default VSI parameters from hardware */
4113 memset(&ctxt, 0, sizeof(ctxt));
4114 ctxt.seid = vsi->seid;
4115 ctxt.pf_num = hw->pf_id;
4116 ctxt.uplink_seid = vsi->uplink_seid;
4118 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4119 if (ret != I40E_SUCCESS) {
4120 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4121 goto fail_msix_alloc;
4123 (void)rte_memcpy(&vsi->info, &ctxt.info,
4124 sizeof(struct i40e_aqc_vsi_properties_data));
4125 vsi->vsi_id = ctxt.vsi_number;
4126 vsi->info.valid_sections = 0;
4128 /* Configure tc, enabled TC0 only */
4129 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4131 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4132 goto fail_msix_alloc;
4135 /* TC, queue mapping */
4136 memset(&ctxt, 0, sizeof(ctxt));
4137 vsi->info.valid_sections |=
4138 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4139 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4140 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4141 (void)rte_memcpy(&ctxt.info, &vsi->info,
4142 sizeof(struct i40e_aqc_vsi_properties_data));
4143 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4144 I40E_DEFAULT_TCMAP);
4145 if (ret != I40E_SUCCESS) {
4146 PMD_DRV_LOG(ERR, "Failed to configure "
4147 "TC queue mapping");
4148 goto fail_msix_alloc;
4150 ctxt.seid = vsi->seid;
4151 ctxt.pf_num = hw->pf_id;
4152 ctxt.uplink_seid = vsi->uplink_seid;
4155 /* Update VSI parameters */
4156 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4157 if (ret != I40E_SUCCESS) {
4158 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4159 goto fail_msix_alloc;
4162 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4163 sizeof(vsi->info.tc_mapping));
4164 (void)rte_memcpy(&vsi->info.queue_mapping,
4165 &ctxt.info.queue_mapping,
4166 sizeof(vsi->info.queue_mapping));
4167 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4168 vsi->info.valid_sections = 0;
4170 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4174 * Updating default filter settings are necessary to prevent
4175 * reception of tagged packets.
4176 * Some old firmware configurations load a default macvlan
4177 * filter which accepts both tagged and untagged packets.
4178 * The updating is to use a normal filter instead if needed.
4179 * For NVM 4.2.2 or after, the updating is not needed anymore.
4180 * The firmware with correct configurations load the default
4181 * macvlan filter which is expected and cannot be removed.
4183 i40e_update_default_filter_setting(vsi);
4184 i40e_config_qinq(hw, vsi);
4185 } else if (type == I40E_VSI_SRIOV) {
4186 memset(&ctxt, 0, sizeof(ctxt));
4188 * For other VSI, the uplink_seid equals to uplink VSI's
4189 * uplink_seid since they share same VEB
4191 vsi->uplink_seid = uplink_vsi->uplink_seid;
4192 ctxt.pf_num = hw->pf_id;
4193 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4194 ctxt.uplink_seid = vsi->uplink_seid;
4195 ctxt.connection_type = 0x1;
4196 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4198 /* Use the VEB configuration if FW >= v5.0 */
4199 if (hw->aq.fw_maj_ver >= 5) {
4200 /* Configure switch ID */
4201 ctxt.info.valid_sections |=
4202 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4203 ctxt.info.switch_id =
4204 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4207 /* Configure port/vlan */
4208 ctxt.info.valid_sections |=
4209 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4210 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4211 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4212 I40E_DEFAULT_TCMAP);
4213 if (ret != I40E_SUCCESS) {
4214 PMD_DRV_LOG(ERR, "Failed to configure "
4215 "TC queue mapping");
4216 goto fail_msix_alloc;
4218 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4219 ctxt.info.valid_sections |=
4220 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4222 * Since VSI is not created yet, only configure parameter,
4223 * will add vsi below.
4226 i40e_config_qinq(hw, vsi);
4227 } else if (type == I40E_VSI_VMDQ2) {
4228 memset(&ctxt, 0, sizeof(ctxt));
4230 * For other VSI, the uplink_seid equals to uplink VSI's
4231 * uplink_seid since they share same VEB
4233 vsi->uplink_seid = uplink_vsi->uplink_seid;
4234 ctxt.pf_num = hw->pf_id;
4236 ctxt.uplink_seid = vsi->uplink_seid;
4237 ctxt.connection_type = 0x1;
4238 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4240 ctxt.info.valid_sections |=
4241 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4242 /* user_param carries flag to enable loop back */
4244 ctxt.info.switch_id =
4245 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4246 ctxt.info.switch_id |=
4247 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4250 /* Configure port/vlan */
4251 ctxt.info.valid_sections |=
4252 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4253 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4254 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4255 I40E_DEFAULT_TCMAP);
4256 if (ret != I40E_SUCCESS) {
4257 PMD_DRV_LOG(ERR, "Failed to configure "
4258 "TC queue mapping");
4259 goto fail_msix_alloc;
4261 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4262 ctxt.info.valid_sections |=
4263 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4264 } else if (type == I40E_VSI_FDIR) {
4265 memset(&ctxt, 0, sizeof(ctxt));
4266 vsi->uplink_seid = uplink_vsi->uplink_seid;
4267 ctxt.pf_num = hw->pf_id;
4269 ctxt.uplink_seid = vsi->uplink_seid;
4270 ctxt.connection_type = 0x1; /* regular data port */
4271 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4272 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4273 I40E_DEFAULT_TCMAP);
4274 if (ret != I40E_SUCCESS) {
4275 PMD_DRV_LOG(ERR, "Failed to configure "
4276 "TC queue mapping.");
4277 goto fail_msix_alloc;
4279 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4280 ctxt.info.valid_sections |=
4281 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4283 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4284 goto fail_msix_alloc;
4287 if (vsi->type != I40E_VSI_MAIN) {
4288 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4289 if (ret != I40E_SUCCESS) {
4290 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4291 hw->aq.asq_last_status);
4292 goto fail_msix_alloc;
4294 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4295 vsi->info.valid_sections = 0;
4296 vsi->seid = ctxt.seid;
4297 vsi->vsi_id = ctxt.vsi_number;
4298 vsi->sib_vsi_list.vsi = vsi;
4299 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4300 &vsi->sib_vsi_list, list);
4303 /* MAC/VLAN configuration */
4304 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4305 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4307 ret = i40e_vsi_add_mac(vsi, &filter);
4308 if (ret != I40E_SUCCESS) {
4309 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4310 goto fail_msix_alloc;
4313 /* Get VSI BW information */
4314 i40e_vsi_get_bw_config(vsi);
4317 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4319 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4325 /* Configure vlan filter on or off */
4327 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4330 struct i40e_mac_filter *f;
4331 struct i40e_mac_filter_info *mac_filter;
4332 enum rte_mac_filter_type desired_filter;
4333 int ret = I40E_SUCCESS;
4336 /* Filter to match MAC and VLAN */
4337 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4339 /* Filter to match only MAC */
4340 desired_filter = RTE_MAC_PERFECT_MATCH;
4345 mac_filter = rte_zmalloc("mac_filter_info_data",
4346 num * sizeof(*mac_filter), 0);
4347 if (mac_filter == NULL) {
4348 PMD_DRV_LOG(ERR, "failed to allocate memory");
4349 return I40E_ERR_NO_MEMORY;
4354 /* Remove all existing mac */
4355 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4356 mac_filter[i] = f->mac_info;
4357 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4359 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4360 on ? "enable" : "disable");
4366 /* Override with new filter */
4367 for (i = 0; i < num; i++) {
4368 mac_filter[i].filter_type = desired_filter;
4369 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4371 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4372 on ? "enable" : "disable");
4378 rte_free(mac_filter);
4382 /* Configure vlan stripping on or off */
4384 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4386 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4387 struct i40e_vsi_context ctxt;
4389 int ret = I40E_SUCCESS;
4391 /* Check if it has been already on or off */
4392 if (vsi->info.valid_sections &
4393 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4395 if ((vsi->info.port_vlan_flags &
4396 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4397 return 0; /* already on */
4399 if ((vsi->info.port_vlan_flags &
4400 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4401 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4402 return 0; /* already off */
4407 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4409 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4410 vsi->info.valid_sections =
4411 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4412 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4413 vsi->info.port_vlan_flags |= vlan_flags;
4414 ctxt.seid = vsi->seid;
4415 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4416 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4418 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4419 on ? "enable" : "disable");
4425 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4427 struct rte_eth_dev_data *data = dev->data;
4431 /* Apply vlan offload setting */
4432 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4433 i40e_vlan_offload_set(dev, mask);
4435 /* Apply double-vlan setting, not implemented yet */
4437 /* Apply pvid setting */
4438 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4439 data->dev_conf.txmode.hw_vlan_insert_pvid);
4441 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4447 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4449 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4451 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4455 i40e_update_flow_control(struct i40e_hw *hw)
4457 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4458 struct i40e_link_status link_status;
4459 uint32_t rxfc = 0, txfc = 0, reg;
4463 memset(&link_status, 0, sizeof(link_status));
4464 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4465 if (ret != I40E_SUCCESS) {
4466 PMD_DRV_LOG(ERR, "Failed to get link status information");
4467 goto write_reg; /* Disable flow control */
4470 an_info = hw->phy.link_info.an_info;
4471 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4472 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4473 ret = I40E_ERR_NOT_READY;
4474 goto write_reg; /* Disable flow control */
4477 * If link auto negotiation is enabled, flow control needs to
4478 * be configured according to it
4480 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4481 case I40E_LINK_PAUSE_RXTX:
4484 hw->fc.current_mode = I40E_FC_FULL;
4486 case I40E_AQ_LINK_PAUSE_RX:
4488 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4490 case I40E_AQ_LINK_PAUSE_TX:
4492 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4495 hw->fc.current_mode = I40E_FC_NONE;
4500 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4501 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4502 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4503 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4504 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4505 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4512 i40e_pf_setup(struct i40e_pf *pf)
4514 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4515 struct i40e_filter_control_settings settings;
4516 struct i40e_vsi *vsi;
4519 /* Clear all stats counters */
4520 pf->offset_loaded = FALSE;
4521 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4522 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4524 ret = i40e_pf_get_switch_config(pf);
4525 if (ret != I40E_SUCCESS) {
4526 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4529 if (pf->flags & I40E_FLAG_FDIR) {
4530 /* make queue allocated first, let FDIR use queue pair 0*/
4531 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4532 if (ret != I40E_FDIR_QUEUE_ID) {
4533 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4535 pf->flags &= ~I40E_FLAG_FDIR;
4538 /* main VSI setup */
4539 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4541 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4542 return I40E_ERR_NOT_READY;
4546 /* Configure filter control */
4547 memset(&settings, 0, sizeof(settings));
4548 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4549 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4550 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4551 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4553 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4554 hw->func_caps.rss_table_size);
4555 return I40E_ERR_PARAM;
4557 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4558 "size: %u\n", hw->func_caps.rss_table_size);
4559 pf->hash_lut_size = hw->func_caps.rss_table_size;
4561 /* Enable ethtype and macvlan filters */
4562 settings.enable_ethtype = TRUE;
4563 settings.enable_macvlan = TRUE;
4564 ret = i40e_set_filter_control(hw, &settings);
4566 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4569 /* Update flow control according to the auto negotiation */
4570 i40e_update_flow_control(hw);
4572 return I40E_SUCCESS;
4576 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4582 * Set or clear TX Queue Disable flags,
4583 * which is required by hardware.
4585 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4586 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4588 /* Wait until the request is finished */
4589 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4590 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4591 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4592 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4593 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4599 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4600 return I40E_SUCCESS; /* already on, skip next steps */
4602 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4603 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4605 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4606 return I40E_SUCCESS; /* already off, skip next steps */
4607 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4609 /* Write the register */
4610 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4611 /* Check the result */
4612 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4613 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4614 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4616 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4617 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4620 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4621 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4625 /* Check if it is timeout */
4626 if (j >= I40E_CHK_Q_ENA_COUNT) {
4627 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4628 (on ? "enable" : "disable"), q_idx);
4629 return I40E_ERR_TIMEOUT;
4632 return I40E_SUCCESS;
4635 /* Swith on or off the tx queues */
4637 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4639 struct rte_eth_dev_data *dev_data = pf->dev_data;
4640 struct i40e_tx_queue *txq;
4641 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4645 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4646 txq = dev_data->tx_queues[i];
4647 /* Don't operate the queue if not configured or
4648 * if starting only per queue */
4649 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4652 ret = i40e_dev_tx_queue_start(dev, i);
4654 ret = i40e_dev_tx_queue_stop(dev, i);
4655 if ( ret != I40E_SUCCESS)
4659 return I40E_SUCCESS;
4663 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4668 /* Wait until the request is finished */
4669 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4670 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4671 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4672 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4673 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4678 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4679 return I40E_SUCCESS; /* Already on, skip next steps */
4680 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4682 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4683 return I40E_SUCCESS; /* Already off, skip next steps */
4684 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4687 /* Write the register */
4688 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4689 /* Check the result */
4690 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4691 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4692 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4694 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4695 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4698 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4699 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4704 /* Check if it is timeout */
4705 if (j >= I40E_CHK_Q_ENA_COUNT) {
4706 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4707 (on ? "enable" : "disable"), q_idx);
4708 return I40E_ERR_TIMEOUT;
4711 return I40E_SUCCESS;
4713 /* Switch on or off the rx queues */
4715 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4717 struct rte_eth_dev_data *dev_data = pf->dev_data;
4718 struct i40e_rx_queue *rxq;
4719 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4723 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4724 rxq = dev_data->rx_queues[i];
4725 /* Don't operate the queue if not configured or
4726 * if starting only per queue */
4727 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4730 ret = i40e_dev_rx_queue_start(dev, i);
4732 ret = i40e_dev_rx_queue_stop(dev, i);
4733 if (ret != I40E_SUCCESS)
4737 return I40E_SUCCESS;
4740 /* Switch on or off all the rx/tx queues */
4742 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4747 /* enable rx queues before enabling tx queues */
4748 ret = i40e_dev_switch_rx_queues(pf, on);
4750 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4753 ret = i40e_dev_switch_tx_queues(pf, on);
4755 /* Stop tx queues before stopping rx queues */
4756 ret = i40e_dev_switch_tx_queues(pf, on);
4758 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4761 ret = i40e_dev_switch_rx_queues(pf, on);
4767 /* Initialize VSI for TX */
4769 i40e_dev_tx_init(struct i40e_pf *pf)
4771 struct rte_eth_dev_data *data = pf->dev_data;
4773 uint32_t ret = I40E_SUCCESS;
4774 struct i40e_tx_queue *txq;
4776 for (i = 0; i < data->nb_tx_queues; i++) {
4777 txq = data->tx_queues[i];
4778 if (!txq || !txq->q_set)
4780 ret = i40e_tx_queue_init(txq);
4781 if (ret != I40E_SUCCESS)
4784 if (ret == I40E_SUCCESS)
4785 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4791 /* Initialize VSI for RX */
4793 i40e_dev_rx_init(struct i40e_pf *pf)
4795 struct rte_eth_dev_data *data = pf->dev_data;
4796 int ret = I40E_SUCCESS;
4798 struct i40e_rx_queue *rxq;
4800 i40e_pf_config_mq_rx(pf);
4801 for (i = 0; i < data->nb_rx_queues; i++) {
4802 rxq = data->rx_queues[i];
4803 if (!rxq || !rxq->q_set)
4806 ret = i40e_rx_queue_init(rxq);
4807 if (ret != I40E_SUCCESS) {
4808 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4813 if (ret == I40E_SUCCESS)
4814 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4821 i40e_dev_rxtx_init(struct i40e_pf *pf)
4825 err = i40e_dev_tx_init(pf);
4827 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4830 err = i40e_dev_rx_init(pf);
4832 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4840 i40e_vmdq_setup(struct rte_eth_dev *dev)
4842 struct rte_eth_conf *conf = &dev->data->dev_conf;
4843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4844 int i, err, conf_vsis, j, loop;
4845 struct i40e_vsi *vsi;
4846 struct i40e_vmdq_info *vmdq_info;
4847 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4848 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4851 * Disable interrupt to avoid message from VF. Furthermore, it will
4852 * avoid race condition in VSI creation/destroy.
4854 i40e_pf_disable_irq0(hw);
4856 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4857 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4861 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4862 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4863 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4864 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4865 pf->max_nb_vmdq_vsi);
4869 if (pf->vmdq != NULL) {
4870 PMD_INIT_LOG(INFO, "VMDQ already configured");
4874 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4875 sizeof(*vmdq_info) * conf_vsis, 0);
4877 if (pf->vmdq == NULL) {
4878 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4882 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4884 /* Create VMDQ VSI */
4885 for (i = 0; i < conf_vsis; i++) {
4886 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4887 vmdq_conf->enable_loop_back);
4889 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4893 vmdq_info = &pf->vmdq[i];
4895 vmdq_info->vsi = vsi;
4897 pf->nb_cfg_vmdq_vsi = conf_vsis;
4899 /* Configure Vlan */
4900 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4901 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4902 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4903 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4904 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4905 vmdq_conf->pool_map[i].vlan_id, j);
4907 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4908 vmdq_conf->pool_map[i].vlan_id);
4910 PMD_INIT_LOG(ERR, "Failed to add vlan");
4918 i40e_pf_enable_irq0(hw);
4923 for (i = 0; i < conf_vsis; i++)
4924 if (pf->vmdq[i].vsi == NULL)
4927 i40e_vsi_release(pf->vmdq[i].vsi);
4931 i40e_pf_enable_irq0(hw);
4936 i40e_stat_update_32(struct i40e_hw *hw,
4944 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4948 if (new_data >= *offset)
4949 *stat = (uint64_t)(new_data - *offset);
4951 *stat = (uint64_t)((new_data +
4952 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4956 i40e_stat_update_48(struct i40e_hw *hw,
4965 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4966 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4967 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4972 if (new_data >= *offset)
4973 *stat = new_data - *offset;
4975 *stat = (uint64_t)((new_data +
4976 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4978 *stat &= I40E_48_BIT_MASK;
4983 i40e_pf_disable_irq0(struct i40e_hw *hw)
4985 /* Disable all interrupt types */
4986 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4987 I40E_WRITE_FLUSH(hw);
4992 i40e_pf_enable_irq0(struct i40e_hw *hw)
4994 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4995 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4996 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4997 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4998 I40E_WRITE_FLUSH(hw);
5002 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5004 /* read pending request and disable first */
5005 i40e_pf_disable_irq0(hw);
5006 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5007 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5008 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5011 /* Link no queues with irq0 */
5012 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5013 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5017 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5019 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5023 uint32_t index, offset, val;
5028 * Try to find which VF trigger a reset, use absolute VF id to access
5029 * since the reg is global register.
5031 for (i = 0; i < pf->vf_num; i++) {
5032 abs_vf_id = hw->func_caps.vf_base_id + i;
5033 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5034 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5035 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5036 /* VFR event occured */
5037 if (val & (0x1 << offset)) {
5040 /* Clear the event first */
5041 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5043 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5045 * Only notify a VF reset event occured,
5046 * don't trigger another SW reset
5048 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5049 if (ret != I40E_SUCCESS)
5050 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5056 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5058 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059 struct i40e_arq_event_info info;
5060 uint16_t pending, opcode;
5063 info.buf_len = I40E_AQ_BUF_SZ;
5064 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5065 if (!info.msg_buf) {
5066 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5072 ret = i40e_clean_arq_element(hw, &info, &pending);
5074 if (ret != I40E_SUCCESS) {
5075 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5076 "aq_err: %u", hw->aq.asq_last_status);
5079 opcode = rte_le_to_cpu_16(info.desc.opcode);
5082 case i40e_aqc_opc_send_msg_to_pf:
5083 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5084 i40e_pf_host_handle_vf_msg(dev,
5085 rte_le_to_cpu_16(info.desc.retval),
5086 rte_le_to_cpu_32(info.desc.cookie_high),
5087 rte_le_to_cpu_32(info.desc.cookie_low),
5092 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5097 rte_free(info.msg_buf);
5101 * Interrupt handler is registered as the alarm callback for handling LSC
5102 * interrupt in a definite of time, in order to wait the NIC into a stable
5103 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5104 * no need for link down interrupt.
5107 i40e_dev_interrupt_delayed_handler(void *param)
5109 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5110 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113 /* read interrupt causes again */
5114 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5116 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5117 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5118 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5119 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5120 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5121 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5122 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5123 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5124 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5125 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5126 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5128 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5129 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5130 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5131 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5132 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5134 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5135 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5136 i40e_dev_handle_vfr_event(dev);
5138 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5139 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5140 i40e_dev_handle_aq_msg(dev);
5143 /* handle the link up interrupt in an alarm callback */
5144 i40e_dev_link_update(dev, 0);
5145 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5147 i40e_pf_enable_irq0(hw);
5148 rte_intr_enable(&(dev->pci_dev->intr_handle));
5152 * Interrupt handler triggered by NIC for handling
5153 * specific interrupt.
5156 * Pointer to interrupt handle.
5158 * The address of parameter (struct rte_eth_dev *) regsitered before.
5164 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5167 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5168 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171 /* Disable interrupt */
5172 i40e_pf_disable_irq0(hw);
5174 /* read out interrupt causes */
5175 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5177 /* No interrupt event indicated */
5178 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5179 PMD_DRV_LOG(INFO, "No interrupt event");
5182 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5183 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5184 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5185 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5186 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5187 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5188 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5189 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5190 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5191 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5192 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5193 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5194 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5195 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5196 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5197 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5199 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5200 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5201 i40e_dev_handle_vfr_event(dev);
5203 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5204 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5205 i40e_dev_handle_aq_msg(dev);
5208 /* Link Status Change interrupt */
5209 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5210 #define I40E_US_PER_SECOND 1000000
5211 struct rte_eth_link link;
5213 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5214 memset(&link, 0, sizeof(link));
5215 rte_i40e_dev_atomic_read_link_status(dev, &link);
5216 i40e_dev_link_update(dev, 0);
5219 * For link up interrupt, it needs to wait 1 second to let the
5220 * hardware be a stable state. Otherwise several consecutive
5221 * interrupts can be observed.
5222 * For link down interrupt, no need to wait.
5224 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5225 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5228 _rte_eth_dev_callback_process(dev,
5229 RTE_ETH_EVENT_INTR_LSC);
5233 /* Enable interrupt */
5234 i40e_pf_enable_irq0(hw);
5235 rte_intr_enable(&(dev->pci_dev->intr_handle));
5239 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5240 struct i40e_macvlan_filter *filter,
5243 int ele_num, ele_buff_size;
5244 int num, actual_num, i;
5246 int ret = I40E_SUCCESS;
5247 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5248 struct i40e_aqc_add_macvlan_element_data *req_list;
5250 if (filter == NULL || total == 0)
5251 return I40E_ERR_PARAM;
5252 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5253 ele_buff_size = hw->aq.asq_buf_size;
5255 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5256 if (req_list == NULL) {
5257 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5258 return I40E_ERR_NO_MEMORY;
5263 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5264 memset(req_list, 0, ele_buff_size);
5266 for (i = 0; i < actual_num; i++) {
5267 (void)rte_memcpy(req_list[i].mac_addr,
5268 &filter[num + i].macaddr, ETH_ADDR_LEN);
5269 req_list[i].vlan_tag =
5270 rte_cpu_to_le_16(filter[num + i].vlan_id);
5272 switch (filter[num + i].filter_type) {
5273 case RTE_MAC_PERFECT_MATCH:
5274 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5275 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5277 case RTE_MACVLAN_PERFECT_MATCH:
5278 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5280 case RTE_MAC_HASH_MATCH:
5281 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5282 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5284 case RTE_MACVLAN_HASH_MATCH:
5285 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5288 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5289 ret = I40E_ERR_PARAM;
5293 req_list[i].queue_number = 0;
5295 req_list[i].flags = rte_cpu_to_le_16(flags);
5298 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5300 if (ret != I40E_SUCCESS) {
5301 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5305 } while (num < total);
5313 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5314 struct i40e_macvlan_filter *filter,
5317 int ele_num, ele_buff_size;
5318 int num, actual_num, i;
5320 int ret = I40E_SUCCESS;
5321 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5322 struct i40e_aqc_remove_macvlan_element_data *req_list;
5324 if (filter == NULL || total == 0)
5325 return I40E_ERR_PARAM;
5327 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5328 ele_buff_size = hw->aq.asq_buf_size;
5330 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5331 if (req_list == NULL) {
5332 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5333 return I40E_ERR_NO_MEMORY;
5338 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5339 memset(req_list, 0, ele_buff_size);
5341 for (i = 0; i < actual_num; i++) {
5342 (void)rte_memcpy(req_list[i].mac_addr,
5343 &filter[num + i].macaddr, ETH_ADDR_LEN);
5344 req_list[i].vlan_tag =
5345 rte_cpu_to_le_16(filter[num + i].vlan_id);
5347 switch (filter[num + i].filter_type) {
5348 case RTE_MAC_PERFECT_MATCH:
5349 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5350 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5352 case RTE_MACVLAN_PERFECT_MATCH:
5353 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5355 case RTE_MAC_HASH_MATCH:
5356 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5357 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5359 case RTE_MACVLAN_HASH_MATCH:
5360 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5363 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5364 ret = I40E_ERR_PARAM;
5367 req_list[i].flags = rte_cpu_to_le_16(flags);
5370 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5372 if (ret != I40E_SUCCESS) {
5373 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5377 } while (num < total);
5384 /* Find out specific MAC filter */
5385 static struct i40e_mac_filter *
5386 i40e_find_mac_filter(struct i40e_vsi *vsi,
5387 struct ether_addr *macaddr)
5389 struct i40e_mac_filter *f;
5391 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5392 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5400 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5403 uint32_t vid_idx, vid_bit;
5405 if (vlan_id > ETH_VLAN_ID_MAX)
5408 vid_idx = I40E_VFTA_IDX(vlan_id);
5409 vid_bit = I40E_VFTA_BIT(vlan_id);
5411 if (vsi->vfta[vid_idx] & vid_bit)
5418 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5419 uint16_t vlan_id, bool on)
5421 uint32_t vid_idx, vid_bit;
5423 if (vlan_id > ETH_VLAN_ID_MAX)
5426 vid_idx = I40E_VFTA_IDX(vlan_id);
5427 vid_bit = I40E_VFTA_BIT(vlan_id);
5430 vsi->vfta[vid_idx] |= vid_bit;
5432 vsi->vfta[vid_idx] &= ~vid_bit;
5436 * Find all vlan options for specific mac addr,
5437 * return with actual vlan found.
5440 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5441 struct i40e_macvlan_filter *mv_f,
5442 int num, struct ether_addr *addr)
5448 * Not to use i40e_find_vlan_filter to decrease the loop time,
5449 * although the code looks complex.
5451 if (num < vsi->vlan_num)
5452 return I40E_ERR_PARAM;
5455 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5457 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5458 if (vsi->vfta[j] & (1 << k)) {
5460 PMD_DRV_LOG(ERR, "vlan number "
5462 return I40E_ERR_PARAM;
5464 (void)rte_memcpy(&mv_f[i].macaddr,
5465 addr, ETH_ADDR_LEN);
5467 j * I40E_UINT32_BIT_SIZE + k;
5473 return I40E_SUCCESS;
5477 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5478 struct i40e_macvlan_filter *mv_f,
5483 struct i40e_mac_filter *f;
5485 if (num < vsi->mac_num)
5486 return I40E_ERR_PARAM;
5488 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5490 PMD_DRV_LOG(ERR, "buffer number not match");
5491 return I40E_ERR_PARAM;
5493 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5495 mv_f[i].vlan_id = vlan;
5496 mv_f[i].filter_type = f->mac_info.filter_type;
5500 return I40E_SUCCESS;
5504 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5507 struct i40e_mac_filter *f;
5508 struct i40e_macvlan_filter *mv_f;
5509 int ret = I40E_SUCCESS;
5511 if (vsi == NULL || vsi->mac_num == 0)
5512 return I40E_ERR_PARAM;
5514 /* Case that no vlan is set */
5515 if (vsi->vlan_num == 0)
5518 num = vsi->mac_num * vsi->vlan_num;
5520 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5522 PMD_DRV_LOG(ERR, "failed to allocate memory");
5523 return I40E_ERR_NO_MEMORY;
5527 if (vsi->vlan_num == 0) {
5528 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5529 (void)rte_memcpy(&mv_f[i].macaddr,
5530 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5531 mv_f[i].vlan_id = 0;
5535 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5536 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5537 vsi->vlan_num, &f->mac_info.mac_addr);
5538 if (ret != I40E_SUCCESS)
5544 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5552 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5554 struct i40e_macvlan_filter *mv_f;
5556 int ret = I40E_SUCCESS;
5558 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5559 return I40E_ERR_PARAM;
5561 /* If it's already set, just return */
5562 if (i40e_find_vlan_filter(vsi,vlan))
5563 return I40E_SUCCESS;
5565 mac_num = vsi->mac_num;
5568 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5569 return I40E_ERR_PARAM;
5572 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5575 PMD_DRV_LOG(ERR, "failed to allocate memory");
5576 return I40E_ERR_NO_MEMORY;
5579 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5581 if (ret != I40E_SUCCESS)
5584 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5586 if (ret != I40E_SUCCESS)
5589 i40e_set_vlan_filter(vsi, vlan, 1);
5599 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5601 struct i40e_macvlan_filter *mv_f;
5603 int ret = I40E_SUCCESS;
5606 * Vlan 0 is the generic filter for untagged packets
5607 * and can't be removed.
5609 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5610 return I40E_ERR_PARAM;
5612 /* If can't find it, just return */
5613 if (!i40e_find_vlan_filter(vsi, vlan))
5614 return I40E_ERR_PARAM;
5616 mac_num = vsi->mac_num;
5619 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5620 return I40E_ERR_PARAM;
5623 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5626 PMD_DRV_LOG(ERR, "failed to allocate memory");
5627 return I40E_ERR_NO_MEMORY;
5630 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5632 if (ret != I40E_SUCCESS)
5635 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5637 if (ret != I40E_SUCCESS)
5640 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5641 if (vsi->vlan_num == 1) {
5642 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5643 if (ret != I40E_SUCCESS)
5646 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5647 if (ret != I40E_SUCCESS)
5651 i40e_set_vlan_filter(vsi, vlan, 0);
5661 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5663 struct i40e_mac_filter *f;
5664 struct i40e_macvlan_filter *mv_f;
5665 int i, vlan_num = 0;
5666 int ret = I40E_SUCCESS;
5668 /* If it's add and we've config it, return */
5669 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5671 return I40E_SUCCESS;
5672 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5673 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5676 * If vlan_num is 0, that's the first time to add mac,
5677 * set mask for vlan_id 0.
5679 if (vsi->vlan_num == 0) {
5680 i40e_set_vlan_filter(vsi, 0, 1);
5683 vlan_num = vsi->vlan_num;
5684 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5685 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5688 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5690 PMD_DRV_LOG(ERR, "failed to allocate memory");
5691 return I40E_ERR_NO_MEMORY;
5694 for (i = 0; i < vlan_num; i++) {
5695 mv_f[i].filter_type = mac_filter->filter_type;
5696 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5700 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5701 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5702 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5703 &mac_filter->mac_addr);
5704 if (ret != I40E_SUCCESS)
5708 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5709 if (ret != I40E_SUCCESS)
5712 /* Add the mac addr into mac list */
5713 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5715 PMD_DRV_LOG(ERR, "failed to allocate memory");
5716 ret = I40E_ERR_NO_MEMORY;
5719 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5721 f->mac_info.filter_type = mac_filter->filter_type;
5722 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5733 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5735 struct i40e_mac_filter *f;
5736 struct i40e_macvlan_filter *mv_f;
5738 enum rte_mac_filter_type filter_type;
5739 int ret = I40E_SUCCESS;
5741 /* Can't find it, return an error */
5742 f = i40e_find_mac_filter(vsi, addr);
5744 return I40E_ERR_PARAM;
5746 vlan_num = vsi->vlan_num;
5747 filter_type = f->mac_info.filter_type;
5748 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5749 filter_type == RTE_MACVLAN_HASH_MATCH) {
5750 if (vlan_num == 0) {
5751 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5752 return I40E_ERR_PARAM;
5754 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5755 filter_type == RTE_MAC_HASH_MATCH)
5758 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5760 PMD_DRV_LOG(ERR, "failed to allocate memory");
5761 return I40E_ERR_NO_MEMORY;
5764 for (i = 0; i < vlan_num; i++) {
5765 mv_f[i].filter_type = filter_type;
5766 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5769 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5770 filter_type == RTE_MACVLAN_HASH_MATCH) {
5771 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5772 if (ret != I40E_SUCCESS)
5776 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5777 if (ret != I40E_SUCCESS)
5780 /* Remove the mac addr into mac list */
5781 TAILQ_REMOVE(&vsi->mac_list, f, next);
5791 /* Configure hash enable flags for RSS */
5793 i40e_config_hena(uint64_t flags)
5800 if (flags & ETH_RSS_FRAG_IPV4)
5801 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5802 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5803 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5804 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5805 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5806 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5807 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5808 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5809 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5810 if (flags & ETH_RSS_FRAG_IPV6)
5811 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5812 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5813 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5814 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5815 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5816 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5817 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5818 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5819 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5820 if (flags & ETH_RSS_L2_PAYLOAD)
5821 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5826 /* Parse the hash enable flags */
5828 i40e_parse_hena(uint64_t flags)
5830 uint64_t rss_hf = 0;
5834 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5835 rss_hf |= ETH_RSS_FRAG_IPV4;
5836 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5837 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5838 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5839 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5840 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5841 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5842 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5843 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5844 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5845 rss_hf |= ETH_RSS_FRAG_IPV6;
5846 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5847 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5848 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5849 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5850 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5851 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5852 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5853 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5854 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5855 rss_hf |= ETH_RSS_L2_PAYLOAD;
5862 i40e_pf_disable_rss(struct i40e_pf *pf)
5864 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5867 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5868 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5869 hena &= ~I40E_RSS_HENA_ALL;
5870 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5871 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5872 I40E_WRITE_FLUSH(hw);
5876 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5878 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5879 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5882 if (!key || key_len == 0) {
5883 PMD_DRV_LOG(DEBUG, "No key to be configured");
5885 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5887 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5891 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5892 struct i40e_aqc_get_set_rss_key_data *key_dw =
5893 (struct i40e_aqc_get_set_rss_key_data *)key;
5895 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5897 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5900 uint32_t *hash_key = (uint32_t *)key;
5903 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5904 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5905 I40E_WRITE_FLUSH(hw);
5912 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5914 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5915 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5918 if (!key || !key_len)
5921 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5922 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5923 (struct i40e_aqc_get_set_rss_key_data *)key);
5925 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5929 uint32_t *key_dw = (uint32_t *)key;
5932 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5933 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5935 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5941 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5943 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5948 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5949 rss_conf->rss_key_len);
5953 rss_hf = rss_conf->rss_hf;
5954 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5955 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5956 hena &= ~I40E_RSS_HENA_ALL;
5957 hena |= i40e_config_hena(rss_hf);
5958 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5959 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5960 I40E_WRITE_FLUSH(hw);
5966 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5967 struct rte_eth_rss_conf *rss_conf)
5969 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5970 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5974 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5975 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5976 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5977 if (rss_hf != 0) /* Enable RSS */
5979 return 0; /* Nothing to do */
5982 if (rss_hf == 0) /* Disable RSS */
5985 return i40e_hw_rss_hash_set(pf, rss_conf);
5989 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5990 struct rte_eth_rss_conf *rss_conf)
5992 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5993 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5997 &rss_conf->rss_key_len);
5999 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6000 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6001 rss_conf->rss_hf = i40e_parse_hena(hena);
6007 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6009 switch (filter_type) {
6010 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6011 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6013 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6014 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6016 case RTE_TUNNEL_FILTER_IMAC_TENID:
6017 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6019 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6020 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6022 case ETH_TUNNEL_FILTER_IMAC:
6023 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6025 case ETH_TUNNEL_FILTER_OIP:
6026 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6028 case ETH_TUNNEL_FILTER_IIP:
6029 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6032 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6040 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6041 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6046 uint8_t i, tun_type = 0;
6047 /* internal varialbe to convert ipv6 byte order */
6048 uint32_t convert_ipv6[4];
6050 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6051 struct i40e_vsi *vsi = pf->main_vsi;
6052 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6053 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6055 cld_filter = rte_zmalloc("tunnel_filter",
6056 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6059 if (NULL == cld_filter) {
6060 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6063 pfilter = cld_filter;
6065 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6066 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6068 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6069 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6070 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6071 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6072 rte_memcpy(&pfilter->ipaddr.v4.data,
6073 &rte_cpu_to_le_32(ipv4_addr),
6074 sizeof(pfilter->ipaddr.v4.data));
6076 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6077 for (i = 0; i < 4; i++) {
6079 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6081 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6082 sizeof(pfilter->ipaddr.v6.data));
6085 /* check tunneled type */
6086 switch (tunnel_filter->tunnel_type) {
6087 case RTE_TUNNEL_TYPE_VXLAN:
6088 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6090 case RTE_TUNNEL_TYPE_NVGRE:
6091 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6093 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6094 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6097 /* Other tunnel types is not supported. */
6098 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6099 rte_free(cld_filter);
6103 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6106 rte_free(cld_filter);
6110 pfilter->flags |= rte_cpu_to_le_16(
6111 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6112 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6113 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6114 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6117 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6119 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6122 rte_free(cld_filter);
6127 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6131 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6132 if (pf->vxlan_ports[i] == port)
6140 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6144 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6146 idx = i40e_get_vxlan_port_idx(pf, port);
6148 /* Check if port already exists */
6150 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6154 /* Now check if there is space to add the new port */
6155 idx = i40e_get_vxlan_port_idx(pf, 0);
6157 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6158 "not adding port %d", port);
6162 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6165 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6169 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6172 /* New port: add it and mark its index in the bitmap */
6173 pf->vxlan_ports[idx] = port;
6174 pf->vxlan_bitmap |= (1 << idx);
6176 if (!(pf->flags & I40E_FLAG_VXLAN))
6177 pf->flags |= I40E_FLAG_VXLAN;
6183 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6186 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6188 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6189 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6193 idx = i40e_get_vxlan_port_idx(pf, port);
6196 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6200 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6201 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6205 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6208 pf->vxlan_ports[idx] = 0;
6209 pf->vxlan_bitmap &= ~(1 << idx);
6211 if (!pf->vxlan_bitmap)
6212 pf->flags &= ~I40E_FLAG_VXLAN;
6217 /* Add UDP tunneling port */
6219 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6220 struct rte_eth_udp_tunnel *udp_tunnel)
6223 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6225 if (udp_tunnel == NULL)
6228 switch (udp_tunnel->prot_type) {
6229 case RTE_TUNNEL_TYPE_VXLAN:
6230 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6233 case RTE_TUNNEL_TYPE_GENEVE:
6234 case RTE_TUNNEL_TYPE_TEREDO:
6235 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6240 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6248 /* Remove UDP tunneling port */
6250 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6251 struct rte_eth_udp_tunnel *udp_tunnel)
6254 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6256 if (udp_tunnel == NULL)
6259 switch (udp_tunnel->prot_type) {
6260 case RTE_TUNNEL_TYPE_VXLAN:
6261 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6263 case RTE_TUNNEL_TYPE_GENEVE:
6264 case RTE_TUNNEL_TYPE_TEREDO:
6265 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6269 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6277 /* Calculate the maximum number of contiguous PF queues that are configured */
6279 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6281 struct rte_eth_dev_data *data = pf->dev_data;
6283 struct i40e_rx_queue *rxq;
6286 for (i = 0; i < pf->lan_nb_qps; i++) {
6287 rxq = data->rx_queues[i];
6288 if (rxq && rxq->q_set)
6299 i40e_pf_config_rss(struct i40e_pf *pf)
6301 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6302 struct rte_eth_rss_conf rss_conf;
6303 uint32_t i, lut = 0;
6307 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6308 * It's necessary to calulate the actual PF queues that are configured.
6310 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6311 num = i40e_pf_calc_configured_queues_num(pf);
6313 num = pf->dev_data->nb_rx_queues;
6315 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6316 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6320 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6324 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6327 lut = (lut << 8) | (j & ((0x1 <<
6328 hw->func_caps.rss_table_entry_width) - 1));
6330 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6333 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6334 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6335 i40e_pf_disable_rss(pf);
6338 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6339 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6340 /* Random default keys */
6341 static uint32_t rss_key_default[] = {0x6b793944,
6342 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6343 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6344 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6346 rss_conf.rss_key = (uint8_t *)rss_key_default;
6347 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6351 return i40e_hw_rss_hash_set(pf, &rss_conf);
6355 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6356 struct rte_eth_tunnel_filter_conf *filter)
6358 if (pf == NULL || filter == NULL) {
6359 PMD_DRV_LOG(ERR, "Invalid parameter");
6363 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6364 PMD_DRV_LOG(ERR, "Invalid queue ID");
6368 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6369 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6373 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6374 (is_zero_ether_addr(&filter->outer_mac))) {
6375 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6379 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6380 (is_zero_ether_addr(&filter->inner_mac))) {
6381 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6388 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6389 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6391 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6396 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6397 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6400 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6401 } else if (len == 4) {
6402 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6404 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6409 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6416 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6417 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6423 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6430 switch (cfg->cfg_type) {
6431 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6432 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6435 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6443 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6444 enum rte_filter_op filter_op,
6447 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6448 int ret = I40E_ERR_PARAM;
6450 switch (filter_op) {
6451 case RTE_ETH_FILTER_SET:
6452 ret = i40e_dev_global_config_set(hw,
6453 (struct rte_eth_global_cfg *)arg);
6456 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6464 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6465 enum rte_filter_op filter_op,
6468 struct rte_eth_tunnel_filter_conf *filter;
6469 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6470 int ret = I40E_SUCCESS;
6472 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6474 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6475 return I40E_ERR_PARAM;
6477 switch (filter_op) {
6478 case RTE_ETH_FILTER_NOP:
6479 if (!(pf->flags & I40E_FLAG_VXLAN))
6480 ret = I40E_NOT_SUPPORTED;
6482 case RTE_ETH_FILTER_ADD:
6483 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6485 case RTE_ETH_FILTER_DELETE:
6486 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6489 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6490 ret = I40E_ERR_PARAM;
6498 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6501 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6504 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6505 ret = i40e_pf_config_rss(pf);
6507 i40e_pf_disable_rss(pf);
6512 /* Get the symmetric hash enable configurations per port */
6514 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6516 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6518 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6521 /* Set the symmetric hash enable configurations per port */
6523 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6525 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6528 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6529 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6533 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6535 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6536 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6540 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6542 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6543 I40E_WRITE_FLUSH(hw);
6547 * Get global configurations of hash function type and symmetric hash enable
6548 * per flow type (pctype). Note that global configuration means it affects all
6549 * the ports on the same NIC.
6552 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6553 struct rte_eth_hash_global_conf *g_cfg)
6555 uint32_t reg, mask = I40E_FLOW_TYPES;
6557 enum i40e_filter_pctype pctype;
6559 memset(g_cfg, 0, sizeof(*g_cfg));
6560 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6561 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6562 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6564 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6565 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6566 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6568 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6569 if (!(mask & (1UL << i)))
6571 mask &= ~(1UL << i);
6572 /* Bit set indicats the coresponding flow type is supported */
6573 g_cfg->valid_bit_mask[0] |= (1UL << i);
6574 pctype = i40e_flowtype_to_pctype(i);
6575 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6576 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6577 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6584 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6587 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6589 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6590 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6591 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6592 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6598 * As i40e supports less than 32 flow types, only first 32 bits need to
6601 mask0 = g_cfg->valid_bit_mask[0];
6602 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6604 /* Check if any unsupported flow type configured */
6605 if ((mask0 | i40e_mask) ^ i40e_mask)
6608 if (g_cfg->valid_bit_mask[i])
6616 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6622 * Set global configurations of hash function type and symmetric hash enable
6623 * per flow type (pctype). Note any modifying global configuration will affect
6624 * all the ports on the same NIC.
6627 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6628 struct rte_eth_hash_global_conf *g_cfg)
6633 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6634 enum i40e_filter_pctype pctype;
6636 /* Check the input parameters */
6637 ret = i40e_hash_global_config_check(g_cfg);
6641 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6642 if (!(mask0 & (1UL << i)))
6644 mask0 &= ~(1UL << i);
6645 pctype = i40e_flowtype_to_pctype(i);
6646 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6647 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6648 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6651 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6652 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6654 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6655 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6659 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6660 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6662 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6663 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6667 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6669 /* Use the default, and keep it as it is */
6672 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6675 I40E_WRITE_FLUSH(hw);
6681 * Valid input sets for hash and flow director filters per PCTYPE
6684 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6685 enum rte_filter_type filter)
6689 static const uint64_t valid_hash_inset_table[] = {
6690 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6691 I40E_INSET_DMAC | I40E_INSET_SMAC |
6692 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6693 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6694 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6695 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6696 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6697 I40E_INSET_FLEX_PAYLOAD,
6698 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6699 I40E_INSET_DMAC | I40E_INSET_SMAC |
6700 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6701 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6702 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6703 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6704 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6705 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6706 I40E_INSET_FLEX_PAYLOAD,
6707 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6708 I40E_INSET_DMAC | I40E_INSET_SMAC |
6709 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6710 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6711 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6712 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6713 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6714 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6715 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6716 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6717 I40E_INSET_DMAC | I40E_INSET_SMAC |
6718 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6719 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6720 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6721 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6722 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6723 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6724 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6725 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6726 I40E_INSET_DMAC | I40E_INSET_SMAC |
6727 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6728 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6729 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6730 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6731 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6732 I40E_INSET_FLEX_PAYLOAD,
6733 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6734 I40E_INSET_DMAC | I40E_INSET_SMAC |
6735 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6736 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6737 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6738 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6739 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6740 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6741 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6742 I40E_INSET_DMAC | I40E_INSET_SMAC |
6743 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6744 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6745 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6746 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6747 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6748 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6749 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6750 I40E_INSET_DMAC | I40E_INSET_SMAC |
6751 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6752 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6753 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6754 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6755 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6756 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6757 I40E_INSET_FLEX_PAYLOAD,
6758 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6759 I40E_INSET_DMAC | I40E_INSET_SMAC |
6760 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6761 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6762 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6763 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6764 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6765 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6766 I40E_INSET_FLEX_PAYLOAD,
6767 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6768 I40E_INSET_DMAC | I40E_INSET_SMAC |
6769 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6770 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6771 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6772 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6773 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6774 I40E_INSET_FLEX_PAYLOAD,
6775 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6776 I40E_INSET_DMAC | I40E_INSET_SMAC |
6777 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6778 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6779 I40E_INSET_FLEX_PAYLOAD,
6783 * Flow director supports only fields defined in
6784 * union rte_eth_fdir_flow.
6786 static const uint64_t valid_fdir_inset_table[] = {
6787 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6788 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6789 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6790 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6791 I40E_INSET_IPV4_TTL,
6792 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6793 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6794 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6795 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6796 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6797 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6798 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6799 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6800 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6801 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6802 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6803 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6804 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6805 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6806 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6808 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6809 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6810 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6811 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6812 I40E_INSET_IPV4_TTL,
6813 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6814 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6815 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6816 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6817 I40E_INSET_IPV6_HOP_LIMIT,
6818 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6819 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6820 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6821 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6822 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6823 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6824 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6825 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6826 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6827 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6828 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6829 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6830 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6831 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6832 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6834 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6835 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6836 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6837 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6838 I40E_INSET_IPV6_HOP_LIMIT,
6839 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6840 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6841 I40E_INSET_LAST_ETHER_TYPE,
6844 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6846 if (filter == RTE_ETH_FILTER_HASH)
6847 valid = valid_hash_inset_table[pctype];
6849 valid = valid_fdir_inset_table[pctype];
6855 * Validate if the input set is allowed for a specific PCTYPE
6858 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6859 enum rte_filter_type filter, uint64_t inset)
6863 valid = i40e_get_valid_input_set(pctype, filter);
6864 if (inset & (~valid))
6870 /* default input set fields combination per pctype */
6872 i40e_get_default_input_set(uint16_t pctype)
6874 static const uint64_t default_inset_table[] = {
6875 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6876 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6877 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6878 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6879 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6880 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6881 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6882 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6883 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6884 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6885 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6887 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6888 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6889 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6890 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6891 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6892 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6893 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6894 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6895 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6896 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6897 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6898 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6899 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6901 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6902 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6903 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6904 I40E_INSET_LAST_ETHER_TYPE,
6907 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6910 return default_inset_table[pctype];
6914 * Parse the input set from index to logical bit masks
6917 i40e_parse_input_set(uint64_t *inset,
6918 enum i40e_filter_pctype pctype,
6919 enum rte_eth_input_set_field *field,
6925 static const struct {
6926 enum rte_eth_input_set_field field;
6928 } inset_convert_table[] = {
6929 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6930 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6931 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6932 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6933 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6934 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6935 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6936 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6937 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6938 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6939 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6940 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6941 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6942 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6943 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6944 I40E_INSET_IPV6_NEXT_HDR},
6945 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
6946 I40E_INSET_IPV6_HOP_LIMIT},
6947 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6948 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6949 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6950 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6951 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6952 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6953 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6954 I40E_INSET_SCTP_VT},
6955 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6956 I40E_INSET_TUNNEL_DMAC},
6957 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6958 I40E_INSET_VLAN_TUNNEL},
6959 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6960 I40E_INSET_TUNNEL_ID},
6961 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6962 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6963 I40E_INSET_FLEX_PAYLOAD_W1},
6964 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6965 I40E_INSET_FLEX_PAYLOAD_W2},
6966 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6967 I40E_INSET_FLEX_PAYLOAD_W3},
6968 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6969 I40E_INSET_FLEX_PAYLOAD_W4},
6970 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6971 I40E_INSET_FLEX_PAYLOAD_W5},
6972 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6973 I40E_INSET_FLEX_PAYLOAD_W6},
6974 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6975 I40E_INSET_FLEX_PAYLOAD_W7},
6976 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6977 I40E_INSET_FLEX_PAYLOAD_W8},
6980 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6983 /* Only one item allowed for default or all */
6985 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6986 *inset = i40e_get_default_input_set(pctype);
6988 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6989 *inset = I40E_INSET_NONE;
6994 for (i = 0, *inset = 0; i < size; i++) {
6995 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6996 if (field[i] == inset_convert_table[j].field) {
6997 *inset |= inset_convert_table[j].inset;
7002 /* It contains unsupported input set, return immediately */
7003 if (j == RTE_DIM(inset_convert_table))
7011 * Translate the input set from bit masks to register aware bit masks
7015 i40e_translate_input_set_reg(uint64_t input)
7020 static const struct {
7024 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7025 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7026 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7027 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7028 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7029 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7030 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7031 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7032 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7033 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7034 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7035 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7036 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7037 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7038 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7039 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7040 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7041 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7042 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7043 {I40E_INSET_TUNNEL_DMAC,
7044 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7045 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7046 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7047 {I40E_INSET_TUNNEL_SRC_PORT,
7048 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7049 {I40E_INSET_TUNNEL_DST_PORT,
7050 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7051 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7052 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7053 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7054 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7055 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7056 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7057 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7058 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7059 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7065 /* Translate input set to register aware inset */
7066 for (i = 0; i < RTE_DIM(inset_map); i++) {
7067 if (input & inset_map[i].inset)
7068 val |= inset_map[i].inset_reg;
7075 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7078 uint64_t inset_need_mask = inset;
7080 static const struct {
7083 } inset_mask_map[] = {
7084 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7085 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7086 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7087 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7088 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7089 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7090 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7091 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7094 if (!inset || !mask || !nb_elem)
7097 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7098 /* Clear the inset bit, if no MASK is required,
7099 * for example proto + ttl
7101 if ((inset & inset_mask_map[i].inset) ==
7102 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7103 inset_need_mask &= ~inset_mask_map[i].inset;
7104 if (!inset_need_mask)
7107 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7108 if ((inset_need_mask & inset_mask_map[i].inset) ==
7109 inset_mask_map[i].inset) {
7110 if (idx >= nb_elem) {
7111 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7114 mask[idx] = inset_mask_map[i].mask;
7123 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7125 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7127 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7129 i40e_write_rx_ctl(hw, addr, val);
7130 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7131 (uint32_t)i40e_read_rx_ctl(hw, addr));
7135 i40e_filter_input_set_init(struct i40e_pf *pf)
7137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7138 enum i40e_filter_pctype pctype;
7139 uint64_t input_set, inset_reg;
7140 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7143 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7144 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7145 if (!I40E_VALID_PCTYPE(pctype))
7147 input_set = i40e_get_default_input_set(pctype);
7149 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7150 I40E_INSET_MASK_NUM_REG);
7153 inset_reg = i40e_translate_input_set_reg(input_set);
7155 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7156 (uint32_t)(inset_reg & UINT32_MAX));
7157 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7158 (uint32_t)((inset_reg >>
7159 I40E_32_BIT_WIDTH) & UINT32_MAX));
7160 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7161 (uint32_t)(inset_reg & UINT32_MAX));
7162 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7163 (uint32_t)((inset_reg >>
7164 I40E_32_BIT_WIDTH) & UINT32_MAX));
7166 for (i = 0; i < num; i++) {
7167 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7169 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7172 /*clear unused mask registers of the pctype */
7173 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7174 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7176 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7179 I40E_WRITE_FLUSH(hw);
7181 /* store the default input set */
7182 pf->hash_input_set[pctype] = input_set;
7183 pf->fdir.input_set[pctype] = input_set;
7188 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7189 struct rte_eth_input_set_conf *conf)
7191 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7192 enum i40e_filter_pctype pctype;
7193 uint64_t input_set, inset_reg = 0;
7194 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7198 PMD_DRV_LOG(ERR, "Invalid pointer");
7201 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7202 conf->op != RTE_ETH_INPUT_SET_ADD) {
7203 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7207 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7208 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7209 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7214 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7217 PMD_DRV_LOG(ERR, "Failed to parse input set");
7220 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7222 PMD_DRV_LOG(ERR, "Invalid input set");
7225 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7226 /* get inset value in register */
7227 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7228 inset_reg <<= I40E_32_BIT_WIDTH;
7229 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7230 input_set |= pf->hash_input_set[pctype];
7232 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7233 I40E_INSET_MASK_NUM_REG);
7237 inset_reg |= i40e_translate_input_set_reg(input_set);
7239 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7240 (uint32_t)(inset_reg & UINT32_MAX));
7241 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7242 (uint32_t)((inset_reg >>
7243 I40E_32_BIT_WIDTH) & UINT32_MAX));
7245 for (i = 0; i < num; i++)
7246 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7248 /*clear unused mask registers of the pctype */
7249 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7250 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7252 I40E_WRITE_FLUSH(hw);
7254 pf->hash_input_set[pctype] = input_set;
7259 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7260 struct rte_eth_input_set_conf *conf)
7262 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7263 enum i40e_filter_pctype pctype;
7264 uint64_t input_set, inset_reg = 0;
7265 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7269 PMD_DRV_LOG(ERR, "Invalid pointer");
7272 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7273 conf->op != RTE_ETH_INPUT_SET_ADD) {
7274 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7278 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7279 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7280 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7284 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7287 PMD_DRV_LOG(ERR, "Failed to parse input set");
7290 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7292 PMD_DRV_LOG(ERR, "Invalid input set");
7296 /* get inset value in register */
7297 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7298 inset_reg <<= I40E_32_BIT_WIDTH;
7299 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7301 /* Can not change the inset reg for flex payload for fdir,
7302 * it is done by writing I40E_PRTQF_FD_FLXINSET
7303 * in i40e_set_flex_mask_on_pctype.
7305 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7306 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7308 input_set |= pf->fdir.input_set[pctype];
7309 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7310 I40E_INSET_MASK_NUM_REG);
7314 inset_reg |= i40e_translate_input_set_reg(input_set);
7316 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7317 (uint32_t)(inset_reg & UINT32_MAX));
7318 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7319 (uint32_t)((inset_reg >>
7320 I40E_32_BIT_WIDTH) & UINT32_MAX));
7322 for (i = 0; i < num; i++)
7323 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7325 /*clear unused mask registers of the pctype */
7326 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7327 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7329 I40E_WRITE_FLUSH(hw);
7331 pf->fdir.input_set[pctype] = input_set;
7336 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7341 PMD_DRV_LOG(ERR, "Invalid pointer");
7345 switch (info->info_type) {
7346 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7347 i40e_get_symmetric_hash_enable_per_port(hw,
7348 &(info->info.enable));
7350 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7351 ret = i40e_get_hash_filter_global_config(hw,
7352 &(info->info.global_conf));
7355 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7365 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7370 PMD_DRV_LOG(ERR, "Invalid pointer");
7374 switch (info->info_type) {
7375 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7376 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7378 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7379 ret = i40e_set_hash_filter_global_config(hw,
7380 &(info->info.global_conf));
7382 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7383 ret = i40e_hash_filter_inset_select(hw,
7384 &(info->info.input_set_conf));
7388 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7397 /* Operations for hash function */
7399 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7400 enum rte_filter_op filter_op,
7403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7406 switch (filter_op) {
7407 case RTE_ETH_FILTER_NOP:
7409 case RTE_ETH_FILTER_GET:
7410 ret = i40e_hash_filter_get(hw,
7411 (struct rte_eth_hash_filter_info *)arg);
7413 case RTE_ETH_FILTER_SET:
7414 ret = i40e_hash_filter_set(hw,
7415 (struct rte_eth_hash_filter_info *)arg);
7418 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7428 * Configure ethertype filter, which can director packet by filtering
7429 * with mac address and ether_type or only ether_type
7432 i40e_ethertype_filter_set(struct i40e_pf *pf,
7433 struct rte_eth_ethertype_filter *filter,
7436 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7437 struct i40e_control_filter_stats stats;
7441 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7442 PMD_DRV_LOG(ERR, "Invalid queue ID");
7445 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7446 filter->ether_type == ETHER_TYPE_IPv6) {
7447 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7448 " control packet filter.", filter->ether_type);
7451 if (filter->ether_type == ETHER_TYPE_VLAN)
7452 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7455 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7456 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7457 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7458 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7459 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7461 memset(&stats, 0, sizeof(stats));
7462 ret = i40e_aq_add_rem_control_packet_filter(hw,
7463 filter->mac_addr.addr_bytes,
7464 filter->ether_type, flags,
7466 filter->queue, add, &stats, NULL);
7468 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7469 " mac_etype_used = %u, etype_used = %u,"
7470 " mac_etype_free = %u, etype_free = %u\n",
7471 ret, stats.mac_etype_used, stats.etype_used,
7472 stats.mac_etype_free, stats.etype_free);
7479 * Handle operations for ethertype filter.
7482 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7483 enum rte_filter_op filter_op,
7486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7489 if (filter_op == RTE_ETH_FILTER_NOP)
7493 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7498 switch (filter_op) {
7499 case RTE_ETH_FILTER_ADD:
7500 ret = i40e_ethertype_filter_set(pf,
7501 (struct rte_eth_ethertype_filter *)arg,
7504 case RTE_ETH_FILTER_DELETE:
7505 ret = i40e_ethertype_filter_set(pf,
7506 (struct rte_eth_ethertype_filter *)arg,
7510 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7518 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7519 enum rte_filter_type filter_type,
7520 enum rte_filter_op filter_op,
7528 switch (filter_type) {
7529 case RTE_ETH_FILTER_NONE:
7530 /* For global configuration */
7531 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7533 case RTE_ETH_FILTER_HASH:
7534 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7536 case RTE_ETH_FILTER_MACVLAN:
7537 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7539 case RTE_ETH_FILTER_ETHERTYPE:
7540 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7542 case RTE_ETH_FILTER_TUNNEL:
7543 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7545 case RTE_ETH_FILTER_FDIR:
7546 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7549 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7559 * Check and enable Extended Tag.
7560 * Enabling Extended Tag is important for 40G performance.
7563 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7568 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7571 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7575 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7576 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7581 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7584 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7588 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7589 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7592 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7593 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7596 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7603 * As some registers wouldn't be reset unless a global hardware reset,
7604 * hardware initialization is needed to put those registers into an
7605 * expected initial state.
7608 i40e_hw_init(struct rte_eth_dev *dev)
7610 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7612 i40e_enable_extended_tag(dev);
7614 /* clear the PF Queue Filter control register */
7615 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7617 /* Disable symmetric hash per port */
7618 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7621 enum i40e_filter_pctype
7622 i40e_flowtype_to_pctype(uint16_t flow_type)
7624 static const enum i40e_filter_pctype pctype_table[] = {
7625 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7626 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7627 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7628 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7629 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7630 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7631 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7632 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7633 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7634 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7635 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7636 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7637 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7638 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7639 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7640 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7641 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7642 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7643 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7646 return pctype_table[flow_type];
7650 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7652 static const uint16_t flowtype_table[] = {
7653 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7654 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7655 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7656 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7657 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7658 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7659 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7660 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7661 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7662 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7663 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7664 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7665 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7666 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7667 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7668 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7669 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7670 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7671 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7674 return flowtype_table[pctype];
7678 * On X710, performance number is far from the expectation on recent firmware
7679 * versions; on XL710, performance number is also far from the expectation on
7680 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7681 * mode is enabled and port MAC address is equal to the packet destination MAC
7682 * address. The fix for this issue may not be integrated in the following
7683 * firmware version. So the workaround in software driver is needed. It needs
7684 * to modify the initial values of 3 internal only registers for both X710 and
7685 * XL710. Note that the values for X710 or XL710 could be different, and the
7686 * workaround can be removed when it is fixed in firmware in the future.
7689 /* For both X710 and XL710 */
7690 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7691 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7693 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7694 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7697 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7699 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7700 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7703 i40e_configure_registers(struct i40e_hw *hw)
7709 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7710 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7711 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7717 for (i = 0; i < RTE_DIM(reg_table); i++) {
7718 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7719 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7721 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7724 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7727 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7730 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7734 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7735 reg_table[i].addr, reg);
7736 if (reg == reg_table[i].val)
7739 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7740 reg_table[i].val, NULL);
7742 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7743 "address of 0x%"PRIx32, reg_table[i].val,
7747 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7748 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7752 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7753 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7754 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7755 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7757 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7762 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7763 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7767 /* Configure for double VLAN RX stripping */
7768 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7769 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7770 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7771 ret = i40e_aq_debug_write_register(hw,
7772 I40E_VSI_TSR(vsi->vsi_id),
7775 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7777 return I40E_ERR_CONFIG;
7781 /* Configure for double VLAN TX insertion */
7782 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7783 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7784 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7785 ret = i40e_aq_debug_write_register(hw,
7786 I40E_VSI_L2TAGSTXVALID(
7787 vsi->vsi_id), reg, NULL);
7789 PMD_DRV_LOG(ERR, "Failed to update "
7790 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7791 return I40E_ERR_CONFIG;
7799 * i40e_aq_add_mirror_rule
7800 * @hw: pointer to the hardware structure
7801 * @seid: VEB seid to add mirror rule to
7802 * @dst_id: destination vsi seid
7803 * @entries: Buffer which contains the entities to be mirrored
7804 * @count: number of entities contained in the buffer
7805 * @rule_id:the rule_id of the rule to be added
7807 * Add a mirror rule for a given veb.
7810 static enum i40e_status_code
7811 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7812 uint16_t seid, uint16_t dst_id,
7813 uint16_t rule_type, uint16_t *entries,
7814 uint16_t count, uint16_t *rule_id)
7816 struct i40e_aq_desc desc;
7817 struct i40e_aqc_add_delete_mirror_rule cmd;
7818 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7819 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7822 enum i40e_status_code status;
7824 i40e_fill_default_direct_cmd_desc(&desc,
7825 i40e_aqc_opc_add_mirror_rule);
7826 memset(&cmd, 0, sizeof(cmd));
7828 buff_len = sizeof(uint16_t) * count;
7829 desc.datalen = rte_cpu_to_le_16(buff_len);
7831 desc.flags |= rte_cpu_to_le_16(
7832 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7833 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7834 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7835 cmd.num_entries = rte_cpu_to_le_16(count);
7836 cmd.seid = rte_cpu_to_le_16(seid);
7837 cmd.destination = rte_cpu_to_le_16(dst_id);
7839 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7840 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7841 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7843 " mirror_rules_used = %u, mirror_rules_free = %u,",
7844 hw->aq.asq_last_status, resp->rule_id,
7845 resp->mirror_rules_used, resp->mirror_rules_free);
7846 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7852 * i40e_aq_del_mirror_rule
7853 * @hw: pointer to the hardware structure
7854 * @seid: VEB seid to add mirror rule to
7855 * @entries: Buffer which contains the entities to be mirrored
7856 * @count: number of entities contained in the buffer
7857 * @rule_id:the rule_id of the rule to be delete
7859 * Delete a mirror rule for a given veb.
7862 static enum i40e_status_code
7863 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7864 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7865 uint16_t count, uint16_t rule_id)
7867 struct i40e_aq_desc desc;
7868 struct i40e_aqc_add_delete_mirror_rule cmd;
7869 uint16_t buff_len = 0;
7870 enum i40e_status_code status;
7873 i40e_fill_default_direct_cmd_desc(&desc,
7874 i40e_aqc_opc_delete_mirror_rule);
7875 memset(&cmd, 0, sizeof(cmd));
7876 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7877 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7879 cmd.num_entries = count;
7880 buff_len = sizeof(uint16_t) * count;
7881 desc.datalen = rte_cpu_to_le_16(buff_len);
7882 buff = (void *)entries;
7884 /* rule id is filled in destination field for deleting mirror rule */
7885 cmd.destination = rte_cpu_to_le_16(rule_id);
7887 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7888 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7889 cmd.seid = rte_cpu_to_le_16(seid);
7891 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7892 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7898 * i40e_mirror_rule_set
7899 * @dev: pointer to the hardware structure
7900 * @mirror_conf: mirror rule info
7901 * @sw_id: mirror rule's sw_id
7902 * @on: enable/disable
7904 * set a mirror rule.
7908 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7909 struct rte_eth_mirror_conf *mirror_conf,
7910 uint8_t sw_id, uint8_t on)
7912 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7914 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7915 struct i40e_mirror_rule *parent = NULL;
7916 uint16_t seid, dst_seid, rule_id;
7920 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7922 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7923 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7924 " without veb or vfs.");
7927 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7928 PMD_DRV_LOG(ERR, "mirror table is full.");
7931 if (mirror_conf->dst_pool > pf->vf_num) {
7932 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7933 mirror_conf->dst_pool);
7937 seid = pf->main_vsi->veb->seid;
7939 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7940 if (sw_id <= it->index) {
7946 if (mirr_rule && sw_id == mirr_rule->index) {
7948 PMD_DRV_LOG(ERR, "mirror rule exists.");
7951 ret = i40e_aq_del_mirror_rule(hw, seid,
7952 mirr_rule->rule_type,
7954 mirr_rule->num_entries, mirr_rule->id);
7956 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7957 " ret = %d, aq_err = %d.",
7958 ret, hw->aq.asq_last_status);
7961 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7962 rte_free(mirr_rule);
7963 pf->nb_mirror_rule--;
7967 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7971 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7972 sizeof(struct i40e_mirror_rule) , 0);
7974 PMD_DRV_LOG(ERR, "failed to allocate memory");
7975 return I40E_ERR_NO_MEMORY;
7977 switch (mirror_conf->rule_type) {
7978 case ETH_MIRROR_VLAN:
7979 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7980 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7981 mirr_rule->entries[j] =
7982 mirror_conf->vlan.vlan_id[i];
7987 PMD_DRV_LOG(ERR, "vlan is not specified.");
7988 rte_free(mirr_rule);
7991 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7993 case ETH_MIRROR_VIRTUAL_POOL_UP:
7994 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7995 /* check if the specified pool bit is out of range */
7996 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7997 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7998 rte_free(mirr_rule);
8001 for (i = 0, j = 0; i < pf->vf_num; i++) {
8002 if (mirror_conf->pool_mask & (1ULL << i)) {
8003 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8007 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8008 /* add pf vsi to entries */
8009 mirr_rule->entries[j] = pf->main_vsi_seid;
8013 PMD_DRV_LOG(ERR, "pool is not specified.");
8014 rte_free(mirr_rule);
8017 /* egress and ingress in aq commands means from switch but not port */
8018 mirr_rule->rule_type =
8019 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8020 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8021 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8023 case ETH_MIRROR_UPLINK_PORT:
8024 /* egress and ingress in aq commands means from switch but not port*/
8025 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8027 case ETH_MIRROR_DOWNLINK_PORT:
8028 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8031 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8032 mirror_conf->rule_type);
8033 rte_free(mirr_rule);
8037 /* If the dst_pool is equal to vf_num, consider it as PF */
8038 if (mirror_conf->dst_pool == pf->vf_num)
8039 dst_seid = pf->main_vsi_seid;
8041 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8043 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8044 mirr_rule->rule_type, mirr_rule->entries,
8047 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8048 " ret = %d, aq_err = %d.",
8049 ret, hw->aq.asq_last_status);
8050 rte_free(mirr_rule);
8054 mirr_rule->index = sw_id;
8055 mirr_rule->num_entries = j;
8056 mirr_rule->id = rule_id;
8057 mirr_rule->dst_vsi_seid = dst_seid;
8060 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8062 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8064 pf->nb_mirror_rule++;
8069 * i40e_mirror_rule_reset
8070 * @dev: pointer to the device
8071 * @sw_id: mirror rule's sw_id
8073 * reset a mirror rule.
8077 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8080 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8081 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8085 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8087 seid = pf->main_vsi->veb->seid;
8089 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8090 if (sw_id == it->index) {
8096 ret = i40e_aq_del_mirror_rule(hw, seid,
8097 mirr_rule->rule_type,
8099 mirr_rule->num_entries, mirr_rule->id);
8101 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8102 " status = %d, aq_err = %d.",
8103 ret, hw->aq.asq_last_status);
8106 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8107 rte_free(mirr_rule);
8108 pf->nb_mirror_rule--;
8110 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8117 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8119 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120 uint64_t systim_cycles;
8122 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8123 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8126 return systim_cycles;
8130 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8135 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8136 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8143 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8145 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8148 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8149 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8156 i40e_start_timecounters(struct rte_eth_dev *dev)
8158 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8159 struct i40e_adapter *adapter =
8160 (struct i40e_adapter *)dev->data->dev_private;
8161 struct rte_eth_link link;
8162 uint32_t tsync_inc_l;
8163 uint32_t tsync_inc_h;
8165 /* Get current link speed. */
8166 memset(&link, 0, sizeof(link));
8167 i40e_dev_link_update(dev, 1);
8168 rte_i40e_dev_atomic_read_link_status(dev, &link);
8170 switch (link.link_speed) {
8171 case ETH_SPEED_NUM_40G:
8172 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8173 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8175 case ETH_SPEED_NUM_10G:
8176 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8177 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8179 case ETH_SPEED_NUM_1G:
8180 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8181 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8188 /* Set the timesync increment value. */
8189 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8190 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8192 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8193 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8194 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8196 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8197 adapter->systime_tc.cc_shift = 0;
8198 adapter->systime_tc.nsec_mask = 0;
8200 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8201 adapter->rx_tstamp_tc.cc_shift = 0;
8202 adapter->rx_tstamp_tc.nsec_mask = 0;
8204 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8205 adapter->tx_tstamp_tc.cc_shift = 0;
8206 adapter->tx_tstamp_tc.nsec_mask = 0;
8210 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8212 struct i40e_adapter *adapter =
8213 (struct i40e_adapter *)dev->data->dev_private;
8215 adapter->systime_tc.nsec += delta;
8216 adapter->rx_tstamp_tc.nsec += delta;
8217 adapter->tx_tstamp_tc.nsec += delta;
8223 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8226 struct i40e_adapter *adapter =
8227 (struct i40e_adapter *)dev->data->dev_private;
8229 ns = rte_timespec_to_ns(ts);
8231 /* Set the timecounters to a new value. */
8232 adapter->systime_tc.nsec = ns;
8233 adapter->rx_tstamp_tc.nsec = ns;
8234 adapter->tx_tstamp_tc.nsec = ns;
8240 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8242 uint64_t ns, systime_cycles;
8243 struct i40e_adapter *adapter =
8244 (struct i40e_adapter *)dev->data->dev_private;
8246 systime_cycles = i40e_read_systime_cyclecounter(dev);
8247 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8248 *ts = rte_ns_to_timespec(ns);
8254 i40e_timesync_enable(struct rte_eth_dev *dev)
8256 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8257 uint32_t tsync_ctl_l;
8258 uint32_t tsync_ctl_h;
8260 /* Stop the timesync system time. */
8261 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8262 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8263 /* Reset the timesync system time value. */
8264 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8265 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8267 i40e_start_timecounters(dev);
8269 /* Clear timesync registers. */
8270 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8271 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8272 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8273 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8274 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8275 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8277 /* Enable timestamping of PTP packets. */
8278 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8279 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8281 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8282 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8283 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8285 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8286 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8292 i40e_timesync_disable(struct rte_eth_dev *dev)
8294 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8295 uint32_t tsync_ctl_l;
8296 uint32_t tsync_ctl_h;
8298 /* Disable timestamping of transmitted PTP packets. */
8299 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8300 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8302 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8303 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8305 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8306 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8308 /* Reset the timesync increment value. */
8309 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8310 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8316 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8317 struct timespec *timestamp, uint32_t flags)
8319 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8320 struct i40e_adapter *adapter =
8321 (struct i40e_adapter *)dev->data->dev_private;
8323 uint32_t sync_status;
8324 uint32_t index = flags & 0x03;
8325 uint64_t rx_tstamp_cycles;
8328 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8329 if ((sync_status & (1 << index)) == 0)
8332 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8333 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8334 *timestamp = rte_ns_to_timespec(ns);
8340 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8341 struct timespec *timestamp)
8343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8344 struct i40e_adapter *adapter =
8345 (struct i40e_adapter *)dev->data->dev_private;
8347 uint32_t sync_status;
8348 uint64_t tx_tstamp_cycles;
8351 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8352 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8355 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8356 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8357 *timestamp = rte_ns_to_timespec(ns);
8363 * i40e_parse_dcb_configure - parse dcb configure from user
8364 * @dev: the device being configured
8365 * @dcb_cfg: pointer of the result of parse
8366 * @*tc_map: bit map of enabled traffic classes
8368 * Returns 0 on success, negative value on failure
8371 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8372 struct i40e_dcbx_config *dcb_cfg,
8375 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8376 uint8_t i, tc_bw, bw_lf;
8378 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8380 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8381 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8382 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8386 /* assume each tc has the same bw */
8387 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8388 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8389 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8390 /* to ensure the sum of tcbw is equal to 100 */
8391 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8392 for (i = 0; i < bw_lf; i++)
8393 dcb_cfg->etscfg.tcbwtable[i]++;
8395 /* assume each tc has the same Transmission Selection Algorithm */
8396 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8397 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8399 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8400 dcb_cfg->etscfg.prioritytable[i] =
8401 dcb_rx_conf->dcb_tc[i];
8403 /* FW needs one App to configure HW */
8404 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8405 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8406 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8407 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8409 if (dcb_rx_conf->nb_tcs == 0)
8410 *tc_map = 1; /* tc0 only */
8412 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8414 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8415 dcb_cfg->pfc.willing = 0;
8416 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8417 dcb_cfg->pfc.pfcenable = *tc_map;
8423 static enum i40e_status_code
8424 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8425 struct i40e_aqc_vsi_properties_data *info,
8426 uint8_t enabled_tcmap)
8428 enum i40e_status_code ret;
8429 int i, total_tc = 0;
8430 uint16_t qpnum_per_tc, bsf, qp_idx;
8431 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8432 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8433 uint16_t used_queues;
8435 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8436 if (ret != I40E_SUCCESS)
8439 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8440 if (enabled_tcmap & (1 << i))
8445 vsi->enabled_tc = enabled_tcmap;
8447 /* different VSI has different queues assigned */
8448 if (vsi->type == I40E_VSI_MAIN)
8449 used_queues = dev_data->nb_rx_queues -
8450 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8451 else if (vsi->type == I40E_VSI_VMDQ2)
8452 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8454 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8455 return I40E_ERR_NO_AVAILABLE_VSI;
8458 qpnum_per_tc = used_queues / total_tc;
8459 /* Number of queues per enabled TC */
8460 if (qpnum_per_tc == 0) {
8461 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8462 return I40E_ERR_INVALID_QP_ID;
8464 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8466 bsf = rte_bsf32(qpnum_per_tc);
8469 * Configure TC and queue mapping parameters, for enabled TC,
8470 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8471 * default queue will serve it.
8474 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8475 if (vsi->enabled_tc & (1 << i)) {
8476 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8477 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8478 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8479 qp_idx += qpnum_per_tc;
8481 info->tc_mapping[i] = 0;
8484 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8485 if (vsi->type == I40E_VSI_SRIOV) {
8486 info->mapping_flags |=
8487 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8488 for (i = 0; i < vsi->nb_qps; i++)
8489 info->queue_mapping[i] =
8490 rte_cpu_to_le_16(vsi->base_queue + i);
8492 info->mapping_flags |=
8493 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8494 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8496 info->valid_sections |=
8497 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8499 return I40E_SUCCESS;
8503 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8504 * @veb: VEB to be configured
8505 * @tc_map: enabled TC bitmap
8507 * Returns 0 on success, negative value on failure
8509 static enum i40e_status_code
8510 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8512 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8513 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8514 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8515 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8516 enum i40e_status_code ret = I40E_SUCCESS;
8520 /* Check if enabled_tc is same as existing or new TCs */
8521 if (veb->enabled_tc == tc_map)
8524 /* configure tc bandwidth */
8525 memset(&veb_bw, 0, sizeof(veb_bw));
8526 veb_bw.tc_valid_bits = tc_map;
8527 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8528 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8529 if (tc_map & BIT_ULL(i))
8530 veb_bw.tc_bw_share_credits[i] = 1;
8532 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8535 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8536 " per TC failed = %d",
8537 hw->aq.asq_last_status);
8541 memset(&ets_query, 0, sizeof(ets_query));
8542 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8544 if (ret != I40E_SUCCESS) {
8545 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8546 " configuration %u", hw->aq.asq_last_status);
8549 memset(&bw_query, 0, sizeof(bw_query));
8550 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8552 if (ret != I40E_SUCCESS) {
8553 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8554 " configuration %u", hw->aq.asq_last_status);
8558 /* store and print out BW info */
8559 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8560 veb->bw_info.bw_max = ets_query.tc_bw_max;
8561 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8562 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8563 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8564 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8566 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8567 veb->bw_info.bw_ets_share_credits[i] =
8568 bw_query.tc_bw_share_credits[i];
8569 veb->bw_info.bw_ets_credits[i] =
8570 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8571 /* 4 bits per TC, 4th bit is reserved */
8572 veb->bw_info.bw_ets_max[i] =
8573 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8574 RTE_LEN2MASK(3, uint8_t));
8575 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8576 veb->bw_info.bw_ets_share_credits[i]);
8577 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8578 veb->bw_info.bw_ets_credits[i]);
8579 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8580 veb->bw_info.bw_ets_max[i]);
8583 veb->enabled_tc = tc_map;
8590 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8591 * @vsi: VSI to be configured
8592 * @tc_map: enabled TC bitmap
8594 * Returns 0 on success, negative value on failure
8596 static enum i40e_status_code
8597 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8599 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8600 struct i40e_vsi_context ctxt;
8601 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8602 enum i40e_status_code ret = I40E_SUCCESS;
8605 /* Check if enabled_tc is same as existing or new TCs */
8606 if (vsi->enabled_tc == tc_map)
8609 /* configure tc bandwidth */
8610 memset(&bw_data, 0, sizeof(bw_data));
8611 bw_data.tc_valid_bits = tc_map;
8612 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8613 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8614 if (tc_map & BIT_ULL(i))
8615 bw_data.tc_bw_credits[i] = 1;
8617 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8619 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8620 " per TC failed = %d",
8621 hw->aq.asq_last_status);
8624 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8625 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8627 /* Update Queue Pairs Mapping for currently enabled UPs */
8628 ctxt.seid = vsi->seid;
8629 ctxt.pf_num = hw->pf_id;
8631 ctxt.uplink_seid = vsi->uplink_seid;
8632 ctxt.info = vsi->info;
8634 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8638 /* Update the VSI after updating the VSI queue-mapping information */
8639 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8641 PMD_INIT_LOG(ERR, "Failed to configure "
8642 "TC queue mapping = %d",
8643 hw->aq.asq_last_status);
8646 /* update the local VSI info with updated queue map */
8647 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8648 sizeof(vsi->info.tc_mapping));
8649 (void)rte_memcpy(&vsi->info.queue_mapping,
8650 &ctxt.info.queue_mapping,
8651 sizeof(vsi->info.queue_mapping));
8652 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8653 vsi->info.valid_sections = 0;
8655 /* query and update current VSI BW information */
8656 ret = i40e_vsi_get_bw_config(vsi);
8659 "Failed updating vsi bw info, err %s aq_err %s",
8660 i40e_stat_str(hw, ret),
8661 i40e_aq_str(hw, hw->aq.asq_last_status));
8665 vsi->enabled_tc = tc_map;
8672 * i40e_dcb_hw_configure - program the dcb setting to hw
8673 * @pf: pf the configuration is taken on
8674 * @new_cfg: new configuration
8675 * @tc_map: enabled TC bitmap
8677 * Returns 0 on success, negative value on failure
8679 static enum i40e_status_code
8680 i40e_dcb_hw_configure(struct i40e_pf *pf,
8681 struct i40e_dcbx_config *new_cfg,
8684 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8685 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8686 struct i40e_vsi *main_vsi = pf->main_vsi;
8687 struct i40e_vsi_list *vsi_list;
8688 enum i40e_status_code ret;
8692 /* Use the FW API if FW > v4.4*/
8693 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8694 (hw->aq.fw_maj_ver >= 5))) {
8695 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8696 " to configure DCB");
8697 return I40E_ERR_FIRMWARE_API_VERSION;
8700 /* Check if need reconfiguration */
8701 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8702 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8703 return I40E_SUCCESS;
8706 /* Copy the new config to the current config */
8707 *old_cfg = *new_cfg;
8708 old_cfg->etsrec = old_cfg->etscfg;
8709 ret = i40e_set_dcb_config(hw);
8712 "Set DCB Config failed, err %s aq_err %s\n",
8713 i40e_stat_str(hw, ret),
8714 i40e_aq_str(hw, hw->aq.asq_last_status));
8717 /* set receive Arbiter to RR mode and ETS scheme by default */
8718 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8719 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8720 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8721 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8722 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8723 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8724 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8725 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8726 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8727 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8728 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8729 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8730 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8732 /* get local mib to check whether it is configured correctly */
8734 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8735 /* Get Local DCB Config */
8736 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8737 &hw->local_dcbx_config);
8739 /* if Veb is created, need to update TC of it at first */
8740 if (main_vsi->veb) {
8741 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8743 PMD_INIT_LOG(WARNING,
8744 "Failed configuring TC for VEB seid=%d\n",
8745 main_vsi->veb->seid);
8747 /* Update each VSI */
8748 i40e_vsi_config_tc(main_vsi, tc_map);
8749 if (main_vsi->veb) {
8750 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8751 /* Beside main VSI and VMDQ VSIs, only enable default
8754 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8755 ret = i40e_vsi_config_tc(vsi_list->vsi,
8758 ret = i40e_vsi_config_tc(vsi_list->vsi,
8759 I40E_DEFAULT_TCMAP);
8761 PMD_INIT_LOG(WARNING,
8762 "Failed configuring TC for VSI seid=%d\n",
8763 vsi_list->vsi->seid);
8767 return I40E_SUCCESS;
8771 * i40e_dcb_init_configure - initial dcb config
8772 * @dev: device being configured
8773 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8775 * Returns 0 on success, negative value on failure
8778 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8784 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8785 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8789 /* DCB initialization:
8790 * Update DCB configuration from the Firmware and configure
8791 * LLDP MIB change event.
8793 if (sw_dcb == TRUE) {
8794 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8795 if (ret != I40E_SUCCESS)
8796 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8798 ret = i40e_init_dcb(hw);
8799 /* if sw_dcb, lldp agent is stopped, the return from
8800 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8803 if (ret != I40E_SUCCESS &&
8804 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8805 memset(&hw->local_dcbx_config, 0,
8806 sizeof(struct i40e_dcbx_config));
8807 /* set dcb default configuration */
8808 hw->local_dcbx_config.etscfg.willing = 0;
8809 hw->local_dcbx_config.etscfg.maxtcs = 0;
8810 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8811 hw->local_dcbx_config.etscfg.tsatable[0] =
8813 hw->local_dcbx_config.etsrec =
8814 hw->local_dcbx_config.etscfg;
8815 hw->local_dcbx_config.pfc.willing = 0;
8816 hw->local_dcbx_config.pfc.pfccap =
8817 I40E_MAX_TRAFFIC_CLASS;
8818 /* FW needs one App to configure HW */
8819 hw->local_dcbx_config.numapps = 1;
8820 hw->local_dcbx_config.app[0].selector =
8821 I40E_APP_SEL_ETHTYPE;
8822 hw->local_dcbx_config.app[0].priority = 3;
8823 hw->local_dcbx_config.app[0].protocolid =
8824 I40E_APP_PROTOID_FCOE;
8825 ret = i40e_set_dcb_config(hw);
8827 PMD_INIT_LOG(ERR, "default dcb config fails."
8828 " err = %d, aq_err = %d.", ret,
8829 hw->aq.asq_last_status);
8833 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8834 " aq_err = %d.", ret,
8835 hw->aq.asq_last_status);
8839 ret = i40e_aq_start_lldp(hw, NULL);
8840 if (ret != I40E_SUCCESS)
8841 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8843 ret = i40e_init_dcb(hw);
8845 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8846 PMD_INIT_LOG(ERR, "HW doesn't support"
8851 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8852 " aq_err = %d.", ret,
8853 hw->aq.asq_last_status);
8861 * i40e_dcb_setup - setup dcb related config
8862 * @dev: device being configured
8864 * Returns 0 on success, negative value on failure
8867 i40e_dcb_setup(struct rte_eth_dev *dev)
8869 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8870 struct i40e_dcbx_config dcb_cfg;
8874 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8875 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8879 if (pf->vf_num != 0)
8880 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8882 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8884 PMD_INIT_LOG(ERR, "invalid dcb config");
8887 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8889 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8897 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8898 struct rte_eth_dcb_info *dcb_info)
8900 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8901 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8902 struct i40e_vsi *vsi = pf->main_vsi;
8903 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8904 uint16_t bsf, tc_mapping;
8907 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8908 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8910 dcb_info->nb_tcs = 1;
8911 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8912 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8913 for (i = 0; i < dcb_info->nb_tcs; i++)
8914 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8916 /* get queue mapping if vmdq is disabled */
8917 if (!pf->nb_cfg_vmdq_vsi) {
8918 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8919 if (!(vsi->enabled_tc & (1 << i)))
8921 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8922 dcb_info->tc_queue.tc_rxq[j][i].base =
8923 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8924 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8925 dcb_info->tc_queue.tc_txq[j][i].base =
8926 dcb_info->tc_queue.tc_rxq[j][i].base;
8927 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8928 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8929 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8930 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8931 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8936 /* get queue mapping if vmdq is enabled */
8938 vsi = pf->vmdq[j].vsi;
8939 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8940 if (!(vsi->enabled_tc & (1 << i)))
8942 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8943 dcb_info->tc_queue.tc_rxq[j][i].base =
8944 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8945 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8946 dcb_info->tc_queue.tc_txq[j][i].base =
8947 dcb_info->tc_queue.tc_rxq[j][i].base;
8948 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8949 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8950 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8951 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8952 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8955 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8960 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8962 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8965 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8968 msix_intr = intr_handle->intr_vec[queue_id];
8969 if (msix_intr == I40E_MISC_VEC_ID)
8970 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8971 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8972 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8973 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8975 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8978 I40E_PFINT_DYN_CTLN(msix_intr -
8980 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8981 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8982 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8984 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8986 I40E_WRITE_FLUSH(hw);
8987 rte_intr_enable(&dev->pci_dev->intr_handle);
8993 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8995 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8996 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8999 msix_intr = intr_handle->intr_vec[queue_id];
9000 if (msix_intr == I40E_MISC_VEC_ID)
9001 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9004 I40E_PFINT_DYN_CTLN(msix_intr -
9007 I40E_WRITE_FLUSH(hw);
9012 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9014 /* Highest base addr + 32-bit word */
9015 return I40E_GLGEN_STAT_CLEAR + 4;
9018 static int i40e_get_regs(struct rte_eth_dev *dev,
9019 struct rte_dev_reg_info *regs)
9021 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9022 uint32_t *ptr_data = regs->data;
9023 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9024 const struct i40e_reg_info *reg_info;
9026 /* The first few registers have to be read using AQ operations */
9028 while (i40e_regs_adminq[reg_idx].name) {
9029 reg_info = &i40e_regs_adminq[reg_idx++];
9030 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9032 arr_idx2 <= reg_info->count2;
9034 reg_offset = arr_idx * reg_info->stride1 +
9035 arr_idx2 * reg_info->stride2;
9036 reg_offset += reg_info->base_addr;
9037 ptr_data[reg_offset >> 2] =
9038 i40e_read_rx_ctl(hw, reg_offset);
9042 /* The remaining registers can be read using primitives */
9044 while (i40e_regs_others[reg_idx].name) {
9045 reg_info = &i40e_regs_others[reg_idx++];
9046 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9048 arr_idx2 <= reg_info->count2;
9050 reg_offset = arr_idx * reg_info->stride1 +
9051 arr_idx2 * reg_info->stride2;
9052 reg_offset += reg_info->base_addr;
9053 ptr_data[reg_offset >> 2] =
9054 I40E_READ_REG(hw, reg_offset);
9061 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9063 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9065 /* Convert word count to byte count */
9066 return hw->nvm.sr_size << 1;
9069 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9070 struct rte_dev_eeprom_info *eeprom)
9072 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9073 uint16_t *data = eeprom->data;
9074 uint16_t offset, length, cnt_words;
9077 offset = eeprom->offset >> 1;
9078 length = eeprom->length >> 1;
9081 if (offset > hw->nvm.sr_size ||
9082 offset + length > hw->nvm.sr_size) {
9083 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9087 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9089 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9090 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9091 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9098 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9099 struct ether_addr *mac_addr)
9101 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9103 if (!is_valid_assigned_ether_addr(mac_addr)) {
9104 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9108 /* Flags: 0x3 updates port address */
9109 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);