1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
404 static const struct rte_pci_id pci_id_i40e_map[] = {
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
425 { .vendor_id = 0, /* sentinel */ },
428 static const struct eth_dev_ops i40e_eth_dev_ops = {
429 .dev_configure = i40e_dev_configure,
430 .dev_start = i40e_dev_start,
431 .dev_stop = i40e_dev_stop,
432 .dev_close = i40e_dev_close,
433 .dev_reset = i40e_dev_reset,
434 .promiscuous_enable = i40e_dev_promiscuous_enable,
435 .promiscuous_disable = i40e_dev_promiscuous_disable,
436 .allmulticast_enable = i40e_dev_allmulticast_enable,
437 .allmulticast_disable = i40e_dev_allmulticast_disable,
438 .dev_set_link_up = i40e_dev_set_link_up,
439 .dev_set_link_down = i40e_dev_set_link_down,
440 .link_update = i40e_dev_link_update,
441 .stats_get = i40e_dev_stats_get,
442 .xstats_get = i40e_dev_xstats_get,
443 .xstats_get_names = i40e_dev_xstats_get_names,
444 .stats_reset = i40e_dev_stats_reset,
445 .xstats_reset = i40e_dev_stats_reset,
446 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
447 .fw_version_get = i40e_fw_version_get,
448 .dev_infos_get = i40e_dev_info_get,
449 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
450 .vlan_filter_set = i40e_vlan_filter_set,
451 .vlan_tpid_set = i40e_vlan_tpid_set,
452 .vlan_offload_set = i40e_vlan_offload_set,
453 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
454 .vlan_pvid_set = i40e_vlan_pvid_set,
455 .rx_queue_start = i40e_dev_rx_queue_start,
456 .rx_queue_stop = i40e_dev_rx_queue_stop,
457 .tx_queue_start = i40e_dev_tx_queue_start,
458 .tx_queue_stop = i40e_dev_tx_queue_stop,
459 .rx_queue_setup = i40e_dev_rx_queue_setup,
460 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
461 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
462 .rx_queue_release = i40e_dev_rx_queue_release,
463 .rx_queue_count = i40e_dev_rx_queue_count,
464 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
465 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
466 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
467 .tx_queue_setup = i40e_dev_tx_queue_setup,
468 .tx_queue_release = i40e_dev_tx_queue_release,
469 .dev_led_on = i40e_dev_led_on,
470 .dev_led_off = i40e_dev_led_off,
471 .flow_ctrl_get = i40e_flow_ctrl_get,
472 .flow_ctrl_set = i40e_flow_ctrl_set,
473 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
474 .mac_addr_add = i40e_macaddr_add,
475 .mac_addr_remove = i40e_macaddr_remove,
476 .reta_update = i40e_dev_rss_reta_update,
477 .reta_query = i40e_dev_rss_reta_query,
478 .rss_hash_update = i40e_dev_rss_hash_update,
479 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
480 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
481 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
482 .filter_ctrl = i40e_dev_filter_ctrl,
483 .rxq_info_get = i40e_rxq_info_get,
484 .txq_info_get = i40e_txq_info_get,
485 .mirror_rule_set = i40e_mirror_rule_set,
486 .mirror_rule_reset = i40e_mirror_rule_reset,
487 .timesync_enable = i40e_timesync_enable,
488 .timesync_disable = i40e_timesync_disable,
489 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
490 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
491 .get_dcb_info = i40e_dev_get_dcb_info,
492 .timesync_adjust_time = i40e_timesync_adjust_time,
493 .timesync_read_time = i40e_timesync_read_time,
494 .timesync_write_time = i40e_timesync_write_time,
495 .get_reg = i40e_get_regs,
496 .get_eeprom_length = i40e_get_eeprom_length,
497 .get_eeprom = i40e_get_eeprom,
498 .get_module_info = i40e_get_module_info,
499 .get_module_eeprom = i40e_get_module_eeprom,
500 .mac_addr_set = i40e_set_default_mac_addr,
501 .mtu_set = i40e_dev_mtu_set,
502 .tm_ops_get = i40e_tm_ops_get,
505 /* store statistics names and its offset in stats structure */
506 struct rte_i40e_xstats_name_off {
507 char name[RTE_ETH_XSTATS_NAME_SIZE];
511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
512 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
513 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
514 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
515 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
516 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
517 rx_unknown_protocol)},
518 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
519 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
520 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
521 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
525 sizeof(rte_i40e_stats_strings[0]))
527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
528 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
529 tx_dropped_link_down)},
530 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
531 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
533 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
534 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
536 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
538 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
540 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
541 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
542 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
543 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
544 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
545 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
547 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
549 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
551 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
553 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
555 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
557 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
562 mac_short_packet_dropped)},
563 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
566 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
567 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
569 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
571 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
573 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
575 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
577 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_flow_director_atr_match_packets",
580 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
581 {"rx_flow_director_sb_match_packets",
582 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
583 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
585 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
587 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
589 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
594 sizeof(rte_i40e_hw_port_strings[0]))
596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
597 {"xon_packets", offsetof(struct i40e_hw_port_stats,
599 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
604 sizeof(rte_i40e_rxq_prio_strings[0]))
606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
607 {"xon_packets", offsetof(struct i40e_hw_port_stats,
609 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
611 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
612 priority_xon_2_xoff)},
615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
616 sizeof(rte_i40e_txq_prio_strings[0]))
619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
620 struct rte_pci_device *pci_dev)
622 char name[RTE_ETH_NAME_MAX_LEN];
623 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
626 if (pci_dev->device.devargs) {
627 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
633 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
634 sizeof(struct i40e_adapter),
635 eth_dev_pci_specific_init, pci_dev,
636 eth_i40e_dev_init, NULL);
638 if (retval || eth_da.nb_representor_ports < 1)
641 /* probe VF representor ports */
642 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
643 pci_dev->device.name);
645 if (pf_ethdev == NULL)
648 for (i = 0; i < eth_da.nb_representor_ports; i++) {
649 struct i40e_vf_representor representor = {
650 .vf_id = eth_da.representor_ports[i],
651 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
652 pf_ethdev->data->dev_private)->switch_domain_id,
653 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
654 pf_ethdev->data->dev_private)
657 /* representor port net_bdf_port */
658 snprintf(name, sizeof(name), "net_%s_representor_%d",
659 pci_dev->device.name, eth_da.representor_ports[i]);
661 retval = rte_eth_dev_create(&pci_dev->device, name,
662 sizeof(struct i40e_vf_representor), NULL, NULL,
663 i40e_vf_representor_init, &representor);
666 PMD_DRV_LOG(ERR, "failed to create i40e vf "
667 "representor %s.", name);
673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
675 struct rte_eth_dev *ethdev;
677 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
682 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
683 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
685 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
688 static struct rte_pci_driver rte_i40e_pmd = {
689 .id_table = pci_id_i40e_map,
690 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
691 RTE_PCI_DRV_IOVA_AS_VA,
692 .probe = eth_i40e_pci_probe,
693 .remove = eth_i40e_pci_remove,
697 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
699 i40e_write_rx_ctl(hw, reg_addr, reg_val);
700 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
705 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
706 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
707 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
709 #ifndef I40E_GLQF_ORT
710 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
712 #ifndef I40E_GLQF_PIT
713 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
715 #ifndef I40E_GLQF_L3_MAP
716 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
719 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
722 * Initialize registers for parsing packet type of QinQ
723 * This should be removed from code once proper
724 * configuration API is added to avoid configuration conflicts
725 * between ports of the same device.
727 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
728 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
729 i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
732 static inline void i40e_config_automask(struct i40e_pf *pf)
734 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
737 /* INTENA flag is not auto-cleared for interrupt */
738 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
739 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
740 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
742 /* If support multi-driver, PF will use INT0. */
743 if (!pf->support_multi_driver)
744 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
746 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
749 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
752 * Add a ethertype filter to drop all flow control frames transmitted
756 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
758 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
759 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
760 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
761 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
764 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
765 I40E_FLOW_CONTROL_ETHERTYPE, flags,
766 pf->main_vsi_seid, 0,
770 "Failed to add filter to drop flow control frames from VSIs.");
774 floating_veb_list_handler(__rte_unused const char *key,
775 const char *floating_veb_value,
779 unsigned int count = 0;
782 bool *vf_floating_veb = opaque;
784 while (isblank(*floating_veb_value))
785 floating_veb_value++;
787 /* Reset floating VEB configuration for VFs */
788 for (idx = 0; idx < I40E_MAX_VF; idx++)
789 vf_floating_veb[idx] = false;
793 while (isblank(*floating_veb_value))
794 floating_veb_value++;
795 if (*floating_veb_value == '\0')
798 idx = strtoul(floating_veb_value, &end, 10);
799 if (errno || end == NULL)
801 while (isblank(*end))
805 } else if ((*end == ';') || (*end == '\0')) {
807 if (min == I40E_MAX_VF)
809 if (max >= I40E_MAX_VF)
810 max = I40E_MAX_VF - 1;
811 for (idx = min; idx <= max; idx++) {
812 vf_floating_veb[idx] = true;
819 floating_veb_value = end + 1;
820 } while (*end != '\0');
829 config_vf_floating_veb(struct rte_devargs *devargs,
830 uint16_t floating_veb,
831 bool *vf_floating_veb)
833 struct rte_kvargs *kvlist;
835 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
839 /* All the VFs attach to the floating VEB by default
840 * when the floating VEB is enabled.
842 for (i = 0; i < I40E_MAX_VF; i++)
843 vf_floating_veb[i] = true;
848 kvlist = rte_kvargs_parse(devargs->args, NULL);
852 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
853 rte_kvargs_free(kvlist);
856 /* When the floating_veb_list parameter exists, all the VFs
857 * will attach to the legacy VEB firstly, then configure VFs
858 * to the floating VEB according to the floating_veb_list.
860 if (rte_kvargs_process(kvlist, floating_veb_list,
861 floating_veb_list_handler,
862 vf_floating_veb) < 0) {
863 rte_kvargs_free(kvlist);
866 rte_kvargs_free(kvlist);
870 i40e_check_floating_handler(__rte_unused const char *key,
872 __rte_unused void *opaque)
874 if (strcmp(value, "1"))
881 is_floating_veb_supported(struct rte_devargs *devargs)
883 struct rte_kvargs *kvlist;
884 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
889 kvlist = rte_kvargs_parse(devargs->args, NULL);
893 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
894 rte_kvargs_free(kvlist);
897 /* Floating VEB is enabled when there's key-value:
898 * enable_floating_veb=1
900 if (rte_kvargs_process(kvlist, floating_veb_key,
901 i40e_check_floating_handler, NULL) < 0) {
902 rte_kvargs_free(kvlist);
905 rte_kvargs_free(kvlist);
911 config_floating_veb(struct rte_eth_dev *dev)
913 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
917 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
919 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
921 is_floating_veb_supported(pci_dev->device.devargs);
922 config_vf_floating_veb(pci_dev->device.devargs,
924 pf->floating_veb_list);
926 pf->floating_veb = false;
930 #define I40E_L2_TAGS_S_TAG_SHIFT 1
931 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
934 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
936 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
937 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
938 char ethertype_hash_name[RTE_HASH_NAMESIZE];
941 struct rte_hash_parameters ethertype_hash_params = {
942 .name = ethertype_hash_name,
943 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
944 .key_len = sizeof(struct i40e_ethertype_filter_input),
945 .hash_func = rte_hash_crc,
946 .hash_func_init_val = 0,
947 .socket_id = rte_socket_id(),
950 /* Initialize ethertype filter rule list and hash */
951 TAILQ_INIT(ðertype_rule->ethertype_list);
952 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
953 "ethertype_%s", dev->device->name);
954 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
955 if (!ethertype_rule->hash_table) {
956 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
959 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
960 sizeof(struct i40e_ethertype_filter *) *
961 I40E_MAX_ETHERTYPE_FILTER_NUM,
963 if (!ethertype_rule->hash_map) {
965 "Failed to allocate memory for ethertype hash map!");
967 goto err_ethertype_hash_map_alloc;
972 err_ethertype_hash_map_alloc:
973 rte_hash_free(ethertype_rule->hash_table);
979 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
981 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
982 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
983 char tunnel_hash_name[RTE_HASH_NAMESIZE];
986 struct rte_hash_parameters tunnel_hash_params = {
987 .name = tunnel_hash_name,
988 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
989 .key_len = sizeof(struct i40e_tunnel_filter_input),
990 .hash_func = rte_hash_crc,
991 .hash_func_init_val = 0,
992 .socket_id = rte_socket_id(),
995 /* Initialize tunnel filter rule list and hash */
996 TAILQ_INIT(&tunnel_rule->tunnel_list);
997 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
998 "tunnel_%s", dev->device->name);
999 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1000 if (!tunnel_rule->hash_table) {
1001 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1004 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1005 sizeof(struct i40e_tunnel_filter *) *
1006 I40E_MAX_TUNNEL_FILTER_NUM,
1008 if (!tunnel_rule->hash_map) {
1010 "Failed to allocate memory for tunnel hash map!");
1012 goto err_tunnel_hash_map_alloc;
1017 err_tunnel_hash_map_alloc:
1018 rte_hash_free(tunnel_rule->hash_table);
1024 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1026 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1027 struct i40e_fdir_info *fdir_info = &pf->fdir;
1028 char fdir_hash_name[RTE_HASH_NAMESIZE];
1031 struct rte_hash_parameters fdir_hash_params = {
1032 .name = fdir_hash_name,
1033 .entries = I40E_MAX_FDIR_FILTER_NUM,
1034 .key_len = sizeof(struct i40e_fdir_input),
1035 .hash_func = rte_hash_crc,
1036 .hash_func_init_val = 0,
1037 .socket_id = rte_socket_id(),
1040 /* Initialize flow director filter rule list and hash */
1041 TAILQ_INIT(&fdir_info->fdir_list);
1042 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1043 "fdir_%s", dev->device->name);
1044 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1045 if (!fdir_info->hash_table) {
1046 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1049 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1050 sizeof(struct i40e_fdir_filter *) *
1051 I40E_MAX_FDIR_FILTER_NUM,
1053 if (!fdir_info->hash_map) {
1055 "Failed to allocate memory for fdir hash map!");
1057 goto err_fdir_hash_map_alloc;
1061 err_fdir_hash_map_alloc:
1062 rte_hash_free(fdir_info->hash_table);
1068 i40e_init_customized_info(struct i40e_pf *pf)
1072 /* Initialize customized pctype */
1073 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1074 pf->customized_pctype[i].index = i;
1075 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1076 pf->customized_pctype[i].valid = false;
1079 pf->gtp_support = false;
1083 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1085 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1086 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1087 struct i40e_queue_regions *info = &pf->queue_region;
1090 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1091 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1093 memset(info, 0, sizeof(struct i40e_queue_regions));
1096 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
1099 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1104 unsigned long support_multi_driver;
1107 pf = (struct i40e_pf *)opaque;
1110 support_multi_driver = strtoul(value, &end, 10);
1111 if (errno != 0 || end == value || *end != 0) {
1112 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1116 if (support_multi_driver == 1 || support_multi_driver == 0)
1117 pf->support_multi_driver = (bool)support_multi_driver;
1119 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1120 "enable global configuration by default."
1121 ETH_I40E_SUPPORT_MULTI_DRIVER);
1126 i40e_support_multi_driver(struct rte_eth_dev *dev)
1128 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1129 static const char *const valid_keys[] = {
1130 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1131 struct rte_kvargs *kvlist;
1133 /* Enable global configuration by default */
1134 pf->support_multi_driver = false;
1136 if (!dev->device->devargs)
1139 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1143 if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1144 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1145 "the first invalid or last valid one is used !",
1146 ETH_I40E_SUPPORT_MULTI_DRIVER);
1148 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1149 i40e_parse_multi_drv_handler, pf) < 0) {
1150 rte_kvargs_free(kvlist);
1154 rte_kvargs_free(kvlist);
1159 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1161 struct rte_pci_device *pci_dev;
1162 struct rte_intr_handle *intr_handle;
1163 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1164 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1165 struct i40e_vsi *vsi;
1168 uint8_t aq_fail = 0;
1170 PMD_INIT_FUNC_TRACE();
1172 dev->dev_ops = &i40e_eth_dev_ops;
1173 dev->rx_pkt_burst = i40e_recv_pkts;
1174 dev->tx_pkt_burst = i40e_xmit_pkts;
1175 dev->tx_pkt_prepare = i40e_prep_pkts;
1177 /* for secondary processes, we don't initialise any further as primary
1178 * has already done this work. Only check we don't need a different
1180 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1181 i40e_set_rx_function(dev);
1182 i40e_set_tx_function(dev);
1185 i40e_set_default_ptype_table(dev);
1186 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1187 intr_handle = &pci_dev->intr_handle;
1189 rte_eth_copy_pci_info(dev, pci_dev);
1191 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1192 pf->adapter->eth_dev = dev;
1193 pf->dev_data = dev->data;
1195 hw->back = I40E_PF_TO_ADAPTER(pf);
1196 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1199 "Hardware is not available, as address is NULL");
1203 hw->vendor_id = pci_dev->id.vendor_id;
1204 hw->device_id = pci_dev->id.device_id;
1205 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1206 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1207 hw->bus.device = pci_dev->addr.devid;
1208 hw->bus.func = pci_dev->addr.function;
1209 hw->adapter_stopped = 0;
1211 /* Check if need to support multi-driver */
1212 i40e_support_multi_driver(dev);
1214 /* Make sure all is clean before doing PF reset */
1217 /* Initialize the hardware */
1220 /* Reset here to make sure all is clean for each PF */
1221 ret = i40e_pf_reset(hw);
1223 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1227 /* Initialize the shared code (base driver) */
1228 ret = i40e_init_shared_code(hw);
1230 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1234 i40e_config_automask(pf);
1236 i40e_set_default_pctype_table(dev);
1239 * To work around the NVM issue, initialize registers
1240 * for packet type of QinQ by software.
1241 * It should be removed once issues are fixed in NVM.
1243 if (!pf->support_multi_driver)
1244 i40e_GLQF_reg_init(hw);
1246 /* Initialize the input set for filters (hash and fd) to default value */
1247 i40e_filter_input_set_init(pf);
1249 /* Initialize the parameters for adminq */
1250 i40e_init_adminq_parameter(hw);
1251 ret = i40e_init_adminq(hw);
1252 if (ret != I40E_SUCCESS) {
1253 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1256 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1257 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1258 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1259 ((hw->nvm.version >> 12) & 0xf),
1260 ((hw->nvm.version >> 4) & 0xff),
1261 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1263 /* initialise the L3_MAP register */
1264 if (!pf->support_multi_driver) {
1265 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1268 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1271 "Global register 0x%08x is changed with 0x28",
1272 I40E_GLQF_L3_MAP(40));
1273 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1276 /* Need the special FW version to support floating VEB */
1277 config_floating_veb(dev);
1278 /* Clear PXE mode */
1279 i40e_clear_pxe_mode(hw);
1280 i40e_dev_sync_phy_type(hw);
1283 * On X710, performance number is far from the expectation on recent
1284 * firmware versions. The fix for this issue may not be integrated in
1285 * the following firmware version. So the workaround in software driver
1286 * is needed. It needs to modify the initial values of 3 internal only
1287 * registers. Note that the workaround can be removed when it is fixed
1288 * in firmware in the future.
1290 i40e_configure_registers(hw);
1292 /* Get hw capabilities */
1293 ret = i40e_get_cap(hw);
1294 if (ret != I40E_SUCCESS) {
1295 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1296 goto err_get_capabilities;
1299 /* Initialize parameters for PF */
1300 ret = i40e_pf_parameter_init(dev);
1302 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1303 goto err_parameter_init;
1306 /* Initialize the queue management */
1307 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1309 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1310 goto err_qp_pool_init;
1312 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1313 hw->func_caps.num_msix_vectors - 1);
1315 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1316 goto err_msix_pool_init;
1319 /* Initialize lan hmc */
1320 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1321 hw->func_caps.num_rx_qp, 0, 0);
1322 if (ret != I40E_SUCCESS) {
1323 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1324 goto err_init_lan_hmc;
1327 /* Configure lan hmc */
1328 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1329 if (ret != I40E_SUCCESS) {
1330 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1331 goto err_configure_lan_hmc;
1334 /* Get and check the mac address */
1335 i40e_get_mac_addr(hw, hw->mac.addr);
1336 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1337 PMD_INIT_LOG(ERR, "mac address is not valid");
1339 goto err_get_mac_addr;
1341 /* Copy the permanent MAC address */
1342 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1343 (struct ether_addr *) hw->mac.perm_addr);
1345 /* Disable flow control */
1346 hw->fc.requested_mode = I40E_FC_NONE;
1347 i40e_set_fc(hw, &aq_fail, TRUE);
1349 /* Set the global registers with default ether type value */
1350 if (!pf->support_multi_driver) {
1351 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1353 if (ret != I40E_SUCCESS) {
1355 "Failed to set the default outer "
1357 goto err_setup_pf_switch;
1361 /* PF setup, which includes VSI setup */
1362 ret = i40e_pf_setup(pf);
1364 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1365 goto err_setup_pf_switch;
1368 /* reset all stats of the device, including pf and main vsi */
1369 i40e_dev_stats_reset(dev);
1373 /* Disable double vlan by default */
1374 i40e_vsi_config_double_vlan(vsi, FALSE);
1376 /* Disable S-TAG identification when floating_veb is disabled */
1377 if (!pf->floating_veb) {
1378 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1379 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1380 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1381 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1385 if (!vsi->max_macaddrs)
1386 len = ETHER_ADDR_LEN;
1388 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1390 /* Should be after VSI initialized */
1391 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1392 if (!dev->data->mac_addrs) {
1394 "Failed to allocated memory for storing mac address");
1397 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1398 &dev->data->mac_addrs[0]);
1400 /* Init dcb to sw mode by default */
1401 ret = i40e_dcb_init_configure(dev, TRUE);
1402 if (ret != I40E_SUCCESS) {
1403 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1404 pf->flags &= ~I40E_FLAG_DCB;
1406 /* Update HW struct after DCB configuration */
1409 /* initialize pf host driver to setup SRIOV resource if applicable */
1410 i40e_pf_host_init(dev);
1412 /* register callback func to eal lib */
1413 rte_intr_callback_register(intr_handle,
1414 i40e_dev_interrupt_handler, dev);
1416 /* configure and enable device interrupt */
1417 i40e_pf_config_irq0(hw, TRUE);
1418 i40e_pf_enable_irq0(hw);
1420 /* enable uio intr after callback register */
1421 rte_intr_enable(intr_handle);
1423 /* By default disable flexible payload in global configuration */
1424 if (!pf->support_multi_driver)
1425 i40e_flex_payload_reg_set_default(hw);
1428 * Add an ethertype filter to drop all flow control frames transmitted
1429 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1432 i40e_add_tx_flow_control_drop_filter(pf);
1434 /* Set the max frame size to 0x2600 by default,
1435 * in case other drivers changed the default value.
1437 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1439 /* initialize mirror rule list */
1440 TAILQ_INIT(&pf->mirror_list);
1442 /* initialize Traffic Manager configuration */
1443 i40e_tm_conf_init(dev);
1445 /* Initialize customized information */
1446 i40e_init_customized_info(pf);
1448 ret = i40e_init_ethtype_filter_list(dev);
1450 goto err_init_ethtype_filter_list;
1451 ret = i40e_init_tunnel_filter_list(dev);
1453 goto err_init_tunnel_filter_list;
1454 ret = i40e_init_fdir_filter_list(dev);
1456 goto err_init_fdir_filter_list;
1458 /* initialize queue region configuration */
1459 i40e_init_queue_region_conf(dev);
1461 /* initialize rss configuration from rte_flow */
1462 memset(&pf->rss_info, 0,
1463 sizeof(struct i40e_rte_flow_rss_conf));
1467 err_init_fdir_filter_list:
1468 rte_free(pf->tunnel.hash_table);
1469 rte_free(pf->tunnel.hash_map);
1470 err_init_tunnel_filter_list:
1471 rte_free(pf->ethertype.hash_table);
1472 rte_free(pf->ethertype.hash_map);
1473 err_init_ethtype_filter_list:
1474 rte_free(dev->data->mac_addrs);
1476 i40e_vsi_release(pf->main_vsi);
1477 err_setup_pf_switch:
1479 err_configure_lan_hmc:
1480 (void)i40e_shutdown_lan_hmc(hw);
1482 i40e_res_pool_destroy(&pf->msix_pool);
1484 i40e_res_pool_destroy(&pf->qp_pool);
1487 err_get_capabilities:
1488 (void)i40e_shutdown_adminq(hw);
1494 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1496 struct i40e_ethertype_filter *p_ethertype;
1497 struct i40e_ethertype_rule *ethertype_rule;
1499 ethertype_rule = &pf->ethertype;
1500 /* Remove all ethertype filter rules and hash */
1501 if (ethertype_rule->hash_map)
1502 rte_free(ethertype_rule->hash_map);
1503 if (ethertype_rule->hash_table)
1504 rte_hash_free(ethertype_rule->hash_table);
1506 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1507 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1508 p_ethertype, rules);
1509 rte_free(p_ethertype);
1514 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1516 struct i40e_tunnel_filter *p_tunnel;
1517 struct i40e_tunnel_rule *tunnel_rule;
1519 tunnel_rule = &pf->tunnel;
1520 /* Remove all tunnel director rules and hash */
1521 if (tunnel_rule->hash_map)
1522 rte_free(tunnel_rule->hash_map);
1523 if (tunnel_rule->hash_table)
1524 rte_hash_free(tunnel_rule->hash_table);
1526 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1527 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1533 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1535 struct i40e_fdir_filter *p_fdir;
1536 struct i40e_fdir_info *fdir_info;
1538 fdir_info = &pf->fdir;
1539 /* Remove all flow director rules and hash */
1540 if (fdir_info->hash_map)
1541 rte_free(fdir_info->hash_map);
1542 if (fdir_info->hash_table)
1543 rte_hash_free(fdir_info->hash_table);
1545 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1546 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1551 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1554 * Disable by default flexible payload
1555 * for corresponding L2/L3/L4 layers.
1557 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1558 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1559 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1560 i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1564 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1567 struct rte_pci_device *pci_dev;
1568 struct rte_intr_handle *intr_handle;
1570 struct i40e_filter_control_settings settings;
1571 struct rte_flow *p_flow;
1573 uint8_t aq_fail = 0;
1576 PMD_INIT_FUNC_TRACE();
1578 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1581 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1582 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1584 intr_handle = &pci_dev->intr_handle;
1586 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1588 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1590 if (hw->adapter_stopped == 0)
1591 i40e_dev_close(dev);
1593 dev->dev_ops = NULL;
1594 dev->rx_pkt_burst = NULL;
1595 dev->tx_pkt_burst = NULL;
1597 /* Clear PXE mode */
1598 i40e_clear_pxe_mode(hw);
1600 /* Unconfigure filter control */
1601 memset(&settings, 0, sizeof(settings));
1602 ret = i40e_set_filter_control(hw, &settings);
1604 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1607 /* Disable flow control */
1608 hw->fc.requested_mode = I40E_FC_NONE;
1609 i40e_set_fc(hw, &aq_fail, TRUE);
1611 /* uninitialize pf host driver */
1612 i40e_pf_host_uninit(dev);
1614 rte_free(dev->data->mac_addrs);
1615 dev->data->mac_addrs = NULL;
1617 /* disable uio intr before callback unregister */
1618 rte_intr_disable(intr_handle);
1620 /* unregister callback func to eal lib */
1622 ret = rte_intr_callback_unregister(intr_handle,
1623 i40e_dev_interrupt_handler, dev);
1626 } else if (ret != -EAGAIN) {
1628 "intr callback unregister failed: %d",
1632 i40e_msec_delay(500);
1633 } while (retries++ < 5);
1635 i40e_rm_ethtype_filter_list(pf);
1636 i40e_rm_tunnel_filter_list(pf);
1637 i40e_rm_fdir_filter_list(pf);
1639 /* Remove all flows */
1640 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1641 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1645 /* Remove all Traffic Manager configuration */
1646 i40e_tm_conf_uninit(dev);
1652 i40e_dev_configure(struct rte_eth_dev *dev)
1654 struct i40e_adapter *ad =
1655 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1656 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1661 ret = i40e_dev_sync_phy_type(hw);
1665 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1666 * bulk allocation or vector Rx preconditions we will reset it.
1668 ad->rx_bulk_alloc_allowed = true;
1669 ad->rx_vec_allowed = true;
1670 ad->tx_simple_allowed = true;
1671 ad->tx_vec_allowed = true;
1673 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1674 ret = i40e_fdir_setup(pf);
1675 if (ret != I40E_SUCCESS) {
1676 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1679 ret = i40e_fdir_configure(dev);
1681 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1685 i40e_fdir_teardown(pf);
1687 ret = i40e_dev_init_vlan(dev);
1692 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1693 * RSS setting have different requirements.
1694 * General PMD driver call sequence are NIC init, configure,
1695 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1696 * will try to lookup the VSI that specific queue belongs to if VMDQ
1697 * applicable. So, VMDQ setting has to be done before
1698 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1699 * For RSS setting, it will try to calculate actual configured RX queue
1700 * number, which will be available after rx_queue_setup(). dev_start()
1701 * function is good to place RSS setup.
1703 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1704 ret = i40e_vmdq_setup(dev);
1709 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1710 ret = i40e_dcb_setup(dev);
1712 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1717 TAILQ_INIT(&pf->flow_list);
1722 /* need to release vmdq resource if exists */
1723 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1724 i40e_vsi_release(pf->vmdq[i].vsi);
1725 pf->vmdq[i].vsi = NULL;
1730 /* need to release fdir resource if exists */
1731 i40e_fdir_teardown(pf);
1736 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1738 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1739 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1740 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1742 uint16_t msix_vect = vsi->msix_intr;
1745 for (i = 0; i < vsi->nb_qps; i++) {
1746 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1747 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1751 if (vsi->type != I40E_VSI_SRIOV) {
1752 if (!rte_intr_allow_others(intr_handle)) {
1753 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1754 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1756 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1759 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1760 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1762 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1767 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1768 vsi->user_param + (msix_vect - 1);
1770 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1771 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1773 I40E_WRITE_FLUSH(hw);
1777 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1778 int base_queue, int nb_queue,
1783 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1784 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1786 /* Bind all RX queues to allocated MSIX interrupt */
1787 for (i = 0; i < nb_queue; i++) {
1788 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1789 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1790 ((base_queue + i + 1) <<
1791 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1792 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1793 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1795 if (i == nb_queue - 1)
1796 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1797 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1800 /* Write first RX queue to Link list register as the head element */
1801 if (vsi->type != I40E_VSI_SRIOV) {
1803 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1804 pf->support_multi_driver);
1806 if (msix_vect == I40E_MISC_VEC_ID) {
1807 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1809 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1811 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1813 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1816 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1818 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1820 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1822 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1829 if (msix_vect == I40E_MISC_VEC_ID) {
1831 I40E_VPINT_LNKLST0(vsi->user_param),
1833 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1835 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1837 /* num_msix_vectors_vf needs to minus irq0 */
1838 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1839 vsi->user_param + (msix_vect - 1);
1841 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1843 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1845 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1849 I40E_WRITE_FLUSH(hw);
1853 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1855 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1857 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1858 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1859 uint16_t msix_vect = vsi->msix_intr;
1860 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1861 uint16_t queue_idx = 0;
1865 for (i = 0; i < vsi->nb_qps; i++) {
1866 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1867 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1870 /* VF bind interrupt */
1871 if (vsi->type == I40E_VSI_SRIOV) {
1872 __vsi_queues_bind_intr(vsi, msix_vect,
1873 vsi->base_queue, vsi->nb_qps,
1878 /* PF & VMDq bind interrupt */
1879 if (rte_intr_dp_is_en(intr_handle)) {
1880 if (vsi->type == I40E_VSI_MAIN) {
1883 } else if (vsi->type == I40E_VSI_VMDQ2) {
1884 struct i40e_vsi *main_vsi =
1885 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1886 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1891 for (i = 0; i < vsi->nb_used_qps; i++) {
1893 if (!rte_intr_allow_others(intr_handle))
1894 /* allow to share MISC_VEC_ID */
1895 msix_vect = I40E_MISC_VEC_ID;
1897 /* no enough msix_vect, map all to one */
1898 __vsi_queues_bind_intr(vsi, msix_vect,
1899 vsi->base_queue + i,
1900 vsi->nb_used_qps - i,
1902 for (; !!record && i < vsi->nb_used_qps; i++)
1903 intr_handle->intr_vec[queue_idx + i] =
1907 /* 1:1 queue/msix_vect mapping */
1908 __vsi_queues_bind_intr(vsi, msix_vect,
1909 vsi->base_queue + i, 1,
1912 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1920 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1922 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1923 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1924 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1925 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1926 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1927 uint16_t msix_intr, i;
1929 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1930 for (i = 0; i < vsi->nb_msix; i++) {
1931 msix_intr = vsi->msix_intr + i;
1932 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1933 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1934 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1935 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1938 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1939 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1940 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1941 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1943 I40E_WRITE_FLUSH(hw);
1947 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1949 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1950 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1951 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1952 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1953 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1954 uint16_t msix_intr, i;
1956 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1957 for (i = 0; i < vsi->nb_msix; i++) {
1958 msix_intr = vsi->msix_intr + i;
1959 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1960 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1963 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1964 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1966 I40E_WRITE_FLUSH(hw);
1969 static inline uint8_t
1970 i40e_parse_link_speeds(uint16_t link_speeds)
1972 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1974 if (link_speeds & ETH_LINK_SPEED_40G)
1975 link_speed |= I40E_LINK_SPEED_40GB;
1976 if (link_speeds & ETH_LINK_SPEED_25G)
1977 link_speed |= I40E_LINK_SPEED_25GB;
1978 if (link_speeds & ETH_LINK_SPEED_20G)
1979 link_speed |= I40E_LINK_SPEED_20GB;
1980 if (link_speeds & ETH_LINK_SPEED_10G)
1981 link_speed |= I40E_LINK_SPEED_10GB;
1982 if (link_speeds & ETH_LINK_SPEED_1G)
1983 link_speed |= I40E_LINK_SPEED_1GB;
1984 if (link_speeds & ETH_LINK_SPEED_100M)
1985 link_speed |= I40E_LINK_SPEED_100MB;
1991 i40e_phy_conf_link(struct i40e_hw *hw,
1993 uint8_t force_speed,
1996 enum i40e_status_code status;
1997 struct i40e_aq_get_phy_abilities_resp phy_ab;
1998 struct i40e_aq_set_phy_config phy_conf;
1999 enum i40e_aq_phy_type cnt;
2000 uint32_t phy_type_mask = 0;
2002 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2003 I40E_AQ_PHY_FLAG_PAUSE_RX |
2004 I40E_AQ_PHY_FLAG_PAUSE_RX |
2005 I40E_AQ_PHY_FLAG_LOW_POWER;
2006 const uint8_t advt = I40E_LINK_SPEED_40GB |
2007 I40E_LINK_SPEED_25GB |
2008 I40E_LINK_SPEED_10GB |
2009 I40E_LINK_SPEED_1GB |
2010 I40E_LINK_SPEED_100MB;
2014 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2019 /* If link already up, no need to set up again */
2020 if (is_up && phy_ab.phy_type != 0)
2021 return I40E_SUCCESS;
2023 memset(&phy_conf, 0, sizeof(phy_conf));
2025 /* bits 0-2 use the values from get_phy_abilities_resp */
2027 abilities |= phy_ab.abilities & mask;
2029 /* update ablities and speed */
2030 if (abilities & I40E_AQ_PHY_AN_ENABLED)
2031 phy_conf.link_speed = advt;
2033 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2035 phy_conf.abilities = abilities;
2039 /* To enable link, phy_type mask needs to include each type */
2040 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
2041 phy_type_mask |= 1 << cnt;
2043 /* use get_phy_abilities_resp value for the rest */
2044 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2045 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2046 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2047 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2048 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2049 phy_conf.eee_capability = phy_ab.eee_capability;
2050 phy_conf.eeer = phy_ab.eeer_val;
2051 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2053 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2054 phy_ab.abilities, phy_ab.link_speed);
2055 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2056 phy_conf.abilities, phy_conf.link_speed);
2058 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2062 return I40E_SUCCESS;
2066 i40e_apply_link_speed(struct rte_eth_dev *dev)
2069 uint8_t abilities = 0;
2070 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071 struct rte_eth_conf *conf = &dev->data->dev_conf;
2073 speed = i40e_parse_link_speeds(conf->link_speeds);
2074 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2075 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2076 abilities |= I40E_AQ_PHY_AN_ENABLED;
2077 abilities |= I40E_AQ_PHY_LINK_ENABLED;
2079 return i40e_phy_conf_link(hw, abilities, speed, true);
2083 i40e_dev_start(struct rte_eth_dev *dev)
2085 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2086 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087 struct i40e_vsi *main_vsi = pf->main_vsi;
2089 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2090 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2091 uint32_t intr_vector = 0;
2092 struct i40e_vsi *vsi;
2094 hw->adapter_stopped = 0;
2096 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2098 "Invalid link_speeds for port %u, autonegotiation disabled",
2099 dev->data->port_id);
2103 rte_intr_disable(intr_handle);
2105 if ((rte_intr_cap_multiple(intr_handle) ||
2106 !RTE_ETH_DEV_SRIOV(dev).active) &&
2107 dev->data->dev_conf.intr_conf.rxq != 0) {
2108 intr_vector = dev->data->nb_rx_queues;
2109 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2114 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2115 intr_handle->intr_vec =
2116 rte_zmalloc("intr_vec",
2117 dev->data->nb_rx_queues * sizeof(int),
2119 if (!intr_handle->intr_vec) {
2121 "Failed to allocate %d rx_queues intr_vec",
2122 dev->data->nb_rx_queues);
2127 /* Initialize VSI */
2128 ret = i40e_dev_rxtx_init(pf);
2129 if (ret != I40E_SUCCESS) {
2130 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2134 /* Map queues with MSIX interrupt */
2135 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2136 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2137 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2138 i40e_vsi_enable_queues_intr(main_vsi);
2140 /* Map VMDQ VSI queues with MSIX interrupt */
2141 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2142 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2143 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2144 I40E_ITR_INDEX_DEFAULT);
2145 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2148 /* enable FDIR MSIX interrupt */
2149 if (pf->fdir.fdir_vsi) {
2150 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2151 I40E_ITR_INDEX_NONE);
2152 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2155 /* Enable all queues which have been configured */
2156 ret = i40e_dev_switch_queues(pf, TRUE);
2157 if (ret != I40E_SUCCESS) {
2158 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2162 /* Enable receiving broadcast packets */
2163 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2164 if (ret != I40E_SUCCESS)
2165 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2167 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2168 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2170 if (ret != I40E_SUCCESS)
2171 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2174 /* Enable the VLAN promiscuous mode. */
2176 for (i = 0; i < pf->vf_num; i++) {
2177 vsi = pf->vfs[i].vsi;
2178 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2183 /* Enable mac loopback mode */
2184 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2185 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2186 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2187 if (ret != I40E_SUCCESS) {
2188 PMD_DRV_LOG(ERR, "fail to set loopback link");
2193 /* Apply link configure */
2194 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2195 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2196 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2197 ETH_LINK_SPEED_40G)) {
2198 PMD_DRV_LOG(ERR, "Invalid link setting");
2201 ret = i40e_apply_link_speed(dev);
2202 if (I40E_SUCCESS != ret) {
2203 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2207 if (!rte_intr_allow_others(intr_handle)) {
2208 rte_intr_callback_unregister(intr_handle,
2209 i40e_dev_interrupt_handler,
2211 /* configure and enable device interrupt */
2212 i40e_pf_config_irq0(hw, FALSE);
2213 i40e_pf_enable_irq0(hw);
2215 if (dev->data->dev_conf.intr_conf.lsc != 0)
2217 "lsc won't enable because of no intr multiplex");
2219 ret = i40e_aq_set_phy_int_mask(hw,
2220 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2221 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2222 I40E_AQ_EVENT_MEDIA_NA), NULL);
2223 if (ret != I40E_SUCCESS)
2224 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2226 /* Call get_link_info aq commond to enable/disable LSE */
2227 i40e_dev_link_update(dev, 0);
2230 /* enable uio intr after callback register */
2231 rte_intr_enable(intr_handle);
2233 i40e_filter_restore(pf);
2235 if (pf->tm_conf.root && !pf->tm_conf.committed)
2236 PMD_DRV_LOG(WARNING,
2237 "please call hierarchy_commit() "
2238 "before starting the port");
2240 return I40E_SUCCESS;
2243 i40e_dev_switch_queues(pf, FALSE);
2244 i40e_dev_clear_queues(dev);
2250 i40e_dev_stop(struct rte_eth_dev *dev)
2252 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2253 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254 struct i40e_vsi *main_vsi = pf->main_vsi;
2255 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2256 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2259 if (hw->adapter_stopped == 1)
2261 /* Disable all queues */
2262 i40e_dev_switch_queues(pf, FALSE);
2264 /* un-map queues with interrupt registers */
2265 i40e_vsi_disable_queues_intr(main_vsi);
2266 i40e_vsi_queues_unbind_intr(main_vsi);
2268 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2269 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2270 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2273 if (pf->fdir.fdir_vsi) {
2274 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2275 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2277 /* Clear all queues and release memory */
2278 i40e_dev_clear_queues(dev);
2281 i40e_dev_set_link_down(dev);
2283 if (!rte_intr_allow_others(intr_handle))
2284 /* resume to the default handler */
2285 rte_intr_callback_register(intr_handle,
2286 i40e_dev_interrupt_handler,
2289 /* Clean datapath event and queue/vec mapping */
2290 rte_intr_efd_disable(intr_handle);
2291 if (intr_handle->intr_vec) {
2292 rte_free(intr_handle->intr_vec);
2293 intr_handle->intr_vec = NULL;
2296 /* reset hierarchy commit */
2297 pf->tm_conf.committed = false;
2299 hw->adapter_stopped = 1;
2303 i40e_dev_close(struct rte_eth_dev *dev)
2305 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2306 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2308 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2309 struct i40e_mirror_rule *p_mirror;
2314 PMD_INIT_FUNC_TRACE();
2318 /* Remove all mirror rules */
2319 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2320 ret = i40e_aq_del_mirror_rule(hw,
2321 pf->main_vsi->veb->seid,
2322 p_mirror->rule_type,
2324 p_mirror->num_entries,
2327 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2328 "status = %d, aq_err = %d.", ret,
2329 hw->aq.asq_last_status);
2331 /* remove mirror software resource anyway */
2332 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2334 pf->nb_mirror_rule--;
2337 i40e_dev_free_queues(dev);
2339 /* Disable interrupt */
2340 i40e_pf_disable_irq0(hw);
2341 rte_intr_disable(intr_handle);
2343 /* shutdown and destroy the HMC */
2344 i40e_shutdown_lan_hmc(hw);
2346 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2347 i40e_vsi_release(pf->vmdq[i].vsi);
2348 pf->vmdq[i].vsi = NULL;
2353 /* release all the existing VSIs and VEBs */
2354 i40e_fdir_teardown(pf);
2355 i40e_vsi_release(pf->main_vsi);
2357 /* shutdown the adminq */
2358 i40e_aq_queue_shutdown(hw, true);
2359 i40e_shutdown_adminq(hw);
2361 i40e_res_pool_destroy(&pf->qp_pool);
2362 i40e_res_pool_destroy(&pf->msix_pool);
2364 /* Disable flexible payload in global configuration */
2365 if (!pf->support_multi_driver)
2366 i40e_flex_payload_reg_set_default(hw);
2368 /* force a PF reset to clean anything leftover */
2369 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2370 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2371 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2372 I40E_WRITE_FLUSH(hw);
2376 * Reset PF device only to re-initialize resources in PMD layer
2379 i40e_dev_reset(struct rte_eth_dev *dev)
2383 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2384 * its VF to make them align with it. The detailed notification
2385 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2386 * To avoid unexpected behavior in VF, currently reset of PF with
2387 * SR-IOV activation is not supported. It might be supported later.
2389 if (dev->data->sriov.active)
2392 ret = eth_i40e_dev_uninit(dev);
2396 ret = eth_i40e_dev_init(dev, NULL);
2402 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2404 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2405 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406 struct i40e_vsi *vsi = pf->main_vsi;
2409 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2411 if (status != I40E_SUCCESS)
2412 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2414 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2416 if (status != I40E_SUCCESS)
2417 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2422 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2424 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2425 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426 struct i40e_vsi *vsi = pf->main_vsi;
2429 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2431 if (status != I40E_SUCCESS)
2432 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2434 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2436 if (status != I40E_SUCCESS)
2437 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2441 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2443 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2444 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445 struct i40e_vsi *vsi = pf->main_vsi;
2448 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2449 if (ret != I40E_SUCCESS)
2450 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2454 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2456 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2457 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458 struct i40e_vsi *vsi = pf->main_vsi;
2461 if (dev->data->promiscuous == 1)
2462 return; /* must remain in all_multicast mode */
2464 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2465 vsi->seid, FALSE, NULL);
2466 if (ret != I40E_SUCCESS)
2467 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2471 * Set device link up.
2474 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2476 /* re-apply link speed setting */
2477 return i40e_apply_link_speed(dev);
2481 * Set device link down.
2484 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2486 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2487 uint8_t abilities = 0;
2488 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2491 return i40e_phy_conf_link(hw, abilities, speed, false);
2494 static __rte_always_inline void
2495 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2497 /* Link status registers and values*/
2498 #define I40E_PRTMAC_LINKSTA 0x001E2420
2499 #define I40E_REG_LINK_UP 0x40000080
2500 #define I40E_PRTMAC_MACC 0x001E24E0
2501 #define I40E_REG_MACC_25GB 0x00020000
2502 #define I40E_REG_SPEED_MASK 0x38000000
2503 #define I40E_REG_SPEED_100MB 0x00000000
2504 #define I40E_REG_SPEED_1GB 0x08000000
2505 #define I40E_REG_SPEED_10GB 0x10000000
2506 #define I40E_REG_SPEED_20GB 0x20000000
2507 #define I40E_REG_SPEED_25_40GB 0x18000000
2508 uint32_t link_speed;
2511 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2512 link_speed = reg_val & I40E_REG_SPEED_MASK;
2513 reg_val &= I40E_REG_LINK_UP;
2514 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2516 if (unlikely(link->link_status == 0))
2519 /* Parse the link status */
2520 switch (link_speed) {
2521 case I40E_REG_SPEED_100MB:
2522 link->link_speed = ETH_SPEED_NUM_100M;
2524 case I40E_REG_SPEED_1GB:
2525 link->link_speed = ETH_SPEED_NUM_1G;
2527 case I40E_REG_SPEED_10GB:
2528 link->link_speed = ETH_SPEED_NUM_10G;
2530 case I40E_REG_SPEED_20GB:
2531 link->link_speed = ETH_SPEED_NUM_20G;
2533 case I40E_REG_SPEED_25_40GB:
2534 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2536 if (reg_val & I40E_REG_MACC_25GB)
2537 link->link_speed = ETH_SPEED_NUM_25G;
2539 link->link_speed = ETH_SPEED_NUM_40G;
2543 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2548 static __rte_always_inline void
2549 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2552 #define CHECK_INTERVAL 100 /* 100ms */
2553 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2554 uint32_t rep_cnt = MAX_REPEAT_TIME;
2555 struct i40e_link_status link_status;
2558 memset(&link_status, 0, sizeof(link_status));
2561 memset(&link_status, 0, sizeof(link_status));
2563 /* Get link status information from hardware */
2564 status = i40e_aq_get_link_info(hw, enable_lse,
2565 &link_status, NULL);
2566 if (unlikely(status != I40E_SUCCESS)) {
2567 link->link_speed = ETH_SPEED_NUM_100M;
2568 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2569 PMD_DRV_LOG(ERR, "Failed to get link info");
2573 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2574 if (unlikely(link->link_status != 0))
2577 rte_delay_ms(CHECK_INTERVAL);
2578 } while (--rep_cnt);
2580 /* Parse the link status */
2581 switch (link_status.link_speed) {
2582 case I40E_LINK_SPEED_100MB:
2583 link->link_speed = ETH_SPEED_NUM_100M;
2585 case I40E_LINK_SPEED_1GB:
2586 link->link_speed = ETH_SPEED_NUM_1G;
2588 case I40E_LINK_SPEED_10GB:
2589 link->link_speed = ETH_SPEED_NUM_10G;
2591 case I40E_LINK_SPEED_20GB:
2592 link->link_speed = ETH_SPEED_NUM_20G;
2594 case I40E_LINK_SPEED_25GB:
2595 link->link_speed = ETH_SPEED_NUM_25G;
2597 case I40E_LINK_SPEED_40GB:
2598 link->link_speed = ETH_SPEED_NUM_40G;
2601 link->link_speed = ETH_SPEED_NUM_100M;
2607 i40e_dev_link_update(struct rte_eth_dev *dev,
2608 int wait_to_complete)
2610 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2611 struct rte_eth_link link;
2612 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2615 memset(&link, 0, sizeof(link));
2617 /* i40e uses full duplex only */
2618 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2619 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2620 ETH_LINK_SPEED_FIXED);
2622 if (!wait_to_complete)
2623 update_link_no_wait(hw, &link);
2625 update_link_wait(hw, &link, enable_lse);
2627 ret = rte_eth_linkstatus_set(dev, &link);
2628 i40e_notify_all_vfs_link_status(dev);
2633 /* Get all the statistics of a VSI */
2635 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2637 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2638 struct i40e_eth_stats *nes = &vsi->eth_stats;
2639 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2640 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2642 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2643 vsi->offset_loaded, &oes->rx_bytes,
2645 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2646 vsi->offset_loaded, &oes->rx_unicast,
2648 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2649 vsi->offset_loaded, &oes->rx_multicast,
2650 &nes->rx_multicast);
2651 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2652 vsi->offset_loaded, &oes->rx_broadcast,
2653 &nes->rx_broadcast);
2654 /* exclude CRC bytes */
2655 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2656 nes->rx_broadcast) * ETHER_CRC_LEN;
2658 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2659 &oes->rx_discards, &nes->rx_discards);
2660 /* GLV_REPC not supported */
2661 /* GLV_RMPC not supported */
2662 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2663 &oes->rx_unknown_protocol,
2664 &nes->rx_unknown_protocol);
2665 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2666 vsi->offset_loaded, &oes->tx_bytes,
2668 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2669 vsi->offset_loaded, &oes->tx_unicast,
2671 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2672 vsi->offset_loaded, &oes->tx_multicast,
2673 &nes->tx_multicast);
2674 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2675 vsi->offset_loaded, &oes->tx_broadcast,
2676 &nes->tx_broadcast);
2677 /* GLV_TDPC not supported */
2678 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2679 &oes->tx_errors, &nes->tx_errors);
2680 vsi->offset_loaded = true;
2682 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2684 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2685 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2686 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2687 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2688 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2689 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2690 nes->rx_unknown_protocol);
2691 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2692 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2693 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2694 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2695 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2696 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2697 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2702 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2705 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2706 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2708 /* Get rx/tx bytes of internal transfer packets */
2709 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2710 I40E_GLV_GORCL(hw->port),
2712 &pf->internal_stats_offset.rx_bytes,
2713 &pf->internal_stats.rx_bytes);
2715 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2716 I40E_GLV_GOTCL(hw->port),
2718 &pf->internal_stats_offset.tx_bytes,
2719 &pf->internal_stats.tx_bytes);
2720 /* Get total internal rx packet count */
2721 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2722 I40E_GLV_UPRCL(hw->port),
2724 &pf->internal_stats_offset.rx_unicast,
2725 &pf->internal_stats.rx_unicast);
2726 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2727 I40E_GLV_MPRCL(hw->port),
2729 &pf->internal_stats_offset.rx_multicast,
2730 &pf->internal_stats.rx_multicast);
2731 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2732 I40E_GLV_BPRCL(hw->port),
2734 &pf->internal_stats_offset.rx_broadcast,
2735 &pf->internal_stats.rx_broadcast);
2736 /* Get total internal tx packet count */
2737 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2738 I40E_GLV_UPTCL(hw->port),
2740 &pf->internal_stats_offset.tx_unicast,
2741 &pf->internal_stats.tx_unicast);
2742 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2743 I40E_GLV_MPTCL(hw->port),
2745 &pf->internal_stats_offset.tx_multicast,
2746 &pf->internal_stats.tx_multicast);
2747 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2748 I40E_GLV_BPTCL(hw->port),
2750 &pf->internal_stats_offset.tx_broadcast,
2751 &pf->internal_stats.tx_broadcast);
2753 /* exclude CRC size */
2754 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2755 pf->internal_stats.rx_multicast +
2756 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2758 /* Get statistics of struct i40e_eth_stats */
2759 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2760 I40E_GLPRT_GORCL(hw->port),
2761 pf->offset_loaded, &os->eth.rx_bytes,
2763 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2764 I40E_GLPRT_UPRCL(hw->port),
2765 pf->offset_loaded, &os->eth.rx_unicast,
2766 &ns->eth.rx_unicast);
2767 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2768 I40E_GLPRT_MPRCL(hw->port),
2769 pf->offset_loaded, &os->eth.rx_multicast,
2770 &ns->eth.rx_multicast);
2771 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2772 I40E_GLPRT_BPRCL(hw->port),
2773 pf->offset_loaded, &os->eth.rx_broadcast,
2774 &ns->eth.rx_broadcast);
2775 /* Workaround: CRC size should not be included in byte statistics,
2776 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2778 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2779 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2781 /* exclude internal rx bytes
2782 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2783 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2785 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2787 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2788 ns->eth.rx_bytes = 0;
2790 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2792 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2793 ns->eth.rx_unicast = 0;
2795 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2797 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2798 ns->eth.rx_multicast = 0;
2800 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2802 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2803 ns->eth.rx_broadcast = 0;
2805 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2807 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2808 pf->offset_loaded, &os->eth.rx_discards,
2809 &ns->eth.rx_discards);
2810 /* GLPRT_REPC not supported */
2811 /* GLPRT_RMPC not supported */
2812 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2814 &os->eth.rx_unknown_protocol,
2815 &ns->eth.rx_unknown_protocol);
2816 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2817 I40E_GLPRT_GOTCL(hw->port),
2818 pf->offset_loaded, &os->eth.tx_bytes,
2820 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2821 I40E_GLPRT_UPTCL(hw->port),
2822 pf->offset_loaded, &os->eth.tx_unicast,
2823 &ns->eth.tx_unicast);
2824 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2825 I40E_GLPRT_MPTCL(hw->port),
2826 pf->offset_loaded, &os->eth.tx_multicast,
2827 &ns->eth.tx_multicast);
2828 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2829 I40E_GLPRT_BPTCL(hw->port),
2830 pf->offset_loaded, &os->eth.tx_broadcast,
2831 &ns->eth.tx_broadcast);
2832 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2833 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2835 /* exclude internal tx bytes
2836 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2837 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2839 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2841 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2842 ns->eth.tx_bytes = 0;
2844 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2846 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2847 ns->eth.tx_unicast = 0;
2849 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2851 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2852 ns->eth.tx_multicast = 0;
2854 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2856 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2857 ns->eth.tx_broadcast = 0;
2859 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2861 /* GLPRT_TEPC not supported */
2863 /* additional port specific stats */
2864 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2865 pf->offset_loaded, &os->tx_dropped_link_down,
2866 &ns->tx_dropped_link_down);
2867 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2868 pf->offset_loaded, &os->crc_errors,
2870 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2871 pf->offset_loaded, &os->illegal_bytes,
2872 &ns->illegal_bytes);
2873 /* GLPRT_ERRBC not supported */
2874 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2875 pf->offset_loaded, &os->mac_local_faults,
2876 &ns->mac_local_faults);
2877 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2878 pf->offset_loaded, &os->mac_remote_faults,
2879 &ns->mac_remote_faults);
2880 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2881 pf->offset_loaded, &os->rx_length_errors,
2882 &ns->rx_length_errors);
2883 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2884 pf->offset_loaded, &os->link_xon_rx,
2886 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2887 pf->offset_loaded, &os->link_xoff_rx,
2889 for (i = 0; i < 8; i++) {
2890 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2892 &os->priority_xon_rx[i],
2893 &ns->priority_xon_rx[i]);
2894 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2896 &os->priority_xoff_rx[i],
2897 &ns->priority_xoff_rx[i]);
2899 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2900 pf->offset_loaded, &os->link_xon_tx,
2902 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2903 pf->offset_loaded, &os->link_xoff_tx,
2905 for (i = 0; i < 8; i++) {
2906 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2908 &os->priority_xon_tx[i],
2909 &ns->priority_xon_tx[i]);
2910 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2912 &os->priority_xoff_tx[i],
2913 &ns->priority_xoff_tx[i]);
2914 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2916 &os->priority_xon_2_xoff[i],
2917 &ns->priority_xon_2_xoff[i]);
2919 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2920 I40E_GLPRT_PRC64L(hw->port),
2921 pf->offset_loaded, &os->rx_size_64,
2923 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2924 I40E_GLPRT_PRC127L(hw->port),
2925 pf->offset_loaded, &os->rx_size_127,
2927 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2928 I40E_GLPRT_PRC255L(hw->port),
2929 pf->offset_loaded, &os->rx_size_255,
2931 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2932 I40E_GLPRT_PRC511L(hw->port),
2933 pf->offset_loaded, &os->rx_size_511,
2935 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2936 I40E_GLPRT_PRC1023L(hw->port),
2937 pf->offset_loaded, &os->rx_size_1023,
2939 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2940 I40E_GLPRT_PRC1522L(hw->port),
2941 pf->offset_loaded, &os->rx_size_1522,
2943 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2944 I40E_GLPRT_PRC9522L(hw->port),
2945 pf->offset_loaded, &os->rx_size_big,
2947 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2948 pf->offset_loaded, &os->rx_undersize,
2950 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2951 pf->offset_loaded, &os->rx_fragments,
2953 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2954 pf->offset_loaded, &os->rx_oversize,
2956 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2957 pf->offset_loaded, &os->rx_jabber,
2959 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2960 I40E_GLPRT_PTC64L(hw->port),
2961 pf->offset_loaded, &os->tx_size_64,
2963 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2964 I40E_GLPRT_PTC127L(hw->port),
2965 pf->offset_loaded, &os->tx_size_127,
2967 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2968 I40E_GLPRT_PTC255L(hw->port),
2969 pf->offset_loaded, &os->tx_size_255,
2971 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2972 I40E_GLPRT_PTC511L(hw->port),
2973 pf->offset_loaded, &os->tx_size_511,
2975 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2976 I40E_GLPRT_PTC1023L(hw->port),
2977 pf->offset_loaded, &os->tx_size_1023,
2979 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2980 I40E_GLPRT_PTC1522L(hw->port),
2981 pf->offset_loaded, &os->tx_size_1522,
2983 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2984 I40E_GLPRT_PTC9522L(hw->port),
2985 pf->offset_loaded, &os->tx_size_big,
2987 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2989 &os->fd_sb_match, &ns->fd_sb_match);
2990 /* GLPRT_MSPDC not supported */
2991 /* GLPRT_XEC not supported */
2993 pf->offset_loaded = true;
2996 i40e_update_vsi_stats(pf->main_vsi);
2999 /* Get all statistics of a port */
3001 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3004 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3008 /* call read registers - updates values, now write them to struct */
3009 i40e_read_stats_registers(pf, hw);
3011 stats->ipackets = ns->eth.rx_unicast +
3012 ns->eth.rx_multicast +
3013 ns->eth.rx_broadcast -
3014 ns->eth.rx_discards -
3015 pf->main_vsi->eth_stats.rx_discards;
3016 stats->opackets = ns->eth.tx_unicast +
3017 ns->eth.tx_multicast +
3018 ns->eth.tx_broadcast;
3019 stats->ibytes = ns->eth.rx_bytes;
3020 stats->obytes = ns->eth.tx_bytes;
3021 stats->oerrors = ns->eth.tx_errors +
3022 pf->main_vsi->eth_stats.tx_errors;
3025 stats->imissed = ns->eth.rx_discards +
3026 pf->main_vsi->eth_stats.rx_discards;
3027 stats->ierrors = ns->crc_errors +
3028 ns->rx_length_errors + ns->rx_undersize +
3029 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3031 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3032 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3033 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3034 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3035 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3036 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3037 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3038 ns->eth.rx_unknown_protocol);
3039 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3040 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3041 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3042 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3043 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3044 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3046 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3047 ns->tx_dropped_link_down);
3048 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3049 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3051 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3052 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3053 ns->mac_local_faults);
3054 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3055 ns->mac_remote_faults);
3056 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3057 ns->rx_length_errors);
3058 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3059 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3060 for (i = 0; i < 8; i++) {
3061 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3062 i, ns->priority_xon_rx[i]);
3063 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3064 i, ns->priority_xoff_rx[i]);
3066 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3067 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3068 for (i = 0; i < 8; i++) {
3069 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3070 i, ns->priority_xon_tx[i]);
3071 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3072 i, ns->priority_xoff_tx[i]);
3073 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3074 i, ns->priority_xon_2_xoff[i]);
3076 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3077 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3078 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3079 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3080 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3081 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3082 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3083 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3084 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3085 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3086 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3087 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3088 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3089 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3090 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3091 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3092 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3093 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3094 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3095 ns->mac_short_packet_dropped);
3096 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3097 ns->checksum_error);
3098 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3099 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3103 /* Reset the statistics */
3105 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3107 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3108 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3110 /* Mark PF and VSI stats to update the offset, aka "reset" */
3111 pf->offset_loaded = false;
3113 pf->main_vsi->offset_loaded = false;
3115 /* read the stats, reading current register values into offset */
3116 i40e_read_stats_registers(pf, hw);
3120 i40e_xstats_calc_num(void)
3122 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3123 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3124 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3127 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3128 struct rte_eth_xstat_name *xstats_names,
3129 __rte_unused unsigned limit)
3134 if (xstats_names == NULL)
3135 return i40e_xstats_calc_num();
3137 /* Note: limit checked in rte_eth_xstats_names() */
3139 /* Get stats from i40e_eth_stats struct */
3140 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3141 snprintf(xstats_names[count].name,
3142 sizeof(xstats_names[count].name),
3143 "%s", rte_i40e_stats_strings[i].name);
3147 /* Get individiual stats from i40e_hw_port struct */
3148 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3149 snprintf(xstats_names[count].name,
3150 sizeof(xstats_names[count].name),
3151 "%s", rte_i40e_hw_port_strings[i].name);
3155 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3156 for (prio = 0; prio < 8; prio++) {
3157 snprintf(xstats_names[count].name,
3158 sizeof(xstats_names[count].name),
3159 "rx_priority%u_%s", prio,
3160 rte_i40e_rxq_prio_strings[i].name);
3165 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3166 for (prio = 0; prio < 8; prio++) {
3167 snprintf(xstats_names[count].name,
3168 sizeof(xstats_names[count].name),
3169 "tx_priority%u_%s", prio,
3170 rte_i40e_txq_prio_strings[i].name);
3178 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183 unsigned i, count, prio;
3184 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3186 count = i40e_xstats_calc_num();
3190 i40e_read_stats_registers(pf, hw);
3197 /* Get stats from i40e_eth_stats struct */
3198 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3199 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3200 rte_i40e_stats_strings[i].offset);
3201 xstats[count].id = count;
3205 /* Get individiual stats from i40e_hw_port struct */
3206 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3207 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3208 rte_i40e_hw_port_strings[i].offset);
3209 xstats[count].id = count;
3213 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3214 for (prio = 0; prio < 8; prio++) {
3215 xstats[count].value =
3216 *(uint64_t *)(((char *)hw_stats) +
3217 rte_i40e_rxq_prio_strings[i].offset +
3218 (sizeof(uint64_t) * prio));
3219 xstats[count].id = count;
3224 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3225 for (prio = 0; prio < 8; prio++) {
3226 xstats[count].value =
3227 *(uint64_t *)(((char *)hw_stats) +
3228 rte_i40e_txq_prio_strings[i].offset +
3229 (sizeof(uint64_t) * prio));
3230 xstats[count].id = count;
3239 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3240 __rte_unused uint16_t queue_id,
3241 __rte_unused uint8_t stat_idx,
3242 __rte_unused uint8_t is_rx)
3244 PMD_INIT_FUNC_TRACE();
3250 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3252 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3258 full_ver = hw->nvm.oem_ver;
3259 ver = (u8)(full_ver >> 24);
3260 build = (u16)((full_ver >> 8) & 0xffff);
3261 patch = (u8)(full_ver & 0xff);
3263 ret = snprintf(fw_version, fw_size,
3264 "%d.%d%d 0x%08x %d.%d.%d",
3265 ((hw->nvm.version >> 12) & 0xf),
3266 ((hw->nvm.version >> 4) & 0xff),
3267 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3270 ret += 1; /* add the size of '\0' */
3271 if (fw_size < (u32)ret)
3278 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3280 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3281 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282 struct i40e_vsi *vsi = pf->main_vsi;
3283 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3285 dev_info->max_rx_queues = vsi->nb_qps;
3286 dev_info->max_tx_queues = vsi->nb_qps;
3287 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3288 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3289 dev_info->max_mac_addrs = vsi->max_macaddrs;
3290 dev_info->max_vfs = pci_dev->max_vfs;
3291 dev_info->rx_queue_offload_capa = 0;
3292 dev_info->rx_offload_capa =
3293 DEV_RX_OFFLOAD_VLAN_STRIP |
3294 DEV_RX_OFFLOAD_QINQ_STRIP |
3295 DEV_RX_OFFLOAD_IPV4_CKSUM |
3296 DEV_RX_OFFLOAD_UDP_CKSUM |
3297 DEV_RX_OFFLOAD_TCP_CKSUM |
3298 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3299 DEV_RX_OFFLOAD_CRC_STRIP |
3300 DEV_RX_OFFLOAD_VLAN_EXTEND |
3301 DEV_RX_OFFLOAD_VLAN_FILTER |
3302 DEV_RX_OFFLOAD_JUMBO_FRAME;
3304 dev_info->tx_queue_offload_capa = 0;
3305 dev_info->tx_offload_capa =
3306 DEV_TX_OFFLOAD_VLAN_INSERT |
3307 DEV_TX_OFFLOAD_QINQ_INSERT |
3308 DEV_TX_OFFLOAD_IPV4_CKSUM |
3309 DEV_TX_OFFLOAD_UDP_CKSUM |
3310 DEV_TX_OFFLOAD_TCP_CKSUM |
3311 DEV_TX_OFFLOAD_SCTP_CKSUM |
3312 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3313 DEV_TX_OFFLOAD_TCP_TSO |
3314 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3315 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3316 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3317 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3318 DEV_TX_OFFLOAD_MULTI_SEGS;
3319 dev_info->dev_capa =
3320 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3321 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3323 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3325 dev_info->reta_size = pf->hash_lut_size;
3326 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3328 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3330 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3331 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3332 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3334 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3339 dev_info->default_txconf = (struct rte_eth_txconf) {
3341 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3342 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3343 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3345 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3346 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3350 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3351 .nb_max = I40E_MAX_RING_DESC,
3352 .nb_min = I40E_MIN_RING_DESC,
3353 .nb_align = I40E_ALIGN_RING_DESC,
3356 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3357 .nb_max = I40E_MAX_RING_DESC,
3358 .nb_min = I40E_MIN_RING_DESC,
3359 .nb_align = I40E_ALIGN_RING_DESC,
3360 .nb_seg_max = I40E_TX_MAX_SEG,
3361 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3364 if (pf->flags & I40E_FLAG_VMDQ) {
3365 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3366 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3367 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3368 pf->max_nb_vmdq_vsi;
3369 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3370 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3371 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3374 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3376 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3377 dev_info->default_rxportconf.nb_queues = 2;
3378 dev_info->default_txportconf.nb_queues = 2;
3379 if (dev->data->nb_rx_queues == 1)
3380 dev_info->default_rxportconf.ring_size = 2048;
3382 dev_info->default_rxportconf.ring_size = 1024;
3383 if (dev->data->nb_tx_queues == 1)
3384 dev_info->default_txportconf.ring_size = 1024;
3386 dev_info->default_txportconf.ring_size = 512;
3388 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3390 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3391 dev_info->default_rxportconf.nb_queues = 1;
3392 dev_info->default_txportconf.nb_queues = 1;
3393 dev_info->default_rxportconf.ring_size = 256;
3394 dev_info->default_txportconf.ring_size = 256;
3397 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3398 dev_info->default_rxportconf.nb_queues = 1;
3399 dev_info->default_txportconf.nb_queues = 1;
3400 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3401 dev_info->default_rxportconf.ring_size = 512;
3402 dev_info->default_txportconf.ring_size = 256;
3404 dev_info->default_rxportconf.ring_size = 256;
3405 dev_info->default_txportconf.ring_size = 256;
3408 dev_info->default_rxportconf.burst_size = 32;
3409 dev_info->default_txportconf.burst_size = 32;
3413 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3415 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3416 struct i40e_vsi *vsi = pf->main_vsi;
3417 PMD_INIT_FUNC_TRACE();
3420 return i40e_vsi_add_vlan(vsi, vlan_id);
3422 return i40e_vsi_delete_vlan(vsi, vlan_id);
3426 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3427 enum rte_vlan_type vlan_type,
3428 uint16_t tpid, int qinq)
3430 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3433 uint16_t reg_id = 3;
3437 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3441 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3443 if (ret != I40E_SUCCESS) {
3445 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3450 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3453 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3454 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3455 if (reg_r == reg_w) {
3456 PMD_DRV_LOG(DEBUG, "No need to write");
3460 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3462 if (ret != I40E_SUCCESS) {
3464 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3469 "Global register 0x%08x is changed with value 0x%08x",
3470 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3476 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3477 enum rte_vlan_type vlan_type,
3480 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3482 int qinq = dev->data->dev_conf.rxmode.offloads &
3483 DEV_RX_OFFLOAD_VLAN_EXTEND;
3486 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3487 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3488 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3490 "Unsupported vlan type.");
3494 if (pf->support_multi_driver) {
3495 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3499 /* 802.1ad frames ability is added in NVM API 1.7*/
3500 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3502 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3503 hw->first_tag = rte_cpu_to_le_16(tpid);
3504 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3505 hw->second_tag = rte_cpu_to_le_16(tpid);
3507 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3508 hw->second_tag = rte_cpu_to_le_16(tpid);
3510 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3511 if (ret != I40E_SUCCESS) {
3513 "Set switch config failed aq_err: %d",
3514 hw->aq.asq_last_status);
3518 /* If NVM API < 1.7, keep the register setting */
3519 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3521 i40e_global_cfg_warning(I40E_WARNING_TPID);
3527 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3529 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3530 struct i40e_vsi *vsi = pf->main_vsi;
3531 struct rte_eth_rxmode *rxmode;
3533 rxmode = &dev->data->dev_conf.rxmode;
3534 if (mask & ETH_VLAN_FILTER_MASK) {
3535 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3536 i40e_vsi_config_vlan_filter(vsi, TRUE);
3538 i40e_vsi_config_vlan_filter(vsi, FALSE);
3541 if (mask & ETH_VLAN_STRIP_MASK) {
3542 /* Enable or disable VLAN stripping */
3543 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3544 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3546 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3549 if (mask & ETH_VLAN_EXTEND_MASK) {
3550 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3551 i40e_vsi_config_double_vlan(vsi, TRUE);
3552 /* Set global registers with default ethertype. */
3553 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3555 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3559 i40e_vsi_config_double_vlan(vsi, FALSE);
3566 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3567 __rte_unused uint16_t queue,
3568 __rte_unused int on)
3570 PMD_INIT_FUNC_TRACE();
3574 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3576 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3577 struct i40e_vsi *vsi = pf->main_vsi;
3578 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3579 struct i40e_vsi_vlan_pvid_info info;
3581 memset(&info, 0, sizeof(info));
3584 info.config.pvid = pvid;
3586 info.config.reject.tagged =
3587 data->dev_conf.txmode.hw_vlan_reject_tagged;
3588 info.config.reject.untagged =
3589 data->dev_conf.txmode.hw_vlan_reject_untagged;
3592 return i40e_vsi_vlan_pvid_set(vsi, &info);
3596 i40e_dev_led_on(struct rte_eth_dev *dev)
3598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599 uint32_t mode = i40e_led_get(hw);
3602 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3608 i40e_dev_led_off(struct rte_eth_dev *dev)
3610 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611 uint32_t mode = i40e_led_get(hw);
3614 i40e_led_set(hw, 0, false);
3620 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3622 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3625 fc_conf->pause_time = pf->fc_conf.pause_time;
3627 /* read out from register, in case they are modified by other port */
3628 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3629 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3630 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3631 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3633 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3634 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3636 /* Return current mode according to actual setting*/
3637 switch (hw->fc.current_mode) {
3639 fc_conf->mode = RTE_FC_FULL;
3641 case I40E_FC_TX_PAUSE:
3642 fc_conf->mode = RTE_FC_TX_PAUSE;
3644 case I40E_FC_RX_PAUSE:
3645 fc_conf->mode = RTE_FC_RX_PAUSE;
3649 fc_conf->mode = RTE_FC_NONE;
3656 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3658 uint32_t mflcn_reg, fctrl_reg, reg;
3659 uint32_t max_high_water;
3660 uint8_t i, aq_failure;
3664 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3665 [RTE_FC_NONE] = I40E_FC_NONE,
3666 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3667 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3668 [RTE_FC_FULL] = I40E_FC_FULL
3671 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3673 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3674 if ((fc_conf->high_water > max_high_water) ||
3675 (fc_conf->high_water < fc_conf->low_water)) {
3677 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3682 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3683 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3684 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3686 pf->fc_conf.pause_time = fc_conf->pause_time;
3687 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3688 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3690 PMD_INIT_FUNC_TRACE();
3692 /* All the link flow control related enable/disable register
3693 * configuration is handle by the F/W
3695 err = i40e_set_fc(hw, &aq_failure, true);
3699 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3700 /* Configure flow control refresh threshold,
3701 * the value for stat_tx_pause_refresh_timer[8]
3702 * is used for global pause operation.
3706 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3707 pf->fc_conf.pause_time);
3709 /* configure the timer value included in transmitted pause
3711 * the value for stat_tx_pause_quanta[8] is used for global
3714 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3715 pf->fc_conf.pause_time);
3717 fctrl_reg = I40E_READ_REG(hw,
3718 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3720 if (fc_conf->mac_ctrl_frame_fwd != 0)
3721 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3723 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3725 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3728 /* Configure pause time (2 TCs per register) */
3729 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3730 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3731 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3733 /* Configure flow control refresh threshold value */
3734 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3735 pf->fc_conf.pause_time / 2);
3737 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3739 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3740 *depending on configuration
3742 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3743 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3744 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3746 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3747 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3750 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3753 if (!pf->support_multi_driver) {
3754 /* config water marker both based on the packets and bytes */
3755 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3756 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3757 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3758 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3759 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3760 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3761 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3762 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3764 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3765 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3767 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3770 "Water marker configuration is not supported.");
3773 I40E_WRITE_FLUSH(hw);
3779 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3780 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3782 PMD_INIT_FUNC_TRACE();
3787 /* Add a MAC address, and update filters */
3789 i40e_macaddr_add(struct rte_eth_dev *dev,
3790 struct ether_addr *mac_addr,
3791 __rte_unused uint32_t index,
3794 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3795 struct i40e_mac_filter_info mac_filter;
3796 struct i40e_vsi *vsi;
3797 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3800 /* If VMDQ not enabled or configured, return */
3801 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3802 !pf->nb_cfg_vmdq_vsi)) {
3803 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3804 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3809 if (pool > pf->nb_cfg_vmdq_vsi) {
3810 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3811 pool, pf->nb_cfg_vmdq_vsi);
3815 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3816 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3817 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3819 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3824 vsi = pf->vmdq[pool - 1].vsi;
3826 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3827 if (ret != I40E_SUCCESS) {
3828 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3834 /* Remove a MAC address, and update filters */
3836 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3838 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3839 struct i40e_vsi *vsi;
3840 struct rte_eth_dev_data *data = dev->data;
3841 struct ether_addr *macaddr;
3846 macaddr = &(data->mac_addrs[index]);
3848 pool_sel = dev->data->mac_pool_sel[index];
3850 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3851 if (pool_sel & (1ULL << i)) {
3855 /* No VMDQ pool enabled or configured */
3856 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3857 (i > pf->nb_cfg_vmdq_vsi)) {
3859 "No VMDQ pool enabled/configured");
3862 vsi = pf->vmdq[i - 1].vsi;
3864 ret = i40e_vsi_delete_mac(vsi, macaddr);
3867 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3874 /* Set perfect match or hash match of MAC and VLAN for a VF */
3876 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3877 struct rte_eth_mac_filter *filter,
3881 struct i40e_mac_filter_info mac_filter;
3882 struct ether_addr old_mac;
3883 struct ether_addr *new_mac;
3884 struct i40e_pf_vf *vf = NULL;
3889 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3892 hw = I40E_PF_TO_HW(pf);
3894 if (filter == NULL) {
3895 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3899 new_mac = &filter->mac_addr;
3901 if (is_zero_ether_addr(new_mac)) {
3902 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3906 vf_id = filter->dst_id;
3908 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3909 PMD_DRV_LOG(ERR, "Invalid argument.");
3912 vf = &pf->vfs[vf_id];
3914 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3915 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3920 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3921 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3923 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3926 mac_filter.filter_type = filter->filter_type;
3927 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3928 if (ret != I40E_SUCCESS) {
3929 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3932 ether_addr_copy(new_mac, &pf->dev_addr);
3934 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3936 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3937 if (ret != I40E_SUCCESS) {
3938 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3942 /* Clear device address as it has been removed */
3943 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3944 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3950 /* MAC filter handle */
3952 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3956 struct rte_eth_mac_filter *filter;
3957 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3958 int ret = I40E_NOT_SUPPORTED;
3960 filter = (struct rte_eth_mac_filter *)(arg);
3962 switch (filter_op) {
3963 case RTE_ETH_FILTER_NOP:
3966 case RTE_ETH_FILTER_ADD:
3967 i40e_pf_disable_irq0(hw);
3969 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3970 i40e_pf_enable_irq0(hw);
3972 case RTE_ETH_FILTER_DELETE:
3973 i40e_pf_disable_irq0(hw);
3975 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3976 i40e_pf_enable_irq0(hw);
3979 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3980 ret = I40E_ERR_PARAM;
3988 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3990 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3991 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3998 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3999 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4002 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4006 uint32_t *lut_dw = (uint32_t *)lut;
4007 uint16_t i, lut_size_dw = lut_size / 4;
4009 if (vsi->type == I40E_VSI_SRIOV) {
4010 for (i = 0; i <= lut_size_dw; i++) {
4011 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4012 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4015 for (i = 0; i < lut_size_dw; i++)
4016 lut_dw[i] = I40E_READ_REG(hw,
4025 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4034 pf = I40E_VSI_TO_PF(vsi);
4035 hw = I40E_VSI_TO_HW(vsi);
4037 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4038 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4041 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4045 uint32_t *lut_dw = (uint32_t *)lut;
4046 uint16_t i, lut_size_dw = lut_size / 4;
4048 if (vsi->type == I40E_VSI_SRIOV) {
4049 for (i = 0; i < lut_size_dw; i++)
4052 I40E_VFQF_HLUT1(i, vsi->user_param),
4055 for (i = 0; i < lut_size_dw; i++)
4056 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4059 I40E_WRITE_FLUSH(hw);
4066 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4067 struct rte_eth_rss_reta_entry64 *reta_conf,
4070 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4071 uint16_t i, lut_size = pf->hash_lut_size;
4072 uint16_t idx, shift;
4076 if (reta_size != lut_size ||
4077 reta_size > ETH_RSS_RETA_SIZE_512) {
4079 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4080 reta_size, lut_size);
4084 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4086 PMD_DRV_LOG(ERR, "No memory can be allocated");
4089 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4092 for (i = 0; i < reta_size; i++) {
4093 idx = i / RTE_RETA_GROUP_SIZE;
4094 shift = i % RTE_RETA_GROUP_SIZE;
4095 if (reta_conf[idx].mask & (1ULL << shift))
4096 lut[i] = reta_conf[idx].reta[shift];
4098 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4107 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4108 struct rte_eth_rss_reta_entry64 *reta_conf,
4111 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4112 uint16_t i, lut_size = pf->hash_lut_size;
4113 uint16_t idx, shift;
4117 if (reta_size != lut_size ||
4118 reta_size > ETH_RSS_RETA_SIZE_512) {
4120 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4121 reta_size, lut_size);
4125 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4127 PMD_DRV_LOG(ERR, "No memory can be allocated");
4131 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4134 for (i = 0; i < reta_size; i++) {
4135 idx = i / RTE_RETA_GROUP_SIZE;
4136 shift = i % RTE_RETA_GROUP_SIZE;
4137 if (reta_conf[idx].mask & (1ULL << shift))
4138 reta_conf[idx].reta[shift] = lut[i];
4148 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4149 * @hw: pointer to the HW structure
4150 * @mem: pointer to mem struct to fill out
4151 * @size: size of memory requested
4152 * @alignment: what to align the allocation to
4154 enum i40e_status_code
4155 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4156 struct i40e_dma_mem *mem,
4160 const struct rte_memzone *mz = NULL;
4161 char z_name[RTE_MEMZONE_NAMESIZE];
4164 return I40E_ERR_PARAM;
4166 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4167 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4168 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4170 return I40E_ERR_NO_MEMORY;
4175 mem->zone = (const void *)mz;
4177 "memzone %s allocated with physical address: %"PRIu64,
4180 return I40E_SUCCESS;
4184 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4185 * @hw: pointer to the HW structure
4186 * @mem: ptr to mem struct to free
4188 enum i40e_status_code
4189 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4190 struct i40e_dma_mem *mem)
4193 return I40E_ERR_PARAM;
4196 "memzone %s to be freed with physical address: %"PRIu64,
4197 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4198 rte_memzone_free((const struct rte_memzone *)mem->zone);
4203 return I40E_SUCCESS;
4207 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4208 * @hw: pointer to the HW structure
4209 * @mem: pointer to mem struct to fill out
4210 * @size: size of memory requested
4212 enum i40e_status_code
4213 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4214 struct i40e_virt_mem *mem,
4218 return I40E_ERR_PARAM;
4221 mem->va = rte_zmalloc("i40e", size, 0);
4224 return I40E_SUCCESS;
4226 return I40E_ERR_NO_MEMORY;
4230 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4231 * @hw: pointer to the HW structure
4232 * @mem: pointer to mem struct to free
4234 enum i40e_status_code
4235 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4236 struct i40e_virt_mem *mem)
4239 return I40E_ERR_PARAM;
4244 return I40E_SUCCESS;
4248 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4250 rte_spinlock_init(&sp->spinlock);
4254 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4256 rte_spinlock_lock(&sp->spinlock);
4260 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4262 rte_spinlock_unlock(&sp->spinlock);
4266 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4272 * Get the hardware capabilities, which will be parsed
4273 * and saved into struct i40e_hw.
4276 i40e_get_cap(struct i40e_hw *hw)
4278 struct i40e_aqc_list_capabilities_element_resp *buf;
4279 uint16_t len, size = 0;
4282 /* Calculate a huge enough buff for saving response data temporarily */
4283 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4284 I40E_MAX_CAP_ELE_NUM;
4285 buf = rte_zmalloc("i40e", len, 0);
4287 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4288 return I40E_ERR_NO_MEMORY;
4291 /* Get, parse the capabilities and save it to hw */
4292 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4293 i40e_aqc_opc_list_func_capabilities, NULL);
4294 if (ret != I40E_SUCCESS)
4295 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4297 /* Free the temporary buffer after being used */
4303 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4304 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4306 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4314 pf = (struct i40e_pf *)opaque;
4318 num = strtoul(value, &end, 0);
4319 if (errno != 0 || end == value || *end != 0) {
4320 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4321 "kept the value = %hu", value, pf->vf_nb_qp_max);
4325 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4326 pf->vf_nb_qp_max = (uint16_t)num;
4328 /* here return 0 to make next valid same argument work */
4329 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4330 "power of 2 and equal or less than 16 !, Now it is "
4331 "kept the value = %hu", num, pf->vf_nb_qp_max);
4336 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4338 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4339 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4340 struct rte_kvargs *kvlist;
4342 /* set default queue number per VF as 4 */
4343 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4345 if (dev->device->devargs == NULL)
4348 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4352 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4353 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4354 "the first invalid or last valid one is used !",
4355 QUEUE_NUM_PER_VF_ARG);
4357 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4358 i40e_pf_parse_vf_queue_number_handler, pf);
4360 rte_kvargs_free(kvlist);
4366 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4368 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4369 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4370 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4371 uint16_t qp_count = 0, vsi_count = 0;
4373 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4374 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4378 i40e_pf_config_vf_rxq_number(dev);
4380 /* Add the parameter init for LFC */
4381 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4382 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4383 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4385 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4386 pf->max_num_vsi = hw->func_caps.num_vsis;
4387 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4388 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4390 /* FDir queue/VSI allocation */
4391 pf->fdir_qp_offset = 0;
4392 if (hw->func_caps.fd) {
4393 pf->flags |= I40E_FLAG_FDIR;
4394 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4396 pf->fdir_nb_qps = 0;
4398 qp_count += pf->fdir_nb_qps;
4401 /* LAN queue/VSI allocation */
4402 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4403 if (!hw->func_caps.rss) {
4406 pf->flags |= I40E_FLAG_RSS;
4407 if (hw->mac.type == I40E_MAC_X722)
4408 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4409 pf->lan_nb_qps = pf->lan_nb_qp_max;
4411 qp_count += pf->lan_nb_qps;
4414 /* VF queue/VSI allocation */
4415 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4416 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4417 pf->flags |= I40E_FLAG_SRIOV;
4418 pf->vf_nb_qps = pf->vf_nb_qp_max;
4419 pf->vf_num = pci_dev->max_vfs;
4421 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4422 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4427 qp_count += pf->vf_nb_qps * pf->vf_num;
4428 vsi_count += pf->vf_num;
4430 /* VMDq queue/VSI allocation */
4431 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4432 pf->vmdq_nb_qps = 0;
4433 pf->max_nb_vmdq_vsi = 0;
4434 if (hw->func_caps.vmdq) {
4435 if (qp_count < hw->func_caps.num_tx_qp &&
4436 vsi_count < hw->func_caps.num_vsis) {
4437 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4438 qp_count) / pf->vmdq_nb_qp_max;
4440 /* Limit the maximum number of VMDq vsi to the maximum
4441 * ethdev can support
4443 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4444 hw->func_caps.num_vsis - vsi_count);
4445 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4447 if (pf->max_nb_vmdq_vsi) {
4448 pf->flags |= I40E_FLAG_VMDQ;
4449 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4451 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4452 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4453 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4456 "No enough queues left for VMDq");
4459 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4462 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4463 vsi_count += pf->max_nb_vmdq_vsi;
4465 if (hw->func_caps.dcb)
4466 pf->flags |= I40E_FLAG_DCB;
4468 if (qp_count > hw->func_caps.num_tx_qp) {
4470 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4471 qp_count, hw->func_caps.num_tx_qp);
4474 if (vsi_count > hw->func_caps.num_vsis) {
4476 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4477 vsi_count, hw->func_caps.num_vsis);
4485 i40e_pf_get_switch_config(struct i40e_pf *pf)
4487 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4488 struct i40e_aqc_get_switch_config_resp *switch_config;
4489 struct i40e_aqc_switch_config_element_resp *element;
4490 uint16_t start_seid = 0, num_reported;
4493 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4494 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4495 if (!switch_config) {
4496 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4500 /* Get the switch configurations */
4501 ret = i40e_aq_get_switch_config(hw, switch_config,
4502 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4503 if (ret != I40E_SUCCESS) {
4504 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4507 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4508 if (num_reported != 1) { /* The number should be 1 */
4509 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4513 /* Parse the switch configuration elements */
4514 element = &(switch_config->element[0]);
4515 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4516 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4517 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4519 PMD_DRV_LOG(INFO, "Unknown element type");
4522 rte_free(switch_config);
4528 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4531 struct pool_entry *entry;
4533 if (pool == NULL || num == 0)
4536 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4537 if (entry == NULL) {
4538 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4542 /* queue heap initialize */
4543 pool->num_free = num;
4544 pool->num_alloc = 0;
4546 LIST_INIT(&pool->alloc_list);
4547 LIST_INIT(&pool->free_list);
4549 /* Initialize element */
4553 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4558 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4560 struct pool_entry *entry, *next_entry;
4565 for (entry = LIST_FIRST(&pool->alloc_list);
4566 entry && (next_entry = LIST_NEXT(entry, next), 1);
4567 entry = next_entry) {
4568 LIST_REMOVE(entry, next);
4572 for (entry = LIST_FIRST(&pool->free_list);
4573 entry && (next_entry = LIST_NEXT(entry, next), 1);
4574 entry = next_entry) {
4575 LIST_REMOVE(entry, next);
4580 pool->num_alloc = 0;
4582 LIST_INIT(&pool->alloc_list);
4583 LIST_INIT(&pool->free_list);
4587 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4590 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4591 uint32_t pool_offset;
4595 PMD_DRV_LOG(ERR, "Invalid parameter");
4599 pool_offset = base - pool->base;
4600 /* Lookup in alloc list */
4601 LIST_FOREACH(entry, &pool->alloc_list, next) {
4602 if (entry->base == pool_offset) {
4603 valid_entry = entry;
4604 LIST_REMOVE(entry, next);
4609 /* Not find, return */
4610 if (valid_entry == NULL) {
4611 PMD_DRV_LOG(ERR, "Failed to find entry");
4616 * Found it, move it to free list and try to merge.
4617 * In order to make merge easier, always sort it by qbase.
4618 * Find adjacent prev and last entries.
4621 LIST_FOREACH(entry, &pool->free_list, next) {
4622 if (entry->base > valid_entry->base) {
4630 /* Try to merge with next one*/
4632 /* Merge with next one */
4633 if (valid_entry->base + valid_entry->len == next->base) {
4634 next->base = valid_entry->base;
4635 next->len += valid_entry->len;
4636 rte_free(valid_entry);
4643 /* Merge with previous one */
4644 if (prev->base + prev->len == valid_entry->base) {
4645 prev->len += valid_entry->len;
4646 /* If it merge with next one, remove next node */
4648 LIST_REMOVE(valid_entry, next);
4649 rte_free(valid_entry);
4651 rte_free(valid_entry);
4657 /* Not find any entry to merge, insert */
4660 LIST_INSERT_AFTER(prev, valid_entry, next);
4661 else if (next != NULL)
4662 LIST_INSERT_BEFORE(next, valid_entry, next);
4663 else /* It's empty list, insert to head */
4664 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4667 pool->num_free += valid_entry->len;
4668 pool->num_alloc -= valid_entry->len;
4674 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4677 struct pool_entry *entry, *valid_entry;
4679 if (pool == NULL || num == 0) {
4680 PMD_DRV_LOG(ERR, "Invalid parameter");
4684 if (pool->num_free < num) {
4685 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4686 num, pool->num_free);
4691 /* Lookup in free list and find most fit one */
4692 LIST_FOREACH(entry, &pool->free_list, next) {
4693 if (entry->len >= num) {
4695 if (entry->len == num) {
4696 valid_entry = entry;
4699 if (valid_entry == NULL || valid_entry->len > entry->len)
4700 valid_entry = entry;
4704 /* Not find one to satisfy the request, return */
4705 if (valid_entry == NULL) {
4706 PMD_DRV_LOG(ERR, "No valid entry found");
4710 * The entry have equal queue number as requested,
4711 * remove it from alloc_list.
4713 if (valid_entry->len == num) {
4714 LIST_REMOVE(valid_entry, next);
4717 * The entry have more numbers than requested,
4718 * create a new entry for alloc_list and minus its
4719 * queue base and number in free_list.
4721 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4722 if (entry == NULL) {
4724 "Failed to allocate memory for resource pool");
4727 entry->base = valid_entry->base;
4729 valid_entry->base += num;
4730 valid_entry->len -= num;
4731 valid_entry = entry;
4734 /* Insert it into alloc list, not sorted */
4735 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4737 pool->num_free -= valid_entry->len;
4738 pool->num_alloc += valid_entry->len;
4740 return valid_entry->base + pool->base;
4744 * bitmap_is_subset - Check whether src2 is subset of src1
4747 bitmap_is_subset(uint8_t src1, uint8_t src2)
4749 return !((src1 ^ src2) & src2);
4752 static enum i40e_status_code
4753 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4755 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4757 /* If DCB is not supported, only default TC is supported */
4758 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4759 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4760 return I40E_NOT_SUPPORTED;
4763 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4765 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4766 hw->func_caps.enabled_tcmap, enabled_tcmap);
4767 return I40E_NOT_SUPPORTED;
4769 return I40E_SUCCESS;
4773 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4774 struct i40e_vsi_vlan_pvid_info *info)
4777 struct i40e_vsi_context ctxt;
4778 uint8_t vlan_flags = 0;
4781 if (vsi == NULL || info == NULL) {
4782 PMD_DRV_LOG(ERR, "invalid parameters");
4783 return I40E_ERR_PARAM;
4787 vsi->info.pvid = info->config.pvid;
4789 * If insert pvid is enabled, only tagged pkts are
4790 * allowed to be sent out.
4792 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4793 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4796 if (info->config.reject.tagged == 0)
4797 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4799 if (info->config.reject.untagged == 0)
4800 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4802 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4803 I40E_AQ_VSI_PVLAN_MODE_MASK);
4804 vsi->info.port_vlan_flags |= vlan_flags;
4805 vsi->info.valid_sections =
4806 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4807 memset(&ctxt, 0, sizeof(ctxt));
4808 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4809 ctxt.seid = vsi->seid;
4811 hw = I40E_VSI_TO_HW(vsi);
4812 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4813 if (ret != I40E_SUCCESS)
4814 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4820 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4822 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4824 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4826 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4827 if (ret != I40E_SUCCESS)
4831 PMD_DRV_LOG(ERR, "seid not valid");
4835 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4836 tc_bw_data.tc_valid_bits = enabled_tcmap;
4837 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4838 tc_bw_data.tc_bw_credits[i] =
4839 (enabled_tcmap & (1 << i)) ? 1 : 0;
4841 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4842 if (ret != I40E_SUCCESS) {
4843 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4847 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4848 sizeof(vsi->info.qs_handle));
4849 return I40E_SUCCESS;
4852 static enum i40e_status_code
4853 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4854 struct i40e_aqc_vsi_properties_data *info,
4855 uint8_t enabled_tcmap)
4857 enum i40e_status_code ret;
4858 int i, total_tc = 0;
4859 uint16_t qpnum_per_tc, bsf, qp_idx;
4861 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4862 if (ret != I40E_SUCCESS)
4865 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4866 if (enabled_tcmap & (1 << i))
4870 vsi->enabled_tc = enabled_tcmap;
4872 /* Number of queues per enabled TC */
4873 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4874 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4875 bsf = rte_bsf32(qpnum_per_tc);
4877 /* Adjust the queue number to actual queues that can be applied */
4878 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4879 vsi->nb_qps = qpnum_per_tc * total_tc;
4882 * Configure TC and queue mapping parameters, for enabled TC,
4883 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4884 * default queue will serve it.
4887 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4888 if (vsi->enabled_tc & (1 << i)) {
4889 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4890 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4891 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4892 qp_idx += qpnum_per_tc;
4894 info->tc_mapping[i] = 0;
4897 /* Associate queue number with VSI */
4898 if (vsi->type == I40E_VSI_SRIOV) {
4899 info->mapping_flags |=
4900 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4901 for (i = 0; i < vsi->nb_qps; i++)
4902 info->queue_mapping[i] =
4903 rte_cpu_to_le_16(vsi->base_queue + i);
4905 info->mapping_flags |=
4906 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4907 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4909 info->valid_sections |=
4910 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4912 return I40E_SUCCESS;
4916 i40e_veb_release(struct i40e_veb *veb)
4918 struct i40e_vsi *vsi;
4924 if (!TAILQ_EMPTY(&veb->head)) {
4925 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4928 /* associate_vsi field is NULL for floating VEB */
4929 if (veb->associate_vsi != NULL) {
4930 vsi = veb->associate_vsi;
4931 hw = I40E_VSI_TO_HW(vsi);
4933 vsi->uplink_seid = veb->uplink_seid;
4936 veb->associate_pf->main_vsi->floating_veb = NULL;
4937 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4940 i40e_aq_delete_element(hw, veb->seid, NULL);
4942 return I40E_SUCCESS;
4946 static struct i40e_veb *
4947 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4949 struct i40e_veb *veb;
4955 "veb setup failed, associated PF shouldn't null");
4958 hw = I40E_PF_TO_HW(pf);
4960 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4962 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4966 veb->associate_vsi = vsi;
4967 veb->associate_pf = pf;
4968 TAILQ_INIT(&veb->head);
4969 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4971 /* create floating veb if vsi is NULL */
4973 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4974 I40E_DEFAULT_TCMAP, false,
4975 &veb->seid, false, NULL);
4977 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4978 true, &veb->seid, false, NULL);
4981 if (ret != I40E_SUCCESS) {
4982 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4983 hw->aq.asq_last_status);
4986 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4988 /* get statistics index */
4989 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4990 &veb->stats_idx, NULL, NULL, NULL);
4991 if (ret != I40E_SUCCESS) {
4992 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4993 hw->aq.asq_last_status);
4996 /* Get VEB bandwidth, to be implemented */
4997 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4999 vsi->uplink_seid = veb->seid;
5008 i40e_vsi_release(struct i40e_vsi *vsi)
5012 struct i40e_vsi_list *vsi_list;
5015 struct i40e_mac_filter *f;
5016 uint16_t user_param;
5019 return I40E_SUCCESS;
5024 user_param = vsi->user_param;
5026 pf = I40E_VSI_TO_PF(vsi);
5027 hw = I40E_VSI_TO_HW(vsi);
5029 /* VSI has child to attach, release child first */
5031 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5032 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5035 i40e_veb_release(vsi->veb);
5038 if (vsi->floating_veb) {
5039 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5040 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5045 /* Remove all macvlan filters of the VSI */
5046 i40e_vsi_remove_all_macvlan_filter(vsi);
5047 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5050 if (vsi->type != I40E_VSI_MAIN &&
5051 ((vsi->type != I40E_VSI_SRIOV) ||
5052 !pf->floating_veb_list[user_param])) {
5053 /* Remove vsi from parent's sibling list */
5054 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5055 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5056 return I40E_ERR_PARAM;
5058 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5059 &vsi->sib_vsi_list, list);
5061 /* Remove all switch element of the VSI */
5062 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5063 if (ret != I40E_SUCCESS)
5064 PMD_DRV_LOG(ERR, "Failed to delete element");
5067 if ((vsi->type == I40E_VSI_SRIOV) &&
5068 pf->floating_veb_list[user_param]) {
5069 /* Remove vsi from parent's sibling list */
5070 if (vsi->parent_vsi == NULL ||
5071 vsi->parent_vsi->floating_veb == NULL) {
5072 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5073 return I40E_ERR_PARAM;
5075 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5076 &vsi->sib_vsi_list, list);
5078 /* Remove all switch element of the VSI */
5079 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5080 if (ret != I40E_SUCCESS)
5081 PMD_DRV_LOG(ERR, "Failed to delete element");
5084 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5086 if (vsi->type != I40E_VSI_SRIOV)
5087 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5090 return I40E_SUCCESS;
5094 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5096 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5097 struct i40e_aqc_remove_macvlan_element_data def_filter;
5098 struct i40e_mac_filter_info filter;
5101 if (vsi->type != I40E_VSI_MAIN)
5102 return I40E_ERR_CONFIG;
5103 memset(&def_filter, 0, sizeof(def_filter));
5104 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5106 def_filter.vlan_tag = 0;
5107 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5108 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5109 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5110 if (ret != I40E_SUCCESS) {
5111 struct i40e_mac_filter *f;
5112 struct ether_addr *mac;
5115 "Cannot remove the default macvlan filter");
5116 /* It needs to add the permanent mac into mac list */
5117 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5119 PMD_DRV_LOG(ERR, "failed to allocate memory");
5120 return I40E_ERR_NO_MEMORY;
5122 mac = &f->mac_info.mac_addr;
5123 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5125 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5126 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5131 rte_memcpy(&filter.mac_addr,
5132 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5133 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5134 return i40e_vsi_add_mac(vsi, &filter);
5138 * i40e_vsi_get_bw_config - Query VSI BW Information
5139 * @vsi: the VSI to be queried
5141 * Returns 0 on success, negative value on failure
5143 static enum i40e_status_code
5144 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5146 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5147 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5148 struct i40e_hw *hw = &vsi->adapter->hw;
5153 memset(&bw_config, 0, sizeof(bw_config));
5154 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5155 if (ret != I40E_SUCCESS) {
5156 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5157 hw->aq.asq_last_status);
5161 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5162 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5163 &ets_sla_config, NULL);
5164 if (ret != I40E_SUCCESS) {
5166 "VSI failed to get TC bandwdith configuration %u",
5167 hw->aq.asq_last_status);
5171 /* store and print out BW info */
5172 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5173 vsi->bw_info.bw_max = bw_config.max_bw;
5174 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5175 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5176 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5177 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5179 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5180 vsi->bw_info.bw_ets_share_credits[i] =
5181 ets_sla_config.share_credits[i];
5182 vsi->bw_info.bw_ets_credits[i] =
5183 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5184 /* 4 bits per TC, 4th bit is reserved */
5185 vsi->bw_info.bw_ets_max[i] =
5186 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5187 RTE_LEN2MASK(3, uint8_t));
5188 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5189 vsi->bw_info.bw_ets_share_credits[i]);
5190 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5191 vsi->bw_info.bw_ets_credits[i]);
5192 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5193 vsi->bw_info.bw_ets_max[i]);
5196 return I40E_SUCCESS;
5199 /* i40e_enable_pf_lb
5200 * @pf: pointer to the pf structure
5202 * allow loopback on pf
5205 i40e_enable_pf_lb(struct i40e_pf *pf)
5207 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5208 struct i40e_vsi_context ctxt;
5211 /* Use the FW API if FW >= v5.0 */
5212 if (hw->aq.fw_maj_ver < 5) {
5213 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5217 memset(&ctxt, 0, sizeof(ctxt));
5218 ctxt.seid = pf->main_vsi_seid;
5219 ctxt.pf_num = hw->pf_id;
5220 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5222 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5223 ret, hw->aq.asq_last_status);
5226 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5227 ctxt.info.valid_sections =
5228 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5229 ctxt.info.switch_id |=
5230 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5232 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5234 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5235 hw->aq.asq_last_status);
5240 i40e_vsi_setup(struct i40e_pf *pf,
5241 enum i40e_vsi_type type,
5242 struct i40e_vsi *uplink_vsi,
5243 uint16_t user_param)
5245 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5246 struct i40e_vsi *vsi;
5247 struct i40e_mac_filter_info filter;
5249 struct i40e_vsi_context ctxt;
5250 struct ether_addr broadcast =
5251 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5253 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5254 uplink_vsi == NULL) {
5256 "VSI setup failed, VSI link shouldn't be NULL");
5260 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5262 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5267 * 1.type is not MAIN and uplink vsi is not NULL
5268 * If uplink vsi didn't setup VEB, create one first under veb field
5269 * 2.type is SRIOV and the uplink is NULL
5270 * If floating VEB is NULL, create one veb under floating veb field
5273 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5274 uplink_vsi->veb == NULL) {
5275 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5277 if (uplink_vsi->veb == NULL) {
5278 PMD_DRV_LOG(ERR, "VEB setup failed");
5281 /* set ALLOWLOOPBACk on pf, when veb is created */
5282 i40e_enable_pf_lb(pf);
5285 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5286 pf->main_vsi->floating_veb == NULL) {
5287 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5289 if (pf->main_vsi->floating_veb == NULL) {
5290 PMD_DRV_LOG(ERR, "VEB setup failed");
5295 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5297 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5300 TAILQ_INIT(&vsi->mac_list);
5302 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5303 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5304 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5305 vsi->user_param = user_param;
5306 vsi->vlan_anti_spoof_on = 0;
5307 vsi->vlan_filter_on = 0;
5308 /* Allocate queues */
5309 switch (vsi->type) {
5310 case I40E_VSI_MAIN :
5311 vsi->nb_qps = pf->lan_nb_qps;
5313 case I40E_VSI_SRIOV :
5314 vsi->nb_qps = pf->vf_nb_qps;
5316 case I40E_VSI_VMDQ2:
5317 vsi->nb_qps = pf->vmdq_nb_qps;
5320 vsi->nb_qps = pf->fdir_nb_qps;
5326 * The filter status descriptor is reported in rx queue 0,
5327 * while the tx queue for fdir filter programming has no
5328 * such constraints, can be non-zero queues.
5329 * To simplify it, choose FDIR vsi use queue 0 pair.
5330 * To make sure it will use queue 0 pair, queue allocation
5331 * need be done before this function is called
5333 if (type != I40E_VSI_FDIR) {
5334 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5336 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5340 vsi->base_queue = ret;
5342 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5344 /* VF has MSIX interrupt in VF range, don't allocate here */
5345 if (type == I40E_VSI_MAIN) {
5346 if (pf->support_multi_driver) {
5347 /* If support multi-driver, need to use INT0 instead of
5348 * allocating from msix pool. The Msix pool is init from
5349 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5350 * to 1 without calling i40e_res_pool_alloc.
5355 ret = i40e_res_pool_alloc(&pf->msix_pool,
5356 RTE_MIN(vsi->nb_qps,
5357 RTE_MAX_RXTX_INTR_VEC_ID));
5360 "VSI MAIN %d get heap failed %d",
5362 goto fail_queue_alloc;
5364 vsi->msix_intr = ret;
5365 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5366 RTE_MAX_RXTX_INTR_VEC_ID);
5368 } else if (type != I40E_VSI_SRIOV) {
5369 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5371 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5372 goto fail_queue_alloc;
5374 vsi->msix_intr = ret;
5382 if (type == I40E_VSI_MAIN) {
5383 /* For main VSI, no need to add since it's default one */
5384 vsi->uplink_seid = pf->mac_seid;
5385 vsi->seid = pf->main_vsi_seid;
5386 /* Bind queues with specific MSIX interrupt */
5388 * Needs 2 interrupt at least, one for misc cause which will
5389 * enabled from OS side, Another for queues binding the
5390 * interrupt from device side only.
5393 /* Get default VSI parameters from hardware */
5394 memset(&ctxt, 0, sizeof(ctxt));
5395 ctxt.seid = vsi->seid;
5396 ctxt.pf_num = hw->pf_id;
5397 ctxt.uplink_seid = vsi->uplink_seid;
5399 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5400 if (ret != I40E_SUCCESS) {
5401 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5402 goto fail_msix_alloc;
5404 rte_memcpy(&vsi->info, &ctxt.info,
5405 sizeof(struct i40e_aqc_vsi_properties_data));
5406 vsi->vsi_id = ctxt.vsi_number;
5407 vsi->info.valid_sections = 0;
5409 /* Configure tc, enabled TC0 only */
5410 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5412 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5413 goto fail_msix_alloc;
5416 /* TC, queue mapping */
5417 memset(&ctxt, 0, sizeof(ctxt));
5418 vsi->info.valid_sections |=
5419 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5420 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5421 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5422 rte_memcpy(&ctxt.info, &vsi->info,
5423 sizeof(struct i40e_aqc_vsi_properties_data));
5424 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5425 I40E_DEFAULT_TCMAP);
5426 if (ret != I40E_SUCCESS) {
5428 "Failed to configure TC queue mapping");
5429 goto fail_msix_alloc;
5431 ctxt.seid = vsi->seid;
5432 ctxt.pf_num = hw->pf_id;
5433 ctxt.uplink_seid = vsi->uplink_seid;
5436 /* Update VSI parameters */
5437 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5438 if (ret != I40E_SUCCESS) {
5439 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5440 goto fail_msix_alloc;
5443 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5444 sizeof(vsi->info.tc_mapping));
5445 rte_memcpy(&vsi->info.queue_mapping,
5446 &ctxt.info.queue_mapping,
5447 sizeof(vsi->info.queue_mapping));
5448 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5449 vsi->info.valid_sections = 0;
5451 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5455 * Updating default filter settings are necessary to prevent
5456 * reception of tagged packets.
5457 * Some old firmware configurations load a default macvlan
5458 * filter which accepts both tagged and untagged packets.
5459 * The updating is to use a normal filter instead if needed.
5460 * For NVM 4.2.2 or after, the updating is not needed anymore.
5461 * The firmware with correct configurations load the default
5462 * macvlan filter which is expected and cannot be removed.
5464 i40e_update_default_filter_setting(vsi);
5465 i40e_config_qinq(hw, vsi);
5466 } else if (type == I40E_VSI_SRIOV) {
5467 memset(&ctxt, 0, sizeof(ctxt));
5469 * For other VSI, the uplink_seid equals to uplink VSI's
5470 * uplink_seid since they share same VEB
5472 if (uplink_vsi == NULL)
5473 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5475 vsi->uplink_seid = uplink_vsi->uplink_seid;
5476 ctxt.pf_num = hw->pf_id;
5477 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5478 ctxt.uplink_seid = vsi->uplink_seid;
5479 ctxt.connection_type = 0x1;
5480 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5482 /* Use the VEB configuration if FW >= v5.0 */
5483 if (hw->aq.fw_maj_ver >= 5) {
5484 /* Configure switch ID */
5485 ctxt.info.valid_sections |=
5486 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5487 ctxt.info.switch_id =
5488 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5491 /* Configure port/vlan */
5492 ctxt.info.valid_sections |=
5493 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5494 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5495 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5496 hw->func_caps.enabled_tcmap);
5497 if (ret != I40E_SUCCESS) {
5499 "Failed to configure TC queue mapping");
5500 goto fail_msix_alloc;
5503 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5504 ctxt.info.valid_sections |=
5505 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5507 * Since VSI is not created yet, only configure parameter,
5508 * will add vsi below.
5511 i40e_config_qinq(hw, vsi);
5512 } else if (type == I40E_VSI_VMDQ2) {
5513 memset(&ctxt, 0, sizeof(ctxt));
5515 * For other VSI, the uplink_seid equals to uplink VSI's
5516 * uplink_seid since they share same VEB
5518 vsi->uplink_seid = uplink_vsi->uplink_seid;
5519 ctxt.pf_num = hw->pf_id;
5521 ctxt.uplink_seid = vsi->uplink_seid;
5522 ctxt.connection_type = 0x1;
5523 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5525 ctxt.info.valid_sections |=
5526 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5527 /* user_param carries flag to enable loop back */
5529 ctxt.info.switch_id =
5530 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5531 ctxt.info.switch_id |=
5532 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5535 /* Configure port/vlan */
5536 ctxt.info.valid_sections |=
5537 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5538 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5539 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5540 I40E_DEFAULT_TCMAP);
5541 if (ret != I40E_SUCCESS) {
5543 "Failed to configure TC queue mapping");
5544 goto fail_msix_alloc;
5546 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5547 ctxt.info.valid_sections |=
5548 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5549 } else if (type == I40E_VSI_FDIR) {
5550 memset(&ctxt, 0, sizeof(ctxt));
5551 vsi->uplink_seid = uplink_vsi->uplink_seid;
5552 ctxt.pf_num = hw->pf_id;
5554 ctxt.uplink_seid = vsi->uplink_seid;
5555 ctxt.connection_type = 0x1; /* regular data port */
5556 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5557 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5558 I40E_DEFAULT_TCMAP);
5559 if (ret != I40E_SUCCESS) {
5561 "Failed to configure TC queue mapping.");
5562 goto fail_msix_alloc;
5564 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5565 ctxt.info.valid_sections |=
5566 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5568 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5569 goto fail_msix_alloc;
5572 if (vsi->type != I40E_VSI_MAIN) {
5573 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5574 if (ret != I40E_SUCCESS) {
5575 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5576 hw->aq.asq_last_status);
5577 goto fail_msix_alloc;
5579 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5580 vsi->info.valid_sections = 0;
5581 vsi->seid = ctxt.seid;
5582 vsi->vsi_id = ctxt.vsi_number;
5583 vsi->sib_vsi_list.vsi = vsi;
5584 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5585 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5586 &vsi->sib_vsi_list, list);
5588 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5589 &vsi->sib_vsi_list, list);
5593 /* MAC/VLAN configuration */
5594 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5595 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5597 ret = i40e_vsi_add_mac(vsi, &filter);
5598 if (ret != I40E_SUCCESS) {
5599 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5600 goto fail_msix_alloc;
5603 /* Get VSI BW information */
5604 i40e_vsi_get_bw_config(vsi);
5607 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5609 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5615 /* Configure vlan filter on or off */
5617 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5620 struct i40e_mac_filter *f;
5622 struct i40e_mac_filter_info *mac_filter;
5623 enum rte_mac_filter_type desired_filter;
5624 int ret = I40E_SUCCESS;
5627 /* Filter to match MAC and VLAN */
5628 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5630 /* Filter to match only MAC */
5631 desired_filter = RTE_MAC_PERFECT_MATCH;
5636 mac_filter = rte_zmalloc("mac_filter_info_data",
5637 num * sizeof(*mac_filter), 0);
5638 if (mac_filter == NULL) {
5639 PMD_DRV_LOG(ERR, "failed to allocate memory");
5640 return I40E_ERR_NO_MEMORY;
5645 /* Remove all existing mac */
5646 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5647 mac_filter[i] = f->mac_info;
5648 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5650 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5651 on ? "enable" : "disable");
5657 /* Override with new filter */
5658 for (i = 0; i < num; i++) {
5659 mac_filter[i].filter_type = desired_filter;
5660 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5662 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5663 on ? "enable" : "disable");
5669 rte_free(mac_filter);
5673 /* Configure vlan stripping on or off */
5675 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5677 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5678 struct i40e_vsi_context ctxt;
5680 int ret = I40E_SUCCESS;
5682 /* Check if it has been already on or off */
5683 if (vsi->info.valid_sections &
5684 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5686 if ((vsi->info.port_vlan_flags &
5687 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5688 return 0; /* already on */
5690 if ((vsi->info.port_vlan_flags &
5691 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5692 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5693 return 0; /* already off */
5698 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5700 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5701 vsi->info.valid_sections =
5702 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5703 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5704 vsi->info.port_vlan_flags |= vlan_flags;
5705 ctxt.seid = vsi->seid;
5706 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5707 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5709 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5710 on ? "enable" : "disable");
5716 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5718 struct rte_eth_dev_data *data = dev->data;
5722 /* Apply vlan offload setting */
5723 mask = ETH_VLAN_STRIP_MASK |
5724 ETH_VLAN_FILTER_MASK |
5725 ETH_VLAN_EXTEND_MASK;
5726 ret = i40e_vlan_offload_set(dev, mask);
5728 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5732 /* Apply pvid setting */
5733 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5734 data->dev_conf.txmode.hw_vlan_insert_pvid);
5736 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5742 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5744 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5746 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5750 i40e_update_flow_control(struct i40e_hw *hw)
5752 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5753 struct i40e_link_status link_status;
5754 uint32_t rxfc = 0, txfc = 0, reg;
5758 memset(&link_status, 0, sizeof(link_status));
5759 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5760 if (ret != I40E_SUCCESS) {
5761 PMD_DRV_LOG(ERR, "Failed to get link status information");
5762 goto write_reg; /* Disable flow control */
5765 an_info = hw->phy.link_info.an_info;
5766 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5767 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5768 ret = I40E_ERR_NOT_READY;
5769 goto write_reg; /* Disable flow control */
5772 * If link auto negotiation is enabled, flow control needs to
5773 * be configured according to it
5775 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5776 case I40E_LINK_PAUSE_RXTX:
5779 hw->fc.current_mode = I40E_FC_FULL;
5781 case I40E_AQ_LINK_PAUSE_RX:
5783 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5785 case I40E_AQ_LINK_PAUSE_TX:
5787 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5790 hw->fc.current_mode = I40E_FC_NONE;
5795 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5796 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5797 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5798 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5799 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5800 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5807 i40e_pf_setup(struct i40e_pf *pf)
5809 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5810 struct i40e_filter_control_settings settings;
5811 struct i40e_vsi *vsi;
5814 /* Clear all stats counters */
5815 pf->offset_loaded = FALSE;
5816 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5817 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5818 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5819 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5821 ret = i40e_pf_get_switch_config(pf);
5822 if (ret != I40E_SUCCESS) {
5823 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5827 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5829 PMD_INIT_LOG(WARNING,
5830 "failed to allocate switch domain for device %d", ret);
5832 if (pf->flags & I40E_FLAG_FDIR) {
5833 /* make queue allocated first, let FDIR use queue pair 0*/
5834 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5835 if (ret != I40E_FDIR_QUEUE_ID) {
5837 "queue allocation fails for FDIR: ret =%d",
5839 pf->flags &= ~I40E_FLAG_FDIR;
5842 /* main VSI setup */
5843 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5845 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5846 return I40E_ERR_NOT_READY;
5850 /* Configure filter control */
5851 memset(&settings, 0, sizeof(settings));
5852 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5853 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5854 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5855 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5857 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5858 hw->func_caps.rss_table_size);
5859 return I40E_ERR_PARAM;
5861 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5862 hw->func_caps.rss_table_size);
5863 pf->hash_lut_size = hw->func_caps.rss_table_size;
5865 /* Enable ethtype and macvlan filters */
5866 settings.enable_ethtype = TRUE;
5867 settings.enable_macvlan = TRUE;
5868 ret = i40e_set_filter_control(hw, &settings);
5870 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5873 /* Update flow control according to the auto negotiation */
5874 i40e_update_flow_control(hw);
5876 return I40E_SUCCESS;
5880 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5886 * Set or clear TX Queue Disable flags,
5887 * which is required by hardware.
5889 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5890 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5892 /* Wait until the request is finished */
5893 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5894 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5895 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5896 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5897 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5903 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5904 return I40E_SUCCESS; /* already on, skip next steps */
5906 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5907 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5909 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5910 return I40E_SUCCESS; /* already off, skip next steps */
5911 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5913 /* Write the register */
5914 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5915 /* Check the result */
5916 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5917 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5918 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5920 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5921 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5924 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5925 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5929 /* Check if it is timeout */
5930 if (j >= I40E_CHK_Q_ENA_COUNT) {
5931 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5932 (on ? "enable" : "disable"), q_idx);
5933 return I40E_ERR_TIMEOUT;
5936 return I40E_SUCCESS;
5939 /* Swith on or off the tx queues */
5941 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5943 struct rte_eth_dev_data *dev_data = pf->dev_data;
5944 struct i40e_tx_queue *txq;
5945 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5949 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5950 txq = dev_data->tx_queues[i];
5951 /* Don't operate the queue if not configured or
5952 * if starting only per queue */
5953 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5956 ret = i40e_dev_tx_queue_start(dev, i);
5958 ret = i40e_dev_tx_queue_stop(dev, i);
5959 if ( ret != I40E_SUCCESS)
5963 return I40E_SUCCESS;
5967 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5972 /* Wait until the request is finished */
5973 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5974 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5975 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5976 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5977 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5982 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5983 return I40E_SUCCESS; /* Already on, skip next steps */
5984 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5986 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5987 return I40E_SUCCESS; /* Already off, skip next steps */
5988 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5991 /* Write the register */
5992 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5993 /* Check the result */
5994 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5995 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5996 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5998 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5999 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6002 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6003 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6008 /* Check if it is timeout */
6009 if (j >= I40E_CHK_Q_ENA_COUNT) {
6010 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6011 (on ? "enable" : "disable"), q_idx);
6012 return I40E_ERR_TIMEOUT;
6015 return I40E_SUCCESS;
6017 /* Switch on or off the rx queues */
6019 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6021 struct rte_eth_dev_data *dev_data = pf->dev_data;
6022 struct i40e_rx_queue *rxq;
6023 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6027 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6028 rxq = dev_data->rx_queues[i];
6029 /* Don't operate the queue if not configured or
6030 * if starting only per queue */
6031 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6034 ret = i40e_dev_rx_queue_start(dev, i);
6036 ret = i40e_dev_rx_queue_stop(dev, i);
6037 if (ret != I40E_SUCCESS)
6041 return I40E_SUCCESS;
6044 /* Switch on or off all the rx/tx queues */
6046 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6051 /* enable rx queues before enabling tx queues */
6052 ret = i40e_dev_switch_rx_queues(pf, on);
6054 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6057 ret = i40e_dev_switch_tx_queues(pf, on);
6059 /* Stop tx queues before stopping rx queues */
6060 ret = i40e_dev_switch_tx_queues(pf, on);
6062 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6065 ret = i40e_dev_switch_rx_queues(pf, on);
6071 /* Initialize VSI for TX */
6073 i40e_dev_tx_init(struct i40e_pf *pf)
6075 struct rte_eth_dev_data *data = pf->dev_data;
6077 uint32_t ret = I40E_SUCCESS;
6078 struct i40e_tx_queue *txq;
6080 for (i = 0; i < data->nb_tx_queues; i++) {
6081 txq = data->tx_queues[i];
6082 if (!txq || !txq->q_set)
6084 ret = i40e_tx_queue_init(txq);
6085 if (ret != I40E_SUCCESS)
6088 if (ret == I40E_SUCCESS)
6089 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6095 /* Initialize VSI for RX */
6097 i40e_dev_rx_init(struct i40e_pf *pf)
6099 struct rte_eth_dev_data *data = pf->dev_data;
6100 int ret = I40E_SUCCESS;
6102 struct i40e_rx_queue *rxq;
6104 i40e_pf_config_mq_rx(pf);
6105 for (i = 0; i < data->nb_rx_queues; i++) {
6106 rxq = data->rx_queues[i];
6107 if (!rxq || !rxq->q_set)
6110 ret = i40e_rx_queue_init(rxq);
6111 if (ret != I40E_SUCCESS) {
6113 "Failed to do RX queue initialization");
6117 if (ret == I40E_SUCCESS)
6118 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6125 i40e_dev_rxtx_init(struct i40e_pf *pf)
6129 err = i40e_dev_tx_init(pf);
6131 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6134 err = i40e_dev_rx_init(pf);
6136 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6144 i40e_vmdq_setup(struct rte_eth_dev *dev)
6146 struct rte_eth_conf *conf = &dev->data->dev_conf;
6147 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6148 int i, err, conf_vsis, j, loop;
6149 struct i40e_vsi *vsi;
6150 struct i40e_vmdq_info *vmdq_info;
6151 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6152 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6155 * Disable interrupt to avoid message from VF. Furthermore, it will
6156 * avoid race condition in VSI creation/destroy.
6158 i40e_pf_disable_irq0(hw);
6160 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6161 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6165 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6166 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6167 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6168 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6169 pf->max_nb_vmdq_vsi);
6173 if (pf->vmdq != NULL) {
6174 PMD_INIT_LOG(INFO, "VMDQ already configured");
6178 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6179 sizeof(*vmdq_info) * conf_vsis, 0);
6181 if (pf->vmdq == NULL) {
6182 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6186 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6188 /* Create VMDQ VSI */
6189 for (i = 0; i < conf_vsis; i++) {
6190 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6191 vmdq_conf->enable_loop_back);
6193 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6197 vmdq_info = &pf->vmdq[i];
6199 vmdq_info->vsi = vsi;
6201 pf->nb_cfg_vmdq_vsi = conf_vsis;
6203 /* Configure Vlan */
6204 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6205 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6206 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6207 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6208 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6209 vmdq_conf->pool_map[i].vlan_id, j);
6211 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6212 vmdq_conf->pool_map[i].vlan_id);
6214 PMD_INIT_LOG(ERR, "Failed to add vlan");
6222 i40e_pf_enable_irq0(hw);
6227 for (i = 0; i < conf_vsis; i++)
6228 if (pf->vmdq[i].vsi == NULL)
6231 i40e_vsi_release(pf->vmdq[i].vsi);
6235 i40e_pf_enable_irq0(hw);
6240 i40e_stat_update_32(struct i40e_hw *hw,
6248 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6252 if (new_data >= *offset)
6253 *stat = (uint64_t)(new_data - *offset);
6255 *stat = (uint64_t)((new_data +
6256 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6260 i40e_stat_update_48(struct i40e_hw *hw,
6269 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6270 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6271 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6276 if (new_data >= *offset)
6277 *stat = new_data - *offset;
6279 *stat = (uint64_t)((new_data +
6280 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6282 *stat &= I40E_48_BIT_MASK;
6287 i40e_pf_disable_irq0(struct i40e_hw *hw)
6289 /* Disable all interrupt types */
6290 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6291 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6292 I40E_WRITE_FLUSH(hw);
6297 i40e_pf_enable_irq0(struct i40e_hw *hw)
6299 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6300 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6301 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6302 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6303 I40E_WRITE_FLUSH(hw);
6307 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6309 /* read pending request and disable first */
6310 i40e_pf_disable_irq0(hw);
6311 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6312 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6313 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6316 /* Link no queues with irq0 */
6317 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6318 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6322 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6324 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6328 uint32_t index, offset, val;
6333 * Try to find which VF trigger a reset, use absolute VF id to access
6334 * since the reg is global register.
6336 for (i = 0; i < pf->vf_num; i++) {
6337 abs_vf_id = hw->func_caps.vf_base_id + i;
6338 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6339 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6340 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6341 /* VFR event occurred */
6342 if (val & (0x1 << offset)) {
6345 /* Clear the event first */
6346 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6348 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6350 * Only notify a VF reset event occurred,
6351 * don't trigger another SW reset
6353 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6354 if (ret != I40E_SUCCESS)
6355 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6361 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6363 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6366 for (i = 0; i < pf->vf_num; i++)
6367 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6371 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6373 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6374 struct i40e_arq_event_info info;
6375 uint16_t pending, opcode;
6378 info.buf_len = I40E_AQ_BUF_SZ;
6379 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6380 if (!info.msg_buf) {
6381 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6387 ret = i40e_clean_arq_element(hw, &info, &pending);
6389 if (ret != I40E_SUCCESS) {
6391 "Failed to read msg from AdminQ, aq_err: %u",
6392 hw->aq.asq_last_status);
6395 opcode = rte_le_to_cpu_16(info.desc.opcode);
6398 case i40e_aqc_opc_send_msg_to_pf:
6399 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6400 i40e_pf_host_handle_vf_msg(dev,
6401 rte_le_to_cpu_16(info.desc.retval),
6402 rte_le_to_cpu_32(info.desc.cookie_high),
6403 rte_le_to_cpu_32(info.desc.cookie_low),
6407 case i40e_aqc_opc_get_link_status:
6408 ret = i40e_dev_link_update(dev, 0);
6410 _rte_eth_dev_callback_process(dev,
6411 RTE_ETH_EVENT_INTR_LSC, NULL);
6414 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6419 rte_free(info.msg_buf);
6423 * Interrupt handler triggered by NIC for handling
6424 * specific interrupt.
6427 * Pointer to interrupt handle.
6429 * The address of parameter (struct rte_eth_dev *) regsitered before.
6435 i40e_dev_interrupt_handler(void *param)
6437 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6441 /* Disable interrupt */
6442 i40e_pf_disable_irq0(hw);
6444 /* read out interrupt causes */
6445 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6447 /* No interrupt event indicated */
6448 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6449 PMD_DRV_LOG(INFO, "No interrupt event");
6452 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6453 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6454 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6455 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6456 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6457 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6458 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6459 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6460 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6461 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6462 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6463 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6464 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6465 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6467 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6468 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6469 i40e_dev_handle_vfr_event(dev);
6471 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6472 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6473 i40e_dev_handle_aq_msg(dev);
6477 /* Enable interrupt */
6478 i40e_pf_enable_irq0(hw);
6479 rte_intr_enable(dev->intr_handle);
6483 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6484 struct i40e_macvlan_filter *filter,
6487 int ele_num, ele_buff_size;
6488 int num, actual_num, i;
6490 int ret = I40E_SUCCESS;
6491 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6492 struct i40e_aqc_add_macvlan_element_data *req_list;
6494 if (filter == NULL || total == 0)
6495 return I40E_ERR_PARAM;
6496 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6497 ele_buff_size = hw->aq.asq_buf_size;
6499 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6500 if (req_list == NULL) {
6501 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6502 return I40E_ERR_NO_MEMORY;
6507 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6508 memset(req_list, 0, ele_buff_size);
6510 for (i = 0; i < actual_num; i++) {
6511 rte_memcpy(req_list[i].mac_addr,
6512 &filter[num + i].macaddr, ETH_ADDR_LEN);
6513 req_list[i].vlan_tag =
6514 rte_cpu_to_le_16(filter[num + i].vlan_id);
6516 switch (filter[num + i].filter_type) {
6517 case RTE_MAC_PERFECT_MATCH:
6518 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6519 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6521 case RTE_MACVLAN_PERFECT_MATCH:
6522 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6524 case RTE_MAC_HASH_MATCH:
6525 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6526 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6528 case RTE_MACVLAN_HASH_MATCH:
6529 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6532 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6533 ret = I40E_ERR_PARAM;
6537 req_list[i].queue_number = 0;
6539 req_list[i].flags = rte_cpu_to_le_16(flags);
6542 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6544 if (ret != I40E_SUCCESS) {
6545 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6549 } while (num < total);
6557 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6558 struct i40e_macvlan_filter *filter,
6561 int ele_num, ele_buff_size;
6562 int num, actual_num, i;
6564 int ret = I40E_SUCCESS;
6565 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6566 struct i40e_aqc_remove_macvlan_element_data *req_list;
6568 if (filter == NULL || total == 0)
6569 return I40E_ERR_PARAM;
6571 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6572 ele_buff_size = hw->aq.asq_buf_size;
6574 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6575 if (req_list == NULL) {
6576 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6577 return I40E_ERR_NO_MEMORY;
6582 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6583 memset(req_list, 0, ele_buff_size);
6585 for (i = 0; i < actual_num; i++) {
6586 rte_memcpy(req_list[i].mac_addr,
6587 &filter[num + i].macaddr, ETH_ADDR_LEN);
6588 req_list[i].vlan_tag =
6589 rte_cpu_to_le_16(filter[num + i].vlan_id);
6591 switch (filter[num + i].filter_type) {
6592 case RTE_MAC_PERFECT_MATCH:
6593 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6594 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6596 case RTE_MACVLAN_PERFECT_MATCH:
6597 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6599 case RTE_MAC_HASH_MATCH:
6600 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6601 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6603 case RTE_MACVLAN_HASH_MATCH:
6604 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6607 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6608 ret = I40E_ERR_PARAM;
6611 req_list[i].flags = rte_cpu_to_le_16(flags);
6614 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6616 if (ret != I40E_SUCCESS) {
6617 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6621 } while (num < total);
6628 /* Find out specific MAC filter */
6629 static struct i40e_mac_filter *
6630 i40e_find_mac_filter(struct i40e_vsi *vsi,
6631 struct ether_addr *macaddr)
6633 struct i40e_mac_filter *f;
6635 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6636 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6644 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6647 uint32_t vid_idx, vid_bit;
6649 if (vlan_id > ETH_VLAN_ID_MAX)
6652 vid_idx = I40E_VFTA_IDX(vlan_id);
6653 vid_bit = I40E_VFTA_BIT(vlan_id);
6655 if (vsi->vfta[vid_idx] & vid_bit)
6662 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6663 uint16_t vlan_id, bool on)
6665 uint32_t vid_idx, vid_bit;
6667 vid_idx = I40E_VFTA_IDX(vlan_id);
6668 vid_bit = I40E_VFTA_BIT(vlan_id);
6671 vsi->vfta[vid_idx] |= vid_bit;
6673 vsi->vfta[vid_idx] &= ~vid_bit;
6677 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6678 uint16_t vlan_id, bool on)
6680 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6681 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6684 if (vlan_id > ETH_VLAN_ID_MAX)
6687 i40e_store_vlan_filter(vsi, vlan_id, on);
6689 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6692 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6695 ret = i40e_aq_add_vlan(hw, vsi->seid,
6696 &vlan_data, 1, NULL);
6697 if (ret != I40E_SUCCESS)
6698 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6700 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6701 &vlan_data, 1, NULL);
6702 if (ret != I40E_SUCCESS)
6704 "Failed to remove vlan filter");
6709 * Find all vlan options for specific mac addr,
6710 * return with actual vlan found.
6713 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6714 struct i40e_macvlan_filter *mv_f,
6715 int num, struct ether_addr *addr)
6721 * Not to use i40e_find_vlan_filter to decrease the loop time,
6722 * although the code looks complex.
6724 if (num < vsi->vlan_num)
6725 return I40E_ERR_PARAM;
6728 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6730 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6731 if (vsi->vfta[j] & (1 << k)) {
6734 "vlan number doesn't match");
6735 return I40E_ERR_PARAM;
6737 rte_memcpy(&mv_f[i].macaddr,
6738 addr, ETH_ADDR_LEN);
6740 j * I40E_UINT32_BIT_SIZE + k;
6746 return I40E_SUCCESS;
6750 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6751 struct i40e_macvlan_filter *mv_f,
6756 struct i40e_mac_filter *f;
6758 if (num < vsi->mac_num)
6759 return I40E_ERR_PARAM;
6761 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6763 PMD_DRV_LOG(ERR, "buffer number not match");
6764 return I40E_ERR_PARAM;
6766 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6768 mv_f[i].vlan_id = vlan;
6769 mv_f[i].filter_type = f->mac_info.filter_type;
6773 return I40E_SUCCESS;
6777 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6780 struct i40e_mac_filter *f;
6781 struct i40e_macvlan_filter *mv_f;
6782 int ret = I40E_SUCCESS;
6784 if (vsi == NULL || vsi->mac_num == 0)
6785 return I40E_ERR_PARAM;
6787 /* Case that no vlan is set */
6788 if (vsi->vlan_num == 0)
6791 num = vsi->mac_num * vsi->vlan_num;
6793 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6795 PMD_DRV_LOG(ERR, "failed to allocate memory");
6796 return I40E_ERR_NO_MEMORY;
6800 if (vsi->vlan_num == 0) {
6801 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6802 rte_memcpy(&mv_f[i].macaddr,
6803 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6804 mv_f[i].filter_type = f->mac_info.filter_type;
6805 mv_f[i].vlan_id = 0;
6809 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6810 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6811 vsi->vlan_num, &f->mac_info.mac_addr);
6812 if (ret != I40E_SUCCESS)
6814 for (j = i; j < i + vsi->vlan_num; j++)
6815 mv_f[j].filter_type = f->mac_info.filter_type;
6820 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6828 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6830 struct i40e_macvlan_filter *mv_f;
6832 int ret = I40E_SUCCESS;
6834 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6835 return I40E_ERR_PARAM;
6837 /* If it's already set, just return */
6838 if (i40e_find_vlan_filter(vsi,vlan))
6839 return I40E_SUCCESS;
6841 mac_num = vsi->mac_num;
6844 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6845 return I40E_ERR_PARAM;
6848 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6851 PMD_DRV_LOG(ERR, "failed to allocate memory");
6852 return I40E_ERR_NO_MEMORY;
6855 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6857 if (ret != I40E_SUCCESS)
6860 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6862 if (ret != I40E_SUCCESS)
6865 i40e_set_vlan_filter(vsi, vlan, 1);
6875 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6877 struct i40e_macvlan_filter *mv_f;
6879 int ret = I40E_SUCCESS;
6882 * Vlan 0 is the generic filter for untagged packets
6883 * and can't be removed.
6885 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6886 return I40E_ERR_PARAM;
6888 /* If can't find it, just return */
6889 if (!i40e_find_vlan_filter(vsi, vlan))
6890 return I40E_ERR_PARAM;
6892 mac_num = vsi->mac_num;
6895 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6896 return I40E_ERR_PARAM;
6899 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6902 PMD_DRV_LOG(ERR, "failed to allocate memory");
6903 return I40E_ERR_NO_MEMORY;
6906 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6908 if (ret != I40E_SUCCESS)
6911 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6913 if (ret != I40E_SUCCESS)
6916 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6917 if (vsi->vlan_num == 1) {
6918 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6919 if (ret != I40E_SUCCESS)
6922 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6923 if (ret != I40E_SUCCESS)
6927 i40e_set_vlan_filter(vsi, vlan, 0);
6937 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6939 struct i40e_mac_filter *f;
6940 struct i40e_macvlan_filter *mv_f;
6941 int i, vlan_num = 0;
6942 int ret = I40E_SUCCESS;
6944 /* If it's add and we've config it, return */
6945 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6947 return I40E_SUCCESS;
6948 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6949 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6952 * If vlan_num is 0, that's the first time to add mac,
6953 * set mask for vlan_id 0.
6955 if (vsi->vlan_num == 0) {
6956 i40e_set_vlan_filter(vsi, 0, 1);
6959 vlan_num = vsi->vlan_num;
6960 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6961 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6964 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6966 PMD_DRV_LOG(ERR, "failed to allocate memory");
6967 return I40E_ERR_NO_MEMORY;
6970 for (i = 0; i < vlan_num; i++) {
6971 mv_f[i].filter_type = mac_filter->filter_type;
6972 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6976 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6977 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6978 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6979 &mac_filter->mac_addr);
6980 if (ret != I40E_SUCCESS)
6984 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6985 if (ret != I40E_SUCCESS)
6988 /* Add the mac addr into mac list */
6989 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6991 PMD_DRV_LOG(ERR, "failed to allocate memory");
6992 ret = I40E_ERR_NO_MEMORY;
6995 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6997 f->mac_info.filter_type = mac_filter->filter_type;
6998 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7009 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7011 struct i40e_mac_filter *f;
7012 struct i40e_macvlan_filter *mv_f;
7014 enum rte_mac_filter_type filter_type;
7015 int ret = I40E_SUCCESS;
7017 /* Can't find it, return an error */
7018 f = i40e_find_mac_filter(vsi, addr);
7020 return I40E_ERR_PARAM;
7022 vlan_num = vsi->vlan_num;
7023 filter_type = f->mac_info.filter_type;
7024 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7025 filter_type == RTE_MACVLAN_HASH_MATCH) {
7026 if (vlan_num == 0) {
7027 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7028 return I40E_ERR_PARAM;
7030 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7031 filter_type == RTE_MAC_HASH_MATCH)
7034 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7036 PMD_DRV_LOG(ERR, "failed to allocate memory");
7037 return I40E_ERR_NO_MEMORY;
7040 for (i = 0; i < vlan_num; i++) {
7041 mv_f[i].filter_type = filter_type;
7042 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7045 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7046 filter_type == RTE_MACVLAN_HASH_MATCH) {
7047 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7048 if (ret != I40E_SUCCESS)
7052 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7053 if (ret != I40E_SUCCESS)
7056 /* Remove the mac addr into mac list */
7057 TAILQ_REMOVE(&vsi->mac_list, f, next);
7067 /* Configure hash enable flags for RSS */
7069 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7077 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7078 if (flags & (1ULL << i))
7079 hena |= adapter->pctypes_tbl[i];
7085 /* Parse the hash enable flags */
7087 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7089 uint64_t rss_hf = 0;
7095 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7096 if (flags & adapter->pctypes_tbl[i])
7097 rss_hf |= (1ULL << i);
7104 i40e_pf_disable_rss(struct i40e_pf *pf)
7106 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7108 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7109 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7110 I40E_WRITE_FLUSH(hw);
7114 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7116 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7117 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7118 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7119 I40E_VFQF_HKEY_MAX_INDEX :
7120 I40E_PFQF_HKEY_MAX_INDEX;
7123 if (!key || key_len == 0) {
7124 PMD_DRV_LOG(DEBUG, "No key to be configured");
7126 } else if (key_len != (key_idx + 1) *
7128 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7132 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7133 struct i40e_aqc_get_set_rss_key_data *key_dw =
7134 (struct i40e_aqc_get_set_rss_key_data *)key;
7136 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7138 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7140 uint32_t *hash_key = (uint32_t *)key;
7143 if (vsi->type == I40E_VSI_SRIOV) {
7144 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7147 I40E_VFQF_HKEY1(i, vsi->user_param),
7151 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7152 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7155 I40E_WRITE_FLUSH(hw);
7162 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7164 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7165 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7169 if (!key || !key_len)
7172 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7173 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7174 (struct i40e_aqc_get_set_rss_key_data *)key);
7176 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7180 uint32_t *key_dw = (uint32_t *)key;
7183 if (vsi->type == I40E_VSI_SRIOV) {
7184 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7185 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7186 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7188 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7191 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7192 reg = I40E_PFQF_HKEY(i);
7193 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7195 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7203 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7205 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7209 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7210 rss_conf->rss_key_len);
7214 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7215 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7216 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7217 I40E_WRITE_FLUSH(hw);
7223 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7224 struct rte_eth_rss_conf *rss_conf)
7226 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7227 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7228 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7231 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7232 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7234 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7235 if (rss_hf != 0) /* Enable RSS */
7237 return 0; /* Nothing to do */
7240 if (rss_hf == 0) /* Disable RSS */
7243 return i40e_hw_rss_hash_set(pf, rss_conf);
7247 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7248 struct rte_eth_rss_conf *rss_conf)
7250 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7251 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7254 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7255 &rss_conf->rss_key_len);
7257 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7258 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7259 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7265 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7267 switch (filter_type) {
7268 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7269 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7271 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7272 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7274 case RTE_TUNNEL_FILTER_IMAC_TENID:
7275 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7277 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7278 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7280 case ETH_TUNNEL_FILTER_IMAC:
7281 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7283 case ETH_TUNNEL_FILTER_OIP:
7284 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7286 case ETH_TUNNEL_FILTER_IIP:
7287 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7290 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7297 /* Convert tunnel filter structure */
7299 i40e_tunnel_filter_convert(
7300 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7301 struct i40e_tunnel_filter *tunnel_filter)
7303 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7304 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7305 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7306 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7307 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7308 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7309 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7310 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7311 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7313 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7314 tunnel_filter->input.flags = cld_filter->element.flags;
7315 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7316 tunnel_filter->queue = cld_filter->element.queue_number;
7317 rte_memcpy(tunnel_filter->input.general_fields,
7318 cld_filter->general_fields,
7319 sizeof(cld_filter->general_fields));
7324 /* Check if there exists the tunnel filter */
7325 struct i40e_tunnel_filter *
7326 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7327 const struct i40e_tunnel_filter_input *input)
7331 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7335 return tunnel_rule->hash_map[ret];
7338 /* Add a tunnel filter into the SW list */
7340 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7341 struct i40e_tunnel_filter *tunnel_filter)
7343 struct i40e_tunnel_rule *rule = &pf->tunnel;
7346 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7349 "Failed to insert tunnel filter to hash table %d!",
7353 rule->hash_map[ret] = tunnel_filter;
7355 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7360 /* Delete a tunnel filter from the SW list */
7362 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7363 struct i40e_tunnel_filter_input *input)
7365 struct i40e_tunnel_rule *rule = &pf->tunnel;
7366 struct i40e_tunnel_filter *tunnel_filter;
7369 ret = rte_hash_del_key(rule->hash_table, input);
7372 "Failed to delete tunnel filter to hash table %d!",
7376 tunnel_filter = rule->hash_map[ret];
7377 rule->hash_map[ret] = NULL;
7379 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7380 rte_free(tunnel_filter);
7386 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7387 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7391 uint32_t ipv4_addr, ipv4_addr_le;
7392 uint8_t i, tun_type = 0;
7393 /* internal varialbe to convert ipv6 byte order */
7394 uint32_t convert_ipv6[4];
7396 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7397 struct i40e_vsi *vsi = pf->main_vsi;
7398 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7399 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7400 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7401 struct i40e_tunnel_filter *tunnel, *node;
7402 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7404 cld_filter = rte_zmalloc("tunnel_filter",
7405 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7408 if (NULL == cld_filter) {
7409 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7412 pfilter = cld_filter;
7414 ether_addr_copy(&tunnel_filter->outer_mac,
7415 (struct ether_addr *)&pfilter->element.outer_mac);
7416 ether_addr_copy(&tunnel_filter->inner_mac,
7417 (struct ether_addr *)&pfilter->element.inner_mac);
7419 pfilter->element.inner_vlan =
7420 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7421 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7422 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7423 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7424 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7425 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7427 sizeof(pfilter->element.ipaddr.v4.data));
7429 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7430 for (i = 0; i < 4; i++) {
7432 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7434 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7436 sizeof(pfilter->element.ipaddr.v6.data));
7439 /* check tunneled type */
7440 switch (tunnel_filter->tunnel_type) {
7441 case RTE_TUNNEL_TYPE_VXLAN:
7442 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7444 case RTE_TUNNEL_TYPE_NVGRE:
7445 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7447 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7448 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7451 /* Other tunnel types is not supported. */
7452 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7453 rte_free(cld_filter);
7457 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7458 &pfilter->element.flags);
7460 rte_free(cld_filter);
7464 pfilter->element.flags |= rte_cpu_to_le_16(
7465 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7466 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7467 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7468 pfilter->element.queue_number =
7469 rte_cpu_to_le_16(tunnel_filter->queue_id);
7471 /* Check if there is the filter in SW list */
7472 memset(&check_filter, 0, sizeof(check_filter));
7473 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7474 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7476 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7477 rte_free(cld_filter);
7481 if (!add && !node) {
7482 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7483 rte_free(cld_filter);
7488 ret = i40e_aq_add_cloud_filters(hw,
7489 vsi->seid, &cld_filter->element, 1);
7491 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7492 rte_free(cld_filter);
7495 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7496 if (tunnel == NULL) {
7497 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7498 rte_free(cld_filter);
7502 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7503 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7507 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7508 &cld_filter->element, 1);
7510 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7511 rte_free(cld_filter);
7514 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7517 rte_free(cld_filter);
7521 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7522 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7523 #define I40E_TR_GENEVE_KEY_MASK 0x8
7524 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7525 #define I40E_TR_GRE_KEY_MASK 0x400
7526 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7527 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7530 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7532 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7533 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7534 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7535 enum i40e_status_code status = I40E_SUCCESS;
7537 if (pf->support_multi_driver) {
7538 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7539 return I40E_NOT_SUPPORTED;
7542 memset(&filter_replace, 0,
7543 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7544 memset(&filter_replace_buf, 0,
7545 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7547 /* create L1 filter */
7548 filter_replace.old_filter_type =
7549 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7550 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7551 filter_replace.tr_bit = 0;
7553 /* Prepare the buffer, 3 entries */
7554 filter_replace_buf.data[0] =
7555 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7556 filter_replace_buf.data[0] |=
7557 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7558 filter_replace_buf.data[2] = 0xFF;
7559 filter_replace_buf.data[3] = 0xFF;
7560 filter_replace_buf.data[4] =
7561 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7562 filter_replace_buf.data[4] |=
7563 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7564 filter_replace_buf.data[7] = 0xF0;
7565 filter_replace_buf.data[8]
7566 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7567 filter_replace_buf.data[8] |=
7568 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7569 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7570 I40E_TR_GENEVE_KEY_MASK |
7571 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7572 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7573 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7574 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7576 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7577 &filter_replace_buf);
7579 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7580 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7581 "cloud l1 type is changed from 0x%x to 0x%x",
7582 filter_replace.old_filter_type,
7583 filter_replace.new_filter_type);
7589 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7591 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7592 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7593 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7594 enum i40e_status_code status = I40E_SUCCESS;
7596 if (pf->support_multi_driver) {
7597 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7598 return I40E_NOT_SUPPORTED;
7602 memset(&filter_replace, 0,
7603 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7604 memset(&filter_replace_buf, 0,
7605 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7606 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7607 I40E_AQC_MIRROR_CLOUD_FILTER;
7608 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7609 filter_replace.new_filter_type =
7610 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7611 /* Prepare the buffer, 2 entries */
7612 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7613 filter_replace_buf.data[0] |=
7614 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7615 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7616 filter_replace_buf.data[4] |=
7617 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7618 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7619 &filter_replace_buf);
7622 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7623 "cloud filter type is changed from 0x%x to 0x%x",
7624 filter_replace.old_filter_type,
7625 filter_replace.new_filter_type);
7628 memset(&filter_replace, 0,
7629 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7630 memset(&filter_replace_buf, 0,
7631 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7633 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7634 I40E_AQC_MIRROR_CLOUD_FILTER;
7635 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7636 filter_replace.new_filter_type =
7637 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7638 /* Prepare the buffer, 2 entries */
7639 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7640 filter_replace_buf.data[0] |=
7641 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7642 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7643 filter_replace_buf.data[4] |=
7644 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7646 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7647 &filter_replace_buf);
7649 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7650 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7651 "cloud filter type is changed from 0x%x to 0x%x",
7652 filter_replace.old_filter_type,
7653 filter_replace.new_filter_type);
7658 static enum i40e_status_code
7659 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7661 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7662 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7663 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7664 enum i40e_status_code status = I40E_SUCCESS;
7666 if (pf->support_multi_driver) {
7667 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7668 return I40E_NOT_SUPPORTED;
7672 memset(&filter_replace, 0,
7673 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7674 memset(&filter_replace_buf, 0,
7675 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7676 /* create L1 filter */
7677 filter_replace.old_filter_type =
7678 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7679 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7680 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7681 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7682 /* Prepare the buffer, 2 entries */
7683 filter_replace_buf.data[0] =
7684 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7685 filter_replace_buf.data[0] |=
7686 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7687 filter_replace_buf.data[2] = 0xFF;
7688 filter_replace_buf.data[3] = 0xFF;
7689 filter_replace_buf.data[4] =
7690 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7691 filter_replace_buf.data[4] |=
7692 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7693 filter_replace_buf.data[6] = 0xFF;
7694 filter_replace_buf.data[7] = 0xFF;
7695 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7696 &filter_replace_buf);
7699 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7700 "cloud l1 type is changed from 0x%x to 0x%x",
7701 filter_replace.old_filter_type,
7702 filter_replace.new_filter_type);
7705 memset(&filter_replace, 0,
7706 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7707 memset(&filter_replace_buf, 0,
7708 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7709 /* create L1 filter */
7710 filter_replace.old_filter_type =
7711 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7712 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7713 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7714 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7715 /* Prepare the buffer, 2 entries */
7716 filter_replace_buf.data[0] =
7717 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7718 filter_replace_buf.data[0] |=
7719 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7720 filter_replace_buf.data[2] = 0xFF;
7721 filter_replace_buf.data[3] = 0xFF;
7722 filter_replace_buf.data[4] =
7723 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7724 filter_replace_buf.data[4] |=
7725 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7726 filter_replace_buf.data[6] = 0xFF;
7727 filter_replace_buf.data[7] = 0xFF;
7729 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7730 &filter_replace_buf);
7732 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7733 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7734 "cloud l1 type is changed from 0x%x to 0x%x",
7735 filter_replace.old_filter_type,
7736 filter_replace.new_filter_type);
7742 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7744 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7745 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7747 enum i40e_status_code status = I40E_SUCCESS;
7749 if (pf->support_multi_driver) {
7750 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7751 return I40E_NOT_SUPPORTED;
7755 memset(&filter_replace, 0,
7756 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7757 memset(&filter_replace_buf, 0,
7758 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7759 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7760 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7761 filter_replace.new_filter_type =
7762 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7763 /* Prepare the buffer, 2 entries */
7764 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7765 filter_replace_buf.data[0] |=
7766 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7767 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7768 filter_replace_buf.data[4] |=
7769 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7770 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7771 &filter_replace_buf);
7774 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7775 "cloud filter type is changed from 0x%x to 0x%x",
7776 filter_replace.old_filter_type,
7777 filter_replace.new_filter_type);
7780 memset(&filter_replace, 0,
7781 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7782 memset(&filter_replace_buf, 0,
7783 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7784 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7785 filter_replace.old_filter_type =
7786 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7787 filter_replace.new_filter_type =
7788 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7789 /* Prepare the buffer, 2 entries */
7790 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7791 filter_replace_buf.data[0] |=
7792 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7793 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7794 filter_replace_buf.data[4] |=
7795 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7797 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7798 &filter_replace_buf);
7800 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7801 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7802 "cloud filter type is changed from 0x%x to 0x%x",
7803 filter_replace.old_filter_type,
7804 filter_replace.new_filter_type);
7810 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7811 struct i40e_tunnel_filter_conf *tunnel_filter,
7815 uint32_t ipv4_addr, ipv4_addr_le;
7816 uint8_t i, tun_type = 0;
7817 /* internal variable to convert ipv6 byte order */
7818 uint32_t convert_ipv6[4];
7820 struct i40e_pf_vf *vf = NULL;
7821 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7822 struct i40e_vsi *vsi;
7823 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7824 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7825 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7826 struct i40e_tunnel_filter *tunnel, *node;
7827 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7829 bool big_buffer = 0;
7831 cld_filter = rte_zmalloc("tunnel_filter",
7832 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7835 if (cld_filter == NULL) {
7836 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7839 pfilter = cld_filter;
7841 ether_addr_copy(&tunnel_filter->outer_mac,
7842 (struct ether_addr *)&pfilter->element.outer_mac);
7843 ether_addr_copy(&tunnel_filter->inner_mac,
7844 (struct ether_addr *)&pfilter->element.inner_mac);
7846 pfilter->element.inner_vlan =
7847 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7848 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7849 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7850 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7851 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7852 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7854 sizeof(pfilter->element.ipaddr.v4.data));
7856 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7857 for (i = 0; i < 4; i++) {
7859 rte_cpu_to_le_32(rte_be_to_cpu_32(
7860 tunnel_filter->ip_addr.ipv6_addr[i]));
7862 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7864 sizeof(pfilter->element.ipaddr.v6.data));
7867 /* check tunneled type */
7868 switch (tunnel_filter->tunnel_type) {
7869 case I40E_TUNNEL_TYPE_VXLAN:
7870 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7872 case I40E_TUNNEL_TYPE_NVGRE:
7873 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7875 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7876 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7878 case I40E_TUNNEL_TYPE_MPLSoUDP:
7879 if (!pf->mpls_replace_flag) {
7880 i40e_replace_mpls_l1_filter(pf);
7881 i40e_replace_mpls_cloud_filter(pf);
7882 pf->mpls_replace_flag = 1;
7884 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7885 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7887 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7888 (teid_le & 0xF) << 12;
7889 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7892 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7894 case I40E_TUNNEL_TYPE_MPLSoGRE:
7895 if (!pf->mpls_replace_flag) {
7896 i40e_replace_mpls_l1_filter(pf);
7897 i40e_replace_mpls_cloud_filter(pf);
7898 pf->mpls_replace_flag = 1;
7900 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7901 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7903 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7904 (teid_le & 0xF) << 12;
7905 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7908 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7910 case I40E_TUNNEL_TYPE_GTPC:
7911 if (!pf->gtp_replace_flag) {
7912 i40e_replace_gtp_l1_filter(pf);
7913 i40e_replace_gtp_cloud_filter(pf);
7914 pf->gtp_replace_flag = 1;
7916 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7917 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7918 (teid_le >> 16) & 0xFFFF;
7919 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7921 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7925 case I40E_TUNNEL_TYPE_GTPU:
7926 if (!pf->gtp_replace_flag) {
7927 i40e_replace_gtp_l1_filter(pf);
7928 i40e_replace_gtp_cloud_filter(pf);
7929 pf->gtp_replace_flag = 1;
7931 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7932 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7933 (teid_le >> 16) & 0xFFFF;
7934 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7936 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7940 case I40E_TUNNEL_TYPE_QINQ:
7941 if (!pf->qinq_replace_flag) {
7942 ret = i40e_cloud_filter_qinq_create(pf);
7945 "QinQ tunnel filter already created.");
7946 pf->qinq_replace_flag = 1;
7948 /* Add in the General fields the values of
7949 * the Outer and Inner VLAN
7950 * Big Buffer should be set, see changes in
7951 * i40e_aq_add_cloud_filters
7953 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7954 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7958 /* Other tunnel types is not supported. */
7959 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7960 rte_free(cld_filter);
7964 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7965 pfilter->element.flags =
7966 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7967 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7968 pfilter->element.flags =
7969 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7970 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7971 pfilter->element.flags =
7972 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7973 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7974 pfilter->element.flags =
7975 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7976 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7977 pfilter->element.flags |=
7978 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7980 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7981 &pfilter->element.flags);
7983 rte_free(cld_filter);
7988 pfilter->element.flags |= rte_cpu_to_le_16(
7989 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7990 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7991 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7992 pfilter->element.queue_number =
7993 rte_cpu_to_le_16(tunnel_filter->queue_id);
7995 if (!tunnel_filter->is_to_vf)
7998 if (tunnel_filter->vf_id >= pf->vf_num) {
7999 PMD_DRV_LOG(ERR, "Invalid argument.");
8000 rte_free(cld_filter);
8003 vf = &pf->vfs[tunnel_filter->vf_id];
8007 /* Check if there is the filter in SW list */
8008 memset(&check_filter, 0, sizeof(check_filter));
8009 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8010 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8011 check_filter.vf_id = tunnel_filter->vf_id;
8012 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8014 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8015 rte_free(cld_filter);
8019 if (!add && !node) {
8020 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8021 rte_free(cld_filter);
8027 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8028 vsi->seid, cld_filter, 1);
8030 ret = i40e_aq_add_cloud_filters(hw,
8031 vsi->seid, &cld_filter->element, 1);
8033 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8034 rte_free(cld_filter);
8037 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8038 if (tunnel == NULL) {
8039 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8040 rte_free(cld_filter);
8044 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8045 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8050 ret = i40e_aq_remove_cloud_filters_big_buffer(
8051 hw, vsi->seid, cld_filter, 1);
8053 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8054 &cld_filter->element, 1);
8056 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8057 rte_free(cld_filter);
8060 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8063 rte_free(cld_filter);
8068 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8072 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8073 if (pf->vxlan_ports[i] == port)
8081 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8085 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8087 idx = i40e_get_vxlan_port_idx(pf, port);
8089 /* Check if port already exists */
8091 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8095 /* Now check if there is space to add the new port */
8096 idx = i40e_get_vxlan_port_idx(pf, 0);
8099 "Maximum number of UDP ports reached, not adding port %d",
8104 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8107 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8111 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8114 /* New port: add it and mark its index in the bitmap */
8115 pf->vxlan_ports[idx] = port;
8116 pf->vxlan_bitmap |= (1 << idx);
8118 if (!(pf->flags & I40E_FLAG_VXLAN))
8119 pf->flags |= I40E_FLAG_VXLAN;
8125 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8128 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8130 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8131 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8135 idx = i40e_get_vxlan_port_idx(pf, port);
8138 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8142 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8143 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8147 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8150 pf->vxlan_ports[idx] = 0;
8151 pf->vxlan_bitmap &= ~(1 << idx);
8153 if (!pf->vxlan_bitmap)
8154 pf->flags &= ~I40E_FLAG_VXLAN;
8159 /* Add UDP tunneling port */
8161 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8162 struct rte_eth_udp_tunnel *udp_tunnel)
8165 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8167 if (udp_tunnel == NULL)
8170 switch (udp_tunnel->prot_type) {
8171 case RTE_TUNNEL_TYPE_VXLAN:
8172 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8175 case RTE_TUNNEL_TYPE_GENEVE:
8176 case RTE_TUNNEL_TYPE_TEREDO:
8177 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8182 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8190 /* Remove UDP tunneling port */
8192 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8193 struct rte_eth_udp_tunnel *udp_tunnel)
8196 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8198 if (udp_tunnel == NULL)
8201 switch (udp_tunnel->prot_type) {
8202 case RTE_TUNNEL_TYPE_VXLAN:
8203 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8205 case RTE_TUNNEL_TYPE_GENEVE:
8206 case RTE_TUNNEL_TYPE_TEREDO:
8207 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8211 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8219 /* Calculate the maximum number of contiguous PF queues that are configured */
8221 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8223 struct rte_eth_dev_data *data = pf->dev_data;
8225 struct i40e_rx_queue *rxq;
8228 for (i = 0; i < pf->lan_nb_qps; i++) {
8229 rxq = data->rx_queues[i];
8230 if (rxq && rxq->q_set)
8241 i40e_pf_config_rss(struct i40e_pf *pf)
8243 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8244 struct rte_eth_rss_conf rss_conf;
8245 uint32_t i, lut = 0;
8249 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8250 * It's necessary to calculate the actual PF queues that are configured.
8252 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8253 num = i40e_pf_calc_configured_queues_num(pf);
8255 num = pf->dev_data->nb_rx_queues;
8257 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8258 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8262 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8266 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8269 lut = (lut << 8) | (j & ((0x1 <<
8270 hw->func_caps.rss_table_entry_width) - 1));
8272 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8275 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8276 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8277 i40e_pf_disable_rss(pf);
8280 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8281 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8282 /* Random default keys */
8283 static uint32_t rss_key_default[] = {0x6b793944,
8284 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8285 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8286 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8288 rss_conf.rss_key = (uint8_t *)rss_key_default;
8289 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8293 return i40e_hw_rss_hash_set(pf, &rss_conf);
8297 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8298 struct rte_eth_tunnel_filter_conf *filter)
8300 if (pf == NULL || filter == NULL) {
8301 PMD_DRV_LOG(ERR, "Invalid parameter");
8305 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8306 PMD_DRV_LOG(ERR, "Invalid queue ID");
8310 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8311 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8315 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8316 (is_zero_ether_addr(&filter->outer_mac))) {
8317 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8321 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8322 (is_zero_ether_addr(&filter->inner_mac))) {
8323 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8330 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8331 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8333 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8335 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8339 if (pf->support_multi_driver) {
8340 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8344 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8345 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8348 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8349 } else if (len == 4) {
8350 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8352 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8357 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8361 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8362 "with value 0x%08x",
8363 I40E_GL_PRS_FVBM(2), reg);
8364 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8368 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8369 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8375 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8382 switch (cfg->cfg_type) {
8383 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8384 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8387 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8395 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8396 enum rte_filter_op filter_op,
8399 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8400 int ret = I40E_ERR_PARAM;
8402 switch (filter_op) {
8403 case RTE_ETH_FILTER_SET:
8404 ret = i40e_dev_global_config_set(hw,
8405 (struct rte_eth_global_cfg *)arg);
8408 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8416 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8417 enum rte_filter_op filter_op,
8420 struct rte_eth_tunnel_filter_conf *filter;
8421 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8422 int ret = I40E_SUCCESS;
8424 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8426 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8427 return I40E_ERR_PARAM;
8429 switch (filter_op) {
8430 case RTE_ETH_FILTER_NOP:
8431 if (!(pf->flags & I40E_FLAG_VXLAN))
8432 ret = I40E_NOT_SUPPORTED;
8434 case RTE_ETH_FILTER_ADD:
8435 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8437 case RTE_ETH_FILTER_DELETE:
8438 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8441 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8442 ret = I40E_ERR_PARAM;
8450 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8453 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8456 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8457 ret = i40e_pf_config_rss(pf);
8459 i40e_pf_disable_rss(pf);
8464 /* Get the symmetric hash enable configurations per port */
8466 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8468 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8470 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8473 /* Set the symmetric hash enable configurations per port */
8475 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8477 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8480 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8482 "Symmetric hash has already been enabled");
8485 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8487 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8489 "Symmetric hash has already been disabled");
8492 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8494 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8495 I40E_WRITE_FLUSH(hw);
8499 * Get global configurations of hash function type and symmetric hash enable
8500 * per flow type (pctype). Note that global configuration means it affects all
8501 * the ports on the same NIC.
8504 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8505 struct rte_eth_hash_global_conf *g_cfg)
8507 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8511 memset(g_cfg, 0, sizeof(*g_cfg));
8512 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8513 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8514 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8516 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8517 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8518 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8521 * As i40e supports less than 64 flow types, only first 64 bits need to
8524 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8525 g_cfg->valid_bit_mask[i] = 0ULL;
8526 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8529 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8531 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8532 if (!adapter->pctypes_tbl[i])
8534 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8535 j < I40E_FILTER_PCTYPE_MAX; j++) {
8536 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8537 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8538 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8539 g_cfg->sym_hash_enable_mask[0] |=
8550 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8551 const struct rte_eth_hash_global_conf *g_cfg)
8554 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8556 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8557 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8558 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8559 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8565 * As i40e supports less than 64 flow types, only first 64 bits need to
8568 mask0 = g_cfg->valid_bit_mask[0];
8569 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8571 /* Check if any unsupported flow type configured */
8572 if ((mask0 | i40e_mask) ^ i40e_mask)
8575 if (g_cfg->valid_bit_mask[i])
8583 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8589 * Set global configurations of hash function type and symmetric hash enable
8590 * per flow type (pctype). Note any modifying global configuration will affect
8591 * all the ports on the same NIC.
8594 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8595 struct rte_eth_hash_global_conf *g_cfg)
8597 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8598 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8602 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8604 if (pf->support_multi_driver) {
8605 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8609 /* Check the input parameters */
8610 ret = i40e_hash_global_config_check(adapter, g_cfg);
8615 * As i40e supports less than 64 flow types, only first 64 bits need to
8618 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8619 if (mask0 & (1UL << i)) {
8620 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8621 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8623 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8624 j < I40E_FILTER_PCTYPE_MAX; j++) {
8625 if (adapter->pctypes_tbl[i] & (1ULL << j))
8626 i40e_write_global_rx_ctl(hw,
8630 i40e_global_cfg_warning(I40E_WARNING_HSYM);
8634 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8635 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8637 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8639 "Hash function already set to Toeplitz");
8642 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8643 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8645 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8647 "Hash function already set to Simple XOR");
8650 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8652 /* Use the default, and keep it as it is */
8655 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8656 i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8659 I40E_WRITE_FLUSH(hw);
8665 * Valid input sets for hash and flow director filters per PCTYPE
8668 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8669 enum rte_filter_type filter)
8673 static const uint64_t valid_hash_inset_table[] = {
8674 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8675 I40E_INSET_DMAC | I40E_INSET_SMAC |
8676 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8677 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8678 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8679 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8680 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8681 I40E_INSET_FLEX_PAYLOAD,
8682 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8683 I40E_INSET_DMAC | I40E_INSET_SMAC |
8684 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8685 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8686 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8687 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8688 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8689 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8690 I40E_INSET_FLEX_PAYLOAD,
8691 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8692 I40E_INSET_DMAC | I40E_INSET_SMAC |
8693 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8694 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8695 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8696 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8697 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8698 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8699 I40E_INSET_FLEX_PAYLOAD,
8700 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8701 I40E_INSET_DMAC | I40E_INSET_SMAC |
8702 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8703 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8704 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8705 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8706 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8707 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8708 I40E_INSET_FLEX_PAYLOAD,
8709 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8710 I40E_INSET_DMAC | I40E_INSET_SMAC |
8711 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8712 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8713 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8714 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8715 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8716 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8717 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8718 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8719 I40E_INSET_DMAC | I40E_INSET_SMAC |
8720 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8721 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8722 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8723 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8724 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8725 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8726 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8727 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8728 I40E_INSET_DMAC | I40E_INSET_SMAC |
8729 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8730 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8731 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8732 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8733 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8734 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8735 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8736 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8737 I40E_INSET_DMAC | I40E_INSET_SMAC |
8738 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8739 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8740 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8741 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8742 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8743 I40E_INSET_FLEX_PAYLOAD,
8744 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8745 I40E_INSET_DMAC | I40E_INSET_SMAC |
8746 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8747 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8748 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8749 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8750 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8751 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8752 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8753 I40E_INSET_DMAC | I40E_INSET_SMAC |
8754 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8755 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8756 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8757 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8758 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8759 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8760 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8761 I40E_INSET_DMAC | I40E_INSET_SMAC |
8762 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8763 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8764 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8765 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8766 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8767 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8768 I40E_INSET_FLEX_PAYLOAD,
8769 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8770 I40E_INSET_DMAC | I40E_INSET_SMAC |
8771 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8772 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8773 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8774 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8775 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8776 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8777 I40E_INSET_FLEX_PAYLOAD,
8778 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8779 I40E_INSET_DMAC | I40E_INSET_SMAC |
8780 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8781 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8782 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8783 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8784 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8785 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8786 I40E_INSET_FLEX_PAYLOAD,
8787 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8788 I40E_INSET_DMAC | I40E_INSET_SMAC |
8789 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8790 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8791 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8792 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8793 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8794 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8795 I40E_INSET_FLEX_PAYLOAD,
8796 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8797 I40E_INSET_DMAC | I40E_INSET_SMAC |
8798 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8799 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8800 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8801 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8802 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8803 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8804 I40E_INSET_FLEX_PAYLOAD,
8805 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8806 I40E_INSET_DMAC | I40E_INSET_SMAC |
8807 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8808 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8809 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8810 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8811 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8812 I40E_INSET_FLEX_PAYLOAD,
8813 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8814 I40E_INSET_DMAC | I40E_INSET_SMAC |
8815 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8816 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8817 I40E_INSET_FLEX_PAYLOAD,
8821 * Flow director supports only fields defined in
8822 * union rte_eth_fdir_flow.
8824 static const uint64_t valid_fdir_inset_table[] = {
8825 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8826 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8827 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8828 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8829 I40E_INSET_IPV4_TTL,
8830 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8831 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8832 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8833 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8834 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8835 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8836 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8837 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8838 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8839 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8840 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8841 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8842 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8843 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8844 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8845 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8846 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8847 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8848 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8849 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8850 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8851 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8852 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8853 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8854 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8855 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8856 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8857 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8858 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8859 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8861 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8862 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8863 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8864 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8865 I40E_INSET_IPV4_TTL,
8866 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8867 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8868 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8869 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8870 I40E_INSET_IPV6_HOP_LIMIT,
8871 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8872 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8873 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8874 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8875 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8876 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8877 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8878 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8879 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8880 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8881 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8882 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8883 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8884 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8885 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8886 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8887 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8888 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8889 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8890 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8891 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8892 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8893 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8894 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8895 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8896 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8897 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8898 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8899 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8900 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8902 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8903 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8904 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8905 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8906 I40E_INSET_IPV6_HOP_LIMIT,
8907 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8908 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8909 I40E_INSET_LAST_ETHER_TYPE,
8912 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8914 if (filter == RTE_ETH_FILTER_HASH)
8915 valid = valid_hash_inset_table[pctype];
8917 valid = valid_fdir_inset_table[pctype];
8923 * Validate if the input set is allowed for a specific PCTYPE
8926 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8927 enum rte_filter_type filter, uint64_t inset)
8931 valid = i40e_get_valid_input_set(pctype, filter);
8932 if (inset & (~valid))
8938 /* default input set fields combination per pctype */
8940 i40e_get_default_input_set(uint16_t pctype)
8942 static const uint64_t default_inset_table[] = {
8943 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8944 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8945 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8946 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8947 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8948 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8949 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8950 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8951 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8952 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8953 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8954 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8955 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8956 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8957 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8958 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8959 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8960 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8961 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8962 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8964 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8965 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8966 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8967 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8968 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8969 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8970 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8971 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8972 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8973 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8974 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8975 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8976 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8977 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8978 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8979 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8980 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8981 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8982 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8983 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8984 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8985 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8987 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8988 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8989 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8990 I40E_INSET_LAST_ETHER_TYPE,
8993 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8996 return default_inset_table[pctype];
9000 * Parse the input set from index to logical bit masks
9003 i40e_parse_input_set(uint64_t *inset,
9004 enum i40e_filter_pctype pctype,
9005 enum rte_eth_input_set_field *field,
9011 static const struct {
9012 enum rte_eth_input_set_field field;
9014 } inset_convert_table[] = {
9015 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9016 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9017 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9018 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9019 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9020 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9021 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9022 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9023 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9024 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9025 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9026 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9027 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9028 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9029 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9030 I40E_INSET_IPV6_NEXT_HDR},
9031 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9032 I40E_INSET_IPV6_HOP_LIMIT},
9033 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9034 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9035 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9036 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9037 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9038 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9039 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9040 I40E_INSET_SCTP_VT},
9041 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9042 I40E_INSET_TUNNEL_DMAC},
9043 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9044 I40E_INSET_VLAN_TUNNEL},
9045 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9046 I40E_INSET_TUNNEL_ID},
9047 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9048 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9049 I40E_INSET_FLEX_PAYLOAD_W1},
9050 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9051 I40E_INSET_FLEX_PAYLOAD_W2},
9052 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9053 I40E_INSET_FLEX_PAYLOAD_W3},
9054 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9055 I40E_INSET_FLEX_PAYLOAD_W4},
9056 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9057 I40E_INSET_FLEX_PAYLOAD_W5},
9058 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9059 I40E_INSET_FLEX_PAYLOAD_W6},
9060 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9061 I40E_INSET_FLEX_PAYLOAD_W7},
9062 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9063 I40E_INSET_FLEX_PAYLOAD_W8},
9066 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9069 /* Only one item allowed for default or all */
9071 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9072 *inset = i40e_get_default_input_set(pctype);
9074 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9075 *inset = I40E_INSET_NONE;
9080 for (i = 0, *inset = 0; i < size; i++) {
9081 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9082 if (field[i] == inset_convert_table[j].field) {
9083 *inset |= inset_convert_table[j].inset;
9088 /* It contains unsupported input set, return immediately */
9089 if (j == RTE_DIM(inset_convert_table))
9097 * Translate the input set from bit masks to register aware bit masks
9101 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9111 static const struct inset_map inset_map_common[] = {
9112 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9113 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9114 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9115 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9116 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9117 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9118 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9119 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9120 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9121 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9122 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9123 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9124 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9125 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9126 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9127 {I40E_INSET_TUNNEL_DMAC,
9128 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9129 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9130 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9131 {I40E_INSET_TUNNEL_SRC_PORT,
9132 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9133 {I40E_INSET_TUNNEL_DST_PORT,
9134 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9135 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9136 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9137 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9138 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9139 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9140 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9141 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9142 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9143 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9146 /* some different registers map in x722*/
9147 static const struct inset_map inset_map_diff_x722[] = {
9148 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9149 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9150 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9151 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9154 static const struct inset_map inset_map_diff_not_x722[] = {
9155 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9156 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9157 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9158 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9164 /* Translate input set to register aware inset */
9165 if (type == I40E_MAC_X722) {
9166 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9167 if (input & inset_map_diff_x722[i].inset)
9168 val |= inset_map_diff_x722[i].inset_reg;
9171 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9172 if (input & inset_map_diff_not_x722[i].inset)
9173 val |= inset_map_diff_not_x722[i].inset_reg;
9177 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9178 if (input & inset_map_common[i].inset)
9179 val |= inset_map_common[i].inset_reg;
9186 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9189 uint64_t inset_need_mask = inset;
9191 static const struct {
9194 } inset_mask_map[] = {
9195 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9196 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9197 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9198 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9199 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9200 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9201 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9202 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9205 if (!inset || !mask || !nb_elem)
9208 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9209 /* Clear the inset bit, if no MASK is required,
9210 * for example proto + ttl
9212 if ((inset & inset_mask_map[i].inset) ==
9213 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9214 inset_need_mask &= ~inset_mask_map[i].inset;
9215 if (!inset_need_mask)
9218 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9219 if ((inset_need_mask & inset_mask_map[i].inset) ==
9220 inset_mask_map[i].inset) {
9221 if (idx >= nb_elem) {
9222 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9225 mask[idx] = inset_mask_map[i].mask;
9234 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9236 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9238 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9240 i40e_write_rx_ctl(hw, addr, val);
9241 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9242 (uint32_t)i40e_read_rx_ctl(hw, addr));
9246 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9248 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9250 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9252 i40e_write_global_rx_ctl(hw, addr, val);
9253 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9254 (uint32_t)i40e_read_rx_ctl(hw, addr));
9258 i40e_filter_input_set_init(struct i40e_pf *pf)
9260 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9261 enum i40e_filter_pctype pctype;
9262 uint64_t input_set, inset_reg;
9263 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9267 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9268 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9269 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9271 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9274 input_set = i40e_get_default_input_set(pctype);
9276 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9277 I40E_INSET_MASK_NUM_REG);
9280 if (pf->support_multi_driver && num > 0) {
9281 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9284 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9287 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9288 (uint32_t)(inset_reg & UINT32_MAX));
9289 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9290 (uint32_t)((inset_reg >>
9291 I40E_32_BIT_WIDTH) & UINT32_MAX));
9292 if (!pf->support_multi_driver) {
9293 i40e_check_write_global_reg(hw,
9294 I40E_GLQF_HASH_INSET(0, pctype),
9295 (uint32_t)(inset_reg & UINT32_MAX));
9296 i40e_check_write_global_reg(hw,
9297 I40E_GLQF_HASH_INSET(1, pctype),
9298 (uint32_t)((inset_reg >>
9299 I40E_32_BIT_WIDTH) & UINT32_MAX));
9301 for (i = 0; i < num; i++) {
9302 i40e_check_write_global_reg(hw,
9303 I40E_GLQF_FD_MSK(i, pctype),
9305 i40e_check_write_global_reg(hw,
9306 I40E_GLQF_HASH_MSK(i, pctype),
9309 /*clear unused mask registers of the pctype */
9310 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9311 i40e_check_write_global_reg(hw,
9312 I40E_GLQF_FD_MSK(i, pctype),
9314 i40e_check_write_global_reg(hw,
9315 I40E_GLQF_HASH_MSK(i, pctype),
9319 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9321 I40E_WRITE_FLUSH(hw);
9323 /* store the default input set */
9324 if (!pf->support_multi_driver)
9325 pf->hash_input_set[pctype] = input_set;
9326 pf->fdir.input_set[pctype] = input_set;
9329 if (!pf->support_multi_driver) {
9330 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9331 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9332 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9337 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9338 struct rte_eth_input_set_conf *conf)
9340 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9341 enum i40e_filter_pctype pctype;
9342 uint64_t input_set, inset_reg = 0;
9343 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9347 PMD_DRV_LOG(ERR, "Invalid pointer");
9350 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9351 conf->op != RTE_ETH_INPUT_SET_ADD) {
9352 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9356 if (pf->support_multi_driver) {
9357 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9361 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9362 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9363 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9367 if (hw->mac.type == I40E_MAC_X722) {
9368 /* get translated pctype value in fd pctype register */
9369 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9370 I40E_GLQF_FD_PCTYPES((int)pctype));
9373 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9376 PMD_DRV_LOG(ERR, "Failed to parse input set");
9380 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9381 /* get inset value in register */
9382 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9383 inset_reg <<= I40E_32_BIT_WIDTH;
9384 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9385 input_set |= pf->hash_input_set[pctype];
9387 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9388 I40E_INSET_MASK_NUM_REG);
9392 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9394 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9395 (uint32_t)(inset_reg & UINT32_MAX));
9396 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9397 (uint32_t)((inset_reg >>
9398 I40E_32_BIT_WIDTH) & UINT32_MAX));
9399 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9401 for (i = 0; i < num; i++)
9402 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9404 /*clear unused mask registers of the pctype */
9405 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9406 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9408 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9409 I40E_WRITE_FLUSH(hw);
9411 pf->hash_input_set[pctype] = input_set;
9416 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9417 struct rte_eth_input_set_conf *conf)
9419 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9420 enum i40e_filter_pctype pctype;
9421 uint64_t input_set, inset_reg = 0;
9422 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9426 PMD_DRV_LOG(ERR, "Invalid pointer");
9429 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9430 conf->op != RTE_ETH_INPUT_SET_ADD) {
9431 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9435 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9437 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9438 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9442 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9445 PMD_DRV_LOG(ERR, "Failed to parse input set");
9449 /* get inset value in register */
9450 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9451 inset_reg <<= I40E_32_BIT_WIDTH;
9452 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9454 /* Can not change the inset reg for flex payload for fdir,
9455 * it is done by writing I40E_PRTQF_FD_FLXINSET
9456 * in i40e_set_flex_mask_on_pctype.
9458 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9459 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9461 input_set |= pf->fdir.input_set[pctype];
9462 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9463 I40E_INSET_MASK_NUM_REG);
9466 if (pf->support_multi_driver && num > 0) {
9467 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9471 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9473 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9474 (uint32_t)(inset_reg & UINT32_MAX));
9475 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9476 (uint32_t)((inset_reg >>
9477 I40E_32_BIT_WIDTH) & UINT32_MAX));
9479 if (!pf->support_multi_driver) {
9480 for (i = 0; i < num; i++)
9481 i40e_check_write_global_reg(hw,
9482 I40E_GLQF_FD_MSK(i, pctype),
9484 /*clear unused mask registers of the pctype */
9485 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9486 i40e_check_write_global_reg(hw,
9487 I40E_GLQF_FD_MSK(i, pctype),
9489 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9491 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9493 I40E_WRITE_FLUSH(hw);
9495 pf->fdir.input_set[pctype] = input_set;
9500 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9505 PMD_DRV_LOG(ERR, "Invalid pointer");
9509 switch (info->info_type) {
9510 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9511 i40e_get_symmetric_hash_enable_per_port(hw,
9512 &(info->info.enable));
9514 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9515 ret = i40e_get_hash_filter_global_config(hw,
9516 &(info->info.global_conf));
9519 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9529 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9534 PMD_DRV_LOG(ERR, "Invalid pointer");
9538 switch (info->info_type) {
9539 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9540 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9542 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9543 ret = i40e_set_hash_filter_global_config(hw,
9544 &(info->info.global_conf));
9546 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9547 ret = i40e_hash_filter_inset_select(hw,
9548 &(info->info.input_set_conf));
9552 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9561 /* Operations for hash function */
9563 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9564 enum rte_filter_op filter_op,
9567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9570 switch (filter_op) {
9571 case RTE_ETH_FILTER_NOP:
9573 case RTE_ETH_FILTER_GET:
9574 ret = i40e_hash_filter_get(hw,
9575 (struct rte_eth_hash_filter_info *)arg);
9577 case RTE_ETH_FILTER_SET:
9578 ret = i40e_hash_filter_set(hw,
9579 (struct rte_eth_hash_filter_info *)arg);
9582 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9591 /* Convert ethertype filter structure */
9593 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9594 struct i40e_ethertype_filter *filter)
9596 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9597 filter->input.ether_type = input->ether_type;
9598 filter->flags = input->flags;
9599 filter->queue = input->queue;
9604 /* Check if there exists the ehtertype filter */
9605 struct i40e_ethertype_filter *
9606 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9607 const struct i40e_ethertype_filter_input *input)
9611 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9615 return ethertype_rule->hash_map[ret];
9618 /* Add ethertype filter in SW list */
9620 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9621 struct i40e_ethertype_filter *filter)
9623 struct i40e_ethertype_rule *rule = &pf->ethertype;
9626 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9629 "Failed to insert ethertype filter"
9630 " to hash table %d!",
9634 rule->hash_map[ret] = filter;
9636 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9641 /* Delete ethertype filter in SW list */
9643 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9644 struct i40e_ethertype_filter_input *input)
9646 struct i40e_ethertype_rule *rule = &pf->ethertype;
9647 struct i40e_ethertype_filter *filter;
9650 ret = rte_hash_del_key(rule->hash_table, input);
9653 "Failed to delete ethertype filter"
9654 " to hash table %d!",
9658 filter = rule->hash_map[ret];
9659 rule->hash_map[ret] = NULL;
9661 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9668 * Configure ethertype filter, which can director packet by filtering
9669 * with mac address and ether_type or only ether_type
9672 i40e_ethertype_filter_set(struct i40e_pf *pf,
9673 struct rte_eth_ethertype_filter *filter,
9676 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9677 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9678 struct i40e_ethertype_filter *ethertype_filter, *node;
9679 struct i40e_ethertype_filter check_filter;
9680 struct i40e_control_filter_stats stats;
9684 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9685 PMD_DRV_LOG(ERR, "Invalid queue ID");
9688 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9689 filter->ether_type == ETHER_TYPE_IPv6) {
9691 "unsupported ether_type(0x%04x) in control packet filter.",
9692 filter->ether_type);
9695 if (filter->ether_type == ETHER_TYPE_VLAN)
9696 PMD_DRV_LOG(WARNING,
9697 "filter vlan ether_type in first tag is not supported.");
9699 /* Check if there is the filter in SW list */
9700 memset(&check_filter, 0, sizeof(check_filter));
9701 i40e_ethertype_filter_convert(filter, &check_filter);
9702 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9703 &check_filter.input);
9705 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9709 if (!add && !node) {
9710 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9714 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9715 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9716 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9717 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9718 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9720 memset(&stats, 0, sizeof(stats));
9721 ret = i40e_aq_add_rem_control_packet_filter(hw,
9722 filter->mac_addr.addr_bytes,
9723 filter->ether_type, flags,
9725 filter->queue, add, &stats, NULL);
9728 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9729 ret, stats.mac_etype_used, stats.etype_used,
9730 stats.mac_etype_free, stats.etype_free);
9734 /* Add or delete a filter in SW list */
9736 ethertype_filter = rte_zmalloc("ethertype_filter",
9737 sizeof(*ethertype_filter), 0);
9738 if (ethertype_filter == NULL) {
9739 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9743 rte_memcpy(ethertype_filter, &check_filter,
9744 sizeof(check_filter));
9745 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9747 rte_free(ethertype_filter);
9749 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9756 * Handle operations for ethertype filter.
9759 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9760 enum rte_filter_op filter_op,
9763 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9766 if (filter_op == RTE_ETH_FILTER_NOP)
9770 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9775 switch (filter_op) {
9776 case RTE_ETH_FILTER_ADD:
9777 ret = i40e_ethertype_filter_set(pf,
9778 (struct rte_eth_ethertype_filter *)arg,
9781 case RTE_ETH_FILTER_DELETE:
9782 ret = i40e_ethertype_filter_set(pf,
9783 (struct rte_eth_ethertype_filter *)arg,
9787 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9795 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9796 enum rte_filter_type filter_type,
9797 enum rte_filter_op filter_op,
9805 switch (filter_type) {
9806 case RTE_ETH_FILTER_NONE:
9807 /* For global configuration */
9808 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9810 case RTE_ETH_FILTER_HASH:
9811 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9813 case RTE_ETH_FILTER_MACVLAN:
9814 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9816 case RTE_ETH_FILTER_ETHERTYPE:
9817 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9819 case RTE_ETH_FILTER_TUNNEL:
9820 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9822 case RTE_ETH_FILTER_FDIR:
9823 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9825 case RTE_ETH_FILTER_GENERIC:
9826 if (filter_op != RTE_ETH_FILTER_GET)
9828 *(const void **)arg = &i40e_flow_ops;
9831 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9841 * Check and enable Extended Tag.
9842 * Enabling Extended Tag is important for 40G performance.
9845 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9847 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9851 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9854 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9858 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9859 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9864 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9867 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9871 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9872 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9875 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9876 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9879 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9886 * As some registers wouldn't be reset unless a global hardware reset,
9887 * hardware initialization is needed to put those registers into an
9888 * expected initial state.
9891 i40e_hw_init(struct rte_eth_dev *dev)
9893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9895 i40e_enable_extended_tag(dev);
9897 /* clear the PF Queue Filter control register */
9898 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9900 /* Disable symmetric hash per port */
9901 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9905 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9906 * however this function will return only one highest pctype index,
9907 * which is not quite correct. This is known problem of i40e driver
9908 * and needs to be fixed later.
9910 enum i40e_filter_pctype
9911 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9914 uint64_t pctype_mask;
9916 if (flow_type < I40E_FLOW_TYPE_MAX) {
9917 pctype_mask = adapter->pctypes_tbl[flow_type];
9918 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9919 if (pctype_mask & (1ULL << i))
9920 return (enum i40e_filter_pctype)i;
9923 return I40E_FILTER_PCTYPE_INVALID;
9927 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9928 enum i40e_filter_pctype pctype)
9931 uint64_t pctype_mask = 1ULL << pctype;
9933 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9935 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9939 return RTE_ETH_FLOW_UNKNOWN;
9943 * On X710, performance number is far from the expectation on recent firmware
9944 * versions; on XL710, performance number is also far from the expectation on
9945 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9946 * mode is enabled and port MAC address is equal to the packet destination MAC
9947 * address. The fix for this issue may not be integrated in the following
9948 * firmware version. So the workaround in software driver is needed. It needs
9949 * to modify the initial values of 3 internal only registers for both X710 and
9950 * XL710. Note that the values for X710 or XL710 could be different, and the
9951 * workaround can be removed when it is fixed in firmware in the future.
9954 /* For both X710 and XL710 */
9955 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9956 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9957 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9959 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9960 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9963 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9964 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9967 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9969 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9970 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9973 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9975 enum i40e_status_code status;
9976 struct i40e_aq_get_phy_abilities_resp phy_ab;
9980 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9984 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9987 rte_delay_us(100000);
9989 status = i40e_aq_get_phy_capabilities(hw, false,
9990 true, &phy_ab, NULL);
9998 i40e_configure_registers(struct i40e_hw *hw)
10004 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10005 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10006 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10012 for (i = 0; i < RTE_DIM(reg_table); i++) {
10013 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10014 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10016 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10017 else /* For X710/XL710/XXV710 */
10018 if (hw->aq.fw_maj_ver < 6)
10020 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10023 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10026 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10027 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10029 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10030 else /* For X710/XL710/XXV710 */
10032 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10035 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10036 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
10037 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
10039 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
10040 else /* For X710 */
10042 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
10045 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10048 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10049 reg_table[i].addr);
10052 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10053 reg_table[i].addr, reg);
10054 if (reg == reg_table[i].val)
10057 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10058 reg_table[i].val, NULL);
10061 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10062 reg_table[i].val, reg_table[i].addr);
10065 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10066 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10070 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10071 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10072 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10073 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10075 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10080 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10081 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10085 /* Configure for double VLAN RX stripping */
10086 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10087 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10088 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10089 ret = i40e_aq_debug_write_register(hw,
10090 I40E_VSI_TSR(vsi->vsi_id),
10093 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10095 return I40E_ERR_CONFIG;
10099 /* Configure for double VLAN TX insertion */
10100 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10101 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10102 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10103 ret = i40e_aq_debug_write_register(hw,
10104 I40E_VSI_L2TAGSTXVALID(
10105 vsi->vsi_id), reg, NULL);
10108 "Failed to update VSI_L2TAGSTXVALID[%d]",
10110 return I40E_ERR_CONFIG;
10118 * i40e_aq_add_mirror_rule
10119 * @hw: pointer to the hardware structure
10120 * @seid: VEB seid to add mirror rule to
10121 * @dst_id: destination vsi seid
10122 * @entries: Buffer which contains the entities to be mirrored
10123 * @count: number of entities contained in the buffer
10124 * @rule_id:the rule_id of the rule to be added
10126 * Add a mirror rule for a given veb.
10129 static enum i40e_status_code
10130 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10131 uint16_t seid, uint16_t dst_id,
10132 uint16_t rule_type, uint16_t *entries,
10133 uint16_t count, uint16_t *rule_id)
10135 struct i40e_aq_desc desc;
10136 struct i40e_aqc_add_delete_mirror_rule cmd;
10137 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10138 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10141 enum i40e_status_code status;
10143 i40e_fill_default_direct_cmd_desc(&desc,
10144 i40e_aqc_opc_add_mirror_rule);
10145 memset(&cmd, 0, sizeof(cmd));
10147 buff_len = sizeof(uint16_t) * count;
10148 desc.datalen = rte_cpu_to_le_16(buff_len);
10150 desc.flags |= rte_cpu_to_le_16(
10151 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10152 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10153 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10154 cmd.num_entries = rte_cpu_to_le_16(count);
10155 cmd.seid = rte_cpu_to_le_16(seid);
10156 cmd.destination = rte_cpu_to_le_16(dst_id);
10158 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10159 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10161 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10162 hw->aq.asq_last_status, resp->rule_id,
10163 resp->mirror_rules_used, resp->mirror_rules_free);
10164 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10170 * i40e_aq_del_mirror_rule
10171 * @hw: pointer to the hardware structure
10172 * @seid: VEB seid to add mirror rule to
10173 * @entries: Buffer which contains the entities to be mirrored
10174 * @count: number of entities contained in the buffer
10175 * @rule_id:the rule_id of the rule to be delete
10177 * Delete a mirror rule for a given veb.
10180 static enum i40e_status_code
10181 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10182 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10183 uint16_t count, uint16_t rule_id)
10185 struct i40e_aq_desc desc;
10186 struct i40e_aqc_add_delete_mirror_rule cmd;
10187 uint16_t buff_len = 0;
10188 enum i40e_status_code status;
10191 i40e_fill_default_direct_cmd_desc(&desc,
10192 i40e_aqc_opc_delete_mirror_rule);
10193 memset(&cmd, 0, sizeof(cmd));
10194 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10195 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10197 cmd.num_entries = count;
10198 buff_len = sizeof(uint16_t) * count;
10199 desc.datalen = rte_cpu_to_le_16(buff_len);
10200 buff = (void *)entries;
10202 /* rule id is filled in destination field for deleting mirror rule */
10203 cmd.destination = rte_cpu_to_le_16(rule_id);
10205 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10206 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10207 cmd.seid = rte_cpu_to_le_16(seid);
10209 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10210 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10216 * i40e_mirror_rule_set
10217 * @dev: pointer to the hardware structure
10218 * @mirror_conf: mirror rule info
10219 * @sw_id: mirror rule's sw_id
10220 * @on: enable/disable
10222 * set a mirror rule.
10226 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10227 struct rte_eth_mirror_conf *mirror_conf,
10228 uint8_t sw_id, uint8_t on)
10230 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10231 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10232 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10233 struct i40e_mirror_rule *parent = NULL;
10234 uint16_t seid, dst_seid, rule_id;
10238 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10240 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10242 "mirror rule can not be configured without veb or vfs.");
10245 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10246 PMD_DRV_LOG(ERR, "mirror table is full.");
10249 if (mirror_conf->dst_pool > pf->vf_num) {
10250 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10251 mirror_conf->dst_pool);
10255 seid = pf->main_vsi->veb->seid;
10257 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10258 if (sw_id <= it->index) {
10264 if (mirr_rule && sw_id == mirr_rule->index) {
10266 PMD_DRV_LOG(ERR, "mirror rule exists.");
10269 ret = i40e_aq_del_mirror_rule(hw, seid,
10270 mirr_rule->rule_type,
10271 mirr_rule->entries,
10272 mirr_rule->num_entries, mirr_rule->id);
10275 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10276 ret, hw->aq.asq_last_status);
10279 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10280 rte_free(mirr_rule);
10281 pf->nb_mirror_rule--;
10285 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10289 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10290 sizeof(struct i40e_mirror_rule) , 0);
10292 PMD_DRV_LOG(ERR, "failed to allocate memory");
10293 return I40E_ERR_NO_MEMORY;
10295 switch (mirror_conf->rule_type) {
10296 case ETH_MIRROR_VLAN:
10297 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10298 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10299 mirr_rule->entries[j] =
10300 mirror_conf->vlan.vlan_id[i];
10305 PMD_DRV_LOG(ERR, "vlan is not specified.");
10306 rte_free(mirr_rule);
10309 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10311 case ETH_MIRROR_VIRTUAL_POOL_UP:
10312 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10313 /* check if the specified pool bit is out of range */
10314 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10315 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10316 rte_free(mirr_rule);
10319 for (i = 0, j = 0; i < pf->vf_num; i++) {
10320 if (mirror_conf->pool_mask & (1ULL << i)) {
10321 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10325 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10326 /* add pf vsi to entries */
10327 mirr_rule->entries[j] = pf->main_vsi_seid;
10331 PMD_DRV_LOG(ERR, "pool is not specified.");
10332 rte_free(mirr_rule);
10335 /* egress and ingress in aq commands means from switch but not port */
10336 mirr_rule->rule_type =
10337 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10338 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10339 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10341 case ETH_MIRROR_UPLINK_PORT:
10342 /* egress and ingress in aq commands means from switch but not port*/
10343 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10345 case ETH_MIRROR_DOWNLINK_PORT:
10346 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10349 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10350 mirror_conf->rule_type);
10351 rte_free(mirr_rule);
10355 /* If the dst_pool is equal to vf_num, consider it as PF */
10356 if (mirror_conf->dst_pool == pf->vf_num)
10357 dst_seid = pf->main_vsi_seid;
10359 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10361 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10362 mirr_rule->rule_type, mirr_rule->entries,
10366 "failed to add mirror rule: ret = %d, aq_err = %d.",
10367 ret, hw->aq.asq_last_status);
10368 rte_free(mirr_rule);
10372 mirr_rule->index = sw_id;
10373 mirr_rule->num_entries = j;
10374 mirr_rule->id = rule_id;
10375 mirr_rule->dst_vsi_seid = dst_seid;
10378 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10380 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10382 pf->nb_mirror_rule++;
10387 * i40e_mirror_rule_reset
10388 * @dev: pointer to the device
10389 * @sw_id: mirror rule's sw_id
10391 * reset a mirror rule.
10395 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10397 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10398 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10399 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10403 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10405 seid = pf->main_vsi->veb->seid;
10407 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10408 if (sw_id == it->index) {
10414 ret = i40e_aq_del_mirror_rule(hw, seid,
10415 mirr_rule->rule_type,
10416 mirr_rule->entries,
10417 mirr_rule->num_entries, mirr_rule->id);
10420 "failed to remove mirror rule: status = %d, aq_err = %d.",
10421 ret, hw->aq.asq_last_status);
10424 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10425 rte_free(mirr_rule);
10426 pf->nb_mirror_rule--;
10428 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10435 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10437 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10438 uint64_t systim_cycles;
10440 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10441 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10444 return systim_cycles;
10448 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10450 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10451 uint64_t rx_tstamp;
10453 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10454 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10461 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10463 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10464 uint64_t tx_tstamp;
10466 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10467 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10474 i40e_start_timecounters(struct rte_eth_dev *dev)
10476 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10477 struct i40e_adapter *adapter =
10478 (struct i40e_adapter *)dev->data->dev_private;
10479 struct rte_eth_link link;
10480 uint32_t tsync_inc_l;
10481 uint32_t tsync_inc_h;
10483 /* Get current link speed. */
10484 i40e_dev_link_update(dev, 1);
10485 rte_eth_linkstatus_get(dev, &link);
10487 switch (link.link_speed) {
10488 case ETH_SPEED_NUM_40G:
10489 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10490 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10492 case ETH_SPEED_NUM_10G:
10493 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10494 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10496 case ETH_SPEED_NUM_1G:
10497 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10498 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10505 /* Set the timesync increment value. */
10506 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10507 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10509 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10510 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10511 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10513 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10514 adapter->systime_tc.cc_shift = 0;
10515 adapter->systime_tc.nsec_mask = 0;
10517 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10518 adapter->rx_tstamp_tc.cc_shift = 0;
10519 adapter->rx_tstamp_tc.nsec_mask = 0;
10521 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10522 adapter->tx_tstamp_tc.cc_shift = 0;
10523 adapter->tx_tstamp_tc.nsec_mask = 0;
10527 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10529 struct i40e_adapter *adapter =
10530 (struct i40e_adapter *)dev->data->dev_private;
10532 adapter->systime_tc.nsec += delta;
10533 adapter->rx_tstamp_tc.nsec += delta;
10534 adapter->tx_tstamp_tc.nsec += delta;
10540 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10543 struct i40e_adapter *adapter =
10544 (struct i40e_adapter *)dev->data->dev_private;
10546 ns = rte_timespec_to_ns(ts);
10548 /* Set the timecounters to a new value. */
10549 adapter->systime_tc.nsec = ns;
10550 adapter->rx_tstamp_tc.nsec = ns;
10551 adapter->tx_tstamp_tc.nsec = ns;
10557 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10559 uint64_t ns, systime_cycles;
10560 struct i40e_adapter *adapter =
10561 (struct i40e_adapter *)dev->data->dev_private;
10563 systime_cycles = i40e_read_systime_cyclecounter(dev);
10564 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10565 *ts = rte_ns_to_timespec(ns);
10571 i40e_timesync_enable(struct rte_eth_dev *dev)
10573 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10574 uint32_t tsync_ctl_l;
10575 uint32_t tsync_ctl_h;
10577 /* Stop the timesync system time. */
10578 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10579 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10580 /* Reset the timesync system time value. */
10581 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10582 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10584 i40e_start_timecounters(dev);
10586 /* Clear timesync registers. */
10587 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10588 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10589 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10590 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10591 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10592 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10594 /* Enable timestamping of PTP packets. */
10595 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10596 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10598 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10599 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10600 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10602 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10603 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10609 i40e_timesync_disable(struct rte_eth_dev *dev)
10611 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10612 uint32_t tsync_ctl_l;
10613 uint32_t tsync_ctl_h;
10615 /* Disable timestamping of transmitted PTP packets. */
10616 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10617 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10619 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10620 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10622 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10623 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10625 /* Reset the timesync increment value. */
10626 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10627 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10633 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10634 struct timespec *timestamp, uint32_t flags)
10636 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10637 struct i40e_adapter *adapter =
10638 (struct i40e_adapter *)dev->data->dev_private;
10640 uint32_t sync_status;
10641 uint32_t index = flags & 0x03;
10642 uint64_t rx_tstamp_cycles;
10645 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10646 if ((sync_status & (1 << index)) == 0)
10649 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10650 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10651 *timestamp = rte_ns_to_timespec(ns);
10657 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10658 struct timespec *timestamp)
10660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10661 struct i40e_adapter *adapter =
10662 (struct i40e_adapter *)dev->data->dev_private;
10664 uint32_t sync_status;
10665 uint64_t tx_tstamp_cycles;
10668 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10669 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10672 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10673 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10674 *timestamp = rte_ns_to_timespec(ns);
10680 * i40e_parse_dcb_configure - parse dcb configure from user
10681 * @dev: the device being configured
10682 * @dcb_cfg: pointer of the result of parse
10683 * @*tc_map: bit map of enabled traffic classes
10685 * Returns 0 on success, negative value on failure
10688 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10689 struct i40e_dcbx_config *dcb_cfg,
10692 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10693 uint8_t i, tc_bw, bw_lf;
10695 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10697 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10698 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10699 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10703 /* assume each tc has the same bw */
10704 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10705 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10706 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10707 /* to ensure the sum of tcbw is equal to 100 */
10708 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10709 for (i = 0; i < bw_lf; i++)
10710 dcb_cfg->etscfg.tcbwtable[i]++;
10712 /* assume each tc has the same Transmission Selection Algorithm */
10713 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10714 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10716 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10717 dcb_cfg->etscfg.prioritytable[i] =
10718 dcb_rx_conf->dcb_tc[i];
10720 /* FW needs one App to configure HW */
10721 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10722 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10723 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10724 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10726 if (dcb_rx_conf->nb_tcs == 0)
10727 *tc_map = 1; /* tc0 only */
10729 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10731 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10732 dcb_cfg->pfc.willing = 0;
10733 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10734 dcb_cfg->pfc.pfcenable = *tc_map;
10740 static enum i40e_status_code
10741 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10742 struct i40e_aqc_vsi_properties_data *info,
10743 uint8_t enabled_tcmap)
10745 enum i40e_status_code ret;
10746 int i, total_tc = 0;
10747 uint16_t qpnum_per_tc, bsf, qp_idx;
10748 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10749 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10750 uint16_t used_queues;
10752 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10753 if (ret != I40E_SUCCESS)
10756 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10757 if (enabled_tcmap & (1 << i))
10762 vsi->enabled_tc = enabled_tcmap;
10764 /* different VSI has different queues assigned */
10765 if (vsi->type == I40E_VSI_MAIN)
10766 used_queues = dev_data->nb_rx_queues -
10767 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10768 else if (vsi->type == I40E_VSI_VMDQ2)
10769 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10771 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10772 return I40E_ERR_NO_AVAILABLE_VSI;
10775 qpnum_per_tc = used_queues / total_tc;
10776 /* Number of queues per enabled TC */
10777 if (qpnum_per_tc == 0) {
10778 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10779 return I40E_ERR_INVALID_QP_ID;
10781 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10782 I40E_MAX_Q_PER_TC);
10783 bsf = rte_bsf32(qpnum_per_tc);
10786 * Configure TC and queue mapping parameters, for enabled TC,
10787 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10788 * default queue will serve it.
10791 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10792 if (vsi->enabled_tc & (1 << i)) {
10793 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10794 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10795 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10796 qp_idx += qpnum_per_tc;
10798 info->tc_mapping[i] = 0;
10801 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10802 if (vsi->type == I40E_VSI_SRIOV) {
10803 info->mapping_flags |=
10804 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10805 for (i = 0; i < vsi->nb_qps; i++)
10806 info->queue_mapping[i] =
10807 rte_cpu_to_le_16(vsi->base_queue + i);
10809 info->mapping_flags |=
10810 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10811 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10813 info->valid_sections |=
10814 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10816 return I40E_SUCCESS;
10820 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10821 * @veb: VEB to be configured
10822 * @tc_map: enabled TC bitmap
10824 * Returns 0 on success, negative value on failure
10826 static enum i40e_status_code
10827 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10829 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10830 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10831 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10832 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10833 enum i40e_status_code ret = I40E_SUCCESS;
10837 /* Check if enabled_tc is same as existing or new TCs */
10838 if (veb->enabled_tc == tc_map)
10841 /* configure tc bandwidth */
10842 memset(&veb_bw, 0, sizeof(veb_bw));
10843 veb_bw.tc_valid_bits = tc_map;
10844 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10845 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10846 if (tc_map & BIT_ULL(i))
10847 veb_bw.tc_bw_share_credits[i] = 1;
10849 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10853 "AQ command Config switch_comp BW allocation per TC failed = %d",
10854 hw->aq.asq_last_status);
10858 memset(&ets_query, 0, sizeof(ets_query));
10859 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10861 if (ret != I40E_SUCCESS) {
10863 "Failed to get switch_comp ETS configuration %u",
10864 hw->aq.asq_last_status);
10867 memset(&bw_query, 0, sizeof(bw_query));
10868 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10870 if (ret != I40E_SUCCESS) {
10872 "Failed to get switch_comp bandwidth configuration %u",
10873 hw->aq.asq_last_status);
10877 /* store and print out BW info */
10878 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10879 veb->bw_info.bw_max = ets_query.tc_bw_max;
10880 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10881 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10882 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10883 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10884 I40E_16_BIT_WIDTH);
10885 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10886 veb->bw_info.bw_ets_share_credits[i] =
10887 bw_query.tc_bw_share_credits[i];
10888 veb->bw_info.bw_ets_credits[i] =
10889 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10890 /* 4 bits per TC, 4th bit is reserved */
10891 veb->bw_info.bw_ets_max[i] =
10892 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10893 RTE_LEN2MASK(3, uint8_t));
10894 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10895 veb->bw_info.bw_ets_share_credits[i]);
10896 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10897 veb->bw_info.bw_ets_credits[i]);
10898 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10899 veb->bw_info.bw_ets_max[i]);
10902 veb->enabled_tc = tc_map;
10909 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10910 * @vsi: VSI to be configured
10911 * @tc_map: enabled TC bitmap
10913 * Returns 0 on success, negative value on failure
10915 static enum i40e_status_code
10916 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10918 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10919 struct i40e_vsi_context ctxt;
10920 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10921 enum i40e_status_code ret = I40E_SUCCESS;
10924 /* Check if enabled_tc is same as existing or new TCs */
10925 if (vsi->enabled_tc == tc_map)
10928 /* configure tc bandwidth */
10929 memset(&bw_data, 0, sizeof(bw_data));
10930 bw_data.tc_valid_bits = tc_map;
10931 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10932 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10933 if (tc_map & BIT_ULL(i))
10934 bw_data.tc_bw_credits[i] = 1;
10936 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10939 "AQ command Config VSI BW allocation per TC failed = %d",
10940 hw->aq.asq_last_status);
10943 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10944 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10946 /* Update Queue Pairs Mapping for currently enabled UPs */
10947 ctxt.seid = vsi->seid;
10948 ctxt.pf_num = hw->pf_id;
10950 ctxt.uplink_seid = vsi->uplink_seid;
10951 ctxt.info = vsi->info;
10953 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10957 /* Update the VSI after updating the VSI queue-mapping information */
10958 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10960 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10961 hw->aq.asq_last_status);
10964 /* update the local VSI info with updated queue map */
10965 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10966 sizeof(vsi->info.tc_mapping));
10967 rte_memcpy(&vsi->info.queue_mapping,
10968 &ctxt.info.queue_mapping,
10969 sizeof(vsi->info.queue_mapping));
10970 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10971 vsi->info.valid_sections = 0;
10973 /* query and update current VSI BW information */
10974 ret = i40e_vsi_get_bw_config(vsi);
10977 "Failed updating vsi bw info, err %s aq_err %s",
10978 i40e_stat_str(hw, ret),
10979 i40e_aq_str(hw, hw->aq.asq_last_status));
10983 vsi->enabled_tc = tc_map;
10990 * i40e_dcb_hw_configure - program the dcb setting to hw
10991 * @pf: pf the configuration is taken on
10992 * @new_cfg: new configuration
10993 * @tc_map: enabled TC bitmap
10995 * Returns 0 on success, negative value on failure
10997 static enum i40e_status_code
10998 i40e_dcb_hw_configure(struct i40e_pf *pf,
10999 struct i40e_dcbx_config *new_cfg,
11002 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11003 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11004 struct i40e_vsi *main_vsi = pf->main_vsi;
11005 struct i40e_vsi_list *vsi_list;
11006 enum i40e_status_code ret;
11010 /* Use the FW API if FW > v4.4*/
11011 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11012 (hw->aq.fw_maj_ver >= 5))) {
11014 "FW < v4.4, can not use FW LLDP API to configure DCB");
11015 return I40E_ERR_FIRMWARE_API_VERSION;
11018 /* Check if need reconfiguration */
11019 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11020 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11021 return I40E_SUCCESS;
11024 /* Copy the new config to the current config */
11025 *old_cfg = *new_cfg;
11026 old_cfg->etsrec = old_cfg->etscfg;
11027 ret = i40e_set_dcb_config(hw);
11029 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11030 i40e_stat_str(hw, ret),
11031 i40e_aq_str(hw, hw->aq.asq_last_status));
11034 /* set receive Arbiter to RR mode and ETS scheme by default */
11035 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11036 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11037 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11038 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11039 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11040 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11041 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11042 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11043 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11044 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11045 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11046 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11047 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11049 /* get local mib to check whether it is configured correctly */
11051 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11052 /* Get Local DCB Config */
11053 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11054 &hw->local_dcbx_config);
11056 /* if Veb is created, need to update TC of it at first */
11057 if (main_vsi->veb) {
11058 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11060 PMD_INIT_LOG(WARNING,
11061 "Failed configuring TC for VEB seid=%d",
11062 main_vsi->veb->seid);
11064 /* Update each VSI */
11065 i40e_vsi_config_tc(main_vsi, tc_map);
11066 if (main_vsi->veb) {
11067 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11068 /* Beside main VSI and VMDQ VSIs, only enable default
11069 * TC for other VSIs
11071 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11072 ret = i40e_vsi_config_tc(vsi_list->vsi,
11075 ret = i40e_vsi_config_tc(vsi_list->vsi,
11076 I40E_DEFAULT_TCMAP);
11078 PMD_INIT_LOG(WARNING,
11079 "Failed configuring TC for VSI seid=%d",
11080 vsi_list->vsi->seid);
11084 return I40E_SUCCESS;
11088 * i40e_dcb_init_configure - initial dcb config
11089 * @dev: device being configured
11090 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11092 * Returns 0 on success, negative value on failure
11095 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11097 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11098 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11102 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11106 /* DCB initialization:
11107 * Update DCB configuration from the Firmware and configure
11108 * LLDP MIB change event.
11110 if (sw_dcb == TRUE) {
11111 ret = i40e_init_dcb(hw);
11112 /* If lldp agent is stopped, the return value from
11113 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11114 * adminq status. Otherwise, it should return success.
11116 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11117 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11118 memset(&hw->local_dcbx_config, 0,
11119 sizeof(struct i40e_dcbx_config));
11120 /* set dcb default configuration */
11121 hw->local_dcbx_config.etscfg.willing = 0;
11122 hw->local_dcbx_config.etscfg.maxtcs = 0;
11123 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11124 hw->local_dcbx_config.etscfg.tsatable[0] =
11126 /* all UPs mapping to TC0 */
11127 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11128 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11129 hw->local_dcbx_config.etsrec =
11130 hw->local_dcbx_config.etscfg;
11131 hw->local_dcbx_config.pfc.willing = 0;
11132 hw->local_dcbx_config.pfc.pfccap =
11133 I40E_MAX_TRAFFIC_CLASS;
11134 /* FW needs one App to configure HW */
11135 hw->local_dcbx_config.numapps = 1;
11136 hw->local_dcbx_config.app[0].selector =
11137 I40E_APP_SEL_ETHTYPE;
11138 hw->local_dcbx_config.app[0].priority = 3;
11139 hw->local_dcbx_config.app[0].protocolid =
11140 I40E_APP_PROTOID_FCOE;
11141 ret = i40e_set_dcb_config(hw);
11144 "default dcb config fails. err = %d, aq_err = %d.",
11145 ret, hw->aq.asq_last_status);
11150 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11151 ret, hw->aq.asq_last_status);
11155 ret = i40e_aq_start_lldp(hw, NULL);
11156 if (ret != I40E_SUCCESS)
11157 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11159 ret = i40e_init_dcb(hw);
11161 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11163 "HW doesn't support DCBX offload.");
11168 "DCBX configuration failed, err = %d, aq_err = %d.",
11169 ret, hw->aq.asq_last_status);
11177 * i40e_dcb_setup - setup dcb related config
11178 * @dev: device being configured
11180 * Returns 0 on success, negative value on failure
11183 i40e_dcb_setup(struct rte_eth_dev *dev)
11185 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11186 struct i40e_dcbx_config dcb_cfg;
11187 uint8_t tc_map = 0;
11190 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11191 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11195 if (pf->vf_num != 0)
11196 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11198 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11200 PMD_INIT_LOG(ERR, "invalid dcb config");
11203 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11205 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11213 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11214 struct rte_eth_dcb_info *dcb_info)
11216 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11217 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11218 struct i40e_vsi *vsi = pf->main_vsi;
11219 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11220 uint16_t bsf, tc_mapping;
11223 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11224 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11226 dcb_info->nb_tcs = 1;
11227 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11228 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11229 for (i = 0; i < dcb_info->nb_tcs; i++)
11230 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11232 /* get queue mapping if vmdq is disabled */
11233 if (!pf->nb_cfg_vmdq_vsi) {
11234 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11235 if (!(vsi->enabled_tc & (1 << i)))
11237 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11238 dcb_info->tc_queue.tc_rxq[j][i].base =
11239 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11240 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11241 dcb_info->tc_queue.tc_txq[j][i].base =
11242 dcb_info->tc_queue.tc_rxq[j][i].base;
11243 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11244 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11245 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11246 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11247 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11252 /* get queue mapping if vmdq is enabled */
11254 vsi = pf->vmdq[j].vsi;
11255 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11256 if (!(vsi->enabled_tc & (1 << i)))
11258 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11259 dcb_info->tc_queue.tc_rxq[j][i].base =
11260 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11261 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11262 dcb_info->tc_queue.tc_txq[j][i].base =
11263 dcb_info->tc_queue.tc_rxq[j][i].base;
11264 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11265 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11266 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11267 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11268 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11271 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11276 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11278 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11279 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11280 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11281 uint16_t msix_intr;
11283 msix_intr = intr_handle->intr_vec[queue_id];
11284 if (msix_intr == I40E_MISC_VEC_ID)
11285 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11286 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11287 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11288 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11291 I40E_PFINT_DYN_CTLN(msix_intr -
11292 I40E_RX_VEC_START),
11293 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11294 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11295 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11297 I40E_WRITE_FLUSH(hw);
11298 rte_intr_enable(&pci_dev->intr_handle);
11304 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11306 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11307 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11308 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11309 uint16_t msix_intr;
11311 msix_intr = intr_handle->intr_vec[queue_id];
11312 if (msix_intr == I40E_MISC_VEC_ID)
11313 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11314 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11317 I40E_PFINT_DYN_CTLN(msix_intr -
11318 I40E_RX_VEC_START),
11319 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11320 I40E_WRITE_FLUSH(hw);
11325 static int i40e_get_regs(struct rte_eth_dev *dev,
11326 struct rte_dev_reg_info *regs)
11328 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11329 uint32_t *ptr_data = regs->data;
11330 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11331 const struct i40e_reg_info *reg_info;
11333 if (ptr_data == NULL) {
11334 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11335 regs->width = sizeof(uint32_t);
11339 /* The first few registers have to be read using AQ operations */
11341 while (i40e_regs_adminq[reg_idx].name) {
11342 reg_info = &i40e_regs_adminq[reg_idx++];
11343 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11345 arr_idx2 <= reg_info->count2;
11347 reg_offset = arr_idx * reg_info->stride1 +
11348 arr_idx2 * reg_info->stride2;
11349 reg_offset += reg_info->base_addr;
11350 ptr_data[reg_offset >> 2] =
11351 i40e_read_rx_ctl(hw, reg_offset);
11355 /* The remaining registers can be read using primitives */
11357 while (i40e_regs_others[reg_idx].name) {
11358 reg_info = &i40e_regs_others[reg_idx++];
11359 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11361 arr_idx2 <= reg_info->count2;
11363 reg_offset = arr_idx * reg_info->stride1 +
11364 arr_idx2 * reg_info->stride2;
11365 reg_offset += reg_info->base_addr;
11366 ptr_data[reg_offset >> 2] =
11367 I40E_READ_REG(hw, reg_offset);
11374 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11376 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11378 /* Convert word count to byte count */
11379 return hw->nvm.sr_size << 1;
11382 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11383 struct rte_dev_eeprom_info *eeprom)
11385 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11386 uint16_t *data = eeprom->data;
11387 uint16_t offset, length, cnt_words;
11390 offset = eeprom->offset >> 1;
11391 length = eeprom->length >> 1;
11392 cnt_words = length;
11394 if (offset > hw->nvm.sr_size ||
11395 offset + length > hw->nvm.sr_size) {
11396 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11400 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11402 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11403 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11404 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11411 static int i40e_get_module_info(struct rte_eth_dev *dev,
11412 struct rte_eth_dev_module_info *modinfo)
11414 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11415 uint32_t sff8472_comp = 0;
11416 uint32_t sff8472_swap = 0;
11417 uint32_t sff8636_rev = 0;
11418 i40e_status status;
11421 /* Check if firmware supports reading module EEPROM. */
11422 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11424 "Module EEPROM memory read not supported. "
11425 "Please update the NVM image.\n");
11429 status = i40e_update_link_info(hw);
11433 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11435 "Cannot read module EEPROM memory. "
11436 "No module connected.\n");
11440 type = hw->phy.link_info.module_type[0];
11443 case I40E_MODULE_TYPE_SFP:
11444 status = i40e_aq_get_phy_register(hw,
11445 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11446 I40E_I2C_EEPROM_DEV_ADDR,
11447 I40E_MODULE_SFF_8472_COMP,
11448 &sff8472_comp, NULL);
11452 status = i40e_aq_get_phy_register(hw,
11453 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11454 I40E_I2C_EEPROM_DEV_ADDR,
11455 I40E_MODULE_SFF_8472_SWAP,
11456 &sff8472_swap, NULL);
11460 /* Check if the module requires address swap to access
11461 * the other EEPROM memory page.
11463 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11464 PMD_DRV_LOG(WARNING,
11465 "Module address swap to access "
11466 "page 0xA2 is not supported.\n");
11467 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11468 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11469 } else if (sff8472_comp == 0x00) {
11470 /* Module is not SFF-8472 compliant */
11471 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11472 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11474 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11475 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11478 case I40E_MODULE_TYPE_QSFP_PLUS:
11479 /* Read from memory page 0. */
11480 status = i40e_aq_get_phy_register(hw,
11481 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11483 I40E_MODULE_REVISION_ADDR,
11484 &sff8636_rev, NULL);
11487 /* Determine revision compliance byte */
11488 if (sff8636_rev > 0x02) {
11489 /* Module is SFF-8636 compliant */
11490 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11491 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11493 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11494 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11497 case I40E_MODULE_TYPE_QSFP28:
11498 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11499 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11502 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11508 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11509 struct rte_dev_eeprom_info *info)
11511 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11512 bool is_sfp = false;
11513 i40e_status status;
11514 uint8_t *data = info->data;
11515 uint32_t value = 0;
11518 if (!info || !info->length || !data)
11521 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11524 for (i = 0; i < info->length; i++) {
11525 u32 offset = i + info->offset;
11526 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11528 /* Check if we need to access the other memory page */
11530 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11531 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11532 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11535 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11536 /* Compute memory page number and offset. */
11537 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11541 status = i40e_aq_get_phy_register(hw,
11542 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11543 addr, offset, &value, NULL);
11546 data[i] = (uint8_t)value;
11551 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11552 struct ether_addr *mac_addr)
11554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11555 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11556 struct i40e_vsi *vsi = pf->main_vsi;
11557 struct i40e_mac_filter_info mac_filter;
11558 struct i40e_mac_filter *f;
11561 if (!is_valid_assigned_ether_addr(mac_addr)) {
11562 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11566 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11567 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11572 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11576 mac_filter = f->mac_info;
11577 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11578 if (ret != I40E_SUCCESS) {
11579 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11582 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11583 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11584 if (ret != I40E_SUCCESS) {
11585 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11588 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11590 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11591 mac_addr->addr_bytes, NULL);
11592 if (ret != I40E_SUCCESS) {
11593 PMD_DRV_LOG(ERR, "Failed to change mac");
11601 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11603 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11604 struct rte_eth_dev_data *dev_data = pf->dev_data;
11605 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11608 /* check if mtu is within the allowed range */
11609 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11612 /* mtu setting is forbidden if port is start */
11613 if (dev_data->dev_started) {
11614 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11615 dev_data->port_id);
11619 if (frame_size > ETHER_MAX_LEN)
11620 dev_data->dev_conf.rxmode.offloads |=
11621 DEV_RX_OFFLOAD_JUMBO_FRAME;
11623 dev_data->dev_conf.rxmode.offloads &=
11624 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11626 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11631 /* Restore ethertype filter */
11633 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11635 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11636 struct i40e_ethertype_filter_list
11637 *ethertype_list = &pf->ethertype.ethertype_list;
11638 struct i40e_ethertype_filter *f;
11639 struct i40e_control_filter_stats stats;
11642 TAILQ_FOREACH(f, ethertype_list, rules) {
11644 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11645 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11646 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11647 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11648 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11650 memset(&stats, 0, sizeof(stats));
11651 i40e_aq_add_rem_control_packet_filter(hw,
11652 f->input.mac_addr.addr_bytes,
11653 f->input.ether_type,
11654 flags, pf->main_vsi->seid,
11655 f->queue, 1, &stats, NULL);
11657 PMD_DRV_LOG(INFO, "Ethertype filter:"
11658 " mac_etype_used = %u, etype_used = %u,"
11659 " mac_etype_free = %u, etype_free = %u",
11660 stats.mac_etype_used, stats.etype_used,
11661 stats.mac_etype_free, stats.etype_free);
11664 /* Restore tunnel filter */
11666 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11668 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11669 struct i40e_vsi *vsi;
11670 struct i40e_pf_vf *vf;
11671 struct i40e_tunnel_filter_list
11672 *tunnel_list = &pf->tunnel.tunnel_list;
11673 struct i40e_tunnel_filter *f;
11674 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11675 bool big_buffer = 0;
11677 TAILQ_FOREACH(f, tunnel_list, rules) {
11679 vsi = pf->main_vsi;
11681 vf = &pf->vfs[f->vf_id];
11684 memset(&cld_filter, 0, sizeof(cld_filter));
11685 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11686 (struct ether_addr *)&cld_filter.element.outer_mac);
11687 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11688 (struct ether_addr *)&cld_filter.element.inner_mac);
11689 cld_filter.element.inner_vlan = f->input.inner_vlan;
11690 cld_filter.element.flags = f->input.flags;
11691 cld_filter.element.tenant_id = f->input.tenant_id;
11692 cld_filter.element.queue_number = f->queue;
11693 rte_memcpy(cld_filter.general_fields,
11694 f->input.general_fields,
11695 sizeof(f->input.general_fields));
11697 if (((f->input.flags &
11698 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11699 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11701 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11702 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11704 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11705 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11709 i40e_aq_add_cloud_filters_big_buffer(hw,
11710 vsi->seid, &cld_filter, 1);
11712 i40e_aq_add_cloud_filters(hw, vsi->seid,
11713 &cld_filter.element, 1);
11717 /* Restore rss filter */
11719 i40e_rss_filter_restore(struct i40e_pf *pf)
11721 struct i40e_rte_flow_rss_conf *conf =
11723 if (conf->conf.queue_num)
11724 i40e_config_rss_filter(pf, conf, TRUE);
11728 i40e_filter_restore(struct i40e_pf *pf)
11730 i40e_ethertype_filter_restore(pf);
11731 i40e_tunnel_filter_restore(pf);
11732 i40e_fdir_filter_restore(pf);
11733 i40e_rss_filter_restore(pf);
11737 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11739 if (strcmp(dev->device->driver->name, drv->driver.name))
11746 is_i40e_supported(struct rte_eth_dev *dev)
11748 return is_device_supported(dev, &rte_i40e_pmd);
11751 struct i40e_customized_pctype*
11752 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11756 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11757 if (pf->customized_pctype[i].index == index)
11758 return &pf->customized_pctype[i];
11764 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11765 uint32_t pkg_size, uint32_t proto_num,
11766 struct rte_pmd_i40e_proto_info *proto,
11767 enum rte_pmd_i40e_package_op op)
11769 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11770 uint32_t pctype_num;
11771 struct rte_pmd_i40e_ptype_info *pctype;
11772 uint32_t buff_size;
11773 struct i40e_customized_pctype *new_pctype = NULL;
11775 uint8_t pctype_value;
11780 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11781 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11782 PMD_DRV_LOG(ERR, "Unsupported operation.");
11786 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11787 (uint8_t *)&pctype_num, sizeof(pctype_num),
11788 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11790 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11794 PMD_DRV_LOG(INFO, "No new pctype added");
11798 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11799 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11801 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11804 /* get information about new pctype list */
11805 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11806 (uint8_t *)pctype, buff_size,
11807 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11809 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11814 /* Update customized pctype. */
11815 for (i = 0; i < pctype_num; i++) {
11816 pctype_value = pctype[i].ptype_id;
11817 memset(name, 0, sizeof(name));
11818 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11819 proto_id = pctype[i].protocols[j];
11820 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11822 for (n = 0; n < proto_num; n++) {
11823 if (proto[n].proto_id != proto_id)
11825 strcat(name, proto[n].name);
11830 name[strlen(name) - 1] = '\0';
11831 if (!strcmp(name, "GTPC"))
11833 i40e_find_customized_pctype(pf,
11834 I40E_CUSTOMIZED_GTPC);
11835 else if (!strcmp(name, "GTPU_IPV4"))
11837 i40e_find_customized_pctype(pf,
11838 I40E_CUSTOMIZED_GTPU_IPV4);
11839 else if (!strcmp(name, "GTPU_IPV6"))
11841 i40e_find_customized_pctype(pf,
11842 I40E_CUSTOMIZED_GTPU_IPV6);
11843 else if (!strcmp(name, "GTPU"))
11845 i40e_find_customized_pctype(pf,
11846 I40E_CUSTOMIZED_GTPU);
11848 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11849 new_pctype->pctype = pctype_value;
11850 new_pctype->valid = true;
11852 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11853 new_pctype->valid = false;
11863 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11864 uint32_t pkg_size, uint32_t proto_num,
11865 struct rte_pmd_i40e_proto_info *proto,
11866 enum rte_pmd_i40e_package_op op)
11868 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11869 uint16_t port_id = dev->data->port_id;
11870 uint32_t ptype_num;
11871 struct rte_pmd_i40e_ptype_info *ptype;
11872 uint32_t buff_size;
11874 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11879 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11880 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11881 PMD_DRV_LOG(ERR, "Unsupported operation.");
11885 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11886 rte_pmd_i40e_ptype_mapping_reset(port_id);
11890 /* get information about new ptype num */
11891 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11892 (uint8_t *)&ptype_num, sizeof(ptype_num),
11893 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11895 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11899 PMD_DRV_LOG(INFO, "No new ptype added");
11903 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11904 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11906 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11910 /* get information about new ptype list */
11911 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11912 (uint8_t *)ptype, buff_size,
11913 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11915 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11920 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11921 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11922 if (!ptype_mapping) {
11923 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11928 /* Update ptype mapping table. */
11929 for (i = 0; i < ptype_num; i++) {
11930 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11931 ptype_mapping[i].sw_ptype = 0;
11933 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11934 proto_id = ptype[i].protocols[j];
11935 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11937 for (n = 0; n < proto_num; n++) {
11938 if (proto[n].proto_id != proto_id)
11940 memset(name, 0, sizeof(name));
11941 strcpy(name, proto[n].name);
11942 if (!strncasecmp(name, "PPPOE", 5))
11943 ptype_mapping[i].sw_ptype |=
11944 RTE_PTYPE_L2_ETHER_PPPOE;
11945 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11947 ptype_mapping[i].sw_ptype |=
11948 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11949 ptype_mapping[i].sw_ptype |=
11951 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11953 ptype_mapping[i].sw_ptype |=
11954 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11955 ptype_mapping[i].sw_ptype |=
11956 RTE_PTYPE_INNER_L4_FRAG;
11957 } else if (!strncasecmp(name, "OIPV4", 5)) {
11958 ptype_mapping[i].sw_ptype |=
11959 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11961 } else if (!strncasecmp(name, "IPV4", 4) &&
11963 ptype_mapping[i].sw_ptype |=
11964 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11965 else if (!strncasecmp(name, "IPV4", 4) &&
11967 ptype_mapping[i].sw_ptype |=
11968 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11969 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11971 ptype_mapping[i].sw_ptype |=
11972 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11973 ptype_mapping[i].sw_ptype |=
11975 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11977 ptype_mapping[i].sw_ptype |=
11978 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11979 ptype_mapping[i].sw_ptype |=
11980 RTE_PTYPE_INNER_L4_FRAG;
11981 } else if (!strncasecmp(name, "OIPV6", 5)) {
11982 ptype_mapping[i].sw_ptype |=
11983 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11985 } else if (!strncasecmp(name, "IPV6", 4) &&
11987 ptype_mapping[i].sw_ptype |=
11988 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11989 else if (!strncasecmp(name, "IPV6", 4) &&
11991 ptype_mapping[i].sw_ptype |=
11992 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11993 else if (!strncasecmp(name, "UDP", 3) &&
11995 ptype_mapping[i].sw_ptype |=
11997 else if (!strncasecmp(name, "UDP", 3) &&
11999 ptype_mapping[i].sw_ptype |=
12000 RTE_PTYPE_INNER_L4_UDP;
12001 else if (!strncasecmp(name, "TCP", 3) &&
12003 ptype_mapping[i].sw_ptype |=
12005 else if (!strncasecmp(name, "TCP", 3) &&
12007 ptype_mapping[i].sw_ptype |=
12008 RTE_PTYPE_INNER_L4_TCP;
12009 else if (!strncasecmp(name, "SCTP", 4) &&
12011 ptype_mapping[i].sw_ptype |=
12013 else if (!strncasecmp(name, "SCTP", 4) &&
12015 ptype_mapping[i].sw_ptype |=
12016 RTE_PTYPE_INNER_L4_SCTP;
12017 else if ((!strncasecmp(name, "ICMP", 4) ||
12018 !strncasecmp(name, "ICMPV6", 6)) &&
12020 ptype_mapping[i].sw_ptype |=
12022 else if ((!strncasecmp(name, "ICMP", 4) ||
12023 !strncasecmp(name, "ICMPV6", 6)) &&
12025 ptype_mapping[i].sw_ptype |=
12026 RTE_PTYPE_INNER_L4_ICMP;
12027 else if (!strncasecmp(name, "GTPC", 4)) {
12028 ptype_mapping[i].sw_ptype |=
12029 RTE_PTYPE_TUNNEL_GTPC;
12031 } else if (!strncasecmp(name, "GTPU", 4)) {
12032 ptype_mapping[i].sw_ptype |=
12033 RTE_PTYPE_TUNNEL_GTPU;
12035 } else if (!strncasecmp(name, "GRENAT", 6)) {
12036 ptype_mapping[i].sw_ptype |=
12037 RTE_PTYPE_TUNNEL_GRENAT;
12039 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
12040 ptype_mapping[i].sw_ptype |=
12041 RTE_PTYPE_TUNNEL_L2TP;
12050 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12053 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12055 rte_free(ptype_mapping);
12061 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12062 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12064 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12065 uint32_t proto_num;
12066 struct rte_pmd_i40e_proto_info *proto;
12067 uint32_t buff_size;
12071 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12072 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12073 PMD_DRV_LOG(ERR, "Unsupported operation.");
12077 /* get information about protocol number */
12078 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12079 (uint8_t *)&proto_num, sizeof(proto_num),
12080 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12082 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12086 PMD_DRV_LOG(INFO, "No new protocol added");
12090 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12091 proto = rte_zmalloc("new_proto", buff_size, 0);
12093 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12097 /* get information about protocol list */
12098 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12099 (uint8_t *)proto, buff_size,
12100 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12102 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12107 /* Check if GTP is supported. */
12108 for (i = 0; i < proto_num; i++) {
12109 if (!strncmp(proto[i].name, "GTP", 3)) {
12110 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12111 pf->gtp_support = true;
12113 pf->gtp_support = false;
12118 /* Update customized pctype info */
12119 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12120 proto_num, proto, op);
12122 PMD_DRV_LOG(INFO, "No pctype is updated.");
12124 /* Update customized ptype info */
12125 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12126 proto_num, proto, op);
12128 PMD_DRV_LOG(INFO, "No ptype is updated.");
12133 /* Create a QinQ cloud filter
12135 * The Fortville NIC has limited resources for tunnel filters,
12136 * so we can only reuse existing filters.
12138 * In step 1 we define which Field Vector fields can be used for
12140 * As we do not have the inner tag defined as a field,
12141 * we have to define it first, by reusing one of L1 entries.
12143 * In step 2 we are replacing one of existing filter types with
12144 * a new one for QinQ.
12145 * As we reusing L1 and replacing L2, some of the default filter
12146 * types will disappear,which depends on L1 and L2 entries we reuse.
12148 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12150 * 1. Create L1 filter of outer vlan (12b) which will be in use
12151 * later when we define the cloud filter.
12152 * a. Valid_flags.replace_cloud = 0
12153 * b. Old_filter = 10 (Stag_Inner_Vlan)
12154 * c. New_filter = 0x10
12155 * d. TR bit = 0xff (optional, not used here)
12156 * e. Buffer – 2 entries:
12157 * i. Byte 0 = 8 (outer vlan FV index).
12159 * Byte 2-3 = 0x0fff
12160 * ii. Byte 0 = 37 (inner vlan FV index).
12162 * Byte 2-3 = 0x0fff
12165 * 2. Create cloud filter using two L1 filters entries: stag and
12166 * new filter(outer vlan+ inner vlan)
12167 * a. Valid_flags.replace_cloud = 1
12168 * b. Old_filter = 1 (instead of outer IP)
12169 * c. New_filter = 0x10
12170 * d. Buffer – 2 entries:
12171 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12172 * Byte 1-3 = 0 (rsv)
12173 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12174 * Byte 9-11 = 0 (rsv)
12177 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12179 int ret = -ENOTSUP;
12180 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12181 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12182 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12184 if (pf->support_multi_driver) {
12185 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12190 memset(&filter_replace, 0,
12191 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12192 memset(&filter_replace_buf, 0,
12193 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12195 /* create L1 filter */
12196 filter_replace.old_filter_type =
12197 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12198 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12199 filter_replace.tr_bit = 0;
12201 /* Prepare the buffer, 2 entries */
12202 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12203 filter_replace_buf.data[0] |=
12204 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12205 /* Field Vector 12b mask */
12206 filter_replace_buf.data[2] = 0xff;
12207 filter_replace_buf.data[3] = 0x0f;
12208 filter_replace_buf.data[4] =
12209 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12210 filter_replace_buf.data[4] |=
12211 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12212 /* Field Vector 12b mask */
12213 filter_replace_buf.data[6] = 0xff;
12214 filter_replace_buf.data[7] = 0x0f;
12215 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12216 &filter_replace_buf);
12217 if (ret != I40E_SUCCESS)
12219 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12220 "cloud l1 type is changed from 0x%x to 0x%x",
12221 filter_replace.old_filter_type,
12222 filter_replace.new_filter_type);
12224 /* Apply the second L2 cloud filter */
12225 memset(&filter_replace, 0,
12226 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12227 memset(&filter_replace_buf, 0,
12228 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12230 /* create L2 filter, input for L2 filter will be L1 filter */
12231 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12232 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12233 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12235 /* Prepare the buffer, 2 entries */
12236 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12237 filter_replace_buf.data[0] |=
12238 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12239 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12240 filter_replace_buf.data[4] |=
12241 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12242 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12243 &filter_replace_buf);
12245 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12246 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12247 "cloud filter type is changed from 0x%x to 0x%x",
12248 filter_replace.old_filter_type,
12249 filter_replace.new_filter_type);
12255 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12256 const struct rte_flow_action_rss *in)
12258 if (in->key_len > RTE_DIM(out->key) ||
12259 in->queue_num > RTE_DIM(out->queue))
12261 out->conf = (struct rte_flow_action_rss){
12263 .level = in->level,
12264 .types = in->types,
12265 .key_len = in->key_len,
12266 .queue_num = in->queue_num,
12267 .key = memcpy(out->key, in->key, in->key_len),
12268 .queue = memcpy(out->queue, in->queue,
12269 sizeof(*in->queue) * in->queue_num),
12275 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12276 const struct rte_flow_action_rss *with)
12278 return (comp->func == with->func &&
12279 comp->level == with->level &&
12280 comp->types == with->types &&
12281 comp->key_len == with->key_len &&
12282 comp->queue_num == with->queue_num &&
12283 !memcmp(comp->key, with->key, with->key_len) &&
12284 !memcmp(comp->queue, with->queue,
12285 sizeof(*with->queue) * with->queue_num));
12289 i40e_config_rss_filter(struct i40e_pf *pf,
12290 struct i40e_rte_flow_rss_conf *conf, bool add)
12292 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12293 uint32_t i, lut = 0;
12295 struct rte_eth_rss_conf rss_conf = {
12296 .rss_key = conf->conf.key_len ?
12297 (void *)(uintptr_t)conf->conf.key : NULL,
12298 .rss_key_len = conf->conf.key_len,
12299 .rss_hf = conf->conf.types,
12301 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12304 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12305 i40e_pf_disable_rss(pf);
12306 memset(rss_info, 0,
12307 sizeof(struct i40e_rte_flow_rss_conf));
12313 if (rss_info->conf.queue_num)
12316 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12317 * It's necessary to calculate the actual PF queues that are configured.
12319 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12320 num = i40e_pf_calc_configured_queues_num(pf);
12322 num = pf->dev_data->nb_rx_queues;
12324 num = RTE_MIN(num, conf->conf.queue_num);
12325 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12329 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12333 /* Fill in redirection table */
12334 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12337 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12338 hw->func_caps.rss_table_entry_width) - 1));
12340 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12343 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12344 i40e_pf_disable_rss(pf);
12347 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12348 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12349 /* Random default keys */
12350 static uint32_t rss_key_default[] = {0x6b793944,
12351 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12352 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12353 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12355 rss_conf.rss_key = (uint8_t *)rss_key_default;
12356 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12360 i40e_hw_rss_hash_set(pf, &rss_conf);
12362 if (i40e_rss_conf_init(rss_info, &conf->conf))
12368 RTE_INIT(i40e_init_log);
12370 i40e_init_log(void)
12372 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12373 if (i40e_logtype_init >= 0)
12374 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12375 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12376 if (i40e_logtype_driver >= 0)
12377 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12380 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12381 QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12382 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");