1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct rte_ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static void i40e_dev_alarm_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct rte_ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
410 int i40e_logtype_tx_free;
413 static const char *const valid_keys[] = {
414 ETH_I40E_FLOATING_VEB_ARG,
415 ETH_I40E_FLOATING_VEB_LIST_ARG,
416 ETH_I40E_SUPPORT_MULTI_DRIVER,
417 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
418 ETH_I40E_USE_LATEST_VEC,
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
446 { .vendor_id = 0, /* sentinel */ },
449 static const struct eth_dev_ops i40e_eth_dev_ops = {
450 .dev_configure = i40e_dev_configure,
451 .dev_start = i40e_dev_start,
452 .dev_stop = i40e_dev_stop,
453 .dev_close = i40e_dev_close,
454 .dev_reset = i40e_dev_reset,
455 .promiscuous_enable = i40e_dev_promiscuous_enable,
456 .promiscuous_disable = i40e_dev_promiscuous_disable,
457 .allmulticast_enable = i40e_dev_allmulticast_enable,
458 .allmulticast_disable = i40e_dev_allmulticast_disable,
459 .dev_set_link_up = i40e_dev_set_link_up,
460 .dev_set_link_down = i40e_dev_set_link_down,
461 .link_update = i40e_dev_link_update,
462 .stats_get = i40e_dev_stats_get,
463 .xstats_get = i40e_dev_xstats_get,
464 .xstats_get_names = i40e_dev_xstats_get_names,
465 .stats_reset = i40e_dev_stats_reset,
466 .xstats_reset = i40e_dev_stats_reset,
467 .fw_version_get = i40e_fw_version_get,
468 .dev_infos_get = i40e_dev_info_get,
469 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
470 .vlan_filter_set = i40e_vlan_filter_set,
471 .vlan_tpid_set = i40e_vlan_tpid_set,
472 .vlan_offload_set = i40e_vlan_offload_set,
473 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
474 .vlan_pvid_set = i40e_vlan_pvid_set,
475 .rx_queue_start = i40e_dev_rx_queue_start,
476 .rx_queue_stop = i40e_dev_rx_queue_stop,
477 .tx_queue_start = i40e_dev_tx_queue_start,
478 .tx_queue_stop = i40e_dev_tx_queue_stop,
479 .rx_queue_setup = i40e_dev_rx_queue_setup,
480 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
481 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
482 .rx_queue_release = i40e_dev_rx_queue_release,
483 .rx_queue_count = i40e_dev_rx_queue_count,
484 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
485 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
486 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
487 .tx_queue_setup = i40e_dev_tx_queue_setup,
488 .tx_queue_release = i40e_dev_tx_queue_release,
489 .dev_led_on = i40e_dev_led_on,
490 .dev_led_off = i40e_dev_led_off,
491 .flow_ctrl_get = i40e_flow_ctrl_get,
492 .flow_ctrl_set = i40e_flow_ctrl_set,
493 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
494 .mac_addr_add = i40e_macaddr_add,
495 .mac_addr_remove = i40e_macaddr_remove,
496 .reta_update = i40e_dev_rss_reta_update,
497 .reta_query = i40e_dev_rss_reta_query,
498 .rss_hash_update = i40e_dev_rss_hash_update,
499 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
500 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
501 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
502 .filter_ctrl = i40e_dev_filter_ctrl,
503 .rxq_info_get = i40e_rxq_info_get,
504 .txq_info_get = i40e_txq_info_get,
505 .rx_burst_mode_get = i40e_rx_burst_mode_get,
506 .tx_burst_mode_get = i40e_tx_burst_mode_get,
507 .mirror_rule_set = i40e_mirror_rule_set,
508 .mirror_rule_reset = i40e_mirror_rule_reset,
509 .timesync_enable = i40e_timesync_enable,
510 .timesync_disable = i40e_timesync_disable,
511 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
512 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
513 .get_dcb_info = i40e_dev_get_dcb_info,
514 .timesync_adjust_time = i40e_timesync_adjust_time,
515 .timesync_read_time = i40e_timesync_read_time,
516 .timesync_write_time = i40e_timesync_write_time,
517 .get_reg = i40e_get_regs,
518 .get_eeprom_length = i40e_get_eeprom_length,
519 .get_eeprom = i40e_get_eeprom,
520 .get_module_info = i40e_get_module_info,
521 .get_module_eeprom = i40e_get_module_eeprom,
522 .mac_addr_set = i40e_set_default_mac_addr,
523 .mtu_set = i40e_dev_mtu_set,
524 .tm_ops_get = i40e_tm_ops_get,
527 /* store statistics names and its offset in stats structure */
528 struct rte_i40e_xstats_name_off {
529 char name[RTE_ETH_XSTATS_NAME_SIZE];
533 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
534 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
535 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
536 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
537 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
538 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
539 rx_unknown_protocol)},
540 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
541 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
542 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
543 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
546 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
547 sizeof(rte_i40e_stats_strings[0]))
549 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
550 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
551 tx_dropped_link_down)},
552 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
553 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
555 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
556 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
558 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
560 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
562 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
563 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
564 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
565 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
566 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
567 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
581 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
584 mac_short_packet_dropped)},
585 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
587 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
588 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
589 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
601 {"rx_flow_director_atr_match_packets",
602 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
603 {"rx_flow_director_sb_match_packets",
604 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
605 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
607 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
609 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
611 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
616 sizeof(rte_i40e_hw_port_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
625 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
626 sizeof(rte_i40e_rxq_prio_strings[0]))
628 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
629 {"xon_packets", offsetof(struct i40e_hw_port_stats,
631 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
633 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
634 priority_xon_2_xoff)},
637 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
638 sizeof(rte_i40e_txq_prio_strings[0]))
641 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
642 struct rte_pci_device *pci_dev)
644 char name[RTE_ETH_NAME_MAX_LEN];
645 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
648 if (pci_dev->device.devargs) {
649 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
655 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
656 sizeof(struct i40e_adapter),
657 eth_dev_pci_specific_init, pci_dev,
658 eth_i40e_dev_init, NULL);
660 if (retval || eth_da.nb_representor_ports < 1)
663 /* probe VF representor ports */
664 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
665 pci_dev->device.name);
667 if (pf_ethdev == NULL)
670 for (i = 0; i < eth_da.nb_representor_ports; i++) {
671 struct i40e_vf_representor representor = {
672 .vf_id = eth_da.representor_ports[i],
673 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
674 pf_ethdev->data->dev_private)->switch_domain_id,
675 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
676 pf_ethdev->data->dev_private)
679 /* representor port net_bdf_port */
680 snprintf(name, sizeof(name), "net_%s_representor_%d",
681 pci_dev->device.name, eth_da.representor_ports[i]);
683 retval = rte_eth_dev_create(&pci_dev->device, name,
684 sizeof(struct i40e_vf_representor), NULL, NULL,
685 i40e_vf_representor_init, &representor);
688 PMD_DRV_LOG(ERR, "failed to create i40e vf "
689 "representor %s.", name);
695 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
697 struct rte_eth_dev *ethdev;
699 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
704 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
705 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
707 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
710 static struct rte_pci_driver rte_i40e_pmd = {
711 .id_table = pci_id_i40e_map,
712 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
713 .probe = eth_i40e_pci_probe,
714 .remove = eth_i40e_pci_remove,
718 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
721 uint32_t ori_reg_val;
722 struct rte_eth_dev *dev;
724 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
725 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
726 i40e_write_rx_ctl(hw, reg_addr, reg_val);
727 if (ori_reg_val != reg_val)
729 "i40e device %s changed global register [0x%08x]."
730 " original: 0x%08x, new: 0x%08x",
731 dev->device->name, reg_addr, ori_reg_val, reg_val);
734 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
735 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
736 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
738 #ifndef I40E_GLQF_ORT
739 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
741 #ifndef I40E_GLQF_PIT
742 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
744 #ifndef I40E_GLQF_L3_MAP
745 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
748 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
751 * Initialize registers for parsing packet type of QinQ
752 * This should be removed from code once proper
753 * configuration API is added to avoid configuration conflicts
754 * between ports of the same device.
756 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
757 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
760 static inline void i40e_config_automask(struct i40e_pf *pf)
762 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
765 /* INTENA flag is not auto-cleared for interrupt */
766 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
767 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
768 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
770 /* If support multi-driver, PF will use INT0. */
771 if (!pf->support_multi_driver)
772 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
774 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
777 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
780 * Add a ethertype filter to drop all flow control frames transmitted
784 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
786 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
787 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
788 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
789 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
792 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
793 I40E_FLOW_CONTROL_ETHERTYPE, flags,
794 pf->main_vsi_seid, 0,
798 "Failed to add filter to drop flow control frames from VSIs.");
802 floating_veb_list_handler(__rte_unused const char *key,
803 const char *floating_veb_value,
807 unsigned int count = 0;
810 bool *vf_floating_veb = opaque;
812 while (isblank(*floating_veb_value))
813 floating_veb_value++;
815 /* Reset floating VEB configuration for VFs */
816 for (idx = 0; idx < I40E_MAX_VF; idx++)
817 vf_floating_veb[idx] = false;
821 while (isblank(*floating_veb_value))
822 floating_veb_value++;
823 if (*floating_veb_value == '\0')
826 idx = strtoul(floating_veb_value, &end, 10);
827 if (errno || end == NULL)
829 while (isblank(*end))
833 } else if ((*end == ';') || (*end == '\0')) {
835 if (min == I40E_MAX_VF)
837 if (max >= I40E_MAX_VF)
838 max = I40E_MAX_VF - 1;
839 for (idx = min; idx <= max; idx++) {
840 vf_floating_veb[idx] = true;
847 floating_veb_value = end + 1;
848 } while (*end != '\0');
857 config_vf_floating_veb(struct rte_devargs *devargs,
858 uint16_t floating_veb,
859 bool *vf_floating_veb)
861 struct rte_kvargs *kvlist;
863 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
867 /* All the VFs attach to the floating VEB by default
868 * when the floating VEB is enabled.
870 for (i = 0; i < I40E_MAX_VF; i++)
871 vf_floating_veb[i] = true;
876 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
880 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
881 rte_kvargs_free(kvlist);
884 /* When the floating_veb_list parameter exists, all the VFs
885 * will attach to the legacy VEB firstly, then configure VFs
886 * to the floating VEB according to the floating_veb_list.
888 if (rte_kvargs_process(kvlist, floating_veb_list,
889 floating_veb_list_handler,
890 vf_floating_veb) < 0) {
891 rte_kvargs_free(kvlist);
894 rte_kvargs_free(kvlist);
898 i40e_check_floating_handler(__rte_unused const char *key,
900 __rte_unused void *opaque)
902 if (strcmp(value, "1"))
909 is_floating_veb_supported(struct rte_devargs *devargs)
911 struct rte_kvargs *kvlist;
912 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
917 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
921 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
922 rte_kvargs_free(kvlist);
925 /* Floating VEB is enabled when there's key-value:
926 * enable_floating_veb=1
928 if (rte_kvargs_process(kvlist, floating_veb_key,
929 i40e_check_floating_handler, NULL) < 0) {
930 rte_kvargs_free(kvlist);
933 rte_kvargs_free(kvlist);
939 config_floating_veb(struct rte_eth_dev *dev)
941 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
942 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
943 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
945 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
947 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
949 is_floating_veb_supported(pci_dev->device.devargs);
950 config_vf_floating_veb(pci_dev->device.devargs,
952 pf->floating_veb_list);
954 pf->floating_veb = false;
958 #define I40E_L2_TAGS_S_TAG_SHIFT 1
959 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
962 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
965 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
966 char ethertype_hash_name[RTE_HASH_NAMESIZE];
969 struct rte_hash_parameters ethertype_hash_params = {
970 .name = ethertype_hash_name,
971 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
972 .key_len = sizeof(struct i40e_ethertype_filter_input),
973 .hash_func = rte_hash_crc,
974 .hash_func_init_val = 0,
975 .socket_id = rte_socket_id(),
978 /* Initialize ethertype filter rule list and hash */
979 TAILQ_INIT(ðertype_rule->ethertype_list);
980 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
981 "ethertype_%s", dev->device->name);
982 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
983 if (!ethertype_rule->hash_table) {
984 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
987 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
988 sizeof(struct i40e_ethertype_filter *) *
989 I40E_MAX_ETHERTYPE_FILTER_NUM,
991 if (!ethertype_rule->hash_map) {
993 "Failed to allocate memory for ethertype hash map!");
995 goto err_ethertype_hash_map_alloc;
1000 err_ethertype_hash_map_alloc:
1001 rte_hash_free(ethertype_rule->hash_table);
1007 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1009 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1010 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1011 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1014 struct rte_hash_parameters tunnel_hash_params = {
1015 .name = tunnel_hash_name,
1016 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1017 .key_len = sizeof(struct i40e_tunnel_filter_input),
1018 .hash_func = rte_hash_crc,
1019 .hash_func_init_val = 0,
1020 .socket_id = rte_socket_id(),
1023 /* Initialize tunnel filter rule list and hash */
1024 TAILQ_INIT(&tunnel_rule->tunnel_list);
1025 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1026 "tunnel_%s", dev->device->name);
1027 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1028 if (!tunnel_rule->hash_table) {
1029 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1032 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1033 sizeof(struct i40e_tunnel_filter *) *
1034 I40E_MAX_TUNNEL_FILTER_NUM,
1036 if (!tunnel_rule->hash_map) {
1038 "Failed to allocate memory for tunnel hash map!");
1040 goto err_tunnel_hash_map_alloc;
1045 err_tunnel_hash_map_alloc:
1046 rte_hash_free(tunnel_rule->hash_table);
1052 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1054 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055 struct i40e_fdir_info *fdir_info = &pf->fdir;
1056 char fdir_hash_name[RTE_HASH_NAMESIZE];
1059 struct rte_hash_parameters fdir_hash_params = {
1060 .name = fdir_hash_name,
1061 .entries = I40E_MAX_FDIR_FILTER_NUM,
1062 .key_len = sizeof(struct i40e_fdir_input),
1063 .hash_func = rte_hash_crc,
1064 .hash_func_init_val = 0,
1065 .socket_id = rte_socket_id(),
1068 /* Initialize flow director filter rule list and hash */
1069 TAILQ_INIT(&fdir_info->fdir_list);
1070 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1071 "fdir_%s", dev->device->name);
1072 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1073 if (!fdir_info->hash_table) {
1074 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1077 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078 sizeof(struct i40e_fdir_filter *) *
1079 I40E_MAX_FDIR_FILTER_NUM,
1081 if (!fdir_info->hash_map) {
1083 "Failed to allocate memory for fdir hash map!");
1085 goto err_fdir_hash_map_alloc;
1089 err_fdir_hash_map_alloc:
1090 rte_hash_free(fdir_info->hash_table);
1096 i40e_init_customized_info(struct i40e_pf *pf)
1100 /* Initialize customized pctype */
1101 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1102 pf->customized_pctype[i].index = i;
1103 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1104 pf->customized_pctype[i].valid = false;
1107 pf->gtp_support = false;
1111 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1113 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1115 struct i40e_queue_regions *info = &pf->queue_region;
1118 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1119 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1121 memset(info, 0, sizeof(struct i40e_queue_regions));
1125 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1130 unsigned long support_multi_driver;
1133 pf = (struct i40e_pf *)opaque;
1136 support_multi_driver = strtoul(value, &end, 10);
1137 if (errno != 0 || end == value || *end != 0) {
1138 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1142 if (support_multi_driver == 1 || support_multi_driver == 0)
1143 pf->support_multi_driver = (bool)support_multi_driver;
1145 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1146 "enable global configuration by default."
1147 ETH_I40E_SUPPORT_MULTI_DRIVER);
1152 i40e_support_multi_driver(struct rte_eth_dev *dev)
1154 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1155 struct rte_kvargs *kvlist;
1158 /* Enable global configuration by default */
1159 pf->support_multi_driver = false;
1161 if (!dev->device->devargs)
1164 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1168 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1169 if (!kvargs_count) {
1170 rte_kvargs_free(kvlist);
1174 if (kvargs_count > 1)
1175 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1176 "the first invalid or last valid one is used !",
1177 ETH_I40E_SUPPORT_MULTI_DRIVER);
1179 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1180 i40e_parse_multi_drv_handler, pf) < 0) {
1181 rte_kvargs_free(kvlist);
1185 rte_kvargs_free(kvlist);
1190 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1191 uint32_t reg_addr, uint64_t reg_val,
1192 struct i40e_asq_cmd_details *cmd_details)
1194 uint64_t ori_reg_val;
1195 struct rte_eth_dev *dev;
1198 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1199 if (ret != I40E_SUCCESS) {
1201 "Fail to debug read from 0x%08x",
1205 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1207 if (ori_reg_val != reg_val)
1208 PMD_DRV_LOG(WARNING,
1209 "i40e device %s changed global register [0x%08x]."
1210 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1211 dev->device->name, reg_addr, ori_reg_val, reg_val);
1213 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1217 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1221 struct i40e_adapter *ad = opaque;
1224 use_latest_vec = atoi(value);
1226 if (use_latest_vec != 0 && use_latest_vec != 1)
1227 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1229 ad->use_latest_vec = (uint8_t)use_latest_vec;
1235 i40e_use_latest_vec(struct rte_eth_dev *dev)
1237 struct i40e_adapter *ad =
1238 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1239 struct rte_kvargs *kvlist;
1242 ad->use_latest_vec = false;
1244 if (!dev->device->devargs)
1247 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1251 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1252 if (!kvargs_count) {
1253 rte_kvargs_free(kvlist);
1257 if (kvargs_count > 1)
1258 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1259 "the first invalid or last valid one is used !",
1260 ETH_I40E_USE_LATEST_VEC);
1262 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1263 i40e_parse_latest_vec_handler, ad) < 0) {
1264 rte_kvargs_free(kvlist);
1268 rte_kvargs_free(kvlist);
1273 read_vf_msg_config(__rte_unused const char *key,
1277 struct i40e_vf_msg_cfg *cfg = opaque;
1279 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1280 &cfg->ignore_second) != 3) {
1281 memset(cfg, 0, sizeof(*cfg));
1282 PMD_DRV_LOG(ERR, "format error! example: "
1283 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1288 * If the message validation function been enabled, the 'period'
1289 * and 'ignore_second' must greater than 0.
1291 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1292 memset(cfg, 0, sizeof(*cfg));
1293 PMD_DRV_LOG(ERR, "%s error! the second and third"
1294 " number must be greater than 0!",
1295 ETH_I40E_VF_MSG_CFG);
1303 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1304 struct i40e_vf_msg_cfg *msg_cfg)
1306 struct rte_kvargs *kvlist;
1310 memset(msg_cfg, 0, sizeof(*msg_cfg));
1312 if (!dev->device->devargs)
1315 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1319 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1323 if (kvargs_count > 1) {
1324 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1325 ETH_I40E_VF_MSG_CFG);
1330 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1331 read_vf_msg_config, msg_cfg) < 0)
1335 rte_kvargs_free(kvlist);
1339 #define I40E_ALARM_INTERVAL 50000 /* us */
1342 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1344 struct rte_pci_device *pci_dev;
1345 struct rte_intr_handle *intr_handle;
1346 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 struct i40e_vsi *vsi;
1351 uint8_t aq_fail = 0;
1353 PMD_INIT_FUNC_TRACE();
1355 dev->dev_ops = &i40e_eth_dev_ops;
1356 dev->rx_pkt_burst = i40e_recv_pkts;
1357 dev->tx_pkt_burst = i40e_xmit_pkts;
1358 dev->tx_pkt_prepare = i40e_prep_pkts;
1360 /* for secondary processes, we don't initialise any further as primary
1361 * has already done this work. Only check we don't need a different
1363 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1364 i40e_set_rx_function(dev);
1365 i40e_set_tx_function(dev);
1368 i40e_set_default_ptype_table(dev);
1369 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1370 intr_handle = &pci_dev->intr_handle;
1372 rte_eth_copy_pci_info(dev, pci_dev);
1374 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1375 pf->adapter->eth_dev = dev;
1376 pf->dev_data = dev->data;
1378 hw->back = I40E_PF_TO_ADAPTER(pf);
1379 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1382 "Hardware is not available, as address is NULL");
1386 hw->vendor_id = pci_dev->id.vendor_id;
1387 hw->device_id = pci_dev->id.device_id;
1388 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1389 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1390 hw->bus.device = pci_dev->addr.devid;
1391 hw->bus.func = pci_dev->addr.function;
1392 hw->adapter_stopped = 0;
1393 hw->adapter_closed = 0;
1396 * Switch Tag value should not be identical to either the First Tag
1397 * or Second Tag values. So set something other than common Ethertype
1398 * for internal switching.
1400 hw->switch_tag = 0xffff;
1402 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1403 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1404 PMD_INIT_LOG(ERR, "\nERROR: "
1405 "Firmware recovery mode detected. Limiting functionality.\n"
1406 "Refer to the Intel(R) Ethernet Adapters and Devices "
1407 "User Guide for details on firmware recovery mode.");
1411 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1412 /* Check if need to support multi-driver */
1413 i40e_support_multi_driver(dev);
1414 /* Check if users want the latest supported vec path */
1415 i40e_use_latest_vec(dev);
1417 /* Make sure all is clean before doing PF reset */
1420 /* Reset here to make sure all is clean for each PF */
1421 ret = i40e_pf_reset(hw);
1423 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1427 /* Initialize the shared code (base driver) */
1428 ret = i40e_init_shared_code(hw);
1430 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1434 /* Initialize the parameters for adminq */
1435 i40e_init_adminq_parameter(hw);
1436 ret = i40e_init_adminq(hw);
1437 if (ret != I40E_SUCCESS) {
1438 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1441 /* Firmware of SFP x722 does not support adminq option */
1442 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1443 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1445 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1446 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1447 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1448 ((hw->nvm.version >> 12) & 0xf),
1449 ((hw->nvm.version >> 4) & 0xff),
1450 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1452 /* Initialize the hardware */
1455 i40e_config_automask(pf);
1457 i40e_set_default_pctype_table(dev);
1460 * To work around the NVM issue, initialize registers
1461 * for packet type of QinQ by software.
1462 * It should be removed once issues are fixed in NVM.
1464 if (!pf->support_multi_driver)
1465 i40e_GLQF_reg_init(hw);
1467 /* Initialize the input set for filters (hash and fd) to default value */
1468 i40e_filter_input_set_init(pf);
1470 /* initialise the L3_MAP register */
1471 if (!pf->support_multi_driver) {
1472 ret = i40e_aq_debug_write_global_register(hw,
1473 I40E_GLQF_L3_MAP(40),
1476 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1479 "Global register 0x%08x is changed with 0x28",
1480 I40E_GLQF_L3_MAP(40));
1483 /* Need the special FW version to support floating VEB */
1484 config_floating_veb(dev);
1485 /* Clear PXE mode */
1486 i40e_clear_pxe_mode(hw);
1487 i40e_dev_sync_phy_type(hw);
1490 * On X710, performance number is far from the expectation on recent
1491 * firmware versions. The fix for this issue may not be integrated in
1492 * the following firmware version. So the workaround in software driver
1493 * is needed. It needs to modify the initial values of 3 internal only
1494 * registers. Note that the workaround can be removed when it is fixed
1495 * in firmware in the future.
1497 i40e_configure_registers(hw);
1499 /* Get hw capabilities */
1500 ret = i40e_get_cap(hw);
1501 if (ret != I40E_SUCCESS) {
1502 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1503 goto err_get_capabilities;
1506 /* Initialize parameters for PF */
1507 ret = i40e_pf_parameter_init(dev);
1509 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1510 goto err_parameter_init;
1513 /* Initialize the queue management */
1514 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1516 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1517 goto err_qp_pool_init;
1519 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1520 hw->func_caps.num_msix_vectors - 1);
1522 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1523 goto err_msix_pool_init;
1526 /* Initialize lan hmc */
1527 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1528 hw->func_caps.num_rx_qp, 0, 0);
1529 if (ret != I40E_SUCCESS) {
1530 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1531 goto err_init_lan_hmc;
1534 /* Configure lan hmc */
1535 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1536 if (ret != I40E_SUCCESS) {
1537 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1538 goto err_configure_lan_hmc;
1541 /* Get and check the mac address */
1542 i40e_get_mac_addr(hw, hw->mac.addr);
1543 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1544 PMD_INIT_LOG(ERR, "mac address is not valid");
1546 goto err_get_mac_addr;
1548 /* Copy the permanent MAC address */
1549 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1550 (struct rte_ether_addr *)hw->mac.perm_addr);
1552 /* Disable flow control */
1553 hw->fc.requested_mode = I40E_FC_NONE;
1554 i40e_set_fc(hw, &aq_fail, TRUE);
1556 /* Set the global registers with default ether type value */
1557 if (!pf->support_multi_driver) {
1558 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1559 RTE_ETHER_TYPE_VLAN);
1560 if (ret != I40E_SUCCESS) {
1562 "Failed to set the default outer "
1564 goto err_setup_pf_switch;
1568 /* PF setup, which includes VSI setup */
1569 ret = i40e_pf_setup(pf);
1571 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1572 goto err_setup_pf_switch;
1577 /* Disable double vlan by default */
1578 i40e_vsi_config_double_vlan(vsi, FALSE);
1580 /* Disable S-TAG identification when floating_veb is disabled */
1581 if (!pf->floating_veb) {
1582 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1583 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1584 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1585 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1589 if (!vsi->max_macaddrs)
1590 len = RTE_ETHER_ADDR_LEN;
1592 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1594 /* Should be after VSI initialized */
1595 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1596 if (!dev->data->mac_addrs) {
1598 "Failed to allocated memory for storing mac address");
1601 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1602 &dev->data->mac_addrs[0]);
1604 /* Pass the information to the rte_eth_dev_close() that it should also
1605 * release the private port resources.
1607 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1609 /* Init dcb to sw mode by default */
1610 ret = i40e_dcb_init_configure(dev, TRUE);
1611 if (ret != I40E_SUCCESS) {
1612 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1613 pf->flags &= ~I40E_FLAG_DCB;
1615 /* Update HW struct after DCB configuration */
1618 /* initialize pf host driver to setup SRIOV resource if applicable */
1619 i40e_pf_host_init(dev);
1621 /* register callback func to eal lib */
1622 rte_intr_callback_register(intr_handle,
1623 i40e_dev_interrupt_handler, dev);
1625 /* configure and enable device interrupt */
1626 i40e_pf_config_irq0(hw, TRUE);
1627 i40e_pf_enable_irq0(hw);
1629 /* enable uio intr after callback register */
1630 rte_intr_enable(intr_handle);
1632 /* By default disable flexible payload in global configuration */
1633 if (!pf->support_multi_driver)
1634 i40e_flex_payload_reg_set_default(hw);
1637 * Add an ethertype filter to drop all flow control frames transmitted
1638 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1641 i40e_add_tx_flow_control_drop_filter(pf);
1643 /* Set the max frame size to 0x2600 by default,
1644 * in case other drivers changed the default value.
1646 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1648 /* initialize mirror rule list */
1649 TAILQ_INIT(&pf->mirror_list);
1651 /* initialize Traffic Manager configuration */
1652 i40e_tm_conf_init(dev);
1654 /* Initialize customized information */
1655 i40e_init_customized_info(pf);
1657 ret = i40e_init_ethtype_filter_list(dev);
1659 goto err_init_ethtype_filter_list;
1660 ret = i40e_init_tunnel_filter_list(dev);
1662 goto err_init_tunnel_filter_list;
1663 ret = i40e_init_fdir_filter_list(dev);
1665 goto err_init_fdir_filter_list;
1667 /* initialize queue region configuration */
1668 i40e_init_queue_region_conf(dev);
1670 /* initialize rss configuration from rte_flow */
1671 memset(&pf->rss_info, 0,
1672 sizeof(struct i40e_rte_flow_rss_conf));
1674 /* reset all stats of the device, including pf and main vsi */
1675 i40e_dev_stats_reset(dev);
1679 err_init_fdir_filter_list:
1680 rte_free(pf->tunnel.hash_table);
1681 rte_free(pf->tunnel.hash_map);
1682 err_init_tunnel_filter_list:
1683 rte_free(pf->ethertype.hash_table);
1684 rte_free(pf->ethertype.hash_map);
1685 err_init_ethtype_filter_list:
1686 rte_free(dev->data->mac_addrs);
1687 dev->data->mac_addrs = NULL;
1689 i40e_vsi_release(pf->main_vsi);
1690 err_setup_pf_switch:
1692 err_configure_lan_hmc:
1693 (void)i40e_shutdown_lan_hmc(hw);
1695 i40e_res_pool_destroy(&pf->msix_pool);
1697 i40e_res_pool_destroy(&pf->qp_pool);
1700 err_get_capabilities:
1701 (void)i40e_shutdown_adminq(hw);
1707 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1709 struct i40e_ethertype_filter *p_ethertype;
1710 struct i40e_ethertype_rule *ethertype_rule;
1712 ethertype_rule = &pf->ethertype;
1713 /* Remove all ethertype filter rules and hash */
1714 if (ethertype_rule->hash_map)
1715 rte_free(ethertype_rule->hash_map);
1716 if (ethertype_rule->hash_table)
1717 rte_hash_free(ethertype_rule->hash_table);
1719 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1720 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1721 p_ethertype, rules);
1722 rte_free(p_ethertype);
1727 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1729 struct i40e_tunnel_filter *p_tunnel;
1730 struct i40e_tunnel_rule *tunnel_rule;
1732 tunnel_rule = &pf->tunnel;
1733 /* Remove all tunnel director rules and hash */
1734 if (tunnel_rule->hash_map)
1735 rte_free(tunnel_rule->hash_map);
1736 if (tunnel_rule->hash_table)
1737 rte_hash_free(tunnel_rule->hash_table);
1739 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1740 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1746 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1748 struct i40e_fdir_filter *p_fdir;
1749 struct i40e_fdir_info *fdir_info;
1751 fdir_info = &pf->fdir;
1752 /* Remove all flow director rules and hash */
1753 if (fdir_info->hash_map)
1754 rte_free(fdir_info->hash_map);
1755 if (fdir_info->hash_table)
1756 rte_hash_free(fdir_info->hash_table);
1758 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1759 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1764 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1767 * Disable by default flexible payload
1768 * for corresponding L2/L3/L4 layers.
1770 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1771 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1772 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1776 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1780 PMD_INIT_FUNC_TRACE();
1782 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1785 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787 if (hw->adapter_closed == 0)
1788 i40e_dev_close(dev);
1794 i40e_dev_configure(struct rte_eth_dev *dev)
1796 struct i40e_adapter *ad =
1797 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1803 ret = i40e_dev_sync_phy_type(hw);
1807 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1808 * bulk allocation or vector Rx preconditions we will reset it.
1810 ad->rx_bulk_alloc_allowed = true;
1811 ad->rx_vec_allowed = true;
1812 ad->tx_simple_allowed = true;
1813 ad->tx_vec_allowed = true;
1815 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1817 /* Only legacy filter API needs the following fdir config. So when the
1818 * legacy filter API is deprecated, the following codes should also be
1821 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1822 ret = i40e_fdir_setup(pf);
1823 if (ret != I40E_SUCCESS) {
1824 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1827 ret = i40e_fdir_configure(dev);
1829 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1833 i40e_fdir_teardown(pf);
1835 ret = i40e_dev_init_vlan(dev);
1840 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1841 * RSS setting have different requirements.
1842 * General PMD driver call sequence are NIC init, configure,
1843 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1844 * will try to lookup the VSI that specific queue belongs to if VMDQ
1845 * applicable. So, VMDQ setting has to be done before
1846 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1847 * For RSS setting, it will try to calculate actual configured RX queue
1848 * number, which will be available after rx_queue_setup(). dev_start()
1849 * function is good to place RSS setup.
1851 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1852 ret = i40e_vmdq_setup(dev);
1857 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1858 ret = i40e_dcb_setup(dev);
1860 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1865 TAILQ_INIT(&pf->flow_list);
1870 /* need to release vmdq resource if exists */
1871 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1872 i40e_vsi_release(pf->vmdq[i].vsi);
1873 pf->vmdq[i].vsi = NULL;
1878 /* Need to release fdir resource if exists.
1879 * Only legacy filter API needs the following fdir config. So when the
1880 * legacy filter API is deprecated, the following code should also be
1883 i40e_fdir_teardown(pf);
1888 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1890 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1891 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1892 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1893 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1894 uint16_t msix_vect = vsi->msix_intr;
1897 for (i = 0; i < vsi->nb_qps; i++) {
1898 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1899 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1903 if (vsi->type != I40E_VSI_SRIOV) {
1904 if (!rte_intr_allow_others(intr_handle)) {
1905 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1906 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1908 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1911 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1912 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1914 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1919 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1920 vsi->user_param + (msix_vect - 1);
1922 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1923 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1925 I40E_WRITE_FLUSH(hw);
1929 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1930 int base_queue, int nb_queue,
1935 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1936 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1938 /* Bind all RX queues to allocated MSIX interrupt */
1939 for (i = 0; i < nb_queue; i++) {
1940 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1941 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1942 ((base_queue + i + 1) <<
1943 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1944 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1945 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1947 if (i == nb_queue - 1)
1948 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1949 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1952 /* Write first RX queue to Link list register as the head element */
1953 if (vsi->type != I40E_VSI_SRIOV) {
1955 i40e_calc_itr_interval(1, pf->support_multi_driver);
1957 if (msix_vect == I40E_MISC_VEC_ID) {
1958 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1960 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1962 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1964 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1967 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1969 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1971 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1973 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1980 if (msix_vect == I40E_MISC_VEC_ID) {
1982 I40E_VPINT_LNKLST0(vsi->user_param),
1984 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1986 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1988 /* num_msix_vectors_vf needs to minus irq0 */
1989 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1990 vsi->user_param + (msix_vect - 1);
1992 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1994 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1996 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2000 I40E_WRITE_FLUSH(hw);
2004 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2006 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2007 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2008 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2009 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2010 uint16_t msix_vect = vsi->msix_intr;
2011 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2012 uint16_t queue_idx = 0;
2016 for (i = 0; i < vsi->nb_qps; i++) {
2017 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2018 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2021 /* VF bind interrupt */
2022 if (vsi->type == I40E_VSI_SRIOV) {
2023 __vsi_queues_bind_intr(vsi, msix_vect,
2024 vsi->base_queue, vsi->nb_qps,
2029 /* PF & VMDq bind interrupt */
2030 if (rte_intr_dp_is_en(intr_handle)) {
2031 if (vsi->type == I40E_VSI_MAIN) {
2034 } else if (vsi->type == I40E_VSI_VMDQ2) {
2035 struct i40e_vsi *main_vsi =
2036 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2037 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2042 for (i = 0; i < vsi->nb_used_qps; i++) {
2044 if (!rte_intr_allow_others(intr_handle))
2045 /* allow to share MISC_VEC_ID */
2046 msix_vect = I40E_MISC_VEC_ID;
2048 /* no enough msix_vect, map all to one */
2049 __vsi_queues_bind_intr(vsi, msix_vect,
2050 vsi->base_queue + i,
2051 vsi->nb_used_qps - i,
2053 for (; !!record && i < vsi->nb_used_qps; i++)
2054 intr_handle->intr_vec[queue_idx + i] =
2058 /* 1:1 queue/msix_vect mapping */
2059 __vsi_queues_bind_intr(vsi, msix_vect,
2060 vsi->base_queue + i, 1,
2063 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2071 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2073 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2075 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2076 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2077 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2078 uint16_t msix_intr, i;
2080 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2081 for (i = 0; i < vsi->nb_msix; i++) {
2082 msix_intr = vsi->msix_intr + i;
2083 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2084 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2085 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2086 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2089 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2090 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2091 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2092 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2094 I40E_WRITE_FLUSH(hw);
2098 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2100 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2101 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2102 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2103 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2104 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2105 uint16_t msix_intr, i;
2107 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2108 for (i = 0; i < vsi->nb_msix; i++) {
2109 msix_intr = vsi->msix_intr + i;
2110 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2111 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2114 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2115 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2117 I40E_WRITE_FLUSH(hw);
2120 static inline uint8_t
2121 i40e_parse_link_speeds(uint16_t link_speeds)
2123 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2125 if (link_speeds & ETH_LINK_SPEED_40G)
2126 link_speed |= I40E_LINK_SPEED_40GB;
2127 if (link_speeds & ETH_LINK_SPEED_25G)
2128 link_speed |= I40E_LINK_SPEED_25GB;
2129 if (link_speeds & ETH_LINK_SPEED_20G)
2130 link_speed |= I40E_LINK_SPEED_20GB;
2131 if (link_speeds & ETH_LINK_SPEED_10G)
2132 link_speed |= I40E_LINK_SPEED_10GB;
2133 if (link_speeds & ETH_LINK_SPEED_1G)
2134 link_speed |= I40E_LINK_SPEED_1GB;
2135 if (link_speeds & ETH_LINK_SPEED_100M)
2136 link_speed |= I40E_LINK_SPEED_100MB;
2142 i40e_phy_conf_link(struct i40e_hw *hw,
2144 uint8_t force_speed,
2147 enum i40e_status_code status;
2148 struct i40e_aq_get_phy_abilities_resp phy_ab;
2149 struct i40e_aq_set_phy_config phy_conf;
2150 enum i40e_aq_phy_type cnt;
2151 uint8_t avail_speed;
2152 uint32_t phy_type_mask = 0;
2154 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2155 I40E_AQ_PHY_FLAG_PAUSE_RX |
2156 I40E_AQ_PHY_FLAG_PAUSE_RX |
2157 I40E_AQ_PHY_FLAG_LOW_POWER;
2160 /* To get phy capabilities of available speeds. */
2161 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2164 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2168 avail_speed = phy_ab.link_speed;
2170 /* To get the current phy config. */
2171 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2174 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2179 /* If link needs to go up and it is in autoneg mode the speed is OK,
2180 * no need to set up again.
2182 if (is_up && phy_ab.phy_type != 0 &&
2183 abilities & I40E_AQ_PHY_AN_ENABLED &&
2184 phy_ab.link_speed != 0)
2185 return I40E_SUCCESS;
2187 memset(&phy_conf, 0, sizeof(phy_conf));
2189 /* bits 0-2 use the values from get_phy_abilities_resp */
2191 abilities |= phy_ab.abilities & mask;
2193 phy_conf.abilities = abilities;
2195 /* If link needs to go up, but the force speed is not supported,
2196 * Warn users and config the default available speeds.
2198 if (is_up && !(force_speed & avail_speed)) {
2199 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2200 phy_conf.link_speed = avail_speed;
2202 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2205 /* PHY type mask needs to include each type except PHY type extension */
2206 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2207 phy_type_mask |= 1 << cnt;
2209 /* use get_phy_abilities_resp value for the rest */
2210 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2211 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2212 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2213 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2214 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2215 phy_conf.eee_capability = phy_ab.eee_capability;
2216 phy_conf.eeer = phy_ab.eeer_val;
2217 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2219 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2220 phy_ab.abilities, phy_ab.link_speed);
2221 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2222 phy_conf.abilities, phy_conf.link_speed);
2224 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2228 return I40E_SUCCESS;
2232 i40e_apply_link_speed(struct rte_eth_dev *dev)
2235 uint8_t abilities = 0;
2236 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237 struct rte_eth_conf *conf = &dev->data->dev_conf;
2239 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2240 conf->link_speeds = ETH_LINK_SPEED_40G |
2241 ETH_LINK_SPEED_25G |
2242 ETH_LINK_SPEED_20G |
2243 ETH_LINK_SPEED_10G |
2245 ETH_LINK_SPEED_100M;
2247 speed = i40e_parse_link_speeds(conf->link_speeds);
2248 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2249 I40E_AQ_PHY_AN_ENABLED |
2250 I40E_AQ_PHY_LINK_ENABLED;
2252 return i40e_phy_conf_link(hw, abilities, speed, true);
2256 i40e_dev_start(struct rte_eth_dev *dev)
2258 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2259 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260 struct i40e_vsi *main_vsi = pf->main_vsi;
2262 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2263 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2264 uint32_t intr_vector = 0;
2265 struct i40e_vsi *vsi;
2267 hw->adapter_stopped = 0;
2269 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2271 "Invalid link_speeds for port %u, autonegotiation disabled",
2272 dev->data->port_id);
2276 rte_intr_disable(intr_handle);
2278 if ((rte_intr_cap_multiple(intr_handle) ||
2279 !RTE_ETH_DEV_SRIOV(dev).active) &&
2280 dev->data->dev_conf.intr_conf.rxq != 0) {
2281 intr_vector = dev->data->nb_rx_queues;
2282 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2287 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2288 intr_handle->intr_vec =
2289 rte_zmalloc("intr_vec",
2290 dev->data->nb_rx_queues * sizeof(int),
2292 if (!intr_handle->intr_vec) {
2294 "Failed to allocate %d rx_queues intr_vec",
2295 dev->data->nb_rx_queues);
2300 /* Initialize VSI */
2301 ret = i40e_dev_rxtx_init(pf);
2302 if (ret != I40E_SUCCESS) {
2303 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2307 /* Map queues with MSIX interrupt */
2308 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2309 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2310 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2311 i40e_vsi_enable_queues_intr(main_vsi);
2313 /* Map VMDQ VSI queues with MSIX interrupt */
2314 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2315 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2316 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2317 I40E_ITR_INDEX_DEFAULT);
2318 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2321 /* enable FDIR MSIX interrupt */
2322 if (pf->fdir.fdir_vsi) {
2323 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2324 I40E_ITR_INDEX_NONE);
2325 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2328 /* Enable all queues which have been configured */
2329 ret = i40e_dev_switch_queues(pf, TRUE);
2330 if (ret != I40E_SUCCESS) {
2331 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2335 /* Enable receiving broadcast packets */
2336 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2337 if (ret != I40E_SUCCESS)
2338 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2340 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2341 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2343 if (ret != I40E_SUCCESS)
2344 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2347 /* Enable the VLAN promiscuous mode. */
2349 for (i = 0; i < pf->vf_num; i++) {
2350 vsi = pf->vfs[i].vsi;
2351 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2356 /* Enable mac loopback mode */
2357 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2358 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2359 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2360 if (ret != I40E_SUCCESS) {
2361 PMD_DRV_LOG(ERR, "fail to set loopback link");
2366 /* Apply link configure */
2367 ret = i40e_apply_link_speed(dev);
2368 if (I40E_SUCCESS != ret) {
2369 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2373 if (!rte_intr_allow_others(intr_handle)) {
2374 rte_intr_callback_unregister(intr_handle,
2375 i40e_dev_interrupt_handler,
2377 /* configure and enable device interrupt */
2378 i40e_pf_config_irq0(hw, FALSE);
2379 i40e_pf_enable_irq0(hw);
2381 if (dev->data->dev_conf.intr_conf.lsc != 0)
2383 "lsc won't enable because of no intr multiplex");
2385 ret = i40e_aq_set_phy_int_mask(hw,
2386 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2387 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2388 I40E_AQ_EVENT_MEDIA_NA), NULL);
2389 if (ret != I40E_SUCCESS)
2390 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2392 /* Call get_link_info aq commond to enable/disable LSE */
2393 i40e_dev_link_update(dev, 0);
2396 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2397 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2398 i40e_dev_alarm_handler, dev);
2400 /* enable uio intr after callback register */
2401 rte_intr_enable(intr_handle);
2404 i40e_filter_restore(pf);
2406 if (pf->tm_conf.root && !pf->tm_conf.committed)
2407 PMD_DRV_LOG(WARNING,
2408 "please call hierarchy_commit() "
2409 "before starting the port");
2411 return I40E_SUCCESS;
2414 i40e_dev_switch_queues(pf, FALSE);
2415 i40e_dev_clear_queues(dev);
2421 i40e_dev_stop(struct rte_eth_dev *dev)
2423 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2424 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425 struct i40e_vsi *main_vsi = pf->main_vsi;
2426 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2427 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2430 if (hw->adapter_stopped == 1)
2433 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2434 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2435 rte_intr_enable(intr_handle);
2438 /* Disable all queues */
2439 i40e_dev_switch_queues(pf, FALSE);
2441 /* un-map queues with interrupt registers */
2442 i40e_vsi_disable_queues_intr(main_vsi);
2443 i40e_vsi_queues_unbind_intr(main_vsi);
2445 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2446 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2447 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2450 if (pf->fdir.fdir_vsi) {
2451 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2452 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2454 /* Clear all queues and release memory */
2455 i40e_dev_clear_queues(dev);
2458 i40e_dev_set_link_down(dev);
2460 if (!rte_intr_allow_others(intr_handle))
2461 /* resume to the default handler */
2462 rte_intr_callback_register(intr_handle,
2463 i40e_dev_interrupt_handler,
2466 /* Clean datapath event and queue/vec mapping */
2467 rte_intr_efd_disable(intr_handle);
2468 if (intr_handle->intr_vec) {
2469 rte_free(intr_handle->intr_vec);
2470 intr_handle->intr_vec = NULL;
2473 /* reset hierarchy commit */
2474 pf->tm_conf.committed = false;
2476 hw->adapter_stopped = 1;
2478 pf->adapter->rss_reta_updated = 0;
2482 i40e_dev_close(struct rte_eth_dev *dev)
2484 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2485 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2487 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2488 struct i40e_mirror_rule *p_mirror;
2489 struct i40e_filter_control_settings settings;
2490 struct rte_flow *p_flow;
2494 uint8_t aq_fail = 0;
2497 PMD_INIT_FUNC_TRACE();
2499 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2501 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2506 /* Remove all mirror rules */
2507 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2508 ret = i40e_aq_del_mirror_rule(hw,
2509 pf->main_vsi->veb->seid,
2510 p_mirror->rule_type,
2512 p_mirror->num_entries,
2515 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2516 "status = %d, aq_err = %d.", ret,
2517 hw->aq.asq_last_status);
2519 /* remove mirror software resource anyway */
2520 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2522 pf->nb_mirror_rule--;
2525 i40e_dev_free_queues(dev);
2527 /* Disable interrupt */
2528 i40e_pf_disable_irq0(hw);
2529 rte_intr_disable(intr_handle);
2532 * Only legacy filter API needs the following fdir config. So when the
2533 * legacy filter API is deprecated, the following code should also be
2536 i40e_fdir_teardown(pf);
2538 /* shutdown and destroy the HMC */
2539 i40e_shutdown_lan_hmc(hw);
2541 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2542 i40e_vsi_release(pf->vmdq[i].vsi);
2543 pf->vmdq[i].vsi = NULL;
2548 /* release all the existing VSIs and VEBs */
2549 i40e_vsi_release(pf->main_vsi);
2551 /* shutdown the adminq */
2552 i40e_aq_queue_shutdown(hw, true);
2553 i40e_shutdown_adminq(hw);
2555 i40e_res_pool_destroy(&pf->qp_pool);
2556 i40e_res_pool_destroy(&pf->msix_pool);
2558 /* Disable flexible payload in global configuration */
2559 if (!pf->support_multi_driver)
2560 i40e_flex_payload_reg_set_default(hw);
2562 /* force a PF reset to clean anything leftover */
2563 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2564 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2565 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2566 I40E_WRITE_FLUSH(hw);
2568 dev->dev_ops = NULL;
2569 dev->rx_pkt_burst = NULL;
2570 dev->tx_pkt_burst = NULL;
2572 /* Clear PXE mode */
2573 i40e_clear_pxe_mode(hw);
2575 /* Unconfigure filter control */
2576 memset(&settings, 0, sizeof(settings));
2577 ret = i40e_set_filter_control(hw, &settings);
2579 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2582 /* Disable flow control */
2583 hw->fc.requested_mode = I40E_FC_NONE;
2584 i40e_set_fc(hw, &aq_fail, TRUE);
2586 /* uninitialize pf host driver */
2587 i40e_pf_host_uninit(dev);
2590 ret = rte_intr_callback_unregister(intr_handle,
2591 i40e_dev_interrupt_handler, dev);
2594 } else if (ret != -EAGAIN) {
2596 "intr callback unregister failed: %d",
2599 i40e_msec_delay(500);
2600 } while (retries++ < 5);
2602 i40e_rm_ethtype_filter_list(pf);
2603 i40e_rm_tunnel_filter_list(pf);
2604 i40e_rm_fdir_filter_list(pf);
2606 /* Remove all flows */
2607 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2608 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2612 /* Remove all Traffic Manager configuration */
2613 i40e_tm_conf_uninit(dev);
2615 hw->adapter_closed = 1;
2619 * Reset PF device only to re-initialize resources in PMD layer
2622 i40e_dev_reset(struct rte_eth_dev *dev)
2626 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2627 * its VF to make them align with it. The detailed notification
2628 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2629 * To avoid unexpected behavior in VF, currently reset of PF with
2630 * SR-IOV activation is not supported. It might be supported later.
2632 if (dev->data->sriov.active)
2635 ret = eth_i40e_dev_uninit(dev);
2639 ret = eth_i40e_dev_init(dev, NULL);
2645 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2647 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2648 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649 struct i40e_vsi *vsi = pf->main_vsi;
2652 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2654 if (status != I40E_SUCCESS) {
2655 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2659 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2661 if (status != I40E_SUCCESS) {
2662 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2663 /* Rollback unicast promiscuous mode */
2664 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2673 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2675 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677 struct i40e_vsi *vsi = pf->main_vsi;
2680 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2682 if (status != I40E_SUCCESS) {
2683 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2687 /* must remain in all_multicast mode */
2688 if (dev->data->all_multicast == 1)
2691 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2693 if (status != I40E_SUCCESS) {
2694 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2695 /* Rollback unicast promiscuous mode */
2696 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2705 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2707 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2708 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709 struct i40e_vsi *vsi = pf->main_vsi;
2712 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2713 if (ret != I40E_SUCCESS) {
2714 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2722 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2724 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2725 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2726 struct i40e_vsi *vsi = pf->main_vsi;
2729 if (dev->data->promiscuous == 1)
2730 return 0; /* must remain in all_multicast mode */
2732 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2733 vsi->seid, FALSE, NULL);
2734 if (ret != I40E_SUCCESS) {
2735 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2743 * Set device link up.
2746 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2748 /* re-apply link speed setting */
2749 return i40e_apply_link_speed(dev);
2753 * Set device link down.
2756 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2758 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2759 uint8_t abilities = 0;
2760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2763 return i40e_phy_conf_link(hw, abilities, speed, false);
2766 static __rte_always_inline void
2767 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2769 /* Link status registers and values*/
2770 #define I40E_PRTMAC_LINKSTA 0x001E2420
2771 #define I40E_REG_LINK_UP 0x40000080
2772 #define I40E_PRTMAC_MACC 0x001E24E0
2773 #define I40E_REG_MACC_25GB 0x00020000
2774 #define I40E_REG_SPEED_MASK 0x38000000
2775 #define I40E_REG_SPEED_0 0x00000000
2776 #define I40E_REG_SPEED_1 0x08000000
2777 #define I40E_REG_SPEED_2 0x10000000
2778 #define I40E_REG_SPEED_3 0x18000000
2779 #define I40E_REG_SPEED_4 0x20000000
2780 uint32_t link_speed;
2783 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2784 link_speed = reg_val & I40E_REG_SPEED_MASK;
2785 reg_val &= I40E_REG_LINK_UP;
2786 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2788 if (unlikely(link->link_status == 0))
2791 /* Parse the link status */
2792 switch (link_speed) {
2793 case I40E_REG_SPEED_0:
2794 link->link_speed = ETH_SPEED_NUM_100M;
2796 case I40E_REG_SPEED_1:
2797 link->link_speed = ETH_SPEED_NUM_1G;
2799 case I40E_REG_SPEED_2:
2800 if (hw->mac.type == I40E_MAC_X722)
2801 link->link_speed = ETH_SPEED_NUM_2_5G;
2803 link->link_speed = ETH_SPEED_NUM_10G;
2805 case I40E_REG_SPEED_3:
2806 if (hw->mac.type == I40E_MAC_X722) {
2807 link->link_speed = ETH_SPEED_NUM_5G;
2809 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2811 if (reg_val & I40E_REG_MACC_25GB)
2812 link->link_speed = ETH_SPEED_NUM_25G;
2814 link->link_speed = ETH_SPEED_NUM_40G;
2817 case I40E_REG_SPEED_4:
2818 if (hw->mac.type == I40E_MAC_X722)
2819 link->link_speed = ETH_SPEED_NUM_10G;
2821 link->link_speed = ETH_SPEED_NUM_20G;
2824 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2829 static __rte_always_inline void
2830 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2831 bool enable_lse, int wait_to_complete)
2833 #define CHECK_INTERVAL 100 /* 100ms */
2834 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2835 uint32_t rep_cnt = MAX_REPEAT_TIME;
2836 struct i40e_link_status link_status;
2839 memset(&link_status, 0, sizeof(link_status));
2842 memset(&link_status, 0, sizeof(link_status));
2844 /* Get link status information from hardware */
2845 status = i40e_aq_get_link_info(hw, enable_lse,
2846 &link_status, NULL);
2847 if (unlikely(status != I40E_SUCCESS)) {
2848 link->link_speed = ETH_SPEED_NUM_NONE;
2849 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2850 PMD_DRV_LOG(ERR, "Failed to get link info");
2854 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2855 if (!wait_to_complete || link->link_status)
2858 rte_delay_ms(CHECK_INTERVAL);
2859 } while (--rep_cnt);
2861 /* Parse the link status */
2862 switch (link_status.link_speed) {
2863 case I40E_LINK_SPEED_100MB:
2864 link->link_speed = ETH_SPEED_NUM_100M;
2866 case I40E_LINK_SPEED_1GB:
2867 link->link_speed = ETH_SPEED_NUM_1G;
2869 case I40E_LINK_SPEED_10GB:
2870 link->link_speed = ETH_SPEED_NUM_10G;
2872 case I40E_LINK_SPEED_20GB:
2873 link->link_speed = ETH_SPEED_NUM_20G;
2875 case I40E_LINK_SPEED_25GB:
2876 link->link_speed = ETH_SPEED_NUM_25G;
2878 case I40E_LINK_SPEED_40GB:
2879 link->link_speed = ETH_SPEED_NUM_40G;
2882 link->link_speed = ETH_SPEED_NUM_NONE;
2888 i40e_dev_link_update(struct rte_eth_dev *dev,
2889 int wait_to_complete)
2891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2892 struct rte_eth_link link;
2893 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2896 memset(&link, 0, sizeof(link));
2898 /* i40e uses full duplex only */
2899 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2900 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2901 ETH_LINK_SPEED_FIXED);
2903 if (!wait_to_complete && !enable_lse)
2904 update_link_reg(hw, &link);
2906 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2908 ret = rte_eth_linkstatus_set(dev, &link);
2909 i40e_notify_all_vfs_link_status(dev);
2914 /* Get all the statistics of a VSI */
2916 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2918 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2919 struct i40e_eth_stats *nes = &vsi->eth_stats;
2920 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2921 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2923 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2924 vsi->offset_loaded, &oes->rx_bytes,
2926 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2927 vsi->offset_loaded, &oes->rx_unicast,
2929 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2930 vsi->offset_loaded, &oes->rx_multicast,
2931 &nes->rx_multicast);
2932 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2933 vsi->offset_loaded, &oes->rx_broadcast,
2934 &nes->rx_broadcast);
2935 /* exclude CRC bytes */
2936 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2937 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2939 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2940 &oes->rx_discards, &nes->rx_discards);
2941 /* GLV_REPC not supported */
2942 /* GLV_RMPC not supported */
2943 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2944 &oes->rx_unknown_protocol,
2945 &nes->rx_unknown_protocol);
2946 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2947 vsi->offset_loaded, &oes->tx_bytes,
2949 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2950 vsi->offset_loaded, &oes->tx_unicast,
2952 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2953 vsi->offset_loaded, &oes->tx_multicast,
2954 &nes->tx_multicast);
2955 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2956 vsi->offset_loaded, &oes->tx_broadcast,
2957 &nes->tx_broadcast);
2958 /* GLV_TDPC not supported */
2959 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2960 &oes->tx_errors, &nes->tx_errors);
2961 vsi->offset_loaded = true;
2963 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2965 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2966 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2967 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2968 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2969 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2970 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2971 nes->rx_unknown_protocol);
2972 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2973 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2974 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2975 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2976 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2977 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2978 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2983 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2986 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2987 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2989 /* Get rx/tx bytes of internal transfer packets */
2990 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2991 I40E_GLV_GORCL(hw->port),
2993 &pf->internal_stats_offset.rx_bytes,
2994 &pf->internal_stats.rx_bytes);
2996 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2997 I40E_GLV_GOTCL(hw->port),
2999 &pf->internal_stats_offset.tx_bytes,
3000 &pf->internal_stats.tx_bytes);
3001 /* Get total internal rx packet count */
3002 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3003 I40E_GLV_UPRCL(hw->port),
3005 &pf->internal_stats_offset.rx_unicast,
3006 &pf->internal_stats.rx_unicast);
3007 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3008 I40E_GLV_MPRCL(hw->port),
3010 &pf->internal_stats_offset.rx_multicast,
3011 &pf->internal_stats.rx_multicast);
3012 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3013 I40E_GLV_BPRCL(hw->port),
3015 &pf->internal_stats_offset.rx_broadcast,
3016 &pf->internal_stats.rx_broadcast);
3017 /* Get total internal tx packet count */
3018 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3019 I40E_GLV_UPTCL(hw->port),
3021 &pf->internal_stats_offset.tx_unicast,
3022 &pf->internal_stats.tx_unicast);
3023 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3024 I40E_GLV_MPTCL(hw->port),
3026 &pf->internal_stats_offset.tx_multicast,
3027 &pf->internal_stats.tx_multicast);
3028 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3029 I40E_GLV_BPTCL(hw->port),
3031 &pf->internal_stats_offset.tx_broadcast,
3032 &pf->internal_stats.tx_broadcast);
3034 /* exclude CRC size */
3035 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3036 pf->internal_stats.rx_multicast +
3037 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3039 /* Get statistics of struct i40e_eth_stats */
3040 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3041 I40E_GLPRT_GORCL(hw->port),
3042 pf->offset_loaded, &os->eth.rx_bytes,
3044 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3045 I40E_GLPRT_UPRCL(hw->port),
3046 pf->offset_loaded, &os->eth.rx_unicast,
3047 &ns->eth.rx_unicast);
3048 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3049 I40E_GLPRT_MPRCL(hw->port),
3050 pf->offset_loaded, &os->eth.rx_multicast,
3051 &ns->eth.rx_multicast);
3052 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3053 I40E_GLPRT_BPRCL(hw->port),
3054 pf->offset_loaded, &os->eth.rx_broadcast,
3055 &ns->eth.rx_broadcast);
3056 /* Workaround: CRC size should not be included in byte statistics,
3057 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3060 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3061 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3063 /* exclude internal rx bytes
3064 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3065 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3067 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3069 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3070 ns->eth.rx_bytes = 0;
3072 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3074 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3075 ns->eth.rx_unicast = 0;
3077 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3079 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3080 ns->eth.rx_multicast = 0;
3082 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3084 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3085 ns->eth.rx_broadcast = 0;
3087 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3089 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3090 pf->offset_loaded, &os->eth.rx_discards,
3091 &ns->eth.rx_discards);
3092 /* GLPRT_REPC not supported */
3093 /* GLPRT_RMPC not supported */
3094 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3096 &os->eth.rx_unknown_protocol,
3097 &ns->eth.rx_unknown_protocol);
3098 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3099 I40E_GLPRT_GOTCL(hw->port),
3100 pf->offset_loaded, &os->eth.tx_bytes,
3102 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3103 I40E_GLPRT_UPTCL(hw->port),
3104 pf->offset_loaded, &os->eth.tx_unicast,
3105 &ns->eth.tx_unicast);
3106 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3107 I40E_GLPRT_MPTCL(hw->port),
3108 pf->offset_loaded, &os->eth.tx_multicast,
3109 &ns->eth.tx_multicast);
3110 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3111 I40E_GLPRT_BPTCL(hw->port),
3112 pf->offset_loaded, &os->eth.tx_broadcast,
3113 &ns->eth.tx_broadcast);
3114 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3115 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3117 /* exclude internal tx bytes
3118 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3119 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3121 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3123 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3124 ns->eth.tx_bytes = 0;
3126 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3128 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3129 ns->eth.tx_unicast = 0;
3131 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3133 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3134 ns->eth.tx_multicast = 0;
3136 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3138 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3139 ns->eth.tx_broadcast = 0;
3141 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3143 /* GLPRT_TEPC not supported */
3145 /* additional port specific stats */
3146 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3147 pf->offset_loaded, &os->tx_dropped_link_down,
3148 &ns->tx_dropped_link_down);
3149 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3150 pf->offset_loaded, &os->crc_errors,
3152 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3153 pf->offset_loaded, &os->illegal_bytes,
3154 &ns->illegal_bytes);
3155 /* GLPRT_ERRBC not supported */
3156 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3157 pf->offset_loaded, &os->mac_local_faults,
3158 &ns->mac_local_faults);
3159 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3160 pf->offset_loaded, &os->mac_remote_faults,
3161 &ns->mac_remote_faults);
3162 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3163 pf->offset_loaded, &os->rx_length_errors,
3164 &ns->rx_length_errors);
3165 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3166 pf->offset_loaded, &os->link_xon_rx,
3168 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3169 pf->offset_loaded, &os->link_xoff_rx,
3171 for (i = 0; i < 8; i++) {
3172 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3174 &os->priority_xon_rx[i],
3175 &ns->priority_xon_rx[i]);
3176 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3178 &os->priority_xoff_rx[i],
3179 &ns->priority_xoff_rx[i]);
3181 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3182 pf->offset_loaded, &os->link_xon_tx,
3184 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3185 pf->offset_loaded, &os->link_xoff_tx,
3187 for (i = 0; i < 8; i++) {
3188 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3190 &os->priority_xon_tx[i],
3191 &ns->priority_xon_tx[i]);
3192 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3194 &os->priority_xoff_tx[i],
3195 &ns->priority_xoff_tx[i]);
3196 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3198 &os->priority_xon_2_xoff[i],
3199 &ns->priority_xon_2_xoff[i]);
3201 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3202 I40E_GLPRT_PRC64L(hw->port),
3203 pf->offset_loaded, &os->rx_size_64,
3205 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3206 I40E_GLPRT_PRC127L(hw->port),
3207 pf->offset_loaded, &os->rx_size_127,
3209 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3210 I40E_GLPRT_PRC255L(hw->port),
3211 pf->offset_loaded, &os->rx_size_255,
3213 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3214 I40E_GLPRT_PRC511L(hw->port),
3215 pf->offset_loaded, &os->rx_size_511,
3217 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3218 I40E_GLPRT_PRC1023L(hw->port),
3219 pf->offset_loaded, &os->rx_size_1023,
3221 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3222 I40E_GLPRT_PRC1522L(hw->port),
3223 pf->offset_loaded, &os->rx_size_1522,
3225 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3226 I40E_GLPRT_PRC9522L(hw->port),
3227 pf->offset_loaded, &os->rx_size_big,
3229 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3230 pf->offset_loaded, &os->rx_undersize,
3232 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3233 pf->offset_loaded, &os->rx_fragments,
3235 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3236 pf->offset_loaded, &os->rx_oversize,
3238 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3239 pf->offset_loaded, &os->rx_jabber,
3241 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3242 I40E_GLPRT_PTC64L(hw->port),
3243 pf->offset_loaded, &os->tx_size_64,
3245 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3246 I40E_GLPRT_PTC127L(hw->port),
3247 pf->offset_loaded, &os->tx_size_127,
3249 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3250 I40E_GLPRT_PTC255L(hw->port),
3251 pf->offset_loaded, &os->tx_size_255,
3253 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3254 I40E_GLPRT_PTC511L(hw->port),
3255 pf->offset_loaded, &os->tx_size_511,
3257 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3258 I40E_GLPRT_PTC1023L(hw->port),
3259 pf->offset_loaded, &os->tx_size_1023,
3261 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3262 I40E_GLPRT_PTC1522L(hw->port),
3263 pf->offset_loaded, &os->tx_size_1522,
3265 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3266 I40E_GLPRT_PTC9522L(hw->port),
3267 pf->offset_loaded, &os->tx_size_big,
3269 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3271 &os->fd_sb_match, &ns->fd_sb_match);
3272 /* GLPRT_MSPDC not supported */
3273 /* GLPRT_XEC not supported */
3275 pf->offset_loaded = true;
3278 i40e_update_vsi_stats(pf->main_vsi);
3281 /* Get all statistics of a port */
3283 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3285 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3286 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3287 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3288 struct i40e_vsi *vsi;
3291 /* call read registers - updates values, now write them to struct */
3292 i40e_read_stats_registers(pf, hw);
3294 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3295 pf->main_vsi->eth_stats.rx_multicast +
3296 pf->main_vsi->eth_stats.rx_broadcast -
3297 pf->main_vsi->eth_stats.rx_discards;
3298 stats->opackets = ns->eth.tx_unicast +
3299 ns->eth.tx_multicast +
3300 ns->eth.tx_broadcast;
3301 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3302 stats->obytes = ns->eth.tx_bytes;
3303 stats->oerrors = ns->eth.tx_errors +
3304 pf->main_vsi->eth_stats.tx_errors;
3307 stats->imissed = ns->eth.rx_discards +
3308 pf->main_vsi->eth_stats.rx_discards;
3309 stats->ierrors = ns->crc_errors +
3310 ns->rx_length_errors + ns->rx_undersize +
3311 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3314 for (i = 0; i < pf->vf_num; i++) {
3315 vsi = pf->vfs[i].vsi;
3316 i40e_update_vsi_stats(vsi);
3318 stats->ipackets += (vsi->eth_stats.rx_unicast +
3319 vsi->eth_stats.rx_multicast +
3320 vsi->eth_stats.rx_broadcast -
3321 vsi->eth_stats.rx_discards);
3322 stats->ibytes += vsi->eth_stats.rx_bytes;
3323 stats->oerrors += vsi->eth_stats.tx_errors;
3324 stats->imissed += vsi->eth_stats.rx_discards;
3328 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3329 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3330 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3331 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3332 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3333 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3334 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3335 ns->eth.rx_unknown_protocol);
3336 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3337 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3338 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3339 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3340 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3341 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3343 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3344 ns->tx_dropped_link_down);
3345 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3346 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3348 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3349 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3350 ns->mac_local_faults);
3351 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3352 ns->mac_remote_faults);
3353 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3354 ns->rx_length_errors);
3355 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3356 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3357 for (i = 0; i < 8; i++) {
3358 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3359 i, ns->priority_xon_rx[i]);
3360 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3361 i, ns->priority_xoff_rx[i]);
3363 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3364 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3365 for (i = 0; i < 8; i++) {
3366 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3367 i, ns->priority_xon_tx[i]);
3368 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3369 i, ns->priority_xoff_tx[i]);
3370 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3371 i, ns->priority_xon_2_xoff[i]);
3373 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3374 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3375 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3376 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3377 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3378 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3379 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3380 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3381 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3382 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3383 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3384 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3385 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3386 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3387 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3388 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3389 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3390 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3391 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3392 ns->mac_short_packet_dropped);
3393 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3394 ns->checksum_error);
3395 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3396 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3400 /* Reset the statistics */
3402 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3404 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3405 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407 /* Mark PF and VSI stats to update the offset, aka "reset" */
3408 pf->offset_loaded = false;
3410 pf->main_vsi->offset_loaded = false;
3412 /* read the stats, reading current register values into offset */
3413 i40e_read_stats_registers(pf, hw);
3419 i40e_xstats_calc_num(void)
3421 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3422 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3423 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3426 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3427 struct rte_eth_xstat_name *xstats_names,
3428 __rte_unused unsigned limit)
3433 if (xstats_names == NULL)
3434 return i40e_xstats_calc_num();
3436 /* Note: limit checked in rte_eth_xstats_names() */
3438 /* Get stats from i40e_eth_stats struct */
3439 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3440 strlcpy(xstats_names[count].name,
3441 rte_i40e_stats_strings[i].name,
3442 sizeof(xstats_names[count].name));
3446 /* Get individiual stats from i40e_hw_port struct */
3447 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3448 strlcpy(xstats_names[count].name,
3449 rte_i40e_hw_port_strings[i].name,
3450 sizeof(xstats_names[count].name));
3454 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3455 for (prio = 0; prio < 8; prio++) {
3456 snprintf(xstats_names[count].name,
3457 sizeof(xstats_names[count].name),
3458 "rx_priority%u_%s", prio,
3459 rte_i40e_rxq_prio_strings[i].name);
3464 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3465 for (prio = 0; prio < 8; prio++) {
3466 snprintf(xstats_names[count].name,
3467 sizeof(xstats_names[count].name),
3468 "tx_priority%u_%s", prio,
3469 rte_i40e_txq_prio_strings[i].name);
3477 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3481 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3482 unsigned i, count, prio;
3483 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3485 count = i40e_xstats_calc_num();
3489 i40e_read_stats_registers(pf, hw);
3496 /* Get stats from i40e_eth_stats struct */
3497 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3498 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3499 rte_i40e_stats_strings[i].offset);
3500 xstats[count].id = count;
3504 /* Get individiual stats from i40e_hw_port struct */
3505 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3506 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3507 rte_i40e_hw_port_strings[i].offset);
3508 xstats[count].id = count;
3512 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3513 for (prio = 0; prio < 8; prio++) {
3514 xstats[count].value =
3515 *(uint64_t *)(((char *)hw_stats) +
3516 rte_i40e_rxq_prio_strings[i].offset +
3517 (sizeof(uint64_t) * prio));
3518 xstats[count].id = count;
3523 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3524 for (prio = 0; prio < 8; prio++) {
3525 xstats[count].value =
3526 *(uint64_t *)(((char *)hw_stats) +
3527 rte_i40e_txq_prio_strings[i].offset +
3528 (sizeof(uint64_t) * prio));
3529 xstats[count].id = count;
3538 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3540 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3546 full_ver = hw->nvm.oem_ver;
3547 ver = (u8)(full_ver >> 24);
3548 build = (u16)((full_ver >> 8) & 0xffff);
3549 patch = (u8)(full_ver & 0xff);
3551 ret = snprintf(fw_version, fw_size,
3552 "%d.%d%d 0x%08x %d.%d.%d",
3553 ((hw->nvm.version >> 12) & 0xf),
3554 ((hw->nvm.version >> 4) & 0xff),
3555 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3558 ret += 1; /* add the size of '\0' */
3559 if (fw_size < (u32)ret)
3566 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3567 * the Rx data path does not hang if the FW LLDP is stopped.
3568 * return true if lldp need to stop
3569 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3572 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3575 char ver_str[64] = {0};
3576 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578 i40e_fw_version_get(dev, ver_str, 64);
3579 nvm_ver = atof(ver_str);
3580 if ((hw->mac.type == I40E_MAC_X722 ||
3581 hw->mac.type == I40E_MAC_X722_VF) &&
3582 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3584 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3591 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3593 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 struct i40e_vsi *vsi = pf->main_vsi;
3596 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3598 dev_info->max_rx_queues = vsi->nb_qps;
3599 dev_info->max_tx_queues = vsi->nb_qps;
3600 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3601 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3602 dev_info->max_mac_addrs = vsi->max_macaddrs;
3603 dev_info->max_vfs = pci_dev->max_vfs;
3604 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3605 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3606 dev_info->rx_queue_offload_capa = 0;
3607 dev_info->rx_offload_capa =
3608 DEV_RX_OFFLOAD_VLAN_STRIP |
3609 DEV_RX_OFFLOAD_QINQ_STRIP |
3610 DEV_RX_OFFLOAD_IPV4_CKSUM |
3611 DEV_RX_OFFLOAD_UDP_CKSUM |
3612 DEV_RX_OFFLOAD_TCP_CKSUM |
3613 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3614 DEV_RX_OFFLOAD_KEEP_CRC |
3615 DEV_RX_OFFLOAD_SCATTER |
3616 DEV_RX_OFFLOAD_VLAN_EXTEND |
3617 DEV_RX_OFFLOAD_VLAN_FILTER |
3618 DEV_RX_OFFLOAD_JUMBO_FRAME |
3619 DEV_RX_OFFLOAD_RSS_HASH;
3621 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3622 dev_info->tx_offload_capa =
3623 DEV_TX_OFFLOAD_VLAN_INSERT |
3624 DEV_TX_OFFLOAD_QINQ_INSERT |
3625 DEV_TX_OFFLOAD_IPV4_CKSUM |
3626 DEV_TX_OFFLOAD_UDP_CKSUM |
3627 DEV_TX_OFFLOAD_TCP_CKSUM |
3628 DEV_TX_OFFLOAD_SCTP_CKSUM |
3629 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3630 DEV_TX_OFFLOAD_TCP_TSO |
3631 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3632 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3633 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3634 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3635 DEV_TX_OFFLOAD_MULTI_SEGS |
3636 dev_info->tx_queue_offload_capa;
3637 dev_info->dev_capa =
3638 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3639 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3641 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3643 dev_info->reta_size = pf->hash_lut_size;
3644 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3646 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3648 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3649 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3650 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3652 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3657 dev_info->default_txconf = (struct rte_eth_txconf) {
3659 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3660 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3661 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3663 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3664 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3668 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3669 .nb_max = I40E_MAX_RING_DESC,
3670 .nb_min = I40E_MIN_RING_DESC,
3671 .nb_align = I40E_ALIGN_RING_DESC,
3674 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3675 .nb_max = I40E_MAX_RING_DESC,
3676 .nb_min = I40E_MIN_RING_DESC,
3677 .nb_align = I40E_ALIGN_RING_DESC,
3678 .nb_seg_max = I40E_TX_MAX_SEG,
3679 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3682 if (pf->flags & I40E_FLAG_VMDQ) {
3683 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3684 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3685 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3686 pf->max_nb_vmdq_vsi;
3687 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3688 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3689 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3692 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3694 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3695 dev_info->default_rxportconf.nb_queues = 2;
3696 dev_info->default_txportconf.nb_queues = 2;
3697 if (dev->data->nb_rx_queues == 1)
3698 dev_info->default_rxportconf.ring_size = 2048;
3700 dev_info->default_rxportconf.ring_size = 1024;
3701 if (dev->data->nb_tx_queues == 1)
3702 dev_info->default_txportconf.ring_size = 1024;
3704 dev_info->default_txportconf.ring_size = 512;
3706 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3708 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3709 dev_info->default_rxportconf.nb_queues = 1;
3710 dev_info->default_txportconf.nb_queues = 1;
3711 dev_info->default_rxportconf.ring_size = 256;
3712 dev_info->default_txportconf.ring_size = 256;
3715 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3716 dev_info->default_rxportconf.nb_queues = 1;
3717 dev_info->default_txportconf.nb_queues = 1;
3718 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3719 dev_info->default_rxportconf.ring_size = 512;
3720 dev_info->default_txportconf.ring_size = 256;
3722 dev_info->default_rxportconf.ring_size = 256;
3723 dev_info->default_txportconf.ring_size = 256;
3726 dev_info->default_rxportconf.burst_size = 32;
3727 dev_info->default_txportconf.burst_size = 32;
3733 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3735 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3736 struct i40e_vsi *vsi = pf->main_vsi;
3737 PMD_INIT_FUNC_TRACE();
3740 return i40e_vsi_add_vlan(vsi, vlan_id);
3742 return i40e_vsi_delete_vlan(vsi, vlan_id);
3746 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3747 enum rte_vlan_type vlan_type,
3748 uint16_t tpid, int qinq)
3750 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3753 uint16_t reg_id = 3;
3757 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3761 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3763 if (ret != I40E_SUCCESS) {
3765 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3770 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3773 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3774 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3775 if (reg_r == reg_w) {
3776 PMD_DRV_LOG(DEBUG, "No need to write");
3780 ret = i40e_aq_debug_write_global_register(hw,
3781 I40E_GL_SWT_L2TAGCTRL(reg_id),
3783 if (ret != I40E_SUCCESS) {
3785 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3790 "Global register 0x%08x is changed with value 0x%08x",
3791 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3797 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3798 enum rte_vlan_type vlan_type,
3801 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3803 int qinq = dev->data->dev_conf.rxmode.offloads &
3804 DEV_RX_OFFLOAD_VLAN_EXTEND;
3807 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3808 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3809 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3811 "Unsupported vlan type.");
3815 if (pf->support_multi_driver) {
3816 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3820 /* 802.1ad frames ability is added in NVM API 1.7*/
3821 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3823 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3824 hw->first_tag = rte_cpu_to_le_16(tpid);
3825 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3826 hw->second_tag = rte_cpu_to_le_16(tpid);
3828 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3829 hw->second_tag = rte_cpu_to_le_16(tpid);
3831 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3832 if (ret != I40E_SUCCESS) {
3834 "Set switch config failed aq_err: %d",
3835 hw->aq.asq_last_status);
3839 /* If NVM API < 1.7, keep the register setting */
3840 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3847 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3850 struct i40e_vsi *vsi = pf->main_vsi;
3851 struct rte_eth_rxmode *rxmode;
3853 if (mask & ETH_QINQ_STRIP_MASK) {
3854 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3858 rxmode = &dev->data->dev_conf.rxmode;
3859 if (mask & ETH_VLAN_FILTER_MASK) {
3860 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3861 i40e_vsi_config_vlan_filter(vsi, TRUE);
3863 i40e_vsi_config_vlan_filter(vsi, FALSE);
3866 if (mask & ETH_VLAN_STRIP_MASK) {
3867 /* Enable or disable VLAN stripping */
3868 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3869 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3871 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3874 if (mask & ETH_VLAN_EXTEND_MASK) {
3875 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3876 i40e_vsi_config_double_vlan(vsi, TRUE);
3877 /* Set global registers with default ethertype. */
3878 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3879 RTE_ETHER_TYPE_VLAN);
3880 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3881 RTE_ETHER_TYPE_VLAN);
3884 i40e_vsi_config_double_vlan(vsi, FALSE);
3891 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3892 __rte_unused uint16_t queue,
3893 __rte_unused int on)
3895 PMD_INIT_FUNC_TRACE();
3899 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3901 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3902 struct i40e_vsi *vsi = pf->main_vsi;
3903 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3904 struct i40e_vsi_vlan_pvid_info info;
3906 memset(&info, 0, sizeof(info));
3909 info.config.pvid = pvid;
3911 info.config.reject.tagged =
3912 data->dev_conf.txmode.hw_vlan_reject_tagged;
3913 info.config.reject.untagged =
3914 data->dev_conf.txmode.hw_vlan_reject_untagged;
3917 return i40e_vsi_vlan_pvid_set(vsi, &info);
3921 i40e_dev_led_on(struct rte_eth_dev *dev)
3923 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3924 uint32_t mode = i40e_led_get(hw);
3927 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3933 i40e_dev_led_off(struct rte_eth_dev *dev)
3935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3936 uint32_t mode = i40e_led_get(hw);
3939 i40e_led_set(hw, 0, false);
3945 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3947 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3948 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3950 fc_conf->pause_time = pf->fc_conf.pause_time;
3952 /* read out from register, in case they are modified by other port */
3953 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3954 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3955 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3956 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3958 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3959 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3961 /* Return current mode according to actual setting*/
3962 switch (hw->fc.current_mode) {
3964 fc_conf->mode = RTE_FC_FULL;
3966 case I40E_FC_TX_PAUSE:
3967 fc_conf->mode = RTE_FC_TX_PAUSE;
3969 case I40E_FC_RX_PAUSE:
3970 fc_conf->mode = RTE_FC_RX_PAUSE;
3974 fc_conf->mode = RTE_FC_NONE;
3981 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3983 uint32_t mflcn_reg, fctrl_reg, reg;
3984 uint32_t max_high_water;
3985 uint8_t i, aq_failure;
3989 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3990 [RTE_FC_NONE] = I40E_FC_NONE,
3991 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3992 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3993 [RTE_FC_FULL] = I40E_FC_FULL
3996 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3998 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3999 if ((fc_conf->high_water > max_high_water) ||
4000 (fc_conf->high_water < fc_conf->low_water)) {
4002 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4007 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4009 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4011 pf->fc_conf.pause_time = fc_conf->pause_time;
4012 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4013 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4015 PMD_INIT_FUNC_TRACE();
4017 /* All the link flow control related enable/disable register
4018 * configuration is handle by the F/W
4020 err = i40e_set_fc(hw, &aq_failure, true);
4024 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4025 /* Configure flow control refresh threshold,
4026 * the value for stat_tx_pause_refresh_timer[8]
4027 * is used for global pause operation.
4031 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4032 pf->fc_conf.pause_time);
4034 /* configure the timer value included in transmitted pause
4036 * the value for stat_tx_pause_quanta[8] is used for global
4039 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4040 pf->fc_conf.pause_time);
4042 fctrl_reg = I40E_READ_REG(hw,
4043 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4045 if (fc_conf->mac_ctrl_frame_fwd != 0)
4046 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4048 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4050 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4053 /* Configure pause time (2 TCs per register) */
4054 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4055 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4056 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4058 /* Configure flow control refresh threshold value */
4059 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4060 pf->fc_conf.pause_time / 2);
4062 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4064 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4065 *depending on configuration
4067 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4068 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4069 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4071 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4072 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4075 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4078 if (!pf->support_multi_driver) {
4079 /* config water marker both based on the packets and bytes */
4080 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4081 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4082 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4083 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4084 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4085 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4086 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4087 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4089 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4090 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4094 "Water marker configuration is not supported.");
4097 I40E_WRITE_FLUSH(hw);
4103 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4104 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4106 PMD_INIT_FUNC_TRACE();
4111 /* Add a MAC address, and update filters */
4113 i40e_macaddr_add(struct rte_eth_dev *dev,
4114 struct rte_ether_addr *mac_addr,
4115 __rte_unused uint32_t index,
4118 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4119 struct i40e_mac_filter_info mac_filter;
4120 struct i40e_vsi *vsi;
4121 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4124 /* If VMDQ not enabled or configured, return */
4125 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4126 !pf->nb_cfg_vmdq_vsi)) {
4127 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4128 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4133 if (pool > pf->nb_cfg_vmdq_vsi) {
4134 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4135 pool, pf->nb_cfg_vmdq_vsi);
4139 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4140 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4141 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4143 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4148 vsi = pf->vmdq[pool - 1].vsi;
4150 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4151 if (ret != I40E_SUCCESS) {
4152 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4158 /* Remove a MAC address, and update filters */
4160 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4162 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4163 struct i40e_vsi *vsi;
4164 struct rte_eth_dev_data *data = dev->data;
4165 struct rte_ether_addr *macaddr;
4170 macaddr = &(data->mac_addrs[index]);
4172 pool_sel = dev->data->mac_pool_sel[index];
4174 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4175 if (pool_sel & (1ULL << i)) {
4179 /* No VMDQ pool enabled or configured */
4180 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4181 (i > pf->nb_cfg_vmdq_vsi)) {
4183 "No VMDQ pool enabled/configured");
4186 vsi = pf->vmdq[i - 1].vsi;
4188 ret = i40e_vsi_delete_mac(vsi, macaddr);
4191 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4198 /* Set perfect match or hash match of MAC and VLAN for a VF */
4200 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4201 struct rte_eth_mac_filter *filter,
4205 struct i40e_mac_filter_info mac_filter;
4206 struct rte_ether_addr old_mac;
4207 struct rte_ether_addr *new_mac;
4208 struct i40e_pf_vf *vf = NULL;
4213 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4216 hw = I40E_PF_TO_HW(pf);
4218 if (filter == NULL) {
4219 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4223 new_mac = &filter->mac_addr;
4225 if (rte_is_zero_ether_addr(new_mac)) {
4226 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4230 vf_id = filter->dst_id;
4232 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4233 PMD_DRV_LOG(ERR, "Invalid argument.");
4236 vf = &pf->vfs[vf_id];
4238 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4239 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4244 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4245 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4246 RTE_ETHER_ADDR_LEN);
4247 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4248 RTE_ETHER_ADDR_LEN);
4250 mac_filter.filter_type = filter->filter_type;
4251 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4252 if (ret != I40E_SUCCESS) {
4253 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4256 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4258 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4259 RTE_ETHER_ADDR_LEN);
4260 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4261 if (ret != I40E_SUCCESS) {
4262 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4266 /* Clear device address as it has been removed */
4267 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4268 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4274 /* MAC filter handle */
4276 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4280 struct rte_eth_mac_filter *filter;
4281 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4282 int ret = I40E_NOT_SUPPORTED;
4284 filter = (struct rte_eth_mac_filter *)(arg);
4286 switch (filter_op) {
4287 case RTE_ETH_FILTER_NOP:
4290 case RTE_ETH_FILTER_ADD:
4291 i40e_pf_disable_irq0(hw);
4293 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4294 i40e_pf_enable_irq0(hw);
4296 case RTE_ETH_FILTER_DELETE:
4297 i40e_pf_disable_irq0(hw);
4299 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4300 i40e_pf_enable_irq0(hw);
4303 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4304 ret = I40E_ERR_PARAM;
4312 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4314 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4315 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4322 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4323 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4324 vsi->type != I40E_VSI_SRIOV,
4327 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4331 uint32_t *lut_dw = (uint32_t *)lut;
4332 uint16_t i, lut_size_dw = lut_size / 4;
4334 if (vsi->type == I40E_VSI_SRIOV) {
4335 for (i = 0; i <= lut_size_dw; i++) {
4336 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4337 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4340 for (i = 0; i < lut_size_dw; i++)
4341 lut_dw[i] = I40E_READ_REG(hw,
4350 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4359 pf = I40E_VSI_TO_PF(vsi);
4360 hw = I40E_VSI_TO_HW(vsi);
4362 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4363 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4364 vsi->type != I40E_VSI_SRIOV,
4367 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4371 uint32_t *lut_dw = (uint32_t *)lut;
4372 uint16_t i, lut_size_dw = lut_size / 4;
4374 if (vsi->type == I40E_VSI_SRIOV) {
4375 for (i = 0; i < lut_size_dw; i++)
4378 I40E_VFQF_HLUT1(i, vsi->user_param),
4381 for (i = 0; i < lut_size_dw; i++)
4382 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4385 I40E_WRITE_FLUSH(hw);
4392 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4393 struct rte_eth_rss_reta_entry64 *reta_conf,
4396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4397 uint16_t i, lut_size = pf->hash_lut_size;
4398 uint16_t idx, shift;
4402 if (reta_size != lut_size ||
4403 reta_size > ETH_RSS_RETA_SIZE_512) {
4405 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4406 reta_size, lut_size);
4410 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4412 PMD_DRV_LOG(ERR, "No memory can be allocated");
4415 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4418 for (i = 0; i < reta_size; i++) {
4419 idx = i / RTE_RETA_GROUP_SIZE;
4420 shift = i % RTE_RETA_GROUP_SIZE;
4421 if (reta_conf[idx].mask & (1ULL << shift))
4422 lut[i] = reta_conf[idx].reta[shift];
4424 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4426 pf->adapter->rss_reta_updated = 1;
4435 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4436 struct rte_eth_rss_reta_entry64 *reta_conf,
4439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4440 uint16_t i, lut_size = pf->hash_lut_size;
4441 uint16_t idx, shift;
4445 if (reta_size != lut_size ||
4446 reta_size > ETH_RSS_RETA_SIZE_512) {
4448 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4449 reta_size, lut_size);
4453 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4455 PMD_DRV_LOG(ERR, "No memory can be allocated");
4459 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4462 for (i = 0; i < reta_size; i++) {
4463 idx = i / RTE_RETA_GROUP_SIZE;
4464 shift = i % RTE_RETA_GROUP_SIZE;
4465 if (reta_conf[idx].mask & (1ULL << shift))
4466 reta_conf[idx].reta[shift] = lut[i];
4476 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4477 * @hw: pointer to the HW structure
4478 * @mem: pointer to mem struct to fill out
4479 * @size: size of memory requested
4480 * @alignment: what to align the allocation to
4482 enum i40e_status_code
4483 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4484 struct i40e_dma_mem *mem,
4488 const struct rte_memzone *mz = NULL;
4489 char z_name[RTE_MEMZONE_NAMESIZE];
4492 return I40E_ERR_PARAM;
4494 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4495 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4496 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4498 return I40E_ERR_NO_MEMORY;
4503 mem->zone = (const void *)mz;
4505 "memzone %s allocated with physical address: %"PRIu64,
4508 return I40E_SUCCESS;
4512 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4513 * @hw: pointer to the HW structure
4514 * @mem: ptr to mem struct to free
4516 enum i40e_status_code
4517 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4518 struct i40e_dma_mem *mem)
4521 return I40E_ERR_PARAM;
4524 "memzone %s to be freed with physical address: %"PRIu64,
4525 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4526 rte_memzone_free((const struct rte_memzone *)mem->zone);
4531 return I40E_SUCCESS;
4535 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4536 * @hw: pointer to the HW structure
4537 * @mem: pointer to mem struct to fill out
4538 * @size: size of memory requested
4540 enum i40e_status_code
4541 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4542 struct i40e_virt_mem *mem,
4546 return I40E_ERR_PARAM;
4549 mem->va = rte_zmalloc("i40e", size, 0);
4552 return I40E_SUCCESS;
4554 return I40E_ERR_NO_MEMORY;
4558 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4559 * @hw: pointer to the HW structure
4560 * @mem: pointer to mem struct to free
4562 enum i40e_status_code
4563 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4564 struct i40e_virt_mem *mem)
4567 return I40E_ERR_PARAM;
4572 return I40E_SUCCESS;
4576 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4578 rte_spinlock_init(&sp->spinlock);
4582 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4584 rte_spinlock_lock(&sp->spinlock);
4588 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4590 rte_spinlock_unlock(&sp->spinlock);
4594 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4600 * Get the hardware capabilities, which will be parsed
4601 * and saved into struct i40e_hw.
4604 i40e_get_cap(struct i40e_hw *hw)
4606 struct i40e_aqc_list_capabilities_element_resp *buf;
4607 uint16_t len, size = 0;
4610 /* Calculate a huge enough buff for saving response data temporarily */
4611 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4612 I40E_MAX_CAP_ELE_NUM;
4613 buf = rte_zmalloc("i40e", len, 0);
4615 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4616 return I40E_ERR_NO_MEMORY;
4619 /* Get, parse the capabilities and save it to hw */
4620 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4621 i40e_aqc_opc_list_func_capabilities, NULL);
4622 if (ret != I40E_SUCCESS)
4623 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4625 /* Free the temporary buffer after being used */
4631 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4633 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4641 pf = (struct i40e_pf *)opaque;
4645 num = strtoul(value, &end, 0);
4646 if (errno != 0 || end == value || *end != 0) {
4647 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4648 "kept the value = %hu", value, pf->vf_nb_qp_max);
4652 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4653 pf->vf_nb_qp_max = (uint16_t)num;
4655 /* here return 0 to make next valid same argument work */
4656 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4657 "power of 2 and equal or less than 16 !, Now it is "
4658 "kept the value = %hu", num, pf->vf_nb_qp_max);
4663 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4666 struct rte_kvargs *kvlist;
4669 /* set default queue number per VF as 4 */
4670 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4672 if (dev->device->devargs == NULL)
4675 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4679 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4680 if (!kvargs_count) {
4681 rte_kvargs_free(kvlist);
4685 if (kvargs_count > 1)
4686 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4687 "the first invalid or last valid one is used !",
4688 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4690 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4691 i40e_pf_parse_vf_queue_number_handler, pf);
4693 rte_kvargs_free(kvlist);
4699 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4701 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4702 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4703 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4704 uint16_t qp_count = 0, vsi_count = 0;
4706 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4707 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4711 i40e_pf_config_vf_rxq_number(dev);
4713 /* Add the parameter init for LFC */
4714 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4715 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4716 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4718 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4719 pf->max_num_vsi = hw->func_caps.num_vsis;
4720 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4721 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4723 /* FDir queue/VSI allocation */
4724 pf->fdir_qp_offset = 0;
4725 if (hw->func_caps.fd) {
4726 pf->flags |= I40E_FLAG_FDIR;
4727 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4729 pf->fdir_nb_qps = 0;
4731 qp_count += pf->fdir_nb_qps;
4734 /* LAN queue/VSI allocation */
4735 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4736 if (!hw->func_caps.rss) {
4739 pf->flags |= I40E_FLAG_RSS;
4740 if (hw->mac.type == I40E_MAC_X722)
4741 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4742 pf->lan_nb_qps = pf->lan_nb_qp_max;
4744 qp_count += pf->lan_nb_qps;
4747 /* VF queue/VSI allocation */
4748 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4749 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4750 pf->flags |= I40E_FLAG_SRIOV;
4751 pf->vf_nb_qps = pf->vf_nb_qp_max;
4752 pf->vf_num = pci_dev->max_vfs;
4754 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4755 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4760 qp_count += pf->vf_nb_qps * pf->vf_num;
4761 vsi_count += pf->vf_num;
4763 /* VMDq queue/VSI allocation */
4764 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4765 pf->vmdq_nb_qps = 0;
4766 pf->max_nb_vmdq_vsi = 0;
4767 if (hw->func_caps.vmdq) {
4768 if (qp_count < hw->func_caps.num_tx_qp &&
4769 vsi_count < hw->func_caps.num_vsis) {
4770 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4771 qp_count) / pf->vmdq_nb_qp_max;
4773 /* Limit the maximum number of VMDq vsi to the maximum
4774 * ethdev can support
4776 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4777 hw->func_caps.num_vsis - vsi_count);
4778 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4780 if (pf->max_nb_vmdq_vsi) {
4781 pf->flags |= I40E_FLAG_VMDQ;
4782 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4784 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4785 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4786 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4789 "No enough queues left for VMDq");
4792 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4795 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4796 vsi_count += pf->max_nb_vmdq_vsi;
4798 if (hw->func_caps.dcb)
4799 pf->flags |= I40E_FLAG_DCB;
4801 if (qp_count > hw->func_caps.num_tx_qp) {
4803 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4804 qp_count, hw->func_caps.num_tx_qp);
4807 if (vsi_count > hw->func_caps.num_vsis) {
4809 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4810 vsi_count, hw->func_caps.num_vsis);
4818 i40e_pf_get_switch_config(struct i40e_pf *pf)
4820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4821 struct i40e_aqc_get_switch_config_resp *switch_config;
4822 struct i40e_aqc_switch_config_element_resp *element;
4823 uint16_t start_seid = 0, num_reported;
4826 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4827 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4828 if (!switch_config) {
4829 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4833 /* Get the switch configurations */
4834 ret = i40e_aq_get_switch_config(hw, switch_config,
4835 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4836 if (ret != I40E_SUCCESS) {
4837 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4840 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4841 if (num_reported != 1) { /* The number should be 1 */
4842 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4846 /* Parse the switch configuration elements */
4847 element = &(switch_config->element[0]);
4848 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4849 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4850 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4852 PMD_DRV_LOG(INFO, "Unknown element type");
4855 rte_free(switch_config);
4861 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4864 struct pool_entry *entry;
4866 if (pool == NULL || num == 0)
4869 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4870 if (entry == NULL) {
4871 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4875 /* queue heap initialize */
4876 pool->num_free = num;
4877 pool->num_alloc = 0;
4879 LIST_INIT(&pool->alloc_list);
4880 LIST_INIT(&pool->free_list);
4882 /* Initialize element */
4886 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4891 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4893 struct pool_entry *entry, *next_entry;
4898 for (entry = LIST_FIRST(&pool->alloc_list);
4899 entry && (next_entry = LIST_NEXT(entry, next), 1);
4900 entry = next_entry) {
4901 LIST_REMOVE(entry, next);
4905 for (entry = LIST_FIRST(&pool->free_list);
4906 entry && (next_entry = LIST_NEXT(entry, next), 1);
4907 entry = next_entry) {
4908 LIST_REMOVE(entry, next);
4913 pool->num_alloc = 0;
4915 LIST_INIT(&pool->alloc_list);
4916 LIST_INIT(&pool->free_list);
4920 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4923 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4924 uint32_t pool_offset;
4928 PMD_DRV_LOG(ERR, "Invalid parameter");
4932 pool_offset = base - pool->base;
4933 /* Lookup in alloc list */
4934 LIST_FOREACH(entry, &pool->alloc_list, next) {
4935 if (entry->base == pool_offset) {
4936 valid_entry = entry;
4937 LIST_REMOVE(entry, next);
4942 /* Not find, return */
4943 if (valid_entry == NULL) {
4944 PMD_DRV_LOG(ERR, "Failed to find entry");
4949 * Found it, move it to free list and try to merge.
4950 * In order to make merge easier, always sort it by qbase.
4951 * Find adjacent prev and last entries.
4954 LIST_FOREACH(entry, &pool->free_list, next) {
4955 if (entry->base > valid_entry->base) {
4963 /* Try to merge with next one*/
4965 /* Merge with next one */
4966 if (valid_entry->base + valid_entry->len == next->base) {
4967 next->base = valid_entry->base;
4968 next->len += valid_entry->len;
4969 rte_free(valid_entry);
4976 /* Merge with previous one */
4977 if (prev->base + prev->len == valid_entry->base) {
4978 prev->len += valid_entry->len;
4979 /* If it merge with next one, remove next node */
4981 LIST_REMOVE(valid_entry, next);
4982 rte_free(valid_entry);
4984 rte_free(valid_entry);
4990 /* Not find any entry to merge, insert */
4993 LIST_INSERT_AFTER(prev, valid_entry, next);
4994 else if (next != NULL)
4995 LIST_INSERT_BEFORE(next, valid_entry, next);
4996 else /* It's empty list, insert to head */
4997 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5000 pool->num_free += valid_entry->len;
5001 pool->num_alloc -= valid_entry->len;
5007 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5010 struct pool_entry *entry, *valid_entry;
5012 if (pool == NULL || num == 0) {
5013 PMD_DRV_LOG(ERR, "Invalid parameter");
5017 if (pool->num_free < num) {
5018 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5019 num, pool->num_free);
5024 /* Lookup in free list and find most fit one */
5025 LIST_FOREACH(entry, &pool->free_list, next) {
5026 if (entry->len >= num) {
5028 if (entry->len == num) {
5029 valid_entry = entry;
5032 if (valid_entry == NULL || valid_entry->len > entry->len)
5033 valid_entry = entry;
5037 /* Not find one to satisfy the request, return */
5038 if (valid_entry == NULL) {
5039 PMD_DRV_LOG(ERR, "No valid entry found");
5043 * The entry have equal queue number as requested,
5044 * remove it from alloc_list.
5046 if (valid_entry->len == num) {
5047 LIST_REMOVE(valid_entry, next);
5050 * The entry have more numbers than requested,
5051 * create a new entry for alloc_list and minus its
5052 * queue base and number in free_list.
5054 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5055 if (entry == NULL) {
5057 "Failed to allocate memory for resource pool");
5060 entry->base = valid_entry->base;
5062 valid_entry->base += num;
5063 valid_entry->len -= num;
5064 valid_entry = entry;
5067 /* Insert it into alloc list, not sorted */
5068 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5070 pool->num_free -= valid_entry->len;
5071 pool->num_alloc += valid_entry->len;
5073 return valid_entry->base + pool->base;
5077 * bitmap_is_subset - Check whether src2 is subset of src1
5080 bitmap_is_subset(uint8_t src1, uint8_t src2)
5082 return !((src1 ^ src2) & src2);
5085 static enum i40e_status_code
5086 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5088 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5090 /* If DCB is not supported, only default TC is supported */
5091 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5092 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5093 return I40E_NOT_SUPPORTED;
5096 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5098 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5099 hw->func_caps.enabled_tcmap, enabled_tcmap);
5100 return I40E_NOT_SUPPORTED;
5102 return I40E_SUCCESS;
5106 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5107 struct i40e_vsi_vlan_pvid_info *info)
5110 struct i40e_vsi_context ctxt;
5111 uint8_t vlan_flags = 0;
5114 if (vsi == NULL || info == NULL) {
5115 PMD_DRV_LOG(ERR, "invalid parameters");
5116 return I40E_ERR_PARAM;
5120 vsi->info.pvid = info->config.pvid;
5122 * If insert pvid is enabled, only tagged pkts are
5123 * allowed to be sent out.
5125 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5126 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5129 if (info->config.reject.tagged == 0)
5130 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5132 if (info->config.reject.untagged == 0)
5133 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5135 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5136 I40E_AQ_VSI_PVLAN_MODE_MASK);
5137 vsi->info.port_vlan_flags |= vlan_flags;
5138 vsi->info.valid_sections =
5139 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5140 memset(&ctxt, 0, sizeof(ctxt));
5141 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5142 ctxt.seid = vsi->seid;
5144 hw = I40E_VSI_TO_HW(vsi);
5145 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5146 if (ret != I40E_SUCCESS)
5147 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5153 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5155 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5157 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5159 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5160 if (ret != I40E_SUCCESS)
5164 PMD_DRV_LOG(ERR, "seid not valid");
5168 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5169 tc_bw_data.tc_valid_bits = enabled_tcmap;
5170 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5171 tc_bw_data.tc_bw_credits[i] =
5172 (enabled_tcmap & (1 << i)) ? 1 : 0;
5174 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5175 if (ret != I40E_SUCCESS) {
5176 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5180 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5181 sizeof(vsi->info.qs_handle));
5182 return I40E_SUCCESS;
5185 static enum i40e_status_code
5186 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5187 struct i40e_aqc_vsi_properties_data *info,
5188 uint8_t enabled_tcmap)
5190 enum i40e_status_code ret;
5191 int i, total_tc = 0;
5192 uint16_t qpnum_per_tc, bsf, qp_idx;
5194 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5195 if (ret != I40E_SUCCESS)
5198 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5199 if (enabled_tcmap & (1 << i))
5203 vsi->enabled_tc = enabled_tcmap;
5205 /* Number of queues per enabled TC */
5206 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5207 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5208 bsf = rte_bsf32(qpnum_per_tc);
5210 /* Adjust the queue number to actual queues that can be applied */
5211 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5212 vsi->nb_qps = qpnum_per_tc * total_tc;
5215 * Configure TC and queue mapping parameters, for enabled TC,
5216 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5217 * default queue will serve it.
5220 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5221 if (vsi->enabled_tc & (1 << i)) {
5222 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5223 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5224 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5225 qp_idx += qpnum_per_tc;
5227 info->tc_mapping[i] = 0;
5230 /* Associate queue number with VSI */
5231 if (vsi->type == I40E_VSI_SRIOV) {
5232 info->mapping_flags |=
5233 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5234 for (i = 0; i < vsi->nb_qps; i++)
5235 info->queue_mapping[i] =
5236 rte_cpu_to_le_16(vsi->base_queue + i);
5238 info->mapping_flags |=
5239 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5240 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5242 info->valid_sections |=
5243 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5245 return I40E_SUCCESS;
5249 i40e_veb_release(struct i40e_veb *veb)
5251 struct i40e_vsi *vsi;
5257 if (!TAILQ_EMPTY(&veb->head)) {
5258 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5261 /* associate_vsi field is NULL for floating VEB */
5262 if (veb->associate_vsi != NULL) {
5263 vsi = veb->associate_vsi;
5264 hw = I40E_VSI_TO_HW(vsi);
5266 vsi->uplink_seid = veb->uplink_seid;
5269 veb->associate_pf->main_vsi->floating_veb = NULL;
5270 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5273 i40e_aq_delete_element(hw, veb->seid, NULL);
5275 return I40E_SUCCESS;
5279 static struct i40e_veb *
5280 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5282 struct i40e_veb *veb;
5288 "veb setup failed, associated PF shouldn't null");
5291 hw = I40E_PF_TO_HW(pf);
5293 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5295 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5299 veb->associate_vsi = vsi;
5300 veb->associate_pf = pf;
5301 TAILQ_INIT(&veb->head);
5302 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5304 /* create floating veb if vsi is NULL */
5306 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5307 I40E_DEFAULT_TCMAP, false,
5308 &veb->seid, false, NULL);
5310 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5311 true, &veb->seid, false, NULL);
5314 if (ret != I40E_SUCCESS) {
5315 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5316 hw->aq.asq_last_status);
5319 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5321 /* get statistics index */
5322 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5323 &veb->stats_idx, NULL, NULL, NULL);
5324 if (ret != I40E_SUCCESS) {
5325 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5326 hw->aq.asq_last_status);
5329 /* Get VEB bandwidth, to be implemented */
5330 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5332 vsi->uplink_seid = veb->seid;
5341 i40e_vsi_release(struct i40e_vsi *vsi)
5345 struct i40e_vsi_list *vsi_list;
5348 struct i40e_mac_filter *f;
5349 uint16_t user_param;
5352 return I40E_SUCCESS;
5357 user_param = vsi->user_param;
5359 pf = I40E_VSI_TO_PF(vsi);
5360 hw = I40E_VSI_TO_HW(vsi);
5362 /* VSI has child to attach, release child first */
5364 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5365 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5368 i40e_veb_release(vsi->veb);
5371 if (vsi->floating_veb) {
5372 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5373 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5378 /* Remove all macvlan filters of the VSI */
5379 i40e_vsi_remove_all_macvlan_filter(vsi);
5380 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5383 if (vsi->type != I40E_VSI_MAIN &&
5384 ((vsi->type != I40E_VSI_SRIOV) ||
5385 !pf->floating_veb_list[user_param])) {
5386 /* Remove vsi from parent's sibling list */
5387 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5388 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5389 return I40E_ERR_PARAM;
5391 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5392 &vsi->sib_vsi_list, list);
5394 /* Remove all switch element of the VSI */
5395 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5396 if (ret != I40E_SUCCESS)
5397 PMD_DRV_LOG(ERR, "Failed to delete element");
5400 if ((vsi->type == I40E_VSI_SRIOV) &&
5401 pf->floating_veb_list[user_param]) {
5402 /* Remove vsi from parent's sibling list */
5403 if (vsi->parent_vsi == NULL ||
5404 vsi->parent_vsi->floating_veb == NULL) {
5405 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5406 return I40E_ERR_PARAM;
5408 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5409 &vsi->sib_vsi_list, list);
5411 /* Remove all switch element of the VSI */
5412 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5413 if (ret != I40E_SUCCESS)
5414 PMD_DRV_LOG(ERR, "Failed to delete element");
5417 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5419 if (vsi->type != I40E_VSI_SRIOV)
5420 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5423 return I40E_SUCCESS;
5427 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5429 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5430 struct i40e_aqc_remove_macvlan_element_data def_filter;
5431 struct i40e_mac_filter_info filter;
5434 if (vsi->type != I40E_VSI_MAIN)
5435 return I40E_ERR_CONFIG;
5436 memset(&def_filter, 0, sizeof(def_filter));
5437 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5439 def_filter.vlan_tag = 0;
5440 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5441 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5442 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5443 if (ret != I40E_SUCCESS) {
5444 struct i40e_mac_filter *f;
5445 struct rte_ether_addr *mac;
5448 "Cannot remove the default macvlan filter");
5449 /* It needs to add the permanent mac into mac list */
5450 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5452 PMD_DRV_LOG(ERR, "failed to allocate memory");
5453 return I40E_ERR_NO_MEMORY;
5455 mac = &f->mac_info.mac_addr;
5456 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5458 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5459 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5464 rte_memcpy(&filter.mac_addr,
5465 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5466 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5467 return i40e_vsi_add_mac(vsi, &filter);
5471 * i40e_vsi_get_bw_config - Query VSI BW Information
5472 * @vsi: the VSI to be queried
5474 * Returns 0 on success, negative value on failure
5476 static enum i40e_status_code
5477 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5479 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5480 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5481 struct i40e_hw *hw = &vsi->adapter->hw;
5486 memset(&bw_config, 0, sizeof(bw_config));
5487 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5488 if (ret != I40E_SUCCESS) {
5489 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5490 hw->aq.asq_last_status);
5494 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5495 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5496 &ets_sla_config, NULL);
5497 if (ret != I40E_SUCCESS) {
5499 "VSI failed to get TC bandwdith configuration %u",
5500 hw->aq.asq_last_status);
5504 /* store and print out BW info */
5505 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5506 vsi->bw_info.bw_max = bw_config.max_bw;
5507 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5508 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5509 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5510 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5512 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5513 vsi->bw_info.bw_ets_share_credits[i] =
5514 ets_sla_config.share_credits[i];
5515 vsi->bw_info.bw_ets_credits[i] =
5516 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5517 /* 4 bits per TC, 4th bit is reserved */
5518 vsi->bw_info.bw_ets_max[i] =
5519 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5520 RTE_LEN2MASK(3, uint8_t));
5521 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5522 vsi->bw_info.bw_ets_share_credits[i]);
5523 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5524 vsi->bw_info.bw_ets_credits[i]);
5525 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5526 vsi->bw_info.bw_ets_max[i]);
5529 return I40E_SUCCESS;
5532 /* i40e_enable_pf_lb
5533 * @pf: pointer to the pf structure
5535 * allow loopback on pf
5538 i40e_enable_pf_lb(struct i40e_pf *pf)
5540 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5541 struct i40e_vsi_context ctxt;
5544 /* Use the FW API if FW >= v5.0 */
5545 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5546 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5550 memset(&ctxt, 0, sizeof(ctxt));
5551 ctxt.seid = pf->main_vsi_seid;
5552 ctxt.pf_num = hw->pf_id;
5553 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5555 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5556 ret, hw->aq.asq_last_status);
5559 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5560 ctxt.info.valid_sections =
5561 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5562 ctxt.info.switch_id |=
5563 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5565 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5567 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5568 hw->aq.asq_last_status);
5573 i40e_vsi_setup(struct i40e_pf *pf,
5574 enum i40e_vsi_type type,
5575 struct i40e_vsi *uplink_vsi,
5576 uint16_t user_param)
5578 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5579 struct i40e_vsi *vsi;
5580 struct i40e_mac_filter_info filter;
5582 struct i40e_vsi_context ctxt;
5583 struct rte_ether_addr broadcast =
5584 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5586 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5587 uplink_vsi == NULL) {
5589 "VSI setup failed, VSI link shouldn't be NULL");
5593 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5595 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5600 * 1.type is not MAIN and uplink vsi is not NULL
5601 * If uplink vsi didn't setup VEB, create one first under veb field
5602 * 2.type is SRIOV and the uplink is NULL
5603 * If floating VEB is NULL, create one veb under floating veb field
5606 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5607 uplink_vsi->veb == NULL) {
5608 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5610 if (uplink_vsi->veb == NULL) {
5611 PMD_DRV_LOG(ERR, "VEB setup failed");
5614 /* set ALLOWLOOPBACk on pf, when veb is created */
5615 i40e_enable_pf_lb(pf);
5618 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5619 pf->main_vsi->floating_veb == NULL) {
5620 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5622 if (pf->main_vsi->floating_veb == NULL) {
5623 PMD_DRV_LOG(ERR, "VEB setup failed");
5628 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5630 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5633 TAILQ_INIT(&vsi->mac_list);
5635 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5636 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5637 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5638 vsi->user_param = user_param;
5639 vsi->vlan_anti_spoof_on = 0;
5640 vsi->vlan_filter_on = 0;
5641 /* Allocate queues */
5642 switch (vsi->type) {
5643 case I40E_VSI_MAIN :
5644 vsi->nb_qps = pf->lan_nb_qps;
5646 case I40E_VSI_SRIOV :
5647 vsi->nb_qps = pf->vf_nb_qps;
5649 case I40E_VSI_VMDQ2:
5650 vsi->nb_qps = pf->vmdq_nb_qps;
5653 vsi->nb_qps = pf->fdir_nb_qps;
5659 * The filter status descriptor is reported in rx queue 0,
5660 * while the tx queue for fdir filter programming has no
5661 * such constraints, can be non-zero queues.
5662 * To simplify it, choose FDIR vsi use queue 0 pair.
5663 * To make sure it will use queue 0 pair, queue allocation
5664 * need be done before this function is called
5666 if (type != I40E_VSI_FDIR) {
5667 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5669 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5673 vsi->base_queue = ret;
5675 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5677 /* VF has MSIX interrupt in VF range, don't allocate here */
5678 if (type == I40E_VSI_MAIN) {
5679 if (pf->support_multi_driver) {
5680 /* If support multi-driver, need to use INT0 instead of
5681 * allocating from msix pool. The Msix pool is init from
5682 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5683 * to 1 without calling i40e_res_pool_alloc.
5688 ret = i40e_res_pool_alloc(&pf->msix_pool,
5689 RTE_MIN(vsi->nb_qps,
5690 RTE_MAX_RXTX_INTR_VEC_ID));
5693 "VSI MAIN %d get heap failed %d",
5695 goto fail_queue_alloc;
5697 vsi->msix_intr = ret;
5698 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5699 RTE_MAX_RXTX_INTR_VEC_ID);
5701 } else if (type != I40E_VSI_SRIOV) {
5702 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5704 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5705 goto fail_queue_alloc;
5707 vsi->msix_intr = ret;
5715 if (type == I40E_VSI_MAIN) {
5716 /* For main VSI, no need to add since it's default one */
5717 vsi->uplink_seid = pf->mac_seid;
5718 vsi->seid = pf->main_vsi_seid;
5719 /* Bind queues with specific MSIX interrupt */
5721 * Needs 2 interrupt at least, one for misc cause which will
5722 * enabled from OS side, Another for queues binding the
5723 * interrupt from device side only.
5726 /* Get default VSI parameters from hardware */
5727 memset(&ctxt, 0, sizeof(ctxt));
5728 ctxt.seid = vsi->seid;
5729 ctxt.pf_num = hw->pf_id;
5730 ctxt.uplink_seid = vsi->uplink_seid;
5732 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5733 if (ret != I40E_SUCCESS) {
5734 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5735 goto fail_msix_alloc;
5737 rte_memcpy(&vsi->info, &ctxt.info,
5738 sizeof(struct i40e_aqc_vsi_properties_data));
5739 vsi->vsi_id = ctxt.vsi_number;
5740 vsi->info.valid_sections = 0;
5742 /* Configure tc, enabled TC0 only */
5743 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5745 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5746 goto fail_msix_alloc;
5749 /* TC, queue mapping */
5750 memset(&ctxt, 0, sizeof(ctxt));
5751 vsi->info.valid_sections |=
5752 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5753 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5754 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5755 rte_memcpy(&ctxt.info, &vsi->info,
5756 sizeof(struct i40e_aqc_vsi_properties_data));
5757 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5758 I40E_DEFAULT_TCMAP);
5759 if (ret != I40E_SUCCESS) {
5761 "Failed to configure TC queue mapping");
5762 goto fail_msix_alloc;
5764 ctxt.seid = vsi->seid;
5765 ctxt.pf_num = hw->pf_id;
5766 ctxt.uplink_seid = vsi->uplink_seid;
5769 /* Update VSI parameters */
5770 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5771 if (ret != I40E_SUCCESS) {
5772 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5773 goto fail_msix_alloc;
5776 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5777 sizeof(vsi->info.tc_mapping));
5778 rte_memcpy(&vsi->info.queue_mapping,
5779 &ctxt.info.queue_mapping,
5780 sizeof(vsi->info.queue_mapping));
5781 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5782 vsi->info.valid_sections = 0;
5784 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5788 * Updating default filter settings are necessary to prevent
5789 * reception of tagged packets.
5790 * Some old firmware configurations load a default macvlan
5791 * filter which accepts both tagged and untagged packets.
5792 * The updating is to use a normal filter instead if needed.
5793 * For NVM 4.2.2 or after, the updating is not needed anymore.
5794 * The firmware with correct configurations load the default
5795 * macvlan filter which is expected and cannot be removed.
5797 i40e_update_default_filter_setting(vsi);
5798 i40e_config_qinq(hw, vsi);
5799 } else if (type == I40E_VSI_SRIOV) {
5800 memset(&ctxt, 0, sizeof(ctxt));
5802 * For other VSI, the uplink_seid equals to uplink VSI's
5803 * uplink_seid since they share same VEB
5805 if (uplink_vsi == NULL)
5806 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5808 vsi->uplink_seid = uplink_vsi->uplink_seid;
5809 ctxt.pf_num = hw->pf_id;
5810 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5811 ctxt.uplink_seid = vsi->uplink_seid;
5812 ctxt.connection_type = 0x1;
5813 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5815 /* Use the VEB configuration if FW >= v5.0 */
5816 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5817 /* Configure switch ID */
5818 ctxt.info.valid_sections |=
5819 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5820 ctxt.info.switch_id =
5821 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5824 /* Configure port/vlan */
5825 ctxt.info.valid_sections |=
5826 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5827 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5828 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5829 hw->func_caps.enabled_tcmap);
5830 if (ret != I40E_SUCCESS) {
5832 "Failed to configure TC queue mapping");
5833 goto fail_msix_alloc;
5836 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5837 ctxt.info.valid_sections |=
5838 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5840 * Since VSI is not created yet, only configure parameter,
5841 * will add vsi below.
5844 i40e_config_qinq(hw, vsi);
5845 } else if (type == I40E_VSI_VMDQ2) {
5846 memset(&ctxt, 0, sizeof(ctxt));
5848 * For other VSI, the uplink_seid equals to uplink VSI's
5849 * uplink_seid since they share same VEB
5851 vsi->uplink_seid = uplink_vsi->uplink_seid;
5852 ctxt.pf_num = hw->pf_id;
5854 ctxt.uplink_seid = vsi->uplink_seid;
5855 ctxt.connection_type = 0x1;
5856 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5858 ctxt.info.valid_sections |=
5859 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5860 /* user_param carries flag to enable loop back */
5862 ctxt.info.switch_id =
5863 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5864 ctxt.info.switch_id |=
5865 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5868 /* Configure port/vlan */
5869 ctxt.info.valid_sections |=
5870 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5871 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5872 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5873 I40E_DEFAULT_TCMAP);
5874 if (ret != I40E_SUCCESS) {
5876 "Failed to configure TC queue mapping");
5877 goto fail_msix_alloc;
5879 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5880 ctxt.info.valid_sections |=
5881 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5882 } else if (type == I40E_VSI_FDIR) {
5883 memset(&ctxt, 0, sizeof(ctxt));
5884 vsi->uplink_seid = uplink_vsi->uplink_seid;
5885 ctxt.pf_num = hw->pf_id;
5887 ctxt.uplink_seid = vsi->uplink_seid;
5888 ctxt.connection_type = 0x1; /* regular data port */
5889 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5890 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5891 I40E_DEFAULT_TCMAP);
5892 if (ret != I40E_SUCCESS) {
5894 "Failed to configure TC queue mapping.");
5895 goto fail_msix_alloc;
5897 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5898 ctxt.info.valid_sections |=
5899 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5901 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5902 goto fail_msix_alloc;
5905 if (vsi->type != I40E_VSI_MAIN) {
5906 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5907 if (ret != I40E_SUCCESS) {
5908 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5909 hw->aq.asq_last_status);
5910 goto fail_msix_alloc;
5912 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5913 vsi->info.valid_sections = 0;
5914 vsi->seid = ctxt.seid;
5915 vsi->vsi_id = ctxt.vsi_number;
5916 vsi->sib_vsi_list.vsi = vsi;
5917 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5918 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5919 &vsi->sib_vsi_list, list);
5921 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5922 &vsi->sib_vsi_list, list);
5926 /* MAC/VLAN configuration */
5927 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5928 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5930 ret = i40e_vsi_add_mac(vsi, &filter);
5931 if (ret != I40E_SUCCESS) {
5932 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5933 goto fail_msix_alloc;
5936 /* Get VSI BW information */
5937 i40e_vsi_get_bw_config(vsi);
5940 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5942 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5948 /* Configure vlan filter on or off */
5950 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5953 struct i40e_mac_filter *f;
5955 struct i40e_mac_filter_info *mac_filter;
5956 enum rte_mac_filter_type desired_filter;
5957 int ret = I40E_SUCCESS;
5960 /* Filter to match MAC and VLAN */
5961 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5963 /* Filter to match only MAC */
5964 desired_filter = RTE_MAC_PERFECT_MATCH;
5969 mac_filter = rte_zmalloc("mac_filter_info_data",
5970 num * sizeof(*mac_filter), 0);
5971 if (mac_filter == NULL) {
5972 PMD_DRV_LOG(ERR, "failed to allocate memory");
5973 return I40E_ERR_NO_MEMORY;
5978 /* Remove all existing mac */
5979 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5980 mac_filter[i] = f->mac_info;
5981 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5983 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5984 on ? "enable" : "disable");
5990 /* Override with new filter */
5991 for (i = 0; i < num; i++) {
5992 mac_filter[i].filter_type = desired_filter;
5993 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5995 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5996 on ? "enable" : "disable");
6002 rte_free(mac_filter);
6006 /* Configure vlan stripping on or off */
6008 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6011 struct i40e_vsi_context ctxt;
6013 int ret = I40E_SUCCESS;
6015 /* Check if it has been already on or off */
6016 if (vsi->info.valid_sections &
6017 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6019 if ((vsi->info.port_vlan_flags &
6020 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6021 return 0; /* already on */
6023 if ((vsi->info.port_vlan_flags &
6024 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6025 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6026 return 0; /* already off */
6031 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6033 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6034 vsi->info.valid_sections =
6035 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6036 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6037 vsi->info.port_vlan_flags |= vlan_flags;
6038 ctxt.seid = vsi->seid;
6039 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6040 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6042 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6043 on ? "enable" : "disable");
6049 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6051 struct rte_eth_dev_data *data = dev->data;
6055 /* Apply vlan offload setting */
6056 mask = ETH_VLAN_STRIP_MASK |
6057 ETH_VLAN_FILTER_MASK |
6058 ETH_VLAN_EXTEND_MASK;
6059 ret = i40e_vlan_offload_set(dev, mask);
6061 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6065 /* Apply pvid setting */
6066 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6067 data->dev_conf.txmode.hw_vlan_insert_pvid);
6069 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6075 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6077 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6079 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6083 i40e_update_flow_control(struct i40e_hw *hw)
6085 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6086 struct i40e_link_status link_status;
6087 uint32_t rxfc = 0, txfc = 0, reg;
6091 memset(&link_status, 0, sizeof(link_status));
6092 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6093 if (ret != I40E_SUCCESS) {
6094 PMD_DRV_LOG(ERR, "Failed to get link status information");
6095 goto write_reg; /* Disable flow control */
6098 an_info = hw->phy.link_info.an_info;
6099 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6100 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6101 ret = I40E_ERR_NOT_READY;
6102 goto write_reg; /* Disable flow control */
6105 * If link auto negotiation is enabled, flow control needs to
6106 * be configured according to it
6108 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6109 case I40E_LINK_PAUSE_RXTX:
6112 hw->fc.current_mode = I40E_FC_FULL;
6114 case I40E_AQ_LINK_PAUSE_RX:
6116 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6118 case I40E_AQ_LINK_PAUSE_TX:
6120 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6123 hw->fc.current_mode = I40E_FC_NONE;
6128 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6129 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6130 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6131 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6132 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6133 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6140 i40e_pf_setup(struct i40e_pf *pf)
6142 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6143 struct i40e_filter_control_settings settings;
6144 struct i40e_vsi *vsi;
6147 /* Clear all stats counters */
6148 pf->offset_loaded = FALSE;
6149 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6150 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6151 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6152 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6154 ret = i40e_pf_get_switch_config(pf);
6155 if (ret != I40E_SUCCESS) {
6156 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6160 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6162 PMD_INIT_LOG(WARNING,
6163 "failed to allocate switch domain for device %d", ret);
6165 if (pf->flags & I40E_FLAG_FDIR) {
6166 /* make queue allocated first, let FDIR use queue pair 0*/
6167 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6168 if (ret != I40E_FDIR_QUEUE_ID) {
6170 "queue allocation fails for FDIR: ret =%d",
6172 pf->flags &= ~I40E_FLAG_FDIR;
6175 /* main VSI setup */
6176 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6178 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6179 return I40E_ERR_NOT_READY;
6183 /* Configure filter control */
6184 memset(&settings, 0, sizeof(settings));
6185 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6186 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6187 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6188 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6190 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6191 hw->func_caps.rss_table_size);
6192 return I40E_ERR_PARAM;
6194 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6195 hw->func_caps.rss_table_size);
6196 pf->hash_lut_size = hw->func_caps.rss_table_size;
6198 /* Enable ethtype and macvlan filters */
6199 settings.enable_ethtype = TRUE;
6200 settings.enable_macvlan = TRUE;
6201 ret = i40e_set_filter_control(hw, &settings);
6203 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6206 /* Update flow control according to the auto negotiation */
6207 i40e_update_flow_control(hw);
6209 return I40E_SUCCESS;
6213 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6219 * Set or clear TX Queue Disable flags,
6220 * which is required by hardware.
6222 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6223 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6225 /* Wait until the request is finished */
6226 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6227 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6228 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6229 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6230 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6236 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6237 return I40E_SUCCESS; /* already on, skip next steps */
6239 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6240 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6242 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6243 return I40E_SUCCESS; /* already off, skip next steps */
6244 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6246 /* Write the register */
6247 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6248 /* Check the result */
6249 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6250 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6251 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6253 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6254 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6257 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6258 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6262 /* Check if it is timeout */
6263 if (j >= I40E_CHK_Q_ENA_COUNT) {
6264 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6265 (on ? "enable" : "disable"), q_idx);
6266 return I40E_ERR_TIMEOUT;
6269 return I40E_SUCCESS;
6272 /* Swith on or off the tx queues */
6274 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6276 struct rte_eth_dev_data *dev_data = pf->dev_data;
6277 struct i40e_tx_queue *txq;
6278 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6282 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6283 txq = dev_data->tx_queues[i];
6284 /* Don't operate the queue if not configured or
6285 * if starting only per queue */
6286 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6289 ret = i40e_dev_tx_queue_start(dev, i);
6291 ret = i40e_dev_tx_queue_stop(dev, i);
6292 if ( ret != I40E_SUCCESS)
6296 return I40E_SUCCESS;
6300 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6305 /* Wait until the request is finished */
6306 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6307 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6308 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6309 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6310 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6315 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6316 return I40E_SUCCESS; /* Already on, skip next steps */
6317 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6319 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6320 return I40E_SUCCESS; /* Already off, skip next steps */
6321 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6324 /* Write the register */
6325 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6326 /* Check the result */
6327 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6328 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6329 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6331 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6332 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6335 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6336 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6341 /* Check if it is timeout */
6342 if (j >= I40E_CHK_Q_ENA_COUNT) {
6343 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6344 (on ? "enable" : "disable"), q_idx);
6345 return I40E_ERR_TIMEOUT;
6348 return I40E_SUCCESS;
6350 /* Switch on or off the rx queues */
6352 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6354 struct rte_eth_dev_data *dev_data = pf->dev_data;
6355 struct i40e_rx_queue *rxq;
6356 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6360 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6361 rxq = dev_data->rx_queues[i];
6362 /* Don't operate the queue if not configured or
6363 * if starting only per queue */
6364 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6367 ret = i40e_dev_rx_queue_start(dev, i);
6369 ret = i40e_dev_rx_queue_stop(dev, i);
6370 if (ret != I40E_SUCCESS)
6374 return I40E_SUCCESS;
6377 /* Switch on or off all the rx/tx queues */
6379 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6384 /* enable rx queues before enabling tx queues */
6385 ret = i40e_dev_switch_rx_queues(pf, on);
6387 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6390 ret = i40e_dev_switch_tx_queues(pf, on);
6392 /* Stop tx queues before stopping rx queues */
6393 ret = i40e_dev_switch_tx_queues(pf, on);
6395 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6398 ret = i40e_dev_switch_rx_queues(pf, on);
6404 /* Initialize VSI for TX */
6406 i40e_dev_tx_init(struct i40e_pf *pf)
6408 struct rte_eth_dev_data *data = pf->dev_data;
6410 uint32_t ret = I40E_SUCCESS;
6411 struct i40e_tx_queue *txq;
6413 for (i = 0; i < data->nb_tx_queues; i++) {
6414 txq = data->tx_queues[i];
6415 if (!txq || !txq->q_set)
6417 ret = i40e_tx_queue_init(txq);
6418 if (ret != I40E_SUCCESS)
6421 if (ret == I40E_SUCCESS)
6422 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6428 /* Initialize VSI for RX */
6430 i40e_dev_rx_init(struct i40e_pf *pf)
6432 struct rte_eth_dev_data *data = pf->dev_data;
6433 int ret = I40E_SUCCESS;
6435 struct i40e_rx_queue *rxq;
6437 i40e_pf_config_mq_rx(pf);
6438 for (i = 0; i < data->nb_rx_queues; i++) {
6439 rxq = data->rx_queues[i];
6440 if (!rxq || !rxq->q_set)
6443 ret = i40e_rx_queue_init(rxq);
6444 if (ret != I40E_SUCCESS) {
6446 "Failed to do RX queue initialization");
6450 if (ret == I40E_SUCCESS)
6451 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6458 i40e_dev_rxtx_init(struct i40e_pf *pf)
6462 err = i40e_dev_tx_init(pf);
6464 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6467 err = i40e_dev_rx_init(pf);
6469 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6477 i40e_vmdq_setup(struct rte_eth_dev *dev)
6479 struct rte_eth_conf *conf = &dev->data->dev_conf;
6480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6481 int i, err, conf_vsis, j, loop;
6482 struct i40e_vsi *vsi;
6483 struct i40e_vmdq_info *vmdq_info;
6484 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6485 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6488 * Disable interrupt to avoid message from VF. Furthermore, it will
6489 * avoid race condition in VSI creation/destroy.
6491 i40e_pf_disable_irq0(hw);
6493 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6494 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6498 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6499 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6500 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6501 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6502 pf->max_nb_vmdq_vsi);
6506 if (pf->vmdq != NULL) {
6507 PMD_INIT_LOG(INFO, "VMDQ already configured");
6511 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6512 sizeof(*vmdq_info) * conf_vsis, 0);
6514 if (pf->vmdq == NULL) {
6515 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6519 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6521 /* Create VMDQ VSI */
6522 for (i = 0; i < conf_vsis; i++) {
6523 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6524 vmdq_conf->enable_loop_back);
6526 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6530 vmdq_info = &pf->vmdq[i];
6532 vmdq_info->vsi = vsi;
6534 pf->nb_cfg_vmdq_vsi = conf_vsis;
6536 /* Configure Vlan */
6537 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6538 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6539 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6540 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6541 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6542 vmdq_conf->pool_map[i].vlan_id, j);
6544 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6545 vmdq_conf->pool_map[i].vlan_id);
6547 PMD_INIT_LOG(ERR, "Failed to add vlan");
6555 i40e_pf_enable_irq0(hw);
6560 for (i = 0; i < conf_vsis; i++)
6561 if (pf->vmdq[i].vsi == NULL)
6564 i40e_vsi_release(pf->vmdq[i].vsi);
6568 i40e_pf_enable_irq0(hw);
6573 i40e_stat_update_32(struct i40e_hw *hw,
6581 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6585 if (new_data >= *offset)
6586 *stat = (uint64_t)(new_data - *offset);
6588 *stat = (uint64_t)((new_data +
6589 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6593 i40e_stat_update_48(struct i40e_hw *hw,
6602 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6603 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6604 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6609 if (new_data >= *offset)
6610 *stat = new_data - *offset;
6612 *stat = (uint64_t)((new_data +
6613 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6615 *stat &= I40E_48_BIT_MASK;
6620 i40e_pf_disable_irq0(struct i40e_hw *hw)
6622 /* Disable all interrupt types */
6623 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6624 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6625 I40E_WRITE_FLUSH(hw);
6630 i40e_pf_enable_irq0(struct i40e_hw *hw)
6632 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6633 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6634 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6635 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6636 I40E_WRITE_FLUSH(hw);
6640 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6642 /* read pending request and disable first */
6643 i40e_pf_disable_irq0(hw);
6644 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6645 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6646 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6649 /* Link no queues with irq0 */
6650 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6651 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6655 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6658 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6661 uint32_t index, offset, val;
6666 * Try to find which VF trigger a reset, use absolute VF id to access
6667 * since the reg is global register.
6669 for (i = 0; i < pf->vf_num; i++) {
6670 abs_vf_id = hw->func_caps.vf_base_id + i;
6671 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6672 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6673 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6674 /* VFR event occurred */
6675 if (val & (0x1 << offset)) {
6678 /* Clear the event first */
6679 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6681 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6683 * Only notify a VF reset event occurred,
6684 * don't trigger another SW reset
6686 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6687 if (ret != I40E_SUCCESS)
6688 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6694 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6696 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6699 for (i = 0; i < pf->vf_num; i++)
6700 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6704 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6707 struct i40e_arq_event_info info;
6708 uint16_t pending, opcode;
6711 info.buf_len = I40E_AQ_BUF_SZ;
6712 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6713 if (!info.msg_buf) {
6714 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6720 ret = i40e_clean_arq_element(hw, &info, &pending);
6722 if (ret != I40E_SUCCESS) {
6724 "Failed to read msg from AdminQ, aq_err: %u",
6725 hw->aq.asq_last_status);
6728 opcode = rte_le_to_cpu_16(info.desc.opcode);
6731 case i40e_aqc_opc_send_msg_to_pf:
6732 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6733 i40e_pf_host_handle_vf_msg(dev,
6734 rte_le_to_cpu_16(info.desc.retval),
6735 rte_le_to_cpu_32(info.desc.cookie_high),
6736 rte_le_to_cpu_32(info.desc.cookie_low),
6740 case i40e_aqc_opc_get_link_status:
6741 ret = i40e_dev_link_update(dev, 0);
6743 _rte_eth_dev_callback_process(dev,
6744 RTE_ETH_EVENT_INTR_LSC, NULL);
6747 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6752 rte_free(info.msg_buf);
6756 * Interrupt handler triggered by NIC for handling
6757 * specific interrupt.
6760 * Pointer to interrupt handle.
6762 * The address of parameter (struct rte_eth_dev *) regsitered before.
6768 i40e_dev_interrupt_handler(void *param)
6770 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6774 /* Disable interrupt */
6775 i40e_pf_disable_irq0(hw);
6777 /* read out interrupt causes */
6778 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6780 /* No interrupt event indicated */
6781 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6782 PMD_DRV_LOG(INFO, "No interrupt event");
6785 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6786 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6787 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6788 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6789 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6790 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6791 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6792 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6793 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6794 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6795 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6796 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6797 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6798 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6800 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6801 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6802 i40e_dev_handle_vfr_event(dev);
6804 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6805 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6806 i40e_dev_handle_aq_msg(dev);
6810 /* Enable interrupt */
6811 i40e_pf_enable_irq0(hw);
6815 i40e_dev_alarm_handler(void *param)
6817 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6821 /* Disable interrupt */
6822 i40e_pf_disable_irq0(hw);
6824 /* read out interrupt causes */
6825 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6827 /* No interrupt event indicated */
6828 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6830 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6831 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6832 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6833 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6834 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6835 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6836 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6837 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6838 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6839 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6840 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6841 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6842 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6843 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6845 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6846 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6847 i40e_dev_handle_vfr_event(dev);
6849 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6850 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6851 i40e_dev_handle_aq_msg(dev);
6855 /* Enable interrupt */
6856 i40e_pf_enable_irq0(hw);
6857 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6858 i40e_dev_alarm_handler, dev);
6862 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6863 struct i40e_macvlan_filter *filter,
6866 int ele_num, ele_buff_size;
6867 int num, actual_num, i;
6869 int ret = I40E_SUCCESS;
6870 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6871 struct i40e_aqc_add_macvlan_element_data *req_list;
6873 if (filter == NULL || total == 0)
6874 return I40E_ERR_PARAM;
6875 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6876 ele_buff_size = hw->aq.asq_buf_size;
6878 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6879 if (req_list == NULL) {
6880 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6881 return I40E_ERR_NO_MEMORY;
6886 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6887 memset(req_list, 0, ele_buff_size);
6889 for (i = 0; i < actual_num; i++) {
6890 rte_memcpy(req_list[i].mac_addr,
6891 &filter[num + i].macaddr, ETH_ADDR_LEN);
6892 req_list[i].vlan_tag =
6893 rte_cpu_to_le_16(filter[num + i].vlan_id);
6895 switch (filter[num + i].filter_type) {
6896 case RTE_MAC_PERFECT_MATCH:
6897 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6898 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6900 case RTE_MACVLAN_PERFECT_MATCH:
6901 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6903 case RTE_MAC_HASH_MATCH:
6904 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6905 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6907 case RTE_MACVLAN_HASH_MATCH:
6908 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6911 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6912 ret = I40E_ERR_PARAM;
6916 req_list[i].queue_number = 0;
6918 req_list[i].flags = rte_cpu_to_le_16(flags);
6921 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6923 if (ret != I40E_SUCCESS) {
6924 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6928 } while (num < total);
6936 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6937 struct i40e_macvlan_filter *filter,
6940 int ele_num, ele_buff_size;
6941 int num, actual_num, i;
6943 int ret = I40E_SUCCESS;
6944 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6945 struct i40e_aqc_remove_macvlan_element_data *req_list;
6947 if (filter == NULL || total == 0)
6948 return I40E_ERR_PARAM;
6950 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6951 ele_buff_size = hw->aq.asq_buf_size;
6953 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6954 if (req_list == NULL) {
6955 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6956 return I40E_ERR_NO_MEMORY;
6961 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6962 memset(req_list, 0, ele_buff_size);
6964 for (i = 0; i < actual_num; i++) {
6965 rte_memcpy(req_list[i].mac_addr,
6966 &filter[num + i].macaddr, ETH_ADDR_LEN);
6967 req_list[i].vlan_tag =
6968 rte_cpu_to_le_16(filter[num + i].vlan_id);
6970 switch (filter[num + i].filter_type) {
6971 case RTE_MAC_PERFECT_MATCH:
6972 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6973 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6975 case RTE_MACVLAN_PERFECT_MATCH:
6976 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6978 case RTE_MAC_HASH_MATCH:
6979 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6980 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6982 case RTE_MACVLAN_HASH_MATCH:
6983 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6986 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6987 ret = I40E_ERR_PARAM;
6990 req_list[i].flags = rte_cpu_to_le_16(flags);
6993 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6995 if (ret != I40E_SUCCESS) {
6996 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7000 } while (num < total);
7007 /* Find out specific MAC filter */
7008 static struct i40e_mac_filter *
7009 i40e_find_mac_filter(struct i40e_vsi *vsi,
7010 struct rte_ether_addr *macaddr)
7012 struct i40e_mac_filter *f;
7014 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7015 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7023 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7026 uint32_t vid_idx, vid_bit;
7028 if (vlan_id > ETH_VLAN_ID_MAX)
7031 vid_idx = I40E_VFTA_IDX(vlan_id);
7032 vid_bit = I40E_VFTA_BIT(vlan_id);
7034 if (vsi->vfta[vid_idx] & vid_bit)
7041 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7042 uint16_t vlan_id, bool on)
7044 uint32_t vid_idx, vid_bit;
7046 vid_idx = I40E_VFTA_IDX(vlan_id);
7047 vid_bit = I40E_VFTA_BIT(vlan_id);
7050 vsi->vfta[vid_idx] |= vid_bit;
7052 vsi->vfta[vid_idx] &= ~vid_bit;
7056 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7057 uint16_t vlan_id, bool on)
7059 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7060 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7063 if (vlan_id > ETH_VLAN_ID_MAX)
7066 i40e_store_vlan_filter(vsi, vlan_id, on);
7068 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7071 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7074 ret = i40e_aq_add_vlan(hw, vsi->seid,
7075 &vlan_data, 1, NULL);
7076 if (ret != I40E_SUCCESS)
7077 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7079 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7080 &vlan_data, 1, NULL);
7081 if (ret != I40E_SUCCESS)
7083 "Failed to remove vlan filter");
7088 * Find all vlan options for specific mac addr,
7089 * return with actual vlan found.
7092 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7093 struct i40e_macvlan_filter *mv_f,
7094 int num, struct rte_ether_addr *addr)
7100 * Not to use i40e_find_vlan_filter to decrease the loop time,
7101 * although the code looks complex.
7103 if (num < vsi->vlan_num)
7104 return I40E_ERR_PARAM;
7107 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7109 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7110 if (vsi->vfta[j] & (1 << k)) {
7113 "vlan number doesn't match");
7114 return I40E_ERR_PARAM;
7116 rte_memcpy(&mv_f[i].macaddr,
7117 addr, ETH_ADDR_LEN);
7119 j * I40E_UINT32_BIT_SIZE + k;
7125 return I40E_SUCCESS;
7129 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7130 struct i40e_macvlan_filter *mv_f,
7135 struct i40e_mac_filter *f;
7137 if (num < vsi->mac_num)
7138 return I40E_ERR_PARAM;
7140 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7142 PMD_DRV_LOG(ERR, "buffer number not match");
7143 return I40E_ERR_PARAM;
7145 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7147 mv_f[i].vlan_id = vlan;
7148 mv_f[i].filter_type = f->mac_info.filter_type;
7152 return I40E_SUCCESS;
7156 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7159 struct i40e_mac_filter *f;
7160 struct i40e_macvlan_filter *mv_f;
7161 int ret = I40E_SUCCESS;
7163 if (vsi == NULL || vsi->mac_num == 0)
7164 return I40E_ERR_PARAM;
7166 /* Case that no vlan is set */
7167 if (vsi->vlan_num == 0)
7170 num = vsi->mac_num * vsi->vlan_num;
7172 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7174 PMD_DRV_LOG(ERR, "failed to allocate memory");
7175 return I40E_ERR_NO_MEMORY;
7179 if (vsi->vlan_num == 0) {
7180 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7181 rte_memcpy(&mv_f[i].macaddr,
7182 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7183 mv_f[i].filter_type = f->mac_info.filter_type;
7184 mv_f[i].vlan_id = 0;
7188 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7189 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7190 vsi->vlan_num, &f->mac_info.mac_addr);
7191 if (ret != I40E_SUCCESS)
7193 for (j = i; j < i + vsi->vlan_num; j++)
7194 mv_f[j].filter_type = f->mac_info.filter_type;
7199 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7207 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7209 struct i40e_macvlan_filter *mv_f;
7211 int ret = I40E_SUCCESS;
7213 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7214 return I40E_ERR_PARAM;
7216 /* If it's already set, just return */
7217 if (i40e_find_vlan_filter(vsi,vlan))
7218 return I40E_SUCCESS;
7220 mac_num = vsi->mac_num;
7223 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7224 return I40E_ERR_PARAM;
7227 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7230 PMD_DRV_LOG(ERR, "failed to allocate memory");
7231 return I40E_ERR_NO_MEMORY;
7234 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7236 if (ret != I40E_SUCCESS)
7239 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7241 if (ret != I40E_SUCCESS)
7244 i40e_set_vlan_filter(vsi, vlan, 1);
7254 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7256 struct i40e_macvlan_filter *mv_f;
7258 int ret = I40E_SUCCESS;
7261 * Vlan 0 is the generic filter for untagged packets
7262 * and can't be removed.
7264 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7265 return I40E_ERR_PARAM;
7267 /* If can't find it, just return */
7268 if (!i40e_find_vlan_filter(vsi, vlan))
7269 return I40E_ERR_PARAM;
7271 mac_num = vsi->mac_num;
7274 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7275 return I40E_ERR_PARAM;
7278 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7281 PMD_DRV_LOG(ERR, "failed to allocate memory");
7282 return I40E_ERR_NO_MEMORY;
7285 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7287 if (ret != I40E_SUCCESS)
7290 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7292 if (ret != I40E_SUCCESS)
7295 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7296 if (vsi->vlan_num == 1) {
7297 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7298 if (ret != I40E_SUCCESS)
7301 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7302 if (ret != I40E_SUCCESS)
7306 i40e_set_vlan_filter(vsi, vlan, 0);
7316 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7318 struct i40e_mac_filter *f;
7319 struct i40e_macvlan_filter *mv_f;
7320 int i, vlan_num = 0;
7321 int ret = I40E_SUCCESS;
7323 /* If it's add and we've config it, return */
7324 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7326 return I40E_SUCCESS;
7327 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7328 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7331 * If vlan_num is 0, that's the first time to add mac,
7332 * set mask for vlan_id 0.
7334 if (vsi->vlan_num == 0) {
7335 i40e_set_vlan_filter(vsi, 0, 1);
7338 vlan_num = vsi->vlan_num;
7339 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7340 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7343 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7345 PMD_DRV_LOG(ERR, "failed to allocate memory");
7346 return I40E_ERR_NO_MEMORY;
7349 for (i = 0; i < vlan_num; i++) {
7350 mv_f[i].filter_type = mac_filter->filter_type;
7351 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7355 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7356 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7357 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7358 &mac_filter->mac_addr);
7359 if (ret != I40E_SUCCESS)
7363 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7364 if (ret != I40E_SUCCESS)
7367 /* Add the mac addr into mac list */
7368 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7370 PMD_DRV_LOG(ERR, "failed to allocate memory");
7371 ret = I40E_ERR_NO_MEMORY;
7374 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7376 f->mac_info.filter_type = mac_filter->filter_type;
7377 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7388 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7390 struct i40e_mac_filter *f;
7391 struct i40e_macvlan_filter *mv_f;
7393 enum rte_mac_filter_type filter_type;
7394 int ret = I40E_SUCCESS;
7396 /* Can't find it, return an error */
7397 f = i40e_find_mac_filter(vsi, addr);
7399 return I40E_ERR_PARAM;
7401 vlan_num = vsi->vlan_num;
7402 filter_type = f->mac_info.filter_type;
7403 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7404 filter_type == RTE_MACVLAN_HASH_MATCH) {
7405 if (vlan_num == 0) {
7406 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7407 return I40E_ERR_PARAM;
7409 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7410 filter_type == RTE_MAC_HASH_MATCH)
7413 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7415 PMD_DRV_LOG(ERR, "failed to allocate memory");
7416 return I40E_ERR_NO_MEMORY;
7419 for (i = 0; i < vlan_num; i++) {
7420 mv_f[i].filter_type = filter_type;
7421 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7424 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7425 filter_type == RTE_MACVLAN_HASH_MATCH) {
7426 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7427 if (ret != I40E_SUCCESS)
7431 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7432 if (ret != I40E_SUCCESS)
7435 /* Remove the mac addr into mac list */
7436 TAILQ_REMOVE(&vsi->mac_list, f, next);
7446 /* Configure hash enable flags for RSS */
7448 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7456 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7457 if (flags & (1ULL << i))
7458 hena |= adapter->pctypes_tbl[i];
7464 /* Parse the hash enable flags */
7466 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7468 uint64_t rss_hf = 0;
7474 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7475 if (flags & adapter->pctypes_tbl[i])
7476 rss_hf |= (1ULL << i);
7483 i40e_pf_disable_rss(struct i40e_pf *pf)
7485 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7487 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7488 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7489 I40E_WRITE_FLUSH(hw);
7493 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7495 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7496 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7497 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7498 I40E_VFQF_HKEY_MAX_INDEX :
7499 I40E_PFQF_HKEY_MAX_INDEX;
7502 if (!key || key_len == 0) {
7503 PMD_DRV_LOG(DEBUG, "No key to be configured");
7505 } else if (key_len != (key_idx + 1) *
7507 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7511 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7512 struct i40e_aqc_get_set_rss_key_data *key_dw =
7513 (struct i40e_aqc_get_set_rss_key_data *)key;
7515 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7517 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7519 uint32_t *hash_key = (uint32_t *)key;
7522 if (vsi->type == I40E_VSI_SRIOV) {
7523 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7526 I40E_VFQF_HKEY1(i, vsi->user_param),
7530 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7531 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7534 I40E_WRITE_FLUSH(hw);
7541 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7543 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7544 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7548 if (!key || !key_len)
7551 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7552 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7553 (struct i40e_aqc_get_set_rss_key_data *)key);
7555 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7559 uint32_t *key_dw = (uint32_t *)key;
7562 if (vsi->type == I40E_VSI_SRIOV) {
7563 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7564 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7565 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7567 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7570 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7571 reg = I40E_PFQF_HKEY(i);
7572 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7574 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7582 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7584 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7588 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7589 rss_conf->rss_key_len);
7593 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7594 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7595 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7596 I40E_WRITE_FLUSH(hw);
7602 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7603 struct rte_eth_rss_conf *rss_conf)
7605 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7606 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7607 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7610 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7611 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7613 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7614 if (rss_hf != 0) /* Enable RSS */
7616 return 0; /* Nothing to do */
7619 if (rss_hf == 0) /* Disable RSS */
7622 return i40e_hw_rss_hash_set(pf, rss_conf);
7626 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7627 struct rte_eth_rss_conf *rss_conf)
7629 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7630 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7637 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7638 &rss_conf->rss_key_len);
7642 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7643 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7644 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7650 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7652 switch (filter_type) {
7653 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7654 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7656 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7657 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7659 case RTE_TUNNEL_FILTER_IMAC_TENID:
7660 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7662 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7663 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7665 case ETH_TUNNEL_FILTER_IMAC:
7666 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7668 case ETH_TUNNEL_FILTER_OIP:
7669 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7671 case ETH_TUNNEL_FILTER_IIP:
7672 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7675 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7682 /* Convert tunnel filter structure */
7684 i40e_tunnel_filter_convert(
7685 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7686 struct i40e_tunnel_filter *tunnel_filter)
7688 rte_ether_addr_copy((struct rte_ether_addr *)
7689 &cld_filter->element.outer_mac,
7690 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7691 rte_ether_addr_copy((struct rte_ether_addr *)
7692 &cld_filter->element.inner_mac,
7693 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7694 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7695 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7696 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7697 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7698 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7700 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7701 tunnel_filter->input.flags = cld_filter->element.flags;
7702 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7703 tunnel_filter->queue = cld_filter->element.queue_number;
7704 rte_memcpy(tunnel_filter->input.general_fields,
7705 cld_filter->general_fields,
7706 sizeof(cld_filter->general_fields));
7711 /* Check if there exists the tunnel filter */
7712 struct i40e_tunnel_filter *
7713 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7714 const struct i40e_tunnel_filter_input *input)
7718 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7722 return tunnel_rule->hash_map[ret];
7725 /* Add a tunnel filter into the SW list */
7727 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7728 struct i40e_tunnel_filter *tunnel_filter)
7730 struct i40e_tunnel_rule *rule = &pf->tunnel;
7733 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7736 "Failed to insert tunnel filter to hash table %d!",
7740 rule->hash_map[ret] = tunnel_filter;
7742 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7747 /* Delete a tunnel filter from the SW list */
7749 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7750 struct i40e_tunnel_filter_input *input)
7752 struct i40e_tunnel_rule *rule = &pf->tunnel;
7753 struct i40e_tunnel_filter *tunnel_filter;
7756 ret = rte_hash_del_key(rule->hash_table, input);
7759 "Failed to delete tunnel filter to hash table %d!",
7763 tunnel_filter = rule->hash_map[ret];
7764 rule->hash_map[ret] = NULL;
7766 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7767 rte_free(tunnel_filter);
7773 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7774 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7778 uint32_t ipv4_addr, ipv4_addr_le;
7779 uint8_t i, tun_type = 0;
7780 /* internal varialbe to convert ipv6 byte order */
7781 uint32_t convert_ipv6[4];
7783 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7784 struct i40e_vsi *vsi = pf->main_vsi;
7785 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7786 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7787 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7788 struct i40e_tunnel_filter *tunnel, *node;
7789 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7791 cld_filter = rte_zmalloc("tunnel_filter",
7792 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7795 if (NULL == cld_filter) {
7796 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7799 pfilter = cld_filter;
7801 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7802 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7803 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7804 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7806 pfilter->element.inner_vlan =
7807 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7808 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7809 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7810 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7811 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7812 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7814 sizeof(pfilter->element.ipaddr.v4.data));
7816 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7817 for (i = 0; i < 4; i++) {
7819 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7821 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7823 sizeof(pfilter->element.ipaddr.v6.data));
7826 /* check tunneled type */
7827 switch (tunnel_filter->tunnel_type) {
7828 case RTE_TUNNEL_TYPE_VXLAN:
7829 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7831 case RTE_TUNNEL_TYPE_NVGRE:
7832 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7834 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7835 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7837 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7838 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7841 /* Other tunnel types is not supported. */
7842 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7843 rte_free(cld_filter);
7847 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7848 &pfilter->element.flags);
7850 rte_free(cld_filter);
7854 pfilter->element.flags |= rte_cpu_to_le_16(
7855 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7856 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7857 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7858 pfilter->element.queue_number =
7859 rte_cpu_to_le_16(tunnel_filter->queue_id);
7861 /* Check if there is the filter in SW list */
7862 memset(&check_filter, 0, sizeof(check_filter));
7863 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7864 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7866 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7867 rte_free(cld_filter);
7871 if (!add && !node) {
7872 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7873 rte_free(cld_filter);
7878 ret = i40e_aq_add_cloud_filters(hw,
7879 vsi->seid, &cld_filter->element, 1);
7881 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7882 rte_free(cld_filter);
7885 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7886 if (tunnel == NULL) {
7887 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7888 rte_free(cld_filter);
7892 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7893 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7897 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7898 &cld_filter->element, 1);
7900 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7901 rte_free(cld_filter);
7904 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7907 rte_free(cld_filter);
7911 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7912 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7913 #define I40E_TR_GENEVE_KEY_MASK 0x8
7914 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7915 #define I40E_TR_GRE_KEY_MASK 0x400
7916 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7917 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7920 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7922 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7923 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7924 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7925 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7926 enum i40e_status_code status = I40E_SUCCESS;
7928 if (pf->support_multi_driver) {
7929 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7930 return I40E_NOT_SUPPORTED;
7933 memset(&filter_replace, 0,
7934 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7935 memset(&filter_replace_buf, 0,
7936 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7938 /* create L1 filter */
7939 filter_replace.old_filter_type =
7940 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7941 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7942 filter_replace.tr_bit = 0;
7944 /* Prepare the buffer, 3 entries */
7945 filter_replace_buf.data[0] =
7946 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7947 filter_replace_buf.data[0] |=
7948 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7949 filter_replace_buf.data[2] = 0xFF;
7950 filter_replace_buf.data[3] = 0xFF;
7951 filter_replace_buf.data[4] =
7952 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7953 filter_replace_buf.data[4] |=
7954 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7955 filter_replace_buf.data[7] = 0xF0;
7956 filter_replace_buf.data[8]
7957 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7958 filter_replace_buf.data[8] |=
7959 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7960 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7961 I40E_TR_GENEVE_KEY_MASK |
7962 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7963 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7964 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7965 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7967 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7968 &filter_replace_buf);
7969 if (!status && (filter_replace.old_filter_type !=
7970 filter_replace.new_filter_type))
7971 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7972 " original: 0x%x, new: 0x%x",
7974 filter_replace.old_filter_type,
7975 filter_replace.new_filter_type);
7981 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7983 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7984 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7985 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7986 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7987 enum i40e_status_code status = I40E_SUCCESS;
7989 if (pf->support_multi_driver) {
7990 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7991 return I40E_NOT_SUPPORTED;
7995 memset(&filter_replace, 0,
7996 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7997 memset(&filter_replace_buf, 0,
7998 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7999 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8000 I40E_AQC_MIRROR_CLOUD_FILTER;
8001 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8002 filter_replace.new_filter_type =
8003 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8004 /* Prepare the buffer, 2 entries */
8005 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8006 filter_replace_buf.data[0] |=
8007 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8008 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8009 filter_replace_buf.data[4] |=
8010 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8011 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8012 &filter_replace_buf);
8015 if (filter_replace.old_filter_type !=
8016 filter_replace.new_filter_type)
8017 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8018 " original: 0x%x, new: 0x%x",
8020 filter_replace.old_filter_type,
8021 filter_replace.new_filter_type);
8024 memset(&filter_replace, 0,
8025 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8026 memset(&filter_replace_buf, 0,
8027 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8029 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8030 I40E_AQC_MIRROR_CLOUD_FILTER;
8031 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8032 filter_replace.new_filter_type =
8033 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8034 /* Prepare the buffer, 2 entries */
8035 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8036 filter_replace_buf.data[0] |=
8037 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8038 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8039 filter_replace_buf.data[4] |=
8040 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8042 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8043 &filter_replace_buf);
8044 if (!status && (filter_replace.old_filter_type !=
8045 filter_replace.new_filter_type))
8046 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8047 " original: 0x%x, new: 0x%x",
8049 filter_replace.old_filter_type,
8050 filter_replace.new_filter_type);
8055 static enum i40e_status_code
8056 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8058 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8059 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8060 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8061 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8062 enum i40e_status_code status = I40E_SUCCESS;
8064 if (pf->support_multi_driver) {
8065 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8066 return I40E_NOT_SUPPORTED;
8070 memset(&filter_replace, 0,
8071 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8072 memset(&filter_replace_buf, 0,
8073 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8074 /* create L1 filter */
8075 filter_replace.old_filter_type =
8076 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8077 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8078 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8079 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8080 /* Prepare the buffer, 2 entries */
8081 filter_replace_buf.data[0] =
8082 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8083 filter_replace_buf.data[0] |=
8084 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8085 filter_replace_buf.data[2] = 0xFF;
8086 filter_replace_buf.data[3] = 0xFF;
8087 filter_replace_buf.data[4] =
8088 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8089 filter_replace_buf.data[4] |=
8090 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8091 filter_replace_buf.data[6] = 0xFF;
8092 filter_replace_buf.data[7] = 0xFF;
8093 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8094 &filter_replace_buf);
8097 if (filter_replace.old_filter_type !=
8098 filter_replace.new_filter_type)
8099 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8100 " original: 0x%x, new: 0x%x",
8102 filter_replace.old_filter_type,
8103 filter_replace.new_filter_type);
8106 memset(&filter_replace, 0,
8107 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8108 memset(&filter_replace_buf, 0,
8109 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8110 /* create L1 filter */
8111 filter_replace.old_filter_type =
8112 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8113 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8114 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8115 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8116 /* Prepare the buffer, 2 entries */
8117 filter_replace_buf.data[0] =
8118 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8119 filter_replace_buf.data[0] |=
8120 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8121 filter_replace_buf.data[2] = 0xFF;
8122 filter_replace_buf.data[3] = 0xFF;
8123 filter_replace_buf.data[4] =
8124 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8125 filter_replace_buf.data[4] |=
8126 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8127 filter_replace_buf.data[6] = 0xFF;
8128 filter_replace_buf.data[7] = 0xFF;
8130 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8131 &filter_replace_buf);
8132 if (!status && (filter_replace.old_filter_type !=
8133 filter_replace.new_filter_type))
8134 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8135 " original: 0x%x, new: 0x%x",
8137 filter_replace.old_filter_type,
8138 filter_replace.new_filter_type);
8144 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8146 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8147 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8148 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8149 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8150 enum i40e_status_code status = I40E_SUCCESS;
8152 if (pf->support_multi_driver) {
8153 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8154 return I40E_NOT_SUPPORTED;
8158 memset(&filter_replace, 0,
8159 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8160 memset(&filter_replace_buf, 0,
8161 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8162 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8163 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8164 filter_replace.new_filter_type =
8165 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8166 /* Prepare the buffer, 2 entries */
8167 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8168 filter_replace_buf.data[0] |=
8169 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8170 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8171 filter_replace_buf.data[4] |=
8172 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8173 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8174 &filter_replace_buf);
8177 if (filter_replace.old_filter_type !=
8178 filter_replace.new_filter_type)
8179 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8180 " original: 0x%x, new: 0x%x",
8182 filter_replace.old_filter_type,
8183 filter_replace.new_filter_type);
8186 memset(&filter_replace, 0,
8187 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8188 memset(&filter_replace_buf, 0,
8189 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8190 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8191 filter_replace.old_filter_type =
8192 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8193 filter_replace.new_filter_type =
8194 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8195 /* Prepare the buffer, 2 entries */
8196 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8197 filter_replace_buf.data[0] |=
8198 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8199 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8200 filter_replace_buf.data[4] |=
8201 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8203 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8204 &filter_replace_buf);
8205 if (!status && (filter_replace.old_filter_type !=
8206 filter_replace.new_filter_type))
8207 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8208 " original: 0x%x, new: 0x%x",
8210 filter_replace.old_filter_type,
8211 filter_replace.new_filter_type);
8217 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8218 struct i40e_tunnel_filter_conf *tunnel_filter,
8222 uint32_t ipv4_addr, ipv4_addr_le;
8223 uint8_t i, tun_type = 0;
8224 /* internal variable to convert ipv6 byte order */
8225 uint32_t convert_ipv6[4];
8227 struct i40e_pf_vf *vf = NULL;
8228 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8229 struct i40e_vsi *vsi;
8230 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8231 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8232 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8233 struct i40e_tunnel_filter *tunnel, *node;
8234 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8236 bool big_buffer = 0;
8238 cld_filter = rte_zmalloc("tunnel_filter",
8239 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8242 if (cld_filter == NULL) {
8243 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8246 pfilter = cld_filter;
8248 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8249 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8250 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8251 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8253 pfilter->element.inner_vlan =
8254 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8255 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8256 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8257 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8258 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8259 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8261 sizeof(pfilter->element.ipaddr.v4.data));
8263 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8264 for (i = 0; i < 4; i++) {
8266 rte_cpu_to_le_32(rte_be_to_cpu_32(
8267 tunnel_filter->ip_addr.ipv6_addr[i]));
8269 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8271 sizeof(pfilter->element.ipaddr.v6.data));
8274 /* check tunneled type */
8275 switch (tunnel_filter->tunnel_type) {
8276 case I40E_TUNNEL_TYPE_VXLAN:
8277 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8279 case I40E_TUNNEL_TYPE_NVGRE:
8280 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8282 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8283 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8285 case I40E_TUNNEL_TYPE_MPLSoUDP:
8286 if (!pf->mpls_replace_flag) {
8287 i40e_replace_mpls_l1_filter(pf);
8288 i40e_replace_mpls_cloud_filter(pf);
8289 pf->mpls_replace_flag = 1;
8291 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8292 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8294 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8295 (teid_le & 0xF) << 12;
8296 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8299 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8301 case I40E_TUNNEL_TYPE_MPLSoGRE:
8302 if (!pf->mpls_replace_flag) {
8303 i40e_replace_mpls_l1_filter(pf);
8304 i40e_replace_mpls_cloud_filter(pf);
8305 pf->mpls_replace_flag = 1;
8307 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8308 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8310 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8311 (teid_le & 0xF) << 12;
8312 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8315 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8317 case I40E_TUNNEL_TYPE_GTPC:
8318 if (!pf->gtp_replace_flag) {
8319 i40e_replace_gtp_l1_filter(pf);
8320 i40e_replace_gtp_cloud_filter(pf);
8321 pf->gtp_replace_flag = 1;
8323 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8324 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8325 (teid_le >> 16) & 0xFFFF;
8326 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8328 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8332 case I40E_TUNNEL_TYPE_GTPU:
8333 if (!pf->gtp_replace_flag) {
8334 i40e_replace_gtp_l1_filter(pf);
8335 i40e_replace_gtp_cloud_filter(pf);
8336 pf->gtp_replace_flag = 1;
8338 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8339 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8340 (teid_le >> 16) & 0xFFFF;
8341 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8343 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8347 case I40E_TUNNEL_TYPE_QINQ:
8348 if (!pf->qinq_replace_flag) {
8349 ret = i40e_cloud_filter_qinq_create(pf);
8352 "QinQ tunnel filter already created.");
8353 pf->qinq_replace_flag = 1;
8355 /* Add in the General fields the values of
8356 * the Outer and Inner VLAN
8357 * Big Buffer should be set, see changes in
8358 * i40e_aq_add_cloud_filters
8360 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8361 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8365 /* Other tunnel types is not supported. */
8366 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8367 rte_free(cld_filter);
8371 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8372 pfilter->element.flags =
8373 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8374 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8375 pfilter->element.flags =
8376 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8377 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8378 pfilter->element.flags =
8379 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8380 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8381 pfilter->element.flags =
8382 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8383 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8384 pfilter->element.flags |=
8385 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8387 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8388 &pfilter->element.flags);
8390 rte_free(cld_filter);
8395 pfilter->element.flags |= rte_cpu_to_le_16(
8396 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8397 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8398 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8399 pfilter->element.queue_number =
8400 rte_cpu_to_le_16(tunnel_filter->queue_id);
8402 if (!tunnel_filter->is_to_vf)
8405 if (tunnel_filter->vf_id >= pf->vf_num) {
8406 PMD_DRV_LOG(ERR, "Invalid argument.");
8407 rte_free(cld_filter);
8410 vf = &pf->vfs[tunnel_filter->vf_id];
8414 /* Check if there is the filter in SW list */
8415 memset(&check_filter, 0, sizeof(check_filter));
8416 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8417 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8418 check_filter.vf_id = tunnel_filter->vf_id;
8419 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8421 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8422 rte_free(cld_filter);
8426 if (!add && !node) {
8427 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8428 rte_free(cld_filter);
8434 ret = i40e_aq_add_cloud_filters_bb(hw,
8435 vsi->seid, cld_filter, 1);
8437 ret = i40e_aq_add_cloud_filters(hw,
8438 vsi->seid, &cld_filter->element, 1);
8440 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8441 rte_free(cld_filter);
8444 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8445 if (tunnel == NULL) {
8446 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8447 rte_free(cld_filter);
8451 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8452 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8457 ret = i40e_aq_rem_cloud_filters_bb(
8458 hw, vsi->seid, cld_filter, 1);
8460 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8461 &cld_filter->element, 1);
8463 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8464 rte_free(cld_filter);
8467 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8470 rte_free(cld_filter);
8475 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8479 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8480 if (pf->vxlan_ports[i] == port)
8488 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8491 uint8_t filter_idx = 0;
8492 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8494 idx = i40e_get_vxlan_port_idx(pf, port);
8496 /* Check if port already exists */
8498 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8502 /* Now check if there is space to add the new port */
8503 idx = i40e_get_vxlan_port_idx(pf, 0);
8506 "Maximum number of UDP ports reached, not adding port %d",
8511 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8514 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8518 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8521 /* New port: add it and mark its index in the bitmap */
8522 pf->vxlan_ports[idx] = port;
8523 pf->vxlan_bitmap |= (1 << idx);
8525 if (!(pf->flags & I40E_FLAG_VXLAN))
8526 pf->flags |= I40E_FLAG_VXLAN;
8532 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8535 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8537 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8538 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8542 idx = i40e_get_vxlan_port_idx(pf, port);
8545 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8549 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8550 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8554 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8557 pf->vxlan_ports[idx] = 0;
8558 pf->vxlan_bitmap &= ~(1 << idx);
8560 if (!pf->vxlan_bitmap)
8561 pf->flags &= ~I40E_FLAG_VXLAN;
8566 /* Add UDP tunneling port */
8568 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8569 struct rte_eth_udp_tunnel *udp_tunnel)
8572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8574 if (udp_tunnel == NULL)
8577 switch (udp_tunnel->prot_type) {
8578 case RTE_TUNNEL_TYPE_VXLAN:
8579 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8580 I40E_AQC_TUNNEL_TYPE_VXLAN);
8582 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8583 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8584 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8586 case RTE_TUNNEL_TYPE_GENEVE:
8587 case RTE_TUNNEL_TYPE_TEREDO:
8588 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8593 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8601 /* Remove UDP tunneling port */
8603 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8604 struct rte_eth_udp_tunnel *udp_tunnel)
8607 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8609 if (udp_tunnel == NULL)
8612 switch (udp_tunnel->prot_type) {
8613 case RTE_TUNNEL_TYPE_VXLAN:
8614 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8615 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8617 case RTE_TUNNEL_TYPE_GENEVE:
8618 case RTE_TUNNEL_TYPE_TEREDO:
8619 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8623 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8631 /* Calculate the maximum number of contiguous PF queues that are configured */
8633 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8635 struct rte_eth_dev_data *data = pf->dev_data;
8637 struct i40e_rx_queue *rxq;
8640 for (i = 0; i < pf->lan_nb_qps; i++) {
8641 rxq = data->rx_queues[i];
8642 if (rxq && rxq->q_set)
8653 i40e_pf_config_rss(struct i40e_pf *pf)
8655 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8656 struct rte_eth_rss_conf rss_conf;
8657 uint32_t i, lut = 0;
8661 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8662 * It's necessary to calculate the actual PF queues that are configured.
8664 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8665 num = i40e_pf_calc_configured_queues_num(pf);
8667 num = pf->dev_data->nb_rx_queues;
8669 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8670 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8674 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8678 if (pf->adapter->rss_reta_updated == 0) {
8679 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8682 lut = (lut << 8) | (j & ((0x1 <<
8683 hw->func_caps.rss_table_entry_width) - 1));
8685 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8690 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8691 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8692 i40e_pf_disable_rss(pf);
8695 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8696 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8697 /* Random default keys */
8698 static uint32_t rss_key_default[] = {0x6b793944,
8699 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8700 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8701 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8703 rss_conf.rss_key = (uint8_t *)rss_key_default;
8704 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8708 return i40e_hw_rss_hash_set(pf, &rss_conf);
8712 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8713 struct rte_eth_tunnel_filter_conf *filter)
8715 if (pf == NULL || filter == NULL) {
8716 PMD_DRV_LOG(ERR, "Invalid parameter");
8720 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8721 PMD_DRV_LOG(ERR, "Invalid queue ID");
8725 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8726 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8730 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8731 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8732 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8736 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8737 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8738 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8745 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8746 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8748 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8750 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8754 if (pf->support_multi_driver) {
8755 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8759 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8760 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8763 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8764 } else if (len == 4) {
8765 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8767 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8772 ret = i40e_aq_debug_write_global_register(hw,
8773 I40E_GL_PRS_FVBM(2),
8777 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8778 "with value 0x%08x",
8779 I40E_GL_PRS_FVBM(2), reg);
8783 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8784 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8790 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8797 switch (cfg->cfg_type) {
8798 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8799 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8802 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8810 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8811 enum rte_filter_op filter_op,
8814 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8815 int ret = I40E_ERR_PARAM;
8817 switch (filter_op) {
8818 case RTE_ETH_FILTER_SET:
8819 ret = i40e_dev_global_config_set(hw,
8820 (struct rte_eth_global_cfg *)arg);
8823 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8831 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8832 enum rte_filter_op filter_op,
8835 struct rte_eth_tunnel_filter_conf *filter;
8836 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8837 int ret = I40E_SUCCESS;
8839 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8841 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8842 return I40E_ERR_PARAM;
8844 switch (filter_op) {
8845 case RTE_ETH_FILTER_NOP:
8846 if (!(pf->flags & I40E_FLAG_VXLAN))
8847 ret = I40E_NOT_SUPPORTED;
8849 case RTE_ETH_FILTER_ADD:
8850 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8852 case RTE_ETH_FILTER_DELETE:
8853 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8856 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8857 ret = I40E_ERR_PARAM;
8865 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8868 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8871 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8872 ret = i40e_pf_config_rss(pf);
8874 i40e_pf_disable_rss(pf);
8879 /* Get the symmetric hash enable configurations per port */
8881 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8883 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8885 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8888 /* Set the symmetric hash enable configurations per port */
8890 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8892 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8895 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8897 "Symmetric hash has already been enabled");
8900 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8902 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8904 "Symmetric hash has already been disabled");
8907 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8909 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8910 I40E_WRITE_FLUSH(hw);
8914 * Get global configurations of hash function type and symmetric hash enable
8915 * per flow type (pctype). Note that global configuration means it affects all
8916 * the ports on the same NIC.
8919 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8920 struct rte_eth_hash_global_conf *g_cfg)
8922 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8926 memset(g_cfg, 0, sizeof(*g_cfg));
8927 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8928 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8929 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8931 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8932 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8933 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8936 * As i40e supports less than 64 flow types, only first 64 bits need to
8939 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8940 g_cfg->valid_bit_mask[i] = 0ULL;
8941 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8944 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8946 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8947 if (!adapter->pctypes_tbl[i])
8949 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8950 j < I40E_FILTER_PCTYPE_MAX; j++) {
8951 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8952 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8953 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8954 g_cfg->sym_hash_enable_mask[0] |=
8965 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8966 const struct rte_eth_hash_global_conf *g_cfg)
8969 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8971 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8972 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8973 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8974 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8980 * As i40e supports less than 64 flow types, only first 64 bits need to
8983 mask0 = g_cfg->valid_bit_mask[0];
8984 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8986 /* Check if any unsupported flow type configured */
8987 if ((mask0 | i40e_mask) ^ i40e_mask)
8990 if (g_cfg->valid_bit_mask[i])
8998 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9004 * Set global configurations of hash function type and symmetric hash enable
9005 * per flow type (pctype). Note any modifying global configuration will affect
9006 * all the ports on the same NIC.
9009 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9010 struct rte_eth_hash_global_conf *g_cfg)
9012 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9013 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9017 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9019 if (pf->support_multi_driver) {
9020 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9024 /* Check the input parameters */
9025 ret = i40e_hash_global_config_check(adapter, g_cfg);
9030 * As i40e supports less than 64 flow types, only first 64 bits need to
9033 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9034 if (mask0 & (1UL << i)) {
9035 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9036 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9038 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9039 j < I40E_FILTER_PCTYPE_MAX; j++) {
9040 if (adapter->pctypes_tbl[i] & (1ULL << j))
9041 i40e_write_global_rx_ctl(hw,
9048 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9049 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9051 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9053 "Hash function already set to Toeplitz");
9056 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9057 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9059 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9061 "Hash function already set to Simple XOR");
9064 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9066 /* Use the default, and keep it as it is */
9069 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9072 I40E_WRITE_FLUSH(hw);
9078 * Valid input sets for hash and flow director filters per PCTYPE
9081 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9082 enum rte_filter_type filter)
9086 static const uint64_t valid_hash_inset_table[] = {
9087 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9088 I40E_INSET_DMAC | I40E_INSET_SMAC |
9089 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9090 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9091 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9092 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9093 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9094 I40E_INSET_FLEX_PAYLOAD,
9095 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9096 I40E_INSET_DMAC | I40E_INSET_SMAC |
9097 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9098 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9099 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9100 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9101 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9102 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9103 I40E_INSET_FLEX_PAYLOAD,
9104 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9105 I40E_INSET_DMAC | I40E_INSET_SMAC |
9106 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9107 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9108 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9109 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9110 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9111 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9112 I40E_INSET_FLEX_PAYLOAD,
9113 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9114 I40E_INSET_DMAC | I40E_INSET_SMAC |
9115 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9116 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9117 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9118 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9119 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9120 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9121 I40E_INSET_FLEX_PAYLOAD,
9122 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9123 I40E_INSET_DMAC | I40E_INSET_SMAC |
9124 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9125 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9126 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9127 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9128 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9129 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9130 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9131 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9132 I40E_INSET_DMAC | I40E_INSET_SMAC |
9133 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9134 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9135 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9136 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9137 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9138 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9139 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9140 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9141 I40E_INSET_DMAC | I40E_INSET_SMAC |
9142 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9143 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9144 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9145 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9146 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9147 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9148 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9149 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9150 I40E_INSET_DMAC | I40E_INSET_SMAC |
9151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9152 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9153 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9154 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9155 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9156 I40E_INSET_FLEX_PAYLOAD,
9157 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9158 I40E_INSET_DMAC | I40E_INSET_SMAC |
9159 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9160 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9161 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9162 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9163 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9164 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9165 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9166 I40E_INSET_DMAC | I40E_INSET_SMAC |
9167 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9168 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9169 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9170 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9171 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9172 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9173 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9174 I40E_INSET_DMAC | I40E_INSET_SMAC |
9175 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9176 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9177 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9178 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9179 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9180 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9181 I40E_INSET_FLEX_PAYLOAD,
9182 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9183 I40E_INSET_DMAC | I40E_INSET_SMAC |
9184 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9185 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9186 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9187 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9188 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9189 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9190 I40E_INSET_FLEX_PAYLOAD,
9191 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9192 I40E_INSET_DMAC | I40E_INSET_SMAC |
9193 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9194 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9195 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9196 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9197 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9198 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9199 I40E_INSET_FLEX_PAYLOAD,
9200 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9201 I40E_INSET_DMAC | I40E_INSET_SMAC |
9202 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9203 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9204 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9205 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9206 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9207 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9208 I40E_INSET_FLEX_PAYLOAD,
9209 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9210 I40E_INSET_DMAC | I40E_INSET_SMAC |
9211 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9212 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9213 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9214 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9215 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9216 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9217 I40E_INSET_FLEX_PAYLOAD,
9218 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9219 I40E_INSET_DMAC | I40E_INSET_SMAC |
9220 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9221 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9222 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9223 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9224 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9225 I40E_INSET_FLEX_PAYLOAD,
9226 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9227 I40E_INSET_DMAC | I40E_INSET_SMAC |
9228 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9229 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9230 I40E_INSET_FLEX_PAYLOAD,
9234 * Flow director supports only fields defined in
9235 * union rte_eth_fdir_flow.
9237 static const uint64_t valid_fdir_inset_table[] = {
9238 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9239 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9240 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9241 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9242 I40E_INSET_IPV4_TTL,
9243 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9244 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9245 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9246 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9247 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9248 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9249 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9250 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9251 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9252 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9253 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9254 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9255 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9256 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9257 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9258 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9259 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9260 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9261 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9262 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9263 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9264 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9265 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9266 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9267 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9268 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9269 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9270 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9271 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9272 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9274 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9275 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9276 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9277 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9278 I40E_INSET_IPV4_TTL,
9279 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9280 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9281 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9282 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9283 I40E_INSET_IPV6_HOP_LIMIT,
9284 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9285 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9286 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9287 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9288 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9289 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9290 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9291 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9292 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9293 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9294 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9295 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9296 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9297 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9298 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9299 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9300 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9301 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9302 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9303 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9304 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9305 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9306 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9307 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9308 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9309 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9310 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9311 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9312 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9313 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9315 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9316 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9317 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9318 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9319 I40E_INSET_IPV6_HOP_LIMIT,
9320 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9321 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9322 I40E_INSET_LAST_ETHER_TYPE,
9325 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9327 if (filter == RTE_ETH_FILTER_HASH)
9328 valid = valid_hash_inset_table[pctype];
9330 valid = valid_fdir_inset_table[pctype];
9336 * Validate if the input set is allowed for a specific PCTYPE
9339 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9340 enum rte_filter_type filter, uint64_t inset)
9344 valid = i40e_get_valid_input_set(pctype, filter);
9345 if (inset & (~valid))
9351 /* default input set fields combination per pctype */
9353 i40e_get_default_input_set(uint16_t pctype)
9355 static const uint64_t default_inset_table[] = {
9356 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9357 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9358 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9359 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9360 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9361 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9362 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9363 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9364 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9365 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9366 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9367 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9368 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9369 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9370 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9371 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9372 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9373 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9374 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9375 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9377 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9378 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9379 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9380 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9381 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9382 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9383 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9384 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9385 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9386 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9387 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9388 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9389 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9390 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9391 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9392 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9393 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9394 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9395 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9396 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9397 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9398 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9400 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9401 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9402 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9403 I40E_INSET_LAST_ETHER_TYPE,
9406 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9409 return default_inset_table[pctype];
9413 * Parse the input set from index to logical bit masks
9416 i40e_parse_input_set(uint64_t *inset,
9417 enum i40e_filter_pctype pctype,
9418 enum rte_eth_input_set_field *field,
9424 static const struct {
9425 enum rte_eth_input_set_field field;
9427 } inset_convert_table[] = {
9428 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9429 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9430 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9431 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9432 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9433 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9434 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9435 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9436 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9437 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9438 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9439 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9440 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9441 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9442 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9443 I40E_INSET_IPV6_NEXT_HDR},
9444 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9445 I40E_INSET_IPV6_HOP_LIMIT},
9446 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9447 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9448 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9449 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9450 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9451 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9452 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9453 I40E_INSET_SCTP_VT},
9454 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9455 I40E_INSET_TUNNEL_DMAC},
9456 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9457 I40E_INSET_VLAN_TUNNEL},
9458 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9459 I40E_INSET_TUNNEL_ID},
9460 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9461 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9462 I40E_INSET_FLEX_PAYLOAD_W1},
9463 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9464 I40E_INSET_FLEX_PAYLOAD_W2},
9465 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9466 I40E_INSET_FLEX_PAYLOAD_W3},
9467 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9468 I40E_INSET_FLEX_PAYLOAD_W4},
9469 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9470 I40E_INSET_FLEX_PAYLOAD_W5},
9471 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9472 I40E_INSET_FLEX_PAYLOAD_W6},
9473 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9474 I40E_INSET_FLEX_PAYLOAD_W7},
9475 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9476 I40E_INSET_FLEX_PAYLOAD_W8},
9479 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9482 /* Only one item allowed for default or all */
9484 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9485 *inset = i40e_get_default_input_set(pctype);
9487 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9488 *inset = I40E_INSET_NONE;
9493 for (i = 0, *inset = 0; i < size; i++) {
9494 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9495 if (field[i] == inset_convert_table[j].field) {
9496 *inset |= inset_convert_table[j].inset;
9501 /* It contains unsupported input set, return immediately */
9502 if (j == RTE_DIM(inset_convert_table))
9510 * Translate the input set from bit masks to register aware bit masks
9514 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9524 static const struct inset_map inset_map_common[] = {
9525 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9526 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9527 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9528 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9529 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9530 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9531 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9532 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9533 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9534 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9535 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9536 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9537 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9538 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9539 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9540 {I40E_INSET_TUNNEL_DMAC,
9541 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9542 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9543 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9544 {I40E_INSET_TUNNEL_SRC_PORT,
9545 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9546 {I40E_INSET_TUNNEL_DST_PORT,
9547 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9548 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9549 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9550 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9551 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9552 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9553 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9554 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9555 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9556 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9559 /* some different registers map in x722*/
9560 static const struct inset_map inset_map_diff_x722[] = {
9561 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9562 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9563 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9564 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9567 static const struct inset_map inset_map_diff_not_x722[] = {
9568 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9569 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9570 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9571 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9577 /* Translate input set to register aware inset */
9578 if (type == I40E_MAC_X722) {
9579 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9580 if (input & inset_map_diff_x722[i].inset)
9581 val |= inset_map_diff_x722[i].inset_reg;
9584 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9585 if (input & inset_map_diff_not_x722[i].inset)
9586 val |= inset_map_diff_not_x722[i].inset_reg;
9590 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9591 if (input & inset_map_common[i].inset)
9592 val |= inset_map_common[i].inset_reg;
9599 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9602 uint64_t inset_need_mask = inset;
9604 static const struct {
9607 } inset_mask_map[] = {
9608 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9609 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9610 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9611 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9612 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9613 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9614 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9615 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9618 if (!inset || !mask || !nb_elem)
9621 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9622 /* Clear the inset bit, if no MASK is required,
9623 * for example proto + ttl
9625 if ((inset & inset_mask_map[i].inset) ==
9626 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9627 inset_need_mask &= ~inset_mask_map[i].inset;
9628 if (!inset_need_mask)
9631 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9632 if ((inset_need_mask & inset_mask_map[i].inset) ==
9633 inset_mask_map[i].inset) {
9634 if (idx >= nb_elem) {
9635 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9638 mask[idx] = inset_mask_map[i].mask;
9647 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9649 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9651 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9653 i40e_write_rx_ctl(hw, addr, val);
9654 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9655 (uint32_t)i40e_read_rx_ctl(hw, addr));
9659 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9661 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9662 struct rte_eth_dev *dev;
9664 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9666 i40e_write_rx_ctl(hw, addr, val);
9667 PMD_DRV_LOG(WARNING,
9668 "i40e device %s changed global register [0x%08x]."
9669 " original: 0x%08x, new: 0x%08x",
9670 dev->device->name, addr, reg,
9671 (uint32_t)i40e_read_rx_ctl(hw, addr));
9676 i40e_filter_input_set_init(struct i40e_pf *pf)
9678 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9679 enum i40e_filter_pctype pctype;
9680 uint64_t input_set, inset_reg;
9681 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9685 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9686 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9687 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9689 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9692 input_set = i40e_get_default_input_set(pctype);
9694 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9695 I40E_INSET_MASK_NUM_REG);
9698 if (pf->support_multi_driver && num > 0) {
9699 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9702 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9705 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9706 (uint32_t)(inset_reg & UINT32_MAX));
9707 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9708 (uint32_t)((inset_reg >>
9709 I40E_32_BIT_WIDTH) & UINT32_MAX));
9710 if (!pf->support_multi_driver) {
9711 i40e_check_write_global_reg(hw,
9712 I40E_GLQF_HASH_INSET(0, pctype),
9713 (uint32_t)(inset_reg & UINT32_MAX));
9714 i40e_check_write_global_reg(hw,
9715 I40E_GLQF_HASH_INSET(1, pctype),
9716 (uint32_t)((inset_reg >>
9717 I40E_32_BIT_WIDTH) & UINT32_MAX));
9719 for (i = 0; i < num; i++) {
9720 i40e_check_write_global_reg(hw,
9721 I40E_GLQF_FD_MSK(i, pctype),
9723 i40e_check_write_global_reg(hw,
9724 I40E_GLQF_HASH_MSK(i, pctype),
9727 /*clear unused mask registers of the pctype */
9728 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9729 i40e_check_write_global_reg(hw,
9730 I40E_GLQF_FD_MSK(i, pctype),
9732 i40e_check_write_global_reg(hw,
9733 I40E_GLQF_HASH_MSK(i, pctype),
9737 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9739 I40E_WRITE_FLUSH(hw);
9741 /* store the default input set */
9742 if (!pf->support_multi_driver)
9743 pf->hash_input_set[pctype] = input_set;
9744 pf->fdir.input_set[pctype] = input_set;
9749 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9750 struct rte_eth_input_set_conf *conf)
9752 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9753 enum i40e_filter_pctype pctype;
9754 uint64_t input_set, inset_reg = 0;
9755 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9759 PMD_DRV_LOG(ERR, "Invalid pointer");
9762 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9763 conf->op != RTE_ETH_INPUT_SET_ADD) {
9764 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9768 if (pf->support_multi_driver) {
9769 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9773 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9774 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9775 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9779 if (hw->mac.type == I40E_MAC_X722) {
9780 /* get translated pctype value in fd pctype register */
9781 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9782 I40E_GLQF_FD_PCTYPES((int)pctype));
9785 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9788 PMD_DRV_LOG(ERR, "Failed to parse input set");
9792 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9793 /* get inset value in register */
9794 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9795 inset_reg <<= I40E_32_BIT_WIDTH;
9796 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9797 input_set |= pf->hash_input_set[pctype];
9799 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9800 I40E_INSET_MASK_NUM_REG);
9804 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9806 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9807 (uint32_t)(inset_reg & UINT32_MAX));
9808 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9809 (uint32_t)((inset_reg >>
9810 I40E_32_BIT_WIDTH) & UINT32_MAX));
9812 for (i = 0; i < num; i++)
9813 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9815 /*clear unused mask registers of the pctype */
9816 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9817 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9819 I40E_WRITE_FLUSH(hw);
9821 pf->hash_input_set[pctype] = input_set;
9826 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9827 struct rte_eth_input_set_conf *conf)
9829 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9830 enum i40e_filter_pctype pctype;
9831 uint64_t input_set, inset_reg = 0;
9832 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9836 PMD_DRV_LOG(ERR, "Invalid pointer");
9839 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9840 conf->op != RTE_ETH_INPUT_SET_ADD) {
9841 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9845 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9847 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9848 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9852 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9855 PMD_DRV_LOG(ERR, "Failed to parse input set");
9859 /* get inset value in register */
9860 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9861 inset_reg <<= I40E_32_BIT_WIDTH;
9862 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9864 /* Can not change the inset reg for flex payload for fdir,
9865 * it is done by writing I40E_PRTQF_FD_FLXINSET
9866 * in i40e_set_flex_mask_on_pctype.
9868 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9869 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9871 input_set |= pf->fdir.input_set[pctype];
9872 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9873 I40E_INSET_MASK_NUM_REG);
9876 if (pf->support_multi_driver && num > 0) {
9877 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9881 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9883 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9884 (uint32_t)(inset_reg & UINT32_MAX));
9885 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9886 (uint32_t)((inset_reg >>
9887 I40E_32_BIT_WIDTH) & UINT32_MAX));
9889 if (!pf->support_multi_driver) {
9890 for (i = 0; i < num; i++)
9891 i40e_check_write_global_reg(hw,
9892 I40E_GLQF_FD_MSK(i, pctype),
9894 /*clear unused mask registers of the pctype */
9895 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9896 i40e_check_write_global_reg(hw,
9897 I40E_GLQF_FD_MSK(i, pctype),
9900 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9902 I40E_WRITE_FLUSH(hw);
9904 pf->fdir.input_set[pctype] = input_set;
9909 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9914 PMD_DRV_LOG(ERR, "Invalid pointer");
9918 switch (info->info_type) {
9919 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9920 i40e_get_symmetric_hash_enable_per_port(hw,
9921 &(info->info.enable));
9923 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9924 ret = i40e_get_hash_filter_global_config(hw,
9925 &(info->info.global_conf));
9928 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9938 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9943 PMD_DRV_LOG(ERR, "Invalid pointer");
9947 switch (info->info_type) {
9948 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9949 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9951 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9952 ret = i40e_set_hash_filter_global_config(hw,
9953 &(info->info.global_conf));
9955 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9956 ret = i40e_hash_filter_inset_select(hw,
9957 &(info->info.input_set_conf));
9961 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9970 /* Operations for hash function */
9972 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9973 enum rte_filter_op filter_op,
9976 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9979 switch (filter_op) {
9980 case RTE_ETH_FILTER_NOP:
9982 case RTE_ETH_FILTER_GET:
9983 ret = i40e_hash_filter_get(hw,
9984 (struct rte_eth_hash_filter_info *)arg);
9986 case RTE_ETH_FILTER_SET:
9987 ret = i40e_hash_filter_set(hw,
9988 (struct rte_eth_hash_filter_info *)arg);
9991 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10000 /* Convert ethertype filter structure */
10002 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10003 struct i40e_ethertype_filter *filter)
10005 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10006 RTE_ETHER_ADDR_LEN);
10007 filter->input.ether_type = input->ether_type;
10008 filter->flags = input->flags;
10009 filter->queue = input->queue;
10014 /* Check if there exists the ehtertype filter */
10015 struct i40e_ethertype_filter *
10016 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10017 const struct i40e_ethertype_filter_input *input)
10021 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10025 return ethertype_rule->hash_map[ret];
10028 /* Add ethertype filter in SW list */
10030 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10031 struct i40e_ethertype_filter *filter)
10033 struct i40e_ethertype_rule *rule = &pf->ethertype;
10036 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10039 "Failed to insert ethertype filter"
10040 " to hash table %d!",
10044 rule->hash_map[ret] = filter;
10046 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10051 /* Delete ethertype filter in SW list */
10053 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10054 struct i40e_ethertype_filter_input *input)
10056 struct i40e_ethertype_rule *rule = &pf->ethertype;
10057 struct i40e_ethertype_filter *filter;
10060 ret = rte_hash_del_key(rule->hash_table, input);
10063 "Failed to delete ethertype filter"
10064 " to hash table %d!",
10068 filter = rule->hash_map[ret];
10069 rule->hash_map[ret] = NULL;
10071 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10078 * Configure ethertype filter, which can director packet by filtering
10079 * with mac address and ether_type or only ether_type
10082 i40e_ethertype_filter_set(struct i40e_pf *pf,
10083 struct rte_eth_ethertype_filter *filter,
10086 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10087 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10088 struct i40e_ethertype_filter *ethertype_filter, *node;
10089 struct i40e_ethertype_filter check_filter;
10090 struct i40e_control_filter_stats stats;
10091 uint16_t flags = 0;
10094 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10095 PMD_DRV_LOG(ERR, "Invalid queue ID");
10098 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10099 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10101 "unsupported ether_type(0x%04x) in control packet filter.",
10102 filter->ether_type);
10105 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10106 PMD_DRV_LOG(WARNING,
10107 "filter vlan ether_type in first tag is not supported.");
10109 /* Check if there is the filter in SW list */
10110 memset(&check_filter, 0, sizeof(check_filter));
10111 i40e_ethertype_filter_convert(filter, &check_filter);
10112 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10113 &check_filter.input);
10115 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10119 if (!add && !node) {
10120 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10124 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10125 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10126 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10127 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10128 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10130 memset(&stats, 0, sizeof(stats));
10131 ret = i40e_aq_add_rem_control_packet_filter(hw,
10132 filter->mac_addr.addr_bytes,
10133 filter->ether_type, flags,
10134 pf->main_vsi->seid,
10135 filter->queue, add, &stats, NULL);
10138 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10139 ret, stats.mac_etype_used, stats.etype_used,
10140 stats.mac_etype_free, stats.etype_free);
10144 /* Add or delete a filter in SW list */
10146 ethertype_filter = rte_zmalloc("ethertype_filter",
10147 sizeof(*ethertype_filter), 0);
10148 if (ethertype_filter == NULL) {
10149 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10153 rte_memcpy(ethertype_filter, &check_filter,
10154 sizeof(check_filter));
10155 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10157 rte_free(ethertype_filter);
10159 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10166 * Handle operations for ethertype filter.
10169 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10170 enum rte_filter_op filter_op,
10173 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10176 if (filter_op == RTE_ETH_FILTER_NOP)
10180 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10185 switch (filter_op) {
10186 case RTE_ETH_FILTER_ADD:
10187 ret = i40e_ethertype_filter_set(pf,
10188 (struct rte_eth_ethertype_filter *)arg,
10191 case RTE_ETH_FILTER_DELETE:
10192 ret = i40e_ethertype_filter_set(pf,
10193 (struct rte_eth_ethertype_filter *)arg,
10197 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10205 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10206 enum rte_filter_type filter_type,
10207 enum rte_filter_op filter_op,
10215 switch (filter_type) {
10216 case RTE_ETH_FILTER_NONE:
10217 /* For global configuration */
10218 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10220 case RTE_ETH_FILTER_HASH:
10221 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10223 case RTE_ETH_FILTER_MACVLAN:
10224 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10226 case RTE_ETH_FILTER_ETHERTYPE:
10227 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10229 case RTE_ETH_FILTER_TUNNEL:
10230 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10232 case RTE_ETH_FILTER_FDIR:
10233 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10235 case RTE_ETH_FILTER_GENERIC:
10236 if (filter_op != RTE_ETH_FILTER_GET)
10238 *(const void **)arg = &i40e_flow_ops;
10241 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10251 * Check and enable Extended Tag.
10252 * Enabling Extended Tag is important for 40G performance.
10255 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10257 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10261 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10264 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10268 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10269 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10274 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10277 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10281 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10282 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10285 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10286 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10289 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10296 * As some registers wouldn't be reset unless a global hardware reset,
10297 * hardware initialization is needed to put those registers into an
10298 * expected initial state.
10301 i40e_hw_init(struct rte_eth_dev *dev)
10303 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10305 i40e_enable_extended_tag(dev);
10307 /* clear the PF Queue Filter control register */
10308 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10310 /* Disable symmetric hash per port */
10311 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10315 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10316 * however this function will return only one highest pctype index,
10317 * which is not quite correct. This is known problem of i40e driver
10318 * and needs to be fixed later.
10320 enum i40e_filter_pctype
10321 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10324 uint64_t pctype_mask;
10326 if (flow_type < I40E_FLOW_TYPE_MAX) {
10327 pctype_mask = adapter->pctypes_tbl[flow_type];
10328 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10329 if (pctype_mask & (1ULL << i))
10330 return (enum i40e_filter_pctype)i;
10333 return I40E_FILTER_PCTYPE_INVALID;
10337 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10338 enum i40e_filter_pctype pctype)
10341 uint64_t pctype_mask = 1ULL << pctype;
10343 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10345 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10349 return RTE_ETH_FLOW_UNKNOWN;
10353 * On X710, performance number is far from the expectation on recent firmware
10354 * versions; on XL710, performance number is also far from the expectation on
10355 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10356 * mode is enabled and port MAC address is equal to the packet destination MAC
10357 * address. The fix for this issue may not be integrated in the following
10358 * firmware version. So the workaround in software driver is needed. It needs
10359 * to modify the initial values of 3 internal only registers for both X710 and
10360 * XL710. Note that the values for X710 or XL710 could be different, and the
10361 * workaround can be removed when it is fixed in firmware in the future.
10364 /* For both X710 and XL710 */
10365 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10366 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10367 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10369 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10370 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10373 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10374 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10377 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10379 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10380 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10383 * GL_SWR_PM_UP_THR:
10384 * The value is not impacted from the link speed, its value is set according
10385 * to the total number of ports for a better pipe-monitor configuration.
10388 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10390 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10391 .device_id = (dev), \
10392 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10394 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10395 .device_id = (dev), \
10396 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10398 static const struct {
10399 uint16_t device_id;
10401 } swr_pm_table[] = {
10402 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10403 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10404 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10405 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10407 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10408 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10409 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10410 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10411 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10412 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10413 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10417 if (value == NULL) {
10418 PMD_DRV_LOG(ERR, "value is NULL");
10422 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10423 if (hw->device_id == swr_pm_table[i].device_id) {
10424 *value = swr_pm_table[i].val;
10426 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10428 hw->device_id, *value);
10437 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10439 enum i40e_status_code status;
10440 struct i40e_aq_get_phy_abilities_resp phy_ab;
10441 int ret = -ENOTSUP;
10444 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10448 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10451 rte_delay_us(100000);
10453 status = i40e_aq_get_phy_capabilities(hw, false,
10454 true, &phy_ab, NULL);
10462 i40e_configure_registers(struct i40e_hw *hw)
10468 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10469 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10470 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10476 for (i = 0; i < RTE_DIM(reg_table); i++) {
10477 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10478 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10480 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10481 else /* For X710/XL710/XXV710 */
10482 if (hw->aq.fw_maj_ver < 6)
10484 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10487 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10490 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10491 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10493 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10494 else /* For X710/XL710/XXV710 */
10496 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10499 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10502 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10503 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10504 "GL_SWR_PM_UP_THR value fixup",
10509 reg_table[i].val = cfg_val;
10512 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10515 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10516 reg_table[i].addr);
10519 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10520 reg_table[i].addr, reg);
10521 if (reg == reg_table[i].val)
10524 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10525 reg_table[i].val, NULL);
10528 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10529 reg_table[i].val, reg_table[i].addr);
10532 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10533 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10537 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10538 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10539 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10540 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10542 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10547 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10548 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10552 /* Configure for double VLAN RX stripping */
10553 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10554 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10555 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10556 ret = i40e_aq_debug_write_register(hw,
10557 I40E_VSI_TSR(vsi->vsi_id),
10560 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10562 return I40E_ERR_CONFIG;
10566 /* Configure for double VLAN TX insertion */
10567 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10568 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10569 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10570 ret = i40e_aq_debug_write_register(hw,
10571 I40E_VSI_L2TAGSTXVALID(
10572 vsi->vsi_id), reg, NULL);
10575 "Failed to update VSI_L2TAGSTXVALID[%d]",
10577 return I40E_ERR_CONFIG;
10585 * i40e_aq_add_mirror_rule
10586 * @hw: pointer to the hardware structure
10587 * @seid: VEB seid to add mirror rule to
10588 * @dst_id: destination vsi seid
10589 * @entries: Buffer which contains the entities to be mirrored
10590 * @count: number of entities contained in the buffer
10591 * @rule_id:the rule_id of the rule to be added
10593 * Add a mirror rule for a given veb.
10596 static enum i40e_status_code
10597 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10598 uint16_t seid, uint16_t dst_id,
10599 uint16_t rule_type, uint16_t *entries,
10600 uint16_t count, uint16_t *rule_id)
10602 struct i40e_aq_desc desc;
10603 struct i40e_aqc_add_delete_mirror_rule cmd;
10604 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10605 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10608 enum i40e_status_code status;
10610 i40e_fill_default_direct_cmd_desc(&desc,
10611 i40e_aqc_opc_add_mirror_rule);
10612 memset(&cmd, 0, sizeof(cmd));
10614 buff_len = sizeof(uint16_t) * count;
10615 desc.datalen = rte_cpu_to_le_16(buff_len);
10617 desc.flags |= rte_cpu_to_le_16(
10618 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10619 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10620 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10621 cmd.num_entries = rte_cpu_to_le_16(count);
10622 cmd.seid = rte_cpu_to_le_16(seid);
10623 cmd.destination = rte_cpu_to_le_16(dst_id);
10625 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10626 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10628 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10629 hw->aq.asq_last_status, resp->rule_id,
10630 resp->mirror_rules_used, resp->mirror_rules_free);
10631 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10637 * i40e_aq_del_mirror_rule
10638 * @hw: pointer to the hardware structure
10639 * @seid: VEB seid to add mirror rule to
10640 * @entries: Buffer which contains the entities to be mirrored
10641 * @count: number of entities contained in the buffer
10642 * @rule_id:the rule_id of the rule to be delete
10644 * Delete a mirror rule for a given veb.
10647 static enum i40e_status_code
10648 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10649 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10650 uint16_t count, uint16_t rule_id)
10652 struct i40e_aq_desc desc;
10653 struct i40e_aqc_add_delete_mirror_rule cmd;
10654 uint16_t buff_len = 0;
10655 enum i40e_status_code status;
10658 i40e_fill_default_direct_cmd_desc(&desc,
10659 i40e_aqc_opc_delete_mirror_rule);
10660 memset(&cmd, 0, sizeof(cmd));
10661 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10662 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10664 cmd.num_entries = count;
10665 buff_len = sizeof(uint16_t) * count;
10666 desc.datalen = rte_cpu_to_le_16(buff_len);
10667 buff = (void *)entries;
10669 /* rule id is filled in destination field for deleting mirror rule */
10670 cmd.destination = rte_cpu_to_le_16(rule_id);
10672 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10673 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10674 cmd.seid = rte_cpu_to_le_16(seid);
10676 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10677 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10683 * i40e_mirror_rule_set
10684 * @dev: pointer to the hardware structure
10685 * @mirror_conf: mirror rule info
10686 * @sw_id: mirror rule's sw_id
10687 * @on: enable/disable
10689 * set a mirror rule.
10693 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10694 struct rte_eth_mirror_conf *mirror_conf,
10695 uint8_t sw_id, uint8_t on)
10697 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10699 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10700 struct i40e_mirror_rule *parent = NULL;
10701 uint16_t seid, dst_seid, rule_id;
10705 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10707 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10709 "mirror rule can not be configured without veb or vfs.");
10712 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10713 PMD_DRV_LOG(ERR, "mirror table is full.");
10716 if (mirror_conf->dst_pool > pf->vf_num) {
10717 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10718 mirror_conf->dst_pool);
10722 seid = pf->main_vsi->veb->seid;
10724 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10725 if (sw_id <= it->index) {
10731 if (mirr_rule && sw_id == mirr_rule->index) {
10733 PMD_DRV_LOG(ERR, "mirror rule exists.");
10736 ret = i40e_aq_del_mirror_rule(hw, seid,
10737 mirr_rule->rule_type,
10738 mirr_rule->entries,
10739 mirr_rule->num_entries, mirr_rule->id);
10742 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10743 ret, hw->aq.asq_last_status);
10746 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10747 rte_free(mirr_rule);
10748 pf->nb_mirror_rule--;
10752 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10756 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10757 sizeof(struct i40e_mirror_rule) , 0);
10759 PMD_DRV_LOG(ERR, "failed to allocate memory");
10760 return I40E_ERR_NO_MEMORY;
10762 switch (mirror_conf->rule_type) {
10763 case ETH_MIRROR_VLAN:
10764 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10765 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10766 mirr_rule->entries[j] =
10767 mirror_conf->vlan.vlan_id[i];
10772 PMD_DRV_LOG(ERR, "vlan is not specified.");
10773 rte_free(mirr_rule);
10776 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10778 case ETH_MIRROR_VIRTUAL_POOL_UP:
10779 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10780 /* check if the specified pool bit is out of range */
10781 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10782 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10783 rte_free(mirr_rule);
10786 for (i = 0, j = 0; i < pf->vf_num; i++) {
10787 if (mirror_conf->pool_mask & (1ULL << i)) {
10788 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10792 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10793 /* add pf vsi to entries */
10794 mirr_rule->entries[j] = pf->main_vsi_seid;
10798 PMD_DRV_LOG(ERR, "pool is not specified.");
10799 rte_free(mirr_rule);
10802 /* egress and ingress in aq commands means from switch but not port */
10803 mirr_rule->rule_type =
10804 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10805 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10806 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10808 case ETH_MIRROR_UPLINK_PORT:
10809 /* egress and ingress in aq commands means from switch but not port*/
10810 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10812 case ETH_MIRROR_DOWNLINK_PORT:
10813 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10816 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10817 mirror_conf->rule_type);
10818 rte_free(mirr_rule);
10822 /* If the dst_pool is equal to vf_num, consider it as PF */
10823 if (mirror_conf->dst_pool == pf->vf_num)
10824 dst_seid = pf->main_vsi_seid;
10826 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10828 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10829 mirr_rule->rule_type, mirr_rule->entries,
10833 "failed to add mirror rule: ret = %d, aq_err = %d.",
10834 ret, hw->aq.asq_last_status);
10835 rte_free(mirr_rule);
10839 mirr_rule->index = sw_id;
10840 mirr_rule->num_entries = j;
10841 mirr_rule->id = rule_id;
10842 mirr_rule->dst_vsi_seid = dst_seid;
10845 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10847 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10849 pf->nb_mirror_rule++;
10854 * i40e_mirror_rule_reset
10855 * @dev: pointer to the device
10856 * @sw_id: mirror rule's sw_id
10858 * reset a mirror rule.
10862 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10864 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10865 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10866 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10870 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10872 seid = pf->main_vsi->veb->seid;
10874 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10875 if (sw_id == it->index) {
10881 ret = i40e_aq_del_mirror_rule(hw, seid,
10882 mirr_rule->rule_type,
10883 mirr_rule->entries,
10884 mirr_rule->num_entries, mirr_rule->id);
10887 "failed to remove mirror rule: status = %d, aq_err = %d.",
10888 ret, hw->aq.asq_last_status);
10891 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10892 rte_free(mirr_rule);
10893 pf->nb_mirror_rule--;
10895 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10902 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10904 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10905 uint64_t systim_cycles;
10907 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10908 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10911 return systim_cycles;
10915 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10918 uint64_t rx_tstamp;
10920 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10921 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10928 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10931 uint64_t tx_tstamp;
10933 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10934 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10941 i40e_start_timecounters(struct rte_eth_dev *dev)
10943 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10944 struct i40e_adapter *adapter = dev->data->dev_private;
10945 struct rte_eth_link link;
10946 uint32_t tsync_inc_l;
10947 uint32_t tsync_inc_h;
10949 /* Get current link speed. */
10950 i40e_dev_link_update(dev, 1);
10951 rte_eth_linkstatus_get(dev, &link);
10953 switch (link.link_speed) {
10954 case ETH_SPEED_NUM_40G:
10955 case ETH_SPEED_NUM_25G:
10956 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10957 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10959 case ETH_SPEED_NUM_10G:
10960 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10961 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10963 case ETH_SPEED_NUM_1G:
10964 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10965 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10972 /* Set the timesync increment value. */
10973 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10974 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10976 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10977 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10978 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10980 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10981 adapter->systime_tc.cc_shift = 0;
10982 adapter->systime_tc.nsec_mask = 0;
10984 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10985 adapter->rx_tstamp_tc.cc_shift = 0;
10986 adapter->rx_tstamp_tc.nsec_mask = 0;
10988 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10989 adapter->tx_tstamp_tc.cc_shift = 0;
10990 adapter->tx_tstamp_tc.nsec_mask = 0;
10994 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10996 struct i40e_adapter *adapter = dev->data->dev_private;
10998 adapter->systime_tc.nsec += delta;
10999 adapter->rx_tstamp_tc.nsec += delta;
11000 adapter->tx_tstamp_tc.nsec += delta;
11006 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11009 struct i40e_adapter *adapter = dev->data->dev_private;
11011 ns = rte_timespec_to_ns(ts);
11013 /* Set the timecounters to a new value. */
11014 adapter->systime_tc.nsec = ns;
11015 adapter->rx_tstamp_tc.nsec = ns;
11016 adapter->tx_tstamp_tc.nsec = ns;
11022 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11024 uint64_t ns, systime_cycles;
11025 struct i40e_adapter *adapter = dev->data->dev_private;
11027 systime_cycles = i40e_read_systime_cyclecounter(dev);
11028 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11029 *ts = rte_ns_to_timespec(ns);
11035 i40e_timesync_enable(struct rte_eth_dev *dev)
11037 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11038 uint32_t tsync_ctl_l;
11039 uint32_t tsync_ctl_h;
11041 /* Stop the timesync system time. */
11042 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11043 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11044 /* Reset the timesync system time value. */
11045 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11046 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11048 i40e_start_timecounters(dev);
11050 /* Clear timesync registers. */
11051 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11052 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11053 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11054 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11055 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11056 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11058 /* Enable timestamping of PTP packets. */
11059 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11060 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11062 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11063 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11064 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11066 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11067 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11073 i40e_timesync_disable(struct rte_eth_dev *dev)
11075 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11076 uint32_t tsync_ctl_l;
11077 uint32_t tsync_ctl_h;
11079 /* Disable timestamping of transmitted PTP packets. */
11080 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11081 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11083 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11084 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11086 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11087 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11089 /* Reset the timesync increment value. */
11090 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11091 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11097 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11098 struct timespec *timestamp, uint32_t flags)
11100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101 struct i40e_adapter *adapter = dev->data->dev_private;
11102 uint32_t sync_status;
11103 uint32_t index = flags & 0x03;
11104 uint64_t rx_tstamp_cycles;
11107 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11108 if ((sync_status & (1 << index)) == 0)
11111 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11112 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11113 *timestamp = rte_ns_to_timespec(ns);
11119 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11120 struct timespec *timestamp)
11122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11123 struct i40e_adapter *adapter = dev->data->dev_private;
11124 uint32_t sync_status;
11125 uint64_t tx_tstamp_cycles;
11128 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11129 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11132 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11133 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11134 *timestamp = rte_ns_to_timespec(ns);
11140 * i40e_parse_dcb_configure - parse dcb configure from user
11141 * @dev: the device being configured
11142 * @dcb_cfg: pointer of the result of parse
11143 * @*tc_map: bit map of enabled traffic classes
11145 * Returns 0 on success, negative value on failure
11148 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11149 struct i40e_dcbx_config *dcb_cfg,
11152 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11153 uint8_t i, tc_bw, bw_lf;
11155 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11157 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11158 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11159 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11163 /* assume each tc has the same bw */
11164 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11165 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11166 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11167 /* to ensure the sum of tcbw is equal to 100 */
11168 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11169 for (i = 0; i < bw_lf; i++)
11170 dcb_cfg->etscfg.tcbwtable[i]++;
11172 /* assume each tc has the same Transmission Selection Algorithm */
11173 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11174 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11176 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11177 dcb_cfg->etscfg.prioritytable[i] =
11178 dcb_rx_conf->dcb_tc[i];
11180 /* FW needs one App to configure HW */
11181 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11182 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11183 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11184 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11186 if (dcb_rx_conf->nb_tcs == 0)
11187 *tc_map = 1; /* tc0 only */
11189 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11191 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11192 dcb_cfg->pfc.willing = 0;
11193 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11194 dcb_cfg->pfc.pfcenable = *tc_map;
11200 static enum i40e_status_code
11201 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11202 struct i40e_aqc_vsi_properties_data *info,
11203 uint8_t enabled_tcmap)
11205 enum i40e_status_code ret;
11206 int i, total_tc = 0;
11207 uint16_t qpnum_per_tc, bsf, qp_idx;
11208 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11209 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11210 uint16_t used_queues;
11212 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11213 if (ret != I40E_SUCCESS)
11216 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11217 if (enabled_tcmap & (1 << i))
11222 vsi->enabled_tc = enabled_tcmap;
11224 /* different VSI has different queues assigned */
11225 if (vsi->type == I40E_VSI_MAIN)
11226 used_queues = dev_data->nb_rx_queues -
11227 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11228 else if (vsi->type == I40E_VSI_VMDQ2)
11229 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11231 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11232 return I40E_ERR_NO_AVAILABLE_VSI;
11235 qpnum_per_tc = used_queues / total_tc;
11236 /* Number of queues per enabled TC */
11237 if (qpnum_per_tc == 0) {
11238 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11239 return I40E_ERR_INVALID_QP_ID;
11241 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11242 I40E_MAX_Q_PER_TC);
11243 bsf = rte_bsf32(qpnum_per_tc);
11246 * Configure TC and queue mapping parameters, for enabled TC,
11247 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11248 * default queue will serve it.
11251 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11252 if (vsi->enabled_tc & (1 << i)) {
11253 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11254 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11255 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11256 qp_idx += qpnum_per_tc;
11258 info->tc_mapping[i] = 0;
11261 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11262 if (vsi->type == I40E_VSI_SRIOV) {
11263 info->mapping_flags |=
11264 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11265 for (i = 0; i < vsi->nb_qps; i++)
11266 info->queue_mapping[i] =
11267 rte_cpu_to_le_16(vsi->base_queue + i);
11269 info->mapping_flags |=
11270 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11271 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11273 info->valid_sections |=
11274 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11276 return I40E_SUCCESS;
11280 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11281 * @veb: VEB to be configured
11282 * @tc_map: enabled TC bitmap
11284 * Returns 0 on success, negative value on failure
11286 static enum i40e_status_code
11287 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11289 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11290 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11291 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11292 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11293 enum i40e_status_code ret = I40E_SUCCESS;
11297 /* Check if enabled_tc is same as existing or new TCs */
11298 if (veb->enabled_tc == tc_map)
11301 /* configure tc bandwidth */
11302 memset(&veb_bw, 0, sizeof(veb_bw));
11303 veb_bw.tc_valid_bits = tc_map;
11304 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11305 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11306 if (tc_map & BIT_ULL(i))
11307 veb_bw.tc_bw_share_credits[i] = 1;
11309 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11313 "AQ command Config switch_comp BW allocation per TC failed = %d",
11314 hw->aq.asq_last_status);
11318 memset(&ets_query, 0, sizeof(ets_query));
11319 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11321 if (ret != I40E_SUCCESS) {
11323 "Failed to get switch_comp ETS configuration %u",
11324 hw->aq.asq_last_status);
11327 memset(&bw_query, 0, sizeof(bw_query));
11328 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11330 if (ret != I40E_SUCCESS) {
11332 "Failed to get switch_comp bandwidth configuration %u",
11333 hw->aq.asq_last_status);
11337 /* store and print out BW info */
11338 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11339 veb->bw_info.bw_max = ets_query.tc_bw_max;
11340 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11341 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11342 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11343 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11344 I40E_16_BIT_WIDTH);
11345 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11346 veb->bw_info.bw_ets_share_credits[i] =
11347 bw_query.tc_bw_share_credits[i];
11348 veb->bw_info.bw_ets_credits[i] =
11349 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11350 /* 4 bits per TC, 4th bit is reserved */
11351 veb->bw_info.bw_ets_max[i] =
11352 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11353 RTE_LEN2MASK(3, uint8_t));
11354 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11355 veb->bw_info.bw_ets_share_credits[i]);
11356 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11357 veb->bw_info.bw_ets_credits[i]);
11358 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11359 veb->bw_info.bw_ets_max[i]);
11362 veb->enabled_tc = tc_map;
11369 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11370 * @vsi: VSI to be configured
11371 * @tc_map: enabled TC bitmap
11373 * Returns 0 on success, negative value on failure
11375 static enum i40e_status_code
11376 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11378 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11379 struct i40e_vsi_context ctxt;
11380 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11381 enum i40e_status_code ret = I40E_SUCCESS;
11384 /* Check if enabled_tc is same as existing or new TCs */
11385 if (vsi->enabled_tc == tc_map)
11388 /* configure tc bandwidth */
11389 memset(&bw_data, 0, sizeof(bw_data));
11390 bw_data.tc_valid_bits = tc_map;
11391 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11392 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11393 if (tc_map & BIT_ULL(i))
11394 bw_data.tc_bw_credits[i] = 1;
11396 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11399 "AQ command Config VSI BW allocation per TC failed = %d",
11400 hw->aq.asq_last_status);
11403 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11404 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11406 /* Update Queue Pairs Mapping for currently enabled UPs */
11407 ctxt.seid = vsi->seid;
11408 ctxt.pf_num = hw->pf_id;
11410 ctxt.uplink_seid = vsi->uplink_seid;
11411 ctxt.info = vsi->info;
11413 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11417 /* Update the VSI after updating the VSI queue-mapping information */
11418 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11420 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11421 hw->aq.asq_last_status);
11424 /* update the local VSI info with updated queue map */
11425 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11426 sizeof(vsi->info.tc_mapping));
11427 rte_memcpy(&vsi->info.queue_mapping,
11428 &ctxt.info.queue_mapping,
11429 sizeof(vsi->info.queue_mapping));
11430 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11431 vsi->info.valid_sections = 0;
11433 /* query and update current VSI BW information */
11434 ret = i40e_vsi_get_bw_config(vsi);
11437 "Failed updating vsi bw info, err %s aq_err %s",
11438 i40e_stat_str(hw, ret),
11439 i40e_aq_str(hw, hw->aq.asq_last_status));
11443 vsi->enabled_tc = tc_map;
11450 * i40e_dcb_hw_configure - program the dcb setting to hw
11451 * @pf: pf the configuration is taken on
11452 * @new_cfg: new configuration
11453 * @tc_map: enabled TC bitmap
11455 * Returns 0 on success, negative value on failure
11457 static enum i40e_status_code
11458 i40e_dcb_hw_configure(struct i40e_pf *pf,
11459 struct i40e_dcbx_config *new_cfg,
11462 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11463 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11464 struct i40e_vsi *main_vsi = pf->main_vsi;
11465 struct i40e_vsi_list *vsi_list;
11466 enum i40e_status_code ret;
11470 /* Use the FW API if FW > v4.4*/
11471 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11472 (hw->aq.fw_maj_ver >= 5))) {
11474 "FW < v4.4, can not use FW LLDP API to configure DCB");
11475 return I40E_ERR_FIRMWARE_API_VERSION;
11478 /* Check if need reconfiguration */
11479 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11480 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11481 return I40E_SUCCESS;
11484 /* Copy the new config to the current config */
11485 *old_cfg = *new_cfg;
11486 old_cfg->etsrec = old_cfg->etscfg;
11487 ret = i40e_set_dcb_config(hw);
11489 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11490 i40e_stat_str(hw, ret),
11491 i40e_aq_str(hw, hw->aq.asq_last_status));
11494 /* set receive Arbiter to RR mode and ETS scheme by default */
11495 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11496 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11497 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11498 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11499 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11500 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11501 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11502 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11503 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11504 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11505 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11506 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11507 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11509 /* get local mib to check whether it is configured correctly */
11511 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11512 /* Get Local DCB Config */
11513 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11514 &hw->local_dcbx_config);
11516 /* if Veb is created, need to update TC of it at first */
11517 if (main_vsi->veb) {
11518 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11520 PMD_INIT_LOG(WARNING,
11521 "Failed configuring TC for VEB seid=%d",
11522 main_vsi->veb->seid);
11524 /* Update each VSI */
11525 i40e_vsi_config_tc(main_vsi, tc_map);
11526 if (main_vsi->veb) {
11527 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11528 /* Beside main VSI and VMDQ VSIs, only enable default
11529 * TC for other VSIs
11531 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11532 ret = i40e_vsi_config_tc(vsi_list->vsi,
11535 ret = i40e_vsi_config_tc(vsi_list->vsi,
11536 I40E_DEFAULT_TCMAP);
11538 PMD_INIT_LOG(WARNING,
11539 "Failed configuring TC for VSI seid=%d",
11540 vsi_list->vsi->seid);
11544 return I40E_SUCCESS;
11548 * i40e_dcb_init_configure - initial dcb config
11549 * @dev: device being configured
11550 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11552 * Returns 0 on success, negative value on failure
11555 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11561 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11562 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11566 /* DCB initialization:
11567 * Update DCB configuration from the Firmware and configure
11568 * LLDP MIB change event.
11570 if (sw_dcb == TRUE) {
11571 if (i40e_need_stop_lldp(dev)) {
11572 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11573 if (ret != I40E_SUCCESS)
11574 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11577 ret = i40e_init_dcb(hw);
11578 /* If lldp agent is stopped, the return value from
11579 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11580 * adminq status. Otherwise, it should return success.
11582 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11583 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11584 memset(&hw->local_dcbx_config, 0,
11585 sizeof(struct i40e_dcbx_config));
11586 /* set dcb default configuration */
11587 hw->local_dcbx_config.etscfg.willing = 0;
11588 hw->local_dcbx_config.etscfg.maxtcs = 0;
11589 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11590 hw->local_dcbx_config.etscfg.tsatable[0] =
11592 /* all UPs mapping to TC0 */
11593 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11594 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11595 hw->local_dcbx_config.etsrec =
11596 hw->local_dcbx_config.etscfg;
11597 hw->local_dcbx_config.pfc.willing = 0;
11598 hw->local_dcbx_config.pfc.pfccap =
11599 I40E_MAX_TRAFFIC_CLASS;
11600 /* FW needs one App to configure HW */
11601 hw->local_dcbx_config.numapps = 1;
11602 hw->local_dcbx_config.app[0].selector =
11603 I40E_APP_SEL_ETHTYPE;
11604 hw->local_dcbx_config.app[0].priority = 3;
11605 hw->local_dcbx_config.app[0].protocolid =
11606 I40E_APP_PROTOID_FCOE;
11607 ret = i40e_set_dcb_config(hw);
11610 "default dcb config fails. err = %d, aq_err = %d.",
11611 ret, hw->aq.asq_last_status);
11616 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11617 ret, hw->aq.asq_last_status);
11621 ret = i40e_aq_start_lldp(hw, NULL);
11622 if (ret != I40E_SUCCESS)
11623 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11625 ret = i40e_init_dcb(hw);
11627 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11629 "HW doesn't support DCBX offload.");
11634 "DCBX configuration failed, err = %d, aq_err = %d.",
11635 ret, hw->aq.asq_last_status);
11643 * i40e_dcb_setup - setup dcb related config
11644 * @dev: device being configured
11646 * Returns 0 on success, negative value on failure
11649 i40e_dcb_setup(struct rte_eth_dev *dev)
11651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11652 struct i40e_dcbx_config dcb_cfg;
11653 uint8_t tc_map = 0;
11656 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11657 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11661 if (pf->vf_num != 0)
11662 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11664 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11666 PMD_INIT_LOG(ERR, "invalid dcb config");
11669 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11671 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11679 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11680 struct rte_eth_dcb_info *dcb_info)
11682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11684 struct i40e_vsi *vsi = pf->main_vsi;
11685 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11686 uint16_t bsf, tc_mapping;
11689 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11690 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11692 dcb_info->nb_tcs = 1;
11693 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11694 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11695 for (i = 0; i < dcb_info->nb_tcs; i++)
11696 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11698 /* get queue mapping if vmdq is disabled */
11699 if (!pf->nb_cfg_vmdq_vsi) {
11700 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11701 if (!(vsi->enabled_tc & (1 << i)))
11703 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11704 dcb_info->tc_queue.tc_rxq[j][i].base =
11705 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11706 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11707 dcb_info->tc_queue.tc_txq[j][i].base =
11708 dcb_info->tc_queue.tc_rxq[j][i].base;
11709 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11710 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11711 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11712 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11713 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11718 /* get queue mapping if vmdq is enabled */
11720 vsi = pf->vmdq[j].vsi;
11721 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11722 if (!(vsi->enabled_tc & (1 << i)))
11724 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11725 dcb_info->tc_queue.tc_rxq[j][i].base =
11726 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11727 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11728 dcb_info->tc_queue.tc_txq[j][i].base =
11729 dcb_info->tc_queue.tc_rxq[j][i].base;
11730 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11731 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11732 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11733 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11734 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11737 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11742 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11744 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11745 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11746 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11747 uint16_t msix_intr;
11749 msix_intr = intr_handle->intr_vec[queue_id];
11750 if (msix_intr == I40E_MISC_VEC_ID)
11751 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11752 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11753 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11754 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11757 I40E_PFINT_DYN_CTLN(msix_intr -
11758 I40E_RX_VEC_START),
11759 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11760 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11761 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11763 I40E_WRITE_FLUSH(hw);
11764 rte_intr_ack(&pci_dev->intr_handle);
11770 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11772 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11773 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11775 uint16_t msix_intr;
11777 msix_intr = intr_handle->intr_vec[queue_id];
11778 if (msix_intr == I40E_MISC_VEC_ID)
11779 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11780 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11783 I40E_PFINT_DYN_CTLN(msix_intr -
11784 I40E_RX_VEC_START),
11785 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11786 I40E_WRITE_FLUSH(hw);
11792 * This function is used to check if the register is valid.
11793 * Below is the valid registers list for X722 only:
11797 * 0x208e00--0x209000
11798 * 0x20be00--0x20c000
11799 * 0x263c00--0x264000
11800 * 0x265c00--0x266000
11802 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11804 if ((type != I40E_MAC_X722) &&
11805 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11806 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11807 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11808 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11809 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11810 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11811 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11817 static int i40e_get_regs(struct rte_eth_dev *dev,
11818 struct rte_dev_reg_info *regs)
11820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11821 uint32_t *ptr_data = regs->data;
11822 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11823 const struct i40e_reg_info *reg_info;
11825 if (ptr_data == NULL) {
11826 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11827 regs->width = sizeof(uint32_t);
11831 /* The first few registers have to be read using AQ operations */
11833 while (i40e_regs_adminq[reg_idx].name) {
11834 reg_info = &i40e_regs_adminq[reg_idx++];
11835 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11837 arr_idx2 <= reg_info->count2;
11839 reg_offset = arr_idx * reg_info->stride1 +
11840 arr_idx2 * reg_info->stride2;
11841 reg_offset += reg_info->base_addr;
11842 ptr_data[reg_offset >> 2] =
11843 i40e_read_rx_ctl(hw, reg_offset);
11847 /* The remaining registers can be read using primitives */
11849 while (i40e_regs_others[reg_idx].name) {
11850 reg_info = &i40e_regs_others[reg_idx++];
11851 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11853 arr_idx2 <= reg_info->count2;
11855 reg_offset = arr_idx * reg_info->stride1 +
11856 arr_idx2 * reg_info->stride2;
11857 reg_offset += reg_info->base_addr;
11858 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11859 ptr_data[reg_offset >> 2] = 0;
11861 ptr_data[reg_offset >> 2] =
11862 I40E_READ_REG(hw, reg_offset);
11869 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11873 /* Convert word count to byte count */
11874 return hw->nvm.sr_size << 1;
11877 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11878 struct rte_dev_eeprom_info *eeprom)
11880 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11881 uint16_t *data = eeprom->data;
11882 uint16_t offset, length, cnt_words;
11885 offset = eeprom->offset >> 1;
11886 length = eeprom->length >> 1;
11887 cnt_words = length;
11889 if (offset > hw->nvm.sr_size ||
11890 offset + length > hw->nvm.sr_size) {
11891 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11895 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11897 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11898 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11899 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11906 static int i40e_get_module_info(struct rte_eth_dev *dev,
11907 struct rte_eth_dev_module_info *modinfo)
11909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11910 uint32_t sff8472_comp = 0;
11911 uint32_t sff8472_swap = 0;
11912 uint32_t sff8636_rev = 0;
11913 i40e_status status;
11916 /* Check if firmware supports reading module EEPROM. */
11917 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11919 "Module EEPROM memory read not supported. "
11920 "Please update the NVM image.\n");
11924 status = i40e_update_link_info(hw);
11928 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11930 "Cannot read module EEPROM memory. "
11931 "No module connected.\n");
11935 type = hw->phy.link_info.module_type[0];
11938 case I40E_MODULE_TYPE_SFP:
11939 status = i40e_aq_get_phy_register(hw,
11940 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11941 I40E_I2C_EEPROM_DEV_ADDR, 1,
11942 I40E_MODULE_SFF_8472_COMP,
11943 &sff8472_comp, NULL);
11947 status = i40e_aq_get_phy_register(hw,
11948 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11949 I40E_I2C_EEPROM_DEV_ADDR, 1,
11950 I40E_MODULE_SFF_8472_SWAP,
11951 &sff8472_swap, NULL);
11955 /* Check if the module requires address swap to access
11956 * the other EEPROM memory page.
11958 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11959 PMD_DRV_LOG(WARNING,
11960 "Module address swap to access "
11961 "page 0xA2 is not supported.\n");
11962 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11963 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11964 } else if (sff8472_comp == 0x00) {
11965 /* Module is not SFF-8472 compliant */
11966 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11967 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11969 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11970 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11973 case I40E_MODULE_TYPE_QSFP_PLUS:
11974 /* Read from memory page 0. */
11975 status = i40e_aq_get_phy_register(hw,
11976 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11978 I40E_MODULE_REVISION_ADDR,
11979 &sff8636_rev, NULL);
11982 /* Determine revision compliance byte */
11983 if (sff8636_rev > 0x02) {
11984 /* Module is SFF-8636 compliant */
11985 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11986 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11988 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11989 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11992 case I40E_MODULE_TYPE_QSFP28:
11993 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11994 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11997 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12003 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12004 struct rte_dev_eeprom_info *info)
12006 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12007 bool is_sfp = false;
12008 i40e_status status;
12010 uint32_t value = 0;
12013 if (!info || !info->length || !info->data)
12016 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12020 for (i = 0; i < info->length; i++) {
12021 u32 offset = i + info->offset;
12022 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12024 /* Check if we need to access the other memory page */
12026 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12027 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12028 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12031 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12032 /* Compute memory page number and offset. */
12033 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12037 status = i40e_aq_get_phy_register(hw,
12038 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12039 addr, offset, 1, &value, NULL);
12042 data[i] = (uint8_t)value;
12047 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12048 struct rte_ether_addr *mac_addr)
12050 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12051 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12052 struct i40e_vsi *vsi = pf->main_vsi;
12053 struct i40e_mac_filter_info mac_filter;
12054 struct i40e_mac_filter *f;
12057 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12058 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12062 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12063 if (rte_is_same_ether_addr(&pf->dev_addr,
12064 &f->mac_info.mac_addr))
12069 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12073 mac_filter = f->mac_info;
12074 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12075 if (ret != I40E_SUCCESS) {
12076 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12079 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12080 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12081 if (ret != I40E_SUCCESS) {
12082 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12085 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12087 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12088 mac_addr->addr_bytes, NULL);
12089 if (ret != I40E_SUCCESS) {
12090 PMD_DRV_LOG(ERR, "Failed to change mac");
12098 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12100 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12101 struct rte_eth_dev_data *dev_data = pf->dev_data;
12102 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12105 /* check if mtu is within the allowed range */
12106 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12109 /* mtu setting is forbidden if port is start */
12110 if (dev_data->dev_started) {
12111 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12112 dev_data->port_id);
12116 if (frame_size > RTE_ETHER_MAX_LEN)
12117 dev_data->dev_conf.rxmode.offloads |=
12118 DEV_RX_OFFLOAD_JUMBO_FRAME;
12120 dev_data->dev_conf.rxmode.offloads &=
12121 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12123 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12128 /* Restore ethertype filter */
12130 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12132 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12133 struct i40e_ethertype_filter_list
12134 *ethertype_list = &pf->ethertype.ethertype_list;
12135 struct i40e_ethertype_filter *f;
12136 struct i40e_control_filter_stats stats;
12139 TAILQ_FOREACH(f, ethertype_list, rules) {
12141 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12142 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12143 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12144 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12145 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12147 memset(&stats, 0, sizeof(stats));
12148 i40e_aq_add_rem_control_packet_filter(hw,
12149 f->input.mac_addr.addr_bytes,
12150 f->input.ether_type,
12151 flags, pf->main_vsi->seid,
12152 f->queue, 1, &stats, NULL);
12154 PMD_DRV_LOG(INFO, "Ethertype filter:"
12155 " mac_etype_used = %u, etype_used = %u,"
12156 " mac_etype_free = %u, etype_free = %u",
12157 stats.mac_etype_used, stats.etype_used,
12158 stats.mac_etype_free, stats.etype_free);
12161 /* Restore tunnel filter */
12163 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12165 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12166 struct i40e_vsi *vsi;
12167 struct i40e_pf_vf *vf;
12168 struct i40e_tunnel_filter_list
12169 *tunnel_list = &pf->tunnel.tunnel_list;
12170 struct i40e_tunnel_filter *f;
12171 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12172 bool big_buffer = 0;
12174 TAILQ_FOREACH(f, tunnel_list, rules) {
12176 vsi = pf->main_vsi;
12178 vf = &pf->vfs[f->vf_id];
12181 memset(&cld_filter, 0, sizeof(cld_filter));
12182 rte_ether_addr_copy((struct rte_ether_addr *)
12183 &f->input.outer_mac,
12184 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12185 rte_ether_addr_copy((struct rte_ether_addr *)
12186 &f->input.inner_mac,
12187 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12188 cld_filter.element.inner_vlan = f->input.inner_vlan;
12189 cld_filter.element.flags = f->input.flags;
12190 cld_filter.element.tenant_id = f->input.tenant_id;
12191 cld_filter.element.queue_number = f->queue;
12192 rte_memcpy(cld_filter.general_fields,
12193 f->input.general_fields,
12194 sizeof(f->input.general_fields));
12196 if (((f->input.flags &
12197 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12198 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12200 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12201 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12203 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12204 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12208 i40e_aq_add_cloud_filters_bb(hw,
12209 vsi->seid, &cld_filter, 1);
12211 i40e_aq_add_cloud_filters(hw, vsi->seid,
12212 &cld_filter.element, 1);
12216 /* Restore rss filter */
12218 i40e_rss_filter_restore(struct i40e_pf *pf)
12220 struct i40e_rte_flow_rss_conf *conf =
12222 if (conf->conf.queue_num)
12223 i40e_config_rss_filter(pf, conf, TRUE);
12227 i40e_filter_restore(struct i40e_pf *pf)
12229 i40e_ethertype_filter_restore(pf);
12230 i40e_tunnel_filter_restore(pf);
12231 i40e_fdir_filter_restore(pf);
12232 i40e_rss_filter_restore(pf);
12236 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12238 if (strcmp(dev->device->driver->name, drv->driver.name))
12245 is_i40e_supported(struct rte_eth_dev *dev)
12247 return is_device_supported(dev, &rte_i40e_pmd);
12250 struct i40e_customized_pctype*
12251 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12255 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12256 if (pf->customized_pctype[i].index == index)
12257 return &pf->customized_pctype[i];
12263 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12264 uint32_t pkg_size, uint32_t proto_num,
12265 struct rte_pmd_i40e_proto_info *proto,
12266 enum rte_pmd_i40e_package_op op)
12268 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12269 uint32_t pctype_num;
12270 struct rte_pmd_i40e_ptype_info *pctype;
12271 uint32_t buff_size;
12272 struct i40e_customized_pctype *new_pctype = NULL;
12274 uint8_t pctype_value;
12279 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12280 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12281 PMD_DRV_LOG(ERR, "Unsupported operation.");
12285 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12286 (uint8_t *)&pctype_num, sizeof(pctype_num),
12287 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12289 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12293 PMD_DRV_LOG(INFO, "No new pctype added");
12297 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12298 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12300 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12303 /* get information about new pctype list */
12304 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12305 (uint8_t *)pctype, buff_size,
12306 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12308 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12313 /* Update customized pctype. */
12314 for (i = 0; i < pctype_num; i++) {
12315 pctype_value = pctype[i].ptype_id;
12316 memset(name, 0, sizeof(name));
12317 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12318 proto_id = pctype[i].protocols[j];
12319 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12321 for (n = 0; n < proto_num; n++) {
12322 if (proto[n].proto_id != proto_id)
12324 strlcat(name, proto[n].name, sizeof(name));
12325 strlcat(name, "_", sizeof(name));
12329 name[strlen(name) - 1] = '\0';
12330 if (!strcmp(name, "GTPC"))
12332 i40e_find_customized_pctype(pf,
12333 I40E_CUSTOMIZED_GTPC);
12334 else if (!strcmp(name, "GTPU_IPV4"))
12336 i40e_find_customized_pctype(pf,
12337 I40E_CUSTOMIZED_GTPU_IPV4);
12338 else if (!strcmp(name, "GTPU_IPV6"))
12340 i40e_find_customized_pctype(pf,
12341 I40E_CUSTOMIZED_GTPU_IPV6);
12342 else if (!strcmp(name, "GTPU"))
12344 i40e_find_customized_pctype(pf,
12345 I40E_CUSTOMIZED_GTPU);
12347 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12348 new_pctype->pctype = pctype_value;
12349 new_pctype->valid = true;
12351 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12352 new_pctype->valid = false;
12362 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12363 uint32_t pkg_size, uint32_t proto_num,
12364 struct rte_pmd_i40e_proto_info *proto,
12365 enum rte_pmd_i40e_package_op op)
12367 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12368 uint16_t port_id = dev->data->port_id;
12369 uint32_t ptype_num;
12370 struct rte_pmd_i40e_ptype_info *ptype;
12371 uint32_t buff_size;
12373 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12378 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12379 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12380 PMD_DRV_LOG(ERR, "Unsupported operation.");
12384 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12385 rte_pmd_i40e_ptype_mapping_reset(port_id);
12389 /* get information about new ptype num */
12390 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12391 (uint8_t *)&ptype_num, sizeof(ptype_num),
12392 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12394 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12398 PMD_DRV_LOG(INFO, "No new ptype added");
12402 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12403 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12405 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12409 /* get information about new ptype list */
12410 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12411 (uint8_t *)ptype, buff_size,
12412 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12414 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12419 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12420 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12421 if (!ptype_mapping) {
12422 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12427 /* Update ptype mapping table. */
12428 for (i = 0; i < ptype_num; i++) {
12429 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12430 ptype_mapping[i].sw_ptype = 0;
12432 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12433 proto_id = ptype[i].protocols[j];
12434 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12436 for (n = 0; n < proto_num; n++) {
12437 if (proto[n].proto_id != proto_id)
12439 memset(name, 0, sizeof(name));
12440 strcpy(name, proto[n].name);
12441 if (!strncasecmp(name, "PPPOE", 5))
12442 ptype_mapping[i].sw_ptype |=
12443 RTE_PTYPE_L2_ETHER_PPPOE;
12444 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12446 ptype_mapping[i].sw_ptype |=
12447 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12448 ptype_mapping[i].sw_ptype |=
12450 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12452 ptype_mapping[i].sw_ptype |=
12453 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12454 ptype_mapping[i].sw_ptype |=
12455 RTE_PTYPE_INNER_L4_FRAG;
12456 } else if (!strncasecmp(name, "OIPV4", 5)) {
12457 ptype_mapping[i].sw_ptype |=
12458 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12460 } else if (!strncasecmp(name, "IPV4", 4) &&
12462 ptype_mapping[i].sw_ptype |=
12463 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12464 else if (!strncasecmp(name, "IPV4", 4) &&
12466 ptype_mapping[i].sw_ptype |=
12467 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12468 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12470 ptype_mapping[i].sw_ptype |=
12471 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12472 ptype_mapping[i].sw_ptype |=
12474 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12476 ptype_mapping[i].sw_ptype |=
12477 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12478 ptype_mapping[i].sw_ptype |=
12479 RTE_PTYPE_INNER_L4_FRAG;
12480 } else if (!strncasecmp(name, "OIPV6", 5)) {
12481 ptype_mapping[i].sw_ptype |=
12482 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12484 } else if (!strncasecmp(name, "IPV6", 4) &&
12486 ptype_mapping[i].sw_ptype |=
12487 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12488 else if (!strncasecmp(name, "IPV6", 4) &&
12490 ptype_mapping[i].sw_ptype |=
12491 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12492 else if (!strncasecmp(name, "UDP", 3) &&
12494 ptype_mapping[i].sw_ptype |=
12496 else if (!strncasecmp(name, "UDP", 3) &&
12498 ptype_mapping[i].sw_ptype |=
12499 RTE_PTYPE_INNER_L4_UDP;
12500 else if (!strncasecmp(name, "TCP", 3) &&
12502 ptype_mapping[i].sw_ptype |=
12504 else if (!strncasecmp(name, "TCP", 3) &&
12506 ptype_mapping[i].sw_ptype |=
12507 RTE_PTYPE_INNER_L4_TCP;
12508 else if (!strncasecmp(name, "SCTP", 4) &&
12510 ptype_mapping[i].sw_ptype |=
12512 else if (!strncasecmp(name, "SCTP", 4) &&
12514 ptype_mapping[i].sw_ptype |=
12515 RTE_PTYPE_INNER_L4_SCTP;
12516 else if ((!strncasecmp(name, "ICMP", 4) ||
12517 !strncasecmp(name, "ICMPV6", 6)) &&
12519 ptype_mapping[i].sw_ptype |=
12521 else if ((!strncasecmp(name, "ICMP", 4) ||
12522 !strncasecmp(name, "ICMPV6", 6)) &&
12524 ptype_mapping[i].sw_ptype |=
12525 RTE_PTYPE_INNER_L4_ICMP;
12526 else if (!strncasecmp(name, "GTPC", 4)) {
12527 ptype_mapping[i].sw_ptype |=
12528 RTE_PTYPE_TUNNEL_GTPC;
12530 } else if (!strncasecmp(name, "GTPU", 4)) {
12531 ptype_mapping[i].sw_ptype |=
12532 RTE_PTYPE_TUNNEL_GTPU;
12534 } else if (!strncasecmp(name, "GRENAT", 6)) {
12535 ptype_mapping[i].sw_ptype |=
12536 RTE_PTYPE_TUNNEL_GRENAT;
12538 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12539 !strncasecmp(name, "L2TPV2", 6)) {
12540 ptype_mapping[i].sw_ptype |=
12541 RTE_PTYPE_TUNNEL_L2TP;
12550 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12553 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12555 rte_free(ptype_mapping);
12561 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12562 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12564 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12565 uint32_t proto_num;
12566 struct rte_pmd_i40e_proto_info *proto;
12567 uint32_t buff_size;
12571 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12572 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12573 PMD_DRV_LOG(ERR, "Unsupported operation.");
12577 /* get information about protocol number */
12578 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12579 (uint8_t *)&proto_num, sizeof(proto_num),
12580 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12582 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12586 PMD_DRV_LOG(INFO, "No new protocol added");
12590 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12591 proto = rte_zmalloc("new_proto", buff_size, 0);
12593 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12597 /* get information about protocol list */
12598 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12599 (uint8_t *)proto, buff_size,
12600 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12602 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12607 /* Check if GTP is supported. */
12608 for (i = 0; i < proto_num; i++) {
12609 if (!strncmp(proto[i].name, "GTP", 3)) {
12610 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12611 pf->gtp_support = true;
12613 pf->gtp_support = false;
12618 /* Update customized pctype info */
12619 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12620 proto_num, proto, op);
12622 PMD_DRV_LOG(INFO, "No pctype is updated.");
12624 /* Update customized ptype info */
12625 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12626 proto_num, proto, op);
12628 PMD_DRV_LOG(INFO, "No ptype is updated.");
12633 /* Create a QinQ cloud filter
12635 * The Fortville NIC has limited resources for tunnel filters,
12636 * so we can only reuse existing filters.
12638 * In step 1 we define which Field Vector fields can be used for
12640 * As we do not have the inner tag defined as a field,
12641 * we have to define it first, by reusing one of L1 entries.
12643 * In step 2 we are replacing one of existing filter types with
12644 * a new one for QinQ.
12645 * As we reusing L1 and replacing L2, some of the default filter
12646 * types will disappear,which depends on L1 and L2 entries we reuse.
12648 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12650 * 1. Create L1 filter of outer vlan (12b) which will be in use
12651 * later when we define the cloud filter.
12652 * a. Valid_flags.replace_cloud = 0
12653 * b. Old_filter = 10 (Stag_Inner_Vlan)
12654 * c. New_filter = 0x10
12655 * d. TR bit = 0xff (optional, not used here)
12656 * e. Buffer – 2 entries:
12657 * i. Byte 0 = 8 (outer vlan FV index).
12659 * Byte 2-3 = 0x0fff
12660 * ii. Byte 0 = 37 (inner vlan FV index).
12662 * Byte 2-3 = 0x0fff
12665 * 2. Create cloud filter using two L1 filters entries: stag and
12666 * new filter(outer vlan+ inner vlan)
12667 * a. Valid_flags.replace_cloud = 1
12668 * b. Old_filter = 1 (instead of outer IP)
12669 * c. New_filter = 0x10
12670 * d. Buffer – 2 entries:
12671 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12672 * Byte 1-3 = 0 (rsv)
12673 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12674 * Byte 9-11 = 0 (rsv)
12677 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12679 int ret = -ENOTSUP;
12680 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12681 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12682 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12683 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12685 if (pf->support_multi_driver) {
12686 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12691 memset(&filter_replace, 0,
12692 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12693 memset(&filter_replace_buf, 0,
12694 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12696 /* create L1 filter */
12697 filter_replace.old_filter_type =
12698 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12699 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12700 filter_replace.tr_bit = 0;
12702 /* Prepare the buffer, 2 entries */
12703 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12704 filter_replace_buf.data[0] |=
12705 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12706 /* Field Vector 12b mask */
12707 filter_replace_buf.data[2] = 0xff;
12708 filter_replace_buf.data[3] = 0x0f;
12709 filter_replace_buf.data[4] =
12710 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12711 filter_replace_buf.data[4] |=
12712 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12713 /* Field Vector 12b mask */
12714 filter_replace_buf.data[6] = 0xff;
12715 filter_replace_buf.data[7] = 0x0f;
12716 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12717 &filter_replace_buf);
12718 if (ret != I40E_SUCCESS)
12721 if (filter_replace.old_filter_type !=
12722 filter_replace.new_filter_type)
12723 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12724 " original: 0x%x, new: 0x%x",
12726 filter_replace.old_filter_type,
12727 filter_replace.new_filter_type);
12729 /* Apply the second L2 cloud filter */
12730 memset(&filter_replace, 0,
12731 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12732 memset(&filter_replace_buf, 0,
12733 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12735 /* create L2 filter, input for L2 filter will be L1 filter */
12736 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12737 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12738 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12740 /* Prepare the buffer, 2 entries */
12741 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12742 filter_replace_buf.data[0] |=
12743 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12744 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12745 filter_replace_buf.data[4] |=
12746 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12747 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12748 &filter_replace_buf);
12749 if (!ret && (filter_replace.old_filter_type !=
12750 filter_replace.new_filter_type))
12751 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12752 " original: 0x%x, new: 0x%x",
12754 filter_replace.old_filter_type,
12755 filter_replace.new_filter_type);
12761 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12762 const struct rte_flow_action_rss *in)
12764 if (in->key_len > RTE_DIM(out->key) ||
12765 in->queue_num > RTE_DIM(out->queue))
12767 if (!in->key && in->key_len)
12769 out->conf = (struct rte_flow_action_rss){
12771 .level = in->level,
12772 .types = in->types,
12773 .key_len = in->key_len,
12774 .queue_num = in->queue_num,
12775 .queue = memcpy(out->queue, in->queue,
12776 sizeof(*in->queue) * in->queue_num),
12779 out->conf.key = memcpy(out->key, in->key, in->key_len);
12784 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12785 const struct rte_flow_action_rss *with)
12787 return (comp->func == with->func &&
12788 comp->level == with->level &&
12789 comp->types == with->types &&
12790 comp->key_len == with->key_len &&
12791 comp->queue_num == with->queue_num &&
12792 !memcmp(comp->key, with->key, with->key_len) &&
12793 !memcmp(comp->queue, with->queue,
12794 sizeof(*with->queue) * with->queue_num));
12798 i40e_config_rss_filter(struct i40e_pf *pf,
12799 struct i40e_rte_flow_rss_conf *conf, bool add)
12801 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12802 uint32_t i, lut = 0;
12804 struct rte_eth_rss_conf rss_conf = {
12805 .rss_key = conf->conf.key_len ?
12806 (void *)(uintptr_t)conf->conf.key : NULL,
12807 .rss_key_len = conf->conf.key_len,
12808 .rss_hf = conf->conf.types,
12810 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12813 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12814 i40e_pf_disable_rss(pf);
12815 memset(rss_info, 0,
12816 sizeof(struct i40e_rte_flow_rss_conf));
12822 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12823 * It's necessary to calculate the actual PF queues that are configured.
12825 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12826 num = i40e_pf_calc_configured_queues_num(pf);
12828 num = pf->dev_data->nb_rx_queues;
12830 num = RTE_MIN(num, conf->conf.queue_num);
12831 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12835 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12839 /* Fill in redirection table */
12840 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12843 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12844 hw->func_caps.rss_table_entry_width) - 1));
12846 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12849 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12850 i40e_pf_disable_rss(pf);
12853 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12854 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12855 /* Random default keys */
12856 static uint32_t rss_key_default[] = {0x6b793944,
12857 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12858 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12859 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12861 rss_conf.rss_key = (uint8_t *)rss_key_default;
12862 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12865 "No valid RSS key config for i40e, using default\n");
12868 i40e_hw_rss_hash_set(pf, &rss_conf);
12870 if (i40e_rss_conf_init(rss_info, &conf->conf))
12876 RTE_INIT(i40e_init_log)
12878 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12879 if (i40e_logtype_init >= 0)
12880 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12881 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12882 if (i40e_logtype_driver >= 0)
12883 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12885 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
12886 i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
12887 if (i40e_logtype_rx >= 0)
12888 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
12891 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
12892 i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
12893 if (i40e_logtype_tx >= 0)
12894 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
12897 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
12898 i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
12899 if (i40e_logtype_tx_free >= 0)
12900 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
12904 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12905 ETH_I40E_FLOATING_VEB_ARG "=1"
12906 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12907 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12908 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12909 ETH_I40E_USE_LATEST_VEC "=0|1");