4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
65 /* Maximun number of MAC addresses */
66 #define I40E_NUM_MACADDR_MAX 64
67 #define I40E_CLEAR_PXE_WAIT_MS 200
69 /* Maximun number of capability elements */
70 #define I40E_MAX_CAP_ELE_NUM 128
72 /* Wait count and inteval */
73 #define I40E_CHK_Q_ENA_COUNT 1000
74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
76 /* Maximun number of VSI */
77 #define I40E_MAX_NUM_VSIS (384UL)
79 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
81 /* Flow control default timer */
82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
84 /* Flow control default high water */
85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
87 /* Flow control default low water */
88 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
90 /* Flow control enable fwd bit */
91 #define I40E_PRTMAC_FWD_CTRL 0x00000001
93 /* Receive Packet Buffer size */
94 #define I40E_RXPBSIZE (968 * 1024)
97 #define I40E_KILOSHIFT 10
99 /* Receive Average Packet Size in Byte*/
100 #define I40E_PACKET_AVERAGE_SIZE 128
102 /* Mask of PF interrupt causes */
103 #define I40E_PFINT_ICR0_ENA_MASK ( \
104 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
105 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
106 I40E_PFINT_ICR0_ENA_GRST_MASK | \
107 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
108 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
109 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
110 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
112 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
113 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
115 #define I40E_FLOW_TYPES ( \
116 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
121 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
126 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
128 /* Additional timesync values. */
129 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
130 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
131 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
132 #define I40E_PRTTSYN_TSYNENA 0x80000000
133 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
134 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffff
136 #define I40E_MAX_PERCENT 100
137 #define I40E_DEFAULT_DCB_APP_NUM 1
138 #define I40E_DEFAULT_DCB_APP_PRIO 3
140 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32))
141 #define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8))
142 #define I40E_GLQF_FD_MSK_FIELD 0x0000FFFF
143 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
144 #define I40E_GLQF_HASH_MSK(_i, _j) (0x00267A00 + ((_i) * 4 + (_j) * 8))
145 #define I40E_GLQF_HASH_MSK_FIELD 0x0000FFFF
147 #define I40E_INSET_NONE 0x00000000000000000ULL
150 #define I40E_INSET_DMAC 0x0000000000000001ULL
151 #define I40E_INSET_SMAC 0x0000000000000002ULL
152 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
153 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
154 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
157 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
158 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
159 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
160 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
161 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
162 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
163 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
165 /* bit 16 ~ bit 31 */
166 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
167 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
168 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
169 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
170 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
171 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
172 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
173 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
175 /* bit 32 ~ bit 47, tunnel fields */
176 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
177 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
178 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
179 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
180 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
181 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
183 /* bit 48 ~ bit 55 */
184 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
186 /* bit 56 ~ bit 63, Flex Payload */
187 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
191 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
192 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
193 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
194 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
195 #define I40E_INSET_FLEX_PAYLOAD \
196 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
197 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
198 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
199 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
202 * Below are values for writing un-exposed registers suggested
205 /* Destination MAC address */
206 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
207 /* Source MAC address */
208 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
209 /* VLAN tag in the outer L2 header */
210 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000000800000ULL
211 /* VLAN tag in the inner L2 header */
212 #define I40E_REG_INSET_L2_INNER_VLAN 0x0000000001000000ULL
213 /* Source IPv4 address */
214 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
215 /* Destination IPv4 address */
216 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
217 /* IPv4 Type of Service (TOS) */
218 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
220 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
221 /* Source IPv6 address */
222 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
223 /* Destination IPv6 address */
224 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
225 /* IPv6 Traffic Class (TC) */
226 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
227 /* IPv6 Next Header */
228 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
230 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
231 /* Destination L4 port */
232 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
233 /* SCTP verification tag */
234 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
235 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
236 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
237 /* Source port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
239 /* Destination port of tunneling UDP */
240 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
241 /* UDP Tunneling ID, NVGRE/GRE key */
242 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
243 /* Last ether type */
244 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
245 /* Tunneling outer destination IPv4 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
247 /* Tunneling outer destination IPv6 address */
248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
249 /* 1st word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
251 /* 2nd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
253 /* 3rd word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
255 /* 4th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
257 /* 5th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
259 /* 6th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
261 /* 7th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
263 /* 8th word of flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
266 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
268 #define I40E_TRANSLATE_INSET 0
269 #define I40E_TRANSLATE_REG 1
271 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
272 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
273 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
274 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
276 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
277 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
278 static int i40e_dev_configure(struct rte_eth_dev *dev);
279 static int i40e_dev_start(struct rte_eth_dev *dev);
280 static void i40e_dev_stop(struct rte_eth_dev *dev);
281 static void i40e_dev_close(struct rte_eth_dev *dev);
282 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
283 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
284 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
285 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
286 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
287 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
288 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
289 struct rte_eth_stats *stats);
290 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
291 struct rte_eth_xstats *xstats, unsigned n);
292 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
293 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
297 static void i40e_dev_info_get(struct rte_eth_dev *dev,
298 struct rte_eth_dev_info *dev_info);
299 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
302 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
303 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
304 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
307 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
308 static int i40e_dev_led_on(struct rte_eth_dev *dev);
309 static int i40e_dev_led_off(struct rte_eth_dev *dev);
310 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
311 struct rte_eth_fc_conf *fc_conf);
312 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
313 struct rte_eth_fc_conf *fc_conf);
314 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
315 struct rte_eth_pfc_conf *pfc_conf);
316 static void i40e_macaddr_add(struct rte_eth_dev *dev,
317 struct ether_addr *mac_addr,
320 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
321 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
322 struct rte_eth_rss_reta_entry64 *reta_conf,
324 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
325 struct rte_eth_rss_reta_entry64 *reta_conf,
328 static int i40e_get_cap(struct i40e_hw *hw);
329 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
330 static int i40e_pf_setup(struct i40e_pf *pf);
331 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
332 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
333 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
334 static int i40e_dcb_setup(struct rte_eth_dev *dev);
335 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
336 bool offset_loaded, uint64_t *offset, uint64_t *stat);
337 static void i40e_stat_update_48(struct i40e_hw *hw,
343 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
344 static void i40e_dev_interrupt_handler(
345 __rte_unused struct rte_intr_handle *handle, void *param);
346 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
347 uint32_t base, uint32_t num);
348 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
349 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
351 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
353 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
354 static int i40e_veb_release(struct i40e_veb *veb);
355 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
356 struct i40e_vsi *vsi);
357 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
358 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
359 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
360 struct i40e_macvlan_filter *mv_f,
362 struct ether_addr *addr);
363 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
364 struct i40e_macvlan_filter *mv_f,
367 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
368 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
369 struct rte_eth_rss_conf *rss_conf);
370 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
371 struct rte_eth_rss_conf *rss_conf);
372 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
373 struct rte_eth_udp_tunnel *udp_tunnel);
374 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
375 struct rte_eth_udp_tunnel *udp_tunnel);
376 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
377 struct rte_eth_ethertype_filter *filter,
379 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
380 enum rte_filter_op filter_op,
382 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
383 enum rte_filter_type filter_type,
384 enum rte_filter_op filter_op,
386 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
387 struct rte_eth_dcb_info *dcb_info);
388 static void i40e_configure_registers(struct i40e_hw *hw);
389 static void i40e_hw_init(struct i40e_hw *hw);
390 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
391 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
392 struct rte_eth_mirror_conf *mirror_conf,
393 uint8_t sw_id, uint8_t on);
394 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
396 static int i40e_timesync_enable(struct rte_eth_dev *dev);
397 static int i40e_timesync_disable(struct rte_eth_dev *dev);
398 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
399 struct timespec *timestamp,
401 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
402 struct timespec *timestamp);
403 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
405 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
407 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
408 struct timespec *timestamp);
409 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
410 const struct timespec *timestamp);
412 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
414 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
418 static const struct rte_pci_id pci_id_i40e_map[] = {
419 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
420 #include "rte_pci_dev_ids.h"
421 { .vendor_id = 0, /* sentinel */ },
424 static const struct eth_dev_ops i40e_eth_dev_ops = {
425 .dev_configure = i40e_dev_configure,
426 .dev_start = i40e_dev_start,
427 .dev_stop = i40e_dev_stop,
428 .dev_close = i40e_dev_close,
429 .promiscuous_enable = i40e_dev_promiscuous_enable,
430 .promiscuous_disable = i40e_dev_promiscuous_disable,
431 .allmulticast_enable = i40e_dev_allmulticast_enable,
432 .allmulticast_disable = i40e_dev_allmulticast_disable,
433 .dev_set_link_up = i40e_dev_set_link_up,
434 .dev_set_link_down = i40e_dev_set_link_down,
435 .link_update = i40e_dev_link_update,
436 .stats_get = i40e_dev_stats_get,
437 .xstats_get = i40e_dev_xstats_get,
438 .stats_reset = i40e_dev_stats_reset,
439 .xstats_reset = i40e_dev_stats_reset,
440 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
441 .dev_infos_get = i40e_dev_info_get,
442 .vlan_filter_set = i40e_vlan_filter_set,
443 .vlan_tpid_set = i40e_vlan_tpid_set,
444 .vlan_offload_set = i40e_vlan_offload_set,
445 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
446 .vlan_pvid_set = i40e_vlan_pvid_set,
447 .rx_queue_start = i40e_dev_rx_queue_start,
448 .rx_queue_stop = i40e_dev_rx_queue_stop,
449 .tx_queue_start = i40e_dev_tx_queue_start,
450 .tx_queue_stop = i40e_dev_tx_queue_stop,
451 .rx_queue_setup = i40e_dev_rx_queue_setup,
452 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
453 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
454 .rx_queue_release = i40e_dev_rx_queue_release,
455 .rx_queue_count = i40e_dev_rx_queue_count,
456 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
457 .tx_queue_setup = i40e_dev_tx_queue_setup,
458 .tx_queue_release = i40e_dev_tx_queue_release,
459 .dev_led_on = i40e_dev_led_on,
460 .dev_led_off = i40e_dev_led_off,
461 .flow_ctrl_get = i40e_flow_ctrl_get,
462 .flow_ctrl_set = i40e_flow_ctrl_set,
463 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
464 .mac_addr_add = i40e_macaddr_add,
465 .mac_addr_remove = i40e_macaddr_remove,
466 .reta_update = i40e_dev_rss_reta_update,
467 .reta_query = i40e_dev_rss_reta_query,
468 .rss_hash_update = i40e_dev_rss_hash_update,
469 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
470 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
471 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
472 .filter_ctrl = i40e_dev_filter_ctrl,
473 .rxq_info_get = i40e_rxq_info_get,
474 .txq_info_get = i40e_txq_info_get,
475 .mirror_rule_set = i40e_mirror_rule_set,
476 .mirror_rule_reset = i40e_mirror_rule_reset,
477 .timesync_enable = i40e_timesync_enable,
478 .timesync_disable = i40e_timesync_disable,
479 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
480 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
481 .get_dcb_info = i40e_dev_get_dcb_info,
482 .timesync_adjust_time = i40e_timesync_adjust_time,
483 .timesync_read_time = i40e_timesync_read_time,
484 .timesync_write_time = i40e_timesync_write_time,
487 /* store statistics names and its offset in stats structure */
488 struct rte_i40e_xstats_name_off {
489 char name[RTE_ETH_XSTATS_NAME_SIZE];
493 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
494 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
495 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
496 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
497 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
498 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
499 rx_unknown_protocol)},
500 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
501 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
502 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
503 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
506 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
507 sizeof(rte_i40e_stats_strings[0]))
509 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
510 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
511 tx_dropped_link_down)},
512 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
513 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
515 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
516 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
518 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
520 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
522 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
523 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
524 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
525 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
526 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
527 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
529 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
531 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
533 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
535 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
537 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
539 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
541 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
543 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
544 mac_short_packet_dropped)},
545 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
548 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
549 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
551 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
553 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
555 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
557 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
559 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_flow_director_atr_match_packets",
562 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
563 {"rx_flow_director_sb_match_packets",
564 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
565 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
567 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
569 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
571 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
575 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
576 sizeof(rte_i40e_hw_port_strings[0]))
578 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
579 {"xon_packets", offsetof(struct i40e_hw_port_stats,
581 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
585 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
586 sizeof(rte_i40e_rxq_prio_strings[0]))
588 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
589 {"xon_packets", offsetof(struct i40e_hw_port_stats,
591 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
593 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
594 priority_xon_2_xoff)},
597 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
598 sizeof(rte_i40e_txq_prio_strings[0]))
600 static struct eth_driver rte_i40e_pmd = {
602 .name = "rte_i40e_pmd",
603 .id_table = pci_id_i40e_map,
604 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
605 RTE_PCI_DRV_DETACHABLE,
607 .eth_dev_init = eth_i40e_dev_init,
608 .eth_dev_uninit = eth_i40e_dev_uninit,
609 .dev_private_size = sizeof(struct i40e_adapter),
613 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
614 struct rte_eth_link *link)
616 struct rte_eth_link *dst = link;
617 struct rte_eth_link *src = &(dev->data->dev_link);
619 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
620 *(uint64_t *)src) == 0)
627 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
628 struct rte_eth_link *link)
630 struct rte_eth_link *dst = &(dev->data->dev_link);
631 struct rte_eth_link *src = link;
633 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
634 *(uint64_t *)src) == 0)
641 * Driver initialization routine.
642 * Invoked once at EAL init time.
643 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
646 rte_i40e_pmd_init(const char *name __rte_unused,
647 const char *params __rte_unused)
649 PMD_INIT_FUNC_TRACE();
650 rte_eth_driver_register(&rte_i40e_pmd);
655 static struct rte_driver rte_i40e_driver = {
657 .init = rte_i40e_pmd_init,
660 PMD_REGISTER_DRIVER(rte_i40e_driver);
663 * Initialize registers for flexible payload, which should be set by NVM.
664 * This should be removed from code once it is fixed in NVM.
666 #ifndef I40E_GLQF_ORT
667 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
669 #ifndef I40E_GLQF_PIT
670 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
673 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
675 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
676 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
677 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
678 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
679 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
680 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
681 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
682 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
683 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
684 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
686 /* GLQF_PIT Registers */
687 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
688 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
691 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
694 * Add a ethertype filter to drop all flow control frames transmitted
698 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
700 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
701 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
702 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
703 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
706 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
707 I40E_FLOW_CONTROL_ETHERTYPE, flags,
708 pf->main_vsi_seid, 0,
711 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
712 " frames from VSIs.");
716 eth_i40e_dev_init(struct rte_eth_dev *dev)
718 struct rte_pci_device *pci_dev;
719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
721 struct i40e_vsi *vsi;
726 PMD_INIT_FUNC_TRACE();
728 dev->dev_ops = &i40e_eth_dev_ops;
729 dev->rx_pkt_burst = i40e_recv_pkts;
730 dev->tx_pkt_burst = i40e_xmit_pkts;
732 /* for secondary processes, we don't initialise any further as primary
733 * has already done this work. Only check we don't need a different
735 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
736 i40e_set_rx_function(dev);
737 i40e_set_tx_function(dev);
740 pci_dev = dev->pci_dev;
742 rte_eth_copy_pci_info(dev, pci_dev);
744 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
745 pf->adapter->eth_dev = dev;
746 pf->dev_data = dev->data;
748 hw->back = I40E_PF_TO_ADAPTER(pf);
749 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
751 PMD_INIT_LOG(ERR, "Hardware is not available, "
752 "as address is NULL");
756 hw->vendor_id = pci_dev->id.vendor_id;
757 hw->device_id = pci_dev->id.device_id;
758 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
759 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
760 hw->bus.device = pci_dev->addr.devid;
761 hw->bus.func = pci_dev->addr.function;
762 hw->adapter_stopped = 0;
764 /* Make sure all is clean before doing PF reset */
767 /* Initialize the hardware */
770 /* Reset here to make sure all is clean for each PF */
771 ret = i40e_pf_reset(hw);
773 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
777 /* Initialize the shared code (base driver) */
778 ret = i40e_init_shared_code(hw);
780 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
785 * To work around the NVM issue,initialize registers
786 * for flexible payload by software.
787 * It should be removed once issues are fixed in NVM.
789 i40e_flex_payload_reg_init(hw);
791 /* Initialize the parameters for adminq */
792 i40e_init_adminq_parameter(hw);
793 ret = i40e_init_adminq(hw);
794 if (ret != I40E_SUCCESS) {
795 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
798 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
799 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
800 hw->aq.api_maj_ver, hw->aq.api_min_ver,
801 ((hw->nvm.version >> 12) & 0xf),
802 ((hw->nvm.version >> 4) & 0xff),
803 (hw->nvm.version & 0xf), hw->nvm.eetrack);
806 i40e_clear_pxe_mode(hw);
809 * On X710, performance number is far from the expectation on recent
810 * firmware versions. The fix for this issue may not be integrated in
811 * the following firmware version. So the workaround in software driver
812 * is needed. It needs to modify the initial values of 3 internal only
813 * registers. Note that the workaround can be removed when it is fixed
814 * in firmware in the future.
816 i40e_configure_registers(hw);
818 /* Get hw capabilities */
819 ret = i40e_get_cap(hw);
820 if (ret != I40E_SUCCESS) {
821 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
822 goto err_get_capabilities;
825 /* Initialize parameters for PF */
826 ret = i40e_pf_parameter_init(dev);
828 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
829 goto err_parameter_init;
832 /* Initialize the queue management */
833 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
835 PMD_INIT_LOG(ERR, "Failed to init queue pool");
836 goto err_qp_pool_init;
838 ret = i40e_res_pool_init(&pf->msix_pool, 1,
839 hw->func_caps.num_msix_vectors - 1);
841 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
842 goto err_msix_pool_init;
845 /* Initialize lan hmc */
846 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
847 hw->func_caps.num_rx_qp, 0, 0);
848 if (ret != I40E_SUCCESS) {
849 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
850 goto err_init_lan_hmc;
853 /* Configure lan hmc */
854 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
855 if (ret != I40E_SUCCESS) {
856 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
857 goto err_configure_lan_hmc;
860 /* Get and check the mac address */
861 i40e_get_mac_addr(hw, hw->mac.addr);
862 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
863 PMD_INIT_LOG(ERR, "mac address is not valid");
865 goto err_get_mac_addr;
867 /* Copy the permanent MAC address */
868 ether_addr_copy((struct ether_addr *) hw->mac.addr,
869 (struct ether_addr *) hw->mac.perm_addr);
871 /* Disable flow control */
872 hw->fc.requested_mode = I40E_FC_NONE;
873 i40e_set_fc(hw, &aq_fail, TRUE);
875 /* PF setup, which includes VSI setup */
876 ret = i40e_pf_setup(pf);
878 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
879 goto err_setup_pf_switch;
884 /* Disable double vlan by default */
885 i40e_vsi_config_double_vlan(vsi, FALSE);
887 if (!vsi->max_macaddrs)
888 len = ETHER_ADDR_LEN;
890 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
892 /* Should be after VSI initialized */
893 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
894 if (!dev->data->mac_addrs) {
895 PMD_INIT_LOG(ERR, "Failed to allocated memory "
896 "for storing mac address");
899 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
900 &dev->data->mac_addrs[0]);
902 /* initialize pf host driver to setup SRIOV resource if applicable */
903 i40e_pf_host_init(dev);
905 /* register callback func to eal lib */
906 rte_intr_callback_register(&(pci_dev->intr_handle),
907 i40e_dev_interrupt_handler, (void *)dev);
909 /* configure and enable device interrupt */
910 i40e_pf_config_irq0(hw, TRUE);
911 i40e_pf_enable_irq0(hw);
913 /* enable uio intr after callback register */
914 rte_intr_enable(&(pci_dev->intr_handle));
916 * Add an ethertype filter to drop all flow control frames transmitted
917 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
920 i40e_add_tx_flow_control_drop_filter(pf);
922 /* initialize mirror rule list */
923 TAILQ_INIT(&pf->mirror_list);
925 /* Init dcb to sw mode by default */
926 ret = i40e_dcb_init_configure(dev, TRUE);
927 if (ret != I40E_SUCCESS) {
928 PMD_INIT_LOG(INFO, "Failed to init dcb.");
929 pf->flags &= ~I40E_FLAG_DCB;
935 i40e_vsi_release(pf->main_vsi);
938 err_configure_lan_hmc:
939 (void)i40e_shutdown_lan_hmc(hw);
941 i40e_res_pool_destroy(&pf->msix_pool);
943 i40e_res_pool_destroy(&pf->qp_pool);
946 err_get_capabilities:
947 (void)i40e_shutdown_adminq(hw);
953 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
955 struct rte_pci_device *pci_dev;
957 struct i40e_filter_control_settings settings;
961 PMD_INIT_FUNC_TRACE();
963 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
966 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
967 pci_dev = dev->pci_dev;
969 if (hw->adapter_stopped == 0)
973 dev->rx_pkt_burst = NULL;
974 dev->tx_pkt_burst = NULL;
977 ret = i40e_aq_stop_lldp(hw, true, NULL);
978 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
979 PMD_INIT_LOG(INFO, "Failed to stop lldp");
982 i40e_clear_pxe_mode(hw);
984 /* Unconfigure filter control */
985 memset(&settings, 0, sizeof(settings));
986 ret = i40e_set_filter_control(hw, &settings);
988 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
991 /* Disable flow control */
992 hw->fc.requested_mode = I40E_FC_NONE;
993 i40e_set_fc(hw, &aq_fail, TRUE);
995 /* uninitialize pf host driver */
996 i40e_pf_host_uninit(dev);
998 rte_free(dev->data->mac_addrs);
999 dev->data->mac_addrs = NULL;
1001 /* disable uio intr before callback unregister */
1002 rte_intr_disable(&(pci_dev->intr_handle));
1004 /* register callback func to eal lib */
1005 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1006 i40e_dev_interrupt_handler, (void *)dev);
1012 i40e_dev_configure(struct rte_eth_dev *dev)
1014 struct i40e_adapter *ad =
1015 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1016 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1020 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1021 * bulk allocation or vector Rx preconditions we will reset it.
1023 ad->rx_bulk_alloc_allowed = true;
1024 ad->rx_vec_allowed = true;
1025 ad->tx_simple_allowed = true;
1026 ad->tx_vec_allowed = true;
1028 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1029 ret = i40e_fdir_setup(pf);
1030 if (ret != I40E_SUCCESS) {
1031 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1034 ret = i40e_fdir_configure(dev);
1036 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1040 i40e_fdir_teardown(pf);
1042 ret = i40e_dev_init_vlan(dev);
1047 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1048 * RSS setting have different requirements.
1049 * General PMD driver call sequence are NIC init, configure,
1050 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1051 * will try to lookup the VSI that specific queue belongs to if VMDQ
1052 * applicable. So, VMDQ setting has to be done before
1053 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1054 * For RSS setting, it will try to calculate actual configured RX queue
1055 * number, which will be available after rx_queue_setup(). dev_start()
1056 * function is good to place RSS setup.
1058 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1059 ret = i40e_vmdq_setup(dev);
1064 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1065 ret = i40e_dcb_setup(dev);
1067 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1075 /* need to release vmdq resource if exists */
1076 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1077 i40e_vsi_release(pf->vmdq[i].vsi);
1078 pf->vmdq[i].vsi = NULL;
1083 /* need to release fdir resource if exists */
1084 i40e_fdir_teardown(pf);
1089 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1091 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1092 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1093 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1094 uint16_t msix_vect = vsi->msix_intr;
1097 for (i = 0; i < vsi->nb_qps; i++) {
1098 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1099 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1103 if (vsi->type != I40E_VSI_SRIOV) {
1104 if (!rte_intr_allow_others(intr_handle)) {
1105 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1106 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1108 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1111 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1112 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1114 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1119 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1120 vsi->user_param + (msix_vect - 1);
1122 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1123 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1125 I40E_WRITE_FLUSH(hw);
1129 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1130 int base_queue, int nb_queue)
1134 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1136 /* Bind all RX queues to allocated MSIX interrupt */
1137 for (i = 0; i < nb_queue; i++) {
1138 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1139 I40E_QINT_RQCTL_ITR_INDX_MASK |
1140 ((base_queue + i + 1) <<
1141 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1142 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1143 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1145 if (i == nb_queue - 1)
1146 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1147 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1150 /* Write first RX queue to Link list register as the head element */
1151 if (vsi->type != I40E_VSI_SRIOV) {
1153 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1155 if (msix_vect == I40E_MISC_VEC_ID) {
1156 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1158 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1160 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1162 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1165 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1167 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1169 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1171 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1178 if (msix_vect == I40E_MISC_VEC_ID) {
1180 I40E_VPINT_LNKLST0(vsi->user_param),
1182 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1184 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1186 /* num_msix_vectors_vf needs to minus irq0 */
1187 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1188 vsi->user_param + (msix_vect - 1);
1190 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1192 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1194 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1198 I40E_WRITE_FLUSH(hw);
1202 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1204 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1205 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1206 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1207 uint16_t msix_vect = vsi->msix_intr;
1208 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1209 uint16_t queue_idx = 0;
1214 for (i = 0; i < vsi->nb_qps; i++) {
1215 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1216 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1219 /* INTENA flag is not auto-cleared for interrupt */
1220 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1221 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1222 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1223 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1224 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1226 /* VF bind interrupt */
1227 if (vsi->type == I40E_VSI_SRIOV) {
1228 __vsi_queues_bind_intr(vsi, msix_vect,
1229 vsi->base_queue, vsi->nb_qps);
1233 /* PF & VMDq bind interrupt */
1234 if (rte_intr_dp_is_en(intr_handle)) {
1235 if (vsi->type == I40E_VSI_MAIN) {
1238 } else if (vsi->type == I40E_VSI_VMDQ2) {
1239 struct i40e_vsi *main_vsi =
1240 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1241 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1246 for (i = 0; i < vsi->nb_used_qps; i++) {
1248 if (!rte_intr_allow_others(intr_handle))
1249 /* allow to share MISC_VEC_ID */
1250 msix_vect = I40E_MISC_VEC_ID;
1252 /* no enough msix_vect, map all to one */
1253 __vsi_queues_bind_intr(vsi, msix_vect,
1254 vsi->base_queue + i,
1255 vsi->nb_used_qps - i);
1256 for (; !!record && i < vsi->nb_used_qps; i++)
1257 intr_handle->intr_vec[queue_idx + i] =
1261 /* 1:1 queue/msix_vect mapping */
1262 __vsi_queues_bind_intr(vsi, msix_vect,
1263 vsi->base_queue + i, 1);
1265 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1273 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1275 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278 uint16_t interval = i40e_calc_itr_interval(\
1279 RTE_LIBRTE_I40E_ITR_INTERVAL);
1280 uint16_t msix_intr, i;
1282 if (rte_intr_allow_others(intr_handle))
1283 for (i = 0; i < vsi->nb_msix; i++) {
1284 msix_intr = vsi->msix_intr + i;
1285 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1286 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1287 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1288 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1290 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1293 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1294 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1295 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1296 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1298 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1300 I40E_WRITE_FLUSH(hw);
1304 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1306 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1307 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1308 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1309 uint16_t msix_intr, i;
1311 if (rte_intr_allow_others(intr_handle))
1312 for (i = 0; i < vsi->nb_msix; i++) {
1313 msix_intr = vsi->msix_intr + i;
1314 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1318 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1320 I40E_WRITE_FLUSH(hw);
1323 static inline uint8_t
1324 i40e_parse_link_speed(uint16_t eth_link_speed)
1326 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1328 switch (eth_link_speed) {
1329 case ETH_LINK_SPEED_40G:
1330 link_speed = I40E_LINK_SPEED_40GB;
1332 case ETH_LINK_SPEED_20G:
1333 link_speed = I40E_LINK_SPEED_20GB;
1335 case ETH_LINK_SPEED_10G:
1336 link_speed = I40E_LINK_SPEED_10GB;
1338 case ETH_LINK_SPEED_1000:
1339 link_speed = I40E_LINK_SPEED_1GB;
1341 case ETH_LINK_SPEED_100:
1342 link_speed = I40E_LINK_SPEED_100MB;
1350 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1352 enum i40e_status_code status;
1353 struct i40e_aq_get_phy_abilities_resp phy_ab;
1354 struct i40e_aq_set_phy_config phy_conf;
1355 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1356 I40E_AQ_PHY_FLAG_PAUSE_RX |
1357 I40E_AQ_PHY_FLAG_LOW_POWER;
1358 const uint8_t advt = I40E_LINK_SPEED_40GB |
1359 I40E_LINK_SPEED_10GB |
1360 I40E_LINK_SPEED_1GB |
1361 I40E_LINK_SPEED_100MB;
1364 /* Skip it on 40G interfaces, as a workaround for the link issue */
1365 if (i40e_is_40G_device(hw->device_id))
1366 return I40E_SUCCESS;
1368 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1373 memset(&phy_conf, 0, sizeof(phy_conf));
1375 /* bits 0-2 use the values from get_phy_abilities_resp */
1377 abilities |= phy_ab.abilities & mask;
1379 /* update ablities and speed */
1380 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1381 phy_conf.link_speed = advt;
1383 phy_conf.link_speed = force_speed;
1385 phy_conf.abilities = abilities;
1387 /* use get_phy_abilities_resp value for the rest */
1388 phy_conf.phy_type = phy_ab.phy_type;
1389 phy_conf.eee_capability = phy_ab.eee_capability;
1390 phy_conf.eeer = phy_ab.eeer_val;
1391 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1393 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1394 phy_ab.abilities, phy_ab.link_speed);
1395 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1396 phy_conf.abilities, phy_conf.link_speed);
1398 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1402 return I40E_SUCCESS;
1406 i40e_apply_link_speed(struct rte_eth_dev *dev)
1409 uint8_t abilities = 0;
1410 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411 struct rte_eth_conf *conf = &dev->data->dev_conf;
1413 speed = i40e_parse_link_speed(conf->link_speed);
1414 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1415 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1416 abilities |= I40E_AQ_PHY_AN_ENABLED;
1418 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1420 return i40e_phy_conf_link(hw, abilities, speed);
1424 i40e_dev_start(struct rte_eth_dev *dev)
1426 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct i40e_vsi *main_vsi = pf->main_vsi;
1430 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1431 uint32_t intr_vector = 0;
1433 hw->adapter_stopped = 0;
1435 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1436 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1437 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1438 dev->data->dev_conf.link_duplex,
1439 dev->data->port_id);
1443 rte_intr_disable(intr_handle);
1445 if ((rte_intr_cap_multiple(intr_handle) ||
1446 !RTE_ETH_DEV_SRIOV(dev).active) &&
1447 dev->data->dev_conf.intr_conf.rxq != 0) {
1448 intr_vector = dev->data->nb_rx_queues;
1449 if (rte_intr_efd_enable(intr_handle, intr_vector))
1453 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1454 intr_handle->intr_vec =
1455 rte_zmalloc("intr_vec",
1456 dev->data->nb_rx_queues * sizeof(int),
1458 if (!intr_handle->intr_vec) {
1459 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1460 " intr_vec\n", dev->data->nb_rx_queues);
1465 /* Initialize VSI */
1466 ret = i40e_dev_rxtx_init(pf);
1467 if (ret != I40E_SUCCESS) {
1468 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1472 /* Map queues with MSIX interrupt */
1473 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1474 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1475 i40e_vsi_queues_bind_intr(main_vsi);
1476 i40e_vsi_enable_queues_intr(main_vsi);
1478 /* Map VMDQ VSI queues with MSIX interrupt */
1479 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1480 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1481 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1482 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1485 /* enable FDIR MSIX interrupt */
1486 if (pf->fdir.fdir_vsi) {
1487 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1488 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1491 /* Enable all queues which have been configured */
1492 ret = i40e_dev_switch_queues(pf, TRUE);
1493 if (ret != I40E_SUCCESS) {
1494 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1498 /* Enable receiving broadcast packets */
1499 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1500 if (ret != I40E_SUCCESS)
1501 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1503 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1504 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1506 if (ret != I40E_SUCCESS)
1507 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1510 /* Apply link configure */
1511 ret = i40e_apply_link_speed(dev);
1512 if (I40E_SUCCESS != ret) {
1513 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1517 if (!rte_intr_allow_others(intr_handle)) {
1518 rte_intr_callback_unregister(intr_handle,
1519 i40e_dev_interrupt_handler,
1521 /* configure and enable device interrupt */
1522 i40e_pf_config_irq0(hw, FALSE);
1523 i40e_pf_enable_irq0(hw);
1525 if (dev->data->dev_conf.intr_conf.lsc != 0)
1526 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1527 " no intr multiplex\n");
1530 /* enable uio intr after callback register */
1531 rte_intr_enable(intr_handle);
1533 return I40E_SUCCESS;
1536 i40e_dev_switch_queues(pf, FALSE);
1537 i40e_dev_clear_queues(dev);
1543 i40e_dev_stop(struct rte_eth_dev *dev)
1545 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1546 struct i40e_vsi *main_vsi = pf->main_vsi;
1547 struct i40e_mirror_rule *p_mirror;
1548 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1551 /* Disable all queues */
1552 i40e_dev_switch_queues(pf, FALSE);
1554 /* un-map queues with interrupt registers */
1555 i40e_vsi_disable_queues_intr(main_vsi);
1556 i40e_vsi_queues_unbind_intr(main_vsi);
1558 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1559 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1560 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1563 if (pf->fdir.fdir_vsi) {
1564 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1565 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1567 /* Clear all queues and release memory */
1568 i40e_dev_clear_queues(dev);
1571 i40e_dev_set_link_down(dev);
1573 /* Remove all mirror rules */
1574 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1575 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1578 pf->nb_mirror_rule = 0;
1580 if (!rte_intr_allow_others(intr_handle))
1581 /* resume to the default handler */
1582 rte_intr_callback_register(intr_handle,
1583 i40e_dev_interrupt_handler,
1586 /* Clean datapath event and queue/vec mapping */
1587 rte_intr_efd_disable(intr_handle);
1588 if (intr_handle->intr_vec) {
1589 rte_free(intr_handle->intr_vec);
1590 intr_handle->intr_vec = NULL;
1595 i40e_dev_close(struct rte_eth_dev *dev)
1597 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1602 PMD_INIT_FUNC_TRACE();
1605 hw->adapter_stopped = 1;
1606 i40e_dev_free_queues(dev);
1608 /* Disable interrupt */
1609 i40e_pf_disable_irq0(hw);
1610 rte_intr_disable(&(dev->pci_dev->intr_handle));
1612 /* shutdown and destroy the HMC */
1613 i40e_shutdown_lan_hmc(hw);
1615 /* release all the existing VSIs and VEBs */
1616 i40e_fdir_teardown(pf);
1617 i40e_vsi_release(pf->main_vsi);
1619 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1620 i40e_vsi_release(pf->vmdq[i].vsi);
1621 pf->vmdq[i].vsi = NULL;
1627 /* shutdown the adminq */
1628 i40e_aq_queue_shutdown(hw, true);
1629 i40e_shutdown_adminq(hw);
1631 i40e_res_pool_destroy(&pf->qp_pool);
1632 i40e_res_pool_destroy(&pf->msix_pool);
1634 /* force a PF reset to clean anything leftover */
1635 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1636 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1637 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1638 I40E_WRITE_FLUSH(hw);
1642 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1644 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1645 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646 struct i40e_vsi *vsi = pf->main_vsi;
1649 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1651 if (status != I40E_SUCCESS)
1652 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1654 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1656 if (status != I40E_SUCCESS)
1657 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1662 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1664 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1665 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666 struct i40e_vsi *vsi = pf->main_vsi;
1669 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1671 if (status != I40E_SUCCESS)
1672 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1674 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1676 if (status != I40E_SUCCESS)
1677 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1681 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1683 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685 struct i40e_vsi *vsi = pf->main_vsi;
1688 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1689 if (ret != I40E_SUCCESS)
1690 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1694 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1696 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1697 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698 struct i40e_vsi *vsi = pf->main_vsi;
1701 if (dev->data->promiscuous == 1)
1702 return; /* must remain in all_multicast mode */
1704 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1705 vsi->seid, FALSE, NULL);
1706 if (ret != I40E_SUCCESS)
1707 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1711 * Set device link up.
1714 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1716 /* re-apply link speed setting */
1717 return i40e_apply_link_speed(dev);
1721 * Set device link down.
1724 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1726 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1727 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1728 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1730 return i40e_phy_conf_link(hw, abilities, speed);
1734 i40e_dev_link_update(struct rte_eth_dev *dev,
1735 int wait_to_complete)
1737 #define CHECK_INTERVAL 100 /* 100ms */
1738 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1739 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740 struct i40e_link_status link_status;
1741 struct rte_eth_link link, old;
1743 unsigned rep_cnt = MAX_REPEAT_TIME;
1745 memset(&link, 0, sizeof(link));
1746 memset(&old, 0, sizeof(old));
1747 memset(&link_status, 0, sizeof(link_status));
1748 rte_i40e_dev_atomic_read_link_status(dev, &old);
1751 /* Get link status information from hardware */
1752 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1753 if (status != I40E_SUCCESS) {
1754 link.link_speed = ETH_LINK_SPEED_100;
1755 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1756 PMD_DRV_LOG(ERR, "Failed to get link info");
1760 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1761 if (!wait_to_complete)
1764 rte_delay_ms(CHECK_INTERVAL);
1765 } while (!link.link_status && rep_cnt--);
1767 if (!link.link_status)
1770 /* i40e uses full duplex only */
1771 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1773 /* Parse the link status */
1774 switch (link_status.link_speed) {
1775 case I40E_LINK_SPEED_100MB:
1776 link.link_speed = ETH_LINK_SPEED_100;
1778 case I40E_LINK_SPEED_1GB:
1779 link.link_speed = ETH_LINK_SPEED_1000;
1781 case I40E_LINK_SPEED_10GB:
1782 link.link_speed = ETH_LINK_SPEED_10G;
1784 case I40E_LINK_SPEED_20GB:
1785 link.link_speed = ETH_LINK_SPEED_20G;
1787 case I40E_LINK_SPEED_40GB:
1788 link.link_speed = ETH_LINK_SPEED_40G;
1791 link.link_speed = ETH_LINK_SPEED_100;
1796 rte_i40e_dev_atomic_write_link_status(dev, &link);
1797 if (link.link_status == old.link_status)
1803 /* Get all the statistics of a VSI */
1805 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1807 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1808 struct i40e_eth_stats *nes = &vsi->eth_stats;
1809 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1810 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1812 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1813 vsi->offset_loaded, &oes->rx_bytes,
1815 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1816 vsi->offset_loaded, &oes->rx_unicast,
1818 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1819 vsi->offset_loaded, &oes->rx_multicast,
1820 &nes->rx_multicast);
1821 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1822 vsi->offset_loaded, &oes->rx_broadcast,
1823 &nes->rx_broadcast);
1824 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1825 &oes->rx_discards, &nes->rx_discards);
1826 /* GLV_REPC not supported */
1827 /* GLV_RMPC not supported */
1828 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1829 &oes->rx_unknown_protocol,
1830 &nes->rx_unknown_protocol);
1831 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1832 vsi->offset_loaded, &oes->tx_bytes,
1834 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1835 vsi->offset_loaded, &oes->tx_unicast,
1837 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1838 vsi->offset_loaded, &oes->tx_multicast,
1839 &nes->tx_multicast);
1840 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1841 vsi->offset_loaded, &oes->tx_broadcast,
1842 &nes->tx_broadcast);
1843 /* GLV_TDPC not supported */
1844 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1845 &oes->tx_errors, &nes->tx_errors);
1846 vsi->offset_loaded = true;
1848 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1850 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1851 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1852 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1853 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1854 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1855 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1856 nes->rx_unknown_protocol);
1857 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1858 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1859 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1860 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1861 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1862 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1863 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1868 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1871 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1872 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1873 /* Get statistics of struct i40e_eth_stats */
1874 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1875 I40E_GLPRT_GORCL(hw->port),
1876 pf->offset_loaded, &os->eth.rx_bytes,
1878 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1879 I40E_GLPRT_UPRCL(hw->port),
1880 pf->offset_loaded, &os->eth.rx_unicast,
1881 &ns->eth.rx_unicast);
1882 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1883 I40E_GLPRT_MPRCL(hw->port),
1884 pf->offset_loaded, &os->eth.rx_multicast,
1885 &ns->eth.rx_multicast);
1886 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1887 I40E_GLPRT_BPRCL(hw->port),
1888 pf->offset_loaded, &os->eth.rx_broadcast,
1889 &ns->eth.rx_broadcast);
1890 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1891 pf->offset_loaded, &os->eth.rx_discards,
1892 &ns->eth.rx_discards);
1893 /* GLPRT_REPC not supported */
1894 /* GLPRT_RMPC not supported */
1895 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1897 &os->eth.rx_unknown_protocol,
1898 &ns->eth.rx_unknown_protocol);
1899 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1900 I40E_GLPRT_GOTCL(hw->port),
1901 pf->offset_loaded, &os->eth.tx_bytes,
1903 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1904 I40E_GLPRT_UPTCL(hw->port),
1905 pf->offset_loaded, &os->eth.tx_unicast,
1906 &ns->eth.tx_unicast);
1907 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1908 I40E_GLPRT_MPTCL(hw->port),
1909 pf->offset_loaded, &os->eth.tx_multicast,
1910 &ns->eth.tx_multicast);
1911 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1912 I40E_GLPRT_BPTCL(hw->port),
1913 pf->offset_loaded, &os->eth.tx_broadcast,
1914 &ns->eth.tx_broadcast);
1915 /* GLPRT_TEPC not supported */
1917 /* additional port specific stats */
1918 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1919 pf->offset_loaded, &os->tx_dropped_link_down,
1920 &ns->tx_dropped_link_down);
1921 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1922 pf->offset_loaded, &os->crc_errors,
1924 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1925 pf->offset_loaded, &os->illegal_bytes,
1926 &ns->illegal_bytes);
1927 /* GLPRT_ERRBC not supported */
1928 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1929 pf->offset_loaded, &os->mac_local_faults,
1930 &ns->mac_local_faults);
1931 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1932 pf->offset_loaded, &os->mac_remote_faults,
1933 &ns->mac_remote_faults);
1934 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1935 pf->offset_loaded, &os->rx_length_errors,
1936 &ns->rx_length_errors);
1937 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1938 pf->offset_loaded, &os->link_xon_rx,
1940 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1941 pf->offset_loaded, &os->link_xoff_rx,
1943 for (i = 0; i < 8; i++) {
1944 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1946 &os->priority_xon_rx[i],
1947 &ns->priority_xon_rx[i]);
1948 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1950 &os->priority_xoff_rx[i],
1951 &ns->priority_xoff_rx[i]);
1953 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1954 pf->offset_loaded, &os->link_xon_tx,
1956 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1957 pf->offset_loaded, &os->link_xoff_tx,
1959 for (i = 0; i < 8; i++) {
1960 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1962 &os->priority_xon_tx[i],
1963 &ns->priority_xon_tx[i]);
1964 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1966 &os->priority_xoff_tx[i],
1967 &ns->priority_xoff_tx[i]);
1968 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1970 &os->priority_xon_2_xoff[i],
1971 &ns->priority_xon_2_xoff[i]);
1973 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1974 I40E_GLPRT_PRC64L(hw->port),
1975 pf->offset_loaded, &os->rx_size_64,
1977 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1978 I40E_GLPRT_PRC127L(hw->port),
1979 pf->offset_loaded, &os->rx_size_127,
1981 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1982 I40E_GLPRT_PRC255L(hw->port),
1983 pf->offset_loaded, &os->rx_size_255,
1985 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1986 I40E_GLPRT_PRC511L(hw->port),
1987 pf->offset_loaded, &os->rx_size_511,
1989 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1990 I40E_GLPRT_PRC1023L(hw->port),
1991 pf->offset_loaded, &os->rx_size_1023,
1993 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1994 I40E_GLPRT_PRC1522L(hw->port),
1995 pf->offset_loaded, &os->rx_size_1522,
1997 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1998 I40E_GLPRT_PRC9522L(hw->port),
1999 pf->offset_loaded, &os->rx_size_big,
2001 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2002 pf->offset_loaded, &os->rx_undersize,
2004 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2005 pf->offset_loaded, &os->rx_fragments,
2007 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2008 pf->offset_loaded, &os->rx_oversize,
2010 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2011 pf->offset_loaded, &os->rx_jabber,
2013 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2014 I40E_GLPRT_PTC64L(hw->port),
2015 pf->offset_loaded, &os->tx_size_64,
2017 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2018 I40E_GLPRT_PTC127L(hw->port),
2019 pf->offset_loaded, &os->tx_size_127,
2021 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2022 I40E_GLPRT_PTC255L(hw->port),
2023 pf->offset_loaded, &os->tx_size_255,
2025 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2026 I40E_GLPRT_PTC511L(hw->port),
2027 pf->offset_loaded, &os->tx_size_511,
2029 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2030 I40E_GLPRT_PTC1023L(hw->port),
2031 pf->offset_loaded, &os->tx_size_1023,
2033 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2034 I40E_GLPRT_PTC1522L(hw->port),
2035 pf->offset_loaded, &os->tx_size_1522,
2037 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2038 I40E_GLPRT_PTC9522L(hw->port),
2039 pf->offset_loaded, &os->tx_size_big,
2041 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2043 &os->fd_sb_match, &ns->fd_sb_match);
2044 /* GLPRT_MSPDC not supported */
2045 /* GLPRT_XEC not supported */
2047 pf->offset_loaded = true;
2050 i40e_update_vsi_stats(pf->main_vsi);
2053 /* Get all statistics of a port */
2055 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2057 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2058 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2062 /* call read registers - updates values, now write them to struct */
2063 i40e_read_stats_registers(pf, hw);
2065 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2066 pf->main_vsi->eth_stats.rx_multicast +
2067 pf->main_vsi->eth_stats.rx_broadcast -
2068 pf->main_vsi->eth_stats.rx_discards;
2069 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2070 pf->main_vsi->eth_stats.tx_multicast +
2071 pf->main_vsi->eth_stats.tx_broadcast;
2072 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
2073 stats->obytes = pf->main_vsi->eth_stats.tx_bytes;
2074 stats->oerrors = ns->eth.tx_errors +
2075 pf->main_vsi->eth_stats.tx_errors;
2076 stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
2079 stats->imissed = ns->eth.rx_discards +
2080 pf->main_vsi->eth_stats.rx_discards;
2081 stats->ierrors = ns->crc_errors +
2082 ns->rx_length_errors + ns->rx_undersize +
2083 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2086 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2087 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2088 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2089 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2090 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2091 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2092 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2093 ns->eth.rx_unknown_protocol);
2094 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2095 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2096 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2097 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2098 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2099 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2101 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2102 ns->tx_dropped_link_down);
2103 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2104 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2106 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2107 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2108 ns->mac_local_faults);
2109 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2110 ns->mac_remote_faults);
2111 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2112 ns->rx_length_errors);
2113 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2114 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2115 for (i = 0; i < 8; i++) {
2116 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2117 i, ns->priority_xon_rx[i]);
2118 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2119 i, ns->priority_xoff_rx[i]);
2121 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2122 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2123 for (i = 0; i < 8; i++) {
2124 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2125 i, ns->priority_xon_tx[i]);
2126 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2127 i, ns->priority_xoff_tx[i]);
2128 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2129 i, ns->priority_xon_2_xoff[i]);
2131 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2132 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2133 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2134 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2135 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2136 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2137 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2138 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2139 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2140 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2141 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2142 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2143 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2144 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2145 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2146 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2147 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2148 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2149 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2150 ns->mac_short_packet_dropped);
2151 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2152 ns->checksum_error);
2153 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2154 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2157 /* Reset the statistics */
2159 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 /* Mark PF and VSI stats to update the offset, aka "reset" */
2165 pf->offset_loaded = false;
2167 pf->main_vsi->offset_loaded = false;
2169 /* read the stats, reading current register values into offset */
2170 i40e_read_stats_registers(pf, hw);
2174 i40e_xstats_calc_num(void)
2176 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2177 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2178 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2182 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2185 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187 unsigned i, count, prio;
2188 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2190 count = i40e_xstats_calc_num();
2194 i40e_read_stats_registers(pf, hw);
2201 /* Get stats from i40e_eth_stats struct */
2202 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2203 snprintf(xstats[count].name, sizeof(xstats[count].name),
2204 "%s", rte_i40e_stats_strings[i].name);
2205 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2206 rte_i40e_stats_strings[i].offset);
2210 /* Get individiual stats from i40e_hw_port struct */
2211 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2212 snprintf(xstats[count].name, sizeof(xstats[count].name),
2213 "%s", rte_i40e_hw_port_strings[i].name);
2214 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2215 rte_i40e_hw_port_strings[i].offset);
2219 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2220 for (prio = 0; prio < 8; prio++) {
2221 snprintf(xstats[count].name,
2222 sizeof(xstats[count].name),
2223 "rx_priority%u_%s", prio,
2224 rte_i40e_rxq_prio_strings[i].name);
2225 xstats[count].value =
2226 *(uint64_t *)(((char *)hw_stats) +
2227 rte_i40e_rxq_prio_strings[i].offset +
2228 (sizeof(uint64_t) * prio));
2233 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2234 for (prio = 0; prio < 8; prio++) {
2235 snprintf(xstats[count].name,
2236 sizeof(xstats[count].name),
2237 "tx_priority%u_%s", prio,
2238 rte_i40e_txq_prio_strings[i].name);
2239 xstats[count].value =
2240 *(uint64_t *)(((char *)hw_stats) +
2241 rte_i40e_txq_prio_strings[i].offset +
2242 (sizeof(uint64_t) * prio));
2251 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2252 __rte_unused uint16_t queue_id,
2253 __rte_unused uint8_t stat_idx,
2254 __rte_unused uint8_t is_rx)
2256 PMD_INIT_FUNC_TRACE();
2262 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2264 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2265 struct i40e_vsi *vsi = pf->main_vsi;
2267 dev_info->max_rx_queues = vsi->nb_qps;
2268 dev_info->max_tx_queues = vsi->nb_qps;
2269 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2270 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2271 dev_info->max_mac_addrs = vsi->max_macaddrs;
2272 dev_info->max_vfs = dev->pci_dev->max_vfs;
2273 dev_info->rx_offload_capa =
2274 DEV_RX_OFFLOAD_VLAN_STRIP |
2275 DEV_RX_OFFLOAD_QINQ_STRIP |
2276 DEV_RX_OFFLOAD_IPV4_CKSUM |
2277 DEV_RX_OFFLOAD_UDP_CKSUM |
2278 DEV_RX_OFFLOAD_TCP_CKSUM;
2279 dev_info->tx_offload_capa =
2280 DEV_TX_OFFLOAD_VLAN_INSERT |
2281 DEV_TX_OFFLOAD_QINQ_INSERT |
2282 DEV_TX_OFFLOAD_IPV4_CKSUM |
2283 DEV_TX_OFFLOAD_UDP_CKSUM |
2284 DEV_TX_OFFLOAD_TCP_CKSUM |
2285 DEV_TX_OFFLOAD_SCTP_CKSUM |
2286 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2287 DEV_TX_OFFLOAD_TCP_TSO;
2288 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2290 dev_info->reta_size = pf->hash_lut_size;
2291 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2293 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2295 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2296 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2297 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2299 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2303 dev_info->default_txconf = (struct rte_eth_txconf) {
2305 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2306 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2307 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2309 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2310 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2311 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2312 ETH_TXQ_FLAGS_NOOFFLOADS,
2315 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2316 .nb_max = I40E_MAX_RING_DESC,
2317 .nb_min = I40E_MIN_RING_DESC,
2318 .nb_align = I40E_ALIGN_RING_DESC,
2321 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2322 .nb_max = I40E_MAX_RING_DESC,
2323 .nb_min = I40E_MIN_RING_DESC,
2324 .nb_align = I40E_ALIGN_RING_DESC,
2327 if (pf->flags & I40E_FLAG_VMDQ) {
2328 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2329 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2330 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2331 pf->max_nb_vmdq_vsi;
2332 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2333 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2334 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2339 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2342 struct i40e_vsi *vsi = pf->main_vsi;
2343 PMD_INIT_FUNC_TRACE();
2346 return i40e_vsi_add_vlan(vsi, vlan_id);
2348 return i40e_vsi_delete_vlan(vsi, vlan_id);
2352 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2353 __rte_unused uint16_t tpid)
2355 PMD_INIT_FUNC_TRACE();
2359 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2361 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2362 struct i40e_vsi *vsi = pf->main_vsi;
2364 if (mask & ETH_VLAN_STRIP_MASK) {
2365 /* Enable or disable VLAN stripping */
2366 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2367 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2369 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2372 if (mask & ETH_VLAN_EXTEND_MASK) {
2373 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2374 i40e_vsi_config_double_vlan(vsi, TRUE);
2376 i40e_vsi_config_double_vlan(vsi, FALSE);
2381 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2382 __rte_unused uint16_t queue,
2383 __rte_unused int on)
2385 PMD_INIT_FUNC_TRACE();
2389 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2391 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2392 struct i40e_vsi *vsi = pf->main_vsi;
2393 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2394 struct i40e_vsi_vlan_pvid_info info;
2396 memset(&info, 0, sizeof(info));
2399 info.config.pvid = pvid;
2401 info.config.reject.tagged =
2402 data->dev_conf.txmode.hw_vlan_reject_tagged;
2403 info.config.reject.untagged =
2404 data->dev_conf.txmode.hw_vlan_reject_untagged;
2407 return i40e_vsi_vlan_pvid_set(vsi, &info);
2411 i40e_dev_led_on(struct rte_eth_dev *dev)
2413 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414 uint32_t mode = i40e_led_get(hw);
2417 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2423 i40e_dev_led_off(struct rte_eth_dev *dev)
2425 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426 uint32_t mode = i40e_led_get(hw);
2429 i40e_led_set(hw, 0, false);
2435 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2437 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2438 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2440 fc_conf->pause_time = pf->fc_conf.pause_time;
2441 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2442 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2444 /* Return current mode according to actual setting*/
2445 switch (hw->fc.current_mode) {
2447 fc_conf->mode = RTE_FC_FULL;
2449 case I40E_FC_TX_PAUSE:
2450 fc_conf->mode = RTE_FC_TX_PAUSE;
2452 case I40E_FC_RX_PAUSE:
2453 fc_conf->mode = RTE_FC_RX_PAUSE;
2457 fc_conf->mode = RTE_FC_NONE;
2464 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2466 uint32_t mflcn_reg, fctrl_reg, reg;
2467 uint32_t max_high_water;
2468 uint8_t i, aq_failure;
2472 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2473 [RTE_FC_NONE] = I40E_FC_NONE,
2474 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2475 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2476 [RTE_FC_FULL] = I40E_FC_FULL
2479 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2481 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2482 if ((fc_conf->high_water > max_high_water) ||
2483 (fc_conf->high_water < fc_conf->low_water)) {
2484 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2485 "High_water must <= %d.", max_high_water);
2489 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2491 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2493 pf->fc_conf.pause_time = fc_conf->pause_time;
2494 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2495 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2497 PMD_INIT_FUNC_TRACE();
2499 /* All the link flow control related enable/disable register
2500 * configuration is handle by the F/W
2502 err = i40e_set_fc(hw, &aq_failure, true);
2506 if (i40e_is_40G_device(hw->device_id)) {
2507 /* Configure flow control refresh threshold,
2508 * the value for stat_tx_pause_refresh_timer[8]
2509 * is used for global pause operation.
2513 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2514 pf->fc_conf.pause_time);
2516 /* configure the timer value included in transmitted pause
2518 * the value for stat_tx_pause_quanta[8] is used for global
2521 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2522 pf->fc_conf.pause_time);
2524 fctrl_reg = I40E_READ_REG(hw,
2525 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2527 if (fc_conf->mac_ctrl_frame_fwd != 0)
2528 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2530 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2532 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2535 /* Configure pause time (2 TCs per register) */
2536 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2537 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2538 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2540 /* Configure flow control refresh threshold value */
2541 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2542 pf->fc_conf.pause_time / 2);
2544 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2546 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2547 *depending on configuration
2549 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2550 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2551 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2553 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2554 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2557 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2560 /* config the water marker both based on the packets and bytes */
2561 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2562 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2563 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2564 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2565 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2566 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2567 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2568 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2570 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2571 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2574 I40E_WRITE_FLUSH(hw);
2580 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2581 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2583 PMD_INIT_FUNC_TRACE();
2588 /* Add a MAC address, and update filters */
2590 i40e_macaddr_add(struct rte_eth_dev *dev,
2591 struct ether_addr *mac_addr,
2592 __rte_unused uint32_t index,
2595 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2596 struct i40e_mac_filter_info mac_filter;
2597 struct i40e_vsi *vsi;
2600 /* If VMDQ not enabled or configured, return */
2601 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2602 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2603 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2608 if (pool > pf->nb_cfg_vmdq_vsi) {
2609 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2610 pool, pf->nb_cfg_vmdq_vsi);
2614 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2615 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2620 vsi = pf->vmdq[pool - 1].vsi;
2622 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2623 if (ret != I40E_SUCCESS) {
2624 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2629 /* Remove a MAC address, and update filters */
2631 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2633 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2634 struct i40e_vsi *vsi;
2635 struct rte_eth_dev_data *data = dev->data;
2636 struct ether_addr *macaddr;
2641 macaddr = &(data->mac_addrs[index]);
2643 pool_sel = dev->data->mac_pool_sel[index];
2645 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2646 if (pool_sel & (1ULL << i)) {
2650 /* No VMDQ pool enabled or configured */
2651 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2652 (i > pf->nb_cfg_vmdq_vsi)) {
2653 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2657 vsi = pf->vmdq[i - 1].vsi;
2659 ret = i40e_vsi_delete_mac(vsi, macaddr);
2662 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2669 /* Set perfect match or hash match of MAC and VLAN for a VF */
2671 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2672 struct rte_eth_mac_filter *filter,
2676 struct i40e_mac_filter_info mac_filter;
2677 struct ether_addr old_mac;
2678 struct ether_addr *new_mac;
2679 struct i40e_pf_vf *vf = NULL;
2684 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2687 hw = I40E_PF_TO_HW(pf);
2689 if (filter == NULL) {
2690 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2694 new_mac = &filter->mac_addr;
2696 if (is_zero_ether_addr(new_mac)) {
2697 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2701 vf_id = filter->dst_id;
2703 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2704 PMD_DRV_LOG(ERR, "Invalid argument.");
2707 vf = &pf->vfs[vf_id];
2709 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2710 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2715 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2716 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2718 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2721 mac_filter.filter_type = filter->filter_type;
2722 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2723 if (ret != I40E_SUCCESS) {
2724 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2727 ether_addr_copy(new_mac, &pf->dev_addr);
2729 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2731 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2732 if (ret != I40E_SUCCESS) {
2733 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2737 /* Clear device address as it has been removed */
2738 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2739 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2745 /* MAC filter handle */
2747 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2751 struct rte_eth_mac_filter *filter;
2752 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2753 int ret = I40E_NOT_SUPPORTED;
2755 filter = (struct rte_eth_mac_filter *)(arg);
2757 switch (filter_op) {
2758 case RTE_ETH_FILTER_NOP:
2761 case RTE_ETH_FILTER_ADD:
2762 i40e_pf_disable_irq0(hw);
2764 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2765 i40e_pf_enable_irq0(hw);
2767 case RTE_ETH_FILTER_DELETE:
2768 i40e_pf_disable_irq0(hw);
2770 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2771 i40e_pf_enable_irq0(hw);
2774 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2775 ret = I40E_ERR_PARAM;
2783 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2785 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2786 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2792 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2793 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2796 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2800 uint32_t *lut_dw = (uint32_t *)lut;
2801 uint16_t i, lut_size_dw = lut_size / 4;
2803 for (i = 0; i < lut_size_dw; i++)
2804 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2811 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2813 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2814 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2820 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2821 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2824 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2828 uint32_t *lut_dw = (uint32_t *)lut;
2829 uint16_t i, lut_size_dw = lut_size / 4;
2831 for (i = 0; i < lut_size_dw; i++)
2832 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2833 I40E_WRITE_FLUSH(hw);
2840 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2841 struct rte_eth_rss_reta_entry64 *reta_conf,
2844 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2845 uint16_t i, lut_size = pf->hash_lut_size;
2846 uint16_t idx, shift;
2850 if (reta_size != lut_size ||
2851 reta_size > ETH_RSS_RETA_SIZE_512) {
2852 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2853 "(%d) doesn't match the number hardware can supported "
2854 "(%d)\n", reta_size, lut_size);
2858 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2860 PMD_DRV_LOG(ERR, "No memory can be allocated");
2863 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2866 for (i = 0; i < reta_size; i++) {
2867 idx = i / RTE_RETA_GROUP_SIZE;
2868 shift = i % RTE_RETA_GROUP_SIZE;
2869 if (reta_conf[idx].mask & (1ULL << shift))
2870 lut[i] = reta_conf[idx].reta[shift];
2872 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2881 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2882 struct rte_eth_rss_reta_entry64 *reta_conf,
2885 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2886 uint16_t i, lut_size = pf->hash_lut_size;
2887 uint16_t idx, shift;
2891 if (reta_size != lut_size ||
2892 reta_size > ETH_RSS_RETA_SIZE_512) {
2893 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2894 "(%d) doesn't match the number hardware can supported "
2895 "(%d)\n", reta_size, lut_size);
2899 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2901 PMD_DRV_LOG(ERR, "No memory can be allocated");
2905 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2908 for (i = 0; i < reta_size; i++) {
2909 idx = i / RTE_RETA_GROUP_SIZE;
2910 shift = i % RTE_RETA_GROUP_SIZE;
2911 if (reta_conf[idx].mask & (1ULL << shift))
2912 reta_conf[idx].reta[shift] = lut[i];
2922 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2923 * @hw: pointer to the HW structure
2924 * @mem: pointer to mem struct to fill out
2925 * @size: size of memory requested
2926 * @alignment: what to align the allocation to
2928 enum i40e_status_code
2929 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2930 struct i40e_dma_mem *mem,
2934 const struct rte_memzone *mz = NULL;
2935 char z_name[RTE_MEMZONE_NAMESIZE];
2938 return I40E_ERR_PARAM;
2940 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2941 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2942 alignment, RTE_PGSIZE_2M);
2944 return I40E_ERR_NO_MEMORY;
2948 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2949 mem->zone = (const void *)mz;
2950 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2951 "%"PRIu64, mz->name, mem->pa);
2953 return I40E_SUCCESS;
2957 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2958 * @hw: pointer to the HW structure
2959 * @mem: ptr to mem struct to free
2961 enum i40e_status_code
2962 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2963 struct i40e_dma_mem *mem)
2966 return I40E_ERR_PARAM;
2968 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2969 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2971 rte_memzone_free((const struct rte_memzone *)mem->zone);
2976 return I40E_SUCCESS;
2980 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2981 * @hw: pointer to the HW structure
2982 * @mem: pointer to mem struct to fill out
2983 * @size: size of memory requested
2985 enum i40e_status_code
2986 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2987 struct i40e_virt_mem *mem,
2991 return I40E_ERR_PARAM;
2994 mem->va = rte_zmalloc("i40e", size, 0);
2997 return I40E_SUCCESS;
2999 return I40E_ERR_NO_MEMORY;
3003 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3004 * @hw: pointer to the HW structure
3005 * @mem: pointer to mem struct to free
3007 enum i40e_status_code
3008 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3009 struct i40e_virt_mem *mem)
3012 return I40E_ERR_PARAM;
3017 return I40E_SUCCESS;
3021 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3023 rte_spinlock_init(&sp->spinlock);
3027 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3029 rte_spinlock_lock(&sp->spinlock);
3033 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3035 rte_spinlock_unlock(&sp->spinlock);
3039 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3045 * Get the hardware capabilities, which will be parsed
3046 * and saved into struct i40e_hw.
3049 i40e_get_cap(struct i40e_hw *hw)
3051 struct i40e_aqc_list_capabilities_element_resp *buf;
3052 uint16_t len, size = 0;
3055 /* Calculate a huge enough buff for saving response data temporarily */
3056 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3057 I40E_MAX_CAP_ELE_NUM;
3058 buf = rte_zmalloc("i40e", len, 0);
3060 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3061 return I40E_ERR_NO_MEMORY;
3064 /* Get, parse the capabilities and save it to hw */
3065 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3066 i40e_aqc_opc_list_func_capabilities, NULL);
3067 if (ret != I40E_SUCCESS)
3068 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3070 /* Free the temporary buffer after being used */
3077 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3080 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3081 uint16_t qp_count = 0, vsi_count = 0;
3083 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3084 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3087 /* Add the parameter init for LFC */
3088 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3089 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3090 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3092 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3093 pf->max_num_vsi = hw->func_caps.num_vsis;
3094 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3095 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3096 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3098 /* FDir queue/VSI allocation */
3099 pf->fdir_qp_offset = 0;
3100 if (hw->func_caps.fd) {
3101 pf->flags |= I40E_FLAG_FDIR;
3102 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3104 pf->fdir_nb_qps = 0;
3106 qp_count += pf->fdir_nb_qps;
3109 /* LAN queue/VSI allocation */
3110 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3111 if (!hw->func_caps.rss) {
3114 pf->flags |= I40E_FLAG_RSS;
3115 if (hw->mac.type == I40E_MAC_X722)
3116 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3117 pf->lan_nb_qps = pf->lan_nb_qp_max;
3119 qp_count += pf->lan_nb_qps;
3122 /* VF queue/VSI allocation */
3123 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3124 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3125 pf->flags |= I40E_FLAG_SRIOV;
3126 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3127 pf->vf_num = dev->pci_dev->max_vfs;
3128 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3129 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3130 pf->vf_nb_qps * pf->vf_num);
3135 qp_count += pf->vf_nb_qps * pf->vf_num;
3136 vsi_count += pf->vf_num;
3138 /* VMDq queue/VSI allocation */
3139 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3140 pf->vmdq_nb_qps = 0;
3141 pf->max_nb_vmdq_vsi = 0;
3142 if (hw->func_caps.vmdq) {
3143 if (qp_count < hw->func_caps.num_tx_qp &&
3144 vsi_count < hw->func_caps.num_vsis) {
3145 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3146 qp_count) / pf->vmdq_nb_qp_max;
3148 /* Limit the maximum number of VMDq vsi to the maximum
3149 * ethdev can support
3151 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3152 hw->func_caps.num_vsis - vsi_count);
3153 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3155 if (pf->max_nb_vmdq_vsi) {
3156 pf->flags |= I40E_FLAG_VMDQ;
3157 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3158 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3159 "per VMDQ VSI, in total %u queues",
3160 pf->max_nb_vmdq_vsi,
3161 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3162 pf->max_nb_vmdq_vsi);
3164 PMD_DRV_LOG(INFO, "No enough queues left for "
3168 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3171 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3172 vsi_count += pf->max_nb_vmdq_vsi;
3174 if (hw->func_caps.dcb)
3175 pf->flags |= I40E_FLAG_DCB;
3177 if (qp_count > hw->func_caps.num_tx_qp) {
3178 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3179 "the hardware maximum %u", qp_count,
3180 hw->func_caps.num_tx_qp);
3183 if (vsi_count > hw->func_caps.num_vsis) {
3184 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3185 "the hardware maximum %u", vsi_count,
3186 hw->func_caps.num_vsis);
3194 i40e_pf_get_switch_config(struct i40e_pf *pf)
3196 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3197 struct i40e_aqc_get_switch_config_resp *switch_config;
3198 struct i40e_aqc_switch_config_element_resp *element;
3199 uint16_t start_seid = 0, num_reported;
3202 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3203 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3204 if (!switch_config) {
3205 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3209 /* Get the switch configurations */
3210 ret = i40e_aq_get_switch_config(hw, switch_config,
3211 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3212 if (ret != I40E_SUCCESS) {
3213 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3216 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3217 if (num_reported != 1) { /* The number should be 1 */
3218 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3222 /* Parse the switch configuration elements */
3223 element = &(switch_config->element[0]);
3224 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3225 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3226 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3228 PMD_DRV_LOG(INFO, "Unknown element type");
3231 rte_free(switch_config);
3237 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3240 struct pool_entry *entry;
3242 if (pool == NULL || num == 0)
3245 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3246 if (entry == NULL) {
3247 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3251 /* queue heap initialize */
3252 pool->num_free = num;
3253 pool->num_alloc = 0;
3255 LIST_INIT(&pool->alloc_list);
3256 LIST_INIT(&pool->free_list);
3258 /* Initialize element */
3262 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3267 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3269 struct pool_entry *entry;
3274 LIST_FOREACH(entry, &pool->alloc_list, next) {
3275 LIST_REMOVE(entry, next);
3279 LIST_FOREACH(entry, &pool->free_list, next) {
3280 LIST_REMOVE(entry, next);
3285 pool->num_alloc = 0;
3287 LIST_INIT(&pool->alloc_list);
3288 LIST_INIT(&pool->free_list);
3292 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3295 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3296 uint32_t pool_offset;
3300 PMD_DRV_LOG(ERR, "Invalid parameter");
3304 pool_offset = base - pool->base;
3305 /* Lookup in alloc list */
3306 LIST_FOREACH(entry, &pool->alloc_list, next) {
3307 if (entry->base == pool_offset) {
3308 valid_entry = entry;
3309 LIST_REMOVE(entry, next);
3314 /* Not find, return */
3315 if (valid_entry == NULL) {
3316 PMD_DRV_LOG(ERR, "Failed to find entry");
3321 * Found it, move it to free list and try to merge.
3322 * In order to make merge easier, always sort it by qbase.
3323 * Find adjacent prev and last entries.
3326 LIST_FOREACH(entry, &pool->free_list, next) {
3327 if (entry->base > valid_entry->base) {
3335 /* Try to merge with next one*/
3337 /* Merge with next one */
3338 if (valid_entry->base + valid_entry->len == next->base) {
3339 next->base = valid_entry->base;
3340 next->len += valid_entry->len;
3341 rte_free(valid_entry);
3348 /* Merge with previous one */
3349 if (prev->base + prev->len == valid_entry->base) {
3350 prev->len += valid_entry->len;
3351 /* If it merge with next one, remove next node */
3353 LIST_REMOVE(valid_entry, next);
3354 rte_free(valid_entry);
3356 rte_free(valid_entry);
3362 /* Not find any entry to merge, insert */
3365 LIST_INSERT_AFTER(prev, valid_entry, next);
3366 else if (next != NULL)
3367 LIST_INSERT_BEFORE(next, valid_entry, next);
3368 else /* It's empty list, insert to head */
3369 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3372 pool->num_free += valid_entry->len;
3373 pool->num_alloc -= valid_entry->len;
3379 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3382 struct pool_entry *entry, *valid_entry;
3384 if (pool == NULL || num == 0) {
3385 PMD_DRV_LOG(ERR, "Invalid parameter");
3389 if (pool->num_free < num) {
3390 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3391 num, pool->num_free);
3396 /* Lookup in free list and find most fit one */
3397 LIST_FOREACH(entry, &pool->free_list, next) {
3398 if (entry->len >= num) {
3400 if (entry->len == num) {
3401 valid_entry = entry;
3404 if (valid_entry == NULL || valid_entry->len > entry->len)
3405 valid_entry = entry;
3409 /* Not find one to satisfy the request, return */
3410 if (valid_entry == NULL) {
3411 PMD_DRV_LOG(ERR, "No valid entry found");
3415 * The entry have equal queue number as requested,
3416 * remove it from alloc_list.
3418 if (valid_entry->len == num) {
3419 LIST_REMOVE(valid_entry, next);
3422 * The entry have more numbers than requested,
3423 * create a new entry for alloc_list and minus its
3424 * queue base and number in free_list.
3426 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3427 if (entry == NULL) {
3428 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3432 entry->base = valid_entry->base;
3434 valid_entry->base += num;
3435 valid_entry->len -= num;
3436 valid_entry = entry;
3439 /* Insert it into alloc list, not sorted */
3440 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3442 pool->num_free -= valid_entry->len;
3443 pool->num_alloc += valid_entry->len;
3445 return (valid_entry->base + pool->base);
3449 * bitmap_is_subset - Check whether src2 is subset of src1
3452 bitmap_is_subset(uint8_t src1, uint8_t src2)
3454 return !((src1 ^ src2) & src2);
3457 static enum i40e_status_code
3458 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3460 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3462 /* If DCB is not supported, only default TC is supported */
3463 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3464 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3465 return I40E_NOT_SUPPORTED;
3468 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3469 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3470 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3472 return I40E_NOT_SUPPORTED;
3474 return I40E_SUCCESS;
3478 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3479 struct i40e_vsi_vlan_pvid_info *info)
3482 struct i40e_vsi_context ctxt;
3483 uint8_t vlan_flags = 0;
3486 if (vsi == NULL || info == NULL) {
3487 PMD_DRV_LOG(ERR, "invalid parameters");
3488 return I40E_ERR_PARAM;
3492 vsi->info.pvid = info->config.pvid;
3494 * If insert pvid is enabled, only tagged pkts are
3495 * allowed to be sent out.
3497 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3498 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3501 if (info->config.reject.tagged == 0)
3502 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3504 if (info->config.reject.untagged == 0)
3505 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3507 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3508 I40E_AQ_VSI_PVLAN_MODE_MASK);
3509 vsi->info.port_vlan_flags |= vlan_flags;
3510 vsi->info.valid_sections =
3511 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3512 memset(&ctxt, 0, sizeof(ctxt));
3513 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3514 ctxt.seid = vsi->seid;
3516 hw = I40E_VSI_TO_HW(vsi);
3517 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3518 if (ret != I40E_SUCCESS)
3519 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3525 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3527 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3529 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3531 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3532 if (ret != I40E_SUCCESS)
3536 PMD_DRV_LOG(ERR, "seid not valid");
3540 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3541 tc_bw_data.tc_valid_bits = enabled_tcmap;
3542 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3543 tc_bw_data.tc_bw_credits[i] =
3544 (enabled_tcmap & (1 << i)) ? 1 : 0;
3546 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3547 if (ret != I40E_SUCCESS) {
3548 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3552 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3553 sizeof(vsi->info.qs_handle));
3554 return I40E_SUCCESS;
3557 static enum i40e_status_code
3558 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3559 struct i40e_aqc_vsi_properties_data *info,
3560 uint8_t enabled_tcmap)
3562 enum i40e_status_code ret;
3563 int i, total_tc = 0;
3564 uint16_t qpnum_per_tc, bsf, qp_idx;
3566 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3567 if (ret != I40E_SUCCESS)
3570 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3571 if (enabled_tcmap & (1 << i))
3573 vsi->enabled_tc = enabled_tcmap;
3575 /* Number of queues per enabled TC */
3576 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3577 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3578 bsf = rte_bsf32(qpnum_per_tc);
3580 /* Adjust the queue number to actual queues that can be applied */
3581 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3582 vsi->nb_qps = qpnum_per_tc * total_tc;
3585 * Configure TC and queue mapping parameters, for enabled TC,
3586 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3587 * default queue will serve it.
3590 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3591 if (vsi->enabled_tc & (1 << i)) {
3592 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3593 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3594 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3595 qp_idx += qpnum_per_tc;
3597 info->tc_mapping[i] = 0;
3600 /* Associate queue number with VSI */
3601 if (vsi->type == I40E_VSI_SRIOV) {
3602 info->mapping_flags |=
3603 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3604 for (i = 0; i < vsi->nb_qps; i++)
3605 info->queue_mapping[i] =
3606 rte_cpu_to_le_16(vsi->base_queue + i);
3608 info->mapping_flags |=
3609 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3610 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3612 info->valid_sections |=
3613 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3615 return I40E_SUCCESS;
3619 i40e_veb_release(struct i40e_veb *veb)
3621 struct i40e_vsi *vsi;
3624 if (veb == NULL || veb->associate_vsi == NULL)
3627 if (!TAILQ_EMPTY(&veb->head)) {
3628 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3632 vsi = veb->associate_vsi;
3633 hw = I40E_VSI_TO_HW(vsi);
3635 vsi->uplink_seid = veb->uplink_seid;
3636 i40e_aq_delete_element(hw, veb->seid, NULL);
3639 return I40E_SUCCESS;
3643 static struct i40e_veb *
3644 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3646 struct i40e_veb *veb;
3650 if (NULL == pf || vsi == NULL) {
3651 PMD_DRV_LOG(ERR, "veb setup failed, "
3652 "associated VSI shouldn't null");
3655 hw = I40E_PF_TO_HW(pf);
3657 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3659 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3663 veb->associate_vsi = vsi;
3664 TAILQ_INIT(&veb->head);
3665 veb->uplink_seid = vsi->uplink_seid;
3667 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3668 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3670 if (ret != I40E_SUCCESS) {
3671 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3672 hw->aq.asq_last_status);
3676 /* get statistics index */
3677 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3678 &veb->stats_idx, NULL, NULL, NULL);
3679 if (ret != I40E_SUCCESS) {
3680 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3681 hw->aq.asq_last_status);
3685 /* Get VEB bandwidth, to be implemented */
3686 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3687 vsi->uplink_seid = veb->seid;
3696 i40e_vsi_release(struct i40e_vsi *vsi)
3700 struct i40e_vsi_list *vsi_list;
3702 struct i40e_mac_filter *f;
3705 return I40E_SUCCESS;
3707 pf = I40E_VSI_TO_PF(vsi);
3708 hw = I40E_VSI_TO_HW(vsi);
3710 /* VSI has child to attach, release child first */
3712 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3713 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3715 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3717 i40e_veb_release(vsi->veb);
3720 /* Remove all macvlan filters of the VSI */
3721 i40e_vsi_remove_all_macvlan_filter(vsi);
3722 TAILQ_FOREACH(f, &vsi->mac_list, next)
3725 if (vsi->type != I40E_VSI_MAIN) {
3726 /* Remove vsi from parent's sibling list */
3727 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3728 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3729 return I40E_ERR_PARAM;
3731 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3732 &vsi->sib_vsi_list, list);
3734 /* Remove all switch element of the VSI */
3735 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3736 if (ret != I40E_SUCCESS)
3737 PMD_DRV_LOG(ERR, "Failed to delete element");
3739 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3741 if (vsi->type != I40E_VSI_SRIOV)
3742 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3745 return I40E_SUCCESS;
3749 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3751 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3752 struct i40e_aqc_remove_macvlan_element_data def_filter;
3753 struct i40e_mac_filter_info filter;
3756 if (vsi->type != I40E_VSI_MAIN)
3757 return I40E_ERR_CONFIG;
3758 memset(&def_filter, 0, sizeof(def_filter));
3759 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3761 def_filter.vlan_tag = 0;
3762 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3763 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3764 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3765 if (ret != I40E_SUCCESS) {
3766 struct i40e_mac_filter *f;
3767 struct ether_addr *mac;
3769 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3771 /* It needs to add the permanent mac into mac list */
3772 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3774 PMD_DRV_LOG(ERR, "failed to allocate memory");
3775 return I40E_ERR_NO_MEMORY;
3777 mac = &f->mac_info.mac_addr;
3778 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3780 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3781 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3786 (void)rte_memcpy(&filter.mac_addr,
3787 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3788 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3789 return i40e_vsi_add_mac(vsi, &filter);
3793 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3795 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3796 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3797 struct i40e_hw *hw = &vsi->adapter->hw;
3801 memset(&bw_config, 0, sizeof(bw_config));
3802 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3803 if (ret != I40E_SUCCESS) {
3804 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3805 hw->aq.asq_last_status);
3809 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3810 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3811 &ets_sla_config, NULL);
3812 if (ret != I40E_SUCCESS) {
3813 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3814 "configuration %u", hw->aq.asq_last_status);
3818 /* Not store the info yet, just print out */
3819 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3820 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3821 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3822 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3823 ets_sla_config.share_credits[i]);
3824 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3825 rte_le_to_cpu_16(ets_sla_config.credits[i]));
3826 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3827 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3836 i40e_vsi_setup(struct i40e_pf *pf,
3837 enum i40e_vsi_type type,
3838 struct i40e_vsi *uplink_vsi,
3839 uint16_t user_param)
3841 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3842 struct i40e_vsi *vsi;
3843 struct i40e_mac_filter_info filter;
3845 struct i40e_vsi_context ctxt;
3846 struct ether_addr broadcast =
3847 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3849 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3850 PMD_DRV_LOG(ERR, "VSI setup failed, "
3851 "VSI link shouldn't be NULL");
3855 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3856 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3857 "uplink VSI should be NULL");
3861 /* If uplink vsi didn't setup VEB, create one first */
3862 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3863 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3865 if (NULL == uplink_vsi->veb) {
3866 PMD_DRV_LOG(ERR, "VEB setup failed");
3871 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3873 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3876 TAILQ_INIT(&vsi->mac_list);
3878 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3879 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3880 vsi->parent_vsi = uplink_vsi;
3881 vsi->user_param = user_param;
3882 /* Allocate queues */
3883 switch (vsi->type) {
3884 case I40E_VSI_MAIN :
3885 vsi->nb_qps = pf->lan_nb_qps;
3887 case I40E_VSI_SRIOV :
3888 vsi->nb_qps = pf->vf_nb_qps;
3890 case I40E_VSI_VMDQ2:
3891 vsi->nb_qps = pf->vmdq_nb_qps;
3894 vsi->nb_qps = pf->fdir_nb_qps;
3900 * The filter status descriptor is reported in rx queue 0,
3901 * while the tx queue for fdir filter programming has no
3902 * such constraints, can be non-zero queues.
3903 * To simplify it, choose FDIR vsi use queue 0 pair.
3904 * To make sure it will use queue 0 pair, queue allocation
3905 * need be done before this function is called
3907 if (type != I40E_VSI_FDIR) {
3908 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3910 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3914 vsi->base_queue = ret;
3916 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3918 /* VF has MSIX interrupt in VF range, don't allocate here */
3919 if (type == I40E_VSI_MAIN) {
3920 ret = i40e_res_pool_alloc(&pf->msix_pool,
3921 RTE_MIN(vsi->nb_qps,
3922 RTE_MAX_RXTX_INTR_VEC_ID));
3924 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3926 goto fail_queue_alloc;
3928 vsi->msix_intr = ret;
3929 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3930 } else if (type != I40E_VSI_SRIOV) {
3931 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3933 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3934 goto fail_queue_alloc;
3936 vsi->msix_intr = ret;
3944 if (type == I40E_VSI_MAIN) {
3945 /* For main VSI, no need to add since it's default one */
3946 vsi->uplink_seid = pf->mac_seid;
3947 vsi->seid = pf->main_vsi_seid;
3948 /* Bind queues with specific MSIX interrupt */
3950 * Needs 2 interrupt at least, one for misc cause which will
3951 * enabled from OS side, Another for queues binding the
3952 * interrupt from device side only.
3955 /* Get default VSI parameters from hardware */
3956 memset(&ctxt, 0, sizeof(ctxt));
3957 ctxt.seid = vsi->seid;
3958 ctxt.pf_num = hw->pf_id;
3959 ctxt.uplink_seid = vsi->uplink_seid;
3961 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3962 if (ret != I40E_SUCCESS) {
3963 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3964 goto fail_msix_alloc;
3966 (void)rte_memcpy(&vsi->info, &ctxt.info,
3967 sizeof(struct i40e_aqc_vsi_properties_data));
3968 vsi->vsi_id = ctxt.vsi_number;
3969 vsi->info.valid_sections = 0;
3971 /* Configure tc, enabled TC0 only */
3972 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3974 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3975 goto fail_msix_alloc;
3978 /* TC, queue mapping */
3979 memset(&ctxt, 0, sizeof(ctxt));
3980 vsi->info.valid_sections |=
3981 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3982 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3983 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3984 (void)rte_memcpy(&ctxt.info, &vsi->info,
3985 sizeof(struct i40e_aqc_vsi_properties_data));
3986 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3987 I40E_DEFAULT_TCMAP);
3988 if (ret != I40E_SUCCESS) {
3989 PMD_DRV_LOG(ERR, "Failed to configure "
3990 "TC queue mapping");
3991 goto fail_msix_alloc;
3993 ctxt.seid = vsi->seid;
3994 ctxt.pf_num = hw->pf_id;
3995 ctxt.uplink_seid = vsi->uplink_seid;
3998 /* Update VSI parameters */
3999 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4000 if (ret != I40E_SUCCESS) {
4001 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4002 goto fail_msix_alloc;
4005 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4006 sizeof(vsi->info.tc_mapping));
4007 (void)rte_memcpy(&vsi->info.queue_mapping,
4008 &ctxt.info.queue_mapping,
4009 sizeof(vsi->info.queue_mapping));
4010 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4011 vsi->info.valid_sections = 0;
4013 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4017 * Updating default filter settings are necessary to prevent
4018 * reception of tagged packets.
4019 * Some old firmware configurations load a default macvlan
4020 * filter which accepts both tagged and untagged packets.
4021 * The updating is to use a normal filter instead if needed.
4022 * For NVM 4.2.2 or after, the updating is not needed anymore.
4023 * The firmware with correct configurations load the default
4024 * macvlan filter which is expected and cannot be removed.
4026 i40e_update_default_filter_setting(vsi);
4027 i40e_config_qinq(hw, vsi);
4028 } else if (type == I40E_VSI_SRIOV) {
4029 memset(&ctxt, 0, sizeof(ctxt));
4031 * For other VSI, the uplink_seid equals to uplink VSI's
4032 * uplink_seid since they share same VEB
4034 vsi->uplink_seid = uplink_vsi->uplink_seid;
4035 ctxt.pf_num = hw->pf_id;
4036 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4037 ctxt.uplink_seid = vsi->uplink_seid;
4038 ctxt.connection_type = 0x1;
4039 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4042 * Do not configure switch ID to enable VEB switch by
4043 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4044 * if the source mac address of packet sent from VF is not
4045 * listed in the VEB's mac table, the VEB will switch the
4046 * packet back to the VF. Need to enable it when HW issue
4050 /* Configure port/vlan */
4051 ctxt.info.valid_sections |=
4052 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4053 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4054 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4055 I40E_DEFAULT_TCMAP);
4056 if (ret != I40E_SUCCESS) {
4057 PMD_DRV_LOG(ERR, "Failed to configure "
4058 "TC queue mapping");
4059 goto fail_msix_alloc;
4061 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4062 ctxt.info.valid_sections |=
4063 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4065 * Since VSI is not created yet, only configure parameter,
4066 * will add vsi below.
4069 i40e_config_qinq(hw, vsi);
4070 } else if (type == I40E_VSI_VMDQ2) {
4071 memset(&ctxt, 0, sizeof(ctxt));
4073 * For other VSI, the uplink_seid equals to uplink VSI's
4074 * uplink_seid since they share same VEB
4076 vsi->uplink_seid = uplink_vsi->uplink_seid;
4077 ctxt.pf_num = hw->pf_id;
4079 ctxt.uplink_seid = vsi->uplink_seid;
4080 ctxt.connection_type = 0x1;
4081 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4083 ctxt.info.valid_sections |=
4084 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4085 /* user_param carries flag to enable loop back */
4087 ctxt.info.switch_id =
4088 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4089 ctxt.info.switch_id |=
4090 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4093 /* Configure port/vlan */
4094 ctxt.info.valid_sections |=
4095 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4096 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4097 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4098 I40E_DEFAULT_TCMAP);
4099 if (ret != I40E_SUCCESS) {
4100 PMD_DRV_LOG(ERR, "Failed to configure "
4101 "TC queue mapping");
4102 goto fail_msix_alloc;
4104 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4105 ctxt.info.valid_sections |=
4106 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4107 } else if (type == I40E_VSI_FDIR) {
4108 memset(&ctxt, 0, sizeof(ctxt));
4109 vsi->uplink_seid = uplink_vsi->uplink_seid;
4110 ctxt.pf_num = hw->pf_id;
4112 ctxt.uplink_seid = vsi->uplink_seid;
4113 ctxt.connection_type = 0x1; /* regular data port */
4114 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4115 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4116 I40E_DEFAULT_TCMAP);
4117 if (ret != I40E_SUCCESS) {
4118 PMD_DRV_LOG(ERR, "Failed to configure "
4119 "TC queue mapping.");
4120 goto fail_msix_alloc;
4122 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4123 ctxt.info.valid_sections |=
4124 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4126 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4127 goto fail_msix_alloc;
4130 if (vsi->type != I40E_VSI_MAIN) {
4131 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4132 if (ret != I40E_SUCCESS) {
4133 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4134 hw->aq.asq_last_status);
4135 goto fail_msix_alloc;
4137 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4138 vsi->info.valid_sections = 0;
4139 vsi->seid = ctxt.seid;
4140 vsi->vsi_id = ctxt.vsi_number;
4141 vsi->sib_vsi_list.vsi = vsi;
4142 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4143 &vsi->sib_vsi_list, list);
4146 /* MAC/VLAN configuration */
4147 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4148 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4150 ret = i40e_vsi_add_mac(vsi, &filter);
4151 if (ret != I40E_SUCCESS) {
4152 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4153 goto fail_msix_alloc;
4156 /* Get VSI BW information */
4157 i40e_vsi_dump_bw_config(vsi);
4160 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4162 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4168 /* Configure vlan stripping on or off */
4170 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4172 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4173 struct i40e_vsi_context ctxt;
4175 int ret = I40E_SUCCESS;
4177 /* Check if it has been already on or off */
4178 if (vsi->info.valid_sections &
4179 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4181 if ((vsi->info.port_vlan_flags &
4182 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4183 return 0; /* already on */
4185 if ((vsi->info.port_vlan_flags &
4186 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4187 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4188 return 0; /* already off */
4193 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4195 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4196 vsi->info.valid_sections =
4197 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4198 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4199 vsi->info.port_vlan_flags |= vlan_flags;
4200 ctxt.seid = vsi->seid;
4201 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4202 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4204 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4205 on ? "enable" : "disable");
4211 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4213 struct rte_eth_dev_data *data = dev->data;
4216 /* Apply vlan offload setting */
4217 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4219 /* Apply double-vlan setting, not implemented yet */
4221 /* Apply pvid setting */
4222 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4223 data->dev_conf.txmode.hw_vlan_insert_pvid);
4225 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4231 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4233 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4235 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4239 i40e_update_flow_control(struct i40e_hw *hw)
4241 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4242 struct i40e_link_status link_status;
4243 uint32_t rxfc = 0, txfc = 0, reg;
4247 memset(&link_status, 0, sizeof(link_status));
4248 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4249 if (ret != I40E_SUCCESS) {
4250 PMD_DRV_LOG(ERR, "Failed to get link status information");
4251 goto write_reg; /* Disable flow control */
4254 an_info = hw->phy.link_info.an_info;
4255 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4256 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4257 ret = I40E_ERR_NOT_READY;
4258 goto write_reg; /* Disable flow control */
4261 * If link auto negotiation is enabled, flow control needs to
4262 * be configured according to it
4264 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4265 case I40E_LINK_PAUSE_RXTX:
4268 hw->fc.current_mode = I40E_FC_FULL;
4270 case I40E_AQ_LINK_PAUSE_RX:
4272 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4274 case I40E_AQ_LINK_PAUSE_TX:
4276 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4279 hw->fc.current_mode = I40E_FC_NONE;
4284 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4285 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4286 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4287 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4288 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4289 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4296 i40e_pf_setup(struct i40e_pf *pf)
4298 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4299 struct i40e_filter_control_settings settings;
4300 struct i40e_vsi *vsi;
4303 /* Clear all stats counters */
4304 pf->offset_loaded = FALSE;
4305 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4306 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4308 ret = i40e_pf_get_switch_config(pf);
4309 if (ret != I40E_SUCCESS) {
4310 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4313 if (pf->flags & I40E_FLAG_FDIR) {
4314 /* make queue allocated first, let FDIR use queue pair 0*/
4315 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4316 if (ret != I40E_FDIR_QUEUE_ID) {
4317 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4319 pf->flags &= ~I40E_FLAG_FDIR;
4322 /* main VSI setup */
4323 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4325 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4326 return I40E_ERR_NOT_READY;
4330 /* Configure filter control */
4331 memset(&settings, 0, sizeof(settings));
4332 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4333 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4334 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4335 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4337 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4338 hw->func_caps.rss_table_size);
4339 return I40E_ERR_PARAM;
4341 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4342 "size: %u\n", hw->func_caps.rss_table_size);
4343 pf->hash_lut_size = hw->func_caps.rss_table_size;
4345 /* Enable ethtype and macvlan filters */
4346 settings.enable_ethtype = TRUE;
4347 settings.enable_macvlan = TRUE;
4348 ret = i40e_set_filter_control(hw, &settings);
4350 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4353 /* Update flow control according to the auto negotiation */
4354 i40e_update_flow_control(hw);
4356 return I40E_SUCCESS;
4360 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4366 * Set or clear TX Queue Disable flags,
4367 * which is required by hardware.
4369 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4370 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4372 /* Wait until the request is finished */
4373 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4374 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4375 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4376 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4377 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4383 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4384 return I40E_SUCCESS; /* already on, skip next steps */
4386 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4387 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4389 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4390 return I40E_SUCCESS; /* already off, skip next steps */
4391 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4393 /* Write the register */
4394 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4395 /* Check the result */
4396 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4397 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4398 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4400 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4401 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4404 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4405 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4409 /* Check if it is timeout */
4410 if (j >= I40E_CHK_Q_ENA_COUNT) {
4411 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4412 (on ? "enable" : "disable"), q_idx);
4413 return I40E_ERR_TIMEOUT;
4416 return I40E_SUCCESS;
4419 /* Swith on or off the tx queues */
4421 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4423 struct rte_eth_dev_data *dev_data = pf->dev_data;
4424 struct i40e_tx_queue *txq;
4425 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4429 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4430 txq = dev_data->tx_queues[i];
4431 /* Don't operate the queue if not configured or
4432 * if starting only per queue */
4433 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4436 ret = i40e_dev_tx_queue_start(dev, i);
4438 ret = i40e_dev_tx_queue_stop(dev, i);
4439 if ( ret != I40E_SUCCESS)
4443 return I40E_SUCCESS;
4447 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4452 /* Wait until the request is finished */
4453 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4454 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4455 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4456 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4457 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4462 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4463 return I40E_SUCCESS; /* Already on, skip next steps */
4464 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4466 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4467 return I40E_SUCCESS; /* Already off, skip next steps */
4468 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4471 /* Write the register */
4472 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4473 /* Check the result */
4474 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4475 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4476 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4478 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4479 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4482 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4483 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4488 /* Check if it is timeout */
4489 if (j >= I40E_CHK_Q_ENA_COUNT) {
4490 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4491 (on ? "enable" : "disable"), q_idx);
4492 return I40E_ERR_TIMEOUT;
4495 return I40E_SUCCESS;
4497 /* Switch on or off the rx queues */
4499 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4501 struct rte_eth_dev_data *dev_data = pf->dev_data;
4502 struct i40e_rx_queue *rxq;
4503 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4507 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4508 rxq = dev_data->rx_queues[i];
4509 /* Don't operate the queue if not configured or
4510 * if starting only per queue */
4511 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4514 ret = i40e_dev_rx_queue_start(dev, i);
4516 ret = i40e_dev_rx_queue_stop(dev, i);
4517 if (ret != I40E_SUCCESS)
4521 return I40E_SUCCESS;
4524 /* Switch on or off all the rx/tx queues */
4526 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4531 /* enable rx queues before enabling tx queues */
4532 ret = i40e_dev_switch_rx_queues(pf, on);
4534 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4537 ret = i40e_dev_switch_tx_queues(pf, on);
4539 /* Stop tx queues before stopping rx queues */
4540 ret = i40e_dev_switch_tx_queues(pf, on);
4542 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4545 ret = i40e_dev_switch_rx_queues(pf, on);
4551 /* Initialize VSI for TX */
4553 i40e_dev_tx_init(struct i40e_pf *pf)
4555 struct rte_eth_dev_data *data = pf->dev_data;
4557 uint32_t ret = I40E_SUCCESS;
4558 struct i40e_tx_queue *txq;
4560 for (i = 0; i < data->nb_tx_queues; i++) {
4561 txq = data->tx_queues[i];
4562 if (!txq || !txq->q_set)
4564 ret = i40e_tx_queue_init(txq);
4565 if (ret != I40E_SUCCESS)
4568 if (ret == I40E_SUCCESS)
4569 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4575 /* Initialize VSI for RX */
4577 i40e_dev_rx_init(struct i40e_pf *pf)
4579 struct rte_eth_dev_data *data = pf->dev_data;
4580 int ret = I40E_SUCCESS;
4582 struct i40e_rx_queue *rxq;
4584 i40e_pf_config_mq_rx(pf);
4585 for (i = 0; i < data->nb_rx_queues; i++) {
4586 rxq = data->rx_queues[i];
4587 if (!rxq || !rxq->q_set)
4590 ret = i40e_rx_queue_init(rxq);
4591 if (ret != I40E_SUCCESS) {
4592 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4597 if (ret == I40E_SUCCESS)
4598 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4605 i40e_dev_rxtx_init(struct i40e_pf *pf)
4609 err = i40e_dev_tx_init(pf);
4611 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4614 err = i40e_dev_rx_init(pf);
4616 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4624 i40e_vmdq_setup(struct rte_eth_dev *dev)
4626 struct rte_eth_conf *conf = &dev->data->dev_conf;
4627 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4628 int i, err, conf_vsis, j, loop;
4629 struct i40e_vsi *vsi;
4630 struct i40e_vmdq_info *vmdq_info;
4631 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4632 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4635 * Disable interrupt to avoid message from VF. Furthermore, it will
4636 * avoid race condition in VSI creation/destroy.
4638 i40e_pf_disable_irq0(hw);
4640 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4641 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4645 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4646 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4647 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4648 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4649 pf->max_nb_vmdq_vsi);
4653 if (pf->vmdq != NULL) {
4654 PMD_INIT_LOG(INFO, "VMDQ already configured");
4658 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4659 sizeof(*vmdq_info) * conf_vsis, 0);
4661 if (pf->vmdq == NULL) {
4662 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4666 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4668 /* Create VMDQ VSI */
4669 for (i = 0; i < conf_vsis; i++) {
4670 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4671 vmdq_conf->enable_loop_back);
4673 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4677 vmdq_info = &pf->vmdq[i];
4679 vmdq_info->vsi = vsi;
4681 pf->nb_cfg_vmdq_vsi = conf_vsis;
4683 /* Configure Vlan */
4684 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4685 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4686 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4687 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4688 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4689 vmdq_conf->pool_map[i].vlan_id, j);
4691 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4692 vmdq_conf->pool_map[i].vlan_id);
4694 PMD_INIT_LOG(ERR, "Failed to add vlan");
4702 i40e_pf_enable_irq0(hw);
4707 for (i = 0; i < conf_vsis; i++)
4708 if (pf->vmdq[i].vsi == NULL)
4711 i40e_vsi_release(pf->vmdq[i].vsi);
4715 i40e_pf_enable_irq0(hw);
4720 i40e_stat_update_32(struct i40e_hw *hw,
4728 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4732 if (new_data >= *offset)
4733 *stat = (uint64_t)(new_data - *offset);
4735 *stat = (uint64_t)((new_data +
4736 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4740 i40e_stat_update_48(struct i40e_hw *hw,
4749 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4750 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4751 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4756 if (new_data >= *offset)
4757 *stat = new_data - *offset;
4759 *stat = (uint64_t)((new_data +
4760 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4762 *stat &= I40E_48_BIT_MASK;
4767 i40e_pf_disable_irq0(struct i40e_hw *hw)
4769 /* Disable all interrupt types */
4770 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4771 I40E_WRITE_FLUSH(hw);
4776 i40e_pf_enable_irq0(struct i40e_hw *hw)
4778 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4779 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4780 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4781 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4782 I40E_WRITE_FLUSH(hw);
4786 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4788 /* read pending request and disable first */
4789 i40e_pf_disable_irq0(hw);
4790 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4791 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4792 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4795 /* Link no queues with irq0 */
4796 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4797 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4801 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4807 uint32_t index, offset, val;
4812 * Try to find which VF trigger a reset, use absolute VF id to access
4813 * since the reg is global register.
4815 for (i = 0; i < pf->vf_num; i++) {
4816 abs_vf_id = hw->func_caps.vf_base_id + i;
4817 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4818 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4819 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4820 /* VFR event occured */
4821 if (val & (0x1 << offset)) {
4824 /* Clear the event first */
4825 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4827 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4829 * Only notify a VF reset event occured,
4830 * don't trigger another SW reset
4832 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4833 if (ret != I40E_SUCCESS)
4834 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4840 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4843 struct i40e_arq_event_info info;
4844 uint16_t pending, opcode;
4847 info.buf_len = I40E_AQ_BUF_SZ;
4848 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4849 if (!info.msg_buf) {
4850 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4856 ret = i40e_clean_arq_element(hw, &info, &pending);
4858 if (ret != I40E_SUCCESS) {
4859 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4860 "aq_err: %u", hw->aq.asq_last_status);
4863 opcode = rte_le_to_cpu_16(info.desc.opcode);
4866 case i40e_aqc_opc_send_msg_to_pf:
4867 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4868 i40e_pf_host_handle_vf_msg(dev,
4869 rte_le_to_cpu_16(info.desc.retval),
4870 rte_le_to_cpu_32(info.desc.cookie_high),
4871 rte_le_to_cpu_32(info.desc.cookie_low),
4876 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4881 rte_free(info.msg_buf);
4885 * Interrupt handler is registered as the alarm callback for handling LSC
4886 * interrupt in a definite of time, in order to wait the NIC into a stable
4887 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4888 * no need for link down interrupt.
4891 i40e_dev_interrupt_delayed_handler(void *param)
4893 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4894 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897 /* read interrupt causes again */
4898 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4900 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4901 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4902 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4903 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4904 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4905 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4906 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4907 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4908 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4909 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4910 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4912 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4913 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4914 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4915 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4916 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4918 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4919 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4920 i40e_dev_handle_vfr_event(dev);
4922 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4923 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4924 i40e_dev_handle_aq_msg(dev);
4927 /* handle the link up interrupt in an alarm callback */
4928 i40e_dev_link_update(dev, 0);
4929 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4931 i40e_pf_enable_irq0(hw);
4932 rte_intr_enable(&(dev->pci_dev->intr_handle));
4936 * Interrupt handler triggered by NIC for handling
4937 * specific interrupt.
4940 * Pointer to interrupt handle.
4942 * The address of parameter (struct rte_eth_dev *) regsitered before.
4948 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4951 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4952 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955 /* Disable interrupt */
4956 i40e_pf_disable_irq0(hw);
4958 /* read out interrupt causes */
4959 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4961 /* No interrupt event indicated */
4962 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4963 PMD_DRV_LOG(INFO, "No interrupt event");
4966 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4967 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4968 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4969 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4970 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4971 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4972 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4973 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4974 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4975 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4976 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4977 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4978 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4979 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4980 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4981 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4983 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4984 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4985 i40e_dev_handle_vfr_event(dev);
4987 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4988 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4989 i40e_dev_handle_aq_msg(dev);
4992 /* Link Status Change interrupt */
4993 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4994 #define I40E_US_PER_SECOND 1000000
4995 struct rte_eth_link link;
4997 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4998 memset(&link, 0, sizeof(link));
4999 rte_i40e_dev_atomic_read_link_status(dev, &link);
5000 i40e_dev_link_update(dev, 0);
5003 * For link up interrupt, it needs to wait 1 second to let the
5004 * hardware be a stable state. Otherwise several consecutive
5005 * interrupts can be observed.
5006 * For link down interrupt, no need to wait.
5008 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5009 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5012 _rte_eth_dev_callback_process(dev,
5013 RTE_ETH_EVENT_INTR_LSC);
5017 /* Enable interrupt */
5018 i40e_pf_enable_irq0(hw);
5019 rte_intr_enable(&(dev->pci_dev->intr_handle));
5023 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5024 struct i40e_macvlan_filter *filter,
5027 int ele_num, ele_buff_size;
5028 int num, actual_num, i;
5030 int ret = I40E_SUCCESS;
5031 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5032 struct i40e_aqc_add_macvlan_element_data *req_list;
5034 if (filter == NULL || total == 0)
5035 return I40E_ERR_PARAM;
5036 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5037 ele_buff_size = hw->aq.asq_buf_size;
5039 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5040 if (req_list == NULL) {
5041 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5042 return I40E_ERR_NO_MEMORY;
5047 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5048 memset(req_list, 0, ele_buff_size);
5050 for (i = 0; i < actual_num; i++) {
5051 (void)rte_memcpy(req_list[i].mac_addr,
5052 &filter[num + i].macaddr, ETH_ADDR_LEN);
5053 req_list[i].vlan_tag =
5054 rte_cpu_to_le_16(filter[num + i].vlan_id);
5056 switch (filter[num + i].filter_type) {
5057 case RTE_MAC_PERFECT_MATCH:
5058 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5059 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5061 case RTE_MACVLAN_PERFECT_MATCH:
5062 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5064 case RTE_MAC_HASH_MATCH:
5065 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5066 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5068 case RTE_MACVLAN_HASH_MATCH:
5069 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5072 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5073 ret = I40E_ERR_PARAM;
5077 req_list[i].queue_number = 0;
5079 req_list[i].flags = rte_cpu_to_le_16(flags);
5082 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5084 if (ret != I40E_SUCCESS) {
5085 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5089 } while (num < total);
5097 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5098 struct i40e_macvlan_filter *filter,
5101 int ele_num, ele_buff_size;
5102 int num, actual_num, i;
5104 int ret = I40E_SUCCESS;
5105 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5106 struct i40e_aqc_remove_macvlan_element_data *req_list;
5108 if (filter == NULL || total == 0)
5109 return I40E_ERR_PARAM;
5111 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5112 ele_buff_size = hw->aq.asq_buf_size;
5114 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5115 if (req_list == NULL) {
5116 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5117 return I40E_ERR_NO_MEMORY;
5122 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5123 memset(req_list, 0, ele_buff_size);
5125 for (i = 0; i < actual_num; i++) {
5126 (void)rte_memcpy(req_list[i].mac_addr,
5127 &filter[num + i].macaddr, ETH_ADDR_LEN);
5128 req_list[i].vlan_tag =
5129 rte_cpu_to_le_16(filter[num + i].vlan_id);
5131 switch (filter[num + i].filter_type) {
5132 case RTE_MAC_PERFECT_MATCH:
5133 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5134 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5136 case RTE_MACVLAN_PERFECT_MATCH:
5137 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5139 case RTE_MAC_HASH_MATCH:
5140 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5141 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5143 case RTE_MACVLAN_HASH_MATCH:
5144 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5147 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5148 ret = I40E_ERR_PARAM;
5151 req_list[i].flags = rte_cpu_to_le_16(flags);
5154 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5156 if (ret != I40E_SUCCESS) {
5157 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5161 } while (num < total);
5168 /* Find out specific MAC filter */
5169 static struct i40e_mac_filter *
5170 i40e_find_mac_filter(struct i40e_vsi *vsi,
5171 struct ether_addr *macaddr)
5173 struct i40e_mac_filter *f;
5175 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5176 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5184 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5187 uint32_t vid_idx, vid_bit;
5189 if (vlan_id > ETH_VLAN_ID_MAX)
5192 vid_idx = I40E_VFTA_IDX(vlan_id);
5193 vid_bit = I40E_VFTA_BIT(vlan_id);
5195 if (vsi->vfta[vid_idx] & vid_bit)
5202 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5203 uint16_t vlan_id, bool on)
5205 uint32_t vid_idx, vid_bit;
5207 if (vlan_id > ETH_VLAN_ID_MAX)
5210 vid_idx = I40E_VFTA_IDX(vlan_id);
5211 vid_bit = I40E_VFTA_BIT(vlan_id);
5214 vsi->vfta[vid_idx] |= vid_bit;
5216 vsi->vfta[vid_idx] &= ~vid_bit;
5220 * Find all vlan options for specific mac addr,
5221 * return with actual vlan found.
5224 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5225 struct i40e_macvlan_filter *mv_f,
5226 int num, struct ether_addr *addr)
5232 * Not to use i40e_find_vlan_filter to decrease the loop time,
5233 * although the code looks complex.
5235 if (num < vsi->vlan_num)
5236 return I40E_ERR_PARAM;
5239 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5241 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5242 if (vsi->vfta[j] & (1 << k)) {
5244 PMD_DRV_LOG(ERR, "vlan number "
5246 return I40E_ERR_PARAM;
5248 (void)rte_memcpy(&mv_f[i].macaddr,
5249 addr, ETH_ADDR_LEN);
5251 j * I40E_UINT32_BIT_SIZE + k;
5257 return I40E_SUCCESS;
5261 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5262 struct i40e_macvlan_filter *mv_f,
5267 struct i40e_mac_filter *f;
5269 if (num < vsi->mac_num)
5270 return I40E_ERR_PARAM;
5272 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5274 PMD_DRV_LOG(ERR, "buffer number not match");
5275 return I40E_ERR_PARAM;
5277 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5279 mv_f[i].vlan_id = vlan;
5280 mv_f[i].filter_type = f->mac_info.filter_type;
5284 return I40E_SUCCESS;
5288 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5291 struct i40e_mac_filter *f;
5292 struct i40e_macvlan_filter *mv_f;
5293 int ret = I40E_SUCCESS;
5295 if (vsi == NULL || vsi->mac_num == 0)
5296 return I40E_ERR_PARAM;
5298 /* Case that no vlan is set */
5299 if (vsi->vlan_num == 0)
5302 num = vsi->mac_num * vsi->vlan_num;
5304 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5306 PMD_DRV_LOG(ERR, "failed to allocate memory");
5307 return I40E_ERR_NO_MEMORY;
5311 if (vsi->vlan_num == 0) {
5312 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5313 (void)rte_memcpy(&mv_f[i].macaddr,
5314 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5315 mv_f[i].vlan_id = 0;
5319 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5320 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5321 vsi->vlan_num, &f->mac_info.mac_addr);
5322 if (ret != I40E_SUCCESS)
5328 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5336 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5338 struct i40e_macvlan_filter *mv_f;
5340 int ret = I40E_SUCCESS;
5342 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5343 return I40E_ERR_PARAM;
5345 /* If it's already set, just return */
5346 if (i40e_find_vlan_filter(vsi,vlan))
5347 return I40E_SUCCESS;
5349 mac_num = vsi->mac_num;
5352 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5353 return I40E_ERR_PARAM;
5356 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5359 PMD_DRV_LOG(ERR, "failed to allocate memory");
5360 return I40E_ERR_NO_MEMORY;
5363 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5365 if (ret != I40E_SUCCESS)
5368 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5370 if (ret != I40E_SUCCESS)
5373 i40e_set_vlan_filter(vsi, vlan, 1);
5383 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5385 struct i40e_macvlan_filter *mv_f;
5387 int ret = I40E_SUCCESS;
5390 * Vlan 0 is the generic filter for untagged packets
5391 * and can't be removed.
5393 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5394 return I40E_ERR_PARAM;
5396 /* If can't find it, just return */
5397 if (!i40e_find_vlan_filter(vsi, vlan))
5398 return I40E_ERR_PARAM;
5400 mac_num = vsi->mac_num;
5403 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5404 return I40E_ERR_PARAM;
5407 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5410 PMD_DRV_LOG(ERR, "failed to allocate memory");
5411 return I40E_ERR_NO_MEMORY;
5414 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5416 if (ret != I40E_SUCCESS)
5419 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5421 if (ret != I40E_SUCCESS)
5424 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5425 if (vsi->vlan_num == 1) {
5426 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5427 if (ret != I40E_SUCCESS)
5430 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5431 if (ret != I40E_SUCCESS)
5435 i40e_set_vlan_filter(vsi, vlan, 0);
5445 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5447 struct i40e_mac_filter *f;
5448 struct i40e_macvlan_filter *mv_f;
5449 int i, vlan_num = 0;
5450 int ret = I40E_SUCCESS;
5452 /* If it's add and we've config it, return */
5453 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5455 return I40E_SUCCESS;
5456 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5457 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5460 * If vlan_num is 0, that's the first time to add mac,
5461 * set mask for vlan_id 0.
5463 if (vsi->vlan_num == 0) {
5464 i40e_set_vlan_filter(vsi, 0, 1);
5467 vlan_num = vsi->vlan_num;
5468 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5469 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5472 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5474 PMD_DRV_LOG(ERR, "failed to allocate memory");
5475 return I40E_ERR_NO_MEMORY;
5478 for (i = 0; i < vlan_num; i++) {
5479 mv_f[i].filter_type = mac_filter->filter_type;
5480 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5484 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5485 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5486 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5487 &mac_filter->mac_addr);
5488 if (ret != I40E_SUCCESS)
5492 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5493 if (ret != I40E_SUCCESS)
5496 /* Add the mac addr into mac list */
5497 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5499 PMD_DRV_LOG(ERR, "failed to allocate memory");
5500 ret = I40E_ERR_NO_MEMORY;
5503 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5505 f->mac_info.filter_type = mac_filter->filter_type;
5506 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5517 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5519 struct i40e_mac_filter *f;
5520 struct i40e_macvlan_filter *mv_f;
5522 enum rte_mac_filter_type filter_type;
5523 int ret = I40E_SUCCESS;
5525 /* Can't find it, return an error */
5526 f = i40e_find_mac_filter(vsi, addr);
5528 return I40E_ERR_PARAM;
5530 vlan_num = vsi->vlan_num;
5531 filter_type = f->mac_info.filter_type;
5532 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5533 filter_type == RTE_MACVLAN_HASH_MATCH) {
5534 if (vlan_num == 0) {
5535 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5536 return I40E_ERR_PARAM;
5538 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5539 filter_type == RTE_MAC_HASH_MATCH)
5542 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5544 PMD_DRV_LOG(ERR, "failed to allocate memory");
5545 return I40E_ERR_NO_MEMORY;
5548 for (i = 0; i < vlan_num; i++) {
5549 mv_f[i].filter_type = filter_type;
5550 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5553 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5554 filter_type == RTE_MACVLAN_HASH_MATCH) {
5555 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5556 if (ret != I40E_SUCCESS)
5560 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5561 if (ret != I40E_SUCCESS)
5564 /* Remove the mac addr into mac list */
5565 TAILQ_REMOVE(&vsi->mac_list, f, next);
5575 /* Configure hash enable flags for RSS */
5577 i40e_config_hena(uint64_t flags)
5584 if (flags & ETH_RSS_FRAG_IPV4)
5585 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5586 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5587 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5588 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5589 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5590 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5591 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5592 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5593 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5594 if (flags & ETH_RSS_FRAG_IPV6)
5595 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5596 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5597 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5598 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5599 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5600 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5601 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5602 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5603 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5604 if (flags & ETH_RSS_L2_PAYLOAD)
5605 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5610 /* Parse the hash enable flags */
5612 i40e_parse_hena(uint64_t flags)
5614 uint64_t rss_hf = 0;
5618 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5619 rss_hf |= ETH_RSS_FRAG_IPV4;
5620 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5621 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5622 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5623 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5624 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5625 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5626 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5627 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5628 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5629 rss_hf |= ETH_RSS_FRAG_IPV6;
5630 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5631 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5632 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5633 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5634 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5635 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5636 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5637 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5638 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5639 rss_hf |= ETH_RSS_L2_PAYLOAD;
5646 i40e_pf_disable_rss(struct i40e_pf *pf)
5648 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5651 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5652 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5653 hena &= ~I40E_RSS_HENA_ALL;
5654 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5655 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5656 I40E_WRITE_FLUSH(hw);
5660 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5662 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5663 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5666 if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5670 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5671 struct i40e_aqc_get_set_rss_key_data *key_dw =
5672 (struct i40e_aqc_get_set_rss_key_data *)key;
5674 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5676 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5679 uint32_t *hash_key = (uint32_t *)key;
5682 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5683 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5684 I40E_WRITE_FLUSH(hw);
5691 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5693 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5694 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5697 if (!key || !key_len)
5700 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5701 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5702 (struct i40e_aqc_get_set_rss_key_data *)key);
5704 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5708 uint32_t *key_dw = (uint32_t *)key;
5711 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5712 key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5714 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5720 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5722 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5727 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5728 rss_conf->rss_key_len);
5732 rss_hf = rss_conf->rss_hf;
5733 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5734 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5735 hena &= ~I40E_RSS_HENA_ALL;
5736 hena |= i40e_config_hena(rss_hf);
5737 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5738 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5739 I40E_WRITE_FLUSH(hw);
5745 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5746 struct rte_eth_rss_conf *rss_conf)
5748 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5753 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5754 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5755 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5756 if (rss_hf != 0) /* Enable RSS */
5758 return 0; /* Nothing to do */
5761 if (rss_hf == 0) /* Disable RSS */
5764 return i40e_hw_rss_hash_set(pf, rss_conf);
5768 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5769 struct rte_eth_rss_conf *rss_conf)
5771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5775 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5776 &rss_conf->rss_key_len);
5778 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5779 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5780 rss_conf->rss_hf = i40e_parse_hena(hena);
5786 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5788 switch (filter_type) {
5789 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5790 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5792 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5793 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5795 case RTE_TUNNEL_FILTER_IMAC_TENID:
5796 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5798 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5799 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5801 case ETH_TUNNEL_FILTER_IMAC:
5802 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5805 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5813 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5814 struct rte_eth_tunnel_filter_conf *tunnel_filter,
5818 uint8_t tun_type = 0;
5820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5821 struct i40e_vsi *vsi = pf->main_vsi;
5822 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
5823 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
5825 cld_filter = rte_zmalloc("tunnel_filter",
5826 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5829 if (NULL == cld_filter) {
5830 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5833 pfilter = cld_filter;
5835 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5836 sizeof(struct ether_addr));
5837 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5838 sizeof(struct ether_addr));
5840 pfilter->inner_vlan = tunnel_filter->inner_vlan;
5841 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5842 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5843 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5844 &tunnel_filter->ip_addr,
5845 sizeof(pfilter->ipaddr.v4.data));
5847 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5848 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5849 &tunnel_filter->ip_addr,
5850 sizeof(pfilter->ipaddr.v6.data));
5853 /* check tunneled type */
5854 switch (tunnel_filter->tunnel_type) {
5855 case RTE_TUNNEL_TYPE_VXLAN:
5856 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5858 case RTE_TUNNEL_TYPE_NVGRE:
5859 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5862 /* Other tunnel types is not supported. */
5863 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5864 rte_free(cld_filter);
5868 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5871 rte_free(cld_filter);
5875 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5876 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5877 pfilter->tenant_id = tunnel_filter->tenant_id;
5878 pfilter->queue_number = tunnel_filter->queue_id;
5881 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5883 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5886 rte_free(cld_filter);
5891 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5895 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5896 if (pf->vxlan_ports[i] == port)
5904 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5908 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5910 idx = i40e_get_vxlan_port_idx(pf, port);
5912 /* Check if port already exists */
5914 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5918 /* Now check if there is space to add the new port */
5919 idx = i40e_get_vxlan_port_idx(pf, 0);
5921 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5922 "not adding port %d", port);
5926 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5929 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5933 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5936 /* New port: add it and mark its index in the bitmap */
5937 pf->vxlan_ports[idx] = port;
5938 pf->vxlan_bitmap |= (1 << idx);
5940 if (!(pf->flags & I40E_FLAG_VXLAN))
5941 pf->flags |= I40E_FLAG_VXLAN;
5947 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5950 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5952 if (!(pf->flags & I40E_FLAG_VXLAN)) {
5953 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5957 idx = i40e_get_vxlan_port_idx(pf, port);
5960 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5964 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5965 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5969 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5972 pf->vxlan_ports[idx] = 0;
5973 pf->vxlan_bitmap &= ~(1 << idx);
5975 if (!pf->vxlan_bitmap)
5976 pf->flags &= ~I40E_FLAG_VXLAN;
5981 /* Add UDP tunneling port */
5983 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5984 struct rte_eth_udp_tunnel *udp_tunnel)
5987 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5989 if (udp_tunnel == NULL)
5992 switch (udp_tunnel->prot_type) {
5993 case RTE_TUNNEL_TYPE_VXLAN:
5994 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5997 case RTE_TUNNEL_TYPE_GENEVE:
5998 case RTE_TUNNEL_TYPE_TEREDO:
5999 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6004 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6012 /* Remove UDP tunneling port */
6014 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6015 struct rte_eth_udp_tunnel *udp_tunnel)
6018 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6020 if (udp_tunnel == NULL)
6023 switch (udp_tunnel->prot_type) {
6024 case RTE_TUNNEL_TYPE_VXLAN:
6025 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6027 case RTE_TUNNEL_TYPE_GENEVE:
6028 case RTE_TUNNEL_TYPE_TEREDO:
6029 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6033 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6041 /* Calculate the maximum number of contiguous PF queues that are configured */
6043 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6045 struct rte_eth_dev_data *data = pf->dev_data;
6047 struct i40e_rx_queue *rxq;
6050 for (i = 0; i < pf->lan_nb_qps; i++) {
6051 rxq = data->rx_queues[i];
6052 if (rxq && rxq->q_set)
6063 i40e_pf_config_rss(struct i40e_pf *pf)
6065 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6066 struct rte_eth_rss_conf rss_conf;
6067 uint32_t i, lut = 0;
6071 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6072 * It's necessary to calulate the actual PF queues that are configured.
6074 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6075 num = i40e_pf_calc_configured_queues_num(pf);
6077 num = pf->dev_data->nb_rx_queues;
6079 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6080 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6084 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6088 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6091 lut = (lut << 8) | (j & ((0x1 <<
6092 hw->func_caps.rss_table_entry_width) - 1));
6094 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6097 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6098 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6099 i40e_pf_disable_rss(pf);
6102 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6103 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6104 /* Random default keys */
6105 static uint32_t rss_key_default[] = {0x6b793944,
6106 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6107 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6108 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6110 rss_conf.rss_key = (uint8_t *)rss_key_default;
6111 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6115 return i40e_hw_rss_hash_set(pf, &rss_conf);
6119 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6120 struct rte_eth_tunnel_filter_conf *filter)
6122 if (pf == NULL || filter == NULL) {
6123 PMD_DRV_LOG(ERR, "Invalid parameter");
6127 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6128 PMD_DRV_LOG(ERR, "Invalid queue ID");
6132 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6133 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6137 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6138 (is_zero_ether_addr(filter->outer_mac))) {
6139 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6143 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6144 (is_zero_ether_addr(filter->inner_mac))) {
6145 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6152 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6153 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6155 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6160 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6161 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6164 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6165 } else if (len == 4) {
6166 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6168 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6173 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6180 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6181 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6187 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6194 switch (cfg->cfg_type) {
6195 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6196 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6199 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6207 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6208 enum rte_filter_op filter_op,
6211 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212 int ret = I40E_ERR_PARAM;
6214 switch (filter_op) {
6215 case RTE_ETH_FILTER_SET:
6216 ret = i40e_dev_global_config_set(hw,
6217 (struct rte_eth_global_cfg *)arg);
6220 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6228 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6229 enum rte_filter_op filter_op,
6232 struct rte_eth_tunnel_filter_conf *filter;
6233 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6234 int ret = I40E_SUCCESS;
6236 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6238 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6239 return I40E_ERR_PARAM;
6241 switch (filter_op) {
6242 case RTE_ETH_FILTER_NOP:
6243 if (!(pf->flags & I40E_FLAG_VXLAN))
6244 ret = I40E_NOT_SUPPORTED;
6246 case RTE_ETH_FILTER_ADD:
6247 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6249 case RTE_ETH_FILTER_DELETE:
6250 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6253 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6254 ret = I40E_ERR_PARAM;
6262 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6265 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6268 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6269 ret = i40e_pf_config_rss(pf);
6271 i40e_pf_disable_rss(pf);
6276 /* Get the symmetric hash enable configurations per port */
6278 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6280 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6282 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6285 /* Set the symmetric hash enable configurations per port */
6287 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6289 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6292 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6293 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6297 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6299 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6300 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6304 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6306 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6307 I40E_WRITE_FLUSH(hw);
6311 * Get global configurations of hash function type and symmetric hash enable
6312 * per flow type (pctype). Note that global configuration means it affects all
6313 * the ports on the same NIC.
6316 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6317 struct rte_eth_hash_global_conf *g_cfg)
6319 uint32_t reg, mask = I40E_FLOW_TYPES;
6321 enum i40e_filter_pctype pctype;
6323 memset(g_cfg, 0, sizeof(*g_cfg));
6324 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6325 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6326 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6328 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6329 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6330 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6332 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6333 if (!(mask & (1UL << i)))
6335 mask &= ~(1UL << i);
6336 /* Bit set indicats the coresponding flow type is supported */
6337 g_cfg->valid_bit_mask[0] |= (1UL << i);
6338 pctype = i40e_flowtype_to_pctype(i);
6339 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6340 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6341 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6348 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6351 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6353 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6354 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6355 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6356 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6362 * As i40e supports less than 32 flow types, only first 32 bits need to
6365 mask0 = g_cfg->valid_bit_mask[0];
6366 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6368 /* Check if any unsupported flow type configured */
6369 if ((mask0 | i40e_mask) ^ i40e_mask)
6372 if (g_cfg->valid_bit_mask[i])
6380 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6386 * Set global configurations of hash function type and symmetric hash enable
6387 * per flow type (pctype). Note any modifying global configuration will affect
6388 * all the ports on the same NIC.
6391 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6392 struct rte_eth_hash_global_conf *g_cfg)
6397 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6398 enum i40e_filter_pctype pctype;
6400 /* Check the input parameters */
6401 ret = i40e_hash_global_config_check(g_cfg);
6405 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6406 if (!(mask0 & (1UL << i)))
6408 mask0 &= ~(1UL << i);
6409 pctype = i40e_flowtype_to_pctype(i);
6410 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6411 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6412 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6415 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6416 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6418 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6419 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6423 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6424 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6426 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6427 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6431 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6433 /* Use the default, and keep it as it is */
6436 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6439 I40E_WRITE_FLUSH(hw);
6445 * Valid input sets for hash and flow director filters per PCTYPE
6448 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6449 enum rte_filter_type filter)
6453 static const uint64_t valid_hash_inset_table[] = {
6454 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6455 I40E_INSET_DMAC | I40E_INSET_SMAC |
6456 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6457 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6458 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6459 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6460 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6461 I40E_INSET_FLEX_PAYLOAD,
6462 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6463 I40E_INSET_DMAC | I40E_INSET_SMAC |
6464 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6465 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6466 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6467 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6468 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6469 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6470 I40E_INSET_FLEX_PAYLOAD,
6471 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6472 I40E_INSET_DMAC | I40E_INSET_SMAC |
6473 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6474 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6475 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6476 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6477 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6478 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6479 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6480 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6481 I40E_INSET_DMAC | I40E_INSET_SMAC |
6482 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6483 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6484 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6485 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6486 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6487 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6488 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6489 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6490 I40E_INSET_DMAC | I40E_INSET_SMAC |
6491 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6492 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6493 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6494 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6495 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6496 I40E_INSET_FLEX_PAYLOAD,
6497 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6498 I40E_INSET_DMAC | I40E_INSET_SMAC |
6499 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6500 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6501 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6502 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6503 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6504 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6505 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6506 I40E_INSET_DMAC | I40E_INSET_SMAC |
6507 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6508 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6509 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6510 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6511 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6512 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6513 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6514 I40E_INSET_DMAC | I40E_INSET_SMAC |
6515 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6516 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6517 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6518 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6519 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6520 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6521 I40E_INSET_FLEX_PAYLOAD,
6522 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6523 I40E_INSET_DMAC | I40E_INSET_SMAC |
6524 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6525 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6526 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6527 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6528 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6529 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6530 I40E_INSET_FLEX_PAYLOAD,
6531 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6532 I40E_INSET_DMAC | I40E_INSET_SMAC |
6533 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6534 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6535 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6536 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6537 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6538 I40E_INSET_FLEX_PAYLOAD,
6539 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6540 I40E_INSET_DMAC | I40E_INSET_SMAC |
6541 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6542 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6543 I40E_INSET_FLEX_PAYLOAD,
6547 * Flow director supports only fields defined in
6548 * union rte_eth_fdir_flow.
6550 static const uint64_t valid_fdir_inset_table[] = {
6551 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6552 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6553 I40E_INSET_FLEX_PAYLOAD,
6554 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6555 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6556 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6557 I40E_INSET_FLEX_PAYLOAD,
6558 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6559 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6560 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6561 I40E_INSET_FLEX_PAYLOAD,
6562 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6563 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6564 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6565 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6566 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6567 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6568 I40E_INSET_FLEX_PAYLOAD,
6569 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6570 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6571 I40E_INSET_FLEX_PAYLOAD,
6572 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6573 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6574 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6575 I40E_INSET_FLEX_PAYLOAD,
6576 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6577 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6578 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6579 I40E_INSET_FLEX_PAYLOAD,
6580 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6581 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6582 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6583 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6584 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6585 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6586 I40E_INSET_FLEX_PAYLOAD,
6587 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6588 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6591 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6593 if (filter == RTE_ETH_FILTER_HASH)
6594 valid = valid_hash_inset_table[pctype];
6596 valid = valid_fdir_inset_table[pctype];
6602 * Validate if the input set is allowed for a specific PCTYPE
6605 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6606 enum rte_filter_type filter, uint64_t inset)
6610 valid = i40e_get_valid_input_set(pctype, filter);
6611 if (inset & (~valid))
6617 /* default input set fields combination per pctype */
6619 i40e_get_default_input_set(uint16_t pctype)
6621 static const uint64_t default_inset_table[] = {
6622 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6623 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6624 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6625 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6626 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6627 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6628 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6629 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6630 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6631 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6632 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6634 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6635 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6636 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6637 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6638 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6639 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6640 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6641 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6642 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6643 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6644 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6645 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6646 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6648 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6649 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6650 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6651 I40E_INSET_LAST_ETHER_TYPE,
6654 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6657 return default_inset_table[pctype];
6661 * Parse the input set from index to logical bit masks
6664 i40e_parse_input_set(uint64_t *inset,
6665 enum i40e_filter_pctype pctype,
6666 enum rte_eth_input_set_field *field,
6672 static const struct {
6673 enum rte_eth_input_set_field field;
6675 } inset_convert_table[] = {
6676 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6677 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6678 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6679 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6680 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6681 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6682 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6683 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6684 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6685 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6686 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6687 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6688 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6689 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6690 I40E_INSET_IPV6_NEXT_HDR},
6691 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6692 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6693 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6694 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6695 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6696 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6697 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6698 I40E_INSET_SCTP_VT},
6699 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6700 I40E_INSET_TUNNEL_DMAC},
6701 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6702 I40E_INSET_VLAN_TUNNEL},
6703 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6704 I40E_INSET_TUNNEL_ID},
6705 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6706 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6707 I40E_INSET_FLEX_PAYLOAD_W1},
6708 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6709 I40E_INSET_FLEX_PAYLOAD_W2},
6710 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6711 I40E_INSET_FLEX_PAYLOAD_W3},
6712 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6713 I40E_INSET_FLEX_PAYLOAD_W4},
6714 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6715 I40E_INSET_FLEX_PAYLOAD_W5},
6716 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6717 I40E_INSET_FLEX_PAYLOAD_W6},
6718 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6719 I40E_INSET_FLEX_PAYLOAD_W7},
6720 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6721 I40E_INSET_FLEX_PAYLOAD_W8},
6724 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6727 /* Only one item allowed for default or all */
6729 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6730 *inset = i40e_get_default_input_set(pctype);
6732 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6733 *inset = I40E_INSET_NONE;
6738 for (i = 0, *inset = 0; i < size; i++) {
6739 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6740 if (field[i] == inset_convert_table[j].field) {
6741 *inset |= inset_convert_table[j].inset;
6746 /* It contains unsupported input set, return immediately */
6747 if (j == RTE_DIM(inset_convert_table))
6755 * Translate the input set from bit masks to register aware bit masks
6759 i40e_translate_input_set_reg(uint64_t input)
6764 static const struct {
6768 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6769 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6770 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6771 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6772 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6773 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6774 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6775 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6776 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6777 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6778 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6779 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6780 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6781 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6782 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6783 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6784 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6785 {I40E_INSET_TUNNEL_DMAC,
6786 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6787 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6788 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6789 {I40E_INSET_TUNNEL_SRC_PORT,
6790 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6791 {I40E_INSET_TUNNEL_DST_PORT,
6792 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6793 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6794 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6795 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6796 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6797 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6798 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6799 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6800 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6801 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6807 /* Translate input set to register aware inset */
6808 for (i = 0; i < RTE_DIM(inset_map); i++) {
6809 if (input & inset_map[i].inset)
6810 val |= inset_map[i].inset_reg;
6817 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6821 static const struct {
6824 } inset_mask_map[] = {
6825 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6826 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6827 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6828 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6831 if (!inset || !mask || !nb_elem)
6834 if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6835 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6837 return I40E_INSET_MASK_NUM_REG;
6840 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6843 if (inset & inset_mask_map[i].inset) {
6844 mask[idx] = inset_mask_map[i].mask;
6853 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6854 enum i40e_filter_pctype pctype)
6858 if (filter == RTE_ETH_FILTER_HASH) {
6859 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6860 reg <<= I40E_32_BIT_WIDTH;
6861 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6862 } else if (filter == RTE_ETH_FILTER_FDIR) {
6863 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6864 reg <<= I40E_32_BIT_WIDTH;
6865 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6872 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6874 uint32_t reg = I40E_READ_REG(hw, addr);
6876 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6878 I40E_WRITE_REG(hw, addr, val);
6879 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6880 (uint32_t)I40E_READ_REG(hw, addr));
6884 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6885 enum i40e_filter_pctype pctype,
6886 enum rte_filter_input_set_op op,
6893 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6896 if (op == RTE_ETH_INPUT_SET_SELECT) {
6897 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6898 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6902 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6905 } else if (op == RTE_ETH_INPUT_SET_ADD) {
6906 uint8_t j, count = 0;
6908 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6909 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6910 if (reg & I40E_GLQF_HASH_MSK_FIELD)
6913 if (count + num > I40E_INSET_MASK_NUM_REG)
6916 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6917 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6925 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6926 enum i40e_filter_pctype pctype,
6927 enum rte_filter_input_set_op op,
6934 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6937 if (op == RTE_ETH_INPUT_SET_SELECT) {
6938 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6939 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6943 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6946 } else if (op == RTE_ETH_INPUT_SET_ADD) {
6947 uint8_t j, count = 0;
6949 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6950 reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6951 if (reg & I40E_GLQF_FD_MSK_FIELD)
6954 if (count + num > I40E_INSET_MASK_NUM_REG)
6957 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6958 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6966 i40e_filter_inset_select(struct i40e_hw *hw,
6967 struct rte_eth_input_set_conf *conf,
6968 enum rte_filter_type filter)
6970 enum i40e_filter_pctype pctype;
6971 uint64_t inset_reg = 0, input_set;
6972 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6977 PMD_DRV_LOG(ERR, "Invalid pointer");
6981 pctype = i40e_flowtype_to_pctype(conf->flow_type);
6982 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6983 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6987 if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6988 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6992 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6995 PMD_DRV_LOG(ERR, "Failed to parse input set");
6998 if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6999 PMD_DRV_LOG(ERR, "Invalid input set");
7003 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7004 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7005 } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7006 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7009 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7010 I40E_INSET_MASK_NUM_REG);
7011 inset_reg |= i40e_translate_input_set_reg(input_set);
7013 if (filter == RTE_ETH_FILTER_HASH) {
7014 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7019 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7020 (uint32_t)(inset_reg & UINT32_MAX));
7021 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7022 (uint32_t)((inset_reg >>
7023 I40E_32_BIT_WIDTH) & UINT32_MAX));
7024 } else if (filter == RTE_ETH_FILTER_FDIR) {
7025 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7030 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7031 (uint32_t)(inset_reg & UINT32_MAX));
7032 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7033 (uint32_t)((inset_reg >>
7034 I40E_32_BIT_WIDTH) & UINT32_MAX));
7036 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7039 I40E_WRITE_FLUSH(hw);
7045 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7050 PMD_DRV_LOG(ERR, "Invalid pointer");
7054 switch (info->info_type) {
7055 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7056 i40e_get_symmetric_hash_enable_per_port(hw,
7057 &(info->info.enable));
7059 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7060 ret = i40e_get_hash_filter_global_config(hw,
7061 &(info->info.global_conf));
7064 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7074 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7079 PMD_DRV_LOG(ERR, "Invalid pointer");
7083 switch (info->info_type) {
7084 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7085 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7087 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7088 ret = i40e_set_hash_filter_global_config(hw,
7089 &(info->info.global_conf));
7091 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7092 ret = i40e_filter_inset_select(hw,
7093 &(info->info.input_set_conf),
7094 RTE_ETH_FILTER_HASH);
7098 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7107 /* Operations for hash function */
7109 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7110 enum rte_filter_op filter_op,
7113 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116 switch (filter_op) {
7117 case RTE_ETH_FILTER_NOP:
7119 case RTE_ETH_FILTER_GET:
7120 ret = i40e_hash_filter_get(hw,
7121 (struct rte_eth_hash_filter_info *)arg);
7123 case RTE_ETH_FILTER_SET:
7124 ret = i40e_hash_filter_set(hw,
7125 (struct rte_eth_hash_filter_info *)arg);
7128 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7138 * Configure ethertype filter, which can director packet by filtering
7139 * with mac address and ether_type or only ether_type
7142 i40e_ethertype_filter_set(struct i40e_pf *pf,
7143 struct rte_eth_ethertype_filter *filter,
7146 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7147 struct i40e_control_filter_stats stats;
7151 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7152 PMD_DRV_LOG(ERR, "Invalid queue ID");
7155 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7156 filter->ether_type == ETHER_TYPE_IPv6) {
7157 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7158 " control packet filter.", filter->ether_type);
7161 if (filter->ether_type == ETHER_TYPE_VLAN)
7162 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7165 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7166 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7167 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7168 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7169 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7171 memset(&stats, 0, sizeof(stats));
7172 ret = i40e_aq_add_rem_control_packet_filter(hw,
7173 filter->mac_addr.addr_bytes,
7174 filter->ether_type, flags,
7176 filter->queue, add, &stats, NULL);
7178 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7179 " mac_etype_used = %u, etype_used = %u,"
7180 " mac_etype_free = %u, etype_free = %u\n",
7181 ret, stats.mac_etype_used, stats.etype_used,
7182 stats.mac_etype_free, stats.etype_free);
7189 * Handle operations for ethertype filter.
7192 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7193 enum rte_filter_op filter_op,
7196 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7199 if (filter_op == RTE_ETH_FILTER_NOP)
7203 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7208 switch (filter_op) {
7209 case RTE_ETH_FILTER_ADD:
7210 ret = i40e_ethertype_filter_set(pf,
7211 (struct rte_eth_ethertype_filter *)arg,
7214 case RTE_ETH_FILTER_DELETE:
7215 ret = i40e_ethertype_filter_set(pf,
7216 (struct rte_eth_ethertype_filter *)arg,
7220 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7228 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7229 enum rte_filter_type filter_type,
7230 enum rte_filter_op filter_op,
7238 switch (filter_type) {
7239 case RTE_ETH_FILTER_NONE:
7240 /* For global configuration */
7241 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7243 case RTE_ETH_FILTER_HASH:
7244 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7246 case RTE_ETH_FILTER_MACVLAN:
7247 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7249 case RTE_ETH_FILTER_ETHERTYPE:
7250 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7252 case RTE_ETH_FILTER_TUNNEL:
7253 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7255 case RTE_ETH_FILTER_FDIR:
7256 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7259 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7269 * As some registers wouldn't be reset unless a global hardware reset,
7270 * hardware initialization is needed to put those registers into an
7271 * expected initial state.
7274 i40e_hw_init(struct i40e_hw *hw)
7276 /* clear the PF Queue Filter control register */
7277 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7279 /* Disable symmetric hash per port */
7280 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7283 enum i40e_filter_pctype
7284 i40e_flowtype_to_pctype(uint16_t flow_type)
7286 static const enum i40e_filter_pctype pctype_table[] = {
7287 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7288 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7289 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7290 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7291 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7292 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7293 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7294 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7295 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7296 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7297 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7298 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7299 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7300 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7301 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7302 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7303 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7304 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7305 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7308 return pctype_table[flow_type];
7312 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7314 static const uint16_t flowtype_table[] = {
7315 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7316 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7317 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7318 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7319 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7320 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7321 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7322 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7323 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7324 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7325 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7326 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7327 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7328 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7329 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7330 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7331 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7332 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7333 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7336 return flowtype_table[pctype];
7340 * On X710, performance number is far from the expectation on recent firmware
7341 * versions; on XL710, performance number is also far from the expectation on
7342 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7343 * mode is enabled and port MAC address is equal to the packet destination MAC
7344 * address. The fix for this issue may not be integrated in the following
7345 * firmware version. So the workaround in software driver is needed. It needs
7346 * to modify the initial values of 3 internal only registers for both X710 and
7347 * XL710. Note that the values for X710 or XL710 could be different, and the
7348 * workaround can be removed when it is fixed in firmware in the future.
7351 /* For both X710 and XL710 */
7352 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7353 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7355 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7356 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7359 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7361 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7362 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7365 i40e_configure_registers(struct i40e_hw *hw)
7371 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7372 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7373 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7379 for (i = 0; i < RTE_DIM(reg_table); i++) {
7380 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7381 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7383 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7386 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7389 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7392 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7396 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7397 reg_table[i].addr, reg);
7398 if (reg == reg_table[i].val)
7401 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7402 reg_table[i].val, NULL);
7404 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7405 "address of 0x%"PRIx32, reg_table[i].val,
7409 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7410 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7414 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7415 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7416 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7417 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7419 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7424 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7425 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7429 /* Configure for double VLAN RX stripping */
7430 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7431 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7432 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7433 ret = i40e_aq_debug_write_register(hw,
7434 I40E_VSI_TSR(vsi->vsi_id),
7437 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7439 return I40E_ERR_CONFIG;
7443 /* Configure for double VLAN TX insertion */
7444 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7445 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7446 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7447 ret = i40e_aq_debug_write_register(hw,
7448 I40E_VSI_L2TAGSTXVALID(
7449 vsi->vsi_id), reg, NULL);
7451 PMD_DRV_LOG(ERR, "Failed to update "
7452 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7453 return I40E_ERR_CONFIG;
7461 * i40e_aq_add_mirror_rule
7462 * @hw: pointer to the hardware structure
7463 * @seid: VEB seid to add mirror rule to
7464 * @dst_id: destination vsi seid
7465 * @entries: Buffer which contains the entities to be mirrored
7466 * @count: number of entities contained in the buffer
7467 * @rule_id:the rule_id of the rule to be added
7469 * Add a mirror rule for a given veb.
7472 static enum i40e_status_code
7473 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7474 uint16_t seid, uint16_t dst_id,
7475 uint16_t rule_type, uint16_t *entries,
7476 uint16_t count, uint16_t *rule_id)
7478 struct i40e_aq_desc desc;
7479 struct i40e_aqc_add_delete_mirror_rule cmd;
7480 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7481 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7484 enum i40e_status_code status;
7486 i40e_fill_default_direct_cmd_desc(&desc,
7487 i40e_aqc_opc_add_mirror_rule);
7488 memset(&cmd, 0, sizeof(cmd));
7490 buff_len = sizeof(uint16_t) * count;
7491 desc.datalen = rte_cpu_to_le_16(buff_len);
7493 desc.flags |= rte_cpu_to_le_16(
7494 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7495 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7496 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7497 cmd.num_entries = rte_cpu_to_le_16(count);
7498 cmd.seid = rte_cpu_to_le_16(seid);
7499 cmd.destination = rte_cpu_to_le_16(dst_id);
7501 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7502 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7503 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7505 " mirror_rules_used = %u, mirror_rules_free = %u,",
7506 hw->aq.asq_last_status, resp->rule_id,
7507 resp->mirror_rules_used, resp->mirror_rules_free);
7508 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7514 * i40e_aq_del_mirror_rule
7515 * @hw: pointer to the hardware structure
7516 * @seid: VEB seid to add mirror rule to
7517 * @entries: Buffer which contains the entities to be mirrored
7518 * @count: number of entities contained in the buffer
7519 * @rule_id:the rule_id of the rule to be delete
7521 * Delete a mirror rule for a given veb.
7524 static enum i40e_status_code
7525 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7526 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7527 uint16_t count, uint16_t rule_id)
7529 struct i40e_aq_desc desc;
7530 struct i40e_aqc_add_delete_mirror_rule cmd;
7531 uint16_t buff_len = 0;
7532 enum i40e_status_code status;
7535 i40e_fill_default_direct_cmd_desc(&desc,
7536 i40e_aqc_opc_delete_mirror_rule);
7537 memset(&cmd, 0, sizeof(cmd));
7538 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7539 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7541 cmd.num_entries = count;
7542 buff_len = sizeof(uint16_t) * count;
7543 desc.datalen = rte_cpu_to_le_16(buff_len);
7544 buff = (void *)entries;
7546 /* rule id is filled in destination field for deleting mirror rule */
7547 cmd.destination = rte_cpu_to_le_16(rule_id);
7549 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7550 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7551 cmd.seid = rte_cpu_to_le_16(seid);
7553 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7554 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7560 * i40e_mirror_rule_set
7561 * @dev: pointer to the hardware structure
7562 * @mirror_conf: mirror rule info
7563 * @sw_id: mirror rule's sw_id
7564 * @on: enable/disable
7566 * set a mirror rule.
7570 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7571 struct rte_eth_mirror_conf *mirror_conf,
7572 uint8_t sw_id, uint8_t on)
7574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7575 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7576 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7577 struct i40e_mirror_rule *parent = NULL;
7578 uint16_t seid, dst_seid, rule_id;
7582 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7584 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7585 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7586 " without veb or vfs.");
7589 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7590 PMD_DRV_LOG(ERR, "mirror table is full.");
7593 if (mirror_conf->dst_pool > pf->vf_num) {
7594 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7595 mirror_conf->dst_pool);
7599 seid = pf->main_vsi->veb->seid;
7601 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7602 if (sw_id <= it->index) {
7608 if (mirr_rule && sw_id == mirr_rule->index) {
7610 PMD_DRV_LOG(ERR, "mirror rule exists.");
7613 ret = i40e_aq_del_mirror_rule(hw, seid,
7614 mirr_rule->rule_type,
7616 mirr_rule->num_entries, mirr_rule->id);
7618 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7619 " ret = %d, aq_err = %d.",
7620 ret, hw->aq.asq_last_status);
7623 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7624 rte_free(mirr_rule);
7625 pf->nb_mirror_rule--;
7629 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7633 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7634 sizeof(struct i40e_mirror_rule) , 0);
7636 PMD_DRV_LOG(ERR, "failed to allocate memory");
7637 return I40E_ERR_NO_MEMORY;
7639 switch (mirror_conf->rule_type) {
7640 case ETH_MIRROR_VLAN:
7641 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7642 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7643 mirr_rule->entries[j] =
7644 mirror_conf->vlan.vlan_id[i];
7649 PMD_DRV_LOG(ERR, "vlan is not specified.");
7650 rte_free(mirr_rule);
7653 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7655 case ETH_MIRROR_VIRTUAL_POOL_UP:
7656 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7657 /* check if the specified pool bit is out of range */
7658 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7659 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7660 rte_free(mirr_rule);
7663 for (i = 0, j = 0; i < pf->vf_num; i++) {
7664 if (mirror_conf->pool_mask & (1ULL << i)) {
7665 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7669 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7670 /* add pf vsi to entries */
7671 mirr_rule->entries[j] = pf->main_vsi_seid;
7675 PMD_DRV_LOG(ERR, "pool is not specified.");
7676 rte_free(mirr_rule);
7679 /* egress and ingress in aq commands means from switch but not port */
7680 mirr_rule->rule_type =
7681 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7682 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7683 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7685 case ETH_MIRROR_UPLINK_PORT:
7686 /* egress and ingress in aq commands means from switch but not port*/
7687 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7689 case ETH_MIRROR_DOWNLINK_PORT:
7690 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7693 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7694 mirror_conf->rule_type);
7695 rte_free(mirr_rule);
7699 /* If the dst_pool is equal to vf_num, consider it as PF */
7700 if (mirror_conf->dst_pool == pf->vf_num)
7701 dst_seid = pf->main_vsi_seid;
7703 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7705 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7706 mirr_rule->rule_type, mirr_rule->entries,
7709 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7710 " ret = %d, aq_err = %d.",
7711 ret, hw->aq.asq_last_status);
7712 rte_free(mirr_rule);
7716 mirr_rule->index = sw_id;
7717 mirr_rule->num_entries = j;
7718 mirr_rule->id = rule_id;
7719 mirr_rule->dst_vsi_seid = dst_seid;
7722 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7724 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7726 pf->nb_mirror_rule++;
7731 * i40e_mirror_rule_reset
7732 * @dev: pointer to the device
7733 * @sw_id: mirror rule's sw_id
7735 * reset a mirror rule.
7739 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7741 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7743 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7747 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7749 seid = pf->main_vsi->veb->seid;
7751 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7752 if (sw_id == it->index) {
7758 ret = i40e_aq_del_mirror_rule(hw, seid,
7759 mirr_rule->rule_type,
7761 mirr_rule->num_entries, mirr_rule->id);
7763 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7764 " status = %d, aq_err = %d.",
7765 ret, hw->aq.asq_last_status);
7768 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7769 rte_free(mirr_rule);
7770 pf->nb_mirror_rule--;
7772 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7779 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7782 uint64_t systim_cycles;
7784 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7785 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7788 return systim_cycles;
7792 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7794 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7797 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7798 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
7805 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7807 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7810 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7811 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
7818 i40e_start_timecounters(struct rte_eth_dev *dev)
7820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7821 struct i40e_adapter *adapter =
7822 (struct i40e_adapter *)dev->data->dev_private;
7823 struct rte_eth_link link;
7824 uint32_t tsync_inc_l;
7825 uint32_t tsync_inc_h;
7827 /* Get current link speed. */
7828 memset(&link, 0, sizeof(link));
7829 i40e_dev_link_update(dev, 1);
7830 rte_i40e_dev_atomic_read_link_status(dev, &link);
7832 switch (link.link_speed) {
7833 case ETH_LINK_SPEED_40G:
7834 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7835 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7837 case ETH_LINK_SPEED_10G:
7838 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7839 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7841 case ETH_LINK_SPEED_1000:
7842 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7843 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7850 /* Set the timesync increment value. */
7851 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7852 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7854 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7855 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7856 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7858 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7859 adapter->systime_tc.cc_shift = 0;
7860 adapter->systime_tc.nsec_mask = 0;
7862 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7863 adapter->rx_tstamp_tc.cc_shift = 0;
7864 adapter->rx_tstamp_tc.nsec_mask = 0;
7866 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7867 adapter->tx_tstamp_tc.cc_shift = 0;
7868 adapter->tx_tstamp_tc.nsec_mask = 0;
7872 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7874 struct i40e_adapter *adapter =
7875 (struct i40e_adapter *)dev->data->dev_private;
7877 adapter->systime_tc.nsec += delta;
7878 adapter->rx_tstamp_tc.nsec += delta;
7879 adapter->tx_tstamp_tc.nsec += delta;
7885 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7888 struct i40e_adapter *adapter =
7889 (struct i40e_adapter *)dev->data->dev_private;
7891 ns = rte_timespec_to_ns(ts);
7893 /* Set the timecounters to a new value. */
7894 adapter->systime_tc.nsec = ns;
7895 adapter->rx_tstamp_tc.nsec = ns;
7896 adapter->tx_tstamp_tc.nsec = ns;
7902 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7904 uint64_t ns, systime_cycles;
7905 struct i40e_adapter *adapter =
7906 (struct i40e_adapter *)dev->data->dev_private;
7908 systime_cycles = i40e_read_systime_cyclecounter(dev);
7909 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7910 *ts = rte_ns_to_timespec(ns);
7916 i40e_timesync_enable(struct rte_eth_dev *dev)
7918 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7919 uint32_t tsync_ctl_l;
7920 uint32_t tsync_ctl_h;
7922 /* Stop the timesync system time. */
7923 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7924 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7925 /* Reset the timesync system time value. */
7926 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
7927 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
7929 i40e_start_timecounters(dev);
7931 /* Clear timesync registers. */
7932 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7933 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7934 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
7935 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
7936 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
7937 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
7939 /* Enable timestamping of PTP packets. */
7940 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7941 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7943 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7944 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7945 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7947 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7948 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7954 i40e_timesync_disable(struct rte_eth_dev *dev)
7956 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7957 uint32_t tsync_ctl_l;
7958 uint32_t tsync_ctl_h;
7960 /* Disable timestamping of transmitted PTP packets. */
7961 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7962 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7964 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7965 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7967 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7968 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7970 /* Reset the timesync increment value. */
7971 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7972 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7978 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7979 struct timespec *timestamp, uint32_t flags)
7981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7982 struct i40e_adapter *adapter =
7983 (struct i40e_adapter *)dev->data->dev_private;
7985 uint32_t sync_status;
7986 uint32_t index = flags & 0x03;
7987 uint64_t rx_tstamp_cycles;
7990 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7991 if ((sync_status & (1 << index)) == 0)
7994 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
7995 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7996 *timestamp = rte_ns_to_timespec(ns);
8002 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8003 struct timespec *timestamp)
8005 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8006 struct i40e_adapter *adapter =
8007 (struct i40e_adapter *)dev->data->dev_private;
8009 uint32_t sync_status;
8010 uint64_t tx_tstamp_cycles;
8013 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8014 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8017 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8018 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8019 *timestamp = rte_ns_to_timespec(ns);
8025 * i40e_parse_dcb_configure - parse dcb configure from user
8026 * @dev: the device being configured
8027 * @dcb_cfg: pointer of the result of parse
8028 * @*tc_map: bit map of enabled traffic classes
8030 * Returns 0 on success, negative value on failure
8033 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8034 struct i40e_dcbx_config *dcb_cfg,
8037 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8038 uint8_t i, tc_bw, bw_lf;
8040 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8042 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8043 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8044 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8048 /* assume each tc has the same bw */
8049 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8050 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8051 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8052 /* to ensure the sum of tcbw is equal to 100 */
8053 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8054 for (i = 0; i < bw_lf; i++)
8055 dcb_cfg->etscfg.tcbwtable[i]++;
8057 /* assume each tc has the same Transmission Selection Algorithm */
8058 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8059 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8061 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8062 dcb_cfg->etscfg.prioritytable[i] =
8063 dcb_rx_conf->dcb_tc[i];
8065 /* FW needs one App to configure HW */
8066 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8067 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8068 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8069 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8071 if (dcb_rx_conf->nb_tcs == 0)
8072 *tc_map = 1; /* tc0 only */
8074 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8076 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8077 dcb_cfg->pfc.willing = 0;
8078 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8079 dcb_cfg->pfc.pfcenable = *tc_map;
8085 * i40e_vsi_get_bw_info - Query VSI BW Information
8086 * @vsi: the VSI being queried
8088 * Returns 0 on success, negative value on failure
8090 static enum i40e_status_code
8091 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
8093 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
8094 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
8095 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8096 enum i40e_status_code ret;
8100 /* Get the VSI level BW configuration */
8101 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
8104 "couldn't get PF vsi bw config, err %s aq_err %s\n",
8105 i40e_stat_str(hw, ret),
8106 i40e_aq_str(hw, hw->aq.asq_last_status));
8110 /* Get the VSI level BW configuration per TC */
8111 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
8115 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
8116 i40e_stat_str(hw, ret),
8117 i40e_aq_str(hw, hw->aq.asq_last_status));
8121 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
8122 PMD_INIT_LOG(WARNING,
8123 "Enabled TCs mismatch from querying VSI BW info"
8124 " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
8125 bw_ets_config.tc_valid_bits);
8126 /* Still continuing */
8129 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
8130 vsi->bw_info.bw_max_quanta = bw_config.max_bw;
8131 tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
8132 (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
8133 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8134 vsi->bw_info.bw_ets_share_credits[i] =
8135 bw_ets_config.share_credits[i];
8136 vsi->bw_info.bw_ets_limit_credits[i] =
8137 rte_le_to_cpu_16(bw_ets_config.credits[i]);
8138 /* 3 bits out of 4 for each TC */
8139 vsi->bw_info.bw_ets_max_quanta[i] =
8140 (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
8142 "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8143 __func__, vsi->seid, i, bw_config.qs_handles[i]);
8149 static enum i40e_status_code
8150 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8151 struct i40e_aqc_vsi_properties_data *info,
8152 uint8_t enabled_tcmap)
8154 enum i40e_status_code ret;
8155 int i, total_tc = 0;
8156 uint16_t qpnum_per_tc, bsf, qp_idx;
8157 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8159 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8160 if (ret != I40E_SUCCESS)
8163 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8164 if (enabled_tcmap & (1 << i))
8169 vsi->enabled_tc = enabled_tcmap;
8171 qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8172 /* Number of queues per enabled TC */
8173 if (qpnum_per_tc == 0) {
8174 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8175 return I40E_ERR_INVALID_QP_ID;
8177 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8179 bsf = rte_bsf32(qpnum_per_tc);
8182 * Configure TC and queue mapping parameters, for enabled TC,
8183 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8184 * default queue will serve it.
8187 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8188 if (vsi->enabled_tc & (1 << i)) {
8189 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8190 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8191 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8192 qp_idx += qpnum_per_tc;
8194 info->tc_mapping[i] = 0;
8197 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8198 if (vsi->type == I40E_VSI_SRIOV) {
8199 info->mapping_flags |=
8200 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8201 for (i = 0; i < vsi->nb_qps; i++)
8202 info->queue_mapping[i] =
8203 rte_cpu_to_le_16(vsi->base_queue + i);
8205 info->mapping_flags |=
8206 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8207 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8209 info->valid_sections |=
8210 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8212 return I40E_SUCCESS;
8216 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8217 * @vsi: VSI to be configured
8218 * @tc_map: enabled TC bitmap
8220 * Returns 0 on success, negative value on failure
8222 static enum i40e_status_code
8223 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8225 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8226 struct i40e_vsi_context ctxt;
8227 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8228 enum i40e_status_code ret = I40E_SUCCESS;
8231 /* Check if enabled_tc is same as existing or new TCs */
8232 if (vsi->enabled_tc == tc_map)
8235 /* configure tc bandwidth */
8236 memset(&bw_data, 0, sizeof(bw_data));
8237 bw_data.tc_valid_bits = tc_map;
8238 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8239 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8240 if (tc_map & BIT_ULL(i))
8241 bw_data.tc_bw_credits[i] = 1;
8243 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8245 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8246 " per TC failed = %d",
8247 hw->aq.asq_last_status);
8250 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8251 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8253 /* Update Queue Pairs Mapping for currently enabled UPs */
8254 ctxt.seid = vsi->seid;
8255 ctxt.pf_num = hw->pf_id;
8257 ctxt.uplink_seid = vsi->uplink_seid;
8258 ctxt.info = vsi->info;
8260 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8264 /* Update the VSI after updating the VSI queue-mapping information */
8265 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8267 PMD_INIT_LOG(ERR, "Failed to configure "
8268 "TC queue mapping = %d",
8269 hw->aq.asq_last_status);
8272 /* update the local VSI info with updated queue map */
8273 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8274 sizeof(vsi->info.tc_mapping));
8275 (void)rte_memcpy(&vsi->info.queue_mapping,
8276 &ctxt.info.queue_mapping,
8277 sizeof(vsi->info.queue_mapping));
8278 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8279 vsi->info.valid_sections = 0;
8281 /* Update current VSI BW information */
8282 ret = i40e_vsi_get_bw_info(vsi);
8285 "Failed updating vsi bw info, err %s aq_err %s",
8286 i40e_stat_str(hw, ret),
8287 i40e_aq_str(hw, hw->aq.asq_last_status));
8291 vsi->enabled_tc = tc_map;
8298 * i40e_dcb_hw_configure - program the dcb setting to hw
8299 * @pf: pf the configuration is taken on
8300 * @new_cfg: new configuration
8301 * @tc_map: enabled TC bitmap
8303 * Returns 0 on success, negative value on failure
8305 static enum i40e_status_code
8306 i40e_dcb_hw_configure(struct i40e_pf *pf,
8307 struct i40e_dcbx_config *new_cfg,
8310 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8311 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8312 struct i40e_vsi *main_vsi = pf->main_vsi;
8313 struct i40e_vsi_list *vsi_list;
8314 enum i40e_status_code ret;
8318 /* Use the FW API if FW > v4.4*/
8319 if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8320 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8321 " to configure DCB");
8322 return I40E_ERR_FIRMWARE_API_VERSION;
8325 /* Check if need reconfiguration */
8326 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8327 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8328 return I40E_SUCCESS;
8331 /* Copy the new config to the current config */
8332 *old_cfg = *new_cfg;
8333 old_cfg->etsrec = old_cfg->etscfg;
8334 ret = i40e_set_dcb_config(hw);
8337 "Set DCB Config failed, err %s aq_err %s\n",
8338 i40e_stat_str(hw, ret),
8339 i40e_aq_str(hw, hw->aq.asq_last_status));
8342 /* set receive Arbiter to RR mode and ETS scheme by default */
8343 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8344 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8345 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8346 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8347 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8348 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8349 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8350 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8351 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8352 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8353 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8354 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8355 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8357 /* get local mib to check whether it is configured correctly */
8359 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8360 /* Get Local DCB Config */
8361 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8362 &hw->local_dcbx_config);
8364 /* Update each VSI */
8365 i40e_vsi_config_tc(main_vsi, tc_map);
8366 if (main_vsi->veb) {
8367 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8368 /* Beside main VSI, only enable default
8371 ret = i40e_vsi_config_tc(vsi_list->vsi,
8372 I40E_DEFAULT_TCMAP);
8374 PMD_INIT_LOG(WARNING,
8375 "Failed configuring TC for VSI seid=%d\n",
8376 vsi_list->vsi->seid);
8380 return I40E_SUCCESS;
8384 * i40e_dcb_init_configure - initial dcb config
8385 * @dev: device being configured
8386 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8388 * Returns 0 on success, negative value on failure
8391 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8393 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8394 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8397 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8398 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8402 /* DCB initialization:
8403 * Update DCB configuration from the Firmware and configure
8404 * LLDP MIB change event.
8406 if (sw_dcb == TRUE) {
8407 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8408 if (ret != I40E_SUCCESS)
8409 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8411 ret = i40e_init_dcb(hw);
8412 /* if sw_dcb, lldp agent is stopped, the return from
8413 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8416 if (ret != I40E_SUCCESS &&
8417 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8418 memset(&hw->local_dcbx_config, 0,
8419 sizeof(struct i40e_dcbx_config));
8420 /* set dcb default configuration */
8421 hw->local_dcbx_config.etscfg.willing = 0;
8422 hw->local_dcbx_config.etscfg.maxtcs = 0;
8423 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8424 hw->local_dcbx_config.etscfg.tsatable[0] =
8426 hw->local_dcbx_config.etsrec =
8427 hw->local_dcbx_config.etscfg;
8428 hw->local_dcbx_config.pfc.willing = 0;
8429 hw->local_dcbx_config.pfc.pfccap =
8430 I40E_MAX_TRAFFIC_CLASS;
8431 /* FW needs one App to configure HW */
8432 hw->local_dcbx_config.numapps = 1;
8433 hw->local_dcbx_config.app[0].selector =
8434 I40E_APP_SEL_ETHTYPE;
8435 hw->local_dcbx_config.app[0].priority = 3;
8436 hw->local_dcbx_config.app[0].protocolid =
8437 I40E_APP_PROTOID_FCOE;
8438 ret = i40e_set_dcb_config(hw);
8440 PMD_INIT_LOG(ERR, "default dcb config fails."
8441 " err = %d, aq_err = %d.", ret,
8442 hw->aq.asq_last_status);
8446 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8447 " aq_err = %d.", ret,
8448 hw->aq.asq_last_status);
8452 ret = i40e_aq_start_lldp(hw, NULL);
8453 if (ret != I40E_SUCCESS)
8454 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8456 ret = i40e_init_dcb(hw);
8458 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8459 PMD_INIT_LOG(ERR, "HW doesn't support"
8464 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8465 " aq_err = %d.", ret,
8466 hw->aq.asq_last_status);
8474 * i40e_dcb_setup - setup dcb related config
8475 * @dev: device being configured
8477 * Returns 0 on success, negative value on failure
8480 i40e_dcb_setup(struct rte_eth_dev *dev)
8482 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8483 struct i40e_dcbx_config dcb_cfg;
8487 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8488 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8492 if (pf->vf_num != 0 ||
8493 (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8494 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8496 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8498 PMD_INIT_LOG(ERR, "invalid dcb config");
8501 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8503 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8511 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8512 struct rte_eth_dcb_info *dcb_info)
8514 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8516 struct i40e_vsi *vsi = pf->main_vsi;
8517 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8518 uint16_t bsf, tc_mapping;
8521 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8522 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8524 dcb_info->nb_tcs = 1;
8525 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8526 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8527 for (i = 0; i < dcb_info->nb_tcs; i++)
8528 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8530 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8531 if (vsi->enabled_tc & (1 << i)) {
8532 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8533 /* only main vsi support multi TCs */
8534 dcb_info->tc_queue.tc_rxq[0][i].base =
8535 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8536 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8537 dcb_info->tc_queue.tc_txq[0][i].base =
8538 dcb_info->tc_queue.tc_rxq[0][i].base;
8539 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8540 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8541 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8542 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8543 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8551 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8553 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8556 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8559 msix_intr = intr_handle->intr_vec[queue_id];
8560 if (msix_intr == I40E_MISC_VEC_ID)
8561 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8562 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8563 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8564 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8566 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8569 I40E_PFINT_DYN_CTLN(msix_intr -
8571 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8572 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8573 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8575 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8577 I40E_WRITE_FLUSH(hw);
8578 rte_intr_enable(&dev->pci_dev->intr_handle);
8584 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8586 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8587 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8590 msix_intr = intr_handle->intr_vec[queue_id];
8591 if (msix_intr == I40E_MISC_VEC_ID)
8592 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8595 I40E_PFINT_DYN_CTLN(msix_intr -
8598 I40E_WRITE_FLUSH(hw);