4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_adminq_cmd.h"
57 #include "base/i40e_type.h"
58 #include "base/i40e_register.h"
59 #include "i40e_ethdev.h"
60 #include "i40e_rxtx.h"
63 /* Maximun number of MAC addresses */
64 #define I40E_NUM_MACADDR_MAX 64
65 #define I40E_CLEAR_PXE_WAIT_MS 200
67 /* Maximun number of capability elements */
68 #define I40E_MAX_CAP_ELE_NUM 128
70 /* Wait count and inteval */
71 #define I40E_CHK_Q_ENA_COUNT 1000
72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
74 /* Maximun number of VSI */
75 #define I40E_MAX_NUM_VSIS (384UL)
77 /* Default queue interrupt throttling time in microseconds */
78 #define I40E_ITR_INDEX_DEFAULT 0
79 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
80 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
82 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
92 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
93 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
94 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
95 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
97 #define I40E_FLOW_TYPES ( \
98 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
103 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
108 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
116 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
117 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
118 static int i40e_dev_configure(struct rte_eth_dev *dev);
119 static int i40e_dev_start(struct rte_eth_dev *dev);
120 static void i40e_dev_stop(struct rte_eth_dev *dev);
121 static void i40e_dev_close(struct rte_eth_dev *dev);
122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
129 struct rte_eth_stats *stats);
130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
149 struct rte_eth_fc_conf *fc_conf);
150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
151 struct rte_eth_pfc_conf *pfc_conf);
152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
153 struct ether_addr *mac_addr,
156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
158 struct rte_eth_rss_reta_entry64 *reta_conf,
160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
161 struct rte_eth_rss_reta_entry64 *reta_conf,
164 static int i40e_get_cap(struct i40e_hw *hw);
165 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
166 static int i40e_pf_setup(struct i40e_pf *pf);
167 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
168 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
169 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
170 bool offset_loaded, uint64_t *offset, uint64_t *stat);
171 static void i40e_stat_update_48(struct i40e_hw *hw,
177 static void i40e_pf_config_irq0(struct i40e_hw *hw);
178 static void i40e_dev_interrupt_handler(
179 __rte_unused struct rte_intr_handle *handle, void *param);
180 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
181 uint32_t base, uint32_t num);
182 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
183 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
185 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
187 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
188 static int i40e_veb_release(struct i40e_veb *veb);
189 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
190 struct i40e_vsi *vsi);
191 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
192 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
194 struct i40e_macvlan_filter *mv_f,
196 struct ether_addr *addr);
197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
198 struct i40e_macvlan_filter *mv_f,
201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
203 struct rte_eth_rss_conf *rss_conf);
204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
205 struct rte_eth_rss_conf *rss_conf);
206 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
207 struct rte_eth_udp_tunnel *udp_tunnel);
208 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
209 struct rte_eth_udp_tunnel *udp_tunnel);
210 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
211 struct rte_eth_ethertype_filter *filter,
213 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
214 enum rte_filter_op filter_op,
216 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
217 enum rte_filter_type filter_type,
218 enum rte_filter_op filter_op,
220 static void i40e_configure_registers(struct i40e_hw *hw);
221 static void i40e_hw_init(struct i40e_hw *hw);
222 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
223 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
224 struct rte_eth_mirror_conf *mirror_conf,
225 uint8_t sw_id, uint8_t on);
226 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
228 static int i40e_timesync_enable(struct rte_eth_dev *dev);
229 static int i40e_timesync_disable(struct rte_eth_dev *dev);
230 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
231 struct timespec *timestamp,
233 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
234 struct timespec *timestamp);
236 static const struct rte_pci_id pci_id_i40e_map[] = {
237 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
238 #include "rte_pci_dev_ids.h"
239 { .vendor_id = 0, /* sentinel */ },
242 static const struct eth_dev_ops i40e_eth_dev_ops = {
243 .dev_configure = i40e_dev_configure,
244 .dev_start = i40e_dev_start,
245 .dev_stop = i40e_dev_stop,
246 .dev_close = i40e_dev_close,
247 .promiscuous_enable = i40e_dev_promiscuous_enable,
248 .promiscuous_disable = i40e_dev_promiscuous_disable,
249 .allmulticast_enable = i40e_dev_allmulticast_enable,
250 .allmulticast_disable = i40e_dev_allmulticast_disable,
251 .dev_set_link_up = i40e_dev_set_link_up,
252 .dev_set_link_down = i40e_dev_set_link_down,
253 .link_update = i40e_dev_link_update,
254 .stats_get = i40e_dev_stats_get,
255 .stats_reset = i40e_dev_stats_reset,
256 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
257 .dev_infos_get = i40e_dev_info_get,
258 .vlan_filter_set = i40e_vlan_filter_set,
259 .vlan_tpid_set = i40e_vlan_tpid_set,
260 .vlan_offload_set = i40e_vlan_offload_set,
261 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
262 .vlan_pvid_set = i40e_vlan_pvid_set,
263 .rx_queue_start = i40e_dev_rx_queue_start,
264 .rx_queue_stop = i40e_dev_rx_queue_stop,
265 .tx_queue_start = i40e_dev_tx_queue_start,
266 .tx_queue_stop = i40e_dev_tx_queue_stop,
267 .rx_queue_setup = i40e_dev_rx_queue_setup,
268 .rx_queue_release = i40e_dev_rx_queue_release,
269 .rx_queue_count = i40e_dev_rx_queue_count,
270 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
271 .tx_queue_setup = i40e_dev_tx_queue_setup,
272 .tx_queue_release = i40e_dev_tx_queue_release,
273 .dev_led_on = i40e_dev_led_on,
274 .dev_led_off = i40e_dev_led_off,
275 .flow_ctrl_set = i40e_flow_ctrl_set,
276 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
277 .mac_addr_add = i40e_macaddr_add,
278 .mac_addr_remove = i40e_macaddr_remove,
279 .reta_update = i40e_dev_rss_reta_update,
280 .reta_query = i40e_dev_rss_reta_query,
281 .rss_hash_update = i40e_dev_rss_hash_update,
282 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
283 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
284 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
285 .filter_ctrl = i40e_dev_filter_ctrl,
286 .mirror_rule_set = i40e_mirror_rule_set,
287 .mirror_rule_reset = i40e_mirror_rule_reset,
288 .timesync_enable = i40e_timesync_enable,
289 .timesync_disable = i40e_timesync_disable,
290 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
291 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
294 static struct eth_driver rte_i40e_pmd = {
296 .name = "rte_i40e_pmd",
297 .id_table = pci_id_i40e_map,
298 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
299 RTE_PCI_DRV_DETACHABLE,
301 .eth_dev_init = eth_i40e_dev_init,
302 .eth_dev_uninit = eth_i40e_dev_uninit,
303 .dev_private_size = sizeof(struct i40e_adapter),
307 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
308 struct rte_eth_link *link)
310 struct rte_eth_link *dst = link;
311 struct rte_eth_link *src = &(dev->data->dev_link);
313 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
314 *(uint64_t *)src) == 0)
321 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
322 struct rte_eth_link *link)
324 struct rte_eth_link *dst = &(dev->data->dev_link);
325 struct rte_eth_link *src = link;
327 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
328 *(uint64_t *)src) == 0)
335 * Driver initialization routine.
336 * Invoked once at EAL init time.
337 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
340 rte_i40e_pmd_init(const char *name __rte_unused,
341 const char *params __rte_unused)
343 PMD_INIT_FUNC_TRACE();
344 rte_eth_driver_register(&rte_i40e_pmd);
349 static struct rte_driver rte_i40e_driver = {
351 .init = rte_i40e_pmd_init,
354 PMD_REGISTER_DRIVER(rte_i40e_driver);
357 * Initialize registers for flexible payload, which should be set by NVM.
358 * This should be removed from code once it is fixed in NVM.
360 #ifndef I40E_GLQF_ORT
361 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
363 #ifndef I40E_GLQF_PIT
364 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
367 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
369 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
370 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
371 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
372 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
373 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
374 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
375 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
376 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
377 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
378 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
380 /* GLQF_PIT Registers */
381 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
382 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
386 eth_i40e_dev_init(struct rte_eth_dev *dev)
388 struct rte_pci_device *pci_dev;
389 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
390 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
391 struct i40e_vsi *vsi;
396 PMD_INIT_FUNC_TRACE();
398 dev->dev_ops = &i40e_eth_dev_ops;
399 dev->rx_pkt_burst = i40e_recv_pkts;
400 dev->tx_pkt_burst = i40e_xmit_pkts;
402 /* for secondary processes, we don't initialise any further as primary
403 * has already done this work. Only check we don't need a different
405 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
406 if (dev->data->scattered_rx)
407 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
410 pci_dev = dev->pci_dev;
411 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
412 pf->adapter->eth_dev = dev;
413 pf->dev_data = dev->data;
415 hw->back = I40E_PF_TO_ADAPTER(pf);
416 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
418 PMD_INIT_LOG(ERR, "Hardware is not available, "
419 "as address is NULL");
423 hw->vendor_id = pci_dev->id.vendor_id;
424 hw->device_id = pci_dev->id.device_id;
425 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
426 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
427 hw->bus.device = pci_dev->addr.devid;
428 hw->bus.func = pci_dev->addr.function;
429 hw->adapter_stopped = 0;
431 /* Make sure all is clean before doing PF reset */
434 /* Initialize the hardware */
437 /* Reset here to make sure all is clean for each PF */
438 ret = i40e_pf_reset(hw);
440 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
444 /* Initialize the shared code (base driver) */
445 ret = i40e_init_shared_code(hw);
447 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
452 * To work around the NVM issue,initialize registers
453 * for flexible payload by software.
454 * It should be removed once issues are fixed in NVM.
456 i40e_flex_payload_reg_init(hw);
458 /* Initialize the parameters for adminq */
459 i40e_init_adminq_parameter(hw);
460 ret = i40e_init_adminq(hw);
461 if (ret != I40E_SUCCESS) {
462 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
465 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
466 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
467 hw->aq.api_maj_ver, hw->aq.api_min_ver,
468 ((hw->nvm.version >> 12) & 0xf),
469 ((hw->nvm.version >> 4) & 0xff),
470 (hw->nvm.version & 0xf), hw->nvm.eetrack);
473 ret = i40e_aq_stop_lldp(hw, true, NULL);
474 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
475 PMD_INIT_LOG(INFO, "Failed to stop lldp");
478 i40e_clear_pxe_mode(hw);
481 * On X710, performance number is far from the expectation on recent
482 * firmware versions. The fix for this issue may not be integrated in
483 * the following firmware version. So the workaround in software driver
484 * is needed. It needs to modify the initial values of 3 internal only
485 * registers. Note that the workaround can be removed when it is fixed
486 * in firmware in the future.
488 i40e_configure_registers(hw);
490 /* Get hw capabilities */
491 ret = i40e_get_cap(hw);
492 if (ret != I40E_SUCCESS) {
493 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
494 goto err_get_capabilities;
497 /* Initialize parameters for PF */
498 ret = i40e_pf_parameter_init(dev);
500 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
501 goto err_parameter_init;
504 /* Initialize the queue management */
505 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
507 PMD_INIT_LOG(ERR, "Failed to init queue pool");
508 goto err_qp_pool_init;
510 ret = i40e_res_pool_init(&pf->msix_pool, 1,
511 hw->func_caps.num_msix_vectors - 1);
513 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
514 goto err_msix_pool_init;
517 /* Initialize lan hmc */
518 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
519 hw->func_caps.num_rx_qp, 0, 0);
520 if (ret != I40E_SUCCESS) {
521 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
522 goto err_init_lan_hmc;
525 /* Configure lan hmc */
526 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
527 if (ret != I40E_SUCCESS) {
528 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
529 goto err_configure_lan_hmc;
532 /* Get and check the mac address */
533 i40e_get_mac_addr(hw, hw->mac.addr);
534 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
535 PMD_INIT_LOG(ERR, "mac address is not valid");
537 goto err_get_mac_addr;
539 /* Copy the permanent MAC address */
540 ether_addr_copy((struct ether_addr *) hw->mac.addr,
541 (struct ether_addr *) hw->mac.perm_addr);
543 /* Disable flow control */
544 hw->fc.requested_mode = I40E_FC_NONE;
545 i40e_set_fc(hw, &aq_fail, TRUE);
547 /* PF setup, which includes VSI setup */
548 ret = i40e_pf_setup(pf);
550 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
551 goto err_setup_pf_switch;
556 /* Disable double vlan by default */
557 i40e_vsi_config_double_vlan(vsi, FALSE);
559 if (!vsi->max_macaddrs)
560 len = ETHER_ADDR_LEN;
562 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
564 /* Should be after VSI initialized */
565 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
566 if (!dev->data->mac_addrs) {
567 PMD_INIT_LOG(ERR, "Failed to allocated memory "
568 "for storing mac address");
571 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
572 &dev->data->mac_addrs[0]);
574 /* initialize pf host driver to setup SRIOV resource if applicable */
575 i40e_pf_host_init(dev);
577 /* register callback func to eal lib */
578 rte_intr_callback_register(&(pci_dev->intr_handle),
579 i40e_dev_interrupt_handler, (void *)dev);
581 /* configure and enable device interrupt */
582 i40e_pf_config_irq0(hw);
583 i40e_pf_enable_irq0(hw);
585 /* enable uio intr after callback register */
586 rte_intr_enable(&(pci_dev->intr_handle));
588 /* initialize mirror rule list */
589 TAILQ_INIT(&pf->mirror_list);
594 i40e_vsi_release(pf->main_vsi);
597 err_configure_lan_hmc:
598 (void)i40e_shutdown_lan_hmc(hw);
600 i40e_res_pool_destroy(&pf->msix_pool);
602 i40e_res_pool_destroy(&pf->qp_pool);
605 err_get_capabilities:
606 (void)i40e_shutdown_adminq(hw);
612 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
614 struct rte_pci_device *pci_dev;
616 struct i40e_filter_control_settings settings;
620 PMD_INIT_FUNC_TRACE();
622 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
625 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
626 pci_dev = dev->pci_dev;
628 if (hw->adapter_stopped == 0)
632 dev->rx_pkt_burst = NULL;
633 dev->tx_pkt_burst = NULL;
636 ret = i40e_aq_stop_lldp(hw, true, NULL);
637 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
638 PMD_INIT_LOG(INFO, "Failed to stop lldp");
641 i40e_clear_pxe_mode(hw);
643 /* Unconfigure filter control */
644 memset(&settings, 0, sizeof(settings));
645 ret = i40e_set_filter_control(hw, &settings);
647 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
650 /* Disable flow control */
651 hw->fc.requested_mode = I40E_FC_NONE;
652 i40e_set_fc(hw, &aq_fail, TRUE);
654 /* uninitialize pf host driver */
655 i40e_pf_host_uninit(dev);
657 rte_free(dev->data->mac_addrs);
658 dev->data->mac_addrs = NULL;
660 /* disable uio intr before callback unregister */
661 rte_intr_disable(&(pci_dev->intr_handle));
663 /* register callback func to eal lib */
664 rte_intr_callback_unregister(&(pci_dev->intr_handle),
665 i40e_dev_interrupt_handler, (void *)dev);
671 i40e_dev_configure(struct rte_eth_dev *dev)
673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
674 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
677 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
678 ret = i40e_fdir_setup(pf);
679 if (ret != I40E_SUCCESS) {
680 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
683 ret = i40e_fdir_configure(dev);
685 PMD_DRV_LOG(ERR, "failed to configure fdir.");
689 i40e_fdir_teardown(pf);
691 ret = i40e_dev_init_vlan(dev);
696 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
697 * RSS setting have different requirements.
698 * General PMD driver call sequence are NIC init, configure,
699 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
700 * will try to lookup the VSI that specific queue belongs to if VMDQ
701 * applicable. So, VMDQ setting has to be done before
702 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
703 * For RSS setting, it will try to calculate actual configured RX queue
704 * number, which will be available after rx_queue_setup(). dev_start()
705 * function is good to place RSS setup.
707 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
708 ret = i40e_vmdq_setup(dev);
714 i40e_fdir_teardown(pf);
719 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
721 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
722 uint16_t msix_vect = vsi->msix_intr;
725 for (i = 0; i < vsi->nb_qps; i++) {
726 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
727 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
731 if (vsi->type != I40E_VSI_SRIOV) {
732 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
733 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
737 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
738 vsi->user_param + (msix_vect - 1);
740 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
742 I40E_WRITE_FLUSH(hw);
745 static inline uint16_t
746 i40e_calc_itr_interval(int16_t interval)
748 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
749 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
751 /* Convert to hardware count, as writing each 1 represents 2 us */
756 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
759 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
760 uint16_t msix_vect = vsi->msix_intr;
763 for (i = 0; i < vsi->nb_qps; i++)
764 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
766 /* Bind all RX queues to allocated MSIX interrupt */
767 for (i = 0; i < vsi->nb_qps; i++) {
768 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
769 I40E_QINT_RQCTL_ITR_INDX_MASK |
770 ((vsi->base_queue + i + 1) <<
771 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
772 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
773 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
775 if (i == vsi->nb_qps - 1)
776 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
777 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
780 /* Write first RX queue to Link list register as the head element */
781 if (vsi->type != I40E_VSI_SRIOV) {
783 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
785 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
787 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
788 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
790 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
791 msix_vect - 1), interval);
793 #ifndef I40E_GLINT_CTL
794 #define I40E_GLINT_CTL 0x0003F800
795 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
797 /* Disable auto-mask on enabling of all none-zero interrupt */
798 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
799 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
803 /* num_msix_vectors_vf needs to minus irq0 */
804 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
805 vsi->user_param + (msix_vect - 1);
807 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
808 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
809 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
812 I40E_WRITE_FLUSH(hw);
816 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
818 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
819 uint16_t interval = i40e_calc_itr_interval(\
820 RTE_LIBRTE_I40E_ITR_INTERVAL);
822 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
823 I40E_PFINT_DYN_CTLN_INTENA_MASK |
824 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
825 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
826 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
830 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
832 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
834 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
837 static inline uint8_t
838 i40e_parse_link_speed(uint16_t eth_link_speed)
840 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
842 switch (eth_link_speed) {
843 case ETH_LINK_SPEED_40G:
844 link_speed = I40E_LINK_SPEED_40GB;
846 case ETH_LINK_SPEED_20G:
847 link_speed = I40E_LINK_SPEED_20GB;
849 case ETH_LINK_SPEED_10G:
850 link_speed = I40E_LINK_SPEED_10GB;
852 case ETH_LINK_SPEED_1000:
853 link_speed = I40E_LINK_SPEED_1GB;
855 case ETH_LINK_SPEED_100:
856 link_speed = I40E_LINK_SPEED_100MB;
864 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
866 enum i40e_status_code status;
867 struct i40e_aq_get_phy_abilities_resp phy_ab;
868 struct i40e_aq_set_phy_config phy_conf;
869 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
870 I40E_AQ_PHY_FLAG_PAUSE_RX |
871 I40E_AQ_PHY_FLAG_LOW_POWER;
872 const uint8_t advt = I40E_LINK_SPEED_40GB |
873 I40E_LINK_SPEED_10GB |
874 I40E_LINK_SPEED_1GB |
875 I40E_LINK_SPEED_100MB;
878 /* Skip it on 40G interfaces, as a workaround for the link issue */
879 if (i40e_is_40G_device(hw->device_id))
882 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
887 memset(&phy_conf, 0, sizeof(phy_conf));
889 /* bits 0-2 use the values from get_phy_abilities_resp */
891 abilities |= phy_ab.abilities & mask;
893 /* update ablities and speed */
894 if (abilities & I40E_AQ_PHY_AN_ENABLED)
895 phy_conf.link_speed = advt;
897 phy_conf.link_speed = force_speed;
899 phy_conf.abilities = abilities;
901 /* use get_phy_abilities_resp value for the rest */
902 phy_conf.phy_type = phy_ab.phy_type;
903 phy_conf.eee_capability = phy_ab.eee_capability;
904 phy_conf.eeer = phy_ab.eeer_val;
905 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
907 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
908 phy_ab.abilities, phy_ab.link_speed);
909 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
910 phy_conf.abilities, phy_conf.link_speed);
912 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
920 i40e_apply_link_speed(struct rte_eth_dev *dev)
923 uint8_t abilities = 0;
924 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
925 struct rte_eth_conf *conf = &dev->data->dev_conf;
927 speed = i40e_parse_link_speed(conf->link_speed);
928 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
929 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
930 abilities |= I40E_AQ_PHY_AN_ENABLED;
932 abilities |= I40E_AQ_PHY_LINK_ENABLED;
934 return i40e_phy_conf_link(hw, abilities, speed);
938 i40e_dev_start(struct rte_eth_dev *dev)
940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
942 struct i40e_vsi *main_vsi = pf->main_vsi;
945 hw->adapter_stopped = 0;
947 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
948 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
949 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
950 dev->data->dev_conf.link_duplex,
956 ret = i40e_dev_rxtx_init(pf);
957 if (ret != I40E_SUCCESS) {
958 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
962 /* Map queues with MSIX interrupt */
963 i40e_vsi_queues_bind_intr(main_vsi);
964 i40e_vsi_enable_queues_intr(main_vsi);
966 /* Map VMDQ VSI queues with MSIX interrupt */
967 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
968 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
969 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
972 /* enable FDIR MSIX interrupt */
973 if (pf->fdir.fdir_vsi) {
974 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
975 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
978 /* Enable all queues which have been configured */
979 ret = i40e_dev_switch_queues(pf, TRUE);
980 if (ret != I40E_SUCCESS) {
981 PMD_DRV_LOG(ERR, "Failed to enable VSI");
985 /* Enable receiving broadcast packets */
986 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
987 if (ret != I40E_SUCCESS)
988 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
990 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
991 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
993 if (ret != I40E_SUCCESS)
994 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
997 /* Apply link configure */
998 ret = i40e_apply_link_speed(dev);
999 if (I40E_SUCCESS != ret) {
1000 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1004 return I40E_SUCCESS;
1007 i40e_dev_switch_queues(pf, FALSE);
1008 i40e_dev_clear_queues(dev);
1014 i40e_dev_stop(struct rte_eth_dev *dev)
1016 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017 struct i40e_vsi *main_vsi = pf->main_vsi;
1018 struct i40e_mirror_rule *p_mirror;
1021 /* Disable all queues */
1022 i40e_dev_switch_queues(pf, FALSE);
1024 /* un-map queues with interrupt registers */
1025 i40e_vsi_disable_queues_intr(main_vsi);
1026 i40e_vsi_queues_unbind_intr(main_vsi);
1028 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1029 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1030 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1033 if (pf->fdir.fdir_vsi) {
1034 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1035 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1037 /* Clear all queues and release memory */
1038 i40e_dev_clear_queues(dev);
1041 i40e_dev_set_link_down(dev);
1043 /* Remove all mirror rules */
1044 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1045 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1048 pf->nb_mirror_rule = 0;
1053 i40e_dev_close(struct rte_eth_dev *dev)
1055 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1056 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060 PMD_INIT_FUNC_TRACE();
1063 hw->adapter_stopped = 1;
1064 i40e_dev_free_queues(dev);
1066 /* Disable interrupt */
1067 i40e_pf_disable_irq0(hw);
1068 rte_intr_disable(&(dev->pci_dev->intr_handle));
1070 /* shutdown and destroy the HMC */
1071 i40e_shutdown_lan_hmc(hw);
1073 /* release all the existing VSIs and VEBs */
1074 i40e_fdir_teardown(pf);
1075 i40e_vsi_release(pf->main_vsi);
1077 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1078 i40e_vsi_release(pf->vmdq[i].vsi);
1079 pf->vmdq[i].vsi = NULL;
1085 /* shutdown the adminq */
1086 i40e_aq_queue_shutdown(hw, true);
1087 i40e_shutdown_adminq(hw);
1089 i40e_res_pool_destroy(&pf->qp_pool);
1090 i40e_res_pool_destroy(&pf->msix_pool);
1092 /* force a PF reset to clean anything leftover */
1093 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1094 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1095 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1096 I40E_WRITE_FLUSH(hw);
1100 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1102 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1103 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104 struct i40e_vsi *vsi = pf->main_vsi;
1107 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1109 if (status != I40E_SUCCESS)
1110 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1112 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1114 if (status != I40E_SUCCESS)
1115 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1120 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1122 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1123 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1124 struct i40e_vsi *vsi = pf->main_vsi;
1127 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1129 if (status != I40E_SUCCESS)
1130 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1132 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1134 if (status != I40E_SUCCESS)
1135 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1139 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1143 struct i40e_vsi *vsi = pf->main_vsi;
1146 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1147 if (ret != I40E_SUCCESS)
1148 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1152 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1154 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1156 struct i40e_vsi *vsi = pf->main_vsi;
1159 if (dev->data->promiscuous == 1)
1160 return; /* must remain in all_multicast mode */
1162 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1163 vsi->seid, FALSE, NULL);
1164 if (ret != I40E_SUCCESS)
1165 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1169 * Set device link up.
1172 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1174 /* re-apply link speed setting */
1175 return i40e_apply_link_speed(dev);
1179 * Set device link down.
1182 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1184 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1185 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188 return i40e_phy_conf_link(hw, abilities, speed);
1192 i40e_dev_link_update(struct rte_eth_dev *dev,
1193 int wait_to_complete)
1195 #define CHECK_INTERVAL 100 /* 100ms */
1196 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1197 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1198 struct i40e_link_status link_status;
1199 struct rte_eth_link link, old;
1201 unsigned rep_cnt = MAX_REPEAT_TIME;
1203 memset(&link, 0, sizeof(link));
1204 memset(&old, 0, sizeof(old));
1205 memset(&link_status, 0, sizeof(link_status));
1206 rte_i40e_dev_atomic_read_link_status(dev, &old);
1209 /* Get link status information from hardware */
1210 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1211 if (status != I40E_SUCCESS) {
1212 link.link_speed = ETH_LINK_SPEED_100;
1213 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1214 PMD_DRV_LOG(ERR, "Failed to get link info");
1218 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1219 if (!wait_to_complete)
1222 rte_delay_ms(CHECK_INTERVAL);
1223 } while (!link.link_status && rep_cnt--);
1225 if (!link.link_status)
1228 /* i40e uses full duplex only */
1229 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1231 /* Parse the link status */
1232 switch (link_status.link_speed) {
1233 case I40E_LINK_SPEED_100MB:
1234 link.link_speed = ETH_LINK_SPEED_100;
1236 case I40E_LINK_SPEED_1GB:
1237 link.link_speed = ETH_LINK_SPEED_1000;
1239 case I40E_LINK_SPEED_10GB:
1240 link.link_speed = ETH_LINK_SPEED_10G;
1242 case I40E_LINK_SPEED_20GB:
1243 link.link_speed = ETH_LINK_SPEED_20G;
1245 case I40E_LINK_SPEED_40GB:
1246 link.link_speed = ETH_LINK_SPEED_40G;
1249 link.link_speed = ETH_LINK_SPEED_100;
1254 rte_i40e_dev_atomic_write_link_status(dev, &link);
1255 if (link.link_status == old.link_status)
1261 /* Get all the statistics of a VSI */
1263 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1265 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1266 struct i40e_eth_stats *nes = &vsi->eth_stats;
1267 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1268 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1270 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1271 vsi->offset_loaded, &oes->rx_bytes,
1273 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1274 vsi->offset_loaded, &oes->rx_unicast,
1276 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1277 vsi->offset_loaded, &oes->rx_multicast,
1278 &nes->rx_multicast);
1279 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1280 vsi->offset_loaded, &oes->rx_broadcast,
1281 &nes->rx_broadcast);
1282 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1283 &oes->rx_discards, &nes->rx_discards);
1284 /* GLV_REPC not supported */
1285 /* GLV_RMPC not supported */
1286 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1287 &oes->rx_unknown_protocol,
1288 &nes->rx_unknown_protocol);
1289 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1290 vsi->offset_loaded, &oes->tx_bytes,
1292 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1293 vsi->offset_loaded, &oes->tx_unicast,
1295 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1296 vsi->offset_loaded, &oes->tx_multicast,
1297 &nes->tx_multicast);
1298 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1299 vsi->offset_loaded, &oes->tx_broadcast,
1300 &nes->tx_broadcast);
1301 /* GLV_TDPC not supported */
1302 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1303 &oes->tx_errors, &nes->tx_errors);
1304 vsi->offset_loaded = true;
1306 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1308 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1309 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1310 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1311 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1312 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1313 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1314 nes->rx_unknown_protocol);
1315 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1316 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1317 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1318 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1319 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1320 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1321 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1325 /* Get all statistics of a port */
1327 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1330 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1331 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1333 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1335 /* Get statistics of struct i40e_eth_stats */
1336 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1337 I40E_GLPRT_GORCL(hw->port),
1338 pf->offset_loaded, &os->eth.rx_bytes,
1340 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1341 I40E_GLPRT_UPRCL(hw->port),
1342 pf->offset_loaded, &os->eth.rx_unicast,
1343 &ns->eth.rx_unicast);
1344 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1345 I40E_GLPRT_MPRCL(hw->port),
1346 pf->offset_loaded, &os->eth.rx_multicast,
1347 &ns->eth.rx_multicast);
1348 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1349 I40E_GLPRT_BPRCL(hw->port),
1350 pf->offset_loaded, &os->eth.rx_broadcast,
1351 &ns->eth.rx_broadcast);
1352 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1353 pf->offset_loaded, &os->eth.rx_discards,
1354 &ns->eth.rx_discards);
1355 /* GLPRT_REPC not supported */
1356 /* GLPRT_RMPC not supported */
1357 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1359 &os->eth.rx_unknown_protocol,
1360 &ns->eth.rx_unknown_protocol);
1361 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1362 I40E_GLPRT_GOTCL(hw->port),
1363 pf->offset_loaded, &os->eth.tx_bytes,
1365 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1366 I40E_GLPRT_UPTCL(hw->port),
1367 pf->offset_loaded, &os->eth.tx_unicast,
1368 &ns->eth.tx_unicast);
1369 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1370 I40E_GLPRT_MPTCL(hw->port),
1371 pf->offset_loaded, &os->eth.tx_multicast,
1372 &ns->eth.tx_multicast);
1373 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1374 I40E_GLPRT_BPTCL(hw->port),
1375 pf->offset_loaded, &os->eth.tx_broadcast,
1376 &ns->eth.tx_broadcast);
1377 /* GLPRT_TEPC not supported */
1379 /* additional port specific stats */
1380 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1381 pf->offset_loaded, &os->tx_dropped_link_down,
1382 &ns->tx_dropped_link_down);
1383 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1384 pf->offset_loaded, &os->crc_errors,
1386 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1387 pf->offset_loaded, &os->illegal_bytes,
1388 &ns->illegal_bytes);
1389 /* GLPRT_ERRBC not supported */
1390 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1391 pf->offset_loaded, &os->mac_local_faults,
1392 &ns->mac_local_faults);
1393 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1394 pf->offset_loaded, &os->mac_remote_faults,
1395 &ns->mac_remote_faults);
1396 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1397 pf->offset_loaded, &os->rx_length_errors,
1398 &ns->rx_length_errors);
1399 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1400 pf->offset_loaded, &os->link_xon_rx,
1402 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1403 pf->offset_loaded, &os->link_xoff_rx,
1405 for (i = 0; i < 8; i++) {
1406 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1408 &os->priority_xon_rx[i],
1409 &ns->priority_xon_rx[i]);
1410 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1412 &os->priority_xoff_rx[i],
1413 &ns->priority_xoff_rx[i]);
1415 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1416 pf->offset_loaded, &os->link_xon_tx,
1418 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1419 pf->offset_loaded, &os->link_xoff_tx,
1421 for (i = 0; i < 8; i++) {
1422 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1424 &os->priority_xon_tx[i],
1425 &ns->priority_xon_tx[i]);
1426 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1428 &os->priority_xoff_tx[i],
1429 &ns->priority_xoff_tx[i]);
1430 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1432 &os->priority_xon_2_xoff[i],
1433 &ns->priority_xon_2_xoff[i]);
1435 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1436 I40E_GLPRT_PRC64L(hw->port),
1437 pf->offset_loaded, &os->rx_size_64,
1439 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1440 I40E_GLPRT_PRC127L(hw->port),
1441 pf->offset_loaded, &os->rx_size_127,
1443 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1444 I40E_GLPRT_PRC255L(hw->port),
1445 pf->offset_loaded, &os->rx_size_255,
1447 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1448 I40E_GLPRT_PRC511L(hw->port),
1449 pf->offset_loaded, &os->rx_size_511,
1451 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1452 I40E_GLPRT_PRC1023L(hw->port),
1453 pf->offset_loaded, &os->rx_size_1023,
1455 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1456 I40E_GLPRT_PRC1522L(hw->port),
1457 pf->offset_loaded, &os->rx_size_1522,
1459 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1460 I40E_GLPRT_PRC9522L(hw->port),
1461 pf->offset_loaded, &os->rx_size_big,
1463 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1464 pf->offset_loaded, &os->rx_undersize,
1466 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1467 pf->offset_loaded, &os->rx_fragments,
1469 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1470 pf->offset_loaded, &os->rx_oversize,
1472 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1473 pf->offset_loaded, &os->rx_jabber,
1475 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1476 I40E_GLPRT_PTC64L(hw->port),
1477 pf->offset_loaded, &os->tx_size_64,
1479 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1480 I40E_GLPRT_PTC127L(hw->port),
1481 pf->offset_loaded, &os->tx_size_127,
1483 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1484 I40E_GLPRT_PTC255L(hw->port),
1485 pf->offset_loaded, &os->tx_size_255,
1487 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1488 I40E_GLPRT_PTC511L(hw->port),
1489 pf->offset_loaded, &os->tx_size_511,
1491 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1492 I40E_GLPRT_PTC1023L(hw->port),
1493 pf->offset_loaded, &os->tx_size_1023,
1495 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1496 I40E_GLPRT_PTC1522L(hw->port),
1497 pf->offset_loaded, &os->tx_size_1522,
1499 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1500 I40E_GLPRT_PTC9522L(hw->port),
1501 pf->offset_loaded, &os->tx_size_big,
1503 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1505 &os->fd_sb_match, &ns->fd_sb_match);
1506 /* GLPRT_MSPDC not supported */
1507 /* GLPRT_XEC not supported */
1509 pf->offset_loaded = true;
1512 i40e_update_vsi_stats(pf->main_vsi);
1514 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1515 ns->eth.rx_broadcast;
1516 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1517 ns->eth.tx_broadcast;
1518 stats->ibytes = ns->eth.rx_bytes;
1519 stats->obytes = ns->eth.tx_bytes;
1520 stats->oerrors = ns->eth.tx_errors;
1521 stats->imcasts = ns->eth.rx_multicast;
1522 stats->fdirmatch = ns->fd_sb_match;
1525 stats->ibadcrc = ns->crc_errors;
1526 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1527 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1528 stats->imissed = ns->eth.rx_discards;
1529 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1531 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1532 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
1533 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
1534 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
1535 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
1536 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
1537 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1538 ns->eth.rx_unknown_protocol);
1539 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
1540 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
1541 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
1542 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
1543 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
1544 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
1546 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
1547 ns->tx_dropped_link_down);
1548 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
1549 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
1551 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
1552 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
1553 ns->mac_local_faults);
1554 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
1555 ns->mac_remote_faults);
1556 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
1557 ns->rx_length_errors);
1558 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
1559 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
1560 for (i = 0; i < 8; i++) {
1561 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
1562 i, ns->priority_xon_rx[i]);
1563 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
1564 i, ns->priority_xoff_rx[i]);
1566 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
1567 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
1568 for (i = 0; i < 8; i++) {
1569 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
1570 i, ns->priority_xon_tx[i]);
1571 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
1572 i, ns->priority_xoff_tx[i]);
1573 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
1574 i, ns->priority_xon_2_xoff[i]);
1576 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
1577 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
1578 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
1579 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
1580 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
1581 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
1582 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
1583 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
1584 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
1585 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
1586 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
1587 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
1588 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
1589 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
1590 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
1591 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
1592 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
1593 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
1594 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1595 ns->mac_short_packet_dropped);
1596 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
1597 ns->checksum_error);
1598 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
1599 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1602 /* Reset the statistics */
1604 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1606 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1608 /* It results in reloading the start point of each counter */
1609 pf->offset_loaded = false;
1613 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1614 __rte_unused uint16_t queue_id,
1615 __rte_unused uint8_t stat_idx,
1616 __rte_unused uint8_t is_rx)
1618 PMD_INIT_FUNC_TRACE();
1624 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1627 struct i40e_vsi *vsi = pf->main_vsi;
1629 dev_info->max_rx_queues = vsi->nb_qps;
1630 dev_info->max_tx_queues = vsi->nb_qps;
1631 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1632 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1633 dev_info->max_mac_addrs = vsi->max_macaddrs;
1634 dev_info->max_vfs = dev->pci_dev->max_vfs;
1635 dev_info->rx_offload_capa =
1636 DEV_RX_OFFLOAD_VLAN_STRIP |
1637 DEV_RX_OFFLOAD_QINQ_STRIP |
1638 DEV_RX_OFFLOAD_IPV4_CKSUM |
1639 DEV_RX_OFFLOAD_UDP_CKSUM |
1640 DEV_RX_OFFLOAD_TCP_CKSUM;
1641 dev_info->tx_offload_capa =
1642 DEV_TX_OFFLOAD_VLAN_INSERT |
1643 DEV_TX_OFFLOAD_QINQ_INSERT |
1644 DEV_TX_OFFLOAD_IPV4_CKSUM |
1645 DEV_TX_OFFLOAD_UDP_CKSUM |
1646 DEV_TX_OFFLOAD_TCP_CKSUM |
1647 DEV_TX_OFFLOAD_SCTP_CKSUM |
1648 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1649 DEV_TX_OFFLOAD_TCP_TSO;
1650 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1652 dev_info->reta_size = pf->hash_lut_size;
1653 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1655 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1657 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1658 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1659 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1661 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1665 dev_info->default_txconf = (struct rte_eth_txconf) {
1667 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1668 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1669 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1671 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1672 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1673 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1674 ETH_TXQ_FLAGS_NOOFFLOADS,
1677 if (pf->flags & I40E_FLAG_VMDQ) {
1678 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1679 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1680 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1681 pf->max_nb_vmdq_vsi;
1682 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1683 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1684 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1689 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1692 struct i40e_vsi *vsi = pf->main_vsi;
1693 PMD_INIT_FUNC_TRACE();
1696 return i40e_vsi_add_vlan(vsi, vlan_id);
1698 return i40e_vsi_delete_vlan(vsi, vlan_id);
1702 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1703 __rte_unused uint16_t tpid)
1705 PMD_INIT_FUNC_TRACE();
1709 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1712 struct i40e_vsi *vsi = pf->main_vsi;
1714 if (mask & ETH_VLAN_STRIP_MASK) {
1715 /* Enable or disable VLAN stripping */
1716 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1717 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1719 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1722 if (mask & ETH_VLAN_EXTEND_MASK) {
1723 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1724 i40e_vsi_config_double_vlan(vsi, TRUE);
1726 i40e_vsi_config_double_vlan(vsi, FALSE);
1731 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1732 __rte_unused uint16_t queue,
1733 __rte_unused int on)
1735 PMD_INIT_FUNC_TRACE();
1739 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1741 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1742 struct i40e_vsi *vsi = pf->main_vsi;
1743 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1744 struct i40e_vsi_vlan_pvid_info info;
1746 memset(&info, 0, sizeof(info));
1749 info.config.pvid = pvid;
1751 info.config.reject.tagged =
1752 data->dev_conf.txmode.hw_vlan_reject_tagged;
1753 info.config.reject.untagged =
1754 data->dev_conf.txmode.hw_vlan_reject_untagged;
1757 return i40e_vsi_vlan_pvid_set(vsi, &info);
1761 i40e_dev_led_on(struct rte_eth_dev *dev)
1763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764 uint32_t mode = i40e_led_get(hw);
1767 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1773 i40e_dev_led_off(struct rte_eth_dev *dev)
1775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776 uint32_t mode = i40e_led_get(hw);
1779 i40e_led_set(hw, 0, false);
1785 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1786 __rte_unused struct rte_eth_fc_conf *fc_conf)
1788 PMD_INIT_FUNC_TRACE();
1794 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1795 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1797 PMD_INIT_FUNC_TRACE();
1802 /* Add a MAC address, and update filters */
1804 i40e_macaddr_add(struct rte_eth_dev *dev,
1805 struct ether_addr *mac_addr,
1806 __rte_unused uint32_t index,
1809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1810 struct i40e_mac_filter_info mac_filter;
1811 struct i40e_vsi *vsi;
1814 /* If VMDQ not enabled or configured, return */
1815 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1816 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1817 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1822 if (pool > pf->nb_cfg_vmdq_vsi) {
1823 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1824 pool, pf->nb_cfg_vmdq_vsi);
1828 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1829 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1834 vsi = pf->vmdq[pool - 1].vsi;
1836 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1837 if (ret != I40E_SUCCESS) {
1838 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1843 /* Remove a MAC address, and update filters */
1845 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1847 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1848 struct i40e_vsi *vsi;
1849 struct rte_eth_dev_data *data = dev->data;
1850 struct ether_addr *macaddr;
1855 macaddr = &(data->mac_addrs[index]);
1857 pool_sel = dev->data->mac_pool_sel[index];
1859 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1860 if (pool_sel & (1ULL << i)) {
1864 /* No VMDQ pool enabled or configured */
1865 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1866 (i > pf->nb_cfg_vmdq_vsi)) {
1867 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1871 vsi = pf->vmdq[i - 1].vsi;
1873 ret = i40e_vsi_delete_mac(vsi, macaddr);
1876 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1883 /* Set perfect match or hash match of MAC and VLAN for a VF */
1885 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1886 struct rte_eth_mac_filter *filter,
1890 struct i40e_mac_filter_info mac_filter;
1891 struct ether_addr old_mac;
1892 struct ether_addr *new_mac;
1893 struct i40e_pf_vf *vf = NULL;
1898 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1901 hw = I40E_PF_TO_HW(pf);
1903 if (filter == NULL) {
1904 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1908 new_mac = &filter->mac_addr;
1910 if (is_zero_ether_addr(new_mac)) {
1911 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1915 vf_id = filter->dst_id;
1917 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1918 PMD_DRV_LOG(ERR, "Invalid argument.");
1921 vf = &pf->vfs[vf_id];
1923 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1924 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1929 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1930 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1932 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1935 mac_filter.filter_type = filter->filter_type;
1936 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1937 if (ret != I40E_SUCCESS) {
1938 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1941 ether_addr_copy(new_mac, &pf->dev_addr);
1943 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1945 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1946 if (ret != I40E_SUCCESS) {
1947 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1951 /* Clear device address as it has been removed */
1952 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1953 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1959 /* MAC filter handle */
1961 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1965 struct rte_eth_mac_filter *filter;
1966 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1967 int ret = I40E_NOT_SUPPORTED;
1969 filter = (struct rte_eth_mac_filter *)(arg);
1971 switch (filter_op) {
1972 case RTE_ETH_FILTER_NOP:
1975 case RTE_ETH_FILTER_ADD:
1976 i40e_pf_disable_irq0(hw);
1978 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1979 i40e_pf_enable_irq0(hw);
1981 case RTE_ETH_FILTER_DELETE:
1982 i40e_pf_disable_irq0(hw);
1984 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1985 i40e_pf_enable_irq0(hw);
1988 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1989 ret = I40E_ERR_PARAM;
1997 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1998 struct rte_eth_rss_reta_entry64 *reta_conf,
2001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2002 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004 uint16_t i, j, lut_size = pf->hash_lut_size;
2005 uint16_t idx, shift;
2008 if (reta_size != lut_size ||
2009 reta_size > ETH_RSS_RETA_SIZE_512) {
2010 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2011 "(%d) doesn't match the number hardware can supported "
2012 "(%d)\n", reta_size, lut_size);
2016 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2017 idx = i / RTE_RETA_GROUP_SIZE;
2018 shift = i % RTE_RETA_GROUP_SIZE;
2019 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2023 if (mask == I40E_4_BIT_MASK)
2026 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2027 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2028 if (mask & (0x1 << j))
2029 lut |= reta_conf[idx].reta[shift + j] <<
2032 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2034 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2041 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2042 struct rte_eth_rss_reta_entry64 *reta_conf,
2045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2046 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048 uint16_t i, j, lut_size = pf->hash_lut_size;
2049 uint16_t idx, shift;
2052 if (reta_size != lut_size ||
2053 reta_size > ETH_RSS_RETA_SIZE_512) {
2054 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2055 "(%d) doesn't match the number hardware can supported "
2056 "(%d)\n", reta_size, lut_size);
2060 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2061 idx = i / RTE_RETA_GROUP_SIZE;
2062 shift = i % RTE_RETA_GROUP_SIZE;
2063 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2068 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2069 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2070 if (mask & (0x1 << j))
2071 reta_conf[idx].reta[shift + j] = ((lut >>
2072 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2080 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2081 * @hw: pointer to the HW structure
2082 * @mem: pointer to mem struct to fill out
2083 * @size: size of memory requested
2084 * @alignment: what to align the allocation to
2086 enum i40e_status_code
2087 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2088 struct i40e_dma_mem *mem,
2092 static uint64_t id = 0;
2093 const struct rte_memzone *mz = NULL;
2094 char z_name[RTE_MEMZONE_NAMESIZE];
2097 return I40E_ERR_PARAM;
2100 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2101 #ifdef RTE_LIBRTE_XEN_DOM0
2102 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2103 alignment, RTE_PGSIZE_2M);
2105 mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2109 return I40E_ERR_NO_MEMORY;
2114 #ifdef RTE_LIBRTE_XEN_DOM0
2115 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2117 mem->pa = mz->phys_addr;
2120 return I40E_SUCCESS;
2124 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2125 * @hw: pointer to the HW structure
2126 * @mem: ptr to mem struct to free
2128 enum i40e_status_code
2129 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2130 struct i40e_dma_mem *mem)
2132 if (!mem || !mem->va)
2133 return I40E_ERR_PARAM;
2138 return I40E_SUCCESS;
2142 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2143 * @hw: pointer to the HW structure
2144 * @mem: pointer to mem struct to fill out
2145 * @size: size of memory requested
2147 enum i40e_status_code
2148 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2149 struct i40e_virt_mem *mem,
2153 return I40E_ERR_PARAM;
2156 mem->va = rte_zmalloc("i40e", size, 0);
2159 return I40E_SUCCESS;
2161 return I40E_ERR_NO_MEMORY;
2165 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2166 * @hw: pointer to the HW structure
2167 * @mem: pointer to mem struct to free
2169 enum i40e_status_code
2170 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2171 struct i40e_virt_mem *mem)
2174 return I40E_ERR_PARAM;
2179 return I40E_SUCCESS;
2183 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2185 rte_spinlock_init(&sp->spinlock);
2189 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2191 rte_spinlock_lock(&sp->spinlock);
2195 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2197 rte_spinlock_unlock(&sp->spinlock);
2201 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2207 * Get the hardware capabilities, which will be parsed
2208 * and saved into struct i40e_hw.
2211 i40e_get_cap(struct i40e_hw *hw)
2213 struct i40e_aqc_list_capabilities_element_resp *buf;
2214 uint16_t len, size = 0;
2217 /* Calculate a huge enough buff for saving response data temporarily */
2218 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2219 I40E_MAX_CAP_ELE_NUM;
2220 buf = rte_zmalloc("i40e", len, 0);
2222 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2223 return I40E_ERR_NO_MEMORY;
2226 /* Get, parse the capabilities and save it to hw */
2227 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2228 i40e_aqc_opc_list_func_capabilities, NULL);
2229 if (ret != I40E_SUCCESS)
2230 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2232 /* Free the temporary buffer after being used */
2239 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2241 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2242 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2243 uint16_t sum_queues = 0, sum_vsis, left_queues;
2245 /* First check if FW support SRIOV */
2246 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2247 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2251 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2252 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2253 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2254 /* Allocate queues for pf */
2255 if (hw->func_caps.rss) {
2256 pf->flags |= I40E_FLAG_RSS;
2257 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2258 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2259 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2262 sum_queues = pf->lan_nb_qps;
2263 /* Default VSI is not counted in */
2265 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2267 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2268 pf->flags |= I40E_FLAG_SRIOV;
2269 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2270 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2271 PMD_INIT_LOG(ERR, "Config VF number %u, "
2272 "max supported %u.",
2273 dev->pci_dev->max_vfs,
2274 hw->func_caps.num_vfs);
2277 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2278 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2279 "max support %u queues.",
2280 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2283 pf->vf_num = dev->pci_dev->max_vfs;
2284 sum_queues += pf->vf_nb_qps * pf->vf_num;
2285 sum_vsis += pf->vf_num;
2286 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2287 pf->vf_num, pf->vf_nb_qps);
2291 if (hw->func_caps.vmdq) {
2292 pf->flags |= I40E_FLAG_VMDQ;
2293 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2294 pf->max_nb_vmdq_vsi = 1;
2296 * If VMDQ available, assume a single VSI can be created. Will adjust
2299 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2300 sum_vsis += pf->max_nb_vmdq_vsi;
2302 pf->vmdq_nb_qps = 0;
2303 pf->max_nb_vmdq_vsi = 0;
2305 pf->nb_cfg_vmdq_vsi = 0;
2307 if (hw->func_caps.fd) {
2308 pf->flags |= I40E_FLAG_FDIR;
2309 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2311 * Each flow director consumes one VSI and one queue,
2312 * but can't calculate out predictably here.
2316 if (sum_vsis > pf->max_num_vsi ||
2317 sum_queues > hw->func_caps.num_rx_qp) {
2318 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2319 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2320 pf->max_num_vsi, sum_vsis);
2321 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2322 hw->func_caps.num_rx_qp, sum_queues);
2326 /* Adjust VMDQ setting to support as many VMs as possible */
2327 if (pf->flags & I40E_FLAG_VMDQ) {
2328 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2330 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2331 pf->max_num_vsi - sum_vsis);
2333 /* Limit the max VMDQ number that rte_ether that can support */
2334 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2337 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2338 pf->max_nb_vmdq_vsi);
2339 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2342 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2344 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2345 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2346 sum_vsis, hw->func_caps.num_msix_vectors);
2349 return I40E_SUCCESS;
2353 i40e_pf_get_switch_config(struct i40e_pf *pf)
2355 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2356 struct i40e_aqc_get_switch_config_resp *switch_config;
2357 struct i40e_aqc_switch_config_element_resp *element;
2358 uint16_t start_seid = 0, num_reported;
2361 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2362 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2363 if (!switch_config) {
2364 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2368 /* Get the switch configurations */
2369 ret = i40e_aq_get_switch_config(hw, switch_config,
2370 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2371 if (ret != I40E_SUCCESS) {
2372 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2375 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2376 if (num_reported != 1) { /* The number should be 1 */
2377 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2381 /* Parse the switch configuration elements */
2382 element = &(switch_config->element[0]);
2383 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2384 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2385 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2387 PMD_DRV_LOG(INFO, "Unknown element type");
2390 rte_free(switch_config);
2396 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2399 struct pool_entry *entry;
2401 if (pool == NULL || num == 0)
2404 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2405 if (entry == NULL) {
2406 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2410 /* queue heap initialize */
2411 pool->num_free = num;
2412 pool->num_alloc = 0;
2414 LIST_INIT(&pool->alloc_list);
2415 LIST_INIT(&pool->free_list);
2417 /* Initialize element */
2421 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2426 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2428 struct pool_entry *entry;
2433 LIST_FOREACH(entry, &pool->alloc_list, next) {
2434 LIST_REMOVE(entry, next);
2438 LIST_FOREACH(entry, &pool->free_list, next) {
2439 LIST_REMOVE(entry, next);
2444 pool->num_alloc = 0;
2446 LIST_INIT(&pool->alloc_list);
2447 LIST_INIT(&pool->free_list);
2451 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2454 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2455 uint32_t pool_offset;
2459 PMD_DRV_LOG(ERR, "Invalid parameter");
2463 pool_offset = base - pool->base;
2464 /* Lookup in alloc list */
2465 LIST_FOREACH(entry, &pool->alloc_list, next) {
2466 if (entry->base == pool_offset) {
2467 valid_entry = entry;
2468 LIST_REMOVE(entry, next);
2473 /* Not find, return */
2474 if (valid_entry == NULL) {
2475 PMD_DRV_LOG(ERR, "Failed to find entry");
2480 * Found it, move it to free list and try to merge.
2481 * In order to make merge easier, always sort it by qbase.
2482 * Find adjacent prev and last entries.
2485 LIST_FOREACH(entry, &pool->free_list, next) {
2486 if (entry->base > valid_entry->base) {
2494 /* Try to merge with next one*/
2496 /* Merge with next one */
2497 if (valid_entry->base + valid_entry->len == next->base) {
2498 next->base = valid_entry->base;
2499 next->len += valid_entry->len;
2500 rte_free(valid_entry);
2507 /* Merge with previous one */
2508 if (prev->base + prev->len == valid_entry->base) {
2509 prev->len += valid_entry->len;
2510 /* If it merge with next one, remove next node */
2512 LIST_REMOVE(valid_entry, next);
2513 rte_free(valid_entry);
2515 rte_free(valid_entry);
2521 /* Not find any entry to merge, insert */
2524 LIST_INSERT_AFTER(prev, valid_entry, next);
2525 else if (next != NULL)
2526 LIST_INSERT_BEFORE(next, valid_entry, next);
2527 else /* It's empty list, insert to head */
2528 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2531 pool->num_free += valid_entry->len;
2532 pool->num_alloc -= valid_entry->len;
2538 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2541 struct pool_entry *entry, *valid_entry;
2543 if (pool == NULL || num == 0) {
2544 PMD_DRV_LOG(ERR, "Invalid parameter");
2548 if (pool->num_free < num) {
2549 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2550 num, pool->num_free);
2555 /* Lookup in free list and find most fit one */
2556 LIST_FOREACH(entry, &pool->free_list, next) {
2557 if (entry->len >= num) {
2559 if (entry->len == num) {
2560 valid_entry = entry;
2563 if (valid_entry == NULL || valid_entry->len > entry->len)
2564 valid_entry = entry;
2568 /* Not find one to satisfy the request, return */
2569 if (valid_entry == NULL) {
2570 PMD_DRV_LOG(ERR, "No valid entry found");
2574 * The entry have equal queue number as requested,
2575 * remove it from alloc_list.
2577 if (valid_entry->len == num) {
2578 LIST_REMOVE(valid_entry, next);
2581 * The entry have more numbers than requested,
2582 * create a new entry for alloc_list and minus its
2583 * queue base and number in free_list.
2585 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2586 if (entry == NULL) {
2587 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2591 entry->base = valid_entry->base;
2593 valid_entry->base += num;
2594 valid_entry->len -= num;
2595 valid_entry = entry;
2598 /* Insert it into alloc list, not sorted */
2599 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2601 pool->num_free -= valid_entry->len;
2602 pool->num_alloc += valid_entry->len;
2604 return (valid_entry->base + pool->base);
2608 * bitmap_is_subset - Check whether src2 is subset of src1
2611 bitmap_is_subset(uint8_t src1, uint8_t src2)
2613 return !((src1 ^ src2) & src2);
2617 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2619 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2621 /* If DCB is not supported, only default TC is supported */
2622 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2623 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2627 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2628 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2629 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2633 return I40E_SUCCESS;
2637 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2638 struct i40e_vsi_vlan_pvid_info *info)
2641 struct i40e_vsi_context ctxt;
2642 uint8_t vlan_flags = 0;
2645 if (vsi == NULL || info == NULL) {
2646 PMD_DRV_LOG(ERR, "invalid parameters");
2647 return I40E_ERR_PARAM;
2651 vsi->info.pvid = info->config.pvid;
2653 * If insert pvid is enabled, only tagged pkts are
2654 * allowed to be sent out.
2656 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2657 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2660 if (info->config.reject.tagged == 0)
2661 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2663 if (info->config.reject.untagged == 0)
2664 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2666 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2667 I40E_AQ_VSI_PVLAN_MODE_MASK);
2668 vsi->info.port_vlan_flags |= vlan_flags;
2669 vsi->info.valid_sections =
2670 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2671 memset(&ctxt, 0, sizeof(ctxt));
2672 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2673 ctxt.seid = vsi->seid;
2675 hw = I40E_VSI_TO_HW(vsi);
2676 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2677 if (ret != I40E_SUCCESS)
2678 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2684 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2686 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2688 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2690 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2691 if (ret != I40E_SUCCESS)
2695 PMD_DRV_LOG(ERR, "seid not valid");
2699 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2700 tc_bw_data.tc_valid_bits = enabled_tcmap;
2701 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2702 tc_bw_data.tc_bw_credits[i] =
2703 (enabled_tcmap & (1 << i)) ? 1 : 0;
2705 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2706 if (ret != I40E_SUCCESS) {
2707 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2711 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2712 sizeof(vsi->info.qs_handle));
2713 return I40E_SUCCESS;
2717 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2718 struct i40e_aqc_vsi_properties_data *info,
2719 uint8_t enabled_tcmap)
2721 int ret, total_tc = 0, i;
2722 uint16_t qpnum_per_tc, bsf, qp_idx;
2724 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2725 if (ret != I40E_SUCCESS)
2728 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2729 if (enabled_tcmap & (1 << i))
2731 vsi->enabled_tc = enabled_tcmap;
2733 /* Number of queues per enabled TC */
2734 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2735 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2736 bsf = rte_bsf32(qpnum_per_tc);
2738 /* Adjust the queue number to actual queues that can be applied */
2739 vsi->nb_qps = qpnum_per_tc * total_tc;
2742 * Configure TC and queue mapping parameters, for enabled TC,
2743 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2744 * default queue will serve it.
2747 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2748 if (vsi->enabled_tc & (1 << i)) {
2749 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2750 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2751 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2752 qp_idx += qpnum_per_tc;
2754 info->tc_mapping[i] = 0;
2757 /* Associate queue number with VSI */
2758 if (vsi->type == I40E_VSI_SRIOV) {
2759 info->mapping_flags |=
2760 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2761 for (i = 0; i < vsi->nb_qps; i++)
2762 info->queue_mapping[i] =
2763 rte_cpu_to_le_16(vsi->base_queue + i);
2765 info->mapping_flags |=
2766 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2767 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2769 info->valid_sections |=
2770 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2772 return I40E_SUCCESS;
2776 i40e_veb_release(struct i40e_veb *veb)
2778 struct i40e_vsi *vsi;
2781 if (veb == NULL || veb->associate_vsi == NULL)
2784 if (!TAILQ_EMPTY(&veb->head)) {
2785 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2789 vsi = veb->associate_vsi;
2790 hw = I40E_VSI_TO_HW(vsi);
2792 vsi->uplink_seid = veb->uplink_seid;
2793 i40e_aq_delete_element(hw, veb->seid, NULL);
2796 return I40E_SUCCESS;
2800 static struct i40e_veb *
2801 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2803 struct i40e_veb *veb;
2807 if (NULL == pf || vsi == NULL) {
2808 PMD_DRV_LOG(ERR, "veb setup failed, "
2809 "associated VSI shouldn't null");
2812 hw = I40E_PF_TO_HW(pf);
2814 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2816 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2820 veb->associate_vsi = vsi;
2821 TAILQ_INIT(&veb->head);
2822 veb->uplink_seid = vsi->uplink_seid;
2824 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2825 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2827 if (ret != I40E_SUCCESS) {
2828 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2829 hw->aq.asq_last_status);
2833 /* get statistics index */
2834 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2835 &veb->stats_idx, NULL, NULL, NULL);
2836 if (ret != I40E_SUCCESS) {
2837 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2838 hw->aq.asq_last_status);
2842 /* Get VEB bandwidth, to be implemented */
2843 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2844 vsi->uplink_seid = veb->seid;
2853 i40e_vsi_release(struct i40e_vsi *vsi)
2857 struct i40e_vsi_list *vsi_list;
2859 struct i40e_mac_filter *f;
2862 return I40E_SUCCESS;
2864 pf = I40E_VSI_TO_PF(vsi);
2865 hw = I40E_VSI_TO_HW(vsi);
2867 /* VSI has child to attach, release child first */
2869 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2870 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2872 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2874 i40e_veb_release(vsi->veb);
2877 /* Remove all macvlan filters of the VSI */
2878 i40e_vsi_remove_all_macvlan_filter(vsi);
2879 TAILQ_FOREACH(f, &vsi->mac_list, next)
2882 if (vsi->type != I40E_VSI_MAIN) {
2883 /* Remove vsi from parent's sibling list */
2884 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2885 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2886 return I40E_ERR_PARAM;
2888 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2889 &vsi->sib_vsi_list, list);
2891 /* Remove all switch element of the VSI */
2892 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2893 if (ret != I40E_SUCCESS)
2894 PMD_DRV_LOG(ERR, "Failed to delete element");
2896 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2898 if (vsi->type != I40E_VSI_SRIOV)
2899 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2902 return I40E_SUCCESS;
2906 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2908 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2909 struct i40e_aqc_remove_macvlan_element_data def_filter;
2910 struct i40e_mac_filter_info filter;
2913 if (vsi->type != I40E_VSI_MAIN)
2914 return I40E_ERR_CONFIG;
2915 memset(&def_filter, 0, sizeof(def_filter));
2916 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2918 def_filter.vlan_tag = 0;
2919 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2920 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2921 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2922 if (ret != I40E_SUCCESS) {
2923 struct i40e_mac_filter *f;
2924 struct ether_addr *mac;
2926 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2928 /* It needs to add the permanent mac into mac list */
2929 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2931 PMD_DRV_LOG(ERR, "failed to allocate memory");
2932 return I40E_ERR_NO_MEMORY;
2934 mac = &f->mac_info.mac_addr;
2935 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2937 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2938 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2943 (void)rte_memcpy(&filter.mac_addr,
2944 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2945 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2946 return i40e_vsi_add_mac(vsi, &filter);
2950 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2952 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2953 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2954 struct i40e_hw *hw = &vsi->adapter->hw;
2958 memset(&bw_config, 0, sizeof(bw_config));
2959 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2960 if (ret != I40E_SUCCESS) {
2961 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2962 hw->aq.asq_last_status);
2966 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2967 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2968 &ets_sla_config, NULL);
2969 if (ret != I40E_SUCCESS) {
2970 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2971 "configuration %u", hw->aq.asq_last_status);
2975 /* Not store the info yet, just print out */
2976 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2977 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2978 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2979 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2980 ets_sla_config.share_credits[i]);
2981 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2982 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2983 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2984 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2993 i40e_vsi_setup(struct i40e_pf *pf,
2994 enum i40e_vsi_type type,
2995 struct i40e_vsi *uplink_vsi,
2996 uint16_t user_param)
2998 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2999 struct i40e_vsi *vsi;
3000 struct i40e_mac_filter_info filter;
3002 struct i40e_vsi_context ctxt;
3003 struct ether_addr broadcast =
3004 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3006 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3007 PMD_DRV_LOG(ERR, "VSI setup failed, "
3008 "VSI link shouldn't be NULL");
3012 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3013 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3014 "uplink VSI should be NULL");
3018 /* If uplink vsi didn't setup VEB, create one first */
3019 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3020 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3022 if (NULL == uplink_vsi->veb) {
3023 PMD_DRV_LOG(ERR, "VEB setup failed");
3028 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3030 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3033 TAILQ_INIT(&vsi->mac_list);
3035 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3036 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3037 vsi->parent_vsi = uplink_vsi;
3038 vsi->user_param = user_param;
3039 /* Allocate queues */
3040 switch (vsi->type) {
3041 case I40E_VSI_MAIN :
3042 vsi->nb_qps = pf->lan_nb_qps;
3044 case I40E_VSI_SRIOV :
3045 vsi->nb_qps = pf->vf_nb_qps;
3047 case I40E_VSI_VMDQ2:
3048 vsi->nb_qps = pf->vmdq_nb_qps;
3051 vsi->nb_qps = pf->fdir_nb_qps;
3057 * The filter status descriptor is reported in rx queue 0,
3058 * while the tx queue for fdir filter programming has no
3059 * such constraints, can be non-zero queues.
3060 * To simplify it, choose FDIR vsi use queue 0 pair.
3061 * To make sure it will use queue 0 pair, queue allocation
3062 * need be done before this function is called
3064 if (type != I40E_VSI_FDIR) {
3065 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3067 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3071 vsi->base_queue = ret;
3073 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3075 /* VF has MSIX interrupt in VF range, don't allocate here */
3076 if (type != I40E_VSI_SRIOV) {
3077 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3079 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3080 goto fail_queue_alloc;
3082 vsi->msix_intr = ret;
3086 if (type == I40E_VSI_MAIN) {
3087 /* For main VSI, no need to add since it's default one */
3088 vsi->uplink_seid = pf->mac_seid;
3089 vsi->seid = pf->main_vsi_seid;
3090 /* Bind queues with specific MSIX interrupt */
3092 * Needs 2 interrupt at least, one for misc cause which will
3093 * enabled from OS side, Another for queues binding the
3094 * interrupt from device side only.
3097 /* Get default VSI parameters from hardware */
3098 memset(&ctxt, 0, sizeof(ctxt));
3099 ctxt.seid = vsi->seid;
3100 ctxt.pf_num = hw->pf_id;
3101 ctxt.uplink_seid = vsi->uplink_seid;
3103 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3104 if (ret != I40E_SUCCESS) {
3105 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3106 goto fail_msix_alloc;
3108 (void)rte_memcpy(&vsi->info, &ctxt.info,
3109 sizeof(struct i40e_aqc_vsi_properties_data));
3110 vsi->vsi_id = ctxt.vsi_number;
3111 vsi->info.valid_sections = 0;
3113 /* Configure tc, enabled TC0 only */
3114 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3116 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3117 goto fail_msix_alloc;
3120 /* TC, queue mapping */
3121 memset(&ctxt, 0, sizeof(ctxt));
3122 vsi->info.valid_sections |=
3123 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3124 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3125 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3126 (void)rte_memcpy(&ctxt.info, &vsi->info,
3127 sizeof(struct i40e_aqc_vsi_properties_data));
3128 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3129 I40E_DEFAULT_TCMAP);
3130 if (ret != I40E_SUCCESS) {
3131 PMD_DRV_LOG(ERR, "Failed to configure "
3132 "TC queue mapping");
3133 goto fail_msix_alloc;
3135 ctxt.seid = vsi->seid;
3136 ctxt.pf_num = hw->pf_id;
3137 ctxt.uplink_seid = vsi->uplink_seid;
3140 /* Update VSI parameters */
3141 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3142 if (ret != I40E_SUCCESS) {
3143 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3144 goto fail_msix_alloc;
3147 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3148 sizeof(vsi->info.tc_mapping));
3149 (void)rte_memcpy(&vsi->info.queue_mapping,
3150 &ctxt.info.queue_mapping,
3151 sizeof(vsi->info.queue_mapping));
3152 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3153 vsi->info.valid_sections = 0;
3155 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3159 * Updating default filter settings are necessary to prevent
3160 * reception of tagged packets.
3161 * Some old firmware configurations load a default macvlan
3162 * filter which accepts both tagged and untagged packets.
3163 * The updating is to use a normal filter instead if needed.
3164 * For NVM 4.2.2 or after, the updating is not needed anymore.
3165 * The firmware with correct configurations load the default
3166 * macvlan filter which is expected and cannot be removed.
3168 i40e_update_default_filter_setting(vsi);
3169 i40e_config_qinq(hw, vsi);
3170 } else if (type == I40E_VSI_SRIOV) {
3171 memset(&ctxt, 0, sizeof(ctxt));
3173 * For other VSI, the uplink_seid equals to uplink VSI's
3174 * uplink_seid since they share same VEB
3176 vsi->uplink_seid = uplink_vsi->uplink_seid;
3177 ctxt.pf_num = hw->pf_id;
3178 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3179 ctxt.uplink_seid = vsi->uplink_seid;
3180 ctxt.connection_type = 0x1;
3181 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3184 * Do not configure switch ID to enable VEB switch by
3185 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3186 * if the source mac address of packet sent from VF is not
3187 * listed in the VEB's mac table, the VEB will switch the
3188 * packet back to the VF. Need to enable it when HW issue
3192 /* Configure port/vlan */
3193 ctxt.info.valid_sections |=
3194 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3195 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3196 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3197 I40E_DEFAULT_TCMAP);
3198 if (ret != I40E_SUCCESS) {
3199 PMD_DRV_LOG(ERR, "Failed to configure "
3200 "TC queue mapping");
3201 goto fail_msix_alloc;
3203 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3204 ctxt.info.valid_sections |=
3205 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3207 * Since VSI is not created yet, only configure parameter,
3208 * will add vsi below.
3211 i40e_config_qinq(hw, vsi);
3212 } else if (type == I40E_VSI_VMDQ2) {
3213 memset(&ctxt, 0, sizeof(ctxt));
3215 * For other VSI, the uplink_seid equals to uplink VSI's
3216 * uplink_seid since they share same VEB
3218 vsi->uplink_seid = uplink_vsi->uplink_seid;
3219 ctxt.pf_num = hw->pf_id;
3221 ctxt.uplink_seid = vsi->uplink_seid;
3222 ctxt.connection_type = 0x1;
3223 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3225 ctxt.info.valid_sections |=
3226 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3227 /* user_param carries flag to enable loop back */
3229 ctxt.info.switch_id =
3230 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3231 ctxt.info.switch_id |=
3232 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3235 /* Configure port/vlan */
3236 ctxt.info.valid_sections |=
3237 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3238 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3239 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3240 I40E_DEFAULT_TCMAP);
3241 if (ret != I40E_SUCCESS) {
3242 PMD_DRV_LOG(ERR, "Failed to configure "
3243 "TC queue mapping");
3244 goto fail_msix_alloc;
3246 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3247 ctxt.info.valid_sections |=
3248 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3249 } else if (type == I40E_VSI_FDIR) {
3250 memset(&ctxt, 0, sizeof(ctxt));
3251 vsi->uplink_seid = uplink_vsi->uplink_seid;
3252 ctxt.pf_num = hw->pf_id;
3254 ctxt.uplink_seid = vsi->uplink_seid;
3255 ctxt.connection_type = 0x1; /* regular data port */
3256 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3257 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3258 I40E_DEFAULT_TCMAP);
3259 if (ret != I40E_SUCCESS) {
3260 PMD_DRV_LOG(ERR, "Failed to configure "
3261 "TC queue mapping.");
3262 goto fail_msix_alloc;
3264 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3265 ctxt.info.valid_sections |=
3266 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3268 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3269 goto fail_msix_alloc;
3272 if (vsi->type != I40E_VSI_MAIN) {
3273 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3274 if (ret != I40E_SUCCESS) {
3275 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3276 hw->aq.asq_last_status);
3277 goto fail_msix_alloc;
3279 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3280 vsi->info.valid_sections = 0;
3281 vsi->seid = ctxt.seid;
3282 vsi->vsi_id = ctxt.vsi_number;
3283 vsi->sib_vsi_list.vsi = vsi;
3284 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3285 &vsi->sib_vsi_list, list);
3288 /* MAC/VLAN configuration */
3289 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3290 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3292 ret = i40e_vsi_add_mac(vsi, &filter);
3293 if (ret != I40E_SUCCESS) {
3294 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3295 goto fail_msix_alloc;
3298 /* Get VSI BW information */
3299 i40e_vsi_dump_bw_config(vsi);
3302 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3304 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3310 /* Configure vlan stripping on or off */
3312 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3314 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3315 struct i40e_vsi_context ctxt;
3317 int ret = I40E_SUCCESS;
3319 /* Check if it has been already on or off */
3320 if (vsi->info.valid_sections &
3321 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3323 if ((vsi->info.port_vlan_flags &
3324 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3325 return 0; /* already on */
3327 if ((vsi->info.port_vlan_flags &
3328 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3329 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3330 return 0; /* already off */
3335 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3337 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3338 vsi->info.valid_sections =
3339 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3340 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3341 vsi->info.port_vlan_flags |= vlan_flags;
3342 ctxt.seid = vsi->seid;
3343 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3344 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3346 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3347 on ? "enable" : "disable");
3353 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3355 struct rte_eth_dev_data *data = dev->data;
3358 /* Apply vlan offload setting */
3359 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3361 /* Apply double-vlan setting, not implemented yet */
3363 /* Apply pvid setting */
3364 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3365 data->dev_conf.txmode.hw_vlan_insert_pvid);
3367 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3373 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3375 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3377 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3381 i40e_update_flow_control(struct i40e_hw *hw)
3383 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3384 struct i40e_link_status link_status;
3385 uint32_t rxfc = 0, txfc = 0, reg;
3389 memset(&link_status, 0, sizeof(link_status));
3390 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3391 if (ret != I40E_SUCCESS) {
3392 PMD_DRV_LOG(ERR, "Failed to get link status information");
3393 goto write_reg; /* Disable flow control */
3396 an_info = hw->phy.link_info.an_info;
3397 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3398 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3399 ret = I40E_ERR_NOT_READY;
3400 goto write_reg; /* Disable flow control */
3403 * If link auto negotiation is enabled, flow control needs to
3404 * be configured according to it
3406 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3407 case I40E_LINK_PAUSE_RXTX:
3410 hw->fc.current_mode = I40E_FC_FULL;
3412 case I40E_AQ_LINK_PAUSE_RX:
3414 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3416 case I40E_AQ_LINK_PAUSE_TX:
3418 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3421 hw->fc.current_mode = I40E_FC_NONE;
3426 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3427 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3428 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3429 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3430 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3431 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3438 i40e_pf_setup(struct i40e_pf *pf)
3440 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3441 struct i40e_filter_control_settings settings;
3442 struct i40e_vsi *vsi;
3445 /* Clear all stats counters */
3446 pf->offset_loaded = FALSE;
3447 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3448 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3450 ret = i40e_pf_get_switch_config(pf);
3451 if (ret != I40E_SUCCESS) {
3452 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3455 if (pf->flags & I40E_FLAG_FDIR) {
3456 /* make queue allocated first, let FDIR use queue pair 0*/
3457 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3458 if (ret != I40E_FDIR_QUEUE_ID) {
3459 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3461 pf->flags &= ~I40E_FLAG_FDIR;
3464 /* main VSI setup */
3465 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3467 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3468 return I40E_ERR_NOT_READY;
3472 /* Configure filter control */
3473 memset(&settings, 0, sizeof(settings));
3474 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3475 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3476 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3477 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3479 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3480 hw->func_caps.rss_table_size);
3481 return I40E_ERR_PARAM;
3483 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3484 "size: %u\n", hw->func_caps.rss_table_size);
3485 pf->hash_lut_size = hw->func_caps.rss_table_size;
3487 /* Enable ethtype and macvlan filters */
3488 settings.enable_ethtype = TRUE;
3489 settings.enable_macvlan = TRUE;
3490 ret = i40e_set_filter_control(hw, &settings);
3492 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3495 /* Update flow control according to the auto negotiation */
3496 i40e_update_flow_control(hw);
3498 return I40E_SUCCESS;
3502 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3508 * Set or clear TX Queue Disable flags,
3509 * which is required by hardware.
3511 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3512 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3514 /* Wait until the request is finished */
3515 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3516 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3517 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3518 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3519 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3525 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3526 return I40E_SUCCESS; /* already on, skip next steps */
3528 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3529 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3531 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3532 return I40E_SUCCESS; /* already off, skip next steps */
3533 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3535 /* Write the register */
3536 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3537 /* Check the result */
3538 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3539 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3540 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3542 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3543 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3546 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3547 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3551 /* Check if it is timeout */
3552 if (j >= I40E_CHK_Q_ENA_COUNT) {
3553 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3554 (on ? "enable" : "disable"), q_idx);
3555 return I40E_ERR_TIMEOUT;
3558 return I40E_SUCCESS;
3561 /* Swith on or off the tx queues */
3563 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3565 struct rte_eth_dev_data *dev_data = pf->dev_data;
3566 struct i40e_tx_queue *txq;
3567 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3571 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3572 txq = dev_data->tx_queues[i];
3573 /* Don't operate the queue if not configured or
3574 * if starting only per queue */
3575 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3578 ret = i40e_dev_tx_queue_start(dev, i);
3580 ret = i40e_dev_tx_queue_stop(dev, i);
3581 if ( ret != I40E_SUCCESS)
3585 return I40E_SUCCESS;
3589 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3594 /* Wait until the request is finished */
3595 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3596 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3597 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3598 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3599 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3604 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3605 return I40E_SUCCESS; /* Already on, skip next steps */
3606 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3608 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3609 return I40E_SUCCESS; /* Already off, skip next steps */
3610 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3613 /* Write the register */
3614 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3615 /* Check the result */
3616 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3617 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3618 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3620 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3621 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3624 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3625 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3630 /* Check if it is timeout */
3631 if (j >= I40E_CHK_Q_ENA_COUNT) {
3632 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3633 (on ? "enable" : "disable"), q_idx);
3634 return I40E_ERR_TIMEOUT;
3637 return I40E_SUCCESS;
3639 /* Switch on or off the rx queues */
3641 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3643 struct rte_eth_dev_data *dev_data = pf->dev_data;
3644 struct i40e_rx_queue *rxq;
3645 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3649 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3650 rxq = dev_data->rx_queues[i];
3651 /* Don't operate the queue if not configured or
3652 * if starting only per queue */
3653 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3656 ret = i40e_dev_rx_queue_start(dev, i);
3658 ret = i40e_dev_rx_queue_stop(dev, i);
3659 if (ret != I40E_SUCCESS)
3663 return I40E_SUCCESS;
3666 /* Switch on or off all the rx/tx queues */
3668 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3673 /* enable rx queues before enabling tx queues */
3674 ret = i40e_dev_switch_rx_queues(pf, on);
3676 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3679 ret = i40e_dev_switch_tx_queues(pf, on);
3681 /* Stop tx queues before stopping rx queues */
3682 ret = i40e_dev_switch_tx_queues(pf, on);
3684 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3687 ret = i40e_dev_switch_rx_queues(pf, on);
3693 /* Initialize VSI for TX */
3695 i40e_dev_tx_init(struct i40e_pf *pf)
3697 struct rte_eth_dev_data *data = pf->dev_data;
3699 uint32_t ret = I40E_SUCCESS;
3700 struct i40e_tx_queue *txq;
3702 for (i = 0; i < data->nb_tx_queues; i++) {
3703 txq = data->tx_queues[i];
3704 if (!txq || !txq->q_set)
3706 ret = i40e_tx_queue_init(txq);
3707 if (ret != I40E_SUCCESS)
3714 /* Initialize VSI for RX */
3716 i40e_dev_rx_init(struct i40e_pf *pf)
3718 struct rte_eth_dev_data *data = pf->dev_data;
3719 int ret = I40E_SUCCESS;
3721 struct i40e_rx_queue *rxq;
3723 i40e_pf_config_mq_rx(pf);
3724 for (i = 0; i < data->nb_rx_queues; i++) {
3725 rxq = data->rx_queues[i];
3726 if (!rxq || !rxq->q_set)
3729 ret = i40e_rx_queue_init(rxq);
3730 if (ret != I40E_SUCCESS) {
3731 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3741 i40e_dev_rxtx_init(struct i40e_pf *pf)
3745 err = i40e_dev_tx_init(pf);
3747 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3750 err = i40e_dev_rx_init(pf);
3752 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3760 i40e_vmdq_setup(struct rte_eth_dev *dev)
3762 struct rte_eth_conf *conf = &dev->data->dev_conf;
3763 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764 int i, err, conf_vsis, j, loop;
3765 struct i40e_vsi *vsi;
3766 struct i40e_vmdq_info *vmdq_info;
3767 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3768 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3771 * Disable interrupt to avoid message from VF. Furthermore, it will
3772 * avoid race condition in VSI creation/destroy.
3774 i40e_pf_disable_irq0(hw);
3776 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3777 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3781 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3782 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3783 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3784 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3785 pf->max_nb_vmdq_vsi);
3789 if (pf->vmdq != NULL) {
3790 PMD_INIT_LOG(INFO, "VMDQ already configured");
3794 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3795 sizeof(*vmdq_info) * conf_vsis, 0);
3797 if (pf->vmdq == NULL) {
3798 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3802 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3804 /* Create VMDQ VSI */
3805 for (i = 0; i < conf_vsis; i++) {
3806 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3807 vmdq_conf->enable_loop_back);
3809 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3813 vmdq_info = &pf->vmdq[i];
3815 vmdq_info->vsi = vsi;
3817 pf->nb_cfg_vmdq_vsi = conf_vsis;
3819 /* Configure Vlan */
3820 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3821 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3822 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3823 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3824 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3825 vmdq_conf->pool_map[i].vlan_id, j);
3827 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3828 vmdq_conf->pool_map[i].vlan_id);
3830 PMD_INIT_LOG(ERR, "Failed to add vlan");
3838 i40e_pf_enable_irq0(hw);
3843 for (i = 0; i < conf_vsis; i++)
3844 if (pf->vmdq[i].vsi == NULL)
3847 i40e_vsi_release(pf->vmdq[i].vsi);
3851 i40e_pf_enable_irq0(hw);
3856 i40e_stat_update_32(struct i40e_hw *hw,
3864 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3868 if (new_data >= *offset)
3869 *stat = (uint64_t)(new_data - *offset);
3871 *stat = (uint64_t)((new_data +
3872 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3876 i40e_stat_update_48(struct i40e_hw *hw,
3885 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3886 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3887 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3892 if (new_data >= *offset)
3893 *stat = new_data - *offset;
3895 *stat = (uint64_t)((new_data +
3896 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3898 *stat &= I40E_48_BIT_MASK;
3903 i40e_pf_disable_irq0(struct i40e_hw *hw)
3905 /* Disable all interrupt types */
3906 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3907 I40E_WRITE_FLUSH(hw);
3912 i40e_pf_enable_irq0(struct i40e_hw *hw)
3914 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3915 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3916 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3917 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3918 I40E_WRITE_FLUSH(hw);
3922 i40e_pf_config_irq0(struct i40e_hw *hw)
3924 /* read pending request and disable first */
3925 i40e_pf_disable_irq0(hw);
3926 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3927 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3928 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3930 /* Link no queues with irq0 */
3931 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3932 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3936 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3942 uint32_t index, offset, val;
3947 * Try to find which VF trigger a reset, use absolute VF id to access
3948 * since the reg is global register.
3950 for (i = 0; i < pf->vf_num; i++) {
3951 abs_vf_id = hw->func_caps.vf_base_id + i;
3952 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3953 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3954 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3955 /* VFR event occured */
3956 if (val & (0x1 << offset)) {
3959 /* Clear the event first */
3960 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3962 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3964 * Only notify a VF reset event occured,
3965 * don't trigger another SW reset
3967 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3968 if (ret != I40E_SUCCESS)
3969 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3975 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3977 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3978 struct i40e_arq_event_info info;
3979 uint16_t pending, opcode;
3982 info.buf_len = I40E_AQ_BUF_SZ;
3983 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3984 if (!info.msg_buf) {
3985 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3991 ret = i40e_clean_arq_element(hw, &info, &pending);
3993 if (ret != I40E_SUCCESS) {
3994 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3995 "aq_err: %u", hw->aq.asq_last_status);
3998 opcode = rte_le_to_cpu_16(info.desc.opcode);
4001 case i40e_aqc_opc_send_msg_to_pf:
4002 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4003 i40e_pf_host_handle_vf_msg(dev,
4004 rte_le_to_cpu_16(info.desc.retval),
4005 rte_le_to_cpu_32(info.desc.cookie_high),
4006 rte_le_to_cpu_32(info.desc.cookie_low),
4011 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4016 rte_free(info.msg_buf);
4020 * Interrupt handler is registered as the alarm callback for handling LSC
4021 * interrupt in a definite of time, in order to wait the NIC into a stable
4022 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4023 * no need for link down interrupt.
4026 i40e_dev_interrupt_delayed_handler(void *param)
4028 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4029 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032 /* read interrupt causes again */
4033 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4035 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4036 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4037 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4038 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4039 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4040 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4041 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4042 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4043 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4044 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4045 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4047 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4048 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4049 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4050 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4051 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4053 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4054 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4055 i40e_dev_handle_vfr_event(dev);
4057 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4058 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4059 i40e_dev_handle_aq_msg(dev);
4062 /* handle the link up interrupt in an alarm callback */
4063 i40e_dev_link_update(dev, 0);
4064 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4066 i40e_pf_enable_irq0(hw);
4067 rte_intr_enable(&(dev->pci_dev->intr_handle));
4071 * Interrupt handler triggered by NIC for handling
4072 * specific interrupt.
4075 * Pointer to interrupt handle.
4077 * The address of parameter (struct rte_eth_dev *) regsitered before.
4083 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4086 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4087 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4090 /* Disable interrupt */
4091 i40e_pf_disable_irq0(hw);
4093 /* read out interrupt causes */
4094 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4096 /* No interrupt event indicated */
4097 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4098 PMD_DRV_LOG(INFO, "No interrupt event");
4101 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4102 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4103 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4104 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4105 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4106 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4107 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4108 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4109 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4110 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4111 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4112 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4113 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4114 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4115 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4116 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4118 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4119 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4120 i40e_dev_handle_vfr_event(dev);
4122 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4123 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4124 i40e_dev_handle_aq_msg(dev);
4127 /* Link Status Change interrupt */
4128 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4129 #define I40E_US_PER_SECOND 1000000
4130 struct rte_eth_link link;
4132 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4133 memset(&link, 0, sizeof(link));
4134 rte_i40e_dev_atomic_read_link_status(dev, &link);
4135 i40e_dev_link_update(dev, 0);
4138 * For link up interrupt, it needs to wait 1 second to let the
4139 * hardware be a stable state. Otherwise several consecutive
4140 * interrupts can be observed.
4141 * For link down interrupt, no need to wait.
4143 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4144 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4147 _rte_eth_dev_callback_process(dev,
4148 RTE_ETH_EVENT_INTR_LSC);
4152 /* Enable interrupt */
4153 i40e_pf_enable_irq0(hw);
4154 rte_intr_enable(&(dev->pci_dev->intr_handle));
4158 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4159 struct i40e_macvlan_filter *filter,
4162 int ele_num, ele_buff_size;
4163 int num, actual_num, i;
4165 int ret = I40E_SUCCESS;
4166 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4167 struct i40e_aqc_add_macvlan_element_data *req_list;
4169 if (filter == NULL || total == 0)
4170 return I40E_ERR_PARAM;
4171 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4172 ele_buff_size = hw->aq.asq_buf_size;
4174 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4175 if (req_list == NULL) {
4176 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4177 return I40E_ERR_NO_MEMORY;
4182 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4183 memset(req_list, 0, ele_buff_size);
4185 for (i = 0; i < actual_num; i++) {
4186 (void)rte_memcpy(req_list[i].mac_addr,
4187 &filter[num + i].macaddr, ETH_ADDR_LEN);
4188 req_list[i].vlan_tag =
4189 rte_cpu_to_le_16(filter[num + i].vlan_id);
4191 switch (filter[num + i].filter_type) {
4192 case RTE_MAC_PERFECT_MATCH:
4193 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4194 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4196 case RTE_MACVLAN_PERFECT_MATCH:
4197 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4199 case RTE_MAC_HASH_MATCH:
4200 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4201 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4203 case RTE_MACVLAN_HASH_MATCH:
4204 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4207 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4208 ret = I40E_ERR_PARAM;
4212 req_list[i].queue_number = 0;
4214 req_list[i].flags = rte_cpu_to_le_16(flags);
4217 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4219 if (ret != I40E_SUCCESS) {
4220 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4224 } while (num < total);
4232 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4233 struct i40e_macvlan_filter *filter,
4236 int ele_num, ele_buff_size;
4237 int num, actual_num, i;
4239 int ret = I40E_SUCCESS;
4240 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4241 struct i40e_aqc_remove_macvlan_element_data *req_list;
4243 if (filter == NULL || total == 0)
4244 return I40E_ERR_PARAM;
4246 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4247 ele_buff_size = hw->aq.asq_buf_size;
4249 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4250 if (req_list == NULL) {
4251 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4252 return I40E_ERR_NO_MEMORY;
4257 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4258 memset(req_list, 0, ele_buff_size);
4260 for (i = 0; i < actual_num; i++) {
4261 (void)rte_memcpy(req_list[i].mac_addr,
4262 &filter[num + i].macaddr, ETH_ADDR_LEN);
4263 req_list[i].vlan_tag =
4264 rte_cpu_to_le_16(filter[num + i].vlan_id);
4266 switch (filter[num + i].filter_type) {
4267 case RTE_MAC_PERFECT_MATCH:
4268 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4269 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4271 case RTE_MACVLAN_PERFECT_MATCH:
4272 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4274 case RTE_MAC_HASH_MATCH:
4275 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4276 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4278 case RTE_MACVLAN_HASH_MATCH:
4279 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4282 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4283 ret = I40E_ERR_PARAM;
4286 req_list[i].flags = rte_cpu_to_le_16(flags);
4289 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4291 if (ret != I40E_SUCCESS) {
4292 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4296 } while (num < total);
4303 /* Find out specific MAC filter */
4304 static struct i40e_mac_filter *
4305 i40e_find_mac_filter(struct i40e_vsi *vsi,
4306 struct ether_addr *macaddr)
4308 struct i40e_mac_filter *f;
4310 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4311 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4319 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4322 uint32_t vid_idx, vid_bit;
4324 if (vlan_id > ETH_VLAN_ID_MAX)
4327 vid_idx = I40E_VFTA_IDX(vlan_id);
4328 vid_bit = I40E_VFTA_BIT(vlan_id);
4330 if (vsi->vfta[vid_idx] & vid_bit)
4337 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4338 uint16_t vlan_id, bool on)
4340 uint32_t vid_idx, vid_bit;
4342 if (vlan_id > ETH_VLAN_ID_MAX)
4345 vid_idx = I40E_VFTA_IDX(vlan_id);
4346 vid_bit = I40E_VFTA_BIT(vlan_id);
4349 vsi->vfta[vid_idx] |= vid_bit;
4351 vsi->vfta[vid_idx] &= ~vid_bit;
4355 * Find all vlan options for specific mac addr,
4356 * return with actual vlan found.
4359 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4360 struct i40e_macvlan_filter *mv_f,
4361 int num, struct ether_addr *addr)
4367 * Not to use i40e_find_vlan_filter to decrease the loop time,
4368 * although the code looks complex.
4370 if (num < vsi->vlan_num)
4371 return I40E_ERR_PARAM;
4374 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4376 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4377 if (vsi->vfta[j] & (1 << k)) {
4379 PMD_DRV_LOG(ERR, "vlan number "
4381 return I40E_ERR_PARAM;
4383 (void)rte_memcpy(&mv_f[i].macaddr,
4384 addr, ETH_ADDR_LEN);
4386 j * I40E_UINT32_BIT_SIZE + k;
4392 return I40E_SUCCESS;
4396 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4397 struct i40e_macvlan_filter *mv_f,
4402 struct i40e_mac_filter *f;
4404 if (num < vsi->mac_num)
4405 return I40E_ERR_PARAM;
4407 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4409 PMD_DRV_LOG(ERR, "buffer number not match");
4410 return I40E_ERR_PARAM;
4412 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4414 mv_f[i].vlan_id = vlan;
4415 mv_f[i].filter_type = f->mac_info.filter_type;
4419 return I40E_SUCCESS;
4423 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4426 struct i40e_mac_filter *f;
4427 struct i40e_macvlan_filter *mv_f;
4428 int ret = I40E_SUCCESS;
4430 if (vsi == NULL || vsi->mac_num == 0)
4431 return I40E_ERR_PARAM;
4433 /* Case that no vlan is set */
4434 if (vsi->vlan_num == 0)
4437 num = vsi->mac_num * vsi->vlan_num;
4439 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4441 PMD_DRV_LOG(ERR, "failed to allocate memory");
4442 return I40E_ERR_NO_MEMORY;
4446 if (vsi->vlan_num == 0) {
4447 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4448 (void)rte_memcpy(&mv_f[i].macaddr,
4449 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4450 mv_f[i].vlan_id = 0;
4454 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4455 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4456 vsi->vlan_num, &f->mac_info.mac_addr);
4457 if (ret != I40E_SUCCESS)
4463 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4471 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4473 struct i40e_macvlan_filter *mv_f;
4475 int ret = I40E_SUCCESS;
4477 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4478 return I40E_ERR_PARAM;
4480 /* If it's already set, just return */
4481 if (i40e_find_vlan_filter(vsi,vlan))
4482 return I40E_SUCCESS;
4484 mac_num = vsi->mac_num;
4487 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4488 return I40E_ERR_PARAM;
4491 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4494 PMD_DRV_LOG(ERR, "failed to allocate memory");
4495 return I40E_ERR_NO_MEMORY;
4498 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4500 if (ret != I40E_SUCCESS)
4503 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4505 if (ret != I40E_SUCCESS)
4508 i40e_set_vlan_filter(vsi, vlan, 1);
4518 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4520 struct i40e_macvlan_filter *mv_f;
4522 int ret = I40E_SUCCESS;
4525 * Vlan 0 is the generic filter for untagged packets
4526 * and can't be removed.
4528 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4529 return I40E_ERR_PARAM;
4531 /* If can't find it, just return */
4532 if (!i40e_find_vlan_filter(vsi, vlan))
4533 return I40E_ERR_PARAM;
4535 mac_num = vsi->mac_num;
4538 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4539 return I40E_ERR_PARAM;
4542 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4545 PMD_DRV_LOG(ERR, "failed to allocate memory");
4546 return I40E_ERR_NO_MEMORY;
4549 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4551 if (ret != I40E_SUCCESS)
4554 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4556 if (ret != I40E_SUCCESS)
4559 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4560 if (vsi->vlan_num == 1) {
4561 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4562 if (ret != I40E_SUCCESS)
4565 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4566 if (ret != I40E_SUCCESS)
4570 i40e_set_vlan_filter(vsi, vlan, 0);
4580 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4582 struct i40e_mac_filter *f;
4583 struct i40e_macvlan_filter *mv_f;
4584 int i, vlan_num = 0;
4585 int ret = I40E_SUCCESS;
4587 /* If it's add and we've config it, return */
4588 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4590 return I40E_SUCCESS;
4591 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4592 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4595 * If vlan_num is 0, that's the first time to add mac,
4596 * set mask for vlan_id 0.
4598 if (vsi->vlan_num == 0) {
4599 i40e_set_vlan_filter(vsi, 0, 1);
4602 vlan_num = vsi->vlan_num;
4603 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4604 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4607 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4609 PMD_DRV_LOG(ERR, "failed to allocate memory");
4610 return I40E_ERR_NO_MEMORY;
4613 for (i = 0; i < vlan_num; i++) {
4614 mv_f[i].filter_type = mac_filter->filter_type;
4615 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4619 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4620 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4621 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4622 &mac_filter->mac_addr);
4623 if (ret != I40E_SUCCESS)
4627 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4628 if (ret != I40E_SUCCESS)
4631 /* Add the mac addr into mac list */
4632 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4634 PMD_DRV_LOG(ERR, "failed to allocate memory");
4635 ret = I40E_ERR_NO_MEMORY;
4638 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4640 f->mac_info.filter_type = mac_filter->filter_type;
4641 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4652 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4654 struct i40e_mac_filter *f;
4655 struct i40e_macvlan_filter *mv_f;
4657 enum rte_mac_filter_type filter_type;
4658 int ret = I40E_SUCCESS;
4660 /* Can't find it, return an error */
4661 f = i40e_find_mac_filter(vsi, addr);
4663 return I40E_ERR_PARAM;
4665 vlan_num = vsi->vlan_num;
4666 filter_type = f->mac_info.filter_type;
4667 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4668 filter_type == RTE_MACVLAN_HASH_MATCH) {
4669 if (vlan_num == 0) {
4670 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4671 return I40E_ERR_PARAM;
4673 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4674 filter_type == RTE_MAC_HASH_MATCH)
4677 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4679 PMD_DRV_LOG(ERR, "failed to allocate memory");
4680 return I40E_ERR_NO_MEMORY;
4683 for (i = 0; i < vlan_num; i++) {
4684 mv_f[i].filter_type = filter_type;
4685 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4688 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4689 filter_type == RTE_MACVLAN_HASH_MATCH) {
4690 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4691 if (ret != I40E_SUCCESS)
4695 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4696 if (ret != I40E_SUCCESS)
4699 /* Remove the mac addr into mac list */
4700 TAILQ_REMOVE(&vsi->mac_list, f, next);
4710 /* Configure hash enable flags for RSS */
4712 i40e_config_hena(uint64_t flags)
4719 if (flags & ETH_RSS_FRAG_IPV4)
4720 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4721 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4722 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4723 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4724 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4725 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4726 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4727 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4728 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4729 if (flags & ETH_RSS_FRAG_IPV6)
4730 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4731 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4732 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4733 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4734 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4735 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4736 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4737 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4738 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4739 if (flags & ETH_RSS_L2_PAYLOAD)
4740 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4745 /* Parse the hash enable flags */
4747 i40e_parse_hena(uint64_t flags)
4749 uint64_t rss_hf = 0;
4753 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4754 rss_hf |= ETH_RSS_FRAG_IPV4;
4755 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4756 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4757 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4758 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4759 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4760 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4761 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4762 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4763 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4764 rss_hf |= ETH_RSS_FRAG_IPV6;
4765 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4766 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4767 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4768 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4769 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4770 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4771 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4772 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4773 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4774 rss_hf |= ETH_RSS_L2_PAYLOAD;
4781 i40e_pf_disable_rss(struct i40e_pf *pf)
4783 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4786 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4787 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4788 hena &= ~I40E_RSS_HENA_ALL;
4789 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4790 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4791 I40E_WRITE_FLUSH(hw);
4795 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4798 uint8_t hash_key_len;
4803 hash_key = (uint32_t *)(rss_conf->rss_key);
4804 hash_key_len = rss_conf->rss_key_len;
4805 if (hash_key != NULL && hash_key_len >=
4806 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4807 /* Fill in RSS hash key */
4808 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4809 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4812 rss_hf = rss_conf->rss_hf;
4813 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4814 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4815 hena &= ~I40E_RSS_HENA_ALL;
4816 hena |= i40e_config_hena(rss_hf);
4817 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4818 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4819 I40E_WRITE_FLUSH(hw);
4825 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4826 struct rte_eth_rss_conf *rss_conf)
4828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4832 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4833 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4834 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4835 if (rss_hf != 0) /* Enable RSS */
4837 return 0; /* Nothing to do */
4840 if (rss_hf == 0) /* Disable RSS */
4843 return i40e_hw_rss_hash_set(hw, rss_conf);
4847 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4848 struct rte_eth_rss_conf *rss_conf)
4850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4855 if (hash_key != NULL) {
4856 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4857 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4858 rss_conf->rss_key_len = i * sizeof(uint32_t);
4860 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4861 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4862 rss_conf->rss_hf = i40e_parse_hena(hena);
4868 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4870 switch (filter_type) {
4871 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4872 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4874 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4875 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4877 case RTE_TUNNEL_FILTER_IMAC_TENID:
4878 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4880 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4881 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4883 case ETH_TUNNEL_FILTER_IMAC:
4884 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4887 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4895 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4896 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4900 uint8_t tun_type = 0;
4902 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4903 struct i40e_vsi *vsi = pf->main_vsi;
4904 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4905 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4907 cld_filter = rte_zmalloc("tunnel_filter",
4908 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4911 if (NULL == cld_filter) {
4912 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4915 pfilter = cld_filter;
4917 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4918 sizeof(struct ether_addr));
4919 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4920 sizeof(struct ether_addr));
4922 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4923 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4924 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4925 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4926 &tunnel_filter->ip_addr,
4927 sizeof(pfilter->ipaddr.v4.data));
4929 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4930 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4931 &tunnel_filter->ip_addr,
4932 sizeof(pfilter->ipaddr.v6.data));
4935 /* check tunneled type */
4936 switch (tunnel_filter->tunnel_type) {
4937 case RTE_TUNNEL_TYPE_VXLAN:
4938 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4940 case RTE_TUNNEL_TYPE_NVGRE:
4941 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4944 /* Other tunnel types is not supported. */
4945 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4946 rte_free(cld_filter);
4950 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4953 rte_free(cld_filter);
4957 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4958 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4959 pfilter->tenant_id = tunnel_filter->tenant_id;
4960 pfilter->queue_number = tunnel_filter->queue_id;
4963 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4965 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4968 rte_free(cld_filter);
4973 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4977 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4978 if (pf->vxlan_ports[i] == port)
4986 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4990 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4992 idx = i40e_get_vxlan_port_idx(pf, port);
4994 /* Check if port already exists */
4996 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5000 /* Now check if there is space to add the new port */
5001 idx = i40e_get_vxlan_port_idx(pf, 0);
5003 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5004 "not adding port %d", port);
5008 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5011 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5015 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5018 /* New port: add it and mark its index in the bitmap */
5019 pf->vxlan_ports[idx] = port;
5020 pf->vxlan_bitmap |= (1 << idx);
5022 if (!(pf->flags & I40E_FLAG_VXLAN))
5023 pf->flags |= I40E_FLAG_VXLAN;
5029 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5032 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5034 if (!(pf->flags & I40E_FLAG_VXLAN)) {
5035 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5039 idx = i40e_get_vxlan_port_idx(pf, port);
5042 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5046 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5047 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5051 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5054 pf->vxlan_ports[idx] = 0;
5055 pf->vxlan_bitmap &= ~(1 << idx);
5057 if (!pf->vxlan_bitmap)
5058 pf->flags &= ~I40E_FLAG_VXLAN;
5063 /* Add UDP tunneling port */
5065 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5066 struct rte_eth_udp_tunnel *udp_tunnel)
5069 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5071 if (udp_tunnel == NULL)
5074 switch (udp_tunnel->prot_type) {
5075 case RTE_TUNNEL_TYPE_VXLAN:
5076 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5079 case RTE_TUNNEL_TYPE_GENEVE:
5080 case RTE_TUNNEL_TYPE_TEREDO:
5081 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5086 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5094 /* Remove UDP tunneling port */
5096 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5097 struct rte_eth_udp_tunnel *udp_tunnel)
5100 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5102 if (udp_tunnel == NULL)
5105 switch (udp_tunnel->prot_type) {
5106 case RTE_TUNNEL_TYPE_VXLAN:
5107 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5109 case RTE_TUNNEL_TYPE_GENEVE:
5110 case RTE_TUNNEL_TYPE_TEREDO:
5111 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5115 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5123 /* Calculate the maximum number of contiguous PF queues that are configured */
5125 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5127 struct rte_eth_dev_data *data = pf->dev_data;
5129 struct i40e_rx_queue *rxq;
5132 for (i = 0; i < pf->lan_nb_qps; i++) {
5133 rxq = data->rx_queues[i];
5134 if (rxq && rxq->q_set)
5145 i40e_pf_config_rss(struct i40e_pf *pf)
5147 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5148 struct rte_eth_rss_conf rss_conf;
5149 uint32_t i, lut = 0;
5153 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5154 * It's necessary to calulate the actual PF queues that are configured.
5156 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5157 num = i40e_pf_calc_configured_queues_num(pf);
5158 num = i40e_align_floor(num);
5160 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5162 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5166 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5170 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5173 lut = (lut << 8) | (j & ((0x1 <<
5174 hw->func_caps.rss_table_entry_width) - 1));
5176 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5179 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5180 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5181 i40e_pf_disable_rss(pf);
5184 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5185 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5186 /* Random default keys */
5187 static uint32_t rss_key_default[] = {0x6b793944,
5188 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5189 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5190 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5192 rss_conf.rss_key = (uint8_t *)rss_key_default;
5193 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5197 return i40e_hw_rss_hash_set(hw, &rss_conf);
5201 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5202 struct rte_eth_tunnel_filter_conf *filter)
5204 if (pf == NULL || filter == NULL) {
5205 PMD_DRV_LOG(ERR, "Invalid parameter");
5209 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5210 PMD_DRV_LOG(ERR, "Invalid queue ID");
5214 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5215 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5219 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5220 (is_zero_ether_addr(filter->outer_mac))) {
5221 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5225 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5226 (is_zero_ether_addr(filter->inner_mac))) {
5227 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5235 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5238 struct rte_eth_tunnel_filter_conf *filter;
5239 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5240 int ret = I40E_SUCCESS;
5242 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5244 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5245 return I40E_ERR_PARAM;
5247 switch (filter_op) {
5248 case RTE_ETH_FILTER_NOP:
5249 if (!(pf->flags & I40E_FLAG_VXLAN))
5250 ret = I40E_NOT_SUPPORTED;
5251 case RTE_ETH_FILTER_ADD:
5252 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5254 case RTE_ETH_FILTER_DELETE:
5255 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5258 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5259 ret = I40E_ERR_PARAM;
5267 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5270 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5272 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5273 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5278 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5279 ret = i40e_pf_config_rss(pf);
5281 i40e_pf_disable_rss(pf);
5286 /* Get the symmetric hash enable configurations per port */
5288 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5290 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5292 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5295 /* Set the symmetric hash enable configurations per port */
5297 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5299 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5302 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5303 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5307 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5309 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5310 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5314 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5316 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5317 I40E_WRITE_FLUSH(hw);
5321 * Get global configurations of hash function type and symmetric hash enable
5322 * per flow type (pctype). Note that global configuration means it affects all
5323 * the ports on the same NIC.
5326 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5327 struct rte_eth_hash_global_conf *g_cfg)
5329 uint32_t reg, mask = I40E_FLOW_TYPES;
5331 enum i40e_filter_pctype pctype;
5333 memset(g_cfg, 0, sizeof(*g_cfg));
5334 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5335 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5336 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5338 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5339 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5340 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5342 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5343 if (!(mask & (1UL << i)))
5345 mask &= ~(1UL << i);
5346 /* Bit set indicats the coresponding flow type is supported */
5347 g_cfg->valid_bit_mask[0] |= (1UL << i);
5348 pctype = i40e_flowtype_to_pctype(i);
5349 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5350 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5351 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5358 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5361 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5363 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5364 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5365 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5366 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5372 * As i40e supports less than 32 flow types, only first 32 bits need to
5375 mask0 = g_cfg->valid_bit_mask[0];
5376 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5378 /* Check if any unsupported flow type configured */
5379 if ((mask0 | i40e_mask) ^ i40e_mask)
5382 if (g_cfg->valid_bit_mask[i])
5390 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5396 * Set global configurations of hash function type and symmetric hash enable
5397 * per flow type (pctype). Note any modifying global configuration will affect
5398 * all the ports on the same NIC.
5401 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5402 struct rte_eth_hash_global_conf *g_cfg)
5407 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5408 enum i40e_filter_pctype pctype;
5410 /* Check the input parameters */
5411 ret = i40e_hash_global_config_check(g_cfg);
5415 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5416 if (!(mask0 & (1UL << i)))
5418 mask0 &= ~(1UL << i);
5419 pctype = i40e_flowtype_to_pctype(i);
5420 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5421 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5422 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5425 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5426 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5428 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5429 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5433 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5434 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5436 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5437 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5441 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5443 /* Use the default, and keep it as it is */
5446 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5449 I40E_WRITE_FLUSH(hw);
5455 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5460 PMD_DRV_LOG(ERR, "Invalid pointer");
5464 switch (info->info_type) {
5465 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5466 i40e_get_symmetric_hash_enable_per_port(hw,
5467 &(info->info.enable));
5469 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5470 ret = i40e_get_hash_filter_global_config(hw,
5471 &(info->info.global_conf));
5474 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5484 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5489 PMD_DRV_LOG(ERR, "Invalid pointer");
5493 switch (info->info_type) {
5494 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5495 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5497 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5498 ret = i40e_set_hash_filter_global_config(hw,
5499 &(info->info.global_conf));
5502 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5511 /* Operations for hash function */
5513 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5514 enum rte_filter_op filter_op,
5517 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5520 switch (filter_op) {
5521 case RTE_ETH_FILTER_NOP:
5523 case RTE_ETH_FILTER_GET:
5524 ret = i40e_hash_filter_get(hw,
5525 (struct rte_eth_hash_filter_info *)arg);
5527 case RTE_ETH_FILTER_SET:
5528 ret = i40e_hash_filter_set(hw,
5529 (struct rte_eth_hash_filter_info *)arg);
5532 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5542 * Configure ethertype filter, which can director packet by filtering
5543 * with mac address and ether_type or only ether_type
5546 i40e_ethertype_filter_set(struct i40e_pf *pf,
5547 struct rte_eth_ethertype_filter *filter,
5550 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5551 struct i40e_control_filter_stats stats;
5555 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5556 PMD_DRV_LOG(ERR, "Invalid queue ID");
5559 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5560 filter->ether_type == ETHER_TYPE_IPv6) {
5561 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5562 " control packet filter.", filter->ether_type);
5565 if (filter->ether_type == ETHER_TYPE_VLAN)
5566 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5569 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5570 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5571 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5572 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5573 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5575 memset(&stats, 0, sizeof(stats));
5576 ret = i40e_aq_add_rem_control_packet_filter(hw,
5577 filter->mac_addr.addr_bytes,
5578 filter->ether_type, flags,
5580 filter->queue, add, &stats, NULL);
5582 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5583 " mac_etype_used = %u, etype_used = %u,"
5584 " mac_etype_free = %u, etype_free = %u\n",
5585 ret, stats.mac_etype_used, stats.etype_used,
5586 stats.mac_etype_free, stats.etype_free);
5593 * Handle operations for ethertype filter.
5596 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5597 enum rte_filter_op filter_op,
5600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5603 if (filter_op == RTE_ETH_FILTER_NOP)
5607 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5612 switch (filter_op) {
5613 case RTE_ETH_FILTER_ADD:
5614 ret = i40e_ethertype_filter_set(pf,
5615 (struct rte_eth_ethertype_filter *)arg,
5618 case RTE_ETH_FILTER_DELETE:
5619 ret = i40e_ethertype_filter_set(pf,
5620 (struct rte_eth_ethertype_filter *)arg,
5624 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5632 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5633 enum rte_filter_type filter_type,
5634 enum rte_filter_op filter_op,
5642 switch (filter_type) {
5643 case RTE_ETH_FILTER_HASH:
5644 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5646 case RTE_ETH_FILTER_MACVLAN:
5647 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5649 case RTE_ETH_FILTER_ETHERTYPE:
5650 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5652 case RTE_ETH_FILTER_TUNNEL:
5653 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5655 case RTE_ETH_FILTER_FDIR:
5656 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5659 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5669 * As some registers wouldn't be reset unless a global hardware reset,
5670 * hardware initialization is needed to put those registers into an
5671 * expected initial state.
5674 i40e_hw_init(struct i40e_hw *hw)
5676 /* clear the PF Queue Filter control register */
5677 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5679 /* Disable symmetric hash per port */
5680 i40e_set_symmetric_hash_enable_per_port(hw, 0);
5683 enum i40e_filter_pctype
5684 i40e_flowtype_to_pctype(uint16_t flow_type)
5686 static const enum i40e_filter_pctype pctype_table[] = {
5687 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5688 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5689 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5690 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5691 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5692 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5693 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5694 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5695 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5696 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5697 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5698 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5699 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5700 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5701 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5702 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5703 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5704 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5705 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5708 return pctype_table[flow_type];
5712 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5714 static const uint16_t flowtype_table[] = {
5715 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5716 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5717 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5718 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5719 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5720 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5721 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5722 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5723 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5724 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5725 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5726 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5727 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5728 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5729 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5730 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5731 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5732 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5733 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5736 return flowtype_table[pctype];
5740 * On X710, performance number is far from the expectation on recent firmware
5741 * versions; on XL710, performance number is also far from the expectation on
5742 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5743 * mode is enabled and port MAC address is equal to the packet destination MAC
5744 * address. The fix for this issue may not be integrated in the following
5745 * firmware version. So the workaround in software driver is needed. It needs
5746 * to modify the initial values of 3 internal only registers for both X710 and
5747 * XL710. Note that the values for X710 or XL710 could be different, and the
5748 * workaround can be removed when it is fixed in firmware in the future.
5751 /* For both X710 and XL710 */
5752 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5753 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
5755 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5756 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
5759 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
5761 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
5762 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
5765 i40e_configure_registers(struct i40e_hw *hw)
5771 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5772 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5773 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5779 for (i = 0; i < RTE_DIM(reg_table); i++) {
5780 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5781 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5783 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5786 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5789 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5792 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5796 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5797 reg_table[i].addr, reg);
5798 if (reg == reg_table[i].val)
5801 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5802 reg_table[i].val, NULL);
5804 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5805 "address of 0x%"PRIx32, reg_table[i].val,
5809 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5810 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5814 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
5815 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
5816 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
5817 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5819 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5824 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5825 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5829 /* Configure for double VLAN RX stripping */
5830 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5831 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5832 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5833 ret = i40e_aq_debug_write_register(hw,
5834 I40E_VSI_TSR(vsi->vsi_id),
5837 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5839 return I40E_ERR_CONFIG;
5843 /* Configure for double VLAN TX insertion */
5844 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5845 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5846 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5847 ret = i40e_aq_debug_write_register(hw,
5848 I40E_VSI_L2TAGSTXVALID(
5849 vsi->vsi_id), reg, NULL);
5851 PMD_DRV_LOG(ERR, "Failed to update "
5852 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5853 return I40E_ERR_CONFIG;
5861 * i40e_aq_add_mirror_rule
5862 * @hw: pointer to the hardware structure
5863 * @seid: VEB seid to add mirror rule to
5864 * @dst_id: destination vsi seid
5865 * @entries: Buffer which contains the entities to be mirrored
5866 * @count: number of entities contained in the buffer
5867 * @rule_id:the rule_id of the rule to be added
5869 * Add a mirror rule for a given veb.
5872 static enum i40e_status_code
5873 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5874 uint16_t seid, uint16_t dst_id,
5875 uint16_t rule_type, uint16_t *entries,
5876 uint16_t count, uint16_t *rule_id)
5878 struct i40e_aq_desc desc;
5879 struct i40e_aqc_add_delete_mirror_rule cmd;
5880 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5881 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5884 enum i40e_status_code status;
5886 i40e_fill_default_direct_cmd_desc(&desc,
5887 i40e_aqc_opc_add_mirror_rule);
5888 memset(&cmd, 0, sizeof(cmd));
5890 buff_len = sizeof(uint16_t) * count;
5891 desc.datalen = rte_cpu_to_le_16(buff_len);
5893 desc.flags |= rte_cpu_to_le_16(
5894 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5895 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5896 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5897 cmd.num_entries = rte_cpu_to_le_16(count);
5898 cmd.seid = rte_cpu_to_le_16(seid);
5899 cmd.destination = rte_cpu_to_le_16(dst_id);
5901 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5902 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5903 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5905 " mirror_rules_used = %u, mirror_rules_free = %u,",
5906 hw->aq.asq_last_status, resp->rule_id,
5907 resp->mirror_rules_used, resp->mirror_rules_free);
5908 *rule_id = rte_le_to_cpu_16(resp->rule_id);
5914 * i40e_aq_del_mirror_rule
5915 * @hw: pointer to the hardware structure
5916 * @seid: VEB seid to add mirror rule to
5917 * @entries: Buffer which contains the entities to be mirrored
5918 * @count: number of entities contained in the buffer
5919 * @rule_id:the rule_id of the rule to be delete
5921 * Delete a mirror rule for a given veb.
5924 static enum i40e_status_code
5925 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5926 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5927 uint16_t count, uint16_t rule_id)
5929 struct i40e_aq_desc desc;
5930 struct i40e_aqc_add_delete_mirror_rule cmd;
5931 uint16_t buff_len = 0;
5932 enum i40e_status_code status;
5935 i40e_fill_default_direct_cmd_desc(&desc,
5936 i40e_aqc_opc_delete_mirror_rule);
5937 memset(&cmd, 0, sizeof(cmd));
5938 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5939 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5941 cmd.num_entries = count;
5942 buff_len = sizeof(uint16_t) * count;
5943 desc.datalen = rte_cpu_to_le_16(buff_len);
5944 buff = (void *)entries;
5946 /* rule id is filled in destination field for deleting mirror rule */
5947 cmd.destination = rte_cpu_to_le_16(rule_id);
5949 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5950 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5951 cmd.seid = rte_cpu_to_le_16(seid);
5953 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5954 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5960 * i40e_mirror_rule_set
5961 * @dev: pointer to the hardware structure
5962 * @mirror_conf: mirror rule info
5963 * @sw_id: mirror rule's sw_id
5964 * @on: enable/disable
5966 * set a mirror rule.
5970 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5971 struct rte_eth_mirror_conf *mirror_conf,
5972 uint8_t sw_id, uint8_t on)
5974 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5975 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976 struct i40e_mirror_rule *it, *mirr_rule = NULL;
5977 struct i40e_mirror_rule *parent = NULL;
5978 uint16_t seid, dst_seid, rule_id;
5982 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5984 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5985 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5986 " without veb or vfs.");
5989 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5990 PMD_DRV_LOG(ERR, "mirror table is full.");
5993 if (mirror_conf->dst_pool > pf->vf_num) {
5994 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
5995 mirror_conf->dst_pool);
5999 seid = pf->main_vsi->veb->seid;
6001 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6002 if (sw_id <= it->index) {
6008 if (mirr_rule && sw_id == mirr_rule->index) {
6010 PMD_DRV_LOG(ERR, "mirror rule exists.");
6013 ret = i40e_aq_del_mirror_rule(hw, seid,
6014 mirr_rule->rule_type,
6016 mirr_rule->num_entries, mirr_rule->id);
6018 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6019 " ret = %d, aq_err = %d.",
6020 ret, hw->aq.asq_last_status);
6023 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6024 rte_free(mirr_rule);
6025 pf->nb_mirror_rule--;
6029 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6033 mirr_rule = rte_zmalloc("i40e_mirror_rule",
6034 sizeof(struct i40e_mirror_rule) , 0);
6036 PMD_DRV_LOG(ERR, "failed to allocate memory");
6037 return I40E_ERR_NO_MEMORY;
6039 switch (mirror_conf->rule_type) {
6040 case ETH_MIRROR_VLAN:
6041 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6042 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6043 mirr_rule->entries[j] =
6044 mirror_conf->vlan.vlan_id[i];
6049 PMD_DRV_LOG(ERR, "vlan is not specified.");
6050 rte_free(mirr_rule);
6053 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6055 case ETH_MIRROR_VIRTUAL_POOL_UP:
6056 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6057 /* check if the specified pool bit is out of range */
6058 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6059 PMD_DRV_LOG(ERR, "pool mask is out of range.");
6060 rte_free(mirr_rule);
6063 for (i = 0, j = 0; i < pf->vf_num; i++) {
6064 if (mirror_conf->pool_mask & (1ULL << i)) {
6065 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6069 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6070 /* add pf vsi to entries */
6071 mirr_rule->entries[j] = pf->main_vsi_seid;
6075 PMD_DRV_LOG(ERR, "pool is not specified.");
6076 rte_free(mirr_rule);
6079 /* egress and ingress in aq commands means from switch but not port */
6080 mirr_rule->rule_type =
6081 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6082 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6083 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6085 case ETH_MIRROR_UPLINK_PORT:
6086 /* egress and ingress in aq commands means from switch but not port*/
6087 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6089 case ETH_MIRROR_DOWNLINK_PORT:
6090 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6093 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6094 mirror_conf->rule_type);
6095 rte_free(mirr_rule);
6099 /* If the dst_pool is equal to vf_num, consider it as PF */
6100 if (mirror_conf->dst_pool == pf->vf_num)
6101 dst_seid = pf->main_vsi_seid;
6103 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6105 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6106 mirr_rule->rule_type, mirr_rule->entries,
6109 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6110 " ret = %d, aq_err = %d.",
6111 ret, hw->aq.asq_last_status);
6112 rte_free(mirr_rule);
6116 mirr_rule->index = sw_id;
6117 mirr_rule->num_entries = j;
6118 mirr_rule->id = rule_id;
6119 mirr_rule->dst_vsi_seid = dst_seid;
6122 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6124 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6126 pf->nb_mirror_rule++;
6131 * i40e_mirror_rule_reset
6132 * @dev: pointer to the device
6133 * @sw_id: mirror rule's sw_id
6135 * reset a mirror rule.
6139 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6143 struct i40e_mirror_rule *it, *mirr_rule = NULL;
6147 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6149 seid = pf->main_vsi->veb->seid;
6151 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6152 if (sw_id == it->index) {
6158 ret = i40e_aq_del_mirror_rule(hw, seid,
6159 mirr_rule->rule_type,
6161 mirr_rule->num_entries, mirr_rule->id);
6163 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6164 " status = %d, aq_err = %d.",
6165 ret, hw->aq.asq_last_status);
6168 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6169 rte_free(mirr_rule);
6170 pf->nb_mirror_rule--;
6172 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6179 i40e_timesync_enable(struct rte_eth_dev *dev)
6181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6182 struct rte_eth_link *link = &dev->data->dev_link;
6183 uint32_t tsync_ctl_l;
6184 uint32_t tsync_ctl_h;
6185 uint32_t tsync_inc_l;
6186 uint32_t tsync_inc_h;
6188 switch (link->link_speed) {
6189 case ETH_LINK_SPEED_40G:
6190 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6191 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6193 case ETH_LINK_SPEED_10G:
6194 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6195 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6197 case ETH_LINK_SPEED_1000:
6198 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6199 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6206 /* Clear timesync registers. */
6207 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6208 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6209 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6210 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6211 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6212 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6213 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6215 /* Set the timesync increment value. */
6216 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6217 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6219 /* Enable timestamping of PTP packets. */
6220 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6221 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6223 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6224 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6225 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6227 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6228 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6234 i40e_timesync_disable(struct rte_eth_dev *dev)
6236 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6237 uint32_t tsync_ctl_l;
6238 uint32_t tsync_ctl_h;
6240 /* Disable timestamping of transmitted PTP packets. */
6241 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6242 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6244 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6245 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6247 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6248 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6250 /* Set the timesync increment value. */
6251 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6252 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6258 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6259 struct timespec *timestamp, uint32_t flags)
6261 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6262 uint32_t sync_status;
6265 uint32_t index = flags & 0x03;
6267 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6268 if ((sync_status & (1 << index)) == 0)
6271 rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6272 rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6274 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6275 timestamp->tv_nsec = 0;
6281 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6282 struct timespec *timestamp)
6284 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6285 uint32_t sync_status;
6289 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6290 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6293 tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6294 tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6296 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6297 timestamp->tv_nsec = 0;