1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define I40E_CLEAR_PXE_WAIT_MS 200
50 /* Maximun number of capability elements */
51 #define I40E_MAX_CAP_ELE_NUM 128
53 /* Wait count and interval */
54 #define I40E_CHK_Q_ENA_COUNT 1000
55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
57 /* Maximun number of VSI */
58 #define I40E_MAX_NUM_VSIS (384UL)
60 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
62 /* Flow control default timer */
63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
65 /* Flow control enable fwd bit */
66 #define I40E_PRTMAC_FWD_CTRL 0x00000001
68 /* Receive Packet Buffer size */
69 #define I40E_RXPBSIZE (968 * 1024)
72 #define I40E_KILOSHIFT 10
74 /* Flow control default high water */
75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
77 /* Flow control default low water */
78 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
80 /* Receive Average Packet Size in Byte*/
81 #define I40E_PACKET_AVERAGE_SIZE 128
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
92 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
93 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
95 #define I40E_FLOW_TYPES ( \
96 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
106 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
108 /* Additional timesync values. */
109 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
110 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
111 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
112 #define I40E_PRTTSYN_TSYNENA 0x80000000
113 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
114 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
117 * Below are values for writing un-exposed registers suggested
120 /* Destination MAC address */
121 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
122 /* Source MAC address */
123 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
127 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
128 /* Single VLAN tag in the inner L2 header */
129 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
130 /* Source IPv4 address */
131 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
132 /* Destination IPv4 address */
133 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
134 /* Source IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
136 /* Destination IPv4 address for X722 */
137 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
138 /* IPv4 Protocol for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
140 /* IPv4 Time to Live for X722 */
141 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
142 /* IPv4 Type of Service (TOS) */
143 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
145 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
146 /* IPv4 Time to Live */
147 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
148 /* Source IPv6 address */
149 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
150 /* Destination IPv6 address */
151 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
152 /* IPv6 Traffic Class (TC) */
153 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
154 /* IPv6 Next Header */
155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
159 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
160 /* Destination L4 port */
161 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
162 /* SCTP verification tag */
163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
166 /* Source port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
168 /* Destination port of tunneling UDP */
169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
170 /* UDP Tunneling ID, NVGRE/GRE key */
171 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
172 /* Last ether type */
173 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
174 /* Tunneling outer destination IPv4 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
176 /* Tunneling outer destination IPv6 address */
177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
178 /* 1st word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
180 /* 2nd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
182 /* 3rd word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
184 /* 4th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
186 /* 5th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
188 /* 6th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
190 /* 7th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
192 /* 8th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
194 /* all 8 words flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
196 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
198 #define I40E_TRANSLATE_INSET 0
199 #define I40E_TRANSLATE_REG 1
201 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
202 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
203 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
204 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
206 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
208 /* PCI offset for querying capability */
209 #define PCI_DEV_CAP_REG 0xA4
210 /* PCI offset for enabling/disabling Extended Tag */
211 #define PCI_DEV_CTRL_REG 0xA8
212 /* Bit mask of Extended Tag capability */
213 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
214 /* Bit shift of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
216 /* Bit mask of Extended Tag enable/disable */
217 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
221 static int i40e_dev_configure(struct rte_eth_dev *dev);
222 static int i40e_dev_start(struct rte_eth_dev *dev);
223 static void i40e_dev_stop(struct rte_eth_dev *dev);
224 static void i40e_dev_close(struct rte_eth_dev *dev);
225 static int i40e_dev_reset(struct rte_eth_dev *dev);
226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
233 struct rte_eth_stats *stats);
234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
235 struct rte_eth_xstat *xstats, unsigned n);
236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
237 struct rte_eth_xstat_name *xstats_names,
239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
240 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
245 char *fw_version, size_t fw_size);
246 static void i40e_dev_info_get(struct rte_eth_dev *dev,
247 struct rte_eth_dev_info *dev_info);
248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
252 enum rte_vlan_type vlan_type,
254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_fc_conf *fc_conf);
265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
266 struct rte_eth_pfc_conf *pfc_conf);
267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
268 struct ether_addr *mac_addr,
271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
276 struct rte_eth_rss_reta_entry64 *reta_conf,
279 static int i40e_get_cap(struct i40e_hw *hw);
280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
281 static int i40e_pf_setup(struct i40e_pf *pf);
282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
286 bool offset_loaded, uint64_t *offset, uint64_t *stat);
287 static void i40e_stat_update_48(struct i40e_hw *hw,
293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
294 static void i40e_dev_interrupt_handler(void *param);
295 static void i40e_dev_alarm_handler(void *param);
296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
297 uint32_t base, uint32_t num);
298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
304 static int i40e_veb_release(struct i40e_veb *veb);
305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
306 struct i40e_vsi *vsi);
307 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
308 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
309 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
310 struct i40e_macvlan_filter *mv_f,
313 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
314 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
315 struct rte_eth_rss_conf *rss_conf);
316 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
317 struct rte_eth_rss_conf *rss_conf);
318 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
319 struct rte_eth_udp_tunnel *udp_tunnel);
320 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
321 struct rte_eth_udp_tunnel *udp_tunnel);
322 static void i40e_filter_input_set_init(struct i40e_pf *pf);
323 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
324 enum rte_filter_op filter_op,
326 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
327 enum rte_filter_type filter_type,
328 enum rte_filter_op filter_op,
330 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
331 struct rte_eth_dcb_info *dcb_info);
332 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
333 static void i40e_configure_registers(struct i40e_hw *hw);
334 static void i40e_hw_init(struct rte_eth_dev *dev);
335 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
336 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
342 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
343 struct rte_eth_mirror_conf *mirror_conf,
344 uint8_t sw_id, uint8_t on);
345 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
347 static int i40e_timesync_enable(struct rte_eth_dev *dev);
348 static int i40e_timesync_disable(struct rte_eth_dev *dev);
349 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp,
352 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp);
354 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
356 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
363 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
365 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
368 static int i40e_get_regs(struct rte_eth_dev *dev,
369 struct rte_dev_reg_info *regs);
371 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
373 static int i40e_get_eeprom(struct rte_eth_dev *dev,
374 struct rte_dev_eeprom_info *eeprom);
376 static int i40e_get_module_info(struct rte_eth_dev *dev,
377 struct rte_eth_dev_module_info *modinfo);
378 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
379 struct rte_dev_eeprom_info *info);
381 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
382 struct ether_addr *mac_addr);
384 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
386 static int i40e_ethertype_filter_convert(
387 const struct rte_eth_ethertype_filter *input,
388 struct i40e_ethertype_filter *filter);
389 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
390 struct i40e_ethertype_filter *filter);
392 static int i40e_tunnel_filter_convert(
393 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
394 struct i40e_tunnel_filter *tunnel_filter);
395 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
396 struct i40e_tunnel_filter *tunnel_filter);
397 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
399 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
400 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
401 static void i40e_filter_restore(struct i40e_pf *pf);
402 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
404 int i40e_logtype_init;
405 int i40e_logtype_driver;
407 static const char *const valid_keys[] = {
408 ETH_I40E_FLOATING_VEB_ARG,
409 ETH_I40E_FLOATING_VEB_LIST_ARG,
410 ETH_I40E_SUPPORT_MULTI_DRIVER,
411 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
412 ETH_I40E_USE_LATEST_VEC,
415 static const struct rte_pci_id pci_id_i40e_map[] = {
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
436 { .vendor_id = 0, /* sentinel */ },
439 static const struct eth_dev_ops i40e_eth_dev_ops = {
440 .dev_configure = i40e_dev_configure,
441 .dev_start = i40e_dev_start,
442 .dev_stop = i40e_dev_stop,
443 .dev_close = i40e_dev_close,
444 .dev_reset = i40e_dev_reset,
445 .promiscuous_enable = i40e_dev_promiscuous_enable,
446 .promiscuous_disable = i40e_dev_promiscuous_disable,
447 .allmulticast_enable = i40e_dev_allmulticast_enable,
448 .allmulticast_disable = i40e_dev_allmulticast_disable,
449 .dev_set_link_up = i40e_dev_set_link_up,
450 .dev_set_link_down = i40e_dev_set_link_down,
451 .link_update = i40e_dev_link_update,
452 .stats_get = i40e_dev_stats_get,
453 .xstats_get = i40e_dev_xstats_get,
454 .xstats_get_names = i40e_dev_xstats_get_names,
455 .stats_reset = i40e_dev_stats_reset,
456 .xstats_reset = i40e_dev_stats_reset,
457 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
458 .fw_version_get = i40e_fw_version_get,
459 .dev_infos_get = i40e_dev_info_get,
460 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
461 .vlan_filter_set = i40e_vlan_filter_set,
462 .vlan_tpid_set = i40e_vlan_tpid_set,
463 .vlan_offload_set = i40e_vlan_offload_set,
464 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
465 .vlan_pvid_set = i40e_vlan_pvid_set,
466 .rx_queue_start = i40e_dev_rx_queue_start,
467 .rx_queue_stop = i40e_dev_rx_queue_stop,
468 .tx_queue_start = i40e_dev_tx_queue_start,
469 .tx_queue_stop = i40e_dev_tx_queue_stop,
470 .rx_queue_setup = i40e_dev_rx_queue_setup,
471 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
472 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
473 .rx_queue_release = i40e_dev_rx_queue_release,
474 .rx_queue_count = i40e_dev_rx_queue_count,
475 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
476 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
477 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
478 .tx_queue_setup = i40e_dev_tx_queue_setup,
479 .tx_queue_release = i40e_dev_tx_queue_release,
480 .dev_led_on = i40e_dev_led_on,
481 .dev_led_off = i40e_dev_led_off,
482 .flow_ctrl_get = i40e_flow_ctrl_get,
483 .flow_ctrl_set = i40e_flow_ctrl_set,
484 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
485 .mac_addr_add = i40e_macaddr_add,
486 .mac_addr_remove = i40e_macaddr_remove,
487 .reta_update = i40e_dev_rss_reta_update,
488 .reta_query = i40e_dev_rss_reta_query,
489 .rss_hash_update = i40e_dev_rss_hash_update,
490 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
491 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
492 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
493 .filter_ctrl = i40e_dev_filter_ctrl,
494 .rxq_info_get = i40e_rxq_info_get,
495 .txq_info_get = i40e_txq_info_get,
496 .mirror_rule_set = i40e_mirror_rule_set,
497 .mirror_rule_reset = i40e_mirror_rule_reset,
498 .timesync_enable = i40e_timesync_enable,
499 .timesync_disable = i40e_timesync_disable,
500 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
501 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
502 .get_dcb_info = i40e_dev_get_dcb_info,
503 .timesync_adjust_time = i40e_timesync_adjust_time,
504 .timesync_read_time = i40e_timesync_read_time,
505 .timesync_write_time = i40e_timesync_write_time,
506 .get_reg = i40e_get_regs,
507 .get_eeprom_length = i40e_get_eeprom_length,
508 .get_eeprom = i40e_get_eeprom,
509 .get_module_info = i40e_get_module_info,
510 .get_module_eeprom = i40e_get_module_eeprom,
511 .mac_addr_set = i40e_set_default_mac_addr,
512 .mtu_set = i40e_dev_mtu_set,
513 .tm_ops_get = i40e_tm_ops_get,
516 /* store statistics names and its offset in stats structure */
517 struct rte_i40e_xstats_name_off {
518 char name[RTE_ETH_XSTATS_NAME_SIZE];
522 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
523 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
524 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
525 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
526 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
527 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
528 rx_unknown_protocol)},
529 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
530 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
531 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
532 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
535 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
536 sizeof(rte_i40e_stats_strings[0]))
538 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
539 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
540 tx_dropped_link_down)},
541 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
542 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
544 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
545 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
547 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
549 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
551 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
552 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
553 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
554 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
555 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
556 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
558 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
570 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
572 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
573 mac_short_packet_dropped)},
574 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
577 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
578 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
580 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
590 {"rx_flow_director_atr_match_packets",
591 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
592 {"rx_flow_director_sb_match_packets",
593 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
594 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
596 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
598 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
605 sizeof(rte_i40e_hw_port_strings[0]))
607 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
608 {"xon_packets", offsetof(struct i40e_hw_port_stats,
610 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
614 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
615 sizeof(rte_i40e_rxq_prio_strings[0]))
617 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
618 {"xon_packets", offsetof(struct i40e_hw_port_stats,
620 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
622 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
623 priority_xon_2_xoff)},
626 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
627 sizeof(rte_i40e_txq_prio_strings[0]))
630 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
631 struct rte_pci_device *pci_dev)
633 char name[RTE_ETH_NAME_MAX_LEN];
634 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
637 if (pci_dev->device.devargs) {
638 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
644 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
645 sizeof(struct i40e_adapter),
646 eth_dev_pci_specific_init, pci_dev,
647 eth_i40e_dev_init, NULL);
649 if (retval || eth_da.nb_representor_ports < 1)
652 /* probe VF representor ports */
653 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
654 pci_dev->device.name);
656 if (pf_ethdev == NULL)
659 for (i = 0; i < eth_da.nb_representor_ports; i++) {
660 struct i40e_vf_representor representor = {
661 .vf_id = eth_da.representor_ports[i],
662 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
663 pf_ethdev->data->dev_private)->switch_domain_id,
664 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
665 pf_ethdev->data->dev_private)
668 /* representor port net_bdf_port */
669 snprintf(name, sizeof(name), "net_%s_representor_%d",
670 pci_dev->device.name, eth_da.representor_ports[i]);
672 retval = rte_eth_dev_create(&pci_dev->device, name,
673 sizeof(struct i40e_vf_representor), NULL, NULL,
674 i40e_vf_representor_init, &representor);
677 PMD_DRV_LOG(ERR, "failed to create i40e vf "
678 "representor %s.", name);
684 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
686 struct rte_eth_dev *ethdev;
688 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
693 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
694 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
696 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
699 static struct rte_pci_driver rte_i40e_pmd = {
700 .id_table = pci_id_i40e_map,
701 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
702 RTE_PCI_DRV_IOVA_AS_VA,
703 .probe = eth_i40e_pci_probe,
704 .remove = eth_i40e_pci_remove,
708 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
711 uint32_t ori_reg_val;
712 struct rte_eth_dev *dev;
714 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
715 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
716 i40e_write_rx_ctl(hw, reg_addr, reg_val);
717 if (ori_reg_val != reg_val)
719 "i40e device %s changed global register [0x%08x]."
720 " original: 0x%08x, new: 0x%08x",
721 dev->device->name, reg_addr, ori_reg_val, reg_val);
724 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
725 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
726 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
728 #ifndef I40E_GLQF_ORT
729 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
731 #ifndef I40E_GLQF_PIT
732 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
734 #ifndef I40E_GLQF_L3_MAP
735 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
738 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
741 * Initialize registers for parsing packet type of QinQ
742 * This should be removed from code once proper
743 * configuration API is added to avoid configuration conflicts
744 * between ports of the same device.
746 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
750 static inline void i40e_config_automask(struct i40e_pf *pf)
752 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
755 /* INTENA flag is not auto-cleared for interrupt */
756 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
757 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
758 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
760 /* If support multi-driver, PF will use INT0. */
761 if (!pf->support_multi_driver)
762 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
764 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
767 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
770 * Add a ethertype filter to drop all flow control frames transmitted
774 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
776 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
777 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
778 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
782 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
783 I40E_FLOW_CONTROL_ETHERTYPE, flags,
784 pf->main_vsi_seid, 0,
788 "Failed to add filter to drop flow control frames from VSIs.");
792 floating_veb_list_handler(__rte_unused const char *key,
793 const char *floating_veb_value,
797 unsigned int count = 0;
800 bool *vf_floating_veb = opaque;
802 while (isblank(*floating_veb_value))
803 floating_veb_value++;
805 /* Reset floating VEB configuration for VFs */
806 for (idx = 0; idx < I40E_MAX_VF; idx++)
807 vf_floating_veb[idx] = false;
811 while (isblank(*floating_veb_value))
812 floating_veb_value++;
813 if (*floating_veb_value == '\0')
816 idx = strtoul(floating_veb_value, &end, 10);
817 if (errno || end == NULL)
819 while (isblank(*end))
823 } else if ((*end == ';') || (*end == '\0')) {
825 if (min == I40E_MAX_VF)
827 if (max >= I40E_MAX_VF)
828 max = I40E_MAX_VF - 1;
829 for (idx = min; idx <= max; idx++) {
830 vf_floating_veb[idx] = true;
837 floating_veb_value = end + 1;
838 } while (*end != '\0');
847 config_vf_floating_veb(struct rte_devargs *devargs,
848 uint16_t floating_veb,
849 bool *vf_floating_veb)
851 struct rte_kvargs *kvlist;
853 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
857 /* All the VFs attach to the floating VEB by default
858 * when the floating VEB is enabled.
860 for (i = 0; i < I40E_MAX_VF; i++)
861 vf_floating_veb[i] = true;
866 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
870 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
871 rte_kvargs_free(kvlist);
874 /* When the floating_veb_list parameter exists, all the VFs
875 * will attach to the legacy VEB firstly, then configure VFs
876 * to the floating VEB according to the floating_veb_list.
878 if (rte_kvargs_process(kvlist, floating_veb_list,
879 floating_veb_list_handler,
880 vf_floating_veb) < 0) {
881 rte_kvargs_free(kvlist);
884 rte_kvargs_free(kvlist);
888 i40e_check_floating_handler(__rte_unused const char *key,
890 __rte_unused void *opaque)
892 if (strcmp(value, "1"))
899 is_floating_veb_supported(struct rte_devargs *devargs)
901 struct rte_kvargs *kvlist;
902 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
907 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
911 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
912 rte_kvargs_free(kvlist);
915 /* Floating VEB is enabled when there's key-value:
916 * enable_floating_veb=1
918 if (rte_kvargs_process(kvlist, floating_veb_key,
919 i40e_check_floating_handler, NULL) < 0) {
920 rte_kvargs_free(kvlist);
923 rte_kvargs_free(kvlist);
929 config_floating_veb(struct rte_eth_dev *dev)
931 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
932 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
935 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
937 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
939 is_floating_veb_supported(pci_dev->device.devargs);
940 config_vf_floating_veb(pci_dev->device.devargs,
942 pf->floating_veb_list);
944 pf->floating_veb = false;
948 #define I40E_L2_TAGS_S_TAG_SHIFT 1
949 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
952 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
954 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
955 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
956 char ethertype_hash_name[RTE_HASH_NAMESIZE];
959 struct rte_hash_parameters ethertype_hash_params = {
960 .name = ethertype_hash_name,
961 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
962 .key_len = sizeof(struct i40e_ethertype_filter_input),
963 .hash_func = rte_hash_crc,
964 .hash_func_init_val = 0,
965 .socket_id = rte_socket_id(),
968 /* Initialize ethertype filter rule list and hash */
969 TAILQ_INIT(ðertype_rule->ethertype_list);
970 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
971 "ethertype_%s", dev->device->name);
972 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
973 if (!ethertype_rule->hash_table) {
974 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
977 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
978 sizeof(struct i40e_ethertype_filter *) *
979 I40E_MAX_ETHERTYPE_FILTER_NUM,
981 if (!ethertype_rule->hash_map) {
983 "Failed to allocate memory for ethertype hash map!");
985 goto err_ethertype_hash_map_alloc;
990 err_ethertype_hash_map_alloc:
991 rte_hash_free(ethertype_rule->hash_table);
997 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
999 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1000 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1001 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1004 struct rte_hash_parameters tunnel_hash_params = {
1005 .name = tunnel_hash_name,
1006 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1007 .key_len = sizeof(struct i40e_tunnel_filter_input),
1008 .hash_func = rte_hash_crc,
1009 .hash_func_init_val = 0,
1010 .socket_id = rte_socket_id(),
1013 /* Initialize tunnel filter rule list and hash */
1014 TAILQ_INIT(&tunnel_rule->tunnel_list);
1015 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1016 "tunnel_%s", dev->device->name);
1017 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1018 if (!tunnel_rule->hash_table) {
1019 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1022 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1023 sizeof(struct i40e_tunnel_filter *) *
1024 I40E_MAX_TUNNEL_FILTER_NUM,
1026 if (!tunnel_rule->hash_map) {
1028 "Failed to allocate memory for tunnel hash map!");
1030 goto err_tunnel_hash_map_alloc;
1035 err_tunnel_hash_map_alloc:
1036 rte_hash_free(tunnel_rule->hash_table);
1042 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1044 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1045 struct i40e_fdir_info *fdir_info = &pf->fdir;
1046 char fdir_hash_name[RTE_HASH_NAMESIZE];
1049 struct rte_hash_parameters fdir_hash_params = {
1050 .name = fdir_hash_name,
1051 .entries = I40E_MAX_FDIR_FILTER_NUM,
1052 .key_len = sizeof(struct i40e_fdir_input),
1053 .hash_func = rte_hash_crc,
1054 .hash_func_init_val = 0,
1055 .socket_id = rte_socket_id(),
1058 /* Initialize flow director filter rule list and hash */
1059 TAILQ_INIT(&fdir_info->fdir_list);
1060 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1061 "fdir_%s", dev->device->name);
1062 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1063 if (!fdir_info->hash_table) {
1064 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1067 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1068 sizeof(struct i40e_fdir_filter *) *
1069 I40E_MAX_FDIR_FILTER_NUM,
1071 if (!fdir_info->hash_map) {
1073 "Failed to allocate memory for fdir hash map!");
1075 goto err_fdir_hash_map_alloc;
1079 err_fdir_hash_map_alloc:
1080 rte_hash_free(fdir_info->hash_table);
1086 i40e_init_customized_info(struct i40e_pf *pf)
1090 /* Initialize customized pctype */
1091 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1092 pf->customized_pctype[i].index = i;
1093 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1094 pf->customized_pctype[i].valid = false;
1097 pf->gtp_support = false;
1101 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1103 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1105 struct i40e_queue_regions *info = &pf->queue_region;
1108 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1109 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1111 memset(info, 0, sizeof(struct i40e_queue_regions));
1115 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1120 unsigned long support_multi_driver;
1123 pf = (struct i40e_pf *)opaque;
1126 support_multi_driver = strtoul(value, &end, 10);
1127 if (errno != 0 || end == value || *end != 0) {
1128 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1132 if (support_multi_driver == 1 || support_multi_driver == 0)
1133 pf->support_multi_driver = (bool)support_multi_driver;
1135 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1136 "enable global configuration by default."
1137 ETH_I40E_SUPPORT_MULTI_DRIVER);
1142 i40e_support_multi_driver(struct rte_eth_dev *dev)
1144 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1145 struct rte_kvargs *kvlist;
1148 /* Enable global configuration by default */
1149 pf->support_multi_driver = false;
1151 if (!dev->device->devargs)
1154 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1158 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1159 if (!kvargs_count) {
1160 rte_kvargs_free(kvlist);
1164 if (kvargs_count > 1)
1165 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1166 "the first invalid or last valid one is used !",
1167 ETH_I40E_SUPPORT_MULTI_DRIVER);
1169 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1170 i40e_parse_multi_drv_handler, pf) < 0) {
1171 rte_kvargs_free(kvlist);
1175 rte_kvargs_free(kvlist);
1180 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1181 uint32_t reg_addr, uint64_t reg_val,
1182 struct i40e_asq_cmd_details *cmd_details)
1184 uint64_t ori_reg_val;
1185 struct rte_eth_dev *dev;
1188 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1189 if (ret != I40E_SUCCESS) {
1191 "Fail to debug read from 0x%08x",
1195 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1197 if (ori_reg_val != reg_val)
1198 PMD_DRV_LOG(WARNING,
1199 "i40e device %s changed global register [0x%08x]."
1200 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1201 dev->device->name, reg_addr, ori_reg_val, reg_val);
1203 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1207 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1211 struct i40e_adapter *ad;
1214 ad = (struct i40e_adapter *)opaque;
1216 use_latest_vec = atoi(value);
1218 if (use_latest_vec != 0 && use_latest_vec != 1)
1219 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1221 ad->use_latest_vec = (uint8_t)use_latest_vec;
1227 i40e_use_latest_vec(struct rte_eth_dev *dev)
1229 struct i40e_adapter *ad =
1230 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1231 struct rte_kvargs *kvlist;
1234 ad->use_latest_vec = false;
1236 if (!dev->device->devargs)
1239 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1243 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1244 if (!kvargs_count) {
1245 rte_kvargs_free(kvlist);
1249 if (kvargs_count > 1)
1250 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1251 "the first invalid or last valid one is used !",
1252 ETH_I40E_USE_LATEST_VEC);
1254 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1255 i40e_parse_latest_vec_handler, ad) < 0) {
1256 rte_kvargs_free(kvlist);
1260 rte_kvargs_free(kvlist);
1264 #define I40E_ALARM_INTERVAL 50000 /* us */
1267 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1269 struct rte_pci_device *pci_dev;
1270 struct rte_intr_handle *intr_handle;
1271 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1272 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273 struct i40e_vsi *vsi;
1276 uint8_t aq_fail = 0;
1278 PMD_INIT_FUNC_TRACE();
1280 dev->dev_ops = &i40e_eth_dev_ops;
1281 dev->rx_pkt_burst = i40e_recv_pkts;
1282 dev->tx_pkt_burst = i40e_xmit_pkts;
1283 dev->tx_pkt_prepare = i40e_prep_pkts;
1285 /* for secondary processes, we don't initialise any further as primary
1286 * has already done this work. Only check we don't need a different
1288 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1289 i40e_set_rx_function(dev);
1290 i40e_set_tx_function(dev);
1293 i40e_set_default_ptype_table(dev);
1294 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1295 intr_handle = &pci_dev->intr_handle;
1297 rte_eth_copy_pci_info(dev, pci_dev);
1299 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1300 pf->adapter->eth_dev = dev;
1301 pf->dev_data = dev->data;
1303 hw->back = I40E_PF_TO_ADAPTER(pf);
1304 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1307 "Hardware is not available, as address is NULL");
1311 hw->vendor_id = pci_dev->id.vendor_id;
1312 hw->device_id = pci_dev->id.device_id;
1313 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1314 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1315 hw->bus.device = pci_dev->addr.devid;
1316 hw->bus.func = pci_dev->addr.function;
1317 hw->adapter_stopped = 0;
1318 hw->adapter_closed = 0;
1321 * Switch Tag value should not be identical to either the First Tag
1322 * or Second Tag values. So set something other than common Ethertype
1323 * for internal switching.
1325 hw->switch_tag = 0xffff;
1327 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1328 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1329 PMD_INIT_LOG(ERR, "\nERROR: "
1330 "Firmware recovery mode detected. Limiting functionality.\n"
1331 "Refer to the Intel(R) Ethernet Adapters and Devices "
1332 "User Guide for details on firmware recovery mode.");
1336 /* Check if need to support multi-driver */
1337 i40e_support_multi_driver(dev);
1338 /* Check if users want the latest supported vec path */
1339 i40e_use_latest_vec(dev);
1341 /* Make sure all is clean before doing PF reset */
1344 /* Reset here to make sure all is clean for each PF */
1345 ret = i40e_pf_reset(hw);
1347 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1351 /* Initialize the shared code (base driver) */
1352 ret = i40e_init_shared_code(hw);
1354 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1358 /* Initialize the parameters for adminq */
1359 i40e_init_adminq_parameter(hw);
1360 ret = i40e_init_adminq(hw);
1361 if (ret != I40E_SUCCESS) {
1362 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1365 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1366 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1367 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1368 ((hw->nvm.version >> 12) & 0xf),
1369 ((hw->nvm.version >> 4) & 0xff),
1370 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1372 /* Initialize the hardware */
1375 i40e_config_automask(pf);
1377 i40e_set_default_pctype_table(dev);
1380 * To work around the NVM issue, initialize registers
1381 * for packet type of QinQ by software.
1382 * It should be removed once issues are fixed in NVM.
1384 if (!pf->support_multi_driver)
1385 i40e_GLQF_reg_init(hw);
1387 /* Initialize the input set for filters (hash and fd) to default value */
1388 i40e_filter_input_set_init(pf);
1390 /* initialise the L3_MAP register */
1391 if (!pf->support_multi_driver) {
1392 ret = i40e_aq_debug_write_global_register(hw,
1393 I40E_GLQF_L3_MAP(40),
1396 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1399 "Global register 0x%08x is changed with 0x28",
1400 I40E_GLQF_L3_MAP(40));
1403 /* Need the special FW version to support floating VEB */
1404 config_floating_veb(dev);
1405 /* Clear PXE mode */
1406 i40e_clear_pxe_mode(hw);
1407 i40e_dev_sync_phy_type(hw);
1410 * On X710, performance number is far from the expectation on recent
1411 * firmware versions. The fix for this issue may not be integrated in
1412 * the following firmware version. So the workaround in software driver
1413 * is needed. It needs to modify the initial values of 3 internal only
1414 * registers. Note that the workaround can be removed when it is fixed
1415 * in firmware in the future.
1417 i40e_configure_registers(hw);
1419 /* Get hw capabilities */
1420 ret = i40e_get_cap(hw);
1421 if (ret != I40E_SUCCESS) {
1422 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1423 goto err_get_capabilities;
1426 /* Initialize parameters for PF */
1427 ret = i40e_pf_parameter_init(dev);
1429 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1430 goto err_parameter_init;
1433 /* Initialize the queue management */
1434 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1436 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1437 goto err_qp_pool_init;
1439 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1440 hw->func_caps.num_msix_vectors - 1);
1442 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1443 goto err_msix_pool_init;
1446 /* Initialize lan hmc */
1447 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1448 hw->func_caps.num_rx_qp, 0, 0);
1449 if (ret != I40E_SUCCESS) {
1450 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1451 goto err_init_lan_hmc;
1454 /* Configure lan hmc */
1455 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1456 if (ret != I40E_SUCCESS) {
1457 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1458 goto err_configure_lan_hmc;
1461 /* Get and check the mac address */
1462 i40e_get_mac_addr(hw, hw->mac.addr);
1463 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1464 PMD_INIT_LOG(ERR, "mac address is not valid");
1466 goto err_get_mac_addr;
1468 /* Copy the permanent MAC address */
1469 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1470 (struct ether_addr *) hw->mac.perm_addr);
1472 /* Disable flow control */
1473 hw->fc.requested_mode = I40E_FC_NONE;
1474 i40e_set_fc(hw, &aq_fail, TRUE);
1476 /* Set the global registers with default ether type value */
1477 if (!pf->support_multi_driver) {
1478 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1480 if (ret != I40E_SUCCESS) {
1482 "Failed to set the default outer "
1484 goto err_setup_pf_switch;
1488 /* PF setup, which includes VSI setup */
1489 ret = i40e_pf_setup(pf);
1491 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1492 goto err_setup_pf_switch;
1497 /* Disable double vlan by default */
1498 i40e_vsi_config_double_vlan(vsi, FALSE);
1500 /* Disable S-TAG identification when floating_veb is disabled */
1501 if (!pf->floating_veb) {
1502 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1503 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1504 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1505 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1509 if (!vsi->max_macaddrs)
1510 len = ETHER_ADDR_LEN;
1512 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1514 /* Should be after VSI initialized */
1515 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1516 if (!dev->data->mac_addrs) {
1518 "Failed to allocated memory for storing mac address");
1521 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1522 &dev->data->mac_addrs[0]);
1524 /* Init dcb to sw mode by default */
1525 ret = i40e_dcb_init_configure(dev, TRUE);
1526 if (ret != I40E_SUCCESS) {
1527 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1528 pf->flags &= ~I40E_FLAG_DCB;
1530 /* Update HW struct after DCB configuration */
1533 /* initialize pf host driver to setup SRIOV resource if applicable */
1534 i40e_pf_host_init(dev);
1536 /* register callback func to eal lib */
1537 rte_intr_callback_register(intr_handle,
1538 i40e_dev_interrupt_handler, dev);
1540 /* configure and enable device interrupt */
1541 i40e_pf_config_irq0(hw, TRUE);
1542 i40e_pf_enable_irq0(hw);
1544 /* enable uio intr after callback register */
1545 rte_intr_enable(intr_handle);
1547 /* By default disable flexible payload in global configuration */
1548 if (!pf->support_multi_driver)
1549 i40e_flex_payload_reg_set_default(hw);
1552 * Add an ethertype filter to drop all flow control frames transmitted
1553 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1556 i40e_add_tx_flow_control_drop_filter(pf);
1558 /* Set the max frame size to 0x2600 by default,
1559 * in case other drivers changed the default value.
1561 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1563 /* initialize mirror rule list */
1564 TAILQ_INIT(&pf->mirror_list);
1566 /* initialize Traffic Manager configuration */
1567 i40e_tm_conf_init(dev);
1569 /* Initialize customized information */
1570 i40e_init_customized_info(pf);
1572 ret = i40e_init_ethtype_filter_list(dev);
1574 goto err_init_ethtype_filter_list;
1575 ret = i40e_init_tunnel_filter_list(dev);
1577 goto err_init_tunnel_filter_list;
1578 ret = i40e_init_fdir_filter_list(dev);
1580 goto err_init_fdir_filter_list;
1582 /* initialize queue region configuration */
1583 i40e_init_queue_region_conf(dev);
1585 /* initialize rss configuration from rte_flow */
1586 memset(&pf->rss_info, 0,
1587 sizeof(struct i40e_rte_flow_rss_conf));
1589 /* reset all stats of the device, including pf and main vsi */
1590 i40e_dev_stats_reset(dev);
1594 err_init_fdir_filter_list:
1595 rte_free(pf->tunnel.hash_table);
1596 rte_free(pf->tunnel.hash_map);
1597 err_init_tunnel_filter_list:
1598 rte_free(pf->ethertype.hash_table);
1599 rte_free(pf->ethertype.hash_map);
1600 err_init_ethtype_filter_list:
1601 rte_free(dev->data->mac_addrs);
1603 i40e_vsi_release(pf->main_vsi);
1604 err_setup_pf_switch:
1606 err_configure_lan_hmc:
1607 (void)i40e_shutdown_lan_hmc(hw);
1609 i40e_res_pool_destroy(&pf->msix_pool);
1611 i40e_res_pool_destroy(&pf->qp_pool);
1614 err_get_capabilities:
1615 (void)i40e_shutdown_adminq(hw);
1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 struct i40e_ethertype_filter *p_ethertype;
1624 struct i40e_ethertype_rule *ethertype_rule;
1626 ethertype_rule = &pf->ethertype;
1627 /* Remove all ethertype filter rules and hash */
1628 if (ethertype_rule->hash_map)
1629 rte_free(ethertype_rule->hash_map);
1630 if (ethertype_rule->hash_table)
1631 rte_hash_free(ethertype_rule->hash_table);
1633 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1634 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1635 p_ethertype, rules);
1636 rte_free(p_ethertype);
1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 struct i40e_tunnel_filter *p_tunnel;
1644 struct i40e_tunnel_rule *tunnel_rule;
1646 tunnel_rule = &pf->tunnel;
1647 /* Remove all tunnel director rules and hash */
1648 if (tunnel_rule->hash_map)
1649 rte_free(tunnel_rule->hash_map);
1650 if (tunnel_rule->hash_table)
1651 rte_hash_free(tunnel_rule->hash_table);
1653 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1654 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 struct i40e_fdir_filter *p_fdir;
1663 struct i40e_fdir_info *fdir_info;
1665 fdir_info = &pf->fdir;
1666 /* Remove all flow director rules and hash */
1667 if (fdir_info->hash_map)
1668 rte_free(fdir_info->hash_map);
1669 if (fdir_info->hash_table)
1670 rte_hash_free(fdir_info->hash_table);
1672 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1673 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1681 * Disable by default flexible payload
1682 * for corresponding L2/L3/L4 layers.
1684 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1693 struct rte_pci_device *pci_dev;
1694 struct rte_intr_handle *intr_handle;
1696 struct i40e_filter_control_settings settings;
1697 struct rte_flow *p_flow;
1699 uint8_t aq_fail = 0;
1702 PMD_INIT_FUNC_TRACE();
1704 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710 intr_handle = &pci_dev->intr_handle;
1712 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716 if (hw->adapter_closed == 0)
1717 i40e_dev_close(dev);
1719 dev->dev_ops = NULL;
1720 dev->rx_pkt_burst = NULL;
1721 dev->tx_pkt_burst = NULL;
1723 /* Clear PXE mode */
1724 i40e_clear_pxe_mode(hw);
1726 /* Unconfigure filter control */
1727 memset(&settings, 0, sizeof(settings));
1728 ret = i40e_set_filter_control(hw, &settings);
1730 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1733 /* Disable flow control */
1734 hw->fc.requested_mode = I40E_FC_NONE;
1735 i40e_set_fc(hw, &aq_fail, TRUE);
1737 /* uninitialize pf host driver */
1738 i40e_pf_host_uninit(dev);
1740 /* disable uio intr before callback unregister */
1741 rte_intr_disable(intr_handle);
1743 /* unregister callback func to eal lib */
1745 ret = rte_intr_callback_unregister(intr_handle,
1746 i40e_dev_interrupt_handler, dev);
1749 } else if (ret != -EAGAIN) {
1751 "intr callback unregister failed: %d",
1755 i40e_msec_delay(500);
1756 } while (retries++ < 5);
1758 i40e_rm_ethtype_filter_list(pf);
1759 i40e_rm_tunnel_filter_list(pf);
1760 i40e_rm_fdir_filter_list(pf);
1762 /* Remove all flows */
1763 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1764 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1768 /* Remove all Traffic Manager configuration */
1769 i40e_tm_conf_uninit(dev);
1775 i40e_dev_configure(struct rte_eth_dev *dev)
1777 struct i40e_adapter *ad =
1778 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1784 ret = i40e_dev_sync_phy_type(hw);
1788 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1789 * bulk allocation or vector Rx preconditions we will reset it.
1791 ad->rx_bulk_alloc_allowed = true;
1792 ad->rx_vec_allowed = true;
1793 ad->tx_simple_allowed = true;
1794 ad->tx_vec_allowed = true;
1796 /* Only legacy filter API needs the following fdir config. So when the
1797 * legacy filter API is deprecated, the following codes should also be
1800 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1801 ret = i40e_fdir_setup(pf);
1802 if (ret != I40E_SUCCESS) {
1803 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1806 ret = i40e_fdir_configure(dev);
1808 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1812 i40e_fdir_teardown(pf);
1814 ret = i40e_dev_init_vlan(dev);
1819 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1820 * RSS setting have different requirements.
1821 * General PMD driver call sequence are NIC init, configure,
1822 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1823 * will try to lookup the VSI that specific queue belongs to if VMDQ
1824 * applicable. So, VMDQ setting has to be done before
1825 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1826 * For RSS setting, it will try to calculate actual configured RX queue
1827 * number, which will be available after rx_queue_setup(). dev_start()
1828 * function is good to place RSS setup.
1830 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1831 ret = i40e_vmdq_setup(dev);
1836 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1837 ret = i40e_dcb_setup(dev);
1839 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1844 TAILQ_INIT(&pf->flow_list);
1849 /* need to release vmdq resource if exists */
1850 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1851 i40e_vsi_release(pf->vmdq[i].vsi);
1852 pf->vmdq[i].vsi = NULL;
1857 /* Need to release fdir resource if exists.
1858 * Only legacy filter API needs the following fdir config. So when the
1859 * legacy filter API is deprecated, the following code should also be
1862 i40e_fdir_teardown(pf);
1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1872 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1873 uint16_t msix_vect = vsi->msix_intr;
1876 for (i = 0; i < vsi->nb_qps; i++) {
1877 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1878 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1882 if (vsi->type != I40E_VSI_SRIOV) {
1883 if (!rte_intr_allow_others(intr_handle)) {
1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1885 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1890 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1891 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1898 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1899 vsi->user_param + (msix_vect - 1);
1901 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1902 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904 I40E_WRITE_FLUSH(hw);
1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1909 int base_queue, int nb_queue,
1914 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1915 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917 /* Bind all RX queues to allocated MSIX interrupt */
1918 for (i = 0; i < nb_queue; i++) {
1919 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1920 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1921 ((base_queue + i + 1) <<
1922 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1923 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1924 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926 if (i == nb_queue - 1)
1927 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1928 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1931 /* Write first RX queue to Link list register as the head element */
1932 if (vsi->type != I40E_VSI_SRIOV) {
1934 i40e_calc_itr_interval(1, pf->support_multi_driver);
1936 if (msix_vect == I40E_MISC_VEC_ID) {
1937 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1946 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1959 if (msix_vect == I40E_MISC_VEC_ID) {
1961 I40E_VPINT_LNKLST0(vsi->user_param),
1963 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967 /* num_msix_vectors_vf needs to minus irq0 */
1968 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969 vsi->user_param + (msix_vect - 1);
1971 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1979 I40E_WRITE_FLUSH(hw);
1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989 uint16_t msix_vect = vsi->msix_intr;
1990 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1991 uint16_t queue_idx = 0;
1995 for (i = 0; i < vsi->nb_qps; i++) {
1996 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1997 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2000 /* VF bind interrupt */
2001 if (vsi->type == I40E_VSI_SRIOV) {
2002 __vsi_queues_bind_intr(vsi, msix_vect,
2003 vsi->base_queue, vsi->nb_qps,
2008 /* PF & VMDq bind interrupt */
2009 if (rte_intr_dp_is_en(intr_handle)) {
2010 if (vsi->type == I40E_VSI_MAIN) {
2013 } else if (vsi->type == I40E_VSI_VMDQ2) {
2014 struct i40e_vsi *main_vsi =
2015 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2016 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2021 for (i = 0; i < vsi->nb_used_qps; i++) {
2023 if (!rte_intr_allow_others(intr_handle))
2024 /* allow to share MISC_VEC_ID */
2025 msix_vect = I40E_MISC_VEC_ID;
2027 /* no enough msix_vect, map all to one */
2028 __vsi_queues_bind_intr(vsi, msix_vect,
2029 vsi->base_queue + i,
2030 vsi->nb_used_qps - i,
2032 for (; !!record && i < vsi->nb_used_qps; i++)
2033 intr_handle->intr_vec[queue_idx + i] =
2037 /* 1:1 queue/msix_vect mapping */
2038 __vsi_queues_bind_intr(vsi, msix_vect,
2039 vsi->base_queue + i, 1,
2042 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2057 uint16_t msix_intr, i;
2059 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2060 for (i = 0; i < vsi->nb_msix; i++) {
2061 msix_intr = vsi->msix_intr + i;
2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2063 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2064 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2065 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2068 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2069 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2070 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2071 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073 I40E_WRITE_FLUSH(hw);
2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2084 uint16_t msix_intr, i;
2086 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2087 for (i = 0; i < vsi->nb_msix; i++) {
2088 msix_intr = vsi->msix_intr + i;
2089 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2090 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2093 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2094 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096 I40E_WRITE_FLUSH(hw);
2099 static inline uint8_t
2100 i40e_parse_link_speeds(uint16_t link_speeds)
2102 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104 if (link_speeds & ETH_LINK_SPEED_40G)
2105 link_speed |= I40E_LINK_SPEED_40GB;
2106 if (link_speeds & ETH_LINK_SPEED_25G)
2107 link_speed |= I40E_LINK_SPEED_25GB;
2108 if (link_speeds & ETH_LINK_SPEED_20G)
2109 link_speed |= I40E_LINK_SPEED_20GB;
2110 if (link_speeds & ETH_LINK_SPEED_10G)
2111 link_speed |= I40E_LINK_SPEED_10GB;
2112 if (link_speeds & ETH_LINK_SPEED_1G)
2113 link_speed |= I40E_LINK_SPEED_1GB;
2114 if (link_speeds & ETH_LINK_SPEED_100M)
2115 link_speed |= I40E_LINK_SPEED_100MB;
2121 i40e_phy_conf_link(struct i40e_hw *hw,
2123 uint8_t force_speed,
2126 enum i40e_status_code status;
2127 struct i40e_aq_get_phy_abilities_resp phy_ab;
2128 struct i40e_aq_set_phy_config phy_conf;
2129 enum i40e_aq_phy_type cnt;
2130 uint8_t avail_speed;
2131 uint32_t phy_type_mask = 0;
2133 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2134 I40E_AQ_PHY_FLAG_PAUSE_RX |
2135 I40E_AQ_PHY_FLAG_PAUSE_RX |
2136 I40E_AQ_PHY_FLAG_LOW_POWER;
2139 /* To get phy capabilities of available speeds. */
2140 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2143 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2147 avail_speed = phy_ab.link_speed;
2149 /* To get the current phy config. */
2150 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2153 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2158 /* If link needs to go up and it is in autoneg mode the speed is OK,
2159 * no need to set up again.
2161 if (is_up && phy_ab.phy_type != 0 &&
2162 abilities & I40E_AQ_PHY_AN_ENABLED &&
2163 phy_ab.link_speed != 0)
2164 return I40E_SUCCESS;
2166 memset(&phy_conf, 0, sizeof(phy_conf));
2168 /* bits 0-2 use the values from get_phy_abilities_resp */
2170 abilities |= phy_ab.abilities & mask;
2172 phy_conf.abilities = abilities;
2174 /* If link needs to go up, but the force speed is not supported,
2175 * Warn users and config the default available speeds.
2177 if (is_up && !(force_speed & avail_speed)) {
2178 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2179 phy_conf.link_speed = avail_speed;
2181 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2184 /* PHY type mask needs to include each type except PHY type extension */
2185 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2186 phy_type_mask |= 1 << cnt;
2188 /* use get_phy_abilities_resp value for the rest */
2189 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2190 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2191 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2192 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2193 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2194 phy_conf.eee_capability = phy_ab.eee_capability;
2195 phy_conf.eeer = phy_ab.eeer_val;
2196 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2199 phy_ab.abilities, phy_ab.link_speed);
2200 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2201 phy_conf.abilities, phy_conf.link_speed);
2203 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2207 return I40E_SUCCESS;
2211 i40e_apply_link_speed(struct rte_eth_dev *dev)
2214 uint8_t abilities = 0;
2215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 struct rte_eth_conf *conf = &dev->data->dev_conf;
2218 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2219 conf->link_speeds = ETH_LINK_SPEED_40G |
2220 ETH_LINK_SPEED_25G |
2221 ETH_LINK_SPEED_20G |
2222 ETH_LINK_SPEED_10G |
2224 ETH_LINK_SPEED_100M;
2226 speed = i40e_parse_link_speeds(conf->link_speeds);
2227 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2228 I40E_AQ_PHY_AN_ENABLED |
2229 I40E_AQ_PHY_LINK_ENABLED;
2231 return i40e_phy_conf_link(hw, abilities, speed, true);
2235 i40e_dev_start(struct rte_eth_dev *dev)
2237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_vsi *main_vsi = pf->main_vsi;
2241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243 uint32_t intr_vector = 0;
2244 struct i40e_vsi *vsi;
2246 hw->adapter_stopped = 0;
2248 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250 "Invalid link_speeds for port %u, autonegotiation disabled",
2251 dev->data->port_id);
2255 rte_intr_disable(intr_handle);
2257 if ((rte_intr_cap_multiple(intr_handle) ||
2258 !RTE_ETH_DEV_SRIOV(dev).active) &&
2259 dev->data->dev_conf.intr_conf.rxq != 0) {
2260 intr_vector = dev->data->nb_rx_queues;
2261 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2266 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2267 intr_handle->intr_vec =
2268 rte_zmalloc("intr_vec",
2269 dev->data->nb_rx_queues * sizeof(int),
2271 if (!intr_handle->intr_vec) {
2273 "Failed to allocate %d rx_queues intr_vec",
2274 dev->data->nb_rx_queues);
2279 /* Initialize VSI */
2280 ret = i40e_dev_rxtx_init(pf);
2281 if (ret != I40E_SUCCESS) {
2282 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2286 /* Map queues with MSIX interrupt */
2287 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2288 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2290 i40e_vsi_enable_queues_intr(main_vsi);
2292 /* Map VMDQ VSI queues with MSIX interrupt */
2293 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2294 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2295 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2296 I40E_ITR_INDEX_DEFAULT);
2297 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2300 /* enable FDIR MSIX interrupt */
2301 if (pf->fdir.fdir_vsi) {
2302 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2303 I40E_ITR_INDEX_NONE);
2304 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2307 /* Enable all queues which have been configured */
2308 ret = i40e_dev_switch_queues(pf, TRUE);
2309 if (ret != I40E_SUCCESS) {
2310 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2314 /* Enable receiving broadcast packets */
2315 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322 if (ret != I40E_SUCCESS)
2323 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2326 /* Enable the VLAN promiscuous mode. */
2328 for (i = 0; i < pf->vf_num; i++) {
2329 vsi = pf->vfs[i].vsi;
2330 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2335 /* Enable mac loopback mode */
2336 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2337 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2338 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2339 if (ret != I40E_SUCCESS) {
2340 PMD_DRV_LOG(ERR, "fail to set loopback link");
2345 /* Apply link configure */
2346 ret = i40e_apply_link_speed(dev);
2347 if (I40E_SUCCESS != ret) {
2348 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2352 if (!rte_intr_allow_others(intr_handle)) {
2353 rte_intr_callback_unregister(intr_handle,
2354 i40e_dev_interrupt_handler,
2356 /* configure and enable device interrupt */
2357 i40e_pf_config_irq0(hw, FALSE);
2358 i40e_pf_enable_irq0(hw);
2360 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362 "lsc won't enable because of no intr multiplex");
2364 ret = i40e_aq_set_phy_int_mask(hw,
2365 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2366 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2367 I40E_AQ_EVENT_MEDIA_NA), NULL);
2368 if (ret != I40E_SUCCESS)
2369 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371 /* Call get_link_info aq commond to enable/disable LSE */
2372 i40e_dev_link_update(dev, 0);
2375 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2376 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2377 i40e_dev_alarm_handler, dev);
2379 /* enable uio intr after callback register */
2380 rte_intr_enable(intr_handle);
2383 i40e_filter_restore(pf);
2385 if (pf->tm_conf.root && !pf->tm_conf.committed)
2386 PMD_DRV_LOG(WARNING,
2387 "please call hierarchy_commit() "
2388 "before starting the port");
2390 return I40E_SUCCESS;
2393 i40e_dev_switch_queues(pf, FALSE);
2394 i40e_dev_clear_queues(dev);
2400 i40e_dev_stop(struct rte_eth_dev *dev)
2402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 struct i40e_vsi *main_vsi = pf->main_vsi;
2405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2406 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2409 if (hw->adapter_stopped == 1)
2412 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2413 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2414 rte_intr_enable(intr_handle);
2417 /* Disable all queues */
2418 i40e_dev_switch_queues(pf, FALSE);
2420 /* un-map queues with interrupt registers */
2421 i40e_vsi_disable_queues_intr(main_vsi);
2422 i40e_vsi_queues_unbind_intr(main_vsi);
2424 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2425 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2426 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2429 if (pf->fdir.fdir_vsi) {
2430 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2431 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433 /* Clear all queues and release memory */
2434 i40e_dev_clear_queues(dev);
2437 i40e_dev_set_link_down(dev);
2439 if (!rte_intr_allow_others(intr_handle))
2440 /* resume to the default handler */
2441 rte_intr_callback_register(intr_handle,
2442 i40e_dev_interrupt_handler,
2445 /* Clean datapath event and queue/vec mapping */
2446 rte_intr_efd_disable(intr_handle);
2447 if (intr_handle->intr_vec) {
2448 rte_free(intr_handle->intr_vec);
2449 intr_handle->intr_vec = NULL;
2452 /* reset hierarchy commit */
2453 pf->tm_conf.committed = false;
2455 hw->adapter_stopped = 1;
2457 pf->adapter->rss_reta_updated = 0;
2461 i40e_dev_close(struct rte_eth_dev *dev)
2463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2467 struct i40e_mirror_rule *p_mirror;
2472 PMD_INIT_FUNC_TRACE();
2476 /* Remove all mirror rules */
2477 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2478 ret = i40e_aq_del_mirror_rule(hw,
2479 pf->main_vsi->veb->seid,
2480 p_mirror->rule_type,
2482 p_mirror->num_entries,
2485 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2486 "status = %d, aq_err = %d.", ret,
2487 hw->aq.asq_last_status);
2489 /* remove mirror software resource anyway */
2490 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492 pf->nb_mirror_rule--;
2495 i40e_dev_free_queues(dev);
2497 /* Disable interrupt */
2498 i40e_pf_disable_irq0(hw);
2499 rte_intr_disable(intr_handle);
2502 * Only legacy filter API needs the following fdir config. So when the
2503 * legacy filter API is deprecated, the following code should also be
2506 i40e_fdir_teardown(pf);
2508 /* shutdown and destroy the HMC */
2509 i40e_shutdown_lan_hmc(hw);
2511 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2512 i40e_vsi_release(pf->vmdq[i].vsi);
2513 pf->vmdq[i].vsi = NULL;
2518 /* release all the existing VSIs and VEBs */
2519 i40e_vsi_release(pf->main_vsi);
2521 /* shutdown the adminq */
2522 i40e_aq_queue_shutdown(hw, true);
2523 i40e_shutdown_adminq(hw);
2525 i40e_res_pool_destroy(&pf->qp_pool);
2526 i40e_res_pool_destroy(&pf->msix_pool);
2528 /* Disable flexible payload in global configuration */
2529 if (!pf->support_multi_driver)
2530 i40e_flex_payload_reg_set_default(hw);
2532 /* force a PF reset to clean anything leftover */
2533 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2534 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2535 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2536 I40E_WRITE_FLUSH(hw);
2538 hw->adapter_closed = 1;
2542 * Reset PF device only to re-initialize resources in PMD layer
2545 i40e_dev_reset(struct rte_eth_dev *dev)
2549 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2550 * its VF to make them align with it. The detailed notification
2551 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2552 * To avoid unexpected behavior in VF, currently reset of PF with
2553 * SR-IOV activation is not supported. It might be supported later.
2555 if (dev->data->sriov.active)
2558 ret = eth_i40e_dev_uninit(dev);
2562 ret = eth_i40e_dev_init(dev, NULL);
2568 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572 struct i40e_vsi *vsi = pf->main_vsi;
2575 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577 if (status != I40E_SUCCESS)
2578 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2580 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2582 if (status != I40E_SUCCESS)
2583 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2588 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592 struct i40e_vsi *vsi = pf->main_vsi;
2595 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2597 if (status != I40E_SUCCESS)
2598 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2600 /* must remain in all_multicast mode */
2601 if (dev->data->all_multicast == 1)
2604 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2606 if (status != I40E_SUCCESS)
2607 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2611 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 struct i40e_vsi *vsi = pf->main_vsi;
2618 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2619 if (ret != I40E_SUCCESS)
2620 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2624 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628 struct i40e_vsi *vsi = pf->main_vsi;
2631 if (dev->data->promiscuous == 1)
2632 return; /* must remain in all_multicast mode */
2634 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2635 vsi->seid, FALSE, NULL);
2636 if (ret != I40E_SUCCESS)
2637 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2641 * Set device link up.
2644 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2646 /* re-apply link speed setting */
2647 return i40e_apply_link_speed(dev);
2651 * Set device link down.
2654 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2656 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2657 uint8_t abilities = 0;
2658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2661 return i40e_phy_conf_link(hw, abilities, speed, false);
2664 static __rte_always_inline void
2665 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2667 /* Link status registers and values*/
2668 #define I40E_PRTMAC_LINKSTA 0x001E2420
2669 #define I40E_REG_LINK_UP 0x40000080
2670 #define I40E_PRTMAC_MACC 0x001E24E0
2671 #define I40E_REG_MACC_25GB 0x00020000
2672 #define I40E_REG_SPEED_MASK 0x38000000
2673 #define I40E_REG_SPEED_0 0x00000000
2674 #define I40E_REG_SPEED_1 0x08000000
2675 #define I40E_REG_SPEED_2 0x10000000
2676 #define I40E_REG_SPEED_3 0x18000000
2677 #define I40E_REG_SPEED_4 0x20000000
2678 uint32_t link_speed;
2681 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2682 link_speed = reg_val & I40E_REG_SPEED_MASK;
2683 reg_val &= I40E_REG_LINK_UP;
2684 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2686 if (unlikely(link->link_status == 0))
2689 /* Parse the link status */
2690 switch (link_speed) {
2691 case I40E_REG_SPEED_0:
2692 link->link_speed = ETH_SPEED_NUM_100M;
2694 case I40E_REG_SPEED_1:
2695 link->link_speed = ETH_SPEED_NUM_1G;
2697 case I40E_REG_SPEED_2:
2698 if (hw->mac.type == I40E_MAC_X722)
2699 link->link_speed = ETH_SPEED_NUM_2_5G;
2701 link->link_speed = ETH_SPEED_NUM_10G;
2703 case I40E_REG_SPEED_3:
2704 if (hw->mac.type == I40E_MAC_X722) {
2705 link->link_speed = ETH_SPEED_NUM_5G;
2707 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2709 if (reg_val & I40E_REG_MACC_25GB)
2710 link->link_speed = ETH_SPEED_NUM_25G;
2712 link->link_speed = ETH_SPEED_NUM_40G;
2715 case I40E_REG_SPEED_4:
2716 if (hw->mac.type == I40E_MAC_X722)
2717 link->link_speed = ETH_SPEED_NUM_10G;
2719 link->link_speed = ETH_SPEED_NUM_20G;
2722 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2727 static __rte_always_inline void
2728 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2729 bool enable_lse, int wait_to_complete)
2731 #define CHECK_INTERVAL 100 /* 100ms */
2732 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2733 uint32_t rep_cnt = MAX_REPEAT_TIME;
2734 struct i40e_link_status link_status;
2737 memset(&link_status, 0, sizeof(link_status));
2740 memset(&link_status, 0, sizeof(link_status));
2742 /* Get link status information from hardware */
2743 status = i40e_aq_get_link_info(hw, enable_lse,
2744 &link_status, NULL);
2745 if (unlikely(status != I40E_SUCCESS)) {
2746 link->link_speed = ETH_SPEED_NUM_100M;
2747 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2748 PMD_DRV_LOG(ERR, "Failed to get link info");
2752 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2753 if (!wait_to_complete || link->link_status)
2756 rte_delay_ms(CHECK_INTERVAL);
2757 } while (--rep_cnt);
2759 /* Parse the link status */
2760 switch (link_status.link_speed) {
2761 case I40E_LINK_SPEED_100MB:
2762 link->link_speed = ETH_SPEED_NUM_100M;
2764 case I40E_LINK_SPEED_1GB:
2765 link->link_speed = ETH_SPEED_NUM_1G;
2767 case I40E_LINK_SPEED_10GB:
2768 link->link_speed = ETH_SPEED_NUM_10G;
2770 case I40E_LINK_SPEED_20GB:
2771 link->link_speed = ETH_SPEED_NUM_20G;
2773 case I40E_LINK_SPEED_25GB:
2774 link->link_speed = ETH_SPEED_NUM_25G;
2776 case I40E_LINK_SPEED_40GB:
2777 link->link_speed = ETH_SPEED_NUM_40G;
2780 link->link_speed = ETH_SPEED_NUM_100M;
2786 i40e_dev_link_update(struct rte_eth_dev *dev,
2787 int wait_to_complete)
2789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790 struct rte_eth_link link;
2791 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2794 memset(&link, 0, sizeof(link));
2796 /* i40e uses full duplex only */
2797 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2798 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2799 ETH_LINK_SPEED_FIXED);
2801 if (!wait_to_complete && !enable_lse)
2802 update_link_reg(hw, &link);
2804 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2806 ret = rte_eth_linkstatus_set(dev, &link);
2807 i40e_notify_all_vfs_link_status(dev);
2812 /* Get all the statistics of a VSI */
2814 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2816 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2817 struct i40e_eth_stats *nes = &vsi->eth_stats;
2818 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2819 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2821 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2822 vsi->offset_loaded, &oes->rx_bytes,
2824 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2825 vsi->offset_loaded, &oes->rx_unicast,
2827 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2828 vsi->offset_loaded, &oes->rx_multicast,
2829 &nes->rx_multicast);
2830 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2831 vsi->offset_loaded, &oes->rx_broadcast,
2832 &nes->rx_broadcast);
2833 /* exclude CRC bytes */
2834 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2835 nes->rx_broadcast) * ETHER_CRC_LEN;
2837 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2838 &oes->rx_discards, &nes->rx_discards);
2839 /* GLV_REPC not supported */
2840 /* GLV_RMPC not supported */
2841 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2842 &oes->rx_unknown_protocol,
2843 &nes->rx_unknown_protocol);
2844 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2845 vsi->offset_loaded, &oes->tx_bytes,
2847 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2848 vsi->offset_loaded, &oes->tx_unicast,
2850 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2851 vsi->offset_loaded, &oes->tx_multicast,
2852 &nes->tx_multicast);
2853 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2854 vsi->offset_loaded, &oes->tx_broadcast,
2855 &nes->tx_broadcast);
2856 /* GLV_TDPC not supported */
2857 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2858 &oes->tx_errors, &nes->tx_errors);
2859 vsi->offset_loaded = true;
2861 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2863 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2864 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2865 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2866 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2867 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2868 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2869 nes->rx_unknown_protocol);
2870 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2871 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2872 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2873 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2874 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2875 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2876 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2881 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2884 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2885 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2887 /* Get rx/tx bytes of internal transfer packets */
2888 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2889 I40E_GLV_GORCL(hw->port),
2891 &pf->internal_stats_offset.rx_bytes,
2892 &pf->internal_stats.rx_bytes);
2894 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2895 I40E_GLV_GOTCL(hw->port),
2897 &pf->internal_stats_offset.tx_bytes,
2898 &pf->internal_stats.tx_bytes);
2899 /* Get total internal rx packet count */
2900 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2901 I40E_GLV_UPRCL(hw->port),
2903 &pf->internal_stats_offset.rx_unicast,
2904 &pf->internal_stats.rx_unicast);
2905 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2906 I40E_GLV_MPRCL(hw->port),
2908 &pf->internal_stats_offset.rx_multicast,
2909 &pf->internal_stats.rx_multicast);
2910 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2911 I40E_GLV_BPRCL(hw->port),
2913 &pf->internal_stats_offset.rx_broadcast,
2914 &pf->internal_stats.rx_broadcast);
2915 /* Get total internal tx packet count */
2916 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2917 I40E_GLV_UPTCL(hw->port),
2919 &pf->internal_stats_offset.tx_unicast,
2920 &pf->internal_stats.tx_unicast);
2921 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2922 I40E_GLV_MPTCL(hw->port),
2924 &pf->internal_stats_offset.tx_multicast,
2925 &pf->internal_stats.tx_multicast);
2926 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2927 I40E_GLV_BPTCL(hw->port),
2929 &pf->internal_stats_offset.tx_broadcast,
2930 &pf->internal_stats.tx_broadcast);
2932 /* exclude CRC size */
2933 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2934 pf->internal_stats.rx_multicast +
2935 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2937 /* Get statistics of struct i40e_eth_stats */
2938 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2939 I40E_GLPRT_GORCL(hw->port),
2940 pf->offset_loaded, &os->eth.rx_bytes,
2942 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2943 I40E_GLPRT_UPRCL(hw->port),
2944 pf->offset_loaded, &os->eth.rx_unicast,
2945 &ns->eth.rx_unicast);
2946 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2947 I40E_GLPRT_MPRCL(hw->port),
2948 pf->offset_loaded, &os->eth.rx_multicast,
2949 &ns->eth.rx_multicast);
2950 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2951 I40E_GLPRT_BPRCL(hw->port),
2952 pf->offset_loaded, &os->eth.rx_broadcast,
2953 &ns->eth.rx_broadcast);
2954 /* Workaround: CRC size should not be included in byte statistics,
2955 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2957 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2958 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2960 /* exclude internal rx bytes
2961 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2962 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2964 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2966 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2967 ns->eth.rx_bytes = 0;
2969 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2971 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2972 ns->eth.rx_unicast = 0;
2974 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2976 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2977 ns->eth.rx_multicast = 0;
2979 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2981 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2982 ns->eth.rx_broadcast = 0;
2984 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2986 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2987 pf->offset_loaded, &os->eth.rx_discards,
2988 &ns->eth.rx_discards);
2989 /* GLPRT_REPC not supported */
2990 /* GLPRT_RMPC not supported */
2991 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2993 &os->eth.rx_unknown_protocol,
2994 &ns->eth.rx_unknown_protocol);
2995 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2996 I40E_GLPRT_GOTCL(hw->port),
2997 pf->offset_loaded, &os->eth.tx_bytes,
2999 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3000 I40E_GLPRT_UPTCL(hw->port),
3001 pf->offset_loaded, &os->eth.tx_unicast,
3002 &ns->eth.tx_unicast);
3003 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3004 I40E_GLPRT_MPTCL(hw->port),
3005 pf->offset_loaded, &os->eth.tx_multicast,
3006 &ns->eth.tx_multicast);
3007 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3008 I40E_GLPRT_BPTCL(hw->port),
3009 pf->offset_loaded, &os->eth.tx_broadcast,
3010 &ns->eth.tx_broadcast);
3011 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3012 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3014 /* exclude internal tx bytes
3015 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3016 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3018 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3020 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3021 ns->eth.tx_bytes = 0;
3023 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3025 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3026 ns->eth.tx_unicast = 0;
3028 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3030 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3031 ns->eth.tx_multicast = 0;
3033 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3035 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3036 ns->eth.tx_broadcast = 0;
3038 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3040 /* GLPRT_TEPC not supported */
3042 /* additional port specific stats */
3043 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3044 pf->offset_loaded, &os->tx_dropped_link_down,
3045 &ns->tx_dropped_link_down);
3046 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3047 pf->offset_loaded, &os->crc_errors,
3049 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3050 pf->offset_loaded, &os->illegal_bytes,
3051 &ns->illegal_bytes);
3052 /* GLPRT_ERRBC not supported */
3053 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3054 pf->offset_loaded, &os->mac_local_faults,
3055 &ns->mac_local_faults);
3056 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3057 pf->offset_loaded, &os->mac_remote_faults,
3058 &ns->mac_remote_faults);
3059 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3060 pf->offset_loaded, &os->rx_length_errors,
3061 &ns->rx_length_errors);
3062 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3063 pf->offset_loaded, &os->link_xon_rx,
3065 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3066 pf->offset_loaded, &os->link_xoff_rx,
3068 for (i = 0; i < 8; i++) {
3069 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3071 &os->priority_xon_rx[i],
3072 &ns->priority_xon_rx[i]);
3073 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3075 &os->priority_xoff_rx[i],
3076 &ns->priority_xoff_rx[i]);
3078 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3079 pf->offset_loaded, &os->link_xon_tx,
3081 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3082 pf->offset_loaded, &os->link_xoff_tx,
3084 for (i = 0; i < 8; i++) {
3085 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3087 &os->priority_xon_tx[i],
3088 &ns->priority_xon_tx[i]);
3089 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3091 &os->priority_xoff_tx[i],
3092 &ns->priority_xoff_tx[i]);
3093 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3095 &os->priority_xon_2_xoff[i],
3096 &ns->priority_xon_2_xoff[i]);
3098 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3099 I40E_GLPRT_PRC64L(hw->port),
3100 pf->offset_loaded, &os->rx_size_64,
3102 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3103 I40E_GLPRT_PRC127L(hw->port),
3104 pf->offset_loaded, &os->rx_size_127,
3106 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3107 I40E_GLPRT_PRC255L(hw->port),
3108 pf->offset_loaded, &os->rx_size_255,
3110 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3111 I40E_GLPRT_PRC511L(hw->port),
3112 pf->offset_loaded, &os->rx_size_511,
3114 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3115 I40E_GLPRT_PRC1023L(hw->port),
3116 pf->offset_loaded, &os->rx_size_1023,
3118 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3119 I40E_GLPRT_PRC1522L(hw->port),
3120 pf->offset_loaded, &os->rx_size_1522,
3122 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3123 I40E_GLPRT_PRC9522L(hw->port),
3124 pf->offset_loaded, &os->rx_size_big,
3126 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3127 pf->offset_loaded, &os->rx_undersize,
3129 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3130 pf->offset_loaded, &os->rx_fragments,
3132 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3133 pf->offset_loaded, &os->rx_oversize,
3135 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3136 pf->offset_loaded, &os->rx_jabber,
3138 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3139 I40E_GLPRT_PTC64L(hw->port),
3140 pf->offset_loaded, &os->tx_size_64,
3142 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3143 I40E_GLPRT_PTC127L(hw->port),
3144 pf->offset_loaded, &os->tx_size_127,
3146 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3147 I40E_GLPRT_PTC255L(hw->port),
3148 pf->offset_loaded, &os->tx_size_255,
3150 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3151 I40E_GLPRT_PTC511L(hw->port),
3152 pf->offset_loaded, &os->tx_size_511,
3154 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3155 I40E_GLPRT_PTC1023L(hw->port),
3156 pf->offset_loaded, &os->tx_size_1023,
3158 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3159 I40E_GLPRT_PTC1522L(hw->port),
3160 pf->offset_loaded, &os->tx_size_1522,
3162 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3163 I40E_GLPRT_PTC9522L(hw->port),
3164 pf->offset_loaded, &os->tx_size_big,
3166 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3168 &os->fd_sb_match, &ns->fd_sb_match);
3169 /* GLPRT_MSPDC not supported */
3170 /* GLPRT_XEC not supported */
3172 pf->offset_loaded = true;
3175 i40e_update_vsi_stats(pf->main_vsi);
3178 /* Get all statistics of a port */
3180 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3182 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3183 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3185 struct i40e_vsi *vsi;
3188 /* call read registers - updates values, now write them to struct */
3189 i40e_read_stats_registers(pf, hw);
3191 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3192 pf->main_vsi->eth_stats.rx_multicast +
3193 pf->main_vsi->eth_stats.rx_broadcast -
3194 pf->main_vsi->eth_stats.rx_discards;
3195 stats->opackets = ns->eth.tx_unicast +
3196 ns->eth.tx_multicast +
3197 ns->eth.tx_broadcast;
3198 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3199 stats->obytes = ns->eth.tx_bytes;
3200 stats->oerrors = ns->eth.tx_errors +
3201 pf->main_vsi->eth_stats.tx_errors;
3204 stats->imissed = ns->eth.rx_discards +
3205 pf->main_vsi->eth_stats.rx_discards;
3206 stats->ierrors = ns->crc_errors +
3207 ns->rx_length_errors + ns->rx_undersize +
3208 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3211 for (i = 0; i < pf->vf_num; i++) {
3212 vsi = pf->vfs[i].vsi;
3213 i40e_update_vsi_stats(vsi);
3215 stats->ipackets += (vsi->eth_stats.rx_unicast +
3216 vsi->eth_stats.rx_multicast +
3217 vsi->eth_stats.rx_broadcast -
3218 vsi->eth_stats.rx_discards);
3219 stats->ibytes += vsi->eth_stats.rx_bytes;
3220 stats->oerrors += vsi->eth_stats.tx_errors;
3221 stats->imissed += vsi->eth_stats.rx_discards;
3225 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3226 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3227 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3228 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3229 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3230 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3231 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3232 ns->eth.rx_unknown_protocol);
3233 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3234 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3235 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3236 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3237 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3238 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3240 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3241 ns->tx_dropped_link_down);
3242 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3243 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3245 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3246 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3247 ns->mac_local_faults);
3248 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3249 ns->mac_remote_faults);
3250 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3251 ns->rx_length_errors);
3252 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3253 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3254 for (i = 0; i < 8; i++) {
3255 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3256 i, ns->priority_xon_rx[i]);
3257 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3258 i, ns->priority_xoff_rx[i]);
3260 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3261 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3262 for (i = 0; i < 8; i++) {
3263 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3264 i, ns->priority_xon_tx[i]);
3265 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3266 i, ns->priority_xoff_tx[i]);
3267 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3268 i, ns->priority_xon_2_xoff[i]);
3270 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3271 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3272 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3273 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3274 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3275 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3276 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3277 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3278 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3279 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3280 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3281 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3282 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3283 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3284 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3285 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3286 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3287 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3288 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3289 ns->mac_short_packet_dropped);
3290 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3291 ns->checksum_error);
3292 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3293 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3297 /* Reset the statistics */
3299 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3301 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3302 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304 /* Mark PF and VSI stats to update the offset, aka "reset" */
3305 pf->offset_loaded = false;
3307 pf->main_vsi->offset_loaded = false;
3309 /* read the stats, reading current register values into offset */
3310 i40e_read_stats_registers(pf, hw);
3314 i40e_xstats_calc_num(void)
3316 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3317 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3318 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3321 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3322 struct rte_eth_xstat_name *xstats_names,
3323 __rte_unused unsigned limit)
3328 if (xstats_names == NULL)
3329 return i40e_xstats_calc_num();
3331 /* Note: limit checked in rte_eth_xstats_names() */
3333 /* Get stats from i40e_eth_stats struct */
3334 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3335 strlcpy(xstats_names[count].name,
3336 rte_i40e_stats_strings[i].name,
3337 sizeof(xstats_names[count].name));
3341 /* Get individiual stats from i40e_hw_port struct */
3342 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3343 strlcpy(xstats_names[count].name,
3344 rte_i40e_hw_port_strings[i].name,
3345 sizeof(xstats_names[count].name));
3349 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3350 for (prio = 0; prio < 8; prio++) {
3351 snprintf(xstats_names[count].name,
3352 sizeof(xstats_names[count].name),
3353 "rx_priority%u_%s", prio,
3354 rte_i40e_rxq_prio_strings[i].name);
3359 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3360 for (prio = 0; prio < 8; prio++) {
3361 snprintf(xstats_names[count].name,
3362 sizeof(xstats_names[count].name),
3363 "tx_priority%u_%s", prio,
3364 rte_i40e_txq_prio_strings[i].name);
3372 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3375 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3376 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3377 unsigned i, count, prio;
3378 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3380 count = i40e_xstats_calc_num();
3384 i40e_read_stats_registers(pf, hw);
3391 /* Get stats from i40e_eth_stats struct */
3392 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3393 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3394 rte_i40e_stats_strings[i].offset);
3395 xstats[count].id = count;
3399 /* Get individiual stats from i40e_hw_port struct */
3400 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3401 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3402 rte_i40e_hw_port_strings[i].offset);
3403 xstats[count].id = count;
3407 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3408 for (prio = 0; prio < 8; prio++) {
3409 xstats[count].value =
3410 *(uint64_t *)(((char *)hw_stats) +
3411 rte_i40e_rxq_prio_strings[i].offset +
3412 (sizeof(uint64_t) * prio));
3413 xstats[count].id = count;
3418 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3419 for (prio = 0; prio < 8; prio++) {
3420 xstats[count].value =
3421 *(uint64_t *)(((char *)hw_stats) +
3422 rte_i40e_txq_prio_strings[i].offset +
3423 (sizeof(uint64_t) * prio));
3424 xstats[count].id = count;
3433 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3434 __rte_unused uint16_t queue_id,
3435 __rte_unused uint8_t stat_idx,
3436 __rte_unused uint8_t is_rx)
3438 PMD_INIT_FUNC_TRACE();
3444 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3446 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452 full_ver = hw->nvm.oem_ver;
3453 ver = (u8)(full_ver >> 24);
3454 build = (u16)((full_ver >> 8) & 0xffff);
3455 patch = (u8)(full_ver & 0xff);
3457 ret = snprintf(fw_version, fw_size,
3458 "%d.%d%d 0x%08x %d.%d.%d",
3459 ((hw->nvm.version >> 12) & 0xf),
3460 ((hw->nvm.version >> 4) & 0xff),
3461 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3464 ret += 1; /* add the size of '\0' */
3465 if (fw_size < (u32)ret)
3472 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3473 * the Rx data path does not hang if the FW LLDP is stopped.
3474 * return true if lldp need to stop
3475 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3478 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3481 char ver_str[64] = {0};
3482 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484 i40e_fw_version_get(dev, ver_str, 64);
3485 nvm_ver = atof(ver_str);
3486 if ((hw->mac.type == I40E_MAC_X722 ||
3487 hw->mac.type == I40E_MAC_X722_VF) &&
3488 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3490 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3497 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3499 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3500 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501 struct i40e_vsi *vsi = pf->main_vsi;
3502 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3504 dev_info->max_rx_queues = vsi->nb_qps;
3505 dev_info->max_tx_queues = vsi->nb_qps;
3506 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3507 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3508 dev_info->max_mac_addrs = vsi->max_macaddrs;
3509 dev_info->max_vfs = pci_dev->max_vfs;
3510 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3511 dev_info->min_mtu = ETHER_MIN_MTU;
3512 dev_info->rx_queue_offload_capa = 0;
3513 dev_info->rx_offload_capa =
3514 DEV_RX_OFFLOAD_VLAN_STRIP |
3515 DEV_RX_OFFLOAD_QINQ_STRIP |
3516 DEV_RX_OFFLOAD_IPV4_CKSUM |
3517 DEV_RX_OFFLOAD_UDP_CKSUM |
3518 DEV_RX_OFFLOAD_TCP_CKSUM |
3519 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3520 DEV_RX_OFFLOAD_KEEP_CRC |
3521 DEV_RX_OFFLOAD_SCATTER |
3522 DEV_RX_OFFLOAD_VLAN_EXTEND |
3523 DEV_RX_OFFLOAD_VLAN_FILTER |
3524 DEV_RX_OFFLOAD_JUMBO_FRAME;
3526 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3527 dev_info->tx_offload_capa =
3528 DEV_TX_OFFLOAD_VLAN_INSERT |
3529 DEV_TX_OFFLOAD_QINQ_INSERT |
3530 DEV_TX_OFFLOAD_IPV4_CKSUM |
3531 DEV_TX_OFFLOAD_UDP_CKSUM |
3532 DEV_TX_OFFLOAD_TCP_CKSUM |
3533 DEV_TX_OFFLOAD_SCTP_CKSUM |
3534 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3535 DEV_TX_OFFLOAD_TCP_TSO |
3536 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3537 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3538 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3539 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3540 DEV_TX_OFFLOAD_MULTI_SEGS |
3541 dev_info->tx_queue_offload_capa;
3542 dev_info->dev_capa =
3543 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3544 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3546 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3548 dev_info->reta_size = pf->hash_lut_size;
3549 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3551 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3553 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3554 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3555 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3557 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3562 dev_info->default_txconf = (struct rte_eth_txconf) {
3564 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3565 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3566 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3568 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3569 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3573 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3574 .nb_max = I40E_MAX_RING_DESC,
3575 .nb_min = I40E_MIN_RING_DESC,
3576 .nb_align = I40E_ALIGN_RING_DESC,
3579 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3580 .nb_max = I40E_MAX_RING_DESC,
3581 .nb_min = I40E_MIN_RING_DESC,
3582 .nb_align = I40E_ALIGN_RING_DESC,
3583 .nb_seg_max = I40E_TX_MAX_SEG,
3584 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3587 if (pf->flags & I40E_FLAG_VMDQ) {
3588 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3589 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3590 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3591 pf->max_nb_vmdq_vsi;
3592 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3593 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3594 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3597 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3599 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3600 dev_info->default_rxportconf.nb_queues = 2;
3601 dev_info->default_txportconf.nb_queues = 2;
3602 if (dev->data->nb_rx_queues == 1)
3603 dev_info->default_rxportconf.ring_size = 2048;
3605 dev_info->default_rxportconf.ring_size = 1024;
3606 if (dev->data->nb_tx_queues == 1)
3607 dev_info->default_txportconf.ring_size = 1024;
3609 dev_info->default_txportconf.ring_size = 512;
3611 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3613 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3614 dev_info->default_rxportconf.nb_queues = 1;
3615 dev_info->default_txportconf.nb_queues = 1;
3616 dev_info->default_rxportconf.ring_size = 256;
3617 dev_info->default_txportconf.ring_size = 256;
3620 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3621 dev_info->default_rxportconf.nb_queues = 1;
3622 dev_info->default_txportconf.nb_queues = 1;
3623 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3624 dev_info->default_rxportconf.ring_size = 512;
3625 dev_info->default_txportconf.ring_size = 256;
3627 dev_info->default_rxportconf.ring_size = 256;
3628 dev_info->default_txportconf.ring_size = 256;
3631 dev_info->default_rxportconf.burst_size = 32;
3632 dev_info->default_txportconf.burst_size = 32;
3636 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3638 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3639 struct i40e_vsi *vsi = pf->main_vsi;
3640 PMD_INIT_FUNC_TRACE();
3643 return i40e_vsi_add_vlan(vsi, vlan_id);
3645 return i40e_vsi_delete_vlan(vsi, vlan_id);
3649 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3650 enum rte_vlan_type vlan_type,
3651 uint16_t tpid, int qinq)
3653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656 uint16_t reg_id = 3;
3660 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3664 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3666 if (ret != I40E_SUCCESS) {
3668 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3673 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3676 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3677 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3678 if (reg_r == reg_w) {
3679 PMD_DRV_LOG(DEBUG, "No need to write");
3683 ret = i40e_aq_debug_write_global_register(hw,
3684 I40E_GL_SWT_L2TAGCTRL(reg_id),
3686 if (ret != I40E_SUCCESS) {
3688 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3693 "Global register 0x%08x is changed with value 0x%08x",
3694 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3700 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3701 enum rte_vlan_type vlan_type,
3704 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3706 int qinq = dev->data->dev_conf.rxmode.offloads &
3707 DEV_RX_OFFLOAD_VLAN_EXTEND;
3710 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3711 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3712 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3714 "Unsupported vlan type.");
3718 if (pf->support_multi_driver) {
3719 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3723 /* 802.1ad frames ability is added in NVM API 1.7*/
3724 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3726 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3727 hw->first_tag = rte_cpu_to_le_16(tpid);
3728 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3729 hw->second_tag = rte_cpu_to_le_16(tpid);
3731 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3732 hw->second_tag = rte_cpu_to_le_16(tpid);
3734 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3735 if (ret != I40E_SUCCESS) {
3737 "Set switch config failed aq_err: %d",
3738 hw->aq.asq_last_status);
3742 /* If NVM API < 1.7, keep the register setting */
3743 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3750 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3752 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3753 struct i40e_vsi *vsi = pf->main_vsi;
3754 struct rte_eth_rxmode *rxmode;
3756 rxmode = &dev->data->dev_conf.rxmode;
3757 if (mask & ETH_VLAN_FILTER_MASK) {
3758 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3759 i40e_vsi_config_vlan_filter(vsi, TRUE);
3761 i40e_vsi_config_vlan_filter(vsi, FALSE);
3764 if (mask & ETH_VLAN_STRIP_MASK) {
3765 /* Enable or disable VLAN stripping */
3766 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3767 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3769 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3772 if (mask & ETH_VLAN_EXTEND_MASK) {
3773 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3774 i40e_vsi_config_double_vlan(vsi, TRUE);
3775 /* Set global registers with default ethertype. */
3776 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3778 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3782 i40e_vsi_config_double_vlan(vsi, FALSE);
3789 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3790 __rte_unused uint16_t queue,
3791 __rte_unused int on)
3793 PMD_INIT_FUNC_TRACE();
3797 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3799 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3800 struct i40e_vsi *vsi = pf->main_vsi;
3801 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3802 struct i40e_vsi_vlan_pvid_info info;
3804 memset(&info, 0, sizeof(info));
3807 info.config.pvid = pvid;
3809 info.config.reject.tagged =
3810 data->dev_conf.txmode.hw_vlan_reject_tagged;
3811 info.config.reject.untagged =
3812 data->dev_conf.txmode.hw_vlan_reject_untagged;
3815 return i40e_vsi_vlan_pvid_set(vsi, &info);
3819 i40e_dev_led_on(struct rte_eth_dev *dev)
3821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3822 uint32_t mode = i40e_led_get(hw);
3825 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3831 i40e_dev_led_off(struct rte_eth_dev *dev)
3833 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834 uint32_t mode = i40e_led_get(hw);
3837 i40e_led_set(hw, 0, false);
3843 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3846 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3848 fc_conf->pause_time = pf->fc_conf.pause_time;
3850 /* read out from register, in case they are modified by other port */
3851 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3852 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3853 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3854 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3856 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3857 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3859 /* Return current mode according to actual setting*/
3860 switch (hw->fc.current_mode) {
3862 fc_conf->mode = RTE_FC_FULL;
3864 case I40E_FC_TX_PAUSE:
3865 fc_conf->mode = RTE_FC_TX_PAUSE;
3867 case I40E_FC_RX_PAUSE:
3868 fc_conf->mode = RTE_FC_RX_PAUSE;
3872 fc_conf->mode = RTE_FC_NONE;
3879 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3881 uint32_t mflcn_reg, fctrl_reg, reg;
3882 uint32_t max_high_water;
3883 uint8_t i, aq_failure;
3887 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3888 [RTE_FC_NONE] = I40E_FC_NONE,
3889 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3890 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3891 [RTE_FC_FULL] = I40E_FC_FULL
3894 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3896 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3897 if ((fc_conf->high_water > max_high_water) ||
3898 (fc_conf->high_water < fc_conf->low_water)) {
3900 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3905 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3906 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3907 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3909 pf->fc_conf.pause_time = fc_conf->pause_time;
3910 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3911 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3913 PMD_INIT_FUNC_TRACE();
3915 /* All the link flow control related enable/disable register
3916 * configuration is handle by the F/W
3918 err = i40e_set_fc(hw, &aq_failure, true);
3922 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3923 /* Configure flow control refresh threshold,
3924 * the value for stat_tx_pause_refresh_timer[8]
3925 * is used for global pause operation.
3929 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3930 pf->fc_conf.pause_time);
3932 /* configure the timer value included in transmitted pause
3934 * the value for stat_tx_pause_quanta[8] is used for global
3937 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3938 pf->fc_conf.pause_time);
3940 fctrl_reg = I40E_READ_REG(hw,
3941 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3943 if (fc_conf->mac_ctrl_frame_fwd != 0)
3944 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3946 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3948 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3951 /* Configure pause time (2 TCs per register) */
3952 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3953 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3954 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3956 /* Configure flow control refresh threshold value */
3957 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3958 pf->fc_conf.pause_time / 2);
3960 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3962 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3963 *depending on configuration
3965 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3966 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3967 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3969 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3970 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3973 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3976 if (!pf->support_multi_driver) {
3977 /* config water marker both based on the packets and bytes */
3978 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3979 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3980 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3981 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3982 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3983 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3984 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3985 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3987 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3988 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3992 "Water marker configuration is not supported.");
3995 I40E_WRITE_FLUSH(hw);
4001 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4002 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4004 PMD_INIT_FUNC_TRACE();
4009 /* Add a MAC address, and update filters */
4011 i40e_macaddr_add(struct rte_eth_dev *dev,
4012 struct ether_addr *mac_addr,
4013 __rte_unused uint32_t index,
4016 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4017 struct i40e_mac_filter_info mac_filter;
4018 struct i40e_vsi *vsi;
4019 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4022 /* If VMDQ not enabled or configured, return */
4023 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4024 !pf->nb_cfg_vmdq_vsi)) {
4025 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4026 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4031 if (pool > pf->nb_cfg_vmdq_vsi) {
4032 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4033 pool, pf->nb_cfg_vmdq_vsi);
4037 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
4038 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4039 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4041 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4046 vsi = pf->vmdq[pool - 1].vsi;
4048 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4049 if (ret != I40E_SUCCESS) {
4050 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4056 /* Remove a MAC address, and update filters */
4058 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4060 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4061 struct i40e_vsi *vsi;
4062 struct rte_eth_dev_data *data = dev->data;
4063 struct ether_addr *macaddr;
4068 macaddr = &(data->mac_addrs[index]);
4070 pool_sel = dev->data->mac_pool_sel[index];
4072 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4073 if (pool_sel & (1ULL << i)) {
4077 /* No VMDQ pool enabled or configured */
4078 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4079 (i > pf->nb_cfg_vmdq_vsi)) {
4081 "No VMDQ pool enabled/configured");
4084 vsi = pf->vmdq[i - 1].vsi;
4086 ret = i40e_vsi_delete_mac(vsi, macaddr);
4089 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4096 /* Set perfect match or hash match of MAC and VLAN for a VF */
4098 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4099 struct rte_eth_mac_filter *filter,
4103 struct i40e_mac_filter_info mac_filter;
4104 struct ether_addr old_mac;
4105 struct ether_addr *new_mac;
4106 struct i40e_pf_vf *vf = NULL;
4111 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4114 hw = I40E_PF_TO_HW(pf);
4116 if (filter == NULL) {
4117 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4121 new_mac = &filter->mac_addr;
4123 if (is_zero_ether_addr(new_mac)) {
4124 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4128 vf_id = filter->dst_id;
4130 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4131 PMD_DRV_LOG(ERR, "Invalid argument.");
4134 vf = &pf->vfs[vf_id];
4136 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4137 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4142 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4143 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4145 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4148 mac_filter.filter_type = filter->filter_type;
4149 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4150 if (ret != I40E_SUCCESS) {
4151 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4154 ether_addr_copy(new_mac, &pf->dev_addr);
4156 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4158 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4159 if (ret != I40E_SUCCESS) {
4160 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4164 /* Clear device address as it has been removed */
4165 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4166 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4172 /* MAC filter handle */
4174 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4177 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4178 struct rte_eth_mac_filter *filter;
4179 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4180 int ret = I40E_NOT_SUPPORTED;
4182 filter = (struct rte_eth_mac_filter *)(arg);
4184 switch (filter_op) {
4185 case RTE_ETH_FILTER_NOP:
4188 case RTE_ETH_FILTER_ADD:
4189 i40e_pf_disable_irq0(hw);
4191 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4192 i40e_pf_enable_irq0(hw);
4194 case RTE_ETH_FILTER_DELETE:
4195 i40e_pf_disable_irq0(hw);
4197 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4198 i40e_pf_enable_irq0(hw);
4201 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4202 ret = I40E_ERR_PARAM;
4210 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4212 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4213 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4220 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4221 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4222 vsi->type != I40E_VSI_SRIOV,
4225 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4229 uint32_t *lut_dw = (uint32_t *)lut;
4230 uint16_t i, lut_size_dw = lut_size / 4;
4232 if (vsi->type == I40E_VSI_SRIOV) {
4233 for (i = 0; i <= lut_size_dw; i++) {
4234 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4235 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4238 for (i = 0; i < lut_size_dw; i++)
4239 lut_dw[i] = I40E_READ_REG(hw,
4248 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4257 pf = I40E_VSI_TO_PF(vsi);
4258 hw = I40E_VSI_TO_HW(vsi);
4260 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4261 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4262 vsi->type != I40E_VSI_SRIOV,
4265 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4269 uint32_t *lut_dw = (uint32_t *)lut;
4270 uint16_t i, lut_size_dw = lut_size / 4;
4272 if (vsi->type == I40E_VSI_SRIOV) {
4273 for (i = 0; i < lut_size_dw; i++)
4276 I40E_VFQF_HLUT1(i, vsi->user_param),
4279 for (i = 0; i < lut_size_dw; i++)
4280 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4283 I40E_WRITE_FLUSH(hw);
4290 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4291 struct rte_eth_rss_reta_entry64 *reta_conf,
4294 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4295 uint16_t i, lut_size = pf->hash_lut_size;
4296 uint16_t idx, shift;
4300 if (reta_size != lut_size ||
4301 reta_size > ETH_RSS_RETA_SIZE_512) {
4303 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4304 reta_size, lut_size);
4308 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4310 PMD_DRV_LOG(ERR, "No memory can be allocated");
4313 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4316 for (i = 0; i < reta_size; i++) {
4317 idx = i / RTE_RETA_GROUP_SIZE;
4318 shift = i % RTE_RETA_GROUP_SIZE;
4319 if (reta_conf[idx].mask & (1ULL << shift))
4320 lut[i] = reta_conf[idx].reta[shift];
4322 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4324 pf->adapter->rss_reta_updated = 1;
4333 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4334 struct rte_eth_rss_reta_entry64 *reta_conf,
4337 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4338 uint16_t i, lut_size = pf->hash_lut_size;
4339 uint16_t idx, shift;
4343 if (reta_size != lut_size ||
4344 reta_size > ETH_RSS_RETA_SIZE_512) {
4346 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4347 reta_size, lut_size);
4351 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4353 PMD_DRV_LOG(ERR, "No memory can be allocated");
4357 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4360 for (i = 0; i < reta_size; i++) {
4361 idx = i / RTE_RETA_GROUP_SIZE;
4362 shift = i % RTE_RETA_GROUP_SIZE;
4363 if (reta_conf[idx].mask & (1ULL << shift))
4364 reta_conf[idx].reta[shift] = lut[i];
4374 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4375 * @hw: pointer to the HW structure
4376 * @mem: pointer to mem struct to fill out
4377 * @size: size of memory requested
4378 * @alignment: what to align the allocation to
4380 enum i40e_status_code
4381 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4382 struct i40e_dma_mem *mem,
4386 const struct rte_memzone *mz = NULL;
4387 char z_name[RTE_MEMZONE_NAMESIZE];
4390 return I40E_ERR_PARAM;
4392 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4393 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4394 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4396 return I40E_ERR_NO_MEMORY;
4401 mem->zone = (const void *)mz;
4403 "memzone %s allocated with physical address: %"PRIu64,
4406 return I40E_SUCCESS;
4410 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4411 * @hw: pointer to the HW structure
4412 * @mem: ptr to mem struct to free
4414 enum i40e_status_code
4415 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4416 struct i40e_dma_mem *mem)
4419 return I40E_ERR_PARAM;
4422 "memzone %s to be freed with physical address: %"PRIu64,
4423 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4424 rte_memzone_free((const struct rte_memzone *)mem->zone);
4429 return I40E_SUCCESS;
4433 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4434 * @hw: pointer to the HW structure
4435 * @mem: pointer to mem struct to fill out
4436 * @size: size of memory requested
4438 enum i40e_status_code
4439 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4440 struct i40e_virt_mem *mem,
4444 return I40E_ERR_PARAM;
4447 mem->va = rte_zmalloc("i40e", size, 0);
4450 return I40E_SUCCESS;
4452 return I40E_ERR_NO_MEMORY;
4456 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4457 * @hw: pointer to the HW structure
4458 * @mem: pointer to mem struct to free
4460 enum i40e_status_code
4461 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4462 struct i40e_virt_mem *mem)
4465 return I40E_ERR_PARAM;
4470 return I40E_SUCCESS;
4474 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4476 rte_spinlock_init(&sp->spinlock);
4480 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4482 rte_spinlock_lock(&sp->spinlock);
4486 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4488 rte_spinlock_unlock(&sp->spinlock);
4492 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4498 * Get the hardware capabilities, which will be parsed
4499 * and saved into struct i40e_hw.
4502 i40e_get_cap(struct i40e_hw *hw)
4504 struct i40e_aqc_list_capabilities_element_resp *buf;
4505 uint16_t len, size = 0;
4508 /* Calculate a huge enough buff for saving response data temporarily */
4509 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4510 I40E_MAX_CAP_ELE_NUM;
4511 buf = rte_zmalloc("i40e", len, 0);
4513 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4514 return I40E_ERR_NO_MEMORY;
4517 /* Get, parse the capabilities and save it to hw */
4518 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4519 i40e_aqc_opc_list_func_capabilities, NULL);
4520 if (ret != I40E_SUCCESS)
4521 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4523 /* Free the temporary buffer after being used */
4529 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4531 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4539 pf = (struct i40e_pf *)opaque;
4543 num = strtoul(value, &end, 0);
4544 if (errno != 0 || end == value || *end != 0) {
4545 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4546 "kept the value = %hu", value, pf->vf_nb_qp_max);
4550 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4551 pf->vf_nb_qp_max = (uint16_t)num;
4553 /* here return 0 to make next valid same argument work */
4554 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4555 "power of 2 and equal or less than 16 !, Now it is "
4556 "kept the value = %hu", num, pf->vf_nb_qp_max);
4561 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4563 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4564 struct rte_kvargs *kvlist;
4567 /* set default queue number per VF as 4 */
4568 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4570 if (dev->device->devargs == NULL)
4573 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4577 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4578 if (!kvargs_count) {
4579 rte_kvargs_free(kvlist);
4583 if (kvargs_count > 1)
4584 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4585 "the first invalid or last valid one is used !",
4586 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4588 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4589 i40e_pf_parse_vf_queue_number_handler, pf);
4591 rte_kvargs_free(kvlist);
4597 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4600 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4601 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4602 uint16_t qp_count = 0, vsi_count = 0;
4604 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4605 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4609 i40e_pf_config_vf_rxq_number(dev);
4611 /* Add the parameter init for LFC */
4612 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4613 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4614 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4616 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4617 pf->max_num_vsi = hw->func_caps.num_vsis;
4618 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4619 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4621 /* FDir queue/VSI allocation */
4622 pf->fdir_qp_offset = 0;
4623 if (hw->func_caps.fd) {
4624 pf->flags |= I40E_FLAG_FDIR;
4625 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4627 pf->fdir_nb_qps = 0;
4629 qp_count += pf->fdir_nb_qps;
4632 /* LAN queue/VSI allocation */
4633 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4634 if (!hw->func_caps.rss) {
4637 pf->flags |= I40E_FLAG_RSS;
4638 if (hw->mac.type == I40E_MAC_X722)
4639 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4640 pf->lan_nb_qps = pf->lan_nb_qp_max;
4642 qp_count += pf->lan_nb_qps;
4645 /* VF queue/VSI allocation */
4646 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4647 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4648 pf->flags |= I40E_FLAG_SRIOV;
4649 pf->vf_nb_qps = pf->vf_nb_qp_max;
4650 pf->vf_num = pci_dev->max_vfs;
4652 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4653 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4658 qp_count += pf->vf_nb_qps * pf->vf_num;
4659 vsi_count += pf->vf_num;
4661 /* VMDq queue/VSI allocation */
4662 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4663 pf->vmdq_nb_qps = 0;
4664 pf->max_nb_vmdq_vsi = 0;
4665 if (hw->func_caps.vmdq) {
4666 if (qp_count < hw->func_caps.num_tx_qp &&
4667 vsi_count < hw->func_caps.num_vsis) {
4668 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4669 qp_count) / pf->vmdq_nb_qp_max;
4671 /* Limit the maximum number of VMDq vsi to the maximum
4672 * ethdev can support
4674 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4675 hw->func_caps.num_vsis - vsi_count);
4676 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4678 if (pf->max_nb_vmdq_vsi) {
4679 pf->flags |= I40E_FLAG_VMDQ;
4680 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4682 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4683 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4684 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4687 "No enough queues left for VMDq");
4690 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4693 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4694 vsi_count += pf->max_nb_vmdq_vsi;
4696 if (hw->func_caps.dcb)
4697 pf->flags |= I40E_FLAG_DCB;
4699 if (qp_count > hw->func_caps.num_tx_qp) {
4701 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4702 qp_count, hw->func_caps.num_tx_qp);
4705 if (vsi_count > hw->func_caps.num_vsis) {
4707 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4708 vsi_count, hw->func_caps.num_vsis);
4716 i40e_pf_get_switch_config(struct i40e_pf *pf)
4718 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4719 struct i40e_aqc_get_switch_config_resp *switch_config;
4720 struct i40e_aqc_switch_config_element_resp *element;
4721 uint16_t start_seid = 0, num_reported;
4724 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4725 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4726 if (!switch_config) {
4727 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4731 /* Get the switch configurations */
4732 ret = i40e_aq_get_switch_config(hw, switch_config,
4733 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4734 if (ret != I40E_SUCCESS) {
4735 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4738 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4739 if (num_reported != 1) { /* The number should be 1 */
4740 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4744 /* Parse the switch configuration elements */
4745 element = &(switch_config->element[0]);
4746 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4747 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4748 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4750 PMD_DRV_LOG(INFO, "Unknown element type");
4753 rte_free(switch_config);
4759 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4762 struct pool_entry *entry;
4764 if (pool == NULL || num == 0)
4767 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4768 if (entry == NULL) {
4769 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4773 /* queue heap initialize */
4774 pool->num_free = num;
4775 pool->num_alloc = 0;
4777 LIST_INIT(&pool->alloc_list);
4778 LIST_INIT(&pool->free_list);
4780 /* Initialize element */
4784 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4789 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4791 struct pool_entry *entry, *next_entry;
4796 for (entry = LIST_FIRST(&pool->alloc_list);
4797 entry && (next_entry = LIST_NEXT(entry, next), 1);
4798 entry = next_entry) {
4799 LIST_REMOVE(entry, next);
4803 for (entry = LIST_FIRST(&pool->free_list);
4804 entry && (next_entry = LIST_NEXT(entry, next), 1);
4805 entry = next_entry) {
4806 LIST_REMOVE(entry, next);
4811 pool->num_alloc = 0;
4813 LIST_INIT(&pool->alloc_list);
4814 LIST_INIT(&pool->free_list);
4818 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4821 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4822 uint32_t pool_offset;
4826 PMD_DRV_LOG(ERR, "Invalid parameter");
4830 pool_offset = base - pool->base;
4831 /* Lookup in alloc list */
4832 LIST_FOREACH(entry, &pool->alloc_list, next) {
4833 if (entry->base == pool_offset) {
4834 valid_entry = entry;
4835 LIST_REMOVE(entry, next);
4840 /* Not find, return */
4841 if (valid_entry == NULL) {
4842 PMD_DRV_LOG(ERR, "Failed to find entry");
4847 * Found it, move it to free list and try to merge.
4848 * In order to make merge easier, always sort it by qbase.
4849 * Find adjacent prev and last entries.
4852 LIST_FOREACH(entry, &pool->free_list, next) {
4853 if (entry->base > valid_entry->base) {
4861 /* Try to merge with next one*/
4863 /* Merge with next one */
4864 if (valid_entry->base + valid_entry->len == next->base) {
4865 next->base = valid_entry->base;
4866 next->len += valid_entry->len;
4867 rte_free(valid_entry);
4874 /* Merge with previous one */
4875 if (prev->base + prev->len == valid_entry->base) {
4876 prev->len += valid_entry->len;
4877 /* If it merge with next one, remove next node */
4879 LIST_REMOVE(valid_entry, next);
4880 rte_free(valid_entry);
4882 rte_free(valid_entry);
4888 /* Not find any entry to merge, insert */
4891 LIST_INSERT_AFTER(prev, valid_entry, next);
4892 else if (next != NULL)
4893 LIST_INSERT_BEFORE(next, valid_entry, next);
4894 else /* It's empty list, insert to head */
4895 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4898 pool->num_free += valid_entry->len;
4899 pool->num_alloc -= valid_entry->len;
4905 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4908 struct pool_entry *entry, *valid_entry;
4910 if (pool == NULL || num == 0) {
4911 PMD_DRV_LOG(ERR, "Invalid parameter");
4915 if (pool->num_free < num) {
4916 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4917 num, pool->num_free);
4922 /* Lookup in free list and find most fit one */
4923 LIST_FOREACH(entry, &pool->free_list, next) {
4924 if (entry->len >= num) {
4926 if (entry->len == num) {
4927 valid_entry = entry;
4930 if (valid_entry == NULL || valid_entry->len > entry->len)
4931 valid_entry = entry;
4935 /* Not find one to satisfy the request, return */
4936 if (valid_entry == NULL) {
4937 PMD_DRV_LOG(ERR, "No valid entry found");
4941 * The entry have equal queue number as requested,
4942 * remove it from alloc_list.
4944 if (valid_entry->len == num) {
4945 LIST_REMOVE(valid_entry, next);
4948 * The entry have more numbers than requested,
4949 * create a new entry for alloc_list and minus its
4950 * queue base and number in free_list.
4952 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4953 if (entry == NULL) {
4955 "Failed to allocate memory for resource pool");
4958 entry->base = valid_entry->base;
4960 valid_entry->base += num;
4961 valid_entry->len -= num;
4962 valid_entry = entry;
4965 /* Insert it into alloc list, not sorted */
4966 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4968 pool->num_free -= valid_entry->len;
4969 pool->num_alloc += valid_entry->len;
4971 return valid_entry->base + pool->base;
4975 * bitmap_is_subset - Check whether src2 is subset of src1
4978 bitmap_is_subset(uint8_t src1, uint8_t src2)
4980 return !((src1 ^ src2) & src2);
4983 static enum i40e_status_code
4984 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4986 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4988 /* If DCB is not supported, only default TC is supported */
4989 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4990 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4991 return I40E_NOT_SUPPORTED;
4994 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4996 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4997 hw->func_caps.enabled_tcmap, enabled_tcmap);
4998 return I40E_NOT_SUPPORTED;
5000 return I40E_SUCCESS;
5004 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5005 struct i40e_vsi_vlan_pvid_info *info)
5008 struct i40e_vsi_context ctxt;
5009 uint8_t vlan_flags = 0;
5012 if (vsi == NULL || info == NULL) {
5013 PMD_DRV_LOG(ERR, "invalid parameters");
5014 return I40E_ERR_PARAM;
5018 vsi->info.pvid = info->config.pvid;
5020 * If insert pvid is enabled, only tagged pkts are
5021 * allowed to be sent out.
5023 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5024 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5027 if (info->config.reject.tagged == 0)
5028 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5030 if (info->config.reject.untagged == 0)
5031 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5033 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5034 I40E_AQ_VSI_PVLAN_MODE_MASK);
5035 vsi->info.port_vlan_flags |= vlan_flags;
5036 vsi->info.valid_sections =
5037 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5038 memset(&ctxt, 0, sizeof(ctxt));
5039 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5040 ctxt.seid = vsi->seid;
5042 hw = I40E_VSI_TO_HW(vsi);
5043 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5044 if (ret != I40E_SUCCESS)
5045 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5051 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5053 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5055 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5057 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5058 if (ret != I40E_SUCCESS)
5062 PMD_DRV_LOG(ERR, "seid not valid");
5066 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5067 tc_bw_data.tc_valid_bits = enabled_tcmap;
5068 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5069 tc_bw_data.tc_bw_credits[i] =
5070 (enabled_tcmap & (1 << i)) ? 1 : 0;
5072 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5073 if (ret != I40E_SUCCESS) {
5074 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5078 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5079 sizeof(vsi->info.qs_handle));
5080 return I40E_SUCCESS;
5083 static enum i40e_status_code
5084 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5085 struct i40e_aqc_vsi_properties_data *info,
5086 uint8_t enabled_tcmap)
5088 enum i40e_status_code ret;
5089 int i, total_tc = 0;
5090 uint16_t qpnum_per_tc, bsf, qp_idx;
5092 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5093 if (ret != I40E_SUCCESS)
5096 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5097 if (enabled_tcmap & (1 << i))
5101 vsi->enabled_tc = enabled_tcmap;
5103 /* Number of queues per enabled TC */
5104 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5105 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5106 bsf = rte_bsf32(qpnum_per_tc);
5108 /* Adjust the queue number to actual queues that can be applied */
5109 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5110 vsi->nb_qps = qpnum_per_tc * total_tc;
5113 * Configure TC and queue mapping parameters, for enabled TC,
5114 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5115 * default queue will serve it.
5118 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5119 if (vsi->enabled_tc & (1 << i)) {
5120 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5121 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5122 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5123 qp_idx += qpnum_per_tc;
5125 info->tc_mapping[i] = 0;
5128 /* Associate queue number with VSI */
5129 if (vsi->type == I40E_VSI_SRIOV) {
5130 info->mapping_flags |=
5131 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5132 for (i = 0; i < vsi->nb_qps; i++)
5133 info->queue_mapping[i] =
5134 rte_cpu_to_le_16(vsi->base_queue + i);
5136 info->mapping_flags |=
5137 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5138 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5140 info->valid_sections |=
5141 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5143 return I40E_SUCCESS;
5147 i40e_veb_release(struct i40e_veb *veb)
5149 struct i40e_vsi *vsi;
5155 if (!TAILQ_EMPTY(&veb->head)) {
5156 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5159 /* associate_vsi field is NULL for floating VEB */
5160 if (veb->associate_vsi != NULL) {
5161 vsi = veb->associate_vsi;
5162 hw = I40E_VSI_TO_HW(vsi);
5164 vsi->uplink_seid = veb->uplink_seid;
5167 veb->associate_pf->main_vsi->floating_veb = NULL;
5168 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5171 i40e_aq_delete_element(hw, veb->seid, NULL);
5173 return I40E_SUCCESS;
5177 static struct i40e_veb *
5178 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5180 struct i40e_veb *veb;
5186 "veb setup failed, associated PF shouldn't null");
5189 hw = I40E_PF_TO_HW(pf);
5191 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5193 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5197 veb->associate_vsi = vsi;
5198 veb->associate_pf = pf;
5199 TAILQ_INIT(&veb->head);
5200 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5202 /* create floating veb if vsi is NULL */
5204 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5205 I40E_DEFAULT_TCMAP, false,
5206 &veb->seid, false, NULL);
5208 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5209 true, &veb->seid, false, NULL);
5212 if (ret != I40E_SUCCESS) {
5213 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5214 hw->aq.asq_last_status);
5217 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5219 /* get statistics index */
5220 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5221 &veb->stats_idx, NULL, NULL, NULL);
5222 if (ret != I40E_SUCCESS) {
5223 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5224 hw->aq.asq_last_status);
5227 /* Get VEB bandwidth, to be implemented */
5228 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5230 vsi->uplink_seid = veb->seid;
5239 i40e_vsi_release(struct i40e_vsi *vsi)
5243 struct i40e_vsi_list *vsi_list;
5246 struct i40e_mac_filter *f;
5247 uint16_t user_param;
5250 return I40E_SUCCESS;
5255 user_param = vsi->user_param;
5257 pf = I40E_VSI_TO_PF(vsi);
5258 hw = I40E_VSI_TO_HW(vsi);
5260 /* VSI has child to attach, release child first */
5262 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5263 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5266 i40e_veb_release(vsi->veb);
5269 if (vsi->floating_veb) {
5270 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5271 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5276 /* Remove all macvlan filters of the VSI */
5277 i40e_vsi_remove_all_macvlan_filter(vsi);
5278 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5281 if (vsi->type != I40E_VSI_MAIN &&
5282 ((vsi->type != I40E_VSI_SRIOV) ||
5283 !pf->floating_veb_list[user_param])) {
5284 /* Remove vsi from parent's sibling list */
5285 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5286 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5287 return I40E_ERR_PARAM;
5289 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5290 &vsi->sib_vsi_list, list);
5292 /* Remove all switch element of the VSI */
5293 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5294 if (ret != I40E_SUCCESS)
5295 PMD_DRV_LOG(ERR, "Failed to delete element");
5298 if ((vsi->type == I40E_VSI_SRIOV) &&
5299 pf->floating_veb_list[user_param]) {
5300 /* Remove vsi from parent's sibling list */
5301 if (vsi->parent_vsi == NULL ||
5302 vsi->parent_vsi->floating_veb == NULL) {
5303 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5304 return I40E_ERR_PARAM;
5306 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5307 &vsi->sib_vsi_list, list);
5309 /* Remove all switch element of the VSI */
5310 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5311 if (ret != I40E_SUCCESS)
5312 PMD_DRV_LOG(ERR, "Failed to delete element");
5315 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5317 if (vsi->type != I40E_VSI_SRIOV)
5318 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5321 return I40E_SUCCESS;
5325 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5327 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5328 struct i40e_aqc_remove_macvlan_element_data def_filter;
5329 struct i40e_mac_filter_info filter;
5332 if (vsi->type != I40E_VSI_MAIN)
5333 return I40E_ERR_CONFIG;
5334 memset(&def_filter, 0, sizeof(def_filter));
5335 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5337 def_filter.vlan_tag = 0;
5338 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5339 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5340 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5341 if (ret != I40E_SUCCESS) {
5342 struct i40e_mac_filter *f;
5343 struct ether_addr *mac;
5346 "Cannot remove the default macvlan filter");
5347 /* It needs to add the permanent mac into mac list */
5348 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5350 PMD_DRV_LOG(ERR, "failed to allocate memory");
5351 return I40E_ERR_NO_MEMORY;
5353 mac = &f->mac_info.mac_addr;
5354 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5356 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5357 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5362 rte_memcpy(&filter.mac_addr,
5363 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5364 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5365 return i40e_vsi_add_mac(vsi, &filter);
5369 * i40e_vsi_get_bw_config - Query VSI BW Information
5370 * @vsi: the VSI to be queried
5372 * Returns 0 on success, negative value on failure
5374 static enum i40e_status_code
5375 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5377 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5378 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5379 struct i40e_hw *hw = &vsi->adapter->hw;
5384 memset(&bw_config, 0, sizeof(bw_config));
5385 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5386 if (ret != I40E_SUCCESS) {
5387 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5388 hw->aq.asq_last_status);
5392 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5393 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5394 &ets_sla_config, NULL);
5395 if (ret != I40E_SUCCESS) {
5397 "VSI failed to get TC bandwdith configuration %u",
5398 hw->aq.asq_last_status);
5402 /* store and print out BW info */
5403 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5404 vsi->bw_info.bw_max = bw_config.max_bw;
5405 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5406 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5407 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5408 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5410 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5411 vsi->bw_info.bw_ets_share_credits[i] =
5412 ets_sla_config.share_credits[i];
5413 vsi->bw_info.bw_ets_credits[i] =
5414 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5415 /* 4 bits per TC, 4th bit is reserved */
5416 vsi->bw_info.bw_ets_max[i] =
5417 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5418 RTE_LEN2MASK(3, uint8_t));
5419 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5420 vsi->bw_info.bw_ets_share_credits[i]);
5421 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5422 vsi->bw_info.bw_ets_credits[i]);
5423 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5424 vsi->bw_info.bw_ets_max[i]);
5427 return I40E_SUCCESS;
5430 /* i40e_enable_pf_lb
5431 * @pf: pointer to the pf structure
5433 * allow loopback on pf
5436 i40e_enable_pf_lb(struct i40e_pf *pf)
5438 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5439 struct i40e_vsi_context ctxt;
5442 /* Use the FW API if FW >= v5.0 */
5443 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5444 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5448 memset(&ctxt, 0, sizeof(ctxt));
5449 ctxt.seid = pf->main_vsi_seid;
5450 ctxt.pf_num = hw->pf_id;
5451 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5453 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5454 ret, hw->aq.asq_last_status);
5457 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5458 ctxt.info.valid_sections =
5459 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5460 ctxt.info.switch_id |=
5461 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5463 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5465 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5466 hw->aq.asq_last_status);
5471 i40e_vsi_setup(struct i40e_pf *pf,
5472 enum i40e_vsi_type type,
5473 struct i40e_vsi *uplink_vsi,
5474 uint16_t user_param)
5476 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5477 struct i40e_vsi *vsi;
5478 struct i40e_mac_filter_info filter;
5480 struct i40e_vsi_context ctxt;
5481 struct ether_addr broadcast =
5482 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5484 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5485 uplink_vsi == NULL) {
5487 "VSI setup failed, VSI link shouldn't be NULL");
5491 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5493 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5498 * 1.type is not MAIN and uplink vsi is not NULL
5499 * If uplink vsi didn't setup VEB, create one first under veb field
5500 * 2.type is SRIOV and the uplink is NULL
5501 * If floating VEB is NULL, create one veb under floating veb field
5504 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5505 uplink_vsi->veb == NULL) {
5506 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5508 if (uplink_vsi->veb == NULL) {
5509 PMD_DRV_LOG(ERR, "VEB setup failed");
5512 /* set ALLOWLOOPBACk on pf, when veb is created */
5513 i40e_enable_pf_lb(pf);
5516 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5517 pf->main_vsi->floating_veb == NULL) {
5518 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5520 if (pf->main_vsi->floating_veb == NULL) {
5521 PMD_DRV_LOG(ERR, "VEB setup failed");
5526 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5528 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5531 TAILQ_INIT(&vsi->mac_list);
5533 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5534 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5535 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5536 vsi->user_param = user_param;
5537 vsi->vlan_anti_spoof_on = 0;
5538 vsi->vlan_filter_on = 0;
5539 /* Allocate queues */
5540 switch (vsi->type) {
5541 case I40E_VSI_MAIN :
5542 vsi->nb_qps = pf->lan_nb_qps;
5544 case I40E_VSI_SRIOV :
5545 vsi->nb_qps = pf->vf_nb_qps;
5547 case I40E_VSI_VMDQ2:
5548 vsi->nb_qps = pf->vmdq_nb_qps;
5551 vsi->nb_qps = pf->fdir_nb_qps;
5557 * The filter status descriptor is reported in rx queue 0,
5558 * while the tx queue for fdir filter programming has no
5559 * such constraints, can be non-zero queues.
5560 * To simplify it, choose FDIR vsi use queue 0 pair.
5561 * To make sure it will use queue 0 pair, queue allocation
5562 * need be done before this function is called
5564 if (type != I40E_VSI_FDIR) {
5565 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5567 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5571 vsi->base_queue = ret;
5573 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5575 /* VF has MSIX interrupt in VF range, don't allocate here */
5576 if (type == I40E_VSI_MAIN) {
5577 if (pf->support_multi_driver) {
5578 /* If support multi-driver, need to use INT0 instead of
5579 * allocating from msix pool. The Msix pool is init from
5580 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5581 * to 1 without calling i40e_res_pool_alloc.
5586 ret = i40e_res_pool_alloc(&pf->msix_pool,
5587 RTE_MIN(vsi->nb_qps,
5588 RTE_MAX_RXTX_INTR_VEC_ID));
5591 "VSI MAIN %d get heap failed %d",
5593 goto fail_queue_alloc;
5595 vsi->msix_intr = ret;
5596 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5597 RTE_MAX_RXTX_INTR_VEC_ID);
5599 } else if (type != I40E_VSI_SRIOV) {
5600 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5602 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5603 goto fail_queue_alloc;
5605 vsi->msix_intr = ret;
5613 if (type == I40E_VSI_MAIN) {
5614 /* For main VSI, no need to add since it's default one */
5615 vsi->uplink_seid = pf->mac_seid;
5616 vsi->seid = pf->main_vsi_seid;
5617 /* Bind queues with specific MSIX interrupt */
5619 * Needs 2 interrupt at least, one for misc cause which will
5620 * enabled from OS side, Another for queues binding the
5621 * interrupt from device side only.
5624 /* Get default VSI parameters from hardware */
5625 memset(&ctxt, 0, sizeof(ctxt));
5626 ctxt.seid = vsi->seid;
5627 ctxt.pf_num = hw->pf_id;
5628 ctxt.uplink_seid = vsi->uplink_seid;
5630 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5631 if (ret != I40E_SUCCESS) {
5632 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5633 goto fail_msix_alloc;
5635 rte_memcpy(&vsi->info, &ctxt.info,
5636 sizeof(struct i40e_aqc_vsi_properties_data));
5637 vsi->vsi_id = ctxt.vsi_number;
5638 vsi->info.valid_sections = 0;
5640 /* Configure tc, enabled TC0 only */
5641 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5643 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5644 goto fail_msix_alloc;
5647 /* TC, queue mapping */
5648 memset(&ctxt, 0, sizeof(ctxt));
5649 vsi->info.valid_sections |=
5650 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5651 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5652 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5653 rte_memcpy(&ctxt.info, &vsi->info,
5654 sizeof(struct i40e_aqc_vsi_properties_data));
5655 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5656 I40E_DEFAULT_TCMAP);
5657 if (ret != I40E_SUCCESS) {
5659 "Failed to configure TC queue mapping");
5660 goto fail_msix_alloc;
5662 ctxt.seid = vsi->seid;
5663 ctxt.pf_num = hw->pf_id;
5664 ctxt.uplink_seid = vsi->uplink_seid;
5667 /* Update VSI parameters */
5668 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5669 if (ret != I40E_SUCCESS) {
5670 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5671 goto fail_msix_alloc;
5674 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5675 sizeof(vsi->info.tc_mapping));
5676 rte_memcpy(&vsi->info.queue_mapping,
5677 &ctxt.info.queue_mapping,
5678 sizeof(vsi->info.queue_mapping));
5679 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5680 vsi->info.valid_sections = 0;
5682 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5686 * Updating default filter settings are necessary to prevent
5687 * reception of tagged packets.
5688 * Some old firmware configurations load a default macvlan
5689 * filter which accepts both tagged and untagged packets.
5690 * The updating is to use a normal filter instead if needed.
5691 * For NVM 4.2.2 or after, the updating is not needed anymore.
5692 * The firmware with correct configurations load the default
5693 * macvlan filter which is expected and cannot be removed.
5695 i40e_update_default_filter_setting(vsi);
5696 i40e_config_qinq(hw, vsi);
5697 } else if (type == I40E_VSI_SRIOV) {
5698 memset(&ctxt, 0, sizeof(ctxt));
5700 * For other VSI, the uplink_seid equals to uplink VSI's
5701 * uplink_seid since they share same VEB
5703 if (uplink_vsi == NULL)
5704 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5706 vsi->uplink_seid = uplink_vsi->uplink_seid;
5707 ctxt.pf_num = hw->pf_id;
5708 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5709 ctxt.uplink_seid = vsi->uplink_seid;
5710 ctxt.connection_type = 0x1;
5711 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5713 /* Use the VEB configuration if FW >= v5.0 */
5714 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5715 /* Configure switch ID */
5716 ctxt.info.valid_sections |=
5717 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5718 ctxt.info.switch_id =
5719 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5722 /* Configure port/vlan */
5723 ctxt.info.valid_sections |=
5724 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5725 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5726 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5727 hw->func_caps.enabled_tcmap);
5728 if (ret != I40E_SUCCESS) {
5730 "Failed to configure TC queue mapping");
5731 goto fail_msix_alloc;
5734 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5735 ctxt.info.valid_sections |=
5736 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5738 * Since VSI is not created yet, only configure parameter,
5739 * will add vsi below.
5742 i40e_config_qinq(hw, vsi);
5743 } else if (type == I40E_VSI_VMDQ2) {
5744 memset(&ctxt, 0, sizeof(ctxt));
5746 * For other VSI, the uplink_seid equals to uplink VSI's
5747 * uplink_seid since they share same VEB
5749 vsi->uplink_seid = uplink_vsi->uplink_seid;
5750 ctxt.pf_num = hw->pf_id;
5752 ctxt.uplink_seid = vsi->uplink_seid;
5753 ctxt.connection_type = 0x1;
5754 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5756 ctxt.info.valid_sections |=
5757 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5758 /* user_param carries flag to enable loop back */
5760 ctxt.info.switch_id =
5761 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5762 ctxt.info.switch_id |=
5763 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5766 /* Configure port/vlan */
5767 ctxt.info.valid_sections |=
5768 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5769 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5770 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5771 I40E_DEFAULT_TCMAP);
5772 if (ret != I40E_SUCCESS) {
5774 "Failed to configure TC queue mapping");
5775 goto fail_msix_alloc;
5777 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5778 ctxt.info.valid_sections |=
5779 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5780 } else if (type == I40E_VSI_FDIR) {
5781 memset(&ctxt, 0, sizeof(ctxt));
5782 vsi->uplink_seid = uplink_vsi->uplink_seid;
5783 ctxt.pf_num = hw->pf_id;
5785 ctxt.uplink_seid = vsi->uplink_seid;
5786 ctxt.connection_type = 0x1; /* regular data port */
5787 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5788 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5789 I40E_DEFAULT_TCMAP);
5790 if (ret != I40E_SUCCESS) {
5792 "Failed to configure TC queue mapping.");
5793 goto fail_msix_alloc;
5795 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5796 ctxt.info.valid_sections |=
5797 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5799 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5800 goto fail_msix_alloc;
5803 if (vsi->type != I40E_VSI_MAIN) {
5804 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5805 if (ret != I40E_SUCCESS) {
5806 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5807 hw->aq.asq_last_status);
5808 goto fail_msix_alloc;
5810 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5811 vsi->info.valid_sections = 0;
5812 vsi->seid = ctxt.seid;
5813 vsi->vsi_id = ctxt.vsi_number;
5814 vsi->sib_vsi_list.vsi = vsi;
5815 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5816 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5817 &vsi->sib_vsi_list, list);
5819 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5820 &vsi->sib_vsi_list, list);
5824 /* MAC/VLAN configuration */
5825 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5826 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5828 ret = i40e_vsi_add_mac(vsi, &filter);
5829 if (ret != I40E_SUCCESS) {
5830 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5831 goto fail_msix_alloc;
5834 /* Get VSI BW information */
5835 i40e_vsi_get_bw_config(vsi);
5838 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5840 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5846 /* Configure vlan filter on or off */
5848 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5851 struct i40e_mac_filter *f;
5853 struct i40e_mac_filter_info *mac_filter;
5854 enum rte_mac_filter_type desired_filter;
5855 int ret = I40E_SUCCESS;
5858 /* Filter to match MAC and VLAN */
5859 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5861 /* Filter to match only MAC */
5862 desired_filter = RTE_MAC_PERFECT_MATCH;
5867 mac_filter = rte_zmalloc("mac_filter_info_data",
5868 num * sizeof(*mac_filter), 0);
5869 if (mac_filter == NULL) {
5870 PMD_DRV_LOG(ERR, "failed to allocate memory");
5871 return I40E_ERR_NO_MEMORY;
5876 /* Remove all existing mac */
5877 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5878 mac_filter[i] = f->mac_info;
5879 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5881 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5882 on ? "enable" : "disable");
5888 /* Override with new filter */
5889 for (i = 0; i < num; i++) {
5890 mac_filter[i].filter_type = desired_filter;
5891 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5893 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5894 on ? "enable" : "disable");
5900 rte_free(mac_filter);
5904 /* Configure vlan stripping on or off */
5906 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5908 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5909 struct i40e_vsi_context ctxt;
5911 int ret = I40E_SUCCESS;
5913 /* Check if it has been already on or off */
5914 if (vsi->info.valid_sections &
5915 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5917 if ((vsi->info.port_vlan_flags &
5918 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5919 return 0; /* already on */
5921 if ((vsi->info.port_vlan_flags &
5922 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5923 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5924 return 0; /* already off */
5929 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5931 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5932 vsi->info.valid_sections =
5933 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5934 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5935 vsi->info.port_vlan_flags |= vlan_flags;
5936 ctxt.seid = vsi->seid;
5937 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5938 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5940 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5941 on ? "enable" : "disable");
5947 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5949 struct rte_eth_dev_data *data = dev->data;
5953 /* Apply vlan offload setting */
5954 mask = ETH_VLAN_STRIP_MASK |
5955 ETH_VLAN_FILTER_MASK |
5956 ETH_VLAN_EXTEND_MASK;
5957 ret = i40e_vlan_offload_set(dev, mask);
5959 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5963 /* Apply pvid setting */
5964 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5965 data->dev_conf.txmode.hw_vlan_insert_pvid);
5967 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5973 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5975 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5977 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5981 i40e_update_flow_control(struct i40e_hw *hw)
5983 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5984 struct i40e_link_status link_status;
5985 uint32_t rxfc = 0, txfc = 0, reg;
5989 memset(&link_status, 0, sizeof(link_status));
5990 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5991 if (ret != I40E_SUCCESS) {
5992 PMD_DRV_LOG(ERR, "Failed to get link status information");
5993 goto write_reg; /* Disable flow control */
5996 an_info = hw->phy.link_info.an_info;
5997 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5998 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5999 ret = I40E_ERR_NOT_READY;
6000 goto write_reg; /* Disable flow control */
6003 * If link auto negotiation is enabled, flow control needs to
6004 * be configured according to it
6006 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6007 case I40E_LINK_PAUSE_RXTX:
6010 hw->fc.current_mode = I40E_FC_FULL;
6012 case I40E_AQ_LINK_PAUSE_RX:
6014 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6016 case I40E_AQ_LINK_PAUSE_TX:
6018 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6021 hw->fc.current_mode = I40E_FC_NONE;
6026 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6027 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6028 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6029 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6030 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6031 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6038 i40e_pf_setup(struct i40e_pf *pf)
6040 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6041 struct i40e_filter_control_settings settings;
6042 struct i40e_vsi *vsi;
6045 /* Clear all stats counters */
6046 pf->offset_loaded = FALSE;
6047 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6048 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6049 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6050 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6052 ret = i40e_pf_get_switch_config(pf);
6053 if (ret != I40E_SUCCESS) {
6054 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6058 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6060 PMD_INIT_LOG(WARNING,
6061 "failed to allocate switch domain for device %d", ret);
6063 if (pf->flags & I40E_FLAG_FDIR) {
6064 /* make queue allocated first, let FDIR use queue pair 0*/
6065 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6066 if (ret != I40E_FDIR_QUEUE_ID) {
6068 "queue allocation fails for FDIR: ret =%d",
6070 pf->flags &= ~I40E_FLAG_FDIR;
6073 /* main VSI setup */
6074 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6076 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6077 return I40E_ERR_NOT_READY;
6081 /* Configure filter control */
6082 memset(&settings, 0, sizeof(settings));
6083 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6084 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6085 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6086 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6088 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6089 hw->func_caps.rss_table_size);
6090 return I40E_ERR_PARAM;
6092 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6093 hw->func_caps.rss_table_size);
6094 pf->hash_lut_size = hw->func_caps.rss_table_size;
6096 /* Enable ethtype and macvlan filters */
6097 settings.enable_ethtype = TRUE;
6098 settings.enable_macvlan = TRUE;
6099 ret = i40e_set_filter_control(hw, &settings);
6101 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6104 /* Update flow control according to the auto negotiation */
6105 i40e_update_flow_control(hw);
6107 return I40E_SUCCESS;
6111 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6117 * Set or clear TX Queue Disable flags,
6118 * which is required by hardware.
6120 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6121 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6123 /* Wait until the request is finished */
6124 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6125 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6126 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6127 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6128 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6134 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6135 return I40E_SUCCESS; /* already on, skip next steps */
6137 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6138 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6140 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6141 return I40E_SUCCESS; /* already off, skip next steps */
6142 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6144 /* Write the register */
6145 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6146 /* Check the result */
6147 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6148 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6149 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6151 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6152 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6155 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6156 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6160 /* Check if it is timeout */
6161 if (j >= I40E_CHK_Q_ENA_COUNT) {
6162 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6163 (on ? "enable" : "disable"), q_idx);
6164 return I40E_ERR_TIMEOUT;
6167 return I40E_SUCCESS;
6170 /* Swith on or off the tx queues */
6172 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6174 struct rte_eth_dev_data *dev_data = pf->dev_data;
6175 struct i40e_tx_queue *txq;
6176 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6180 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6181 txq = dev_data->tx_queues[i];
6182 /* Don't operate the queue if not configured or
6183 * if starting only per queue */
6184 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6187 ret = i40e_dev_tx_queue_start(dev, i);
6189 ret = i40e_dev_tx_queue_stop(dev, i);
6190 if ( ret != I40E_SUCCESS)
6194 return I40E_SUCCESS;
6198 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6203 /* Wait until the request is finished */
6204 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6205 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6206 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6207 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6208 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6213 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6214 return I40E_SUCCESS; /* Already on, skip next steps */
6215 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6217 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6218 return I40E_SUCCESS; /* Already off, skip next steps */
6219 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6222 /* Write the register */
6223 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6224 /* Check the result */
6225 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6226 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6227 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6229 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6230 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6233 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6234 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6239 /* Check if it is timeout */
6240 if (j >= I40E_CHK_Q_ENA_COUNT) {
6241 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6242 (on ? "enable" : "disable"), q_idx);
6243 return I40E_ERR_TIMEOUT;
6246 return I40E_SUCCESS;
6248 /* Switch on or off the rx queues */
6250 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6252 struct rte_eth_dev_data *dev_data = pf->dev_data;
6253 struct i40e_rx_queue *rxq;
6254 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6258 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6259 rxq = dev_data->rx_queues[i];
6260 /* Don't operate the queue if not configured or
6261 * if starting only per queue */
6262 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6265 ret = i40e_dev_rx_queue_start(dev, i);
6267 ret = i40e_dev_rx_queue_stop(dev, i);
6268 if (ret != I40E_SUCCESS)
6272 return I40E_SUCCESS;
6275 /* Switch on or off all the rx/tx queues */
6277 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6282 /* enable rx queues before enabling tx queues */
6283 ret = i40e_dev_switch_rx_queues(pf, on);
6285 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6288 ret = i40e_dev_switch_tx_queues(pf, on);
6290 /* Stop tx queues before stopping rx queues */
6291 ret = i40e_dev_switch_tx_queues(pf, on);
6293 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6296 ret = i40e_dev_switch_rx_queues(pf, on);
6302 /* Initialize VSI for TX */
6304 i40e_dev_tx_init(struct i40e_pf *pf)
6306 struct rte_eth_dev_data *data = pf->dev_data;
6308 uint32_t ret = I40E_SUCCESS;
6309 struct i40e_tx_queue *txq;
6311 for (i = 0; i < data->nb_tx_queues; i++) {
6312 txq = data->tx_queues[i];
6313 if (!txq || !txq->q_set)
6315 ret = i40e_tx_queue_init(txq);
6316 if (ret != I40E_SUCCESS)
6319 if (ret == I40E_SUCCESS)
6320 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6326 /* Initialize VSI for RX */
6328 i40e_dev_rx_init(struct i40e_pf *pf)
6330 struct rte_eth_dev_data *data = pf->dev_data;
6331 int ret = I40E_SUCCESS;
6333 struct i40e_rx_queue *rxq;
6335 i40e_pf_config_mq_rx(pf);
6336 for (i = 0; i < data->nb_rx_queues; i++) {
6337 rxq = data->rx_queues[i];
6338 if (!rxq || !rxq->q_set)
6341 ret = i40e_rx_queue_init(rxq);
6342 if (ret != I40E_SUCCESS) {
6344 "Failed to do RX queue initialization");
6348 if (ret == I40E_SUCCESS)
6349 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6356 i40e_dev_rxtx_init(struct i40e_pf *pf)
6360 err = i40e_dev_tx_init(pf);
6362 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6365 err = i40e_dev_rx_init(pf);
6367 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6375 i40e_vmdq_setup(struct rte_eth_dev *dev)
6377 struct rte_eth_conf *conf = &dev->data->dev_conf;
6378 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6379 int i, err, conf_vsis, j, loop;
6380 struct i40e_vsi *vsi;
6381 struct i40e_vmdq_info *vmdq_info;
6382 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6383 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6386 * Disable interrupt to avoid message from VF. Furthermore, it will
6387 * avoid race condition in VSI creation/destroy.
6389 i40e_pf_disable_irq0(hw);
6391 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6392 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6396 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6397 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6398 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6399 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6400 pf->max_nb_vmdq_vsi);
6404 if (pf->vmdq != NULL) {
6405 PMD_INIT_LOG(INFO, "VMDQ already configured");
6409 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6410 sizeof(*vmdq_info) * conf_vsis, 0);
6412 if (pf->vmdq == NULL) {
6413 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6417 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6419 /* Create VMDQ VSI */
6420 for (i = 0; i < conf_vsis; i++) {
6421 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6422 vmdq_conf->enable_loop_back);
6424 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6428 vmdq_info = &pf->vmdq[i];
6430 vmdq_info->vsi = vsi;
6432 pf->nb_cfg_vmdq_vsi = conf_vsis;
6434 /* Configure Vlan */
6435 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6436 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6437 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6438 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6439 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6440 vmdq_conf->pool_map[i].vlan_id, j);
6442 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6443 vmdq_conf->pool_map[i].vlan_id);
6445 PMD_INIT_LOG(ERR, "Failed to add vlan");
6453 i40e_pf_enable_irq0(hw);
6458 for (i = 0; i < conf_vsis; i++)
6459 if (pf->vmdq[i].vsi == NULL)
6462 i40e_vsi_release(pf->vmdq[i].vsi);
6466 i40e_pf_enable_irq0(hw);
6471 i40e_stat_update_32(struct i40e_hw *hw,
6479 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6483 if (new_data >= *offset)
6484 *stat = (uint64_t)(new_data - *offset);
6486 *stat = (uint64_t)((new_data +
6487 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6491 i40e_stat_update_48(struct i40e_hw *hw,
6500 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6501 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6502 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6507 if (new_data >= *offset)
6508 *stat = new_data - *offset;
6510 *stat = (uint64_t)((new_data +
6511 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6513 *stat &= I40E_48_BIT_MASK;
6518 i40e_pf_disable_irq0(struct i40e_hw *hw)
6520 /* Disable all interrupt types */
6521 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6522 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6523 I40E_WRITE_FLUSH(hw);
6528 i40e_pf_enable_irq0(struct i40e_hw *hw)
6530 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6531 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6532 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6533 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6534 I40E_WRITE_FLUSH(hw);
6538 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6540 /* read pending request and disable first */
6541 i40e_pf_disable_irq0(hw);
6542 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6543 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6544 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6547 /* Link no queues with irq0 */
6548 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6549 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6553 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6555 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6556 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6559 uint32_t index, offset, val;
6564 * Try to find which VF trigger a reset, use absolute VF id to access
6565 * since the reg is global register.
6567 for (i = 0; i < pf->vf_num; i++) {
6568 abs_vf_id = hw->func_caps.vf_base_id + i;
6569 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6570 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6571 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6572 /* VFR event occurred */
6573 if (val & (0x1 << offset)) {
6576 /* Clear the event first */
6577 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6579 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6581 * Only notify a VF reset event occurred,
6582 * don't trigger another SW reset
6584 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6585 if (ret != I40E_SUCCESS)
6586 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6592 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6597 for (i = 0; i < pf->vf_num; i++)
6598 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6602 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6605 struct i40e_arq_event_info info;
6606 uint16_t pending, opcode;
6609 info.buf_len = I40E_AQ_BUF_SZ;
6610 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6611 if (!info.msg_buf) {
6612 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6618 ret = i40e_clean_arq_element(hw, &info, &pending);
6620 if (ret != I40E_SUCCESS) {
6622 "Failed to read msg from AdminQ, aq_err: %u",
6623 hw->aq.asq_last_status);
6626 opcode = rte_le_to_cpu_16(info.desc.opcode);
6629 case i40e_aqc_opc_send_msg_to_pf:
6630 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6631 i40e_pf_host_handle_vf_msg(dev,
6632 rte_le_to_cpu_16(info.desc.retval),
6633 rte_le_to_cpu_32(info.desc.cookie_high),
6634 rte_le_to_cpu_32(info.desc.cookie_low),
6638 case i40e_aqc_opc_get_link_status:
6639 ret = i40e_dev_link_update(dev, 0);
6641 _rte_eth_dev_callback_process(dev,
6642 RTE_ETH_EVENT_INTR_LSC, NULL);
6645 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6650 rte_free(info.msg_buf);
6654 * Interrupt handler triggered by NIC for handling
6655 * specific interrupt.
6658 * Pointer to interrupt handle.
6660 * The address of parameter (struct rte_eth_dev *) regsitered before.
6666 i40e_dev_interrupt_handler(void *param)
6668 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6669 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6672 /* Disable interrupt */
6673 i40e_pf_disable_irq0(hw);
6675 /* read out interrupt causes */
6676 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6678 /* No interrupt event indicated */
6679 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6680 PMD_DRV_LOG(INFO, "No interrupt event");
6683 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6684 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6685 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6686 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6687 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6688 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6689 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6690 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6691 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6692 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6693 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6694 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6695 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6696 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6698 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6699 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6700 i40e_dev_handle_vfr_event(dev);
6702 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6703 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6704 i40e_dev_handle_aq_msg(dev);
6708 /* Enable interrupt */
6709 i40e_pf_enable_irq0(hw);
6713 i40e_dev_alarm_handler(void *param)
6715 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6716 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6719 /* Disable interrupt */
6720 i40e_pf_disable_irq0(hw);
6722 /* read out interrupt causes */
6723 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6725 /* No interrupt event indicated */
6726 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6728 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6729 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6730 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6731 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6732 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6733 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6734 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6735 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6736 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6737 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6738 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6739 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6740 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6741 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6743 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6744 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6745 i40e_dev_handle_vfr_event(dev);
6747 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6748 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6749 i40e_dev_handle_aq_msg(dev);
6753 /* Enable interrupt */
6754 i40e_pf_enable_irq0(hw);
6755 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6756 i40e_dev_alarm_handler, dev);
6760 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6761 struct i40e_macvlan_filter *filter,
6764 int ele_num, ele_buff_size;
6765 int num, actual_num, i;
6767 int ret = I40E_SUCCESS;
6768 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6769 struct i40e_aqc_add_macvlan_element_data *req_list;
6771 if (filter == NULL || total == 0)
6772 return I40E_ERR_PARAM;
6773 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6774 ele_buff_size = hw->aq.asq_buf_size;
6776 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6777 if (req_list == NULL) {
6778 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6779 return I40E_ERR_NO_MEMORY;
6784 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6785 memset(req_list, 0, ele_buff_size);
6787 for (i = 0; i < actual_num; i++) {
6788 rte_memcpy(req_list[i].mac_addr,
6789 &filter[num + i].macaddr, ETH_ADDR_LEN);
6790 req_list[i].vlan_tag =
6791 rte_cpu_to_le_16(filter[num + i].vlan_id);
6793 switch (filter[num + i].filter_type) {
6794 case RTE_MAC_PERFECT_MATCH:
6795 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6796 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6798 case RTE_MACVLAN_PERFECT_MATCH:
6799 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6801 case RTE_MAC_HASH_MATCH:
6802 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6803 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6805 case RTE_MACVLAN_HASH_MATCH:
6806 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6809 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6810 ret = I40E_ERR_PARAM;
6814 req_list[i].queue_number = 0;
6816 req_list[i].flags = rte_cpu_to_le_16(flags);
6819 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6821 if (ret != I40E_SUCCESS) {
6822 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6826 } while (num < total);
6834 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6835 struct i40e_macvlan_filter *filter,
6838 int ele_num, ele_buff_size;
6839 int num, actual_num, i;
6841 int ret = I40E_SUCCESS;
6842 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6843 struct i40e_aqc_remove_macvlan_element_data *req_list;
6845 if (filter == NULL || total == 0)
6846 return I40E_ERR_PARAM;
6848 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6849 ele_buff_size = hw->aq.asq_buf_size;
6851 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6852 if (req_list == NULL) {
6853 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6854 return I40E_ERR_NO_MEMORY;
6859 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6860 memset(req_list, 0, ele_buff_size);
6862 for (i = 0; i < actual_num; i++) {
6863 rte_memcpy(req_list[i].mac_addr,
6864 &filter[num + i].macaddr, ETH_ADDR_LEN);
6865 req_list[i].vlan_tag =
6866 rte_cpu_to_le_16(filter[num + i].vlan_id);
6868 switch (filter[num + i].filter_type) {
6869 case RTE_MAC_PERFECT_MATCH:
6870 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6871 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6873 case RTE_MACVLAN_PERFECT_MATCH:
6874 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6876 case RTE_MAC_HASH_MATCH:
6877 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6878 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6880 case RTE_MACVLAN_HASH_MATCH:
6881 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6884 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6885 ret = I40E_ERR_PARAM;
6888 req_list[i].flags = rte_cpu_to_le_16(flags);
6891 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6893 if (ret != I40E_SUCCESS) {
6894 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6898 } while (num < total);
6905 /* Find out specific MAC filter */
6906 static struct i40e_mac_filter *
6907 i40e_find_mac_filter(struct i40e_vsi *vsi,
6908 struct ether_addr *macaddr)
6910 struct i40e_mac_filter *f;
6912 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6913 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6921 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6924 uint32_t vid_idx, vid_bit;
6926 if (vlan_id > ETH_VLAN_ID_MAX)
6929 vid_idx = I40E_VFTA_IDX(vlan_id);
6930 vid_bit = I40E_VFTA_BIT(vlan_id);
6932 if (vsi->vfta[vid_idx] & vid_bit)
6939 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6940 uint16_t vlan_id, bool on)
6942 uint32_t vid_idx, vid_bit;
6944 vid_idx = I40E_VFTA_IDX(vlan_id);
6945 vid_bit = I40E_VFTA_BIT(vlan_id);
6948 vsi->vfta[vid_idx] |= vid_bit;
6950 vsi->vfta[vid_idx] &= ~vid_bit;
6954 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6955 uint16_t vlan_id, bool on)
6957 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6958 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6961 if (vlan_id > ETH_VLAN_ID_MAX)
6964 i40e_store_vlan_filter(vsi, vlan_id, on);
6966 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6969 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6972 ret = i40e_aq_add_vlan(hw, vsi->seid,
6973 &vlan_data, 1, NULL);
6974 if (ret != I40E_SUCCESS)
6975 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6977 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6978 &vlan_data, 1, NULL);
6979 if (ret != I40E_SUCCESS)
6981 "Failed to remove vlan filter");
6986 * Find all vlan options for specific mac addr,
6987 * return with actual vlan found.
6990 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6991 struct i40e_macvlan_filter *mv_f,
6992 int num, struct ether_addr *addr)
6998 * Not to use i40e_find_vlan_filter to decrease the loop time,
6999 * although the code looks complex.
7001 if (num < vsi->vlan_num)
7002 return I40E_ERR_PARAM;
7005 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7007 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7008 if (vsi->vfta[j] & (1 << k)) {
7011 "vlan number doesn't match");
7012 return I40E_ERR_PARAM;
7014 rte_memcpy(&mv_f[i].macaddr,
7015 addr, ETH_ADDR_LEN);
7017 j * I40E_UINT32_BIT_SIZE + k;
7023 return I40E_SUCCESS;
7027 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7028 struct i40e_macvlan_filter *mv_f,
7033 struct i40e_mac_filter *f;
7035 if (num < vsi->mac_num)
7036 return I40E_ERR_PARAM;
7038 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7040 PMD_DRV_LOG(ERR, "buffer number not match");
7041 return I40E_ERR_PARAM;
7043 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7045 mv_f[i].vlan_id = vlan;
7046 mv_f[i].filter_type = f->mac_info.filter_type;
7050 return I40E_SUCCESS;
7054 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7057 struct i40e_mac_filter *f;
7058 struct i40e_macvlan_filter *mv_f;
7059 int ret = I40E_SUCCESS;
7061 if (vsi == NULL || vsi->mac_num == 0)
7062 return I40E_ERR_PARAM;
7064 /* Case that no vlan is set */
7065 if (vsi->vlan_num == 0)
7068 num = vsi->mac_num * vsi->vlan_num;
7070 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7072 PMD_DRV_LOG(ERR, "failed to allocate memory");
7073 return I40E_ERR_NO_MEMORY;
7077 if (vsi->vlan_num == 0) {
7078 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7079 rte_memcpy(&mv_f[i].macaddr,
7080 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7081 mv_f[i].filter_type = f->mac_info.filter_type;
7082 mv_f[i].vlan_id = 0;
7086 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7087 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7088 vsi->vlan_num, &f->mac_info.mac_addr);
7089 if (ret != I40E_SUCCESS)
7091 for (j = i; j < i + vsi->vlan_num; j++)
7092 mv_f[j].filter_type = f->mac_info.filter_type;
7097 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7105 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7107 struct i40e_macvlan_filter *mv_f;
7109 int ret = I40E_SUCCESS;
7111 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7112 return I40E_ERR_PARAM;
7114 /* If it's already set, just return */
7115 if (i40e_find_vlan_filter(vsi,vlan))
7116 return I40E_SUCCESS;
7118 mac_num = vsi->mac_num;
7121 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7122 return I40E_ERR_PARAM;
7125 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7128 PMD_DRV_LOG(ERR, "failed to allocate memory");
7129 return I40E_ERR_NO_MEMORY;
7132 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7134 if (ret != I40E_SUCCESS)
7137 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7139 if (ret != I40E_SUCCESS)
7142 i40e_set_vlan_filter(vsi, vlan, 1);
7152 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7154 struct i40e_macvlan_filter *mv_f;
7156 int ret = I40E_SUCCESS;
7159 * Vlan 0 is the generic filter for untagged packets
7160 * and can't be removed.
7162 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7163 return I40E_ERR_PARAM;
7165 /* If can't find it, just return */
7166 if (!i40e_find_vlan_filter(vsi, vlan))
7167 return I40E_ERR_PARAM;
7169 mac_num = vsi->mac_num;
7172 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7173 return I40E_ERR_PARAM;
7176 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7179 PMD_DRV_LOG(ERR, "failed to allocate memory");
7180 return I40E_ERR_NO_MEMORY;
7183 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7185 if (ret != I40E_SUCCESS)
7188 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7190 if (ret != I40E_SUCCESS)
7193 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7194 if (vsi->vlan_num == 1) {
7195 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7196 if (ret != I40E_SUCCESS)
7199 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7200 if (ret != I40E_SUCCESS)
7204 i40e_set_vlan_filter(vsi, vlan, 0);
7214 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7216 struct i40e_mac_filter *f;
7217 struct i40e_macvlan_filter *mv_f;
7218 int i, vlan_num = 0;
7219 int ret = I40E_SUCCESS;
7221 /* If it's add and we've config it, return */
7222 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7224 return I40E_SUCCESS;
7225 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7226 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7229 * If vlan_num is 0, that's the first time to add mac,
7230 * set mask for vlan_id 0.
7232 if (vsi->vlan_num == 0) {
7233 i40e_set_vlan_filter(vsi, 0, 1);
7236 vlan_num = vsi->vlan_num;
7237 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7238 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7241 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7243 PMD_DRV_LOG(ERR, "failed to allocate memory");
7244 return I40E_ERR_NO_MEMORY;
7247 for (i = 0; i < vlan_num; i++) {
7248 mv_f[i].filter_type = mac_filter->filter_type;
7249 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7253 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7254 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7255 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7256 &mac_filter->mac_addr);
7257 if (ret != I40E_SUCCESS)
7261 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7262 if (ret != I40E_SUCCESS)
7265 /* Add the mac addr into mac list */
7266 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7268 PMD_DRV_LOG(ERR, "failed to allocate memory");
7269 ret = I40E_ERR_NO_MEMORY;
7272 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7274 f->mac_info.filter_type = mac_filter->filter_type;
7275 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7286 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7288 struct i40e_mac_filter *f;
7289 struct i40e_macvlan_filter *mv_f;
7291 enum rte_mac_filter_type filter_type;
7292 int ret = I40E_SUCCESS;
7294 /* Can't find it, return an error */
7295 f = i40e_find_mac_filter(vsi, addr);
7297 return I40E_ERR_PARAM;
7299 vlan_num = vsi->vlan_num;
7300 filter_type = f->mac_info.filter_type;
7301 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7302 filter_type == RTE_MACVLAN_HASH_MATCH) {
7303 if (vlan_num == 0) {
7304 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7305 return I40E_ERR_PARAM;
7307 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7308 filter_type == RTE_MAC_HASH_MATCH)
7311 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7313 PMD_DRV_LOG(ERR, "failed to allocate memory");
7314 return I40E_ERR_NO_MEMORY;
7317 for (i = 0; i < vlan_num; i++) {
7318 mv_f[i].filter_type = filter_type;
7319 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7322 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7323 filter_type == RTE_MACVLAN_HASH_MATCH) {
7324 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7325 if (ret != I40E_SUCCESS)
7329 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7330 if (ret != I40E_SUCCESS)
7333 /* Remove the mac addr into mac list */
7334 TAILQ_REMOVE(&vsi->mac_list, f, next);
7344 /* Configure hash enable flags for RSS */
7346 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7354 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7355 if (flags & (1ULL << i))
7356 hena |= adapter->pctypes_tbl[i];
7362 /* Parse the hash enable flags */
7364 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7366 uint64_t rss_hf = 0;
7372 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7373 if (flags & adapter->pctypes_tbl[i])
7374 rss_hf |= (1ULL << i);
7381 i40e_pf_disable_rss(struct i40e_pf *pf)
7383 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7385 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7386 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7387 I40E_WRITE_FLUSH(hw);
7391 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7393 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7394 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7395 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7396 I40E_VFQF_HKEY_MAX_INDEX :
7397 I40E_PFQF_HKEY_MAX_INDEX;
7400 if (!key || key_len == 0) {
7401 PMD_DRV_LOG(DEBUG, "No key to be configured");
7403 } else if (key_len != (key_idx + 1) *
7405 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7409 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7410 struct i40e_aqc_get_set_rss_key_data *key_dw =
7411 (struct i40e_aqc_get_set_rss_key_data *)key;
7413 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7415 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7417 uint32_t *hash_key = (uint32_t *)key;
7420 if (vsi->type == I40E_VSI_SRIOV) {
7421 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7424 I40E_VFQF_HKEY1(i, vsi->user_param),
7428 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7429 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7432 I40E_WRITE_FLUSH(hw);
7439 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7441 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7442 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7446 if (!key || !key_len)
7449 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7450 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7451 (struct i40e_aqc_get_set_rss_key_data *)key);
7453 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7457 uint32_t *key_dw = (uint32_t *)key;
7460 if (vsi->type == I40E_VSI_SRIOV) {
7461 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7462 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7463 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7465 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7468 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7469 reg = I40E_PFQF_HKEY(i);
7470 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7472 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7480 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7482 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7486 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7487 rss_conf->rss_key_len);
7491 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7492 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7493 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7494 I40E_WRITE_FLUSH(hw);
7500 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7501 struct rte_eth_rss_conf *rss_conf)
7503 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7505 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7508 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7509 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7511 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7512 if (rss_hf != 0) /* Enable RSS */
7514 return 0; /* Nothing to do */
7517 if (rss_hf == 0) /* Disable RSS */
7520 return i40e_hw_rss_hash_set(pf, rss_conf);
7524 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7525 struct rte_eth_rss_conf *rss_conf)
7527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7528 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7535 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7536 &rss_conf->rss_key_len);
7540 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7541 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7542 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7548 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7550 switch (filter_type) {
7551 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7552 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7554 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7555 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7557 case RTE_TUNNEL_FILTER_IMAC_TENID:
7558 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7560 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7561 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7563 case ETH_TUNNEL_FILTER_IMAC:
7564 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7566 case ETH_TUNNEL_FILTER_OIP:
7567 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7569 case ETH_TUNNEL_FILTER_IIP:
7570 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7573 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7580 /* Convert tunnel filter structure */
7582 i40e_tunnel_filter_convert(
7583 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7584 struct i40e_tunnel_filter *tunnel_filter)
7586 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7587 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7588 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7589 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7590 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7591 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7592 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7593 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7594 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7596 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7597 tunnel_filter->input.flags = cld_filter->element.flags;
7598 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7599 tunnel_filter->queue = cld_filter->element.queue_number;
7600 rte_memcpy(tunnel_filter->input.general_fields,
7601 cld_filter->general_fields,
7602 sizeof(cld_filter->general_fields));
7607 /* Check if there exists the tunnel filter */
7608 struct i40e_tunnel_filter *
7609 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7610 const struct i40e_tunnel_filter_input *input)
7614 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7618 return tunnel_rule->hash_map[ret];
7621 /* Add a tunnel filter into the SW list */
7623 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7624 struct i40e_tunnel_filter *tunnel_filter)
7626 struct i40e_tunnel_rule *rule = &pf->tunnel;
7629 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7632 "Failed to insert tunnel filter to hash table %d!",
7636 rule->hash_map[ret] = tunnel_filter;
7638 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7643 /* Delete a tunnel filter from the SW list */
7645 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7646 struct i40e_tunnel_filter_input *input)
7648 struct i40e_tunnel_rule *rule = &pf->tunnel;
7649 struct i40e_tunnel_filter *tunnel_filter;
7652 ret = rte_hash_del_key(rule->hash_table, input);
7655 "Failed to delete tunnel filter to hash table %d!",
7659 tunnel_filter = rule->hash_map[ret];
7660 rule->hash_map[ret] = NULL;
7662 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7663 rte_free(tunnel_filter);
7669 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7670 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7674 uint32_t ipv4_addr, ipv4_addr_le;
7675 uint8_t i, tun_type = 0;
7676 /* internal varialbe to convert ipv6 byte order */
7677 uint32_t convert_ipv6[4];
7679 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7680 struct i40e_vsi *vsi = pf->main_vsi;
7681 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7682 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7683 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7684 struct i40e_tunnel_filter *tunnel, *node;
7685 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7687 cld_filter = rte_zmalloc("tunnel_filter",
7688 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7691 if (NULL == cld_filter) {
7692 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7695 pfilter = cld_filter;
7697 ether_addr_copy(&tunnel_filter->outer_mac,
7698 (struct ether_addr *)&pfilter->element.outer_mac);
7699 ether_addr_copy(&tunnel_filter->inner_mac,
7700 (struct ether_addr *)&pfilter->element.inner_mac);
7702 pfilter->element.inner_vlan =
7703 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7704 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7705 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7706 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7707 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7708 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7710 sizeof(pfilter->element.ipaddr.v4.data));
7712 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7713 for (i = 0; i < 4; i++) {
7715 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7717 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7719 sizeof(pfilter->element.ipaddr.v6.data));
7722 /* check tunneled type */
7723 switch (tunnel_filter->tunnel_type) {
7724 case RTE_TUNNEL_TYPE_VXLAN:
7725 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7727 case RTE_TUNNEL_TYPE_NVGRE:
7728 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7730 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7731 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7733 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7734 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7737 /* Other tunnel types is not supported. */
7738 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7739 rte_free(cld_filter);
7743 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7744 &pfilter->element.flags);
7746 rte_free(cld_filter);
7750 pfilter->element.flags |= rte_cpu_to_le_16(
7751 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7752 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7753 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7754 pfilter->element.queue_number =
7755 rte_cpu_to_le_16(tunnel_filter->queue_id);
7757 /* Check if there is the filter in SW list */
7758 memset(&check_filter, 0, sizeof(check_filter));
7759 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7760 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7762 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7763 rte_free(cld_filter);
7767 if (!add && !node) {
7768 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7769 rte_free(cld_filter);
7774 ret = i40e_aq_add_cloud_filters(hw,
7775 vsi->seid, &cld_filter->element, 1);
7777 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7778 rte_free(cld_filter);
7781 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7782 if (tunnel == NULL) {
7783 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7784 rte_free(cld_filter);
7788 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7789 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7793 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7794 &cld_filter->element, 1);
7796 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7797 rte_free(cld_filter);
7800 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7803 rte_free(cld_filter);
7807 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7808 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7809 #define I40E_TR_GENEVE_KEY_MASK 0x8
7810 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7811 #define I40E_TR_GRE_KEY_MASK 0x400
7812 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7813 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7816 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7818 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7819 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7821 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7822 enum i40e_status_code status = I40E_SUCCESS;
7824 if (pf->support_multi_driver) {
7825 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7826 return I40E_NOT_SUPPORTED;
7829 memset(&filter_replace, 0,
7830 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7831 memset(&filter_replace_buf, 0,
7832 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7834 /* create L1 filter */
7835 filter_replace.old_filter_type =
7836 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7837 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7838 filter_replace.tr_bit = 0;
7840 /* Prepare the buffer, 3 entries */
7841 filter_replace_buf.data[0] =
7842 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7843 filter_replace_buf.data[0] |=
7844 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7845 filter_replace_buf.data[2] = 0xFF;
7846 filter_replace_buf.data[3] = 0xFF;
7847 filter_replace_buf.data[4] =
7848 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7849 filter_replace_buf.data[4] |=
7850 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7851 filter_replace_buf.data[7] = 0xF0;
7852 filter_replace_buf.data[8]
7853 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7854 filter_replace_buf.data[8] |=
7855 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7856 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7857 I40E_TR_GENEVE_KEY_MASK |
7858 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7859 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7860 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7861 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7863 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7864 &filter_replace_buf);
7865 if (!status && (filter_replace.old_filter_type !=
7866 filter_replace.new_filter_type))
7867 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7868 " original: 0x%x, new: 0x%x",
7870 filter_replace.old_filter_type,
7871 filter_replace.new_filter_type);
7877 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7879 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7880 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7881 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7882 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7883 enum i40e_status_code status = I40E_SUCCESS;
7885 if (pf->support_multi_driver) {
7886 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7887 return I40E_NOT_SUPPORTED;
7891 memset(&filter_replace, 0,
7892 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7893 memset(&filter_replace_buf, 0,
7894 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7895 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7896 I40E_AQC_MIRROR_CLOUD_FILTER;
7897 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7898 filter_replace.new_filter_type =
7899 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7900 /* Prepare the buffer, 2 entries */
7901 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7902 filter_replace_buf.data[0] |=
7903 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7904 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7905 filter_replace_buf.data[4] |=
7906 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7907 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7908 &filter_replace_buf);
7911 if (filter_replace.old_filter_type !=
7912 filter_replace.new_filter_type)
7913 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7914 " original: 0x%x, new: 0x%x",
7916 filter_replace.old_filter_type,
7917 filter_replace.new_filter_type);
7920 memset(&filter_replace, 0,
7921 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7922 memset(&filter_replace_buf, 0,
7923 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7925 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7926 I40E_AQC_MIRROR_CLOUD_FILTER;
7927 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7928 filter_replace.new_filter_type =
7929 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7930 /* Prepare the buffer, 2 entries */
7931 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7932 filter_replace_buf.data[0] |=
7933 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7934 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7935 filter_replace_buf.data[4] |=
7936 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7938 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7939 &filter_replace_buf);
7940 if (!status && (filter_replace.old_filter_type !=
7941 filter_replace.new_filter_type))
7942 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7943 " original: 0x%x, new: 0x%x",
7945 filter_replace.old_filter_type,
7946 filter_replace.new_filter_type);
7951 static enum i40e_status_code
7952 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7954 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7955 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7956 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7957 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7958 enum i40e_status_code status = I40E_SUCCESS;
7960 if (pf->support_multi_driver) {
7961 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7962 return I40E_NOT_SUPPORTED;
7966 memset(&filter_replace, 0,
7967 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7968 memset(&filter_replace_buf, 0,
7969 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7970 /* create L1 filter */
7971 filter_replace.old_filter_type =
7972 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7973 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7974 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7975 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7976 /* Prepare the buffer, 2 entries */
7977 filter_replace_buf.data[0] =
7978 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7979 filter_replace_buf.data[0] |=
7980 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7981 filter_replace_buf.data[2] = 0xFF;
7982 filter_replace_buf.data[3] = 0xFF;
7983 filter_replace_buf.data[4] =
7984 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7985 filter_replace_buf.data[4] |=
7986 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7987 filter_replace_buf.data[6] = 0xFF;
7988 filter_replace_buf.data[7] = 0xFF;
7989 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7990 &filter_replace_buf);
7993 if (filter_replace.old_filter_type !=
7994 filter_replace.new_filter_type)
7995 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7996 " original: 0x%x, new: 0x%x",
7998 filter_replace.old_filter_type,
7999 filter_replace.new_filter_type);
8002 memset(&filter_replace, 0,
8003 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8004 memset(&filter_replace_buf, 0,
8005 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8006 /* create L1 filter */
8007 filter_replace.old_filter_type =
8008 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8009 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8010 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8011 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8012 /* Prepare the buffer, 2 entries */
8013 filter_replace_buf.data[0] =
8014 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8015 filter_replace_buf.data[0] |=
8016 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8017 filter_replace_buf.data[2] = 0xFF;
8018 filter_replace_buf.data[3] = 0xFF;
8019 filter_replace_buf.data[4] =
8020 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8021 filter_replace_buf.data[4] |=
8022 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8023 filter_replace_buf.data[6] = 0xFF;
8024 filter_replace_buf.data[7] = 0xFF;
8026 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8027 &filter_replace_buf);
8028 if (!status && (filter_replace.old_filter_type !=
8029 filter_replace.new_filter_type))
8030 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8031 " original: 0x%x, new: 0x%x",
8033 filter_replace.old_filter_type,
8034 filter_replace.new_filter_type);
8040 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8042 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8043 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8044 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8045 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8046 enum i40e_status_code status = I40E_SUCCESS;
8048 if (pf->support_multi_driver) {
8049 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8050 return I40E_NOT_SUPPORTED;
8054 memset(&filter_replace, 0,
8055 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8056 memset(&filter_replace_buf, 0,
8057 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8058 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8059 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8060 filter_replace.new_filter_type =
8061 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8062 /* Prepare the buffer, 2 entries */
8063 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8064 filter_replace_buf.data[0] |=
8065 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8066 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8067 filter_replace_buf.data[4] |=
8068 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8069 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8070 &filter_replace_buf);
8073 if (filter_replace.old_filter_type !=
8074 filter_replace.new_filter_type)
8075 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8076 " original: 0x%x, new: 0x%x",
8078 filter_replace.old_filter_type,
8079 filter_replace.new_filter_type);
8082 memset(&filter_replace, 0,
8083 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8084 memset(&filter_replace_buf, 0,
8085 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8086 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8087 filter_replace.old_filter_type =
8088 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8089 filter_replace.new_filter_type =
8090 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8091 /* Prepare the buffer, 2 entries */
8092 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8093 filter_replace_buf.data[0] |=
8094 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8095 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8096 filter_replace_buf.data[4] |=
8097 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8099 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8100 &filter_replace_buf);
8101 if (!status && (filter_replace.old_filter_type !=
8102 filter_replace.new_filter_type))
8103 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8104 " original: 0x%x, new: 0x%x",
8106 filter_replace.old_filter_type,
8107 filter_replace.new_filter_type);
8113 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8114 struct i40e_tunnel_filter_conf *tunnel_filter,
8118 uint32_t ipv4_addr, ipv4_addr_le;
8119 uint8_t i, tun_type = 0;
8120 /* internal variable to convert ipv6 byte order */
8121 uint32_t convert_ipv6[4];
8123 struct i40e_pf_vf *vf = NULL;
8124 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8125 struct i40e_vsi *vsi;
8126 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8127 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8128 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8129 struct i40e_tunnel_filter *tunnel, *node;
8130 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8132 bool big_buffer = 0;
8134 cld_filter = rte_zmalloc("tunnel_filter",
8135 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8138 if (cld_filter == NULL) {
8139 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8142 pfilter = cld_filter;
8144 ether_addr_copy(&tunnel_filter->outer_mac,
8145 (struct ether_addr *)&pfilter->element.outer_mac);
8146 ether_addr_copy(&tunnel_filter->inner_mac,
8147 (struct ether_addr *)&pfilter->element.inner_mac);
8149 pfilter->element.inner_vlan =
8150 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8151 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8152 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8153 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8154 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8155 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8157 sizeof(pfilter->element.ipaddr.v4.data));
8159 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8160 for (i = 0; i < 4; i++) {
8162 rte_cpu_to_le_32(rte_be_to_cpu_32(
8163 tunnel_filter->ip_addr.ipv6_addr[i]));
8165 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8167 sizeof(pfilter->element.ipaddr.v6.data));
8170 /* check tunneled type */
8171 switch (tunnel_filter->tunnel_type) {
8172 case I40E_TUNNEL_TYPE_VXLAN:
8173 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8175 case I40E_TUNNEL_TYPE_NVGRE:
8176 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8178 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8179 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8181 case I40E_TUNNEL_TYPE_MPLSoUDP:
8182 if (!pf->mpls_replace_flag) {
8183 i40e_replace_mpls_l1_filter(pf);
8184 i40e_replace_mpls_cloud_filter(pf);
8185 pf->mpls_replace_flag = 1;
8187 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8188 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8190 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8191 (teid_le & 0xF) << 12;
8192 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8195 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8197 case I40E_TUNNEL_TYPE_MPLSoGRE:
8198 if (!pf->mpls_replace_flag) {
8199 i40e_replace_mpls_l1_filter(pf);
8200 i40e_replace_mpls_cloud_filter(pf);
8201 pf->mpls_replace_flag = 1;
8203 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8204 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8206 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8207 (teid_le & 0xF) << 12;
8208 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8211 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8213 case I40E_TUNNEL_TYPE_GTPC:
8214 if (!pf->gtp_replace_flag) {
8215 i40e_replace_gtp_l1_filter(pf);
8216 i40e_replace_gtp_cloud_filter(pf);
8217 pf->gtp_replace_flag = 1;
8219 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8220 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8221 (teid_le >> 16) & 0xFFFF;
8222 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8224 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8228 case I40E_TUNNEL_TYPE_GTPU:
8229 if (!pf->gtp_replace_flag) {
8230 i40e_replace_gtp_l1_filter(pf);
8231 i40e_replace_gtp_cloud_filter(pf);
8232 pf->gtp_replace_flag = 1;
8234 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8235 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8236 (teid_le >> 16) & 0xFFFF;
8237 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8239 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8243 case I40E_TUNNEL_TYPE_QINQ:
8244 if (!pf->qinq_replace_flag) {
8245 ret = i40e_cloud_filter_qinq_create(pf);
8248 "QinQ tunnel filter already created.");
8249 pf->qinq_replace_flag = 1;
8251 /* Add in the General fields the values of
8252 * the Outer and Inner VLAN
8253 * Big Buffer should be set, see changes in
8254 * i40e_aq_add_cloud_filters
8256 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8257 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8261 /* Other tunnel types is not supported. */
8262 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8263 rte_free(cld_filter);
8267 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8268 pfilter->element.flags =
8269 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8270 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8271 pfilter->element.flags =
8272 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8273 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8274 pfilter->element.flags =
8275 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8276 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8277 pfilter->element.flags =
8278 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8279 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8280 pfilter->element.flags |=
8281 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8283 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8284 &pfilter->element.flags);
8286 rte_free(cld_filter);
8291 pfilter->element.flags |= rte_cpu_to_le_16(
8292 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8293 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8294 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8295 pfilter->element.queue_number =
8296 rte_cpu_to_le_16(tunnel_filter->queue_id);
8298 if (!tunnel_filter->is_to_vf)
8301 if (tunnel_filter->vf_id >= pf->vf_num) {
8302 PMD_DRV_LOG(ERR, "Invalid argument.");
8303 rte_free(cld_filter);
8306 vf = &pf->vfs[tunnel_filter->vf_id];
8310 /* Check if there is the filter in SW list */
8311 memset(&check_filter, 0, sizeof(check_filter));
8312 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8313 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8314 check_filter.vf_id = tunnel_filter->vf_id;
8315 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8317 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8318 rte_free(cld_filter);
8322 if (!add && !node) {
8323 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8324 rte_free(cld_filter);
8330 ret = i40e_aq_add_cloud_filters_bb(hw,
8331 vsi->seid, cld_filter, 1);
8333 ret = i40e_aq_add_cloud_filters(hw,
8334 vsi->seid, &cld_filter->element, 1);
8336 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8337 rte_free(cld_filter);
8340 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8341 if (tunnel == NULL) {
8342 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8343 rte_free(cld_filter);
8347 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8348 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8353 ret = i40e_aq_rem_cloud_filters_bb(
8354 hw, vsi->seid, cld_filter, 1);
8356 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8357 &cld_filter->element, 1);
8359 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8360 rte_free(cld_filter);
8363 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8366 rte_free(cld_filter);
8371 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8375 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8376 if (pf->vxlan_ports[i] == port)
8384 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8388 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8390 idx = i40e_get_vxlan_port_idx(pf, port);
8392 /* Check if port already exists */
8394 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8398 /* Now check if there is space to add the new port */
8399 idx = i40e_get_vxlan_port_idx(pf, 0);
8402 "Maximum number of UDP ports reached, not adding port %d",
8407 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8410 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8414 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8417 /* New port: add it and mark its index in the bitmap */
8418 pf->vxlan_ports[idx] = port;
8419 pf->vxlan_bitmap |= (1 << idx);
8421 if (!(pf->flags & I40E_FLAG_VXLAN))
8422 pf->flags |= I40E_FLAG_VXLAN;
8428 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8431 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8433 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8434 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8438 idx = i40e_get_vxlan_port_idx(pf, port);
8441 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8445 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8446 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8450 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8453 pf->vxlan_ports[idx] = 0;
8454 pf->vxlan_bitmap &= ~(1 << idx);
8456 if (!pf->vxlan_bitmap)
8457 pf->flags &= ~I40E_FLAG_VXLAN;
8462 /* Add UDP tunneling port */
8464 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8465 struct rte_eth_udp_tunnel *udp_tunnel)
8468 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8470 if (udp_tunnel == NULL)
8473 switch (udp_tunnel->prot_type) {
8474 case RTE_TUNNEL_TYPE_VXLAN:
8475 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8476 I40E_AQC_TUNNEL_TYPE_VXLAN);
8478 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8479 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8480 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8482 case RTE_TUNNEL_TYPE_GENEVE:
8483 case RTE_TUNNEL_TYPE_TEREDO:
8484 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8489 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8497 /* Remove UDP tunneling port */
8499 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8500 struct rte_eth_udp_tunnel *udp_tunnel)
8503 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8505 if (udp_tunnel == NULL)
8508 switch (udp_tunnel->prot_type) {
8509 case RTE_TUNNEL_TYPE_VXLAN:
8510 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8511 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8513 case RTE_TUNNEL_TYPE_GENEVE:
8514 case RTE_TUNNEL_TYPE_TEREDO:
8515 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8519 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8527 /* Calculate the maximum number of contiguous PF queues that are configured */
8529 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8531 struct rte_eth_dev_data *data = pf->dev_data;
8533 struct i40e_rx_queue *rxq;
8536 for (i = 0; i < pf->lan_nb_qps; i++) {
8537 rxq = data->rx_queues[i];
8538 if (rxq && rxq->q_set)
8549 i40e_pf_config_rss(struct i40e_pf *pf)
8551 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8552 struct rte_eth_rss_conf rss_conf;
8553 uint32_t i, lut = 0;
8557 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8558 * It's necessary to calculate the actual PF queues that are configured.
8560 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8561 num = i40e_pf_calc_configured_queues_num(pf);
8563 num = pf->dev_data->nb_rx_queues;
8565 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8566 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8570 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8574 if (pf->adapter->rss_reta_updated == 0) {
8575 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8578 lut = (lut << 8) | (j & ((0x1 <<
8579 hw->func_caps.rss_table_entry_width) - 1));
8581 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8586 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8587 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8588 i40e_pf_disable_rss(pf);
8591 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8592 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8593 /* Random default keys */
8594 static uint32_t rss_key_default[] = {0x6b793944,
8595 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8596 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8597 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8599 rss_conf.rss_key = (uint8_t *)rss_key_default;
8600 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8604 return i40e_hw_rss_hash_set(pf, &rss_conf);
8608 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8609 struct rte_eth_tunnel_filter_conf *filter)
8611 if (pf == NULL || filter == NULL) {
8612 PMD_DRV_LOG(ERR, "Invalid parameter");
8616 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8617 PMD_DRV_LOG(ERR, "Invalid queue ID");
8621 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8622 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8626 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8627 (is_zero_ether_addr(&filter->outer_mac))) {
8628 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8632 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8633 (is_zero_ether_addr(&filter->inner_mac))) {
8634 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8641 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8642 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8644 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8646 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8650 if (pf->support_multi_driver) {
8651 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8655 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8656 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8659 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8660 } else if (len == 4) {
8661 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8663 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8668 ret = i40e_aq_debug_write_global_register(hw,
8669 I40E_GL_PRS_FVBM(2),
8673 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8674 "with value 0x%08x",
8675 I40E_GL_PRS_FVBM(2), reg);
8679 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8680 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8686 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8693 switch (cfg->cfg_type) {
8694 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8695 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8698 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8706 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8707 enum rte_filter_op filter_op,
8710 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8711 int ret = I40E_ERR_PARAM;
8713 switch (filter_op) {
8714 case RTE_ETH_FILTER_SET:
8715 ret = i40e_dev_global_config_set(hw,
8716 (struct rte_eth_global_cfg *)arg);
8719 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8727 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8728 enum rte_filter_op filter_op,
8731 struct rte_eth_tunnel_filter_conf *filter;
8732 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8733 int ret = I40E_SUCCESS;
8735 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8737 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8738 return I40E_ERR_PARAM;
8740 switch (filter_op) {
8741 case RTE_ETH_FILTER_NOP:
8742 if (!(pf->flags & I40E_FLAG_VXLAN))
8743 ret = I40E_NOT_SUPPORTED;
8745 case RTE_ETH_FILTER_ADD:
8746 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8748 case RTE_ETH_FILTER_DELETE:
8749 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8752 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8753 ret = I40E_ERR_PARAM;
8761 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8764 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8767 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8768 ret = i40e_pf_config_rss(pf);
8770 i40e_pf_disable_rss(pf);
8775 /* Get the symmetric hash enable configurations per port */
8777 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8779 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8781 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8784 /* Set the symmetric hash enable configurations per port */
8786 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8788 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8791 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8793 "Symmetric hash has already been enabled");
8796 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8798 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8800 "Symmetric hash has already been disabled");
8803 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8805 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8806 I40E_WRITE_FLUSH(hw);
8810 * Get global configurations of hash function type and symmetric hash enable
8811 * per flow type (pctype). Note that global configuration means it affects all
8812 * the ports on the same NIC.
8815 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8816 struct rte_eth_hash_global_conf *g_cfg)
8818 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8822 memset(g_cfg, 0, sizeof(*g_cfg));
8823 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8824 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8825 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8827 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8828 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8829 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8832 * As i40e supports less than 64 flow types, only first 64 bits need to
8835 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8836 g_cfg->valid_bit_mask[i] = 0ULL;
8837 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8840 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8842 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8843 if (!adapter->pctypes_tbl[i])
8845 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8846 j < I40E_FILTER_PCTYPE_MAX; j++) {
8847 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8848 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8849 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8850 g_cfg->sym_hash_enable_mask[0] |=
8861 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8862 const struct rte_eth_hash_global_conf *g_cfg)
8865 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8867 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8868 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8869 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8870 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8876 * As i40e supports less than 64 flow types, only first 64 bits need to
8879 mask0 = g_cfg->valid_bit_mask[0];
8880 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8882 /* Check if any unsupported flow type configured */
8883 if ((mask0 | i40e_mask) ^ i40e_mask)
8886 if (g_cfg->valid_bit_mask[i])
8894 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8900 * Set global configurations of hash function type and symmetric hash enable
8901 * per flow type (pctype). Note any modifying global configuration will affect
8902 * all the ports on the same NIC.
8905 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8906 struct rte_eth_hash_global_conf *g_cfg)
8908 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8909 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8913 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8915 if (pf->support_multi_driver) {
8916 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8920 /* Check the input parameters */
8921 ret = i40e_hash_global_config_check(adapter, g_cfg);
8926 * As i40e supports less than 64 flow types, only first 64 bits need to
8929 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8930 if (mask0 & (1UL << i)) {
8931 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8932 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8934 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8935 j < I40E_FILTER_PCTYPE_MAX; j++) {
8936 if (adapter->pctypes_tbl[i] & (1ULL << j))
8937 i40e_write_global_rx_ctl(hw,
8944 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8945 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8947 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8949 "Hash function already set to Toeplitz");
8952 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8953 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8955 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8957 "Hash function already set to Simple XOR");
8960 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8962 /* Use the default, and keep it as it is */
8965 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8968 I40E_WRITE_FLUSH(hw);
8974 * Valid input sets for hash and flow director filters per PCTYPE
8977 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8978 enum rte_filter_type filter)
8982 static const uint64_t valid_hash_inset_table[] = {
8983 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8984 I40E_INSET_DMAC | I40E_INSET_SMAC |
8985 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8986 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8987 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8988 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8989 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8990 I40E_INSET_FLEX_PAYLOAD,
8991 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8992 I40E_INSET_DMAC | I40E_INSET_SMAC |
8993 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8994 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8995 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8996 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8997 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8998 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8999 I40E_INSET_FLEX_PAYLOAD,
9000 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9001 I40E_INSET_DMAC | I40E_INSET_SMAC |
9002 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9003 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9004 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9005 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9006 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9007 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9008 I40E_INSET_FLEX_PAYLOAD,
9009 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9010 I40E_INSET_DMAC | I40E_INSET_SMAC |
9011 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9012 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9013 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9014 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9015 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9016 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9017 I40E_INSET_FLEX_PAYLOAD,
9018 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9019 I40E_INSET_DMAC | I40E_INSET_SMAC |
9020 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9021 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9022 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9023 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9024 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9025 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9026 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9027 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9028 I40E_INSET_DMAC | I40E_INSET_SMAC |
9029 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9030 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9031 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9032 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9033 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9034 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9035 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9036 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9037 I40E_INSET_DMAC | I40E_INSET_SMAC |
9038 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9039 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9040 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9041 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9042 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9043 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9044 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9045 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9046 I40E_INSET_DMAC | I40E_INSET_SMAC |
9047 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9048 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9049 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9050 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9051 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9052 I40E_INSET_FLEX_PAYLOAD,
9053 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9054 I40E_INSET_DMAC | I40E_INSET_SMAC |
9055 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9056 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9057 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9058 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9059 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9060 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9061 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9062 I40E_INSET_DMAC | I40E_INSET_SMAC |
9063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9064 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9065 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9066 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9067 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9068 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9069 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9070 I40E_INSET_DMAC | I40E_INSET_SMAC |
9071 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9072 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9073 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9074 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9075 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9076 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9077 I40E_INSET_FLEX_PAYLOAD,
9078 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9079 I40E_INSET_DMAC | I40E_INSET_SMAC |
9080 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9081 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9082 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9083 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9084 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9085 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9086 I40E_INSET_FLEX_PAYLOAD,
9087 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9088 I40E_INSET_DMAC | I40E_INSET_SMAC |
9089 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9090 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9091 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9092 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9093 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9094 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9095 I40E_INSET_FLEX_PAYLOAD,
9096 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9097 I40E_INSET_DMAC | I40E_INSET_SMAC |
9098 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9099 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9100 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9101 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9102 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9103 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9104 I40E_INSET_FLEX_PAYLOAD,
9105 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9106 I40E_INSET_DMAC | I40E_INSET_SMAC |
9107 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9108 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9109 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9110 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9111 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9112 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9113 I40E_INSET_FLEX_PAYLOAD,
9114 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9115 I40E_INSET_DMAC | I40E_INSET_SMAC |
9116 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9117 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9118 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9119 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9120 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9121 I40E_INSET_FLEX_PAYLOAD,
9122 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9123 I40E_INSET_DMAC | I40E_INSET_SMAC |
9124 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9125 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9126 I40E_INSET_FLEX_PAYLOAD,
9130 * Flow director supports only fields defined in
9131 * union rte_eth_fdir_flow.
9133 static const uint64_t valid_fdir_inset_table[] = {
9134 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9135 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9136 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9137 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9138 I40E_INSET_IPV4_TTL,
9139 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9140 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9141 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9142 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9143 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9144 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9145 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9146 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9147 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9148 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9149 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9150 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9151 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9152 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9153 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9154 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9155 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9156 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9157 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9158 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9159 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9160 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9161 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9162 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9163 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9164 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9165 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9166 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9167 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9168 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9170 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9171 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9173 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9174 I40E_INSET_IPV4_TTL,
9175 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9176 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9177 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9178 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9179 I40E_INSET_IPV6_HOP_LIMIT,
9180 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9181 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9182 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9183 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9184 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9185 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9186 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9187 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9188 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9189 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9190 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9191 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9192 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9193 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9194 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9195 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9196 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9197 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9198 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9199 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9200 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9201 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9202 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9203 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9204 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9205 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9206 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9207 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9208 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9209 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9211 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9214 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9215 I40E_INSET_IPV6_HOP_LIMIT,
9216 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9217 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218 I40E_INSET_LAST_ETHER_TYPE,
9221 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9223 if (filter == RTE_ETH_FILTER_HASH)
9224 valid = valid_hash_inset_table[pctype];
9226 valid = valid_fdir_inset_table[pctype];
9232 * Validate if the input set is allowed for a specific PCTYPE
9235 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9236 enum rte_filter_type filter, uint64_t inset)
9240 valid = i40e_get_valid_input_set(pctype, filter);
9241 if (inset & (~valid))
9247 /* default input set fields combination per pctype */
9249 i40e_get_default_input_set(uint16_t pctype)
9251 static const uint64_t default_inset_table[] = {
9252 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9253 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9254 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9255 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9256 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9257 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9258 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9259 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9261 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9262 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9263 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9264 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9265 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9266 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9267 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9268 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9269 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9270 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9271 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9273 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9274 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9275 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9276 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9277 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9278 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9279 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9280 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9281 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9282 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9283 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9284 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9285 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9287 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9288 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9289 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9290 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9291 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9292 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9293 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9296 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9297 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9298 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9299 I40E_INSET_LAST_ETHER_TYPE,
9302 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9305 return default_inset_table[pctype];
9309 * Parse the input set from index to logical bit masks
9312 i40e_parse_input_set(uint64_t *inset,
9313 enum i40e_filter_pctype pctype,
9314 enum rte_eth_input_set_field *field,
9320 static const struct {
9321 enum rte_eth_input_set_field field;
9323 } inset_convert_table[] = {
9324 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9325 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9326 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9327 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9328 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9329 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9330 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9331 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9332 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9333 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9334 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9335 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9336 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9337 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9338 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9339 I40E_INSET_IPV6_NEXT_HDR},
9340 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9341 I40E_INSET_IPV6_HOP_LIMIT},
9342 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9343 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9344 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9345 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9346 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9347 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9348 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9349 I40E_INSET_SCTP_VT},
9350 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9351 I40E_INSET_TUNNEL_DMAC},
9352 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9353 I40E_INSET_VLAN_TUNNEL},
9354 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9355 I40E_INSET_TUNNEL_ID},
9356 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9357 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9358 I40E_INSET_FLEX_PAYLOAD_W1},
9359 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9360 I40E_INSET_FLEX_PAYLOAD_W2},
9361 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9362 I40E_INSET_FLEX_PAYLOAD_W3},
9363 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9364 I40E_INSET_FLEX_PAYLOAD_W4},
9365 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9366 I40E_INSET_FLEX_PAYLOAD_W5},
9367 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9368 I40E_INSET_FLEX_PAYLOAD_W6},
9369 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9370 I40E_INSET_FLEX_PAYLOAD_W7},
9371 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9372 I40E_INSET_FLEX_PAYLOAD_W8},
9375 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9378 /* Only one item allowed for default or all */
9380 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9381 *inset = i40e_get_default_input_set(pctype);
9383 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9384 *inset = I40E_INSET_NONE;
9389 for (i = 0, *inset = 0; i < size; i++) {
9390 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9391 if (field[i] == inset_convert_table[j].field) {
9392 *inset |= inset_convert_table[j].inset;
9397 /* It contains unsupported input set, return immediately */
9398 if (j == RTE_DIM(inset_convert_table))
9406 * Translate the input set from bit masks to register aware bit masks
9410 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9420 static const struct inset_map inset_map_common[] = {
9421 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9422 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9423 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9424 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9425 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9426 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9427 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9428 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9429 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9430 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9431 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9432 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9433 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9434 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9435 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9436 {I40E_INSET_TUNNEL_DMAC,
9437 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9438 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9439 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9440 {I40E_INSET_TUNNEL_SRC_PORT,
9441 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9442 {I40E_INSET_TUNNEL_DST_PORT,
9443 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9444 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9445 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9446 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9447 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9448 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9449 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9450 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9451 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9452 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9455 /* some different registers map in x722*/
9456 static const struct inset_map inset_map_diff_x722[] = {
9457 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9458 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9459 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9460 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9463 static const struct inset_map inset_map_diff_not_x722[] = {
9464 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9465 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9466 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9467 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9473 /* Translate input set to register aware inset */
9474 if (type == I40E_MAC_X722) {
9475 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9476 if (input & inset_map_diff_x722[i].inset)
9477 val |= inset_map_diff_x722[i].inset_reg;
9480 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9481 if (input & inset_map_diff_not_x722[i].inset)
9482 val |= inset_map_diff_not_x722[i].inset_reg;
9486 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9487 if (input & inset_map_common[i].inset)
9488 val |= inset_map_common[i].inset_reg;
9495 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9498 uint64_t inset_need_mask = inset;
9500 static const struct {
9503 } inset_mask_map[] = {
9504 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9505 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9506 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9507 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9508 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9509 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9510 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9511 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9514 if (!inset || !mask || !nb_elem)
9517 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9518 /* Clear the inset bit, if no MASK is required,
9519 * for example proto + ttl
9521 if ((inset & inset_mask_map[i].inset) ==
9522 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9523 inset_need_mask &= ~inset_mask_map[i].inset;
9524 if (!inset_need_mask)
9527 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9528 if ((inset_need_mask & inset_mask_map[i].inset) ==
9529 inset_mask_map[i].inset) {
9530 if (idx >= nb_elem) {
9531 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9534 mask[idx] = inset_mask_map[i].mask;
9543 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9545 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9547 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9549 i40e_write_rx_ctl(hw, addr, val);
9550 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9551 (uint32_t)i40e_read_rx_ctl(hw, addr));
9555 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9557 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9558 struct rte_eth_dev *dev;
9560 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9562 i40e_write_rx_ctl(hw, addr, val);
9563 PMD_DRV_LOG(WARNING,
9564 "i40e device %s changed global register [0x%08x]."
9565 " original: 0x%08x, new: 0x%08x",
9566 dev->device->name, addr, reg,
9567 (uint32_t)i40e_read_rx_ctl(hw, addr));
9572 i40e_filter_input_set_init(struct i40e_pf *pf)
9574 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9575 enum i40e_filter_pctype pctype;
9576 uint64_t input_set, inset_reg;
9577 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9581 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9582 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9583 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9585 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9588 input_set = i40e_get_default_input_set(pctype);
9590 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9591 I40E_INSET_MASK_NUM_REG);
9594 if (pf->support_multi_driver && num > 0) {
9595 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9598 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9601 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9602 (uint32_t)(inset_reg & UINT32_MAX));
9603 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9604 (uint32_t)((inset_reg >>
9605 I40E_32_BIT_WIDTH) & UINT32_MAX));
9606 if (!pf->support_multi_driver) {
9607 i40e_check_write_global_reg(hw,
9608 I40E_GLQF_HASH_INSET(0, pctype),
9609 (uint32_t)(inset_reg & UINT32_MAX));
9610 i40e_check_write_global_reg(hw,
9611 I40E_GLQF_HASH_INSET(1, pctype),
9612 (uint32_t)((inset_reg >>
9613 I40E_32_BIT_WIDTH) & UINT32_MAX));
9615 for (i = 0; i < num; i++) {
9616 i40e_check_write_global_reg(hw,
9617 I40E_GLQF_FD_MSK(i, pctype),
9619 i40e_check_write_global_reg(hw,
9620 I40E_GLQF_HASH_MSK(i, pctype),
9623 /*clear unused mask registers of the pctype */
9624 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9625 i40e_check_write_global_reg(hw,
9626 I40E_GLQF_FD_MSK(i, pctype),
9628 i40e_check_write_global_reg(hw,
9629 I40E_GLQF_HASH_MSK(i, pctype),
9633 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9635 I40E_WRITE_FLUSH(hw);
9637 /* store the default input set */
9638 if (!pf->support_multi_driver)
9639 pf->hash_input_set[pctype] = input_set;
9640 pf->fdir.input_set[pctype] = input_set;
9645 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9646 struct rte_eth_input_set_conf *conf)
9648 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9649 enum i40e_filter_pctype pctype;
9650 uint64_t input_set, inset_reg = 0;
9651 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9655 PMD_DRV_LOG(ERR, "Invalid pointer");
9658 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9659 conf->op != RTE_ETH_INPUT_SET_ADD) {
9660 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9664 if (pf->support_multi_driver) {
9665 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9669 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9670 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9671 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9675 if (hw->mac.type == I40E_MAC_X722) {
9676 /* get translated pctype value in fd pctype register */
9677 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9678 I40E_GLQF_FD_PCTYPES((int)pctype));
9681 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9684 PMD_DRV_LOG(ERR, "Failed to parse input set");
9688 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9689 /* get inset value in register */
9690 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9691 inset_reg <<= I40E_32_BIT_WIDTH;
9692 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9693 input_set |= pf->hash_input_set[pctype];
9695 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9696 I40E_INSET_MASK_NUM_REG);
9700 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9702 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9703 (uint32_t)(inset_reg & UINT32_MAX));
9704 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9705 (uint32_t)((inset_reg >>
9706 I40E_32_BIT_WIDTH) & UINT32_MAX));
9708 for (i = 0; i < num; i++)
9709 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9711 /*clear unused mask registers of the pctype */
9712 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9713 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9715 I40E_WRITE_FLUSH(hw);
9717 pf->hash_input_set[pctype] = input_set;
9722 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9723 struct rte_eth_input_set_conf *conf)
9725 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9726 enum i40e_filter_pctype pctype;
9727 uint64_t input_set, inset_reg = 0;
9728 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9732 PMD_DRV_LOG(ERR, "Invalid pointer");
9735 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9736 conf->op != RTE_ETH_INPUT_SET_ADD) {
9737 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9741 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9743 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9744 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9748 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9751 PMD_DRV_LOG(ERR, "Failed to parse input set");
9755 /* get inset value in register */
9756 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9757 inset_reg <<= I40E_32_BIT_WIDTH;
9758 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9760 /* Can not change the inset reg for flex payload for fdir,
9761 * it is done by writing I40E_PRTQF_FD_FLXINSET
9762 * in i40e_set_flex_mask_on_pctype.
9764 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9765 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9767 input_set |= pf->fdir.input_set[pctype];
9768 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9769 I40E_INSET_MASK_NUM_REG);
9772 if (pf->support_multi_driver && num > 0) {
9773 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9777 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9779 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9780 (uint32_t)(inset_reg & UINT32_MAX));
9781 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9782 (uint32_t)((inset_reg >>
9783 I40E_32_BIT_WIDTH) & UINT32_MAX));
9785 if (!pf->support_multi_driver) {
9786 for (i = 0; i < num; i++)
9787 i40e_check_write_global_reg(hw,
9788 I40E_GLQF_FD_MSK(i, pctype),
9790 /*clear unused mask registers of the pctype */
9791 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9792 i40e_check_write_global_reg(hw,
9793 I40E_GLQF_FD_MSK(i, pctype),
9796 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9798 I40E_WRITE_FLUSH(hw);
9800 pf->fdir.input_set[pctype] = input_set;
9805 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9810 PMD_DRV_LOG(ERR, "Invalid pointer");
9814 switch (info->info_type) {
9815 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9816 i40e_get_symmetric_hash_enable_per_port(hw,
9817 &(info->info.enable));
9819 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9820 ret = i40e_get_hash_filter_global_config(hw,
9821 &(info->info.global_conf));
9824 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9834 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9839 PMD_DRV_LOG(ERR, "Invalid pointer");
9843 switch (info->info_type) {
9844 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9845 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9847 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9848 ret = i40e_set_hash_filter_global_config(hw,
9849 &(info->info.global_conf));
9851 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9852 ret = i40e_hash_filter_inset_select(hw,
9853 &(info->info.input_set_conf));
9857 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9866 /* Operations for hash function */
9868 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9869 enum rte_filter_op filter_op,
9872 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9875 switch (filter_op) {
9876 case RTE_ETH_FILTER_NOP:
9878 case RTE_ETH_FILTER_GET:
9879 ret = i40e_hash_filter_get(hw,
9880 (struct rte_eth_hash_filter_info *)arg);
9882 case RTE_ETH_FILTER_SET:
9883 ret = i40e_hash_filter_set(hw,
9884 (struct rte_eth_hash_filter_info *)arg);
9887 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9896 /* Convert ethertype filter structure */
9898 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9899 struct i40e_ethertype_filter *filter)
9901 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9902 filter->input.ether_type = input->ether_type;
9903 filter->flags = input->flags;
9904 filter->queue = input->queue;
9909 /* Check if there exists the ehtertype filter */
9910 struct i40e_ethertype_filter *
9911 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9912 const struct i40e_ethertype_filter_input *input)
9916 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9920 return ethertype_rule->hash_map[ret];
9923 /* Add ethertype filter in SW list */
9925 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9926 struct i40e_ethertype_filter *filter)
9928 struct i40e_ethertype_rule *rule = &pf->ethertype;
9931 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9934 "Failed to insert ethertype filter"
9935 " to hash table %d!",
9939 rule->hash_map[ret] = filter;
9941 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9946 /* Delete ethertype filter in SW list */
9948 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9949 struct i40e_ethertype_filter_input *input)
9951 struct i40e_ethertype_rule *rule = &pf->ethertype;
9952 struct i40e_ethertype_filter *filter;
9955 ret = rte_hash_del_key(rule->hash_table, input);
9958 "Failed to delete ethertype filter"
9959 " to hash table %d!",
9963 filter = rule->hash_map[ret];
9964 rule->hash_map[ret] = NULL;
9966 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9973 * Configure ethertype filter, which can director packet by filtering
9974 * with mac address and ether_type or only ether_type
9977 i40e_ethertype_filter_set(struct i40e_pf *pf,
9978 struct rte_eth_ethertype_filter *filter,
9981 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9982 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9983 struct i40e_ethertype_filter *ethertype_filter, *node;
9984 struct i40e_ethertype_filter check_filter;
9985 struct i40e_control_filter_stats stats;
9989 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9990 PMD_DRV_LOG(ERR, "Invalid queue ID");
9993 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9994 filter->ether_type == ETHER_TYPE_IPv6) {
9996 "unsupported ether_type(0x%04x) in control packet filter.",
9997 filter->ether_type);
10000 if (filter->ether_type == ETHER_TYPE_VLAN)
10001 PMD_DRV_LOG(WARNING,
10002 "filter vlan ether_type in first tag is not supported.");
10004 /* Check if there is the filter in SW list */
10005 memset(&check_filter, 0, sizeof(check_filter));
10006 i40e_ethertype_filter_convert(filter, &check_filter);
10007 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10008 &check_filter.input);
10010 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10014 if (!add && !node) {
10015 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10019 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10020 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10021 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10022 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10023 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10025 memset(&stats, 0, sizeof(stats));
10026 ret = i40e_aq_add_rem_control_packet_filter(hw,
10027 filter->mac_addr.addr_bytes,
10028 filter->ether_type, flags,
10029 pf->main_vsi->seid,
10030 filter->queue, add, &stats, NULL);
10033 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10034 ret, stats.mac_etype_used, stats.etype_used,
10035 stats.mac_etype_free, stats.etype_free);
10039 /* Add or delete a filter in SW list */
10041 ethertype_filter = rte_zmalloc("ethertype_filter",
10042 sizeof(*ethertype_filter), 0);
10043 if (ethertype_filter == NULL) {
10044 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10048 rte_memcpy(ethertype_filter, &check_filter,
10049 sizeof(check_filter));
10050 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10052 rte_free(ethertype_filter);
10054 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10061 * Handle operations for ethertype filter.
10064 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10065 enum rte_filter_op filter_op,
10068 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10071 if (filter_op == RTE_ETH_FILTER_NOP)
10075 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10080 switch (filter_op) {
10081 case RTE_ETH_FILTER_ADD:
10082 ret = i40e_ethertype_filter_set(pf,
10083 (struct rte_eth_ethertype_filter *)arg,
10086 case RTE_ETH_FILTER_DELETE:
10087 ret = i40e_ethertype_filter_set(pf,
10088 (struct rte_eth_ethertype_filter *)arg,
10092 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10100 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10101 enum rte_filter_type filter_type,
10102 enum rte_filter_op filter_op,
10110 switch (filter_type) {
10111 case RTE_ETH_FILTER_NONE:
10112 /* For global configuration */
10113 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10115 case RTE_ETH_FILTER_HASH:
10116 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10118 case RTE_ETH_FILTER_MACVLAN:
10119 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10121 case RTE_ETH_FILTER_ETHERTYPE:
10122 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10124 case RTE_ETH_FILTER_TUNNEL:
10125 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10127 case RTE_ETH_FILTER_FDIR:
10128 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10130 case RTE_ETH_FILTER_GENERIC:
10131 if (filter_op != RTE_ETH_FILTER_GET)
10133 *(const void **)arg = &i40e_flow_ops;
10136 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10146 * Check and enable Extended Tag.
10147 * Enabling Extended Tag is important for 40G performance.
10150 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10152 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10156 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10159 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10163 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10164 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10169 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10172 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10176 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10177 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10180 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10181 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10184 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10191 * As some registers wouldn't be reset unless a global hardware reset,
10192 * hardware initialization is needed to put those registers into an
10193 * expected initial state.
10196 i40e_hw_init(struct rte_eth_dev *dev)
10198 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10200 i40e_enable_extended_tag(dev);
10202 /* clear the PF Queue Filter control register */
10203 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10205 /* Disable symmetric hash per port */
10206 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10210 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10211 * however this function will return only one highest pctype index,
10212 * which is not quite correct. This is known problem of i40e driver
10213 * and needs to be fixed later.
10215 enum i40e_filter_pctype
10216 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10219 uint64_t pctype_mask;
10221 if (flow_type < I40E_FLOW_TYPE_MAX) {
10222 pctype_mask = adapter->pctypes_tbl[flow_type];
10223 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10224 if (pctype_mask & (1ULL << i))
10225 return (enum i40e_filter_pctype)i;
10228 return I40E_FILTER_PCTYPE_INVALID;
10232 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10233 enum i40e_filter_pctype pctype)
10236 uint64_t pctype_mask = 1ULL << pctype;
10238 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10240 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10244 return RTE_ETH_FLOW_UNKNOWN;
10248 * On X710, performance number is far from the expectation on recent firmware
10249 * versions; on XL710, performance number is also far from the expectation on
10250 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10251 * mode is enabled and port MAC address is equal to the packet destination MAC
10252 * address. The fix for this issue may not be integrated in the following
10253 * firmware version. So the workaround in software driver is needed. It needs
10254 * to modify the initial values of 3 internal only registers for both X710 and
10255 * XL710. Note that the values for X710 or XL710 could be different, and the
10256 * workaround can be removed when it is fixed in firmware in the future.
10259 /* For both X710 and XL710 */
10260 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10261 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10262 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10264 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10265 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10268 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10269 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10272 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10274 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10275 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10278 * GL_SWR_PM_UP_THR:
10279 * The value is not impacted from the link speed, its value is set according
10280 * to the total number of ports for a better pipe-monitor configuration.
10283 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10285 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10286 .device_id = (dev), \
10287 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10289 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10290 .device_id = (dev), \
10291 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10293 static const struct {
10294 uint16_t device_id;
10296 } swr_pm_table[] = {
10297 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10298 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10299 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10300 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10302 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10303 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10304 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10305 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10306 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10307 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10308 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10312 if (value == NULL) {
10313 PMD_DRV_LOG(ERR, "value is NULL");
10317 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10318 if (hw->device_id == swr_pm_table[i].device_id) {
10319 *value = swr_pm_table[i].val;
10321 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10323 hw->device_id, *value);
10332 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10334 enum i40e_status_code status;
10335 struct i40e_aq_get_phy_abilities_resp phy_ab;
10336 int ret = -ENOTSUP;
10339 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10343 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10346 rte_delay_us(100000);
10348 status = i40e_aq_get_phy_capabilities(hw, false,
10349 true, &phy_ab, NULL);
10357 i40e_configure_registers(struct i40e_hw *hw)
10363 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10364 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10365 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10371 for (i = 0; i < RTE_DIM(reg_table); i++) {
10372 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10373 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10375 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10376 else /* For X710/XL710/XXV710 */
10377 if (hw->aq.fw_maj_ver < 6)
10379 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10382 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10385 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10386 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10388 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10389 else /* For X710/XL710/XXV710 */
10391 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10394 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10397 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10398 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10399 "GL_SWR_PM_UP_THR value fixup",
10404 reg_table[i].val = cfg_val;
10407 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10410 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10411 reg_table[i].addr);
10414 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10415 reg_table[i].addr, reg);
10416 if (reg == reg_table[i].val)
10419 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10420 reg_table[i].val, NULL);
10423 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10424 reg_table[i].val, reg_table[i].addr);
10427 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10428 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10432 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10433 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10434 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10435 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10437 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10442 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10443 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10447 /* Configure for double VLAN RX stripping */
10448 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10449 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10450 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10451 ret = i40e_aq_debug_write_register(hw,
10452 I40E_VSI_TSR(vsi->vsi_id),
10455 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10457 return I40E_ERR_CONFIG;
10461 /* Configure for double VLAN TX insertion */
10462 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10463 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10464 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10465 ret = i40e_aq_debug_write_register(hw,
10466 I40E_VSI_L2TAGSTXVALID(
10467 vsi->vsi_id), reg, NULL);
10470 "Failed to update VSI_L2TAGSTXVALID[%d]",
10472 return I40E_ERR_CONFIG;
10480 * i40e_aq_add_mirror_rule
10481 * @hw: pointer to the hardware structure
10482 * @seid: VEB seid to add mirror rule to
10483 * @dst_id: destination vsi seid
10484 * @entries: Buffer which contains the entities to be mirrored
10485 * @count: number of entities contained in the buffer
10486 * @rule_id:the rule_id of the rule to be added
10488 * Add a mirror rule for a given veb.
10491 static enum i40e_status_code
10492 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10493 uint16_t seid, uint16_t dst_id,
10494 uint16_t rule_type, uint16_t *entries,
10495 uint16_t count, uint16_t *rule_id)
10497 struct i40e_aq_desc desc;
10498 struct i40e_aqc_add_delete_mirror_rule cmd;
10499 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10500 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10503 enum i40e_status_code status;
10505 i40e_fill_default_direct_cmd_desc(&desc,
10506 i40e_aqc_opc_add_mirror_rule);
10507 memset(&cmd, 0, sizeof(cmd));
10509 buff_len = sizeof(uint16_t) * count;
10510 desc.datalen = rte_cpu_to_le_16(buff_len);
10512 desc.flags |= rte_cpu_to_le_16(
10513 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10514 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10515 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10516 cmd.num_entries = rte_cpu_to_le_16(count);
10517 cmd.seid = rte_cpu_to_le_16(seid);
10518 cmd.destination = rte_cpu_to_le_16(dst_id);
10520 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10521 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10523 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10524 hw->aq.asq_last_status, resp->rule_id,
10525 resp->mirror_rules_used, resp->mirror_rules_free);
10526 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10532 * i40e_aq_del_mirror_rule
10533 * @hw: pointer to the hardware structure
10534 * @seid: VEB seid to add mirror rule to
10535 * @entries: Buffer which contains the entities to be mirrored
10536 * @count: number of entities contained in the buffer
10537 * @rule_id:the rule_id of the rule to be delete
10539 * Delete a mirror rule for a given veb.
10542 static enum i40e_status_code
10543 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10544 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10545 uint16_t count, uint16_t rule_id)
10547 struct i40e_aq_desc desc;
10548 struct i40e_aqc_add_delete_mirror_rule cmd;
10549 uint16_t buff_len = 0;
10550 enum i40e_status_code status;
10553 i40e_fill_default_direct_cmd_desc(&desc,
10554 i40e_aqc_opc_delete_mirror_rule);
10555 memset(&cmd, 0, sizeof(cmd));
10556 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10557 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10559 cmd.num_entries = count;
10560 buff_len = sizeof(uint16_t) * count;
10561 desc.datalen = rte_cpu_to_le_16(buff_len);
10562 buff = (void *)entries;
10564 /* rule id is filled in destination field for deleting mirror rule */
10565 cmd.destination = rte_cpu_to_le_16(rule_id);
10567 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10568 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10569 cmd.seid = rte_cpu_to_le_16(seid);
10571 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10572 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10578 * i40e_mirror_rule_set
10579 * @dev: pointer to the hardware structure
10580 * @mirror_conf: mirror rule info
10581 * @sw_id: mirror rule's sw_id
10582 * @on: enable/disable
10584 * set a mirror rule.
10588 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10589 struct rte_eth_mirror_conf *mirror_conf,
10590 uint8_t sw_id, uint8_t on)
10592 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10593 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10594 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10595 struct i40e_mirror_rule *parent = NULL;
10596 uint16_t seid, dst_seid, rule_id;
10600 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10602 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10604 "mirror rule can not be configured without veb or vfs.");
10607 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10608 PMD_DRV_LOG(ERR, "mirror table is full.");
10611 if (mirror_conf->dst_pool > pf->vf_num) {
10612 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10613 mirror_conf->dst_pool);
10617 seid = pf->main_vsi->veb->seid;
10619 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10620 if (sw_id <= it->index) {
10626 if (mirr_rule && sw_id == mirr_rule->index) {
10628 PMD_DRV_LOG(ERR, "mirror rule exists.");
10631 ret = i40e_aq_del_mirror_rule(hw, seid,
10632 mirr_rule->rule_type,
10633 mirr_rule->entries,
10634 mirr_rule->num_entries, mirr_rule->id);
10637 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10638 ret, hw->aq.asq_last_status);
10641 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10642 rte_free(mirr_rule);
10643 pf->nb_mirror_rule--;
10647 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10651 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10652 sizeof(struct i40e_mirror_rule) , 0);
10654 PMD_DRV_LOG(ERR, "failed to allocate memory");
10655 return I40E_ERR_NO_MEMORY;
10657 switch (mirror_conf->rule_type) {
10658 case ETH_MIRROR_VLAN:
10659 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10660 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10661 mirr_rule->entries[j] =
10662 mirror_conf->vlan.vlan_id[i];
10667 PMD_DRV_LOG(ERR, "vlan is not specified.");
10668 rte_free(mirr_rule);
10671 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10673 case ETH_MIRROR_VIRTUAL_POOL_UP:
10674 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10675 /* check if the specified pool bit is out of range */
10676 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10677 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10678 rte_free(mirr_rule);
10681 for (i = 0, j = 0; i < pf->vf_num; i++) {
10682 if (mirror_conf->pool_mask & (1ULL << i)) {
10683 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10687 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10688 /* add pf vsi to entries */
10689 mirr_rule->entries[j] = pf->main_vsi_seid;
10693 PMD_DRV_LOG(ERR, "pool is not specified.");
10694 rte_free(mirr_rule);
10697 /* egress and ingress in aq commands means from switch but not port */
10698 mirr_rule->rule_type =
10699 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10700 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10701 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10703 case ETH_MIRROR_UPLINK_PORT:
10704 /* egress and ingress in aq commands means from switch but not port*/
10705 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10707 case ETH_MIRROR_DOWNLINK_PORT:
10708 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10711 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10712 mirror_conf->rule_type);
10713 rte_free(mirr_rule);
10717 /* If the dst_pool is equal to vf_num, consider it as PF */
10718 if (mirror_conf->dst_pool == pf->vf_num)
10719 dst_seid = pf->main_vsi_seid;
10721 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10723 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10724 mirr_rule->rule_type, mirr_rule->entries,
10728 "failed to add mirror rule: ret = %d, aq_err = %d.",
10729 ret, hw->aq.asq_last_status);
10730 rte_free(mirr_rule);
10734 mirr_rule->index = sw_id;
10735 mirr_rule->num_entries = j;
10736 mirr_rule->id = rule_id;
10737 mirr_rule->dst_vsi_seid = dst_seid;
10740 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10742 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10744 pf->nb_mirror_rule++;
10749 * i40e_mirror_rule_reset
10750 * @dev: pointer to the device
10751 * @sw_id: mirror rule's sw_id
10753 * reset a mirror rule.
10757 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10759 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10761 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10765 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10767 seid = pf->main_vsi->veb->seid;
10769 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10770 if (sw_id == it->index) {
10776 ret = i40e_aq_del_mirror_rule(hw, seid,
10777 mirr_rule->rule_type,
10778 mirr_rule->entries,
10779 mirr_rule->num_entries, mirr_rule->id);
10782 "failed to remove mirror rule: status = %d, aq_err = %d.",
10783 ret, hw->aq.asq_last_status);
10786 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10787 rte_free(mirr_rule);
10788 pf->nb_mirror_rule--;
10790 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10797 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10800 uint64_t systim_cycles;
10802 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10803 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10806 return systim_cycles;
10810 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10812 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10813 uint64_t rx_tstamp;
10815 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10816 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10823 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10825 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10826 uint64_t tx_tstamp;
10828 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10829 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10836 i40e_start_timecounters(struct rte_eth_dev *dev)
10838 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10839 struct i40e_adapter *adapter =
10840 (struct i40e_adapter *)dev->data->dev_private;
10841 struct rte_eth_link link;
10842 uint32_t tsync_inc_l;
10843 uint32_t tsync_inc_h;
10845 /* Get current link speed. */
10846 i40e_dev_link_update(dev, 1);
10847 rte_eth_linkstatus_get(dev, &link);
10849 switch (link.link_speed) {
10850 case ETH_SPEED_NUM_40G:
10851 case ETH_SPEED_NUM_25G:
10852 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10853 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10855 case ETH_SPEED_NUM_10G:
10856 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10857 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10859 case ETH_SPEED_NUM_1G:
10860 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10861 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10868 /* Set the timesync increment value. */
10869 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10870 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10872 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10873 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10874 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10876 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10877 adapter->systime_tc.cc_shift = 0;
10878 adapter->systime_tc.nsec_mask = 0;
10880 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10881 adapter->rx_tstamp_tc.cc_shift = 0;
10882 adapter->rx_tstamp_tc.nsec_mask = 0;
10884 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10885 adapter->tx_tstamp_tc.cc_shift = 0;
10886 adapter->tx_tstamp_tc.nsec_mask = 0;
10890 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10892 struct i40e_adapter *adapter =
10893 (struct i40e_adapter *)dev->data->dev_private;
10895 adapter->systime_tc.nsec += delta;
10896 adapter->rx_tstamp_tc.nsec += delta;
10897 adapter->tx_tstamp_tc.nsec += delta;
10903 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10906 struct i40e_adapter *adapter =
10907 (struct i40e_adapter *)dev->data->dev_private;
10909 ns = rte_timespec_to_ns(ts);
10911 /* Set the timecounters to a new value. */
10912 adapter->systime_tc.nsec = ns;
10913 adapter->rx_tstamp_tc.nsec = ns;
10914 adapter->tx_tstamp_tc.nsec = ns;
10920 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10922 uint64_t ns, systime_cycles;
10923 struct i40e_adapter *adapter =
10924 (struct i40e_adapter *)dev->data->dev_private;
10926 systime_cycles = i40e_read_systime_cyclecounter(dev);
10927 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10928 *ts = rte_ns_to_timespec(ns);
10934 i40e_timesync_enable(struct rte_eth_dev *dev)
10936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10937 uint32_t tsync_ctl_l;
10938 uint32_t tsync_ctl_h;
10940 /* Stop the timesync system time. */
10941 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10942 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10943 /* Reset the timesync system time value. */
10944 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10945 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10947 i40e_start_timecounters(dev);
10949 /* Clear timesync registers. */
10950 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10951 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10952 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10953 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10954 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10955 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10957 /* Enable timestamping of PTP packets. */
10958 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10959 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10961 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10962 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10963 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10965 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10966 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10972 i40e_timesync_disable(struct rte_eth_dev *dev)
10974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10975 uint32_t tsync_ctl_l;
10976 uint32_t tsync_ctl_h;
10978 /* Disable timestamping of transmitted PTP packets. */
10979 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10980 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10982 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10983 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10985 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10986 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10988 /* Reset the timesync increment value. */
10989 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10990 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10996 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10997 struct timespec *timestamp, uint32_t flags)
10999 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11000 struct i40e_adapter *adapter =
11001 (struct i40e_adapter *)dev->data->dev_private;
11003 uint32_t sync_status;
11004 uint32_t index = flags & 0x03;
11005 uint64_t rx_tstamp_cycles;
11008 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11009 if ((sync_status & (1 << index)) == 0)
11012 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11013 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11014 *timestamp = rte_ns_to_timespec(ns);
11020 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11021 struct timespec *timestamp)
11023 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11024 struct i40e_adapter *adapter =
11025 (struct i40e_adapter *)dev->data->dev_private;
11027 uint32_t sync_status;
11028 uint64_t tx_tstamp_cycles;
11031 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11032 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11035 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11036 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11037 *timestamp = rte_ns_to_timespec(ns);
11043 * i40e_parse_dcb_configure - parse dcb configure from user
11044 * @dev: the device being configured
11045 * @dcb_cfg: pointer of the result of parse
11046 * @*tc_map: bit map of enabled traffic classes
11048 * Returns 0 on success, negative value on failure
11051 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11052 struct i40e_dcbx_config *dcb_cfg,
11055 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11056 uint8_t i, tc_bw, bw_lf;
11058 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11060 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11061 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11062 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11066 /* assume each tc has the same bw */
11067 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11068 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11069 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11070 /* to ensure the sum of tcbw is equal to 100 */
11071 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11072 for (i = 0; i < bw_lf; i++)
11073 dcb_cfg->etscfg.tcbwtable[i]++;
11075 /* assume each tc has the same Transmission Selection Algorithm */
11076 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11077 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11079 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11080 dcb_cfg->etscfg.prioritytable[i] =
11081 dcb_rx_conf->dcb_tc[i];
11083 /* FW needs one App to configure HW */
11084 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11085 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11086 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11087 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11089 if (dcb_rx_conf->nb_tcs == 0)
11090 *tc_map = 1; /* tc0 only */
11092 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11094 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11095 dcb_cfg->pfc.willing = 0;
11096 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11097 dcb_cfg->pfc.pfcenable = *tc_map;
11103 static enum i40e_status_code
11104 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11105 struct i40e_aqc_vsi_properties_data *info,
11106 uint8_t enabled_tcmap)
11108 enum i40e_status_code ret;
11109 int i, total_tc = 0;
11110 uint16_t qpnum_per_tc, bsf, qp_idx;
11111 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11112 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11113 uint16_t used_queues;
11115 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11116 if (ret != I40E_SUCCESS)
11119 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11120 if (enabled_tcmap & (1 << i))
11125 vsi->enabled_tc = enabled_tcmap;
11127 /* different VSI has different queues assigned */
11128 if (vsi->type == I40E_VSI_MAIN)
11129 used_queues = dev_data->nb_rx_queues -
11130 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11131 else if (vsi->type == I40E_VSI_VMDQ2)
11132 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11134 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11135 return I40E_ERR_NO_AVAILABLE_VSI;
11138 qpnum_per_tc = used_queues / total_tc;
11139 /* Number of queues per enabled TC */
11140 if (qpnum_per_tc == 0) {
11141 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11142 return I40E_ERR_INVALID_QP_ID;
11144 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11145 I40E_MAX_Q_PER_TC);
11146 bsf = rte_bsf32(qpnum_per_tc);
11149 * Configure TC and queue mapping parameters, for enabled TC,
11150 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11151 * default queue will serve it.
11154 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11155 if (vsi->enabled_tc & (1 << i)) {
11156 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11157 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11158 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11159 qp_idx += qpnum_per_tc;
11161 info->tc_mapping[i] = 0;
11164 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11165 if (vsi->type == I40E_VSI_SRIOV) {
11166 info->mapping_flags |=
11167 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11168 for (i = 0; i < vsi->nb_qps; i++)
11169 info->queue_mapping[i] =
11170 rte_cpu_to_le_16(vsi->base_queue + i);
11172 info->mapping_flags |=
11173 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11174 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11176 info->valid_sections |=
11177 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11179 return I40E_SUCCESS;
11183 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11184 * @veb: VEB to be configured
11185 * @tc_map: enabled TC bitmap
11187 * Returns 0 on success, negative value on failure
11189 static enum i40e_status_code
11190 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11192 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11193 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11194 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11195 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11196 enum i40e_status_code ret = I40E_SUCCESS;
11200 /* Check if enabled_tc is same as existing or new TCs */
11201 if (veb->enabled_tc == tc_map)
11204 /* configure tc bandwidth */
11205 memset(&veb_bw, 0, sizeof(veb_bw));
11206 veb_bw.tc_valid_bits = tc_map;
11207 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11208 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11209 if (tc_map & BIT_ULL(i))
11210 veb_bw.tc_bw_share_credits[i] = 1;
11212 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11216 "AQ command Config switch_comp BW allocation per TC failed = %d",
11217 hw->aq.asq_last_status);
11221 memset(&ets_query, 0, sizeof(ets_query));
11222 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11224 if (ret != I40E_SUCCESS) {
11226 "Failed to get switch_comp ETS configuration %u",
11227 hw->aq.asq_last_status);
11230 memset(&bw_query, 0, sizeof(bw_query));
11231 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11233 if (ret != I40E_SUCCESS) {
11235 "Failed to get switch_comp bandwidth configuration %u",
11236 hw->aq.asq_last_status);
11240 /* store and print out BW info */
11241 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11242 veb->bw_info.bw_max = ets_query.tc_bw_max;
11243 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11244 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11245 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11246 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11247 I40E_16_BIT_WIDTH);
11248 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11249 veb->bw_info.bw_ets_share_credits[i] =
11250 bw_query.tc_bw_share_credits[i];
11251 veb->bw_info.bw_ets_credits[i] =
11252 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11253 /* 4 bits per TC, 4th bit is reserved */
11254 veb->bw_info.bw_ets_max[i] =
11255 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11256 RTE_LEN2MASK(3, uint8_t));
11257 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11258 veb->bw_info.bw_ets_share_credits[i]);
11259 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11260 veb->bw_info.bw_ets_credits[i]);
11261 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11262 veb->bw_info.bw_ets_max[i]);
11265 veb->enabled_tc = tc_map;
11272 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11273 * @vsi: VSI to be configured
11274 * @tc_map: enabled TC bitmap
11276 * Returns 0 on success, negative value on failure
11278 static enum i40e_status_code
11279 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11281 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11282 struct i40e_vsi_context ctxt;
11283 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11284 enum i40e_status_code ret = I40E_SUCCESS;
11287 /* Check if enabled_tc is same as existing or new TCs */
11288 if (vsi->enabled_tc == tc_map)
11291 /* configure tc bandwidth */
11292 memset(&bw_data, 0, sizeof(bw_data));
11293 bw_data.tc_valid_bits = tc_map;
11294 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11295 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11296 if (tc_map & BIT_ULL(i))
11297 bw_data.tc_bw_credits[i] = 1;
11299 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11302 "AQ command Config VSI BW allocation per TC failed = %d",
11303 hw->aq.asq_last_status);
11306 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11307 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11309 /* Update Queue Pairs Mapping for currently enabled UPs */
11310 ctxt.seid = vsi->seid;
11311 ctxt.pf_num = hw->pf_id;
11313 ctxt.uplink_seid = vsi->uplink_seid;
11314 ctxt.info = vsi->info;
11316 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11320 /* Update the VSI after updating the VSI queue-mapping information */
11321 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11323 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11324 hw->aq.asq_last_status);
11327 /* update the local VSI info with updated queue map */
11328 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11329 sizeof(vsi->info.tc_mapping));
11330 rte_memcpy(&vsi->info.queue_mapping,
11331 &ctxt.info.queue_mapping,
11332 sizeof(vsi->info.queue_mapping));
11333 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11334 vsi->info.valid_sections = 0;
11336 /* query and update current VSI BW information */
11337 ret = i40e_vsi_get_bw_config(vsi);
11340 "Failed updating vsi bw info, err %s aq_err %s",
11341 i40e_stat_str(hw, ret),
11342 i40e_aq_str(hw, hw->aq.asq_last_status));
11346 vsi->enabled_tc = tc_map;
11353 * i40e_dcb_hw_configure - program the dcb setting to hw
11354 * @pf: pf the configuration is taken on
11355 * @new_cfg: new configuration
11356 * @tc_map: enabled TC bitmap
11358 * Returns 0 on success, negative value on failure
11360 static enum i40e_status_code
11361 i40e_dcb_hw_configure(struct i40e_pf *pf,
11362 struct i40e_dcbx_config *new_cfg,
11365 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11366 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11367 struct i40e_vsi *main_vsi = pf->main_vsi;
11368 struct i40e_vsi_list *vsi_list;
11369 enum i40e_status_code ret;
11373 /* Use the FW API if FW > v4.4*/
11374 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11375 (hw->aq.fw_maj_ver >= 5))) {
11377 "FW < v4.4, can not use FW LLDP API to configure DCB");
11378 return I40E_ERR_FIRMWARE_API_VERSION;
11381 /* Check if need reconfiguration */
11382 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11383 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11384 return I40E_SUCCESS;
11387 /* Copy the new config to the current config */
11388 *old_cfg = *new_cfg;
11389 old_cfg->etsrec = old_cfg->etscfg;
11390 ret = i40e_set_dcb_config(hw);
11392 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11393 i40e_stat_str(hw, ret),
11394 i40e_aq_str(hw, hw->aq.asq_last_status));
11397 /* set receive Arbiter to RR mode and ETS scheme by default */
11398 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11399 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11400 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11401 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11402 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11403 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11404 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11405 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11406 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11407 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11408 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11409 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11410 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11412 /* get local mib to check whether it is configured correctly */
11414 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11415 /* Get Local DCB Config */
11416 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11417 &hw->local_dcbx_config);
11419 /* if Veb is created, need to update TC of it at first */
11420 if (main_vsi->veb) {
11421 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11423 PMD_INIT_LOG(WARNING,
11424 "Failed configuring TC for VEB seid=%d",
11425 main_vsi->veb->seid);
11427 /* Update each VSI */
11428 i40e_vsi_config_tc(main_vsi, tc_map);
11429 if (main_vsi->veb) {
11430 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11431 /* Beside main VSI and VMDQ VSIs, only enable default
11432 * TC for other VSIs
11434 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11435 ret = i40e_vsi_config_tc(vsi_list->vsi,
11438 ret = i40e_vsi_config_tc(vsi_list->vsi,
11439 I40E_DEFAULT_TCMAP);
11441 PMD_INIT_LOG(WARNING,
11442 "Failed configuring TC for VSI seid=%d",
11443 vsi_list->vsi->seid);
11447 return I40E_SUCCESS;
11451 * i40e_dcb_init_configure - initial dcb config
11452 * @dev: device being configured
11453 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11455 * Returns 0 on success, negative value on failure
11458 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11460 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11461 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11464 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11465 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11469 /* DCB initialization:
11470 * Update DCB configuration from the Firmware and configure
11471 * LLDP MIB change event.
11473 if (sw_dcb == TRUE) {
11474 if (i40e_need_stop_lldp(dev)) {
11475 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11476 if (ret != I40E_SUCCESS)
11477 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11480 ret = i40e_init_dcb(hw);
11481 /* If lldp agent is stopped, the return value from
11482 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11483 * adminq status. Otherwise, it should return success.
11485 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11486 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11487 memset(&hw->local_dcbx_config, 0,
11488 sizeof(struct i40e_dcbx_config));
11489 /* set dcb default configuration */
11490 hw->local_dcbx_config.etscfg.willing = 0;
11491 hw->local_dcbx_config.etscfg.maxtcs = 0;
11492 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11493 hw->local_dcbx_config.etscfg.tsatable[0] =
11495 /* all UPs mapping to TC0 */
11496 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11497 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11498 hw->local_dcbx_config.etsrec =
11499 hw->local_dcbx_config.etscfg;
11500 hw->local_dcbx_config.pfc.willing = 0;
11501 hw->local_dcbx_config.pfc.pfccap =
11502 I40E_MAX_TRAFFIC_CLASS;
11503 /* FW needs one App to configure HW */
11504 hw->local_dcbx_config.numapps = 1;
11505 hw->local_dcbx_config.app[0].selector =
11506 I40E_APP_SEL_ETHTYPE;
11507 hw->local_dcbx_config.app[0].priority = 3;
11508 hw->local_dcbx_config.app[0].protocolid =
11509 I40E_APP_PROTOID_FCOE;
11510 ret = i40e_set_dcb_config(hw);
11513 "default dcb config fails. err = %d, aq_err = %d.",
11514 ret, hw->aq.asq_last_status);
11519 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11520 ret, hw->aq.asq_last_status);
11524 ret = i40e_aq_start_lldp(hw, NULL);
11525 if (ret != I40E_SUCCESS)
11526 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11528 ret = i40e_init_dcb(hw);
11530 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11532 "HW doesn't support DCBX offload.");
11537 "DCBX configuration failed, err = %d, aq_err = %d.",
11538 ret, hw->aq.asq_last_status);
11546 * i40e_dcb_setup - setup dcb related config
11547 * @dev: device being configured
11549 * Returns 0 on success, negative value on failure
11552 i40e_dcb_setup(struct rte_eth_dev *dev)
11554 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11555 struct i40e_dcbx_config dcb_cfg;
11556 uint8_t tc_map = 0;
11559 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11560 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11564 if (pf->vf_num != 0)
11565 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11567 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11569 PMD_INIT_LOG(ERR, "invalid dcb config");
11572 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11574 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11582 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11583 struct rte_eth_dcb_info *dcb_info)
11585 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11587 struct i40e_vsi *vsi = pf->main_vsi;
11588 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11589 uint16_t bsf, tc_mapping;
11592 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11593 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11595 dcb_info->nb_tcs = 1;
11596 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11597 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11598 for (i = 0; i < dcb_info->nb_tcs; i++)
11599 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11601 /* get queue mapping if vmdq is disabled */
11602 if (!pf->nb_cfg_vmdq_vsi) {
11603 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11604 if (!(vsi->enabled_tc & (1 << i)))
11606 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11607 dcb_info->tc_queue.tc_rxq[j][i].base =
11608 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11609 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11610 dcb_info->tc_queue.tc_txq[j][i].base =
11611 dcb_info->tc_queue.tc_rxq[j][i].base;
11612 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11613 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11614 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11615 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11616 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11621 /* get queue mapping if vmdq is enabled */
11623 vsi = pf->vmdq[j].vsi;
11624 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11625 if (!(vsi->enabled_tc & (1 << i)))
11627 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11628 dcb_info->tc_queue.tc_rxq[j][i].base =
11629 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11630 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11631 dcb_info->tc_queue.tc_txq[j][i].base =
11632 dcb_info->tc_queue.tc_rxq[j][i].base;
11633 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11634 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11635 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11636 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11637 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11640 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11645 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11647 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11648 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11649 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11650 uint16_t msix_intr;
11652 msix_intr = intr_handle->intr_vec[queue_id];
11653 if (msix_intr == I40E_MISC_VEC_ID)
11654 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11655 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11656 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11657 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11660 I40E_PFINT_DYN_CTLN(msix_intr -
11661 I40E_RX_VEC_START),
11662 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11663 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11664 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11666 I40E_WRITE_FLUSH(hw);
11667 rte_intr_enable(&pci_dev->intr_handle);
11673 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11675 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11676 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11677 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11678 uint16_t msix_intr;
11680 msix_intr = intr_handle->intr_vec[queue_id];
11681 if (msix_intr == I40E_MISC_VEC_ID)
11682 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11683 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11686 I40E_PFINT_DYN_CTLN(msix_intr -
11687 I40E_RX_VEC_START),
11688 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11689 I40E_WRITE_FLUSH(hw);
11695 * This function is used to check if the register is valid.
11696 * Below is the valid registers list for X722 only:
11700 * 0x208e00--0x209000
11701 * 0x20be00--0x20c000
11702 * 0x263c00--0x264000
11703 * 0x265c00--0x266000
11705 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11707 if ((type != I40E_MAC_X722) &&
11708 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11709 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11710 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11711 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11712 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11713 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11714 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11720 static int i40e_get_regs(struct rte_eth_dev *dev,
11721 struct rte_dev_reg_info *regs)
11723 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11724 uint32_t *ptr_data = regs->data;
11725 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11726 const struct i40e_reg_info *reg_info;
11728 if (ptr_data == NULL) {
11729 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11730 regs->width = sizeof(uint32_t);
11734 /* The first few registers have to be read using AQ operations */
11736 while (i40e_regs_adminq[reg_idx].name) {
11737 reg_info = &i40e_regs_adminq[reg_idx++];
11738 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11740 arr_idx2 <= reg_info->count2;
11742 reg_offset = arr_idx * reg_info->stride1 +
11743 arr_idx2 * reg_info->stride2;
11744 reg_offset += reg_info->base_addr;
11745 ptr_data[reg_offset >> 2] =
11746 i40e_read_rx_ctl(hw, reg_offset);
11750 /* The remaining registers can be read using primitives */
11752 while (i40e_regs_others[reg_idx].name) {
11753 reg_info = &i40e_regs_others[reg_idx++];
11754 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11756 arr_idx2 <= reg_info->count2;
11758 reg_offset = arr_idx * reg_info->stride1 +
11759 arr_idx2 * reg_info->stride2;
11760 reg_offset += reg_info->base_addr;
11761 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11762 ptr_data[reg_offset >> 2] = 0;
11764 ptr_data[reg_offset >> 2] =
11765 I40E_READ_REG(hw, reg_offset);
11772 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11776 /* Convert word count to byte count */
11777 return hw->nvm.sr_size << 1;
11780 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11781 struct rte_dev_eeprom_info *eeprom)
11783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11784 uint16_t *data = eeprom->data;
11785 uint16_t offset, length, cnt_words;
11788 offset = eeprom->offset >> 1;
11789 length = eeprom->length >> 1;
11790 cnt_words = length;
11792 if (offset > hw->nvm.sr_size ||
11793 offset + length > hw->nvm.sr_size) {
11794 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11798 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11800 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11801 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11802 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11809 static int i40e_get_module_info(struct rte_eth_dev *dev,
11810 struct rte_eth_dev_module_info *modinfo)
11812 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11813 uint32_t sff8472_comp = 0;
11814 uint32_t sff8472_swap = 0;
11815 uint32_t sff8636_rev = 0;
11816 i40e_status status;
11819 /* Check if firmware supports reading module EEPROM. */
11820 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11822 "Module EEPROM memory read not supported. "
11823 "Please update the NVM image.\n");
11827 status = i40e_update_link_info(hw);
11831 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11833 "Cannot read module EEPROM memory. "
11834 "No module connected.\n");
11838 type = hw->phy.link_info.module_type[0];
11841 case I40E_MODULE_TYPE_SFP:
11842 status = i40e_aq_get_phy_register(hw,
11843 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11844 I40E_I2C_EEPROM_DEV_ADDR, 1,
11845 I40E_MODULE_SFF_8472_COMP,
11846 &sff8472_comp, NULL);
11850 status = i40e_aq_get_phy_register(hw,
11851 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11852 I40E_I2C_EEPROM_DEV_ADDR, 1,
11853 I40E_MODULE_SFF_8472_SWAP,
11854 &sff8472_swap, NULL);
11858 /* Check if the module requires address swap to access
11859 * the other EEPROM memory page.
11861 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11862 PMD_DRV_LOG(WARNING,
11863 "Module address swap to access "
11864 "page 0xA2 is not supported.\n");
11865 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11866 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11867 } else if (sff8472_comp == 0x00) {
11868 /* Module is not SFF-8472 compliant */
11869 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11870 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11872 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11873 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11876 case I40E_MODULE_TYPE_QSFP_PLUS:
11877 /* Read from memory page 0. */
11878 status = i40e_aq_get_phy_register(hw,
11879 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11881 I40E_MODULE_REVISION_ADDR,
11882 &sff8636_rev, NULL);
11885 /* Determine revision compliance byte */
11886 if (sff8636_rev > 0x02) {
11887 /* Module is SFF-8636 compliant */
11888 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11889 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11891 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11892 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11895 case I40E_MODULE_TYPE_QSFP28:
11896 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11897 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11900 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11906 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11907 struct rte_dev_eeprom_info *info)
11909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11910 bool is_sfp = false;
11911 i40e_status status;
11913 uint32_t value = 0;
11916 if (!info || !info->length || !info->data)
11919 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11923 for (i = 0; i < info->length; i++) {
11924 u32 offset = i + info->offset;
11925 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11927 /* Check if we need to access the other memory page */
11929 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11930 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11931 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11934 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11935 /* Compute memory page number and offset. */
11936 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11940 status = i40e_aq_get_phy_register(hw,
11941 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11942 addr, offset, 1, &value, NULL);
11945 data[i] = (uint8_t)value;
11950 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11951 struct ether_addr *mac_addr)
11953 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11954 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11955 struct i40e_vsi *vsi = pf->main_vsi;
11956 struct i40e_mac_filter_info mac_filter;
11957 struct i40e_mac_filter *f;
11960 if (!is_valid_assigned_ether_addr(mac_addr)) {
11961 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11965 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11966 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11971 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11975 mac_filter = f->mac_info;
11976 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11977 if (ret != I40E_SUCCESS) {
11978 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11981 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11982 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11983 if (ret != I40E_SUCCESS) {
11984 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11987 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11989 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11990 mac_addr->addr_bytes, NULL);
11991 if (ret != I40E_SUCCESS) {
11992 PMD_DRV_LOG(ERR, "Failed to change mac");
12000 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12003 struct rte_eth_dev_data *dev_data = pf->dev_data;
12004 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12007 /* check if mtu is within the allowed range */
12008 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
12011 /* mtu setting is forbidden if port is start */
12012 if (dev_data->dev_started) {
12013 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12014 dev_data->port_id);
12018 if (frame_size > ETHER_MAX_LEN)
12019 dev_data->dev_conf.rxmode.offloads |=
12020 DEV_RX_OFFLOAD_JUMBO_FRAME;
12022 dev_data->dev_conf.rxmode.offloads &=
12023 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12025 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12030 /* Restore ethertype filter */
12032 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12034 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12035 struct i40e_ethertype_filter_list
12036 *ethertype_list = &pf->ethertype.ethertype_list;
12037 struct i40e_ethertype_filter *f;
12038 struct i40e_control_filter_stats stats;
12041 TAILQ_FOREACH(f, ethertype_list, rules) {
12043 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12044 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12045 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12046 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12047 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12049 memset(&stats, 0, sizeof(stats));
12050 i40e_aq_add_rem_control_packet_filter(hw,
12051 f->input.mac_addr.addr_bytes,
12052 f->input.ether_type,
12053 flags, pf->main_vsi->seid,
12054 f->queue, 1, &stats, NULL);
12056 PMD_DRV_LOG(INFO, "Ethertype filter:"
12057 " mac_etype_used = %u, etype_used = %u,"
12058 " mac_etype_free = %u, etype_free = %u",
12059 stats.mac_etype_used, stats.etype_used,
12060 stats.mac_etype_free, stats.etype_free);
12063 /* Restore tunnel filter */
12065 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12067 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12068 struct i40e_vsi *vsi;
12069 struct i40e_pf_vf *vf;
12070 struct i40e_tunnel_filter_list
12071 *tunnel_list = &pf->tunnel.tunnel_list;
12072 struct i40e_tunnel_filter *f;
12073 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12074 bool big_buffer = 0;
12076 TAILQ_FOREACH(f, tunnel_list, rules) {
12078 vsi = pf->main_vsi;
12080 vf = &pf->vfs[f->vf_id];
12083 memset(&cld_filter, 0, sizeof(cld_filter));
12084 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
12085 (struct ether_addr *)&cld_filter.element.outer_mac);
12086 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
12087 (struct ether_addr *)&cld_filter.element.inner_mac);
12088 cld_filter.element.inner_vlan = f->input.inner_vlan;
12089 cld_filter.element.flags = f->input.flags;
12090 cld_filter.element.tenant_id = f->input.tenant_id;
12091 cld_filter.element.queue_number = f->queue;
12092 rte_memcpy(cld_filter.general_fields,
12093 f->input.general_fields,
12094 sizeof(f->input.general_fields));
12096 if (((f->input.flags &
12097 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12098 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12100 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12101 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12103 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12104 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12108 i40e_aq_add_cloud_filters_bb(hw,
12109 vsi->seid, &cld_filter, 1);
12111 i40e_aq_add_cloud_filters(hw, vsi->seid,
12112 &cld_filter.element, 1);
12116 /* Restore rss filter */
12118 i40e_rss_filter_restore(struct i40e_pf *pf)
12120 struct i40e_rte_flow_rss_conf *conf =
12122 if (conf->conf.queue_num)
12123 i40e_config_rss_filter(pf, conf, TRUE);
12127 i40e_filter_restore(struct i40e_pf *pf)
12129 i40e_ethertype_filter_restore(pf);
12130 i40e_tunnel_filter_restore(pf);
12131 i40e_fdir_filter_restore(pf);
12132 i40e_rss_filter_restore(pf);
12136 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12138 if (strcmp(dev->device->driver->name, drv->driver.name))
12145 is_i40e_supported(struct rte_eth_dev *dev)
12147 return is_device_supported(dev, &rte_i40e_pmd);
12150 struct i40e_customized_pctype*
12151 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12155 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12156 if (pf->customized_pctype[i].index == index)
12157 return &pf->customized_pctype[i];
12163 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12164 uint32_t pkg_size, uint32_t proto_num,
12165 struct rte_pmd_i40e_proto_info *proto,
12166 enum rte_pmd_i40e_package_op op)
12168 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12169 uint32_t pctype_num;
12170 struct rte_pmd_i40e_ptype_info *pctype;
12171 uint32_t buff_size;
12172 struct i40e_customized_pctype *new_pctype = NULL;
12174 uint8_t pctype_value;
12179 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12180 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12181 PMD_DRV_LOG(ERR, "Unsupported operation.");
12185 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12186 (uint8_t *)&pctype_num, sizeof(pctype_num),
12187 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12189 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12193 PMD_DRV_LOG(INFO, "No new pctype added");
12197 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12198 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12200 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12203 /* get information about new pctype list */
12204 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12205 (uint8_t *)pctype, buff_size,
12206 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12208 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12213 /* Update customized pctype. */
12214 for (i = 0; i < pctype_num; i++) {
12215 pctype_value = pctype[i].ptype_id;
12216 memset(name, 0, sizeof(name));
12217 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12218 proto_id = pctype[i].protocols[j];
12219 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12221 for (n = 0; n < proto_num; n++) {
12222 if (proto[n].proto_id != proto_id)
12224 strlcat(name, proto[n].name, sizeof(name));
12225 strlcat(name, "_", sizeof(name));
12229 name[strlen(name) - 1] = '\0';
12230 if (!strcmp(name, "GTPC"))
12232 i40e_find_customized_pctype(pf,
12233 I40E_CUSTOMIZED_GTPC);
12234 else if (!strcmp(name, "GTPU_IPV4"))
12236 i40e_find_customized_pctype(pf,
12237 I40E_CUSTOMIZED_GTPU_IPV4);
12238 else if (!strcmp(name, "GTPU_IPV6"))
12240 i40e_find_customized_pctype(pf,
12241 I40E_CUSTOMIZED_GTPU_IPV6);
12242 else if (!strcmp(name, "GTPU"))
12244 i40e_find_customized_pctype(pf,
12245 I40E_CUSTOMIZED_GTPU);
12247 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12248 new_pctype->pctype = pctype_value;
12249 new_pctype->valid = true;
12251 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12252 new_pctype->valid = false;
12262 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12263 uint32_t pkg_size, uint32_t proto_num,
12264 struct rte_pmd_i40e_proto_info *proto,
12265 enum rte_pmd_i40e_package_op op)
12267 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12268 uint16_t port_id = dev->data->port_id;
12269 uint32_t ptype_num;
12270 struct rte_pmd_i40e_ptype_info *ptype;
12271 uint32_t buff_size;
12273 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12278 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12279 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12280 PMD_DRV_LOG(ERR, "Unsupported operation.");
12284 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12285 rte_pmd_i40e_ptype_mapping_reset(port_id);
12289 /* get information about new ptype num */
12290 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12291 (uint8_t *)&ptype_num, sizeof(ptype_num),
12292 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12294 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12298 PMD_DRV_LOG(INFO, "No new ptype added");
12302 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12303 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12305 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12309 /* get information about new ptype list */
12310 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12311 (uint8_t *)ptype, buff_size,
12312 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12314 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12319 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12320 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12321 if (!ptype_mapping) {
12322 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12327 /* Update ptype mapping table. */
12328 for (i = 0; i < ptype_num; i++) {
12329 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12330 ptype_mapping[i].sw_ptype = 0;
12332 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12333 proto_id = ptype[i].protocols[j];
12334 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12336 for (n = 0; n < proto_num; n++) {
12337 if (proto[n].proto_id != proto_id)
12339 memset(name, 0, sizeof(name));
12340 strcpy(name, proto[n].name);
12341 if (!strncasecmp(name, "PPPOE", 5))
12342 ptype_mapping[i].sw_ptype |=
12343 RTE_PTYPE_L2_ETHER_PPPOE;
12344 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12346 ptype_mapping[i].sw_ptype |=
12347 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12348 ptype_mapping[i].sw_ptype |=
12350 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12352 ptype_mapping[i].sw_ptype |=
12353 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12354 ptype_mapping[i].sw_ptype |=
12355 RTE_PTYPE_INNER_L4_FRAG;
12356 } else if (!strncasecmp(name, "OIPV4", 5)) {
12357 ptype_mapping[i].sw_ptype |=
12358 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12360 } else if (!strncasecmp(name, "IPV4", 4) &&
12362 ptype_mapping[i].sw_ptype |=
12363 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12364 else if (!strncasecmp(name, "IPV4", 4) &&
12366 ptype_mapping[i].sw_ptype |=
12367 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12368 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12370 ptype_mapping[i].sw_ptype |=
12371 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12372 ptype_mapping[i].sw_ptype |=
12374 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12376 ptype_mapping[i].sw_ptype |=
12377 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12378 ptype_mapping[i].sw_ptype |=
12379 RTE_PTYPE_INNER_L4_FRAG;
12380 } else if (!strncasecmp(name, "OIPV6", 5)) {
12381 ptype_mapping[i].sw_ptype |=
12382 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12384 } else if (!strncasecmp(name, "IPV6", 4) &&
12386 ptype_mapping[i].sw_ptype |=
12387 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12388 else if (!strncasecmp(name, "IPV6", 4) &&
12390 ptype_mapping[i].sw_ptype |=
12391 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12392 else if (!strncasecmp(name, "UDP", 3) &&
12394 ptype_mapping[i].sw_ptype |=
12396 else if (!strncasecmp(name, "UDP", 3) &&
12398 ptype_mapping[i].sw_ptype |=
12399 RTE_PTYPE_INNER_L4_UDP;
12400 else if (!strncasecmp(name, "TCP", 3) &&
12402 ptype_mapping[i].sw_ptype |=
12404 else if (!strncasecmp(name, "TCP", 3) &&
12406 ptype_mapping[i].sw_ptype |=
12407 RTE_PTYPE_INNER_L4_TCP;
12408 else if (!strncasecmp(name, "SCTP", 4) &&
12410 ptype_mapping[i].sw_ptype |=
12412 else if (!strncasecmp(name, "SCTP", 4) &&
12414 ptype_mapping[i].sw_ptype |=
12415 RTE_PTYPE_INNER_L4_SCTP;
12416 else if ((!strncasecmp(name, "ICMP", 4) ||
12417 !strncasecmp(name, "ICMPV6", 6)) &&
12419 ptype_mapping[i].sw_ptype |=
12421 else if ((!strncasecmp(name, "ICMP", 4) ||
12422 !strncasecmp(name, "ICMPV6", 6)) &&
12424 ptype_mapping[i].sw_ptype |=
12425 RTE_PTYPE_INNER_L4_ICMP;
12426 else if (!strncasecmp(name, "GTPC", 4)) {
12427 ptype_mapping[i].sw_ptype |=
12428 RTE_PTYPE_TUNNEL_GTPC;
12430 } else if (!strncasecmp(name, "GTPU", 4)) {
12431 ptype_mapping[i].sw_ptype |=
12432 RTE_PTYPE_TUNNEL_GTPU;
12434 } else if (!strncasecmp(name, "GRENAT", 6)) {
12435 ptype_mapping[i].sw_ptype |=
12436 RTE_PTYPE_TUNNEL_GRENAT;
12438 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12439 !strncasecmp(name, "L2TPV2", 6)) {
12440 ptype_mapping[i].sw_ptype |=
12441 RTE_PTYPE_TUNNEL_L2TP;
12450 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12453 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12455 rte_free(ptype_mapping);
12461 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12462 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12464 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12465 uint32_t proto_num;
12466 struct rte_pmd_i40e_proto_info *proto;
12467 uint32_t buff_size;
12471 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12472 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12473 PMD_DRV_LOG(ERR, "Unsupported operation.");
12477 /* get information about protocol number */
12478 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12479 (uint8_t *)&proto_num, sizeof(proto_num),
12480 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12482 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12486 PMD_DRV_LOG(INFO, "No new protocol added");
12490 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12491 proto = rte_zmalloc("new_proto", buff_size, 0);
12493 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12497 /* get information about protocol list */
12498 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12499 (uint8_t *)proto, buff_size,
12500 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12502 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12507 /* Check if GTP is supported. */
12508 for (i = 0; i < proto_num; i++) {
12509 if (!strncmp(proto[i].name, "GTP", 3)) {
12510 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12511 pf->gtp_support = true;
12513 pf->gtp_support = false;
12518 /* Update customized pctype info */
12519 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12520 proto_num, proto, op);
12522 PMD_DRV_LOG(INFO, "No pctype is updated.");
12524 /* Update customized ptype info */
12525 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12526 proto_num, proto, op);
12528 PMD_DRV_LOG(INFO, "No ptype is updated.");
12533 /* Create a QinQ cloud filter
12535 * The Fortville NIC has limited resources for tunnel filters,
12536 * so we can only reuse existing filters.
12538 * In step 1 we define which Field Vector fields can be used for
12540 * As we do not have the inner tag defined as a field,
12541 * we have to define it first, by reusing one of L1 entries.
12543 * In step 2 we are replacing one of existing filter types with
12544 * a new one for QinQ.
12545 * As we reusing L1 and replacing L2, some of the default filter
12546 * types will disappear,which depends on L1 and L2 entries we reuse.
12548 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12550 * 1. Create L1 filter of outer vlan (12b) which will be in use
12551 * later when we define the cloud filter.
12552 * a. Valid_flags.replace_cloud = 0
12553 * b. Old_filter = 10 (Stag_Inner_Vlan)
12554 * c. New_filter = 0x10
12555 * d. TR bit = 0xff (optional, not used here)
12556 * e. Buffer – 2 entries:
12557 * i. Byte 0 = 8 (outer vlan FV index).
12559 * Byte 2-3 = 0x0fff
12560 * ii. Byte 0 = 37 (inner vlan FV index).
12562 * Byte 2-3 = 0x0fff
12565 * 2. Create cloud filter using two L1 filters entries: stag and
12566 * new filter(outer vlan+ inner vlan)
12567 * a. Valid_flags.replace_cloud = 1
12568 * b. Old_filter = 1 (instead of outer IP)
12569 * c. New_filter = 0x10
12570 * d. Buffer – 2 entries:
12571 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12572 * Byte 1-3 = 0 (rsv)
12573 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12574 * Byte 9-11 = 0 (rsv)
12577 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12579 int ret = -ENOTSUP;
12580 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12581 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12582 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12583 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12585 if (pf->support_multi_driver) {
12586 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12591 memset(&filter_replace, 0,
12592 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12593 memset(&filter_replace_buf, 0,
12594 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12596 /* create L1 filter */
12597 filter_replace.old_filter_type =
12598 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12599 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12600 filter_replace.tr_bit = 0;
12602 /* Prepare the buffer, 2 entries */
12603 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12604 filter_replace_buf.data[0] |=
12605 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12606 /* Field Vector 12b mask */
12607 filter_replace_buf.data[2] = 0xff;
12608 filter_replace_buf.data[3] = 0x0f;
12609 filter_replace_buf.data[4] =
12610 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12611 filter_replace_buf.data[4] |=
12612 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12613 /* Field Vector 12b mask */
12614 filter_replace_buf.data[6] = 0xff;
12615 filter_replace_buf.data[7] = 0x0f;
12616 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12617 &filter_replace_buf);
12618 if (ret != I40E_SUCCESS)
12621 if (filter_replace.old_filter_type !=
12622 filter_replace.new_filter_type)
12623 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12624 " original: 0x%x, new: 0x%x",
12626 filter_replace.old_filter_type,
12627 filter_replace.new_filter_type);
12629 /* Apply the second L2 cloud filter */
12630 memset(&filter_replace, 0,
12631 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12632 memset(&filter_replace_buf, 0,
12633 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12635 /* create L2 filter, input for L2 filter will be L1 filter */
12636 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12637 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12638 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12640 /* Prepare the buffer, 2 entries */
12641 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12642 filter_replace_buf.data[0] |=
12643 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12644 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12645 filter_replace_buf.data[4] |=
12646 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12647 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12648 &filter_replace_buf);
12649 if (!ret && (filter_replace.old_filter_type !=
12650 filter_replace.new_filter_type))
12651 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12652 " original: 0x%x, new: 0x%x",
12654 filter_replace.old_filter_type,
12655 filter_replace.new_filter_type);
12661 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12662 const struct rte_flow_action_rss *in)
12664 if (in->key_len > RTE_DIM(out->key) ||
12665 in->queue_num > RTE_DIM(out->queue))
12667 if (!in->key && in->key_len)
12669 out->conf = (struct rte_flow_action_rss){
12671 .level = in->level,
12672 .types = in->types,
12673 .key_len = in->key_len,
12674 .queue_num = in->queue_num,
12675 .queue = memcpy(out->queue, in->queue,
12676 sizeof(*in->queue) * in->queue_num),
12679 out->conf.key = memcpy(out->key, in->key, in->key_len);
12684 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12685 const struct rte_flow_action_rss *with)
12687 return (comp->func == with->func &&
12688 comp->level == with->level &&
12689 comp->types == with->types &&
12690 comp->key_len == with->key_len &&
12691 comp->queue_num == with->queue_num &&
12692 !memcmp(comp->key, with->key, with->key_len) &&
12693 !memcmp(comp->queue, with->queue,
12694 sizeof(*with->queue) * with->queue_num));
12698 i40e_config_rss_filter(struct i40e_pf *pf,
12699 struct i40e_rte_flow_rss_conf *conf, bool add)
12701 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12702 uint32_t i, lut = 0;
12704 struct rte_eth_rss_conf rss_conf = {
12705 .rss_key = conf->conf.key_len ?
12706 (void *)(uintptr_t)conf->conf.key : NULL,
12707 .rss_key_len = conf->conf.key_len,
12708 .rss_hf = conf->conf.types,
12710 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12713 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12714 i40e_pf_disable_rss(pf);
12715 memset(rss_info, 0,
12716 sizeof(struct i40e_rte_flow_rss_conf));
12722 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12723 * It's necessary to calculate the actual PF queues that are configured.
12725 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12726 num = i40e_pf_calc_configured_queues_num(pf);
12728 num = pf->dev_data->nb_rx_queues;
12730 num = RTE_MIN(num, conf->conf.queue_num);
12731 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12735 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12739 /* Fill in redirection table */
12740 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12743 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12744 hw->func_caps.rss_table_entry_width) - 1));
12746 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12749 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12750 i40e_pf_disable_rss(pf);
12753 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12754 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12755 /* Random default keys */
12756 static uint32_t rss_key_default[] = {0x6b793944,
12757 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12758 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12759 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12761 rss_conf.rss_key = (uint8_t *)rss_key_default;
12762 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12765 "No valid RSS key config for i40e, using default\n");
12768 i40e_hw_rss_hash_set(pf, &rss_conf);
12770 if (i40e_rss_conf_init(rss_info, &conf->conf))
12776 RTE_INIT(i40e_init_log)
12778 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12779 if (i40e_logtype_init >= 0)
12780 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12781 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12782 if (i40e_logtype_driver >= 0)
12783 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12786 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12787 ETH_I40E_FLOATING_VEB_ARG "=1"
12788 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12789 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12790 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12791 ETH_I40E_USE_LATEST_VEC "=0|1");