4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
68 #include "rte_pmd_i40e.h"
70 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
71 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
73 #define I40E_CLEAR_PXE_WAIT_MS 200
75 /* Maximun number of capability elements */
76 #define I40E_MAX_CAP_ELE_NUM 128
78 /* Wait count and interval */
79 #define I40E_CHK_Q_ENA_COUNT 1000
80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
82 /* Maximun number of VSI */
83 #define I40E_MAX_NUM_VSIS (384UL)
85 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
87 /* Flow control default timer */
88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
90 /* Flow control enable fwd bit */
91 #define I40E_PRTMAC_FWD_CTRL 0x00000001
93 /* Receive Packet Buffer size */
94 #define I40E_RXPBSIZE (968 * 1024)
97 #define I40E_KILOSHIFT 10
99 /* Flow control default high water */
100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
102 /* Flow control default low water */
103 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
105 /* Receive Average Packet Size in Byte*/
106 #define I40E_PACKET_AVERAGE_SIZE 128
108 /* Mask of PF interrupt causes */
109 #define I40E_PFINT_ICR0_ENA_MASK ( \
110 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
112 I40E_PFINT_ICR0_ENA_GRST_MASK | \
113 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
114 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
115 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
116 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
117 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
118 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
120 #define I40E_FLOW_TYPES ( \
121 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
126 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
130 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
131 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
133 /* Additional timesync values. */
134 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
135 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
136 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
137 #define I40E_PRTTSYN_TSYNENA 0x80000000
138 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
139 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define I40E_MAX_PERCENT 100
142 #define I40E_DEFAULT_DCB_APP_NUM 1
143 #define I40E_DEFAULT_DCB_APP_PRIO 3
146 * Below are values for writing un-exposed registers suggested
149 /* Destination MAC address */
150 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
151 /* Source MAC address */
152 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
153 /* Outer (S-Tag) VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
155 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
156 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
157 /* Single VLAN tag in the inner L2 header */
158 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
159 /* Source IPv4 address */
160 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
161 /* Destination IPv4 address */
162 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
163 /* Source IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
165 /* Destination IPv4 address for X722 */
166 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
167 /* IPv4 Protocol for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
169 /* IPv4 Time to Live for X722 */
170 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
171 /* IPv4 Type of Service (TOS) */
172 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
174 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
175 /* IPv4 Time to Live */
176 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
177 /* Source IPv6 address */
178 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
179 /* Destination IPv6 address */
180 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
181 /* IPv6 Traffic Class (TC) */
182 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
183 /* IPv6 Next Header */
184 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
186 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
188 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
189 /* Destination L4 port */
190 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
191 /* SCTP verification tag */
192 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
193 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
194 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
195 /* Source port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
197 /* Destination port of tunneling UDP */
198 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
199 /* UDP Tunneling ID, NVGRE/GRE key */
200 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
201 /* Last ether type */
202 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
203 /* Tunneling outer destination IPv4 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
205 /* Tunneling outer destination IPv6 address */
206 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
207 /* 1st word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
209 /* 2nd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
211 /* 3rd word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
213 /* 4th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
215 /* 5th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
217 /* 6th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
219 /* 7th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
221 /* 8th word of flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
223 /* all 8 words flex payload */
224 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
225 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
227 #define I40E_TRANSLATE_INSET 0
228 #define I40E_TRANSLATE_REG 1
230 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
231 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
232 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
233 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
234 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
235 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
237 /* PCI offset for querying capability */
238 #define PCI_DEV_CAP_REG 0xA4
239 /* PCI offset for enabling/disabling Extended Tag */
240 #define PCI_DEV_CTRL_REG 0xA8
241 /* Bit mask of Extended Tag capability */
242 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
243 /* Bit shift of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
245 /* Bit mask of Extended Tag enable/disable */
246 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
248 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
249 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
250 static int i40e_dev_configure(struct rte_eth_dev *dev);
251 static int i40e_dev_start(struct rte_eth_dev *dev);
252 static void i40e_dev_stop(struct rte_eth_dev *dev);
253 static void i40e_dev_close(struct rte_eth_dev *dev);
254 static int i40e_dev_reset(struct rte_eth_dev *dev);
255 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
257 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
258 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
259 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
260 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
261 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
262 struct rte_eth_stats *stats);
263 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
264 struct rte_eth_xstat *xstats, unsigned n);
265 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
266 struct rte_eth_xstat_name *xstats_names,
268 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
269 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
273 static int i40e_fw_version_get(struct rte_eth_dev *dev,
274 char *fw_version, size_t fw_size);
275 static void i40e_dev_info_get(struct rte_eth_dev *dev,
276 struct rte_eth_dev_info *dev_info);
277 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
280 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
281 enum rte_vlan_type vlan_type,
283 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
284 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
287 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
288 static int i40e_dev_led_on(struct rte_eth_dev *dev);
289 static int i40e_dev_led_off(struct rte_eth_dev *dev);
290 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_fc_conf *fc_conf);
294 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
295 struct rte_eth_pfc_conf *pfc_conf);
296 static int i40e_macaddr_add(struct rte_eth_dev *dev,
297 struct ether_addr *mac_addr,
300 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
301 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
304 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
305 struct rte_eth_rss_reta_entry64 *reta_conf,
308 static int i40e_get_cap(struct i40e_hw *hw);
309 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
310 static int i40e_pf_setup(struct i40e_pf *pf);
311 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
312 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
313 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
314 static int i40e_dcb_setup(struct rte_eth_dev *dev);
315 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
316 bool offset_loaded, uint64_t *offset, uint64_t *stat);
317 static void i40e_stat_update_48(struct i40e_hw *hw,
323 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
324 static void i40e_dev_interrupt_handler(void *param);
325 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
326 uint32_t base, uint32_t num);
327 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
328 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
330 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
332 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
333 static int i40e_veb_release(struct i40e_veb *veb);
334 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
335 struct i40e_vsi *vsi);
336 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
337 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
338 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
339 struct i40e_macvlan_filter *mv_f,
342 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
343 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
347 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static void i40e_filter_input_set_init(struct i40e_pf *pf);
352 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
353 enum rte_filter_op filter_op,
355 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
356 enum rte_filter_type filter_type,
357 enum rte_filter_op filter_op,
359 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
360 struct rte_eth_dcb_info *dcb_info);
361 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
362 static void i40e_configure_registers(struct i40e_hw *hw);
363 static void i40e_hw_init(struct rte_eth_dev *dev);
364 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
365 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
371 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
372 struct rte_eth_mirror_conf *mirror_conf,
373 uint8_t sw_id, uint8_t on);
374 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
376 static int i40e_timesync_enable(struct rte_eth_dev *dev);
377 static int i40e_timesync_disable(struct rte_eth_dev *dev);
378 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
379 struct timespec *timestamp,
381 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
382 struct timespec *timestamp);
383 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
385 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
387 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
388 struct timespec *timestamp);
389 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
390 const struct timespec *timestamp);
392 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
394 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
397 static int i40e_get_regs(struct rte_eth_dev *dev,
398 struct rte_dev_reg_info *regs);
400 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
402 static int i40e_get_eeprom(struct rte_eth_dev *dev,
403 struct rte_dev_eeprom_info *eeprom);
405 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
406 struct ether_addr *mac_addr);
408 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
410 static int i40e_ethertype_filter_convert(
411 const struct rte_eth_ethertype_filter *input,
412 struct i40e_ethertype_filter *filter);
413 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
414 struct i40e_ethertype_filter *filter);
416 static int i40e_tunnel_filter_convert(
417 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
418 struct i40e_tunnel_filter *tunnel_filter);
419 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
420 struct i40e_tunnel_filter *tunnel_filter);
421 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
423 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
424 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
425 static void i40e_filter_restore(struct i40e_pf *pf);
426 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
428 int i40e_logtype_init;
429 int i40e_logtype_driver;
431 static const struct rte_pci_id pci_id_i40e_map[] = {
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
452 { .vendor_id = 0, /* sentinel */ },
455 static const struct eth_dev_ops i40e_eth_dev_ops = {
456 .dev_configure = i40e_dev_configure,
457 .dev_start = i40e_dev_start,
458 .dev_stop = i40e_dev_stop,
459 .dev_close = i40e_dev_close,
460 .dev_reset = i40e_dev_reset,
461 .promiscuous_enable = i40e_dev_promiscuous_enable,
462 .promiscuous_disable = i40e_dev_promiscuous_disable,
463 .allmulticast_enable = i40e_dev_allmulticast_enable,
464 .allmulticast_disable = i40e_dev_allmulticast_disable,
465 .dev_set_link_up = i40e_dev_set_link_up,
466 .dev_set_link_down = i40e_dev_set_link_down,
467 .link_update = i40e_dev_link_update,
468 .stats_get = i40e_dev_stats_get,
469 .xstats_get = i40e_dev_xstats_get,
470 .xstats_get_names = i40e_dev_xstats_get_names,
471 .stats_reset = i40e_dev_stats_reset,
472 .xstats_reset = i40e_dev_stats_reset,
473 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
474 .fw_version_get = i40e_fw_version_get,
475 .dev_infos_get = i40e_dev_info_get,
476 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
477 .vlan_filter_set = i40e_vlan_filter_set,
478 .vlan_tpid_set = i40e_vlan_tpid_set,
479 .vlan_offload_set = i40e_vlan_offload_set,
480 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
481 .vlan_pvid_set = i40e_vlan_pvid_set,
482 .rx_queue_start = i40e_dev_rx_queue_start,
483 .rx_queue_stop = i40e_dev_rx_queue_stop,
484 .tx_queue_start = i40e_dev_tx_queue_start,
485 .tx_queue_stop = i40e_dev_tx_queue_stop,
486 .rx_queue_setup = i40e_dev_rx_queue_setup,
487 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
488 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
489 .rx_queue_release = i40e_dev_rx_queue_release,
490 .rx_queue_count = i40e_dev_rx_queue_count,
491 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
492 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
493 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
494 .tx_queue_setup = i40e_dev_tx_queue_setup,
495 .tx_queue_release = i40e_dev_tx_queue_release,
496 .dev_led_on = i40e_dev_led_on,
497 .dev_led_off = i40e_dev_led_off,
498 .flow_ctrl_get = i40e_flow_ctrl_get,
499 .flow_ctrl_set = i40e_flow_ctrl_set,
500 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
501 .mac_addr_add = i40e_macaddr_add,
502 .mac_addr_remove = i40e_macaddr_remove,
503 .reta_update = i40e_dev_rss_reta_update,
504 .reta_query = i40e_dev_rss_reta_query,
505 .rss_hash_update = i40e_dev_rss_hash_update,
506 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
507 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
508 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
509 .filter_ctrl = i40e_dev_filter_ctrl,
510 .rxq_info_get = i40e_rxq_info_get,
511 .txq_info_get = i40e_txq_info_get,
512 .mirror_rule_set = i40e_mirror_rule_set,
513 .mirror_rule_reset = i40e_mirror_rule_reset,
514 .timesync_enable = i40e_timesync_enable,
515 .timesync_disable = i40e_timesync_disable,
516 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
517 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
518 .get_dcb_info = i40e_dev_get_dcb_info,
519 .timesync_adjust_time = i40e_timesync_adjust_time,
520 .timesync_read_time = i40e_timesync_read_time,
521 .timesync_write_time = i40e_timesync_write_time,
522 .get_reg = i40e_get_regs,
523 .get_eeprom_length = i40e_get_eeprom_length,
524 .get_eeprom = i40e_get_eeprom,
525 .mac_addr_set = i40e_set_default_mac_addr,
526 .mtu_set = i40e_dev_mtu_set,
527 .tm_ops_get = i40e_tm_ops_get,
530 /* store statistics names and its offset in stats structure */
531 struct rte_i40e_xstats_name_off {
532 char name[RTE_ETH_XSTATS_NAME_SIZE];
536 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
537 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
538 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
539 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
540 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
541 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
542 rx_unknown_protocol)},
543 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
544 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
545 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
546 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
549 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
550 sizeof(rte_i40e_stats_strings[0]))
552 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
553 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
554 tx_dropped_link_down)},
555 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
556 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
559 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
561 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
563 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
565 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
566 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
567 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
568 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
569 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
570 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
584 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
587 mac_short_packet_dropped)},
588 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
590 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
591 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
592 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
604 {"rx_flow_director_atr_match_packets",
605 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
606 {"rx_flow_director_sb_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
608 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
610 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
614 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
619 sizeof(rte_i40e_hw_port_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
628 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
629 sizeof(rte_i40e_rxq_prio_strings[0]))
631 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
632 {"xon_packets", offsetof(struct i40e_hw_port_stats,
634 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
636 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
637 priority_xon_2_xoff)},
640 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
641 sizeof(rte_i40e_txq_prio_strings[0]))
643 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
644 struct rte_pci_device *pci_dev)
646 return rte_eth_dev_pci_generic_probe(pci_dev,
647 sizeof(struct i40e_adapter), eth_i40e_dev_init);
650 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
652 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
655 static struct rte_pci_driver rte_i40e_pmd = {
656 .id_table = pci_id_i40e_map,
657 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
658 .probe = eth_i40e_pci_probe,
659 .remove = eth_i40e_pci_remove,
663 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
664 struct rte_eth_link *link)
666 struct rte_eth_link *dst = link;
667 struct rte_eth_link *src = &(dev->data->dev_link);
669 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
670 *(uint64_t *)src) == 0)
677 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
678 struct rte_eth_link *link)
680 struct rte_eth_link *dst = &(dev->data->dev_link);
681 struct rte_eth_link *src = link;
683 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
684 *(uint64_t *)src) == 0)
690 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
691 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
692 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
694 #ifndef I40E_GLQF_ORT
695 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
697 #ifndef I40E_GLQF_PIT
698 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
700 #ifndef I40E_GLQF_L3_MAP
701 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
704 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
707 * Initialize registers for flexible payload, which should be set by NVM.
708 * This should be removed from code once it is fixed in NVM.
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
720 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
721 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
723 /* Initialize registers for parsing packet type of QinQ */
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
725 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
728 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
731 * Add a ethertype filter to drop all flow control frames transmitted
735 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
737 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
738 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
739 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
740 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
743 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
744 I40E_FLOW_CONTROL_ETHERTYPE, flags,
745 pf->main_vsi_seid, 0,
749 "Failed to add filter to drop flow control frames from VSIs.");
753 floating_veb_list_handler(__rte_unused const char *key,
754 const char *floating_veb_value,
758 unsigned int count = 0;
761 bool *vf_floating_veb = opaque;
763 while (isblank(*floating_veb_value))
764 floating_veb_value++;
766 /* Reset floating VEB configuration for VFs */
767 for (idx = 0; idx < I40E_MAX_VF; idx++)
768 vf_floating_veb[idx] = false;
772 while (isblank(*floating_veb_value))
773 floating_veb_value++;
774 if (*floating_veb_value == '\0')
777 idx = strtoul(floating_veb_value, &end, 10);
778 if (errno || end == NULL)
780 while (isblank(*end))
784 } else if ((*end == ';') || (*end == '\0')) {
786 if (min == I40E_MAX_VF)
788 if (max >= I40E_MAX_VF)
789 max = I40E_MAX_VF - 1;
790 for (idx = min; idx <= max; idx++) {
791 vf_floating_veb[idx] = true;
798 floating_veb_value = end + 1;
799 } while (*end != '\0');
808 config_vf_floating_veb(struct rte_devargs *devargs,
809 uint16_t floating_veb,
810 bool *vf_floating_veb)
812 struct rte_kvargs *kvlist;
814 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
818 /* All the VFs attach to the floating VEB by default
819 * when the floating VEB is enabled.
821 for (i = 0; i < I40E_MAX_VF; i++)
822 vf_floating_veb[i] = true;
827 kvlist = rte_kvargs_parse(devargs->args, NULL);
831 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
832 rte_kvargs_free(kvlist);
835 /* When the floating_veb_list parameter exists, all the VFs
836 * will attach to the legacy VEB firstly, then configure VFs
837 * to the floating VEB according to the floating_veb_list.
839 if (rte_kvargs_process(kvlist, floating_veb_list,
840 floating_veb_list_handler,
841 vf_floating_veb) < 0) {
842 rte_kvargs_free(kvlist);
845 rte_kvargs_free(kvlist);
849 i40e_check_floating_handler(__rte_unused const char *key,
851 __rte_unused void *opaque)
853 if (strcmp(value, "1"))
860 is_floating_veb_supported(struct rte_devargs *devargs)
862 struct rte_kvargs *kvlist;
863 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
868 kvlist = rte_kvargs_parse(devargs->args, NULL);
872 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
873 rte_kvargs_free(kvlist);
876 /* Floating VEB is enabled when there's key-value:
877 * enable_floating_veb=1
879 if (rte_kvargs_process(kvlist, floating_veb_key,
880 i40e_check_floating_handler, NULL) < 0) {
881 rte_kvargs_free(kvlist);
884 rte_kvargs_free(kvlist);
890 config_floating_veb(struct rte_eth_dev *dev)
892 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
893 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
894 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
898 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
900 is_floating_veb_supported(pci_dev->device.devargs);
901 config_vf_floating_veb(pci_dev->device.devargs,
903 pf->floating_veb_list);
905 pf->floating_veb = false;
909 #define I40E_L2_TAGS_S_TAG_SHIFT 1
910 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
913 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
916 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
917 char ethertype_hash_name[RTE_HASH_NAMESIZE];
920 struct rte_hash_parameters ethertype_hash_params = {
921 .name = ethertype_hash_name,
922 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
923 .key_len = sizeof(struct i40e_ethertype_filter_input),
924 .hash_func = rte_hash_crc,
925 .hash_func_init_val = 0,
926 .socket_id = rte_socket_id(),
929 /* Initialize ethertype filter rule list and hash */
930 TAILQ_INIT(ðertype_rule->ethertype_list);
931 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
932 "ethertype_%s", dev->device->name);
933 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
934 if (!ethertype_rule->hash_table) {
935 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
938 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
939 sizeof(struct i40e_ethertype_filter *) *
940 I40E_MAX_ETHERTYPE_FILTER_NUM,
942 if (!ethertype_rule->hash_map) {
944 "Failed to allocate memory for ethertype hash map!");
946 goto err_ethertype_hash_map_alloc;
951 err_ethertype_hash_map_alloc:
952 rte_hash_free(ethertype_rule->hash_table);
958 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
960 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
961 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
962 char tunnel_hash_name[RTE_HASH_NAMESIZE];
965 struct rte_hash_parameters tunnel_hash_params = {
966 .name = tunnel_hash_name,
967 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
968 .key_len = sizeof(struct i40e_tunnel_filter_input),
969 .hash_func = rte_hash_crc,
970 .hash_func_init_val = 0,
971 .socket_id = rte_socket_id(),
974 /* Initialize tunnel filter rule list and hash */
975 TAILQ_INIT(&tunnel_rule->tunnel_list);
976 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
977 "tunnel_%s", dev->device->name);
978 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
979 if (!tunnel_rule->hash_table) {
980 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
983 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
984 sizeof(struct i40e_tunnel_filter *) *
985 I40E_MAX_TUNNEL_FILTER_NUM,
987 if (!tunnel_rule->hash_map) {
989 "Failed to allocate memory for tunnel hash map!");
991 goto err_tunnel_hash_map_alloc;
996 err_tunnel_hash_map_alloc:
997 rte_hash_free(tunnel_rule->hash_table);
1003 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1005 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1006 struct i40e_fdir_info *fdir_info = &pf->fdir;
1007 char fdir_hash_name[RTE_HASH_NAMESIZE];
1010 struct rte_hash_parameters fdir_hash_params = {
1011 .name = fdir_hash_name,
1012 .entries = I40E_MAX_FDIR_FILTER_NUM,
1013 .key_len = sizeof(struct rte_eth_fdir_input),
1014 .hash_func = rte_hash_crc,
1015 .hash_func_init_val = 0,
1016 .socket_id = rte_socket_id(),
1019 /* Initialize flow director filter rule list and hash */
1020 TAILQ_INIT(&fdir_info->fdir_list);
1021 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1022 "fdir_%s", dev->device->name);
1023 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1024 if (!fdir_info->hash_table) {
1025 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1028 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1029 sizeof(struct i40e_fdir_filter *) *
1030 I40E_MAX_FDIR_FILTER_NUM,
1032 if (!fdir_info->hash_map) {
1034 "Failed to allocate memory for fdir hash map!");
1036 goto err_fdir_hash_map_alloc;
1040 err_fdir_hash_map_alloc:
1041 rte_hash_free(fdir_info->hash_table);
1047 i40e_init_customized_info(struct i40e_pf *pf)
1051 /* Initialize customized pctype */
1052 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1053 pf->customized_pctype[i].index = i;
1054 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1055 pf->customized_pctype[i].valid = false;
1058 pf->gtp_support = false;
1062 eth_i40e_dev_init(struct rte_eth_dev *dev)
1064 struct rte_pci_device *pci_dev;
1065 struct rte_intr_handle *intr_handle;
1066 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1067 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1068 struct i40e_vsi *vsi;
1071 uint8_t aq_fail = 0;
1073 PMD_INIT_FUNC_TRACE();
1075 dev->dev_ops = &i40e_eth_dev_ops;
1076 dev->rx_pkt_burst = i40e_recv_pkts;
1077 dev->tx_pkt_burst = i40e_xmit_pkts;
1078 dev->tx_pkt_prepare = i40e_prep_pkts;
1080 /* for secondary processes, we don't initialise any further as primary
1081 * has already done this work. Only check we don't need a different
1083 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1084 i40e_set_rx_function(dev);
1085 i40e_set_tx_function(dev);
1088 i40e_set_default_ptype_table(dev);
1089 i40e_set_default_pctype_table(dev);
1090 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1091 intr_handle = &pci_dev->intr_handle;
1093 rte_eth_copy_pci_info(dev, pci_dev);
1094 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1096 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1097 pf->adapter->eth_dev = dev;
1098 pf->dev_data = dev->data;
1100 hw->back = I40E_PF_TO_ADAPTER(pf);
1101 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1104 "Hardware is not available, as address is NULL");
1108 hw->vendor_id = pci_dev->id.vendor_id;
1109 hw->device_id = pci_dev->id.device_id;
1110 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1111 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1112 hw->bus.device = pci_dev->addr.devid;
1113 hw->bus.func = pci_dev->addr.function;
1114 hw->adapter_stopped = 0;
1116 /* Make sure all is clean before doing PF reset */
1119 /* Initialize the hardware */
1122 /* Reset here to make sure all is clean for each PF */
1123 ret = i40e_pf_reset(hw);
1125 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1129 /* Initialize the shared code (base driver) */
1130 ret = i40e_init_shared_code(hw);
1132 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1137 * To work around the NVM issue, initialize registers
1138 * for flexible payload and packet type of QinQ by
1139 * software. It should be removed once issues are fixed
1142 i40e_GLQF_reg_init(hw);
1144 /* Initialize the input set for filters (hash and fd) to default value */
1145 i40e_filter_input_set_init(pf);
1147 /* Initialize the parameters for adminq */
1148 i40e_init_adminq_parameter(hw);
1149 ret = i40e_init_adminq(hw);
1150 if (ret != I40E_SUCCESS) {
1151 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1154 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1155 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1156 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1157 ((hw->nvm.version >> 12) & 0xf),
1158 ((hw->nvm.version >> 4) & 0xff),
1159 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1161 /* initialise the L3_MAP register */
1162 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1165 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1167 /* Need the special FW version to support floating VEB */
1168 config_floating_veb(dev);
1169 /* Clear PXE mode */
1170 i40e_clear_pxe_mode(hw);
1171 i40e_dev_sync_phy_type(hw);
1174 * On X710, performance number is far from the expectation on recent
1175 * firmware versions. The fix for this issue may not be integrated in
1176 * the following firmware version. So the workaround in software driver
1177 * is needed. It needs to modify the initial values of 3 internal only
1178 * registers. Note that the workaround can be removed when it is fixed
1179 * in firmware in the future.
1181 i40e_configure_registers(hw);
1183 /* Get hw capabilities */
1184 ret = i40e_get_cap(hw);
1185 if (ret != I40E_SUCCESS) {
1186 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1187 goto err_get_capabilities;
1190 /* Initialize parameters for PF */
1191 ret = i40e_pf_parameter_init(dev);
1193 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1194 goto err_parameter_init;
1197 /* Initialize the queue management */
1198 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1200 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1201 goto err_qp_pool_init;
1203 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1204 hw->func_caps.num_msix_vectors - 1);
1206 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1207 goto err_msix_pool_init;
1210 /* Initialize lan hmc */
1211 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1212 hw->func_caps.num_rx_qp, 0, 0);
1213 if (ret != I40E_SUCCESS) {
1214 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1215 goto err_init_lan_hmc;
1218 /* Configure lan hmc */
1219 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1220 if (ret != I40E_SUCCESS) {
1221 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1222 goto err_configure_lan_hmc;
1225 /* Get and check the mac address */
1226 i40e_get_mac_addr(hw, hw->mac.addr);
1227 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1228 PMD_INIT_LOG(ERR, "mac address is not valid");
1230 goto err_get_mac_addr;
1232 /* Copy the permanent MAC address */
1233 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1234 (struct ether_addr *) hw->mac.perm_addr);
1236 /* Disable flow control */
1237 hw->fc.requested_mode = I40E_FC_NONE;
1238 i40e_set_fc(hw, &aq_fail, TRUE);
1240 /* Set the global registers with default ether type value */
1241 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1242 if (ret != I40E_SUCCESS) {
1244 "Failed to set the default outer VLAN ether type");
1245 goto err_setup_pf_switch;
1248 /* PF setup, which includes VSI setup */
1249 ret = i40e_pf_setup(pf);
1251 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1252 goto err_setup_pf_switch;
1255 /* reset all stats of the device, including pf and main vsi */
1256 i40e_dev_stats_reset(dev);
1260 /* Disable double vlan by default */
1261 i40e_vsi_config_double_vlan(vsi, FALSE);
1263 /* Disable S-TAG identification when floating_veb is disabled */
1264 if (!pf->floating_veb) {
1265 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1266 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1267 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1268 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1272 if (!vsi->max_macaddrs)
1273 len = ETHER_ADDR_LEN;
1275 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1277 /* Should be after VSI initialized */
1278 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1279 if (!dev->data->mac_addrs) {
1281 "Failed to allocated memory for storing mac address");
1284 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1285 &dev->data->mac_addrs[0]);
1287 /* Init dcb to sw mode by default */
1288 ret = i40e_dcb_init_configure(dev, TRUE);
1289 if (ret != I40E_SUCCESS) {
1290 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1291 pf->flags &= ~I40E_FLAG_DCB;
1293 /* Update HW struct after DCB configuration */
1296 /* initialize pf host driver to setup SRIOV resource if applicable */
1297 i40e_pf_host_init(dev);
1299 /* register callback func to eal lib */
1300 rte_intr_callback_register(intr_handle,
1301 i40e_dev_interrupt_handler, dev);
1303 /* configure and enable device interrupt */
1304 i40e_pf_config_irq0(hw, TRUE);
1305 i40e_pf_enable_irq0(hw);
1307 /* enable uio intr after callback register */
1308 rte_intr_enable(intr_handle);
1310 * Add an ethertype filter to drop all flow control frames transmitted
1311 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1314 i40e_add_tx_flow_control_drop_filter(pf);
1316 /* Set the max frame size to 0x2600 by default,
1317 * in case other drivers changed the default value.
1319 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1321 /* initialize mirror rule list */
1322 TAILQ_INIT(&pf->mirror_list);
1324 /* initialize Traffic Manager configuration */
1325 i40e_tm_conf_init(dev);
1327 /* Initialize customized information */
1328 i40e_init_customized_info(pf);
1330 ret = i40e_init_ethtype_filter_list(dev);
1332 goto err_init_ethtype_filter_list;
1333 ret = i40e_init_tunnel_filter_list(dev);
1335 goto err_init_tunnel_filter_list;
1336 ret = i40e_init_fdir_filter_list(dev);
1338 goto err_init_fdir_filter_list;
1342 err_init_fdir_filter_list:
1343 rte_free(pf->tunnel.hash_table);
1344 rte_free(pf->tunnel.hash_map);
1345 err_init_tunnel_filter_list:
1346 rte_free(pf->ethertype.hash_table);
1347 rte_free(pf->ethertype.hash_map);
1348 err_init_ethtype_filter_list:
1349 rte_free(dev->data->mac_addrs);
1351 i40e_vsi_release(pf->main_vsi);
1352 err_setup_pf_switch:
1354 err_configure_lan_hmc:
1355 (void)i40e_shutdown_lan_hmc(hw);
1357 i40e_res_pool_destroy(&pf->msix_pool);
1359 i40e_res_pool_destroy(&pf->qp_pool);
1362 err_get_capabilities:
1363 (void)i40e_shutdown_adminq(hw);
1369 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1371 struct i40e_ethertype_filter *p_ethertype;
1372 struct i40e_ethertype_rule *ethertype_rule;
1374 ethertype_rule = &pf->ethertype;
1375 /* Remove all ethertype filter rules and hash */
1376 if (ethertype_rule->hash_map)
1377 rte_free(ethertype_rule->hash_map);
1378 if (ethertype_rule->hash_table)
1379 rte_hash_free(ethertype_rule->hash_table);
1381 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1382 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1383 p_ethertype, rules);
1384 rte_free(p_ethertype);
1389 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1391 struct i40e_tunnel_filter *p_tunnel;
1392 struct i40e_tunnel_rule *tunnel_rule;
1394 tunnel_rule = &pf->tunnel;
1395 /* Remove all tunnel director rules and hash */
1396 if (tunnel_rule->hash_map)
1397 rte_free(tunnel_rule->hash_map);
1398 if (tunnel_rule->hash_table)
1399 rte_hash_free(tunnel_rule->hash_table);
1401 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1402 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1408 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1410 struct i40e_fdir_filter *p_fdir;
1411 struct i40e_fdir_info *fdir_info;
1413 fdir_info = &pf->fdir;
1414 /* Remove all flow director rules and hash */
1415 if (fdir_info->hash_map)
1416 rte_free(fdir_info->hash_map);
1417 if (fdir_info->hash_table)
1418 rte_hash_free(fdir_info->hash_table);
1420 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1421 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1427 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1430 struct rte_pci_device *pci_dev;
1431 struct rte_intr_handle *intr_handle;
1433 struct i40e_filter_control_settings settings;
1434 struct rte_flow *p_flow;
1436 uint8_t aq_fail = 0;
1438 PMD_INIT_FUNC_TRACE();
1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1443 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1446 intr_handle = &pci_dev->intr_handle;
1448 if (hw->adapter_stopped == 0)
1449 i40e_dev_close(dev);
1451 dev->dev_ops = NULL;
1452 dev->rx_pkt_burst = NULL;
1453 dev->tx_pkt_burst = NULL;
1455 /* Clear PXE mode */
1456 i40e_clear_pxe_mode(hw);
1458 /* Unconfigure filter control */
1459 memset(&settings, 0, sizeof(settings));
1460 ret = i40e_set_filter_control(hw, &settings);
1462 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1465 /* Disable flow control */
1466 hw->fc.requested_mode = I40E_FC_NONE;
1467 i40e_set_fc(hw, &aq_fail, TRUE);
1469 /* uninitialize pf host driver */
1470 i40e_pf_host_uninit(dev);
1472 rte_free(dev->data->mac_addrs);
1473 dev->data->mac_addrs = NULL;
1475 /* disable uio intr before callback unregister */
1476 rte_intr_disable(intr_handle);
1478 /* register callback func to eal lib */
1479 rte_intr_callback_unregister(intr_handle,
1480 i40e_dev_interrupt_handler, dev);
1482 i40e_rm_ethtype_filter_list(pf);
1483 i40e_rm_tunnel_filter_list(pf);
1484 i40e_rm_fdir_filter_list(pf);
1486 /* Remove all flows */
1487 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1488 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1492 /* Remove all Traffic Manager configuration */
1493 i40e_tm_conf_uninit(dev);
1499 i40e_dev_configure(struct rte_eth_dev *dev)
1501 struct i40e_adapter *ad =
1502 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1503 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1508 ret = i40e_dev_sync_phy_type(hw);
1512 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1513 * bulk allocation or vector Rx preconditions we will reset it.
1515 ad->rx_bulk_alloc_allowed = true;
1516 ad->rx_vec_allowed = true;
1517 ad->tx_simple_allowed = true;
1518 ad->tx_vec_allowed = true;
1520 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1521 ret = i40e_fdir_setup(pf);
1522 if (ret != I40E_SUCCESS) {
1523 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1526 ret = i40e_fdir_configure(dev);
1528 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1532 i40e_fdir_teardown(pf);
1534 ret = i40e_dev_init_vlan(dev);
1539 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1540 * RSS setting have different requirements.
1541 * General PMD driver call sequence are NIC init, configure,
1542 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1543 * will try to lookup the VSI that specific queue belongs to if VMDQ
1544 * applicable. So, VMDQ setting has to be done before
1545 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1546 * For RSS setting, it will try to calculate actual configured RX queue
1547 * number, which will be available after rx_queue_setup(). dev_start()
1548 * function is good to place RSS setup.
1550 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1551 ret = i40e_vmdq_setup(dev);
1556 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1557 ret = i40e_dcb_setup(dev);
1559 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1564 TAILQ_INIT(&pf->flow_list);
1569 /* need to release vmdq resource if exists */
1570 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1571 i40e_vsi_release(pf->vmdq[i].vsi);
1572 pf->vmdq[i].vsi = NULL;
1577 /* need to release fdir resource if exists */
1578 i40e_fdir_teardown(pf);
1583 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1585 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1586 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1589 uint16_t msix_vect = vsi->msix_intr;
1592 for (i = 0; i < vsi->nb_qps; i++) {
1593 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1594 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1598 if (vsi->type != I40E_VSI_SRIOV) {
1599 if (!rte_intr_allow_others(intr_handle)) {
1600 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1601 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1603 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1606 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1607 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1609 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1614 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1615 vsi->user_param + (msix_vect - 1);
1617 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1618 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1620 I40E_WRITE_FLUSH(hw);
1624 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1625 int base_queue, int nb_queue,
1630 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1632 /* Bind all RX queues to allocated MSIX interrupt */
1633 for (i = 0; i < nb_queue; i++) {
1634 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1635 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1636 ((base_queue + i + 1) <<
1637 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1638 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1639 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1641 if (i == nb_queue - 1)
1642 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1643 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1646 /* Write first RX queue to Link list register as the head element */
1647 if (vsi->type != I40E_VSI_SRIOV) {
1649 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1651 if (msix_vect == I40E_MISC_VEC_ID) {
1652 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1654 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1656 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1658 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1661 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1663 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1665 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1667 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1674 if (msix_vect == I40E_MISC_VEC_ID) {
1676 I40E_VPINT_LNKLST0(vsi->user_param),
1678 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1680 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1682 /* num_msix_vectors_vf needs to minus irq0 */
1683 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1684 vsi->user_param + (msix_vect - 1);
1686 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1688 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1690 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1694 I40E_WRITE_FLUSH(hw);
1698 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1700 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1701 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1702 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1703 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1704 uint16_t msix_vect = vsi->msix_intr;
1705 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1706 uint16_t queue_idx = 0;
1711 for (i = 0; i < vsi->nb_qps; i++) {
1712 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1713 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1716 /* INTENA flag is not auto-cleared for interrupt */
1717 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1718 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1719 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1720 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1721 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1723 /* VF bind interrupt */
1724 if (vsi->type == I40E_VSI_SRIOV) {
1725 __vsi_queues_bind_intr(vsi, msix_vect,
1726 vsi->base_queue, vsi->nb_qps,
1731 /* PF & VMDq bind interrupt */
1732 if (rte_intr_dp_is_en(intr_handle)) {
1733 if (vsi->type == I40E_VSI_MAIN) {
1736 } else if (vsi->type == I40E_VSI_VMDQ2) {
1737 struct i40e_vsi *main_vsi =
1738 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1739 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1744 for (i = 0; i < vsi->nb_used_qps; i++) {
1746 if (!rte_intr_allow_others(intr_handle))
1747 /* allow to share MISC_VEC_ID */
1748 msix_vect = I40E_MISC_VEC_ID;
1750 /* no enough msix_vect, map all to one */
1751 __vsi_queues_bind_intr(vsi, msix_vect,
1752 vsi->base_queue + i,
1753 vsi->nb_used_qps - i,
1755 for (; !!record && i < vsi->nb_used_qps; i++)
1756 intr_handle->intr_vec[queue_idx + i] =
1760 /* 1:1 queue/msix_vect mapping */
1761 __vsi_queues_bind_intr(vsi, msix_vect,
1762 vsi->base_queue + i, 1,
1765 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1773 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1775 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779 uint16_t interval = i40e_calc_itr_interval(\
1780 RTE_LIBRTE_I40E_ITR_INTERVAL);
1781 uint16_t msix_intr, i;
1783 if (rte_intr_allow_others(intr_handle))
1784 for (i = 0; i < vsi->nb_msix; i++) {
1785 msix_intr = vsi->msix_intr + i;
1786 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1787 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1788 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1789 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1791 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1794 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1795 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1796 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1797 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1799 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1801 I40E_WRITE_FLUSH(hw);
1805 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1807 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1808 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1809 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1810 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1811 uint16_t msix_intr, i;
1813 if (rte_intr_allow_others(intr_handle))
1814 for (i = 0; i < vsi->nb_msix; i++) {
1815 msix_intr = vsi->msix_intr + i;
1816 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1820 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1822 I40E_WRITE_FLUSH(hw);
1825 static inline uint8_t
1826 i40e_parse_link_speeds(uint16_t link_speeds)
1828 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1830 if (link_speeds & ETH_LINK_SPEED_40G)
1831 link_speed |= I40E_LINK_SPEED_40GB;
1832 if (link_speeds & ETH_LINK_SPEED_25G)
1833 link_speed |= I40E_LINK_SPEED_25GB;
1834 if (link_speeds & ETH_LINK_SPEED_20G)
1835 link_speed |= I40E_LINK_SPEED_20GB;
1836 if (link_speeds & ETH_LINK_SPEED_10G)
1837 link_speed |= I40E_LINK_SPEED_10GB;
1838 if (link_speeds & ETH_LINK_SPEED_1G)
1839 link_speed |= I40E_LINK_SPEED_1GB;
1840 if (link_speeds & ETH_LINK_SPEED_100M)
1841 link_speed |= I40E_LINK_SPEED_100MB;
1847 i40e_phy_conf_link(struct i40e_hw *hw,
1849 uint8_t force_speed,
1852 enum i40e_status_code status;
1853 struct i40e_aq_get_phy_abilities_resp phy_ab;
1854 struct i40e_aq_set_phy_config phy_conf;
1855 enum i40e_aq_phy_type cnt;
1856 uint32_t phy_type_mask = 0;
1858 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1859 I40E_AQ_PHY_FLAG_PAUSE_RX |
1860 I40E_AQ_PHY_FLAG_PAUSE_RX |
1861 I40E_AQ_PHY_FLAG_LOW_POWER;
1862 const uint8_t advt = I40E_LINK_SPEED_40GB |
1863 I40E_LINK_SPEED_25GB |
1864 I40E_LINK_SPEED_10GB |
1865 I40E_LINK_SPEED_1GB |
1866 I40E_LINK_SPEED_100MB;
1870 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1875 /* If link already up, no need to set up again */
1876 if (is_up && phy_ab.phy_type != 0)
1877 return I40E_SUCCESS;
1879 memset(&phy_conf, 0, sizeof(phy_conf));
1881 /* bits 0-2 use the values from get_phy_abilities_resp */
1883 abilities |= phy_ab.abilities & mask;
1885 /* update ablities and speed */
1886 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1887 phy_conf.link_speed = advt;
1889 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1891 phy_conf.abilities = abilities;
1895 /* To enable link, phy_type mask needs to include each type */
1896 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1897 phy_type_mask |= 1 << cnt;
1899 /* use get_phy_abilities_resp value for the rest */
1900 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1901 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1902 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1903 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1904 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1905 phy_conf.eee_capability = phy_ab.eee_capability;
1906 phy_conf.eeer = phy_ab.eeer_val;
1907 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1909 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1910 phy_ab.abilities, phy_ab.link_speed);
1911 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1912 phy_conf.abilities, phy_conf.link_speed);
1914 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1918 return I40E_SUCCESS;
1922 i40e_apply_link_speed(struct rte_eth_dev *dev)
1925 uint8_t abilities = 0;
1926 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927 struct rte_eth_conf *conf = &dev->data->dev_conf;
1929 speed = i40e_parse_link_speeds(conf->link_speeds);
1930 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1931 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1932 abilities |= I40E_AQ_PHY_AN_ENABLED;
1933 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1935 return i40e_phy_conf_link(hw, abilities, speed, true);
1939 i40e_dev_start(struct rte_eth_dev *dev)
1941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943 struct i40e_vsi *main_vsi = pf->main_vsi;
1945 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1946 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1947 uint32_t intr_vector = 0;
1948 struct i40e_vsi *vsi;
1950 hw->adapter_stopped = 0;
1952 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1953 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1954 dev->data->port_id);
1958 rte_intr_disable(intr_handle);
1960 if ((rte_intr_cap_multiple(intr_handle) ||
1961 !RTE_ETH_DEV_SRIOV(dev).active) &&
1962 dev->data->dev_conf.intr_conf.rxq != 0) {
1963 intr_vector = dev->data->nb_rx_queues;
1964 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1969 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1970 intr_handle->intr_vec =
1971 rte_zmalloc("intr_vec",
1972 dev->data->nb_rx_queues * sizeof(int),
1974 if (!intr_handle->intr_vec) {
1976 "Failed to allocate %d rx_queues intr_vec",
1977 dev->data->nb_rx_queues);
1982 /* Initialize VSI */
1983 ret = i40e_dev_rxtx_init(pf);
1984 if (ret != I40E_SUCCESS) {
1985 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1989 /* Map queues with MSIX interrupt */
1990 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1991 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1992 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1993 i40e_vsi_enable_queues_intr(main_vsi);
1995 /* Map VMDQ VSI queues with MSIX interrupt */
1996 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1997 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1998 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1999 I40E_ITR_INDEX_DEFAULT);
2000 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2003 /* enable FDIR MSIX interrupt */
2004 if (pf->fdir.fdir_vsi) {
2005 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2006 I40E_ITR_INDEX_NONE);
2007 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2010 /* Enable all queues which have been configured */
2011 ret = i40e_dev_switch_queues(pf, TRUE);
2012 if (ret != I40E_SUCCESS) {
2013 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2017 /* Enable receiving broadcast packets */
2018 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2019 if (ret != I40E_SUCCESS)
2020 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2022 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2023 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2025 if (ret != I40E_SUCCESS)
2026 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2029 /* Enable the VLAN promiscuous mode. */
2031 for (i = 0; i < pf->vf_num; i++) {
2032 vsi = pf->vfs[i].vsi;
2033 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2038 /* Apply link configure */
2039 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2040 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2041 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2042 ETH_LINK_SPEED_40G)) {
2043 PMD_DRV_LOG(ERR, "Invalid link setting");
2046 ret = i40e_apply_link_speed(dev);
2047 if (I40E_SUCCESS != ret) {
2048 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2052 if (!rte_intr_allow_others(intr_handle)) {
2053 rte_intr_callback_unregister(intr_handle,
2054 i40e_dev_interrupt_handler,
2056 /* configure and enable device interrupt */
2057 i40e_pf_config_irq0(hw, FALSE);
2058 i40e_pf_enable_irq0(hw);
2060 if (dev->data->dev_conf.intr_conf.lsc != 0)
2062 "lsc won't enable because of no intr multiplex");
2064 ret = i40e_aq_set_phy_int_mask(hw,
2065 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2066 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2067 I40E_AQ_EVENT_MEDIA_NA), NULL);
2068 if (ret != I40E_SUCCESS)
2069 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2071 /* Call get_link_info aq commond to enable/disable LSE */
2072 i40e_dev_link_update(dev, 0);
2075 /* enable uio intr after callback register */
2076 rte_intr_enable(intr_handle);
2078 i40e_filter_restore(pf);
2080 if (pf->tm_conf.root && !pf->tm_conf.committed)
2081 PMD_DRV_LOG(WARNING,
2082 "please call hierarchy_commit() "
2083 "before starting the port");
2085 return I40E_SUCCESS;
2088 i40e_dev_switch_queues(pf, FALSE);
2089 i40e_dev_clear_queues(dev);
2095 i40e_dev_stop(struct rte_eth_dev *dev)
2097 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2098 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099 struct i40e_vsi *main_vsi = pf->main_vsi;
2100 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2101 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2104 if (hw->adapter_stopped == 1)
2106 /* Disable all queues */
2107 i40e_dev_switch_queues(pf, FALSE);
2109 /* un-map queues with interrupt registers */
2110 i40e_vsi_disable_queues_intr(main_vsi);
2111 i40e_vsi_queues_unbind_intr(main_vsi);
2113 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2115 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2118 if (pf->fdir.fdir_vsi) {
2119 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2120 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2122 /* Clear all queues and release memory */
2123 i40e_dev_clear_queues(dev);
2126 i40e_dev_set_link_down(dev);
2128 if (!rte_intr_allow_others(intr_handle))
2129 /* resume to the default handler */
2130 rte_intr_callback_register(intr_handle,
2131 i40e_dev_interrupt_handler,
2134 /* Clean datapath event and queue/vec mapping */
2135 rte_intr_efd_disable(intr_handle);
2136 if (intr_handle->intr_vec) {
2137 rte_free(intr_handle->intr_vec);
2138 intr_handle->intr_vec = NULL;
2141 /* reset hierarchy commit */
2142 pf->tm_conf.committed = false;
2144 hw->adapter_stopped = 1;
2148 i40e_dev_close(struct rte_eth_dev *dev)
2150 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2153 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2154 struct i40e_mirror_rule *p_mirror;
2159 PMD_INIT_FUNC_TRACE();
2163 /* Remove all mirror rules */
2164 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2165 ret = i40e_aq_del_mirror_rule(hw,
2166 pf->main_vsi->veb->seid,
2167 p_mirror->rule_type,
2169 p_mirror->num_entries,
2172 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2173 "status = %d, aq_err = %d.", ret,
2174 hw->aq.asq_last_status);
2176 /* remove mirror software resource anyway */
2177 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2179 pf->nb_mirror_rule--;
2182 i40e_dev_free_queues(dev);
2184 /* Disable interrupt */
2185 i40e_pf_disable_irq0(hw);
2186 rte_intr_disable(intr_handle);
2188 /* shutdown and destroy the HMC */
2189 i40e_shutdown_lan_hmc(hw);
2191 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2192 i40e_vsi_release(pf->vmdq[i].vsi);
2193 pf->vmdq[i].vsi = NULL;
2198 /* release all the existing VSIs and VEBs */
2199 i40e_fdir_teardown(pf);
2200 i40e_vsi_release(pf->main_vsi);
2202 /* shutdown the adminq */
2203 i40e_aq_queue_shutdown(hw, true);
2204 i40e_shutdown_adminq(hw);
2206 i40e_res_pool_destroy(&pf->qp_pool);
2207 i40e_res_pool_destroy(&pf->msix_pool);
2209 /* force a PF reset to clean anything leftover */
2210 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2211 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2212 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2213 I40E_WRITE_FLUSH(hw);
2217 * Reset PF device only to re-initialize resources in PMD layer
2220 i40e_dev_reset(struct rte_eth_dev *dev)
2224 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2225 * its VF to make them align with it. The detailed notification
2226 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2227 * To avoid unexpected behavior in VF, currently reset of PF with
2228 * SR-IOV activation is not supported. It might be supported later.
2230 if (dev->data->sriov.active)
2233 ret = eth_i40e_dev_uninit(dev);
2237 ret = eth_i40e_dev_init(dev);
2243 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2246 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247 struct i40e_vsi *vsi = pf->main_vsi;
2250 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2252 if (status != I40E_SUCCESS)
2253 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2255 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2257 if (status != I40E_SUCCESS)
2258 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2263 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2265 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2266 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267 struct i40e_vsi *vsi = pf->main_vsi;
2270 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2272 if (status != I40E_SUCCESS)
2273 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2275 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2277 if (status != I40E_SUCCESS)
2278 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2282 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2284 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2285 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286 struct i40e_vsi *vsi = pf->main_vsi;
2289 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2290 if (ret != I40E_SUCCESS)
2291 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2295 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2297 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2298 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2299 struct i40e_vsi *vsi = pf->main_vsi;
2302 if (dev->data->promiscuous == 1)
2303 return; /* must remain in all_multicast mode */
2305 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2306 vsi->seid, FALSE, NULL);
2307 if (ret != I40E_SUCCESS)
2308 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2312 * Set device link up.
2315 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2317 /* re-apply link speed setting */
2318 return i40e_apply_link_speed(dev);
2322 * Set device link down.
2325 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2327 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2328 uint8_t abilities = 0;
2329 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2332 return i40e_phy_conf_link(hw, abilities, speed, false);
2336 i40e_dev_link_update(struct rte_eth_dev *dev,
2337 int wait_to_complete)
2339 #define CHECK_INTERVAL 100 /* 100ms */
2340 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342 struct i40e_link_status link_status;
2343 struct rte_eth_link link, old;
2345 unsigned rep_cnt = MAX_REPEAT_TIME;
2346 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2348 memset(&link, 0, sizeof(link));
2349 memset(&old, 0, sizeof(old));
2350 memset(&link_status, 0, sizeof(link_status));
2351 rte_i40e_dev_atomic_read_link_status(dev, &old);
2354 /* Get link status information from hardware */
2355 status = i40e_aq_get_link_info(hw, enable_lse,
2356 &link_status, NULL);
2357 if (status != I40E_SUCCESS) {
2358 link.link_speed = ETH_SPEED_NUM_100M;
2359 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2360 PMD_DRV_LOG(ERR, "Failed to get link info");
2364 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2365 if (!wait_to_complete || link.link_status)
2368 rte_delay_ms(CHECK_INTERVAL);
2369 } while (--rep_cnt);
2371 if (!link.link_status)
2374 /* i40e uses full duplex only */
2375 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2377 /* Parse the link status */
2378 switch (link_status.link_speed) {
2379 case I40E_LINK_SPEED_100MB:
2380 link.link_speed = ETH_SPEED_NUM_100M;
2382 case I40E_LINK_SPEED_1GB:
2383 link.link_speed = ETH_SPEED_NUM_1G;
2385 case I40E_LINK_SPEED_10GB:
2386 link.link_speed = ETH_SPEED_NUM_10G;
2388 case I40E_LINK_SPEED_20GB:
2389 link.link_speed = ETH_SPEED_NUM_20G;
2391 case I40E_LINK_SPEED_25GB:
2392 link.link_speed = ETH_SPEED_NUM_25G;
2394 case I40E_LINK_SPEED_40GB:
2395 link.link_speed = ETH_SPEED_NUM_40G;
2398 link.link_speed = ETH_SPEED_NUM_100M;
2402 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2403 ETH_LINK_SPEED_FIXED);
2406 rte_i40e_dev_atomic_write_link_status(dev, &link);
2407 if (link.link_status == old.link_status)
2410 i40e_notify_all_vfs_link_status(dev);
2415 /* Get all the statistics of a VSI */
2417 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2419 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2420 struct i40e_eth_stats *nes = &vsi->eth_stats;
2421 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2422 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2424 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2425 vsi->offset_loaded, &oes->rx_bytes,
2427 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2428 vsi->offset_loaded, &oes->rx_unicast,
2430 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2431 vsi->offset_loaded, &oes->rx_multicast,
2432 &nes->rx_multicast);
2433 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2434 vsi->offset_loaded, &oes->rx_broadcast,
2435 &nes->rx_broadcast);
2436 /* exclude CRC bytes */
2437 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2438 nes->rx_broadcast) * ETHER_CRC_LEN;
2440 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2441 &oes->rx_discards, &nes->rx_discards);
2442 /* GLV_REPC not supported */
2443 /* GLV_RMPC not supported */
2444 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2445 &oes->rx_unknown_protocol,
2446 &nes->rx_unknown_protocol);
2447 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2448 vsi->offset_loaded, &oes->tx_bytes,
2450 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2451 vsi->offset_loaded, &oes->tx_unicast,
2453 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2454 vsi->offset_loaded, &oes->tx_multicast,
2455 &nes->tx_multicast);
2456 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2457 vsi->offset_loaded, &oes->tx_broadcast,
2458 &nes->tx_broadcast);
2459 /* GLV_TDPC not supported */
2460 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2461 &oes->tx_errors, &nes->tx_errors);
2462 vsi->offset_loaded = true;
2464 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2466 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2467 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2468 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2469 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2470 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2471 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2472 nes->rx_unknown_protocol);
2473 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2474 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2475 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2476 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2477 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2478 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2479 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2484 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2487 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2488 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2490 /* Get rx/tx bytes of internal transfer packets */
2491 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2492 I40E_GLV_GORCL(hw->port),
2494 &pf->internal_stats_offset.rx_bytes,
2495 &pf->internal_stats.rx_bytes);
2497 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2498 I40E_GLV_GOTCL(hw->port),
2500 &pf->internal_stats_offset.tx_bytes,
2501 &pf->internal_stats.tx_bytes);
2502 /* Get total internal rx packet count */
2503 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2504 I40E_GLV_UPRCL(hw->port),
2506 &pf->internal_stats_offset.rx_unicast,
2507 &pf->internal_stats.rx_unicast);
2508 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2509 I40E_GLV_MPRCL(hw->port),
2511 &pf->internal_stats_offset.rx_multicast,
2512 &pf->internal_stats.rx_multicast);
2513 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2514 I40E_GLV_BPRCL(hw->port),
2516 &pf->internal_stats_offset.rx_broadcast,
2517 &pf->internal_stats.rx_broadcast);
2519 /* exclude CRC size */
2520 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2521 pf->internal_stats.rx_multicast +
2522 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2524 /* Get statistics of struct i40e_eth_stats */
2525 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2526 I40E_GLPRT_GORCL(hw->port),
2527 pf->offset_loaded, &os->eth.rx_bytes,
2529 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2530 I40E_GLPRT_UPRCL(hw->port),
2531 pf->offset_loaded, &os->eth.rx_unicast,
2532 &ns->eth.rx_unicast);
2533 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2534 I40E_GLPRT_MPRCL(hw->port),
2535 pf->offset_loaded, &os->eth.rx_multicast,
2536 &ns->eth.rx_multicast);
2537 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2538 I40E_GLPRT_BPRCL(hw->port),
2539 pf->offset_loaded, &os->eth.rx_broadcast,
2540 &ns->eth.rx_broadcast);
2541 /* Workaround: CRC size should not be included in byte statistics,
2542 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2544 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2545 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2547 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2548 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2551 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2552 ns->eth.rx_bytes = 0;
2553 /* exlude internal rx bytes */
2555 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2557 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2558 pf->offset_loaded, &os->eth.rx_discards,
2559 &ns->eth.rx_discards);
2560 /* GLPRT_REPC not supported */
2561 /* GLPRT_RMPC not supported */
2562 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2564 &os->eth.rx_unknown_protocol,
2565 &ns->eth.rx_unknown_protocol);
2566 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2567 I40E_GLPRT_GOTCL(hw->port),
2568 pf->offset_loaded, &os->eth.tx_bytes,
2570 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2571 I40E_GLPRT_UPTCL(hw->port),
2572 pf->offset_loaded, &os->eth.tx_unicast,
2573 &ns->eth.tx_unicast);
2574 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2575 I40E_GLPRT_MPTCL(hw->port),
2576 pf->offset_loaded, &os->eth.tx_multicast,
2577 &ns->eth.tx_multicast);
2578 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2579 I40E_GLPRT_BPTCL(hw->port),
2580 pf->offset_loaded, &os->eth.tx_broadcast,
2581 &ns->eth.tx_broadcast);
2582 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2583 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2585 /* exclude internal tx bytes */
2586 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2587 ns->eth.tx_bytes = 0;
2589 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2591 /* GLPRT_TEPC not supported */
2593 /* additional port specific stats */
2594 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2595 pf->offset_loaded, &os->tx_dropped_link_down,
2596 &ns->tx_dropped_link_down);
2597 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2598 pf->offset_loaded, &os->crc_errors,
2600 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2601 pf->offset_loaded, &os->illegal_bytes,
2602 &ns->illegal_bytes);
2603 /* GLPRT_ERRBC not supported */
2604 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2605 pf->offset_loaded, &os->mac_local_faults,
2606 &ns->mac_local_faults);
2607 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2608 pf->offset_loaded, &os->mac_remote_faults,
2609 &ns->mac_remote_faults);
2610 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2611 pf->offset_loaded, &os->rx_length_errors,
2612 &ns->rx_length_errors);
2613 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2614 pf->offset_loaded, &os->link_xon_rx,
2616 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2617 pf->offset_loaded, &os->link_xoff_rx,
2619 for (i = 0; i < 8; i++) {
2620 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2622 &os->priority_xon_rx[i],
2623 &ns->priority_xon_rx[i]);
2624 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2626 &os->priority_xoff_rx[i],
2627 &ns->priority_xoff_rx[i]);
2629 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2630 pf->offset_loaded, &os->link_xon_tx,
2632 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2633 pf->offset_loaded, &os->link_xoff_tx,
2635 for (i = 0; i < 8; i++) {
2636 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2638 &os->priority_xon_tx[i],
2639 &ns->priority_xon_tx[i]);
2640 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2642 &os->priority_xoff_tx[i],
2643 &ns->priority_xoff_tx[i]);
2644 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2646 &os->priority_xon_2_xoff[i],
2647 &ns->priority_xon_2_xoff[i]);
2649 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2650 I40E_GLPRT_PRC64L(hw->port),
2651 pf->offset_loaded, &os->rx_size_64,
2653 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2654 I40E_GLPRT_PRC127L(hw->port),
2655 pf->offset_loaded, &os->rx_size_127,
2657 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2658 I40E_GLPRT_PRC255L(hw->port),
2659 pf->offset_loaded, &os->rx_size_255,
2661 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2662 I40E_GLPRT_PRC511L(hw->port),
2663 pf->offset_loaded, &os->rx_size_511,
2665 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2666 I40E_GLPRT_PRC1023L(hw->port),
2667 pf->offset_loaded, &os->rx_size_1023,
2669 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2670 I40E_GLPRT_PRC1522L(hw->port),
2671 pf->offset_loaded, &os->rx_size_1522,
2673 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2674 I40E_GLPRT_PRC9522L(hw->port),
2675 pf->offset_loaded, &os->rx_size_big,
2677 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2678 pf->offset_loaded, &os->rx_undersize,
2680 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2681 pf->offset_loaded, &os->rx_fragments,
2683 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2684 pf->offset_loaded, &os->rx_oversize,
2686 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2687 pf->offset_loaded, &os->rx_jabber,
2689 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2690 I40E_GLPRT_PTC64L(hw->port),
2691 pf->offset_loaded, &os->tx_size_64,
2693 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2694 I40E_GLPRT_PTC127L(hw->port),
2695 pf->offset_loaded, &os->tx_size_127,
2697 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2698 I40E_GLPRT_PTC255L(hw->port),
2699 pf->offset_loaded, &os->tx_size_255,
2701 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2702 I40E_GLPRT_PTC511L(hw->port),
2703 pf->offset_loaded, &os->tx_size_511,
2705 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2706 I40E_GLPRT_PTC1023L(hw->port),
2707 pf->offset_loaded, &os->tx_size_1023,
2709 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2710 I40E_GLPRT_PTC1522L(hw->port),
2711 pf->offset_loaded, &os->tx_size_1522,
2713 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2714 I40E_GLPRT_PTC9522L(hw->port),
2715 pf->offset_loaded, &os->tx_size_big,
2717 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2719 &os->fd_sb_match, &ns->fd_sb_match);
2720 /* GLPRT_MSPDC not supported */
2721 /* GLPRT_XEC not supported */
2723 pf->offset_loaded = true;
2726 i40e_update_vsi_stats(pf->main_vsi);
2729 /* Get all statistics of a port */
2731 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2733 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2734 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2738 /* call read registers - updates values, now write them to struct */
2739 i40e_read_stats_registers(pf, hw);
2741 stats->ipackets = ns->eth.rx_unicast +
2742 ns->eth.rx_multicast +
2743 ns->eth.rx_broadcast -
2744 ns->eth.rx_discards -
2745 pf->main_vsi->eth_stats.rx_discards;
2746 stats->opackets = ns->eth.tx_unicast +
2747 ns->eth.tx_multicast +
2748 ns->eth.tx_broadcast;
2749 stats->ibytes = ns->eth.rx_bytes;
2750 stats->obytes = ns->eth.tx_bytes;
2751 stats->oerrors = ns->eth.tx_errors +
2752 pf->main_vsi->eth_stats.tx_errors;
2755 stats->imissed = ns->eth.rx_discards +
2756 pf->main_vsi->eth_stats.rx_discards;
2757 stats->ierrors = ns->crc_errors +
2758 ns->rx_length_errors + ns->rx_undersize +
2759 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2761 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2762 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2763 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2764 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2765 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2766 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2767 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2768 ns->eth.rx_unknown_protocol);
2769 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2770 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2771 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2772 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2773 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2774 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2776 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2777 ns->tx_dropped_link_down);
2778 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2779 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2781 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2782 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2783 ns->mac_local_faults);
2784 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2785 ns->mac_remote_faults);
2786 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2787 ns->rx_length_errors);
2788 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2789 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2790 for (i = 0; i < 8; i++) {
2791 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2792 i, ns->priority_xon_rx[i]);
2793 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2794 i, ns->priority_xoff_rx[i]);
2796 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2797 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2798 for (i = 0; i < 8; i++) {
2799 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2800 i, ns->priority_xon_tx[i]);
2801 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2802 i, ns->priority_xoff_tx[i]);
2803 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2804 i, ns->priority_xon_2_xoff[i]);
2806 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2807 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2808 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2809 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2810 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2811 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2812 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2813 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2814 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2815 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2816 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2817 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2818 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2819 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2820 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2821 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2822 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2823 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2824 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2825 ns->mac_short_packet_dropped);
2826 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2827 ns->checksum_error);
2828 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2829 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2832 /* Reset the statistics */
2834 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2836 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2837 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839 /* Mark PF and VSI stats to update the offset, aka "reset" */
2840 pf->offset_loaded = false;
2842 pf->main_vsi->offset_loaded = false;
2844 /* read the stats, reading current register values into offset */
2845 i40e_read_stats_registers(pf, hw);
2849 i40e_xstats_calc_num(void)
2851 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2852 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2853 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2856 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2857 struct rte_eth_xstat_name *xstats_names,
2858 __rte_unused unsigned limit)
2863 if (xstats_names == NULL)
2864 return i40e_xstats_calc_num();
2866 /* Note: limit checked in rte_eth_xstats_names() */
2868 /* Get stats from i40e_eth_stats struct */
2869 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2870 snprintf(xstats_names[count].name,
2871 sizeof(xstats_names[count].name),
2872 "%s", rte_i40e_stats_strings[i].name);
2876 /* Get individiual stats from i40e_hw_port struct */
2877 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2878 snprintf(xstats_names[count].name,
2879 sizeof(xstats_names[count].name),
2880 "%s", rte_i40e_hw_port_strings[i].name);
2884 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2885 for (prio = 0; prio < 8; prio++) {
2886 snprintf(xstats_names[count].name,
2887 sizeof(xstats_names[count].name),
2888 "rx_priority%u_%s", prio,
2889 rte_i40e_rxq_prio_strings[i].name);
2894 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2895 for (prio = 0; prio < 8; prio++) {
2896 snprintf(xstats_names[count].name,
2897 sizeof(xstats_names[count].name),
2898 "tx_priority%u_%s", prio,
2899 rte_i40e_txq_prio_strings[i].name);
2907 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2910 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2911 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912 unsigned i, count, prio;
2913 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2915 count = i40e_xstats_calc_num();
2919 i40e_read_stats_registers(pf, hw);
2926 /* Get stats from i40e_eth_stats struct */
2927 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2928 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2929 rte_i40e_stats_strings[i].offset);
2930 xstats[count].id = count;
2934 /* Get individiual stats from i40e_hw_port struct */
2935 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2936 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2937 rte_i40e_hw_port_strings[i].offset);
2938 xstats[count].id = count;
2942 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2943 for (prio = 0; prio < 8; prio++) {
2944 xstats[count].value =
2945 *(uint64_t *)(((char *)hw_stats) +
2946 rte_i40e_rxq_prio_strings[i].offset +
2947 (sizeof(uint64_t) * prio));
2948 xstats[count].id = count;
2953 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2954 for (prio = 0; prio < 8; prio++) {
2955 xstats[count].value =
2956 *(uint64_t *)(((char *)hw_stats) +
2957 rte_i40e_txq_prio_strings[i].offset +
2958 (sizeof(uint64_t) * prio));
2959 xstats[count].id = count;
2968 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2969 __rte_unused uint16_t queue_id,
2970 __rte_unused uint8_t stat_idx,
2971 __rte_unused uint8_t is_rx)
2973 PMD_INIT_FUNC_TRACE();
2979 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2987 full_ver = hw->nvm.oem_ver;
2988 ver = (u8)(full_ver >> 24);
2989 build = (u16)((full_ver >> 8) & 0xffff);
2990 patch = (u8)(full_ver & 0xff);
2992 ret = snprintf(fw_version, fw_size,
2993 "%d.%d%d 0x%08x %d.%d.%d",
2994 ((hw->nvm.version >> 12) & 0xf),
2995 ((hw->nvm.version >> 4) & 0xff),
2996 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2999 ret += 1; /* add the size of '\0' */
3000 if (fw_size < (u32)ret)
3007 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3009 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3011 struct i40e_vsi *vsi = pf->main_vsi;
3012 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3014 dev_info->pci_dev = pci_dev;
3015 dev_info->max_rx_queues = vsi->nb_qps;
3016 dev_info->max_tx_queues = vsi->nb_qps;
3017 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3018 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3019 dev_info->max_mac_addrs = vsi->max_macaddrs;
3020 dev_info->max_vfs = pci_dev->max_vfs;
3021 dev_info->rx_offload_capa =
3022 DEV_RX_OFFLOAD_VLAN_STRIP |
3023 DEV_RX_OFFLOAD_QINQ_STRIP |
3024 DEV_RX_OFFLOAD_IPV4_CKSUM |
3025 DEV_RX_OFFLOAD_UDP_CKSUM |
3026 DEV_RX_OFFLOAD_TCP_CKSUM;
3027 dev_info->tx_offload_capa =
3028 DEV_TX_OFFLOAD_VLAN_INSERT |
3029 DEV_TX_OFFLOAD_QINQ_INSERT |
3030 DEV_TX_OFFLOAD_IPV4_CKSUM |
3031 DEV_TX_OFFLOAD_UDP_CKSUM |
3032 DEV_TX_OFFLOAD_TCP_CKSUM |
3033 DEV_TX_OFFLOAD_SCTP_CKSUM |
3034 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3035 DEV_TX_OFFLOAD_TCP_TSO |
3036 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3037 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3038 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3039 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3040 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3042 dev_info->reta_size = pf->hash_lut_size;
3043 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3045 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3047 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3048 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3049 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3051 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3055 dev_info->default_txconf = (struct rte_eth_txconf) {
3057 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3058 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3059 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3061 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3062 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3063 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3064 ETH_TXQ_FLAGS_NOOFFLOADS,
3067 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3068 .nb_max = I40E_MAX_RING_DESC,
3069 .nb_min = I40E_MIN_RING_DESC,
3070 .nb_align = I40E_ALIGN_RING_DESC,
3073 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3074 .nb_max = I40E_MAX_RING_DESC,
3075 .nb_min = I40E_MIN_RING_DESC,
3076 .nb_align = I40E_ALIGN_RING_DESC,
3077 .nb_seg_max = I40E_TX_MAX_SEG,
3078 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3081 if (pf->flags & I40E_FLAG_VMDQ) {
3082 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3083 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3084 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3085 pf->max_nb_vmdq_vsi;
3086 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3087 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3088 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3091 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3093 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3094 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3096 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3099 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3103 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3106 struct i40e_vsi *vsi = pf->main_vsi;
3107 PMD_INIT_FUNC_TRACE();
3110 return i40e_vsi_add_vlan(vsi, vlan_id);
3112 return i40e_vsi_delete_vlan(vsi, vlan_id);
3116 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3117 enum rte_vlan_type vlan_type,
3118 uint16_t tpid, int qinq)
3120 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123 uint16_t reg_id = 3;
3127 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3131 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3133 if (ret != I40E_SUCCESS) {
3135 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3140 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3143 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3144 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3145 if (reg_r == reg_w) {
3146 PMD_DRV_LOG(DEBUG, "No need to write");
3150 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3152 if (ret != I40E_SUCCESS) {
3154 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3159 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3166 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3167 enum rte_vlan_type vlan_type,
3170 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3174 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3175 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3176 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3178 "Unsupported vlan type.");
3181 /* 802.1ad frames ability is added in NVM API 1.7*/
3182 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3184 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3185 hw->first_tag = rte_cpu_to_le_16(tpid);
3186 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3187 hw->second_tag = rte_cpu_to_le_16(tpid);
3189 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3190 hw->second_tag = rte_cpu_to_le_16(tpid);
3192 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3193 if (ret != I40E_SUCCESS) {
3195 "Set switch config failed aq_err: %d",
3196 hw->aq.asq_last_status);
3200 /* If NVM API < 1.7, keep the register setting */
3201 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3208 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3210 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211 struct i40e_vsi *vsi = pf->main_vsi;
3213 if (mask & ETH_VLAN_FILTER_MASK) {
3214 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3215 i40e_vsi_config_vlan_filter(vsi, TRUE);
3217 i40e_vsi_config_vlan_filter(vsi, FALSE);
3220 if (mask & ETH_VLAN_STRIP_MASK) {
3221 /* Enable or disable VLAN stripping */
3222 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3223 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3225 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3228 if (mask & ETH_VLAN_EXTEND_MASK) {
3229 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3230 i40e_vsi_config_double_vlan(vsi, TRUE);
3231 /* Set global registers with default ethertype. */
3232 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3234 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3238 i40e_vsi_config_double_vlan(vsi, FALSE);
3243 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3244 __rte_unused uint16_t queue,
3245 __rte_unused int on)
3247 PMD_INIT_FUNC_TRACE();
3251 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3253 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254 struct i40e_vsi *vsi = pf->main_vsi;
3255 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3256 struct i40e_vsi_vlan_pvid_info info;
3258 memset(&info, 0, sizeof(info));
3261 info.config.pvid = pvid;
3263 info.config.reject.tagged =
3264 data->dev_conf.txmode.hw_vlan_reject_tagged;
3265 info.config.reject.untagged =
3266 data->dev_conf.txmode.hw_vlan_reject_untagged;
3269 return i40e_vsi_vlan_pvid_set(vsi, &info);
3273 i40e_dev_led_on(struct rte_eth_dev *dev)
3275 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276 uint32_t mode = i40e_led_get(hw);
3279 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3285 i40e_dev_led_off(struct rte_eth_dev *dev)
3287 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 uint32_t mode = i40e_led_get(hw);
3291 i40e_led_set(hw, 0, false);
3297 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3299 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3302 fc_conf->pause_time = pf->fc_conf.pause_time;
3304 /* read out from register, in case they are modified by other port */
3305 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3306 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3307 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3308 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3310 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3311 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3313 /* Return current mode according to actual setting*/
3314 switch (hw->fc.current_mode) {
3316 fc_conf->mode = RTE_FC_FULL;
3318 case I40E_FC_TX_PAUSE:
3319 fc_conf->mode = RTE_FC_TX_PAUSE;
3321 case I40E_FC_RX_PAUSE:
3322 fc_conf->mode = RTE_FC_RX_PAUSE;
3326 fc_conf->mode = RTE_FC_NONE;
3333 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3335 uint32_t mflcn_reg, fctrl_reg, reg;
3336 uint32_t max_high_water;
3337 uint8_t i, aq_failure;
3341 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3342 [RTE_FC_NONE] = I40E_FC_NONE,
3343 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3344 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3345 [RTE_FC_FULL] = I40E_FC_FULL
3348 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3350 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3351 if ((fc_conf->high_water > max_high_water) ||
3352 (fc_conf->high_water < fc_conf->low_water)) {
3354 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3359 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3363 pf->fc_conf.pause_time = fc_conf->pause_time;
3364 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3365 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3367 PMD_INIT_FUNC_TRACE();
3369 /* All the link flow control related enable/disable register
3370 * configuration is handle by the F/W
3372 err = i40e_set_fc(hw, &aq_failure, true);
3376 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3377 /* Configure flow control refresh threshold,
3378 * the value for stat_tx_pause_refresh_timer[8]
3379 * is used for global pause operation.
3383 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3384 pf->fc_conf.pause_time);
3386 /* configure the timer value included in transmitted pause
3388 * the value for stat_tx_pause_quanta[8] is used for global
3391 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3392 pf->fc_conf.pause_time);
3394 fctrl_reg = I40E_READ_REG(hw,
3395 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3397 if (fc_conf->mac_ctrl_frame_fwd != 0)
3398 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3400 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3402 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3405 /* Configure pause time (2 TCs per register) */
3406 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3407 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3408 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3410 /* Configure flow control refresh threshold value */
3411 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3412 pf->fc_conf.pause_time / 2);
3414 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3416 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3417 *depending on configuration
3419 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3420 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3421 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3423 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3424 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3427 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3430 /* config the water marker both based on the packets and bytes */
3431 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3432 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3433 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3434 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3435 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3436 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3437 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3438 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3440 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3441 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3444 I40E_WRITE_FLUSH(hw);
3450 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3451 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3453 PMD_INIT_FUNC_TRACE();
3458 /* Add a MAC address, and update filters */
3460 i40e_macaddr_add(struct rte_eth_dev *dev,
3461 struct ether_addr *mac_addr,
3462 __rte_unused uint32_t index,
3465 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3466 struct i40e_mac_filter_info mac_filter;
3467 struct i40e_vsi *vsi;
3470 /* If VMDQ not enabled or configured, return */
3471 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3472 !pf->nb_cfg_vmdq_vsi)) {
3473 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3474 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3479 if (pool > pf->nb_cfg_vmdq_vsi) {
3480 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3481 pool, pf->nb_cfg_vmdq_vsi);
3485 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3486 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3487 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3489 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3494 vsi = pf->vmdq[pool - 1].vsi;
3496 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3497 if (ret != I40E_SUCCESS) {
3498 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3504 /* Remove a MAC address, and update filters */
3506 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3509 struct i40e_vsi *vsi;
3510 struct rte_eth_dev_data *data = dev->data;
3511 struct ether_addr *macaddr;
3516 macaddr = &(data->mac_addrs[index]);
3518 pool_sel = dev->data->mac_pool_sel[index];
3520 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3521 if (pool_sel & (1ULL << i)) {
3525 /* No VMDQ pool enabled or configured */
3526 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3527 (i > pf->nb_cfg_vmdq_vsi)) {
3529 "No VMDQ pool enabled/configured");
3532 vsi = pf->vmdq[i - 1].vsi;
3534 ret = i40e_vsi_delete_mac(vsi, macaddr);
3537 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3544 /* Set perfect match or hash match of MAC and VLAN for a VF */
3546 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3547 struct rte_eth_mac_filter *filter,
3551 struct i40e_mac_filter_info mac_filter;
3552 struct ether_addr old_mac;
3553 struct ether_addr *new_mac;
3554 struct i40e_pf_vf *vf = NULL;
3559 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3562 hw = I40E_PF_TO_HW(pf);
3564 if (filter == NULL) {
3565 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3569 new_mac = &filter->mac_addr;
3571 if (is_zero_ether_addr(new_mac)) {
3572 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3576 vf_id = filter->dst_id;
3578 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3579 PMD_DRV_LOG(ERR, "Invalid argument.");
3582 vf = &pf->vfs[vf_id];
3584 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3585 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3590 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3591 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3593 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3596 mac_filter.filter_type = filter->filter_type;
3597 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3598 if (ret != I40E_SUCCESS) {
3599 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3602 ether_addr_copy(new_mac, &pf->dev_addr);
3604 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3606 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3607 if (ret != I40E_SUCCESS) {
3608 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3612 /* Clear device address as it has been removed */
3613 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3614 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3620 /* MAC filter handle */
3622 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3625 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626 struct rte_eth_mac_filter *filter;
3627 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3628 int ret = I40E_NOT_SUPPORTED;
3630 filter = (struct rte_eth_mac_filter *)(arg);
3632 switch (filter_op) {
3633 case RTE_ETH_FILTER_NOP:
3636 case RTE_ETH_FILTER_ADD:
3637 i40e_pf_disable_irq0(hw);
3639 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3640 i40e_pf_enable_irq0(hw);
3642 case RTE_ETH_FILTER_DELETE:
3643 i40e_pf_disable_irq0(hw);
3645 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3646 i40e_pf_enable_irq0(hw);
3649 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3650 ret = I40E_ERR_PARAM;
3658 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3660 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3661 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3667 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3668 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3671 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3675 uint32_t *lut_dw = (uint32_t *)lut;
3676 uint16_t i, lut_size_dw = lut_size / 4;
3678 for (i = 0; i < lut_size_dw; i++)
3679 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3686 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3695 pf = I40E_VSI_TO_PF(vsi);
3696 hw = I40E_VSI_TO_HW(vsi);
3698 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3699 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3702 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3706 uint32_t *lut_dw = (uint32_t *)lut;
3707 uint16_t i, lut_size_dw = lut_size / 4;
3709 for (i = 0; i < lut_size_dw; i++)
3710 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3711 I40E_WRITE_FLUSH(hw);
3718 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3719 struct rte_eth_rss_reta_entry64 *reta_conf,
3722 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3723 uint16_t i, lut_size = pf->hash_lut_size;
3724 uint16_t idx, shift;
3728 if (reta_size != lut_size ||
3729 reta_size > ETH_RSS_RETA_SIZE_512) {
3731 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3732 reta_size, lut_size);
3736 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3738 PMD_DRV_LOG(ERR, "No memory can be allocated");
3741 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3744 for (i = 0; i < reta_size; i++) {
3745 idx = i / RTE_RETA_GROUP_SIZE;
3746 shift = i % RTE_RETA_GROUP_SIZE;
3747 if (reta_conf[idx].mask & (1ULL << shift))
3748 lut[i] = reta_conf[idx].reta[shift];
3750 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3759 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3760 struct rte_eth_rss_reta_entry64 *reta_conf,
3763 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764 uint16_t i, lut_size = pf->hash_lut_size;
3765 uint16_t idx, shift;
3769 if (reta_size != lut_size ||
3770 reta_size > ETH_RSS_RETA_SIZE_512) {
3772 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3773 reta_size, lut_size);
3777 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3779 PMD_DRV_LOG(ERR, "No memory can be allocated");
3783 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3786 for (i = 0; i < reta_size; i++) {
3787 idx = i / RTE_RETA_GROUP_SIZE;
3788 shift = i % RTE_RETA_GROUP_SIZE;
3789 if (reta_conf[idx].mask & (1ULL << shift))
3790 reta_conf[idx].reta[shift] = lut[i];
3800 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3801 * @hw: pointer to the HW structure
3802 * @mem: pointer to mem struct to fill out
3803 * @size: size of memory requested
3804 * @alignment: what to align the allocation to
3806 enum i40e_status_code
3807 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3808 struct i40e_dma_mem *mem,
3812 const struct rte_memzone *mz = NULL;
3813 char z_name[RTE_MEMZONE_NAMESIZE];
3816 return I40E_ERR_PARAM;
3818 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3819 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3820 alignment, RTE_PGSIZE_2M);
3822 return I40E_ERR_NO_MEMORY;
3826 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3827 mem->zone = (const void *)mz;
3829 "memzone %s allocated with physical address: %"PRIu64,
3832 return I40E_SUCCESS;
3836 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3837 * @hw: pointer to the HW structure
3838 * @mem: ptr to mem struct to free
3840 enum i40e_status_code
3841 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3842 struct i40e_dma_mem *mem)
3845 return I40E_ERR_PARAM;
3848 "memzone %s to be freed with physical address: %"PRIu64,
3849 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3850 rte_memzone_free((const struct rte_memzone *)mem->zone);
3855 return I40E_SUCCESS;
3859 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3860 * @hw: pointer to the HW structure
3861 * @mem: pointer to mem struct to fill out
3862 * @size: size of memory requested
3864 enum i40e_status_code
3865 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3866 struct i40e_virt_mem *mem,
3870 return I40E_ERR_PARAM;
3873 mem->va = rte_zmalloc("i40e", size, 0);
3876 return I40E_SUCCESS;
3878 return I40E_ERR_NO_MEMORY;
3882 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3883 * @hw: pointer to the HW structure
3884 * @mem: pointer to mem struct to free
3886 enum i40e_status_code
3887 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3888 struct i40e_virt_mem *mem)
3891 return I40E_ERR_PARAM;
3896 return I40E_SUCCESS;
3900 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3902 rte_spinlock_init(&sp->spinlock);
3906 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3908 rte_spinlock_lock(&sp->spinlock);
3912 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3914 rte_spinlock_unlock(&sp->spinlock);
3918 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3924 * Get the hardware capabilities, which will be parsed
3925 * and saved into struct i40e_hw.
3928 i40e_get_cap(struct i40e_hw *hw)
3930 struct i40e_aqc_list_capabilities_element_resp *buf;
3931 uint16_t len, size = 0;
3934 /* Calculate a huge enough buff for saving response data temporarily */
3935 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3936 I40E_MAX_CAP_ELE_NUM;
3937 buf = rte_zmalloc("i40e", len, 0);
3939 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3940 return I40E_ERR_NO_MEMORY;
3943 /* Get, parse the capabilities and save it to hw */
3944 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3945 i40e_aqc_opc_list_func_capabilities, NULL);
3946 if (ret != I40E_SUCCESS)
3947 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3949 /* Free the temporary buffer after being used */
3956 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3958 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3959 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3960 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3961 uint16_t qp_count = 0, vsi_count = 0;
3963 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3964 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3967 /* Add the parameter init for LFC */
3968 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3969 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3970 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3972 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3973 pf->max_num_vsi = hw->func_caps.num_vsis;
3974 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3975 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3976 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3978 /* FDir queue/VSI allocation */
3979 pf->fdir_qp_offset = 0;
3980 if (hw->func_caps.fd) {
3981 pf->flags |= I40E_FLAG_FDIR;
3982 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3984 pf->fdir_nb_qps = 0;
3986 qp_count += pf->fdir_nb_qps;
3989 /* LAN queue/VSI allocation */
3990 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3991 if (!hw->func_caps.rss) {
3994 pf->flags |= I40E_FLAG_RSS;
3995 if (hw->mac.type == I40E_MAC_X722)
3996 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3997 pf->lan_nb_qps = pf->lan_nb_qp_max;
3999 qp_count += pf->lan_nb_qps;
4002 /* VF queue/VSI allocation */
4003 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4004 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4005 pf->flags |= I40E_FLAG_SRIOV;
4006 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4007 pf->vf_num = pci_dev->max_vfs;
4009 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4010 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4015 qp_count += pf->vf_nb_qps * pf->vf_num;
4016 vsi_count += pf->vf_num;
4018 /* VMDq queue/VSI allocation */
4019 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4020 pf->vmdq_nb_qps = 0;
4021 pf->max_nb_vmdq_vsi = 0;
4022 if (hw->func_caps.vmdq) {
4023 if (qp_count < hw->func_caps.num_tx_qp &&
4024 vsi_count < hw->func_caps.num_vsis) {
4025 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4026 qp_count) / pf->vmdq_nb_qp_max;
4028 /* Limit the maximum number of VMDq vsi to the maximum
4029 * ethdev can support
4031 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4032 hw->func_caps.num_vsis - vsi_count);
4033 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4035 if (pf->max_nb_vmdq_vsi) {
4036 pf->flags |= I40E_FLAG_VMDQ;
4037 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4039 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4040 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4041 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4044 "No enough queues left for VMDq");
4047 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4050 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4051 vsi_count += pf->max_nb_vmdq_vsi;
4053 if (hw->func_caps.dcb)
4054 pf->flags |= I40E_FLAG_DCB;
4056 if (qp_count > hw->func_caps.num_tx_qp) {
4058 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4059 qp_count, hw->func_caps.num_tx_qp);
4062 if (vsi_count > hw->func_caps.num_vsis) {
4064 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4065 vsi_count, hw->func_caps.num_vsis);
4073 i40e_pf_get_switch_config(struct i40e_pf *pf)
4075 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4076 struct i40e_aqc_get_switch_config_resp *switch_config;
4077 struct i40e_aqc_switch_config_element_resp *element;
4078 uint16_t start_seid = 0, num_reported;
4081 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4082 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4083 if (!switch_config) {
4084 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4088 /* Get the switch configurations */
4089 ret = i40e_aq_get_switch_config(hw, switch_config,
4090 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4091 if (ret != I40E_SUCCESS) {
4092 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4095 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4096 if (num_reported != 1) { /* The number should be 1 */
4097 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4101 /* Parse the switch configuration elements */
4102 element = &(switch_config->element[0]);
4103 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4104 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4105 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4107 PMD_DRV_LOG(INFO, "Unknown element type");
4110 rte_free(switch_config);
4116 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4119 struct pool_entry *entry;
4121 if (pool == NULL || num == 0)
4124 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4125 if (entry == NULL) {
4126 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4130 /* queue heap initialize */
4131 pool->num_free = num;
4132 pool->num_alloc = 0;
4134 LIST_INIT(&pool->alloc_list);
4135 LIST_INIT(&pool->free_list);
4137 /* Initialize element */
4141 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4146 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4148 struct pool_entry *entry, *next_entry;
4153 for (entry = LIST_FIRST(&pool->alloc_list);
4154 entry && (next_entry = LIST_NEXT(entry, next), 1);
4155 entry = next_entry) {
4156 LIST_REMOVE(entry, next);
4160 for (entry = LIST_FIRST(&pool->free_list);
4161 entry && (next_entry = LIST_NEXT(entry, next), 1);
4162 entry = next_entry) {
4163 LIST_REMOVE(entry, next);
4168 pool->num_alloc = 0;
4170 LIST_INIT(&pool->alloc_list);
4171 LIST_INIT(&pool->free_list);
4175 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4178 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4179 uint32_t pool_offset;
4183 PMD_DRV_LOG(ERR, "Invalid parameter");
4187 pool_offset = base - pool->base;
4188 /* Lookup in alloc list */
4189 LIST_FOREACH(entry, &pool->alloc_list, next) {
4190 if (entry->base == pool_offset) {
4191 valid_entry = entry;
4192 LIST_REMOVE(entry, next);
4197 /* Not find, return */
4198 if (valid_entry == NULL) {
4199 PMD_DRV_LOG(ERR, "Failed to find entry");
4204 * Found it, move it to free list and try to merge.
4205 * In order to make merge easier, always sort it by qbase.
4206 * Find adjacent prev and last entries.
4209 LIST_FOREACH(entry, &pool->free_list, next) {
4210 if (entry->base > valid_entry->base) {
4218 /* Try to merge with next one*/
4220 /* Merge with next one */
4221 if (valid_entry->base + valid_entry->len == next->base) {
4222 next->base = valid_entry->base;
4223 next->len += valid_entry->len;
4224 rte_free(valid_entry);
4231 /* Merge with previous one */
4232 if (prev->base + prev->len == valid_entry->base) {
4233 prev->len += valid_entry->len;
4234 /* If it merge with next one, remove next node */
4236 LIST_REMOVE(valid_entry, next);
4237 rte_free(valid_entry);
4239 rte_free(valid_entry);
4245 /* Not find any entry to merge, insert */
4248 LIST_INSERT_AFTER(prev, valid_entry, next);
4249 else if (next != NULL)
4250 LIST_INSERT_BEFORE(next, valid_entry, next);
4251 else /* It's empty list, insert to head */
4252 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4255 pool->num_free += valid_entry->len;
4256 pool->num_alloc -= valid_entry->len;
4262 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4265 struct pool_entry *entry, *valid_entry;
4267 if (pool == NULL || num == 0) {
4268 PMD_DRV_LOG(ERR, "Invalid parameter");
4272 if (pool->num_free < num) {
4273 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4274 num, pool->num_free);
4279 /* Lookup in free list and find most fit one */
4280 LIST_FOREACH(entry, &pool->free_list, next) {
4281 if (entry->len >= num) {
4283 if (entry->len == num) {
4284 valid_entry = entry;
4287 if (valid_entry == NULL || valid_entry->len > entry->len)
4288 valid_entry = entry;
4292 /* Not find one to satisfy the request, return */
4293 if (valid_entry == NULL) {
4294 PMD_DRV_LOG(ERR, "No valid entry found");
4298 * The entry have equal queue number as requested,
4299 * remove it from alloc_list.
4301 if (valid_entry->len == num) {
4302 LIST_REMOVE(valid_entry, next);
4305 * The entry have more numbers than requested,
4306 * create a new entry for alloc_list and minus its
4307 * queue base and number in free_list.
4309 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4310 if (entry == NULL) {
4312 "Failed to allocate memory for resource pool");
4315 entry->base = valid_entry->base;
4317 valid_entry->base += num;
4318 valid_entry->len -= num;
4319 valid_entry = entry;
4322 /* Insert it into alloc list, not sorted */
4323 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4325 pool->num_free -= valid_entry->len;
4326 pool->num_alloc += valid_entry->len;
4328 return valid_entry->base + pool->base;
4332 * bitmap_is_subset - Check whether src2 is subset of src1
4335 bitmap_is_subset(uint8_t src1, uint8_t src2)
4337 return !((src1 ^ src2) & src2);
4340 static enum i40e_status_code
4341 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4343 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4345 /* If DCB is not supported, only default TC is supported */
4346 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4347 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4348 return I40E_NOT_SUPPORTED;
4351 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4353 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4354 hw->func_caps.enabled_tcmap, enabled_tcmap);
4355 return I40E_NOT_SUPPORTED;
4357 return I40E_SUCCESS;
4361 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4362 struct i40e_vsi_vlan_pvid_info *info)
4365 struct i40e_vsi_context ctxt;
4366 uint8_t vlan_flags = 0;
4369 if (vsi == NULL || info == NULL) {
4370 PMD_DRV_LOG(ERR, "invalid parameters");
4371 return I40E_ERR_PARAM;
4375 vsi->info.pvid = info->config.pvid;
4377 * If insert pvid is enabled, only tagged pkts are
4378 * allowed to be sent out.
4380 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4381 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4384 if (info->config.reject.tagged == 0)
4385 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4387 if (info->config.reject.untagged == 0)
4388 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4390 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4391 I40E_AQ_VSI_PVLAN_MODE_MASK);
4392 vsi->info.port_vlan_flags |= vlan_flags;
4393 vsi->info.valid_sections =
4394 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4395 memset(&ctxt, 0, sizeof(ctxt));
4396 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4397 ctxt.seid = vsi->seid;
4399 hw = I40E_VSI_TO_HW(vsi);
4400 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4401 if (ret != I40E_SUCCESS)
4402 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4408 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4410 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4412 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4414 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4415 if (ret != I40E_SUCCESS)
4419 PMD_DRV_LOG(ERR, "seid not valid");
4423 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4424 tc_bw_data.tc_valid_bits = enabled_tcmap;
4425 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4426 tc_bw_data.tc_bw_credits[i] =
4427 (enabled_tcmap & (1 << i)) ? 1 : 0;
4429 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4430 if (ret != I40E_SUCCESS) {
4431 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4435 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4436 sizeof(vsi->info.qs_handle));
4437 return I40E_SUCCESS;
4440 static enum i40e_status_code
4441 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4442 struct i40e_aqc_vsi_properties_data *info,
4443 uint8_t enabled_tcmap)
4445 enum i40e_status_code ret;
4446 int i, total_tc = 0;
4447 uint16_t qpnum_per_tc, bsf, qp_idx;
4449 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4450 if (ret != I40E_SUCCESS)
4453 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4454 if (enabled_tcmap & (1 << i))
4458 vsi->enabled_tc = enabled_tcmap;
4460 /* Number of queues per enabled TC */
4461 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4462 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4463 bsf = rte_bsf32(qpnum_per_tc);
4465 /* Adjust the queue number to actual queues that can be applied */
4466 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4467 vsi->nb_qps = qpnum_per_tc * total_tc;
4470 * Configure TC and queue mapping parameters, for enabled TC,
4471 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4472 * default queue will serve it.
4475 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4476 if (vsi->enabled_tc & (1 << i)) {
4477 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4478 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4479 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4480 qp_idx += qpnum_per_tc;
4482 info->tc_mapping[i] = 0;
4485 /* Associate queue number with VSI */
4486 if (vsi->type == I40E_VSI_SRIOV) {
4487 info->mapping_flags |=
4488 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4489 for (i = 0; i < vsi->nb_qps; i++)
4490 info->queue_mapping[i] =
4491 rte_cpu_to_le_16(vsi->base_queue + i);
4493 info->mapping_flags |=
4494 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4495 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4497 info->valid_sections |=
4498 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4500 return I40E_SUCCESS;
4504 i40e_veb_release(struct i40e_veb *veb)
4506 struct i40e_vsi *vsi;
4512 if (!TAILQ_EMPTY(&veb->head)) {
4513 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4516 /* associate_vsi field is NULL for floating VEB */
4517 if (veb->associate_vsi != NULL) {
4518 vsi = veb->associate_vsi;
4519 hw = I40E_VSI_TO_HW(vsi);
4521 vsi->uplink_seid = veb->uplink_seid;
4524 veb->associate_pf->main_vsi->floating_veb = NULL;
4525 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4528 i40e_aq_delete_element(hw, veb->seid, NULL);
4530 return I40E_SUCCESS;
4534 static struct i40e_veb *
4535 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4537 struct i40e_veb *veb;
4543 "veb setup failed, associated PF shouldn't null");
4546 hw = I40E_PF_TO_HW(pf);
4548 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4550 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4554 veb->associate_vsi = vsi;
4555 veb->associate_pf = pf;
4556 TAILQ_INIT(&veb->head);
4557 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4559 /* create floating veb if vsi is NULL */
4561 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4562 I40E_DEFAULT_TCMAP, false,
4563 &veb->seid, false, NULL);
4565 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4566 true, &veb->seid, false, NULL);
4569 if (ret != I40E_SUCCESS) {
4570 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4571 hw->aq.asq_last_status);
4574 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4576 /* get statistics index */
4577 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4578 &veb->stats_idx, NULL, NULL, NULL);
4579 if (ret != I40E_SUCCESS) {
4580 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4581 hw->aq.asq_last_status);
4584 /* Get VEB bandwidth, to be implemented */
4585 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4587 vsi->uplink_seid = veb->seid;
4596 i40e_vsi_release(struct i40e_vsi *vsi)
4600 struct i40e_vsi_list *vsi_list;
4603 struct i40e_mac_filter *f;
4604 uint16_t user_param;
4607 return I40E_SUCCESS;
4612 user_param = vsi->user_param;
4614 pf = I40E_VSI_TO_PF(vsi);
4615 hw = I40E_VSI_TO_HW(vsi);
4617 /* VSI has child to attach, release child first */
4619 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4620 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4623 i40e_veb_release(vsi->veb);
4626 if (vsi->floating_veb) {
4627 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4628 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4633 /* Remove all macvlan filters of the VSI */
4634 i40e_vsi_remove_all_macvlan_filter(vsi);
4635 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4638 if (vsi->type != I40E_VSI_MAIN &&
4639 ((vsi->type != I40E_VSI_SRIOV) ||
4640 !pf->floating_veb_list[user_param])) {
4641 /* Remove vsi from parent's sibling list */
4642 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4643 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4644 return I40E_ERR_PARAM;
4646 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4647 &vsi->sib_vsi_list, list);
4649 /* Remove all switch element of the VSI */
4650 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4651 if (ret != I40E_SUCCESS)
4652 PMD_DRV_LOG(ERR, "Failed to delete element");
4655 if ((vsi->type == I40E_VSI_SRIOV) &&
4656 pf->floating_veb_list[user_param]) {
4657 /* Remove vsi from parent's sibling list */
4658 if (vsi->parent_vsi == NULL ||
4659 vsi->parent_vsi->floating_veb == NULL) {
4660 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4661 return I40E_ERR_PARAM;
4663 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4664 &vsi->sib_vsi_list, list);
4666 /* Remove all switch element of the VSI */
4667 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4668 if (ret != I40E_SUCCESS)
4669 PMD_DRV_LOG(ERR, "Failed to delete element");
4672 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4674 if (vsi->type != I40E_VSI_SRIOV)
4675 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4678 return I40E_SUCCESS;
4682 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4684 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4685 struct i40e_aqc_remove_macvlan_element_data def_filter;
4686 struct i40e_mac_filter_info filter;
4689 if (vsi->type != I40E_VSI_MAIN)
4690 return I40E_ERR_CONFIG;
4691 memset(&def_filter, 0, sizeof(def_filter));
4692 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4694 def_filter.vlan_tag = 0;
4695 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4696 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4697 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4698 if (ret != I40E_SUCCESS) {
4699 struct i40e_mac_filter *f;
4700 struct ether_addr *mac;
4703 "Cannot remove the default macvlan filter");
4704 /* It needs to add the permanent mac into mac list */
4705 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4707 PMD_DRV_LOG(ERR, "failed to allocate memory");
4708 return I40E_ERR_NO_MEMORY;
4710 mac = &f->mac_info.mac_addr;
4711 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4713 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4714 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4719 rte_memcpy(&filter.mac_addr,
4720 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4721 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4722 return i40e_vsi_add_mac(vsi, &filter);
4726 * i40e_vsi_get_bw_config - Query VSI BW Information
4727 * @vsi: the VSI to be queried
4729 * Returns 0 on success, negative value on failure
4731 static enum i40e_status_code
4732 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4734 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4735 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4736 struct i40e_hw *hw = &vsi->adapter->hw;
4741 memset(&bw_config, 0, sizeof(bw_config));
4742 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4743 if (ret != I40E_SUCCESS) {
4744 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4745 hw->aq.asq_last_status);
4749 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4750 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4751 &ets_sla_config, NULL);
4752 if (ret != I40E_SUCCESS) {
4754 "VSI failed to get TC bandwdith configuration %u",
4755 hw->aq.asq_last_status);
4759 /* store and print out BW info */
4760 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4761 vsi->bw_info.bw_max = bw_config.max_bw;
4762 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4763 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4764 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4765 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4767 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4768 vsi->bw_info.bw_ets_share_credits[i] =
4769 ets_sla_config.share_credits[i];
4770 vsi->bw_info.bw_ets_credits[i] =
4771 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4772 /* 4 bits per TC, 4th bit is reserved */
4773 vsi->bw_info.bw_ets_max[i] =
4774 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4775 RTE_LEN2MASK(3, uint8_t));
4776 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4777 vsi->bw_info.bw_ets_share_credits[i]);
4778 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4779 vsi->bw_info.bw_ets_credits[i]);
4780 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4781 vsi->bw_info.bw_ets_max[i]);
4784 return I40E_SUCCESS;
4787 /* i40e_enable_pf_lb
4788 * @pf: pointer to the pf structure
4790 * allow loopback on pf
4793 i40e_enable_pf_lb(struct i40e_pf *pf)
4795 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4796 struct i40e_vsi_context ctxt;
4799 /* Use the FW API if FW >= v5.0 */
4800 if (hw->aq.fw_maj_ver < 5) {
4801 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4805 memset(&ctxt, 0, sizeof(ctxt));
4806 ctxt.seid = pf->main_vsi_seid;
4807 ctxt.pf_num = hw->pf_id;
4808 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4810 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4811 ret, hw->aq.asq_last_status);
4814 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4815 ctxt.info.valid_sections =
4816 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4817 ctxt.info.switch_id |=
4818 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4820 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4822 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4823 hw->aq.asq_last_status);
4828 i40e_vsi_setup(struct i40e_pf *pf,
4829 enum i40e_vsi_type type,
4830 struct i40e_vsi *uplink_vsi,
4831 uint16_t user_param)
4833 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834 struct i40e_vsi *vsi;
4835 struct i40e_mac_filter_info filter;
4837 struct i40e_vsi_context ctxt;
4838 struct ether_addr broadcast =
4839 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4841 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4842 uplink_vsi == NULL) {
4844 "VSI setup failed, VSI link shouldn't be NULL");
4848 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4850 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4855 * 1.type is not MAIN and uplink vsi is not NULL
4856 * If uplink vsi didn't setup VEB, create one first under veb field
4857 * 2.type is SRIOV and the uplink is NULL
4858 * If floating VEB is NULL, create one veb under floating veb field
4861 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4862 uplink_vsi->veb == NULL) {
4863 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4865 if (uplink_vsi->veb == NULL) {
4866 PMD_DRV_LOG(ERR, "VEB setup failed");
4869 /* set ALLOWLOOPBACk on pf, when veb is created */
4870 i40e_enable_pf_lb(pf);
4873 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4874 pf->main_vsi->floating_veb == NULL) {
4875 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4877 if (pf->main_vsi->floating_veb == NULL) {
4878 PMD_DRV_LOG(ERR, "VEB setup failed");
4883 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4885 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4888 TAILQ_INIT(&vsi->mac_list);
4890 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4891 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4892 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4893 vsi->user_param = user_param;
4894 vsi->vlan_anti_spoof_on = 0;
4895 vsi->vlan_filter_on = 0;
4896 /* Allocate queues */
4897 switch (vsi->type) {
4898 case I40E_VSI_MAIN :
4899 vsi->nb_qps = pf->lan_nb_qps;
4901 case I40E_VSI_SRIOV :
4902 vsi->nb_qps = pf->vf_nb_qps;
4904 case I40E_VSI_VMDQ2:
4905 vsi->nb_qps = pf->vmdq_nb_qps;
4908 vsi->nb_qps = pf->fdir_nb_qps;
4914 * The filter status descriptor is reported in rx queue 0,
4915 * while the tx queue for fdir filter programming has no
4916 * such constraints, can be non-zero queues.
4917 * To simplify it, choose FDIR vsi use queue 0 pair.
4918 * To make sure it will use queue 0 pair, queue allocation
4919 * need be done before this function is called
4921 if (type != I40E_VSI_FDIR) {
4922 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4924 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4928 vsi->base_queue = ret;
4930 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4932 /* VF has MSIX interrupt in VF range, don't allocate here */
4933 if (type == I40E_VSI_MAIN) {
4934 ret = i40e_res_pool_alloc(&pf->msix_pool,
4935 RTE_MIN(vsi->nb_qps,
4936 RTE_MAX_RXTX_INTR_VEC_ID));
4938 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4940 goto fail_queue_alloc;
4942 vsi->msix_intr = ret;
4943 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4944 } else if (type != I40E_VSI_SRIOV) {
4945 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4947 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4948 goto fail_queue_alloc;
4950 vsi->msix_intr = ret;
4958 if (type == I40E_VSI_MAIN) {
4959 /* For main VSI, no need to add since it's default one */
4960 vsi->uplink_seid = pf->mac_seid;
4961 vsi->seid = pf->main_vsi_seid;
4962 /* Bind queues with specific MSIX interrupt */
4964 * Needs 2 interrupt at least, one for misc cause which will
4965 * enabled from OS side, Another for queues binding the
4966 * interrupt from device side only.
4969 /* Get default VSI parameters from hardware */
4970 memset(&ctxt, 0, sizeof(ctxt));
4971 ctxt.seid = vsi->seid;
4972 ctxt.pf_num = hw->pf_id;
4973 ctxt.uplink_seid = vsi->uplink_seid;
4975 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4976 if (ret != I40E_SUCCESS) {
4977 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4978 goto fail_msix_alloc;
4980 rte_memcpy(&vsi->info, &ctxt.info,
4981 sizeof(struct i40e_aqc_vsi_properties_data));
4982 vsi->vsi_id = ctxt.vsi_number;
4983 vsi->info.valid_sections = 0;
4985 /* Configure tc, enabled TC0 only */
4986 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4988 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4989 goto fail_msix_alloc;
4992 /* TC, queue mapping */
4993 memset(&ctxt, 0, sizeof(ctxt));
4994 vsi->info.valid_sections |=
4995 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4996 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4997 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4998 rte_memcpy(&ctxt.info, &vsi->info,
4999 sizeof(struct i40e_aqc_vsi_properties_data));
5000 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5001 I40E_DEFAULT_TCMAP);
5002 if (ret != I40E_SUCCESS) {
5004 "Failed to configure TC queue mapping");
5005 goto fail_msix_alloc;
5007 ctxt.seid = vsi->seid;
5008 ctxt.pf_num = hw->pf_id;
5009 ctxt.uplink_seid = vsi->uplink_seid;
5012 /* Update VSI parameters */
5013 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5014 if (ret != I40E_SUCCESS) {
5015 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5016 goto fail_msix_alloc;
5019 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5020 sizeof(vsi->info.tc_mapping));
5021 rte_memcpy(&vsi->info.queue_mapping,
5022 &ctxt.info.queue_mapping,
5023 sizeof(vsi->info.queue_mapping));
5024 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5025 vsi->info.valid_sections = 0;
5027 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5031 * Updating default filter settings are necessary to prevent
5032 * reception of tagged packets.
5033 * Some old firmware configurations load a default macvlan
5034 * filter which accepts both tagged and untagged packets.
5035 * The updating is to use a normal filter instead if needed.
5036 * For NVM 4.2.2 or after, the updating is not needed anymore.
5037 * The firmware with correct configurations load the default
5038 * macvlan filter which is expected and cannot be removed.
5040 i40e_update_default_filter_setting(vsi);
5041 i40e_config_qinq(hw, vsi);
5042 } else if (type == I40E_VSI_SRIOV) {
5043 memset(&ctxt, 0, sizeof(ctxt));
5045 * For other VSI, the uplink_seid equals to uplink VSI's
5046 * uplink_seid since they share same VEB
5048 if (uplink_vsi == NULL)
5049 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5051 vsi->uplink_seid = uplink_vsi->uplink_seid;
5052 ctxt.pf_num = hw->pf_id;
5053 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5054 ctxt.uplink_seid = vsi->uplink_seid;
5055 ctxt.connection_type = 0x1;
5056 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5058 /* Use the VEB configuration if FW >= v5.0 */
5059 if (hw->aq.fw_maj_ver >= 5) {
5060 /* Configure switch ID */
5061 ctxt.info.valid_sections |=
5062 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5063 ctxt.info.switch_id =
5064 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5067 /* Configure port/vlan */
5068 ctxt.info.valid_sections |=
5069 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5070 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5071 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5072 hw->func_caps.enabled_tcmap);
5073 if (ret != I40E_SUCCESS) {
5075 "Failed to configure TC queue mapping");
5076 goto fail_msix_alloc;
5079 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5080 ctxt.info.valid_sections |=
5081 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5083 * Since VSI is not created yet, only configure parameter,
5084 * will add vsi below.
5087 i40e_config_qinq(hw, vsi);
5088 } else if (type == I40E_VSI_VMDQ2) {
5089 memset(&ctxt, 0, sizeof(ctxt));
5091 * For other VSI, the uplink_seid equals to uplink VSI's
5092 * uplink_seid since they share same VEB
5094 vsi->uplink_seid = uplink_vsi->uplink_seid;
5095 ctxt.pf_num = hw->pf_id;
5097 ctxt.uplink_seid = vsi->uplink_seid;
5098 ctxt.connection_type = 0x1;
5099 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5101 ctxt.info.valid_sections |=
5102 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5103 /* user_param carries flag to enable loop back */
5105 ctxt.info.switch_id =
5106 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5107 ctxt.info.switch_id |=
5108 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5111 /* Configure port/vlan */
5112 ctxt.info.valid_sections |=
5113 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5114 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5115 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5116 I40E_DEFAULT_TCMAP);
5117 if (ret != I40E_SUCCESS) {
5119 "Failed to configure TC queue mapping");
5120 goto fail_msix_alloc;
5122 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5123 ctxt.info.valid_sections |=
5124 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5125 } else if (type == I40E_VSI_FDIR) {
5126 memset(&ctxt, 0, sizeof(ctxt));
5127 vsi->uplink_seid = uplink_vsi->uplink_seid;
5128 ctxt.pf_num = hw->pf_id;
5130 ctxt.uplink_seid = vsi->uplink_seid;
5131 ctxt.connection_type = 0x1; /* regular data port */
5132 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5133 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5134 I40E_DEFAULT_TCMAP);
5135 if (ret != I40E_SUCCESS) {
5137 "Failed to configure TC queue mapping.");
5138 goto fail_msix_alloc;
5140 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5141 ctxt.info.valid_sections |=
5142 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5144 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5145 goto fail_msix_alloc;
5148 if (vsi->type != I40E_VSI_MAIN) {
5149 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5150 if (ret != I40E_SUCCESS) {
5151 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5152 hw->aq.asq_last_status);
5153 goto fail_msix_alloc;
5155 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5156 vsi->info.valid_sections = 0;
5157 vsi->seid = ctxt.seid;
5158 vsi->vsi_id = ctxt.vsi_number;
5159 vsi->sib_vsi_list.vsi = vsi;
5160 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5161 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5162 &vsi->sib_vsi_list, list);
5164 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5165 &vsi->sib_vsi_list, list);
5169 /* MAC/VLAN configuration */
5170 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5171 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5173 ret = i40e_vsi_add_mac(vsi, &filter);
5174 if (ret != I40E_SUCCESS) {
5175 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5176 goto fail_msix_alloc;
5179 /* Get VSI BW information */
5180 i40e_vsi_get_bw_config(vsi);
5183 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5185 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5191 /* Configure vlan filter on or off */
5193 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5196 struct i40e_mac_filter *f;
5198 struct i40e_mac_filter_info *mac_filter;
5199 enum rte_mac_filter_type desired_filter;
5200 int ret = I40E_SUCCESS;
5203 /* Filter to match MAC and VLAN */
5204 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5206 /* Filter to match only MAC */
5207 desired_filter = RTE_MAC_PERFECT_MATCH;
5212 mac_filter = rte_zmalloc("mac_filter_info_data",
5213 num * sizeof(*mac_filter), 0);
5214 if (mac_filter == NULL) {
5215 PMD_DRV_LOG(ERR, "failed to allocate memory");
5216 return I40E_ERR_NO_MEMORY;
5221 /* Remove all existing mac */
5222 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5223 mac_filter[i] = f->mac_info;
5224 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5226 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5227 on ? "enable" : "disable");
5233 /* Override with new filter */
5234 for (i = 0; i < num; i++) {
5235 mac_filter[i].filter_type = desired_filter;
5236 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5238 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5239 on ? "enable" : "disable");
5245 rte_free(mac_filter);
5249 /* Configure vlan stripping on or off */
5251 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5253 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5254 struct i40e_vsi_context ctxt;
5256 int ret = I40E_SUCCESS;
5258 /* Check if it has been already on or off */
5259 if (vsi->info.valid_sections &
5260 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5262 if ((vsi->info.port_vlan_flags &
5263 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5264 return 0; /* already on */
5266 if ((vsi->info.port_vlan_flags &
5267 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5268 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5269 return 0; /* already off */
5274 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5276 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5277 vsi->info.valid_sections =
5278 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5279 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5280 vsi->info.port_vlan_flags |= vlan_flags;
5281 ctxt.seid = vsi->seid;
5282 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5283 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5285 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5286 on ? "enable" : "disable");
5292 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5294 struct rte_eth_dev_data *data = dev->data;
5298 /* Apply vlan offload setting */
5299 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5300 i40e_vlan_offload_set(dev, mask);
5302 /* Apply double-vlan setting, not implemented yet */
5304 /* Apply pvid setting */
5305 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5306 data->dev_conf.txmode.hw_vlan_insert_pvid);
5308 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5314 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5316 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5318 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5322 i40e_update_flow_control(struct i40e_hw *hw)
5324 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5325 struct i40e_link_status link_status;
5326 uint32_t rxfc = 0, txfc = 0, reg;
5330 memset(&link_status, 0, sizeof(link_status));
5331 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5332 if (ret != I40E_SUCCESS) {
5333 PMD_DRV_LOG(ERR, "Failed to get link status information");
5334 goto write_reg; /* Disable flow control */
5337 an_info = hw->phy.link_info.an_info;
5338 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5339 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5340 ret = I40E_ERR_NOT_READY;
5341 goto write_reg; /* Disable flow control */
5344 * If link auto negotiation is enabled, flow control needs to
5345 * be configured according to it
5347 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5348 case I40E_LINK_PAUSE_RXTX:
5351 hw->fc.current_mode = I40E_FC_FULL;
5353 case I40E_AQ_LINK_PAUSE_RX:
5355 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5357 case I40E_AQ_LINK_PAUSE_TX:
5359 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5362 hw->fc.current_mode = I40E_FC_NONE;
5367 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5368 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5369 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5370 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5371 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5372 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5379 i40e_pf_setup(struct i40e_pf *pf)
5381 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5382 struct i40e_filter_control_settings settings;
5383 struct i40e_vsi *vsi;
5386 /* Clear all stats counters */
5387 pf->offset_loaded = FALSE;
5388 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5389 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5390 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5391 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5393 ret = i40e_pf_get_switch_config(pf);
5394 if (ret != I40E_SUCCESS) {
5395 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5398 if (pf->flags & I40E_FLAG_FDIR) {
5399 /* make queue allocated first, let FDIR use queue pair 0*/
5400 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5401 if (ret != I40E_FDIR_QUEUE_ID) {
5403 "queue allocation fails for FDIR: ret =%d",
5405 pf->flags &= ~I40E_FLAG_FDIR;
5408 /* main VSI setup */
5409 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5411 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5412 return I40E_ERR_NOT_READY;
5416 /* Configure filter control */
5417 memset(&settings, 0, sizeof(settings));
5418 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5419 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5420 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5421 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5423 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5424 hw->func_caps.rss_table_size);
5425 return I40E_ERR_PARAM;
5427 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5428 hw->func_caps.rss_table_size);
5429 pf->hash_lut_size = hw->func_caps.rss_table_size;
5431 /* Enable ethtype and macvlan filters */
5432 settings.enable_ethtype = TRUE;
5433 settings.enable_macvlan = TRUE;
5434 ret = i40e_set_filter_control(hw, &settings);
5436 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5439 /* Update flow control according to the auto negotiation */
5440 i40e_update_flow_control(hw);
5442 return I40E_SUCCESS;
5446 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5452 * Set or clear TX Queue Disable flags,
5453 * which is required by hardware.
5455 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5456 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5458 /* Wait until the request is finished */
5459 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5460 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5461 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5462 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5463 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5469 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5470 return I40E_SUCCESS; /* already on, skip next steps */
5472 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5473 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5475 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5476 return I40E_SUCCESS; /* already off, skip next steps */
5477 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5479 /* Write the register */
5480 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5481 /* Check the result */
5482 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5483 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5484 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5486 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5487 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5490 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5491 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5495 /* Check if it is timeout */
5496 if (j >= I40E_CHK_Q_ENA_COUNT) {
5497 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5498 (on ? "enable" : "disable"), q_idx);
5499 return I40E_ERR_TIMEOUT;
5502 return I40E_SUCCESS;
5505 /* Swith on or off the tx queues */
5507 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5509 struct rte_eth_dev_data *dev_data = pf->dev_data;
5510 struct i40e_tx_queue *txq;
5511 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5515 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5516 txq = dev_data->tx_queues[i];
5517 /* Don't operate the queue if not configured or
5518 * if starting only per queue */
5519 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5522 ret = i40e_dev_tx_queue_start(dev, i);
5524 ret = i40e_dev_tx_queue_stop(dev, i);
5525 if ( ret != I40E_SUCCESS)
5529 return I40E_SUCCESS;
5533 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5538 /* Wait until the request is finished */
5539 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5540 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5541 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5542 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5543 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5548 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5549 return I40E_SUCCESS; /* Already on, skip next steps */
5550 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5552 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5553 return I40E_SUCCESS; /* Already off, skip next steps */
5554 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5557 /* Write the register */
5558 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5559 /* Check the result */
5560 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5561 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5562 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5564 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5565 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5568 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5569 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5574 /* Check if it is timeout */
5575 if (j >= I40E_CHK_Q_ENA_COUNT) {
5576 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5577 (on ? "enable" : "disable"), q_idx);
5578 return I40E_ERR_TIMEOUT;
5581 return I40E_SUCCESS;
5583 /* Switch on or off the rx queues */
5585 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5587 struct rte_eth_dev_data *dev_data = pf->dev_data;
5588 struct i40e_rx_queue *rxq;
5589 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5593 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5594 rxq = dev_data->rx_queues[i];
5595 /* Don't operate the queue if not configured or
5596 * if starting only per queue */
5597 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5600 ret = i40e_dev_rx_queue_start(dev, i);
5602 ret = i40e_dev_rx_queue_stop(dev, i);
5603 if (ret != I40E_SUCCESS)
5607 return I40E_SUCCESS;
5610 /* Switch on or off all the rx/tx queues */
5612 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5617 /* enable rx queues before enabling tx queues */
5618 ret = i40e_dev_switch_rx_queues(pf, on);
5620 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5623 ret = i40e_dev_switch_tx_queues(pf, on);
5625 /* Stop tx queues before stopping rx queues */
5626 ret = i40e_dev_switch_tx_queues(pf, on);
5628 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5631 ret = i40e_dev_switch_rx_queues(pf, on);
5637 /* Initialize VSI for TX */
5639 i40e_dev_tx_init(struct i40e_pf *pf)
5641 struct rte_eth_dev_data *data = pf->dev_data;
5643 uint32_t ret = I40E_SUCCESS;
5644 struct i40e_tx_queue *txq;
5646 for (i = 0; i < data->nb_tx_queues; i++) {
5647 txq = data->tx_queues[i];
5648 if (!txq || !txq->q_set)
5650 ret = i40e_tx_queue_init(txq);
5651 if (ret != I40E_SUCCESS)
5654 if (ret == I40E_SUCCESS)
5655 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5661 /* Initialize VSI for RX */
5663 i40e_dev_rx_init(struct i40e_pf *pf)
5665 struct rte_eth_dev_data *data = pf->dev_data;
5666 int ret = I40E_SUCCESS;
5668 struct i40e_rx_queue *rxq;
5670 i40e_pf_config_mq_rx(pf);
5671 for (i = 0; i < data->nb_rx_queues; i++) {
5672 rxq = data->rx_queues[i];
5673 if (!rxq || !rxq->q_set)
5676 ret = i40e_rx_queue_init(rxq);
5677 if (ret != I40E_SUCCESS) {
5679 "Failed to do RX queue initialization");
5683 if (ret == I40E_SUCCESS)
5684 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5691 i40e_dev_rxtx_init(struct i40e_pf *pf)
5695 err = i40e_dev_tx_init(pf);
5697 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5700 err = i40e_dev_rx_init(pf);
5702 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5710 i40e_vmdq_setup(struct rte_eth_dev *dev)
5712 struct rte_eth_conf *conf = &dev->data->dev_conf;
5713 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5714 int i, err, conf_vsis, j, loop;
5715 struct i40e_vsi *vsi;
5716 struct i40e_vmdq_info *vmdq_info;
5717 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5718 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5721 * Disable interrupt to avoid message from VF. Furthermore, it will
5722 * avoid race condition in VSI creation/destroy.
5724 i40e_pf_disable_irq0(hw);
5726 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5727 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5731 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5732 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5733 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5734 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5735 pf->max_nb_vmdq_vsi);
5739 if (pf->vmdq != NULL) {
5740 PMD_INIT_LOG(INFO, "VMDQ already configured");
5744 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5745 sizeof(*vmdq_info) * conf_vsis, 0);
5747 if (pf->vmdq == NULL) {
5748 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5752 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5754 /* Create VMDQ VSI */
5755 for (i = 0; i < conf_vsis; i++) {
5756 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5757 vmdq_conf->enable_loop_back);
5759 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5763 vmdq_info = &pf->vmdq[i];
5765 vmdq_info->vsi = vsi;
5767 pf->nb_cfg_vmdq_vsi = conf_vsis;
5769 /* Configure Vlan */
5770 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5771 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5772 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5773 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5774 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5775 vmdq_conf->pool_map[i].vlan_id, j);
5777 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5778 vmdq_conf->pool_map[i].vlan_id);
5780 PMD_INIT_LOG(ERR, "Failed to add vlan");
5788 i40e_pf_enable_irq0(hw);
5793 for (i = 0; i < conf_vsis; i++)
5794 if (pf->vmdq[i].vsi == NULL)
5797 i40e_vsi_release(pf->vmdq[i].vsi);
5801 i40e_pf_enable_irq0(hw);
5806 i40e_stat_update_32(struct i40e_hw *hw,
5814 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5818 if (new_data >= *offset)
5819 *stat = (uint64_t)(new_data - *offset);
5821 *stat = (uint64_t)((new_data +
5822 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5826 i40e_stat_update_48(struct i40e_hw *hw,
5835 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5836 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5837 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5842 if (new_data >= *offset)
5843 *stat = new_data - *offset;
5845 *stat = (uint64_t)((new_data +
5846 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5848 *stat &= I40E_48_BIT_MASK;
5853 i40e_pf_disable_irq0(struct i40e_hw *hw)
5855 /* Disable all interrupt types */
5856 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5857 I40E_WRITE_FLUSH(hw);
5862 i40e_pf_enable_irq0(struct i40e_hw *hw)
5864 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5865 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5866 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5867 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5868 I40E_WRITE_FLUSH(hw);
5872 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5874 /* read pending request and disable first */
5875 i40e_pf_disable_irq0(hw);
5876 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5877 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5878 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5881 /* Link no queues with irq0 */
5882 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5883 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5887 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5889 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5893 uint32_t index, offset, val;
5898 * Try to find which VF trigger a reset, use absolute VF id to access
5899 * since the reg is global register.
5901 for (i = 0; i < pf->vf_num; i++) {
5902 abs_vf_id = hw->func_caps.vf_base_id + i;
5903 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5904 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5905 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5906 /* VFR event occurred */
5907 if (val & (0x1 << offset)) {
5910 /* Clear the event first */
5911 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5913 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5915 * Only notify a VF reset event occurred,
5916 * don't trigger another SW reset
5918 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5919 if (ret != I40E_SUCCESS)
5920 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5926 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5928 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5931 for (i = 0; i < pf->vf_num; i++)
5932 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5936 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939 struct i40e_arq_event_info info;
5940 uint16_t pending, opcode;
5943 info.buf_len = I40E_AQ_BUF_SZ;
5944 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5945 if (!info.msg_buf) {
5946 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5952 ret = i40e_clean_arq_element(hw, &info, &pending);
5954 if (ret != I40E_SUCCESS) {
5956 "Failed to read msg from AdminQ, aq_err: %u",
5957 hw->aq.asq_last_status);
5960 opcode = rte_le_to_cpu_16(info.desc.opcode);
5963 case i40e_aqc_opc_send_msg_to_pf:
5964 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5965 i40e_pf_host_handle_vf_msg(dev,
5966 rte_le_to_cpu_16(info.desc.retval),
5967 rte_le_to_cpu_32(info.desc.cookie_high),
5968 rte_le_to_cpu_32(info.desc.cookie_low),
5972 case i40e_aqc_opc_get_link_status:
5973 ret = i40e_dev_link_update(dev, 0);
5975 _rte_eth_dev_callback_process(dev,
5976 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5979 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5984 rte_free(info.msg_buf);
5988 * Interrupt handler triggered by NIC for handling
5989 * specific interrupt.
5992 * Pointer to interrupt handle.
5994 * The address of parameter (struct rte_eth_dev *) regsitered before.
6000 i40e_dev_interrupt_handler(void *param)
6002 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6003 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6006 /* Disable interrupt */
6007 i40e_pf_disable_irq0(hw);
6009 /* read out interrupt causes */
6010 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6012 /* No interrupt event indicated */
6013 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6014 PMD_DRV_LOG(INFO, "No interrupt event");
6017 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6018 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6019 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6020 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6021 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6022 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6023 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6024 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6025 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6026 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6027 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6028 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6029 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6030 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6032 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6033 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6034 i40e_dev_handle_vfr_event(dev);
6036 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6037 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6038 i40e_dev_handle_aq_msg(dev);
6042 /* Enable interrupt */
6043 i40e_pf_enable_irq0(hw);
6044 rte_intr_enable(dev->intr_handle);
6048 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6049 struct i40e_macvlan_filter *filter,
6052 int ele_num, ele_buff_size;
6053 int num, actual_num, i;
6055 int ret = I40E_SUCCESS;
6056 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6057 struct i40e_aqc_add_macvlan_element_data *req_list;
6059 if (filter == NULL || total == 0)
6060 return I40E_ERR_PARAM;
6061 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6062 ele_buff_size = hw->aq.asq_buf_size;
6064 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6065 if (req_list == NULL) {
6066 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6067 return I40E_ERR_NO_MEMORY;
6072 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6073 memset(req_list, 0, ele_buff_size);
6075 for (i = 0; i < actual_num; i++) {
6076 rte_memcpy(req_list[i].mac_addr,
6077 &filter[num + i].macaddr, ETH_ADDR_LEN);
6078 req_list[i].vlan_tag =
6079 rte_cpu_to_le_16(filter[num + i].vlan_id);
6081 switch (filter[num + i].filter_type) {
6082 case RTE_MAC_PERFECT_MATCH:
6083 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6084 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6086 case RTE_MACVLAN_PERFECT_MATCH:
6087 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6089 case RTE_MAC_HASH_MATCH:
6090 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6091 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6093 case RTE_MACVLAN_HASH_MATCH:
6094 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6097 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6098 ret = I40E_ERR_PARAM;
6102 req_list[i].queue_number = 0;
6104 req_list[i].flags = rte_cpu_to_le_16(flags);
6107 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6109 if (ret != I40E_SUCCESS) {
6110 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6114 } while (num < total);
6122 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6123 struct i40e_macvlan_filter *filter,
6126 int ele_num, ele_buff_size;
6127 int num, actual_num, i;
6129 int ret = I40E_SUCCESS;
6130 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6131 struct i40e_aqc_remove_macvlan_element_data *req_list;
6133 if (filter == NULL || total == 0)
6134 return I40E_ERR_PARAM;
6136 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6137 ele_buff_size = hw->aq.asq_buf_size;
6139 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6140 if (req_list == NULL) {
6141 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6142 return I40E_ERR_NO_MEMORY;
6147 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6148 memset(req_list, 0, ele_buff_size);
6150 for (i = 0; i < actual_num; i++) {
6151 rte_memcpy(req_list[i].mac_addr,
6152 &filter[num + i].macaddr, ETH_ADDR_LEN);
6153 req_list[i].vlan_tag =
6154 rte_cpu_to_le_16(filter[num + i].vlan_id);
6156 switch (filter[num + i].filter_type) {
6157 case RTE_MAC_PERFECT_MATCH:
6158 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6159 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6161 case RTE_MACVLAN_PERFECT_MATCH:
6162 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6164 case RTE_MAC_HASH_MATCH:
6165 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6166 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6168 case RTE_MACVLAN_HASH_MATCH:
6169 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6172 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6173 ret = I40E_ERR_PARAM;
6176 req_list[i].flags = rte_cpu_to_le_16(flags);
6179 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6181 if (ret != I40E_SUCCESS) {
6182 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6186 } while (num < total);
6193 /* Find out specific MAC filter */
6194 static struct i40e_mac_filter *
6195 i40e_find_mac_filter(struct i40e_vsi *vsi,
6196 struct ether_addr *macaddr)
6198 struct i40e_mac_filter *f;
6200 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6201 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6209 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6212 uint32_t vid_idx, vid_bit;
6214 if (vlan_id > ETH_VLAN_ID_MAX)
6217 vid_idx = I40E_VFTA_IDX(vlan_id);
6218 vid_bit = I40E_VFTA_BIT(vlan_id);
6220 if (vsi->vfta[vid_idx] & vid_bit)
6227 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6228 uint16_t vlan_id, bool on)
6230 uint32_t vid_idx, vid_bit;
6232 vid_idx = I40E_VFTA_IDX(vlan_id);
6233 vid_bit = I40E_VFTA_BIT(vlan_id);
6236 vsi->vfta[vid_idx] |= vid_bit;
6238 vsi->vfta[vid_idx] &= ~vid_bit;
6242 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6243 uint16_t vlan_id, bool on)
6245 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6246 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6249 if (vlan_id > ETH_VLAN_ID_MAX)
6252 i40e_store_vlan_filter(vsi, vlan_id, on);
6254 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6257 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6260 ret = i40e_aq_add_vlan(hw, vsi->seid,
6261 &vlan_data, 1, NULL);
6262 if (ret != I40E_SUCCESS)
6263 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6265 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6266 &vlan_data, 1, NULL);
6267 if (ret != I40E_SUCCESS)
6269 "Failed to remove vlan filter");
6274 * Find all vlan options for specific mac addr,
6275 * return with actual vlan found.
6278 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6279 struct i40e_macvlan_filter *mv_f,
6280 int num, struct ether_addr *addr)
6286 * Not to use i40e_find_vlan_filter to decrease the loop time,
6287 * although the code looks complex.
6289 if (num < vsi->vlan_num)
6290 return I40E_ERR_PARAM;
6293 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6295 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6296 if (vsi->vfta[j] & (1 << k)) {
6299 "vlan number doesn't match");
6300 return I40E_ERR_PARAM;
6302 rte_memcpy(&mv_f[i].macaddr,
6303 addr, ETH_ADDR_LEN);
6305 j * I40E_UINT32_BIT_SIZE + k;
6311 return I40E_SUCCESS;
6315 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6316 struct i40e_macvlan_filter *mv_f,
6321 struct i40e_mac_filter *f;
6323 if (num < vsi->mac_num)
6324 return I40E_ERR_PARAM;
6326 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6328 PMD_DRV_LOG(ERR, "buffer number not match");
6329 return I40E_ERR_PARAM;
6331 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6333 mv_f[i].vlan_id = vlan;
6334 mv_f[i].filter_type = f->mac_info.filter_type;
6338 return I40E_SUCCESS;
6342 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6345 struct i40e_mac_filter *f;
6346 struct i40e_macvlan_filter *mv_f;
6347 int ret = I40E_SUCCESS;
6349 if (vsi == NULL || vsi->mac_num == 0)
6350 return I40E_ERR_PARAM;
6352 /* Case that no vlan is set */
6353 if (vsi->vlan_num == 0)
6356 num = vsi->mac_num * vsi->vlan_num;
6358 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6360 PMD_DRV_LOG(ERR, "failed to allocate memory");
6361 return I40E_ERR_NO_MEMORY;
6365 if (vsi->vlan_num == 0) {
6366 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6367 rte_memcpy(&mv_f[i].macaddr,
6368 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6369 mv_f[i].filter_type = f->mac_info.filter_type;
6370 mv_f[i].vlan_id = 0;
6374 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6375 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6376 vsi->vlan_num, &f->mac_info.mac_addr);
6377 if (ret != I40E_SUCCESS)
6379 for (j = i; j < i + vsi->vlan_num; j++)
6380 mv_f[j].filter_type = f->mac_info.filter_type;
6385 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6393 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6395 struct i40e_macvlan_filter *mv_f;
6397 int ret = I40E_SUCCESS;
6399 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6400 return I40E_ERR_PARAM;
6402 /* If it's already set, just return */
6403 if (i40e_find_vlan_filter(vsi,vlan))
6404 return I40E_SUCCESS;
6406 mac_num = vsi->mac_num;
6409 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6410 return I40E_ERR_PARAM;
6413 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6416 PMD_DRV_LOG(ERR, "failed to allocate memory");
6417 return I40E_ERR_NO_MEMORY;
6420 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6422 if (ret != I40E_SUCCESS)
6425 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6427 if (ret != I40E_SUCCESS)
6430 i40e_set_vlan_filter(vsi, vlan, 1);
6440 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6442 struct i40e_macvlan_filter *mv_f;
6444 int ret = I40E_SUCCESS;
6447 * Vlan 0 is the generic filter for untagged packets
6448 * and can't be removed.
6450 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6451 return I40E_ERR_PARAM;
6453 /* If can't find it, just return */
6454 if (!i40e_find_vlan_filter(vsi, vlan))
6455 return I40E_ERR_PARAM;
6457 mac_num = vsi->mac_num;
6460 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6461 return I40E_ERR_PARAM;
6464 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6467 PMD_DRV_LOG(ERR, "failed to allocate memory");
6468 return I40E_ERR_NO_MEMORY;
6471 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6473 if (ret != I40E_SUCCESS)
6476 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6478 if (ret != I40E_SUCCESS)
6481 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6482 if (vsi->vlan_num == 1) {
6483 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6484 if (ret != I40E_SUCCESS)
6487 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6488 if (ret != I40E_SUCCESS)
6492 i40e_set_vlan_filter(vsi, vlan, 0);
6502 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6504 struct i40e_mac_filter *f;
6505 struct i40e_macvlan_filter *mv_f;
6506 int i, vlan_num = 0;
6507 int ret = I40E_SUCCESS;
6509 /* If it's add and we've config it, return */
6510 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6512 return I40E_SUCCESS;
6513 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6514 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6517 * If vlan_num is 0, that's the first time to add mac,
6518 * set mask for vlan_id 0.
6520 if (vsi->vlan_num == 0) {
6521 i40e_set_vlan_filter(vsi, 0, 1);
6524 vlan_num = vsi->vlan_num;
6525 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6526 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6529 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6531 PMD_DRV_LOG(ERR, "failed to allocate memory");
6532 return I40E_ERR_NO_MEMORY;
6535 for (i = 0; i < vlan_num; i++) {
6536 mv_f[i].filter_type = mac_filter->filter_type;
6537 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6541 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6542 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6543 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6544 &mac_filter->mac_addr);
6545 if (ret != I40E_SUCCESS)
6549 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6550 if (ret != I40E_SUCCESS)
6553 /* Add the mac addr into mac list */
6554 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6556 PMD_DRV_LOG(ERR, "failed to allocate memory");
6557 ret = I40E_ERR_NO_MEMORY;
6560 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6562 f->mac_info.filter_type = mac_filter->filter_type;
6563 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6574 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6576 struct i40e_mac_filter *f;
6577 struct i40e_macvlan_filter *mv_f;
6579 enum rte_mac_filter_type filter_type;
6580 int ret = I40E_SUCCESS;
6582 /* Can't find it, return an error */
6583 f = i40e_find_mac_filter(vsi, addr);
6585 return I40E_ERR_PARAM;
6587 vlan_num = vsi->vlan_num;
6588 filter_type = f->mac_info.filter_type;
6589 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6590 filter_type == RTE_MACVLAN_HASH_MATCH) {
6591 if (vlan_num == 0) {
6592 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6593 return I40E_ERR_PARAM;
6595 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6596 filter_type == RTE_MAC_HASH_MATCH)
6599 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6601 PMD_DRV_LOG(ERR, "failed to allocate memory");
6602 return I40E_ERR_NO_MEMORY;
6605 for (i = 0; i < vlan_num; i++) {
6606 mv_f[i].filter_type = filter_type;
6607 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6610 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6611 filter_type == RTE_MACVLAN_HASH_MATCH) {
6612 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6613 if (ret != I40E_SUCCESS)
6617 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6618 if (ret != I40E_SUCCESS)
6621 /* Remove the mac addr into mac list */
6622 TAILQ_REMOVE(&vsi->mac_list, f, next);
6632 /* Configure hash enable flags for RSS */
6634 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6642 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6643 if (flags & (1ULL << i))
6644 hena |= adapter->pctypes_tbl[i];
6650 /* Parse the hash enable flags */
6652 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6654 uint64_t rss_hf = 0;
6660 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6661 if (flags & adapter->pctypes_tbl[i])
6662 rss_hf |= (1ULL << i);
6669 i40e_pf_disable_rss(struct i40e_pf *pf)
6671 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6673 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6674 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6675 I40E_WRITE_FLUSH(hw);
6679 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6681 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6682 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6685 if (!key || key_len == 0) {
6686 PMD_DRV_LOG(DEBUG, "No key to be configured");
6688 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6690 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6694 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6695 struct i40e_aqc_get_set_rss_key_data *key_dw =
6696 (struct i40e_aqc_get_set_rss_key_data *)key;
6698 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6700 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6702 uint32_t *hash_key = (uint32_t *)key;
6705 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6706 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6707 I40E_WRITE_FLUSH(hw);
6714 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6716 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6717 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6720 if (!key || !key_len)
6723 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6724 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6725 (struct i40e_aqc_get_set_rss_key_data *)key);
6727 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6731 uint32_t *key_dw = (uint32_t *)key;
6734 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6735 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6737 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6743 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6745 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6749 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6750 rss_conf->rss_key_len);
6754 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6755 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6756 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6757 I40E_WRITE_FLUSH(hw);
6763 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6764 struct rte_eth_rss_conf *rss_conf)
6766 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6768 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6771 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6772 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6774 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6775 if (rss_hf != 0) /* Enable RSS */
6777 return 0; /* Nothing to do */
6780 if (rss_hf == 0) /* Disable RSS */
6783 return i40e_hw_rss_hash_set(pf, rss_conf);
6787 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6788 struct rte_eth_rss_conf *rss_conf)
6790 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6791 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6795 &rss_conf->rss_key_len);
6797 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6798 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6799 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6805 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6807 switch (filter_type) {
6808 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6809 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6811 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6812 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6814 case RTE_TUNNEL_FILTER_IMAC_TENID:
6815 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6817 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6818 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6820 case ETH_TUNNEL_FILTER_IMAC:
6821 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6823 case ETH_TUNNEL_FILTER_OIP:
6824 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6826 case ETH_TUNNEL_FILTER_IIP:
6827 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6830 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6837 /* Convert tunnel filter structure */
6839 i40e_tunnel_filter_convert(
6840 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6841 struct i40e_tunnel_filter *tunnel_filter)
6843 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6844 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6845 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6846 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6847 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6848 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6849 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6850 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6851 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6853 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6854 tunnel_filter->input.flags = cld_filter->element.flags;
6855 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6856 tunnel_filter->queue = cld_filter->element.queue_number;
6857 rte_memcpy(tunnel_filter->input.general_fields,
6858 cld_filter->general_fields,
6859 sizeof(cld_filter->general_fields));
6864 /* Check if there exists the tunnel filter */
6865 struct i40e_tunnel_filter *
6866 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6867 const struct i40e_tunnel_filter_input *input)
6871 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6875 return tunnel_rule->hash_map[ret];
6878 /* Add a tunnel filter into the SW list */
6880 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6881 struct i40e_tunnel_filter *tunnel_filter)
6883 struct i40e_tunnel_rule *rule = &pf->tunnel;
6886 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6889 "Failed to insert tunnel filter to hash table %d!",
6893 rule->hash_map[ret] = tunnel_filter;
6895 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6900 /* Delete a tunnel filter from the SW list */
6902 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6903 struct i40e_tunnel_filter_input *input)
6905 struct i40e_tunnel_rule *rule = &pf->tunnel;
6906 struct i40e_tunnel_filter *tunnel_filter;
6909 ret = rte_hash_del_key(rule->hash_table, input);
6912 "Failed to delete tunnel filter to hash table %d!",
6916 tunnel_filter = rule->hash_map[ret];
6917 rule->hash_map[ret] = NULL;
6919 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6920 rte_free(tunnel_filter);
6926 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6927 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6932 uint8_t i, tun_type = 0;
6933 /* internal varialbe to convert ipv6 byte order */
6934 uint32_t convert_ipv6[4];
6936 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6937 struct i40e_vsi *vsi = pf->main_vsi;
6938 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6939 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6940 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6941 struct i40e_tunnel_filter *tunnel, *node;
6942 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6944 cld_filter = rte_zmalloc("tunnel_filter",
6945 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6948 if (NULL == cld_filter) {
6949 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6952 pfilter = cld_filter;
6954 ether_addr_copy(&tunnel_filter->outer_mac,
6955 (struct ether_addr *)&pfilter->element.outer_mac);
6956 ether_addr_copy(&tunnel_filter->inner_mac,
6957 (struct ether_addr *)&pfilter->element.inner_mac);
6959 pfilter->element.inner_vlan =
6960 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6961 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6962 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6963 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6964 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6965 &rte_cpu_to_le_32(ipv4_addr),
6966 sizeof(pfilter->element.ipaddr.v4.data));
6968 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6969 for (i = 0; i < 4; i++) {
6971 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6973 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6975 sizeof(pfilter->element.ipaddr.v6.data));
6978 /* check tunneled type */
6979 switch (tunnel_filter->tunnel_type) {
6980 case RTE_TUNNEL_TYPE_VXLAN:
6981 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6983 case RTE_TUNNEL_TYPE_NVGRE:
6984 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6986 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6987 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6990 /* Other tunnel types is not supported. */
6991 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6992 rte_free(cld_filter);
6996 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6997 &pfilter->element.flags);
6999 rte_free(cld_filter);
7003 pfilter->element.flags |= rte_cpu_to_le_16(
7004 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7005 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7006 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7007 pfilter->element.queue_number =
7008 rte_cpu_to_le_16(tunnel_filter->queue_id);
7010 /* Check if there is the filter in SW list */
7011 memset(&check_filter, 0, sizeof(check_filter));
7012 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7013 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7015 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7019 if (!add && !node) {
7020 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7025 ret = i40e_aq_add_cloud_filters(hw,
7026 vsi->seid, &cld_filter->element, 1);
7028 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7031 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7032 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7033 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7035 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7036 &cld_filter->element, 1);
7038 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7041 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7044 rte_free(cld_filter);
7048 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7049 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7050 #define I40E_TR_GENEVE_KEY_MASK 0x8
7051 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7052 #define I40E_TR_GRE_KEY_MASK 0x400
7053 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7054 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7057 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7059 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7060 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7061 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7062 enum i40e_status_code status = I40E_SUCCESS;
7064 memset(&filter_replace, 0,
7065 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7066 memset(&filter_replace_buf, 0,
7067 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7069 /* create L1 filter */
7070 filter_replace.old_filter_type =
7071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7072 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7073 filter_replace.tr_bit = 0;
7075 /* Prepare the buffer, 3 entries */
7076 filter_replace_buf.data[0] =
7077 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7078 filter_replace_buf.data[0] |=
7079 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7080 filter_replace_buf.data[2] = 0xFF;
7081 filter_replace_buf.data[3] = 0xFF;
7082 filter_replace_buf.data[4] =
7083 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7084 filter_replace_buf.data[4] |=
7085 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7086 filter_replace_buf.data[7] = 0xF0;
7087 filter_replace_buf.data[8]
7088 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7089 filter_replace_buf.data[8] |=
7090 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7091 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7092 I40E_TR_GENEVE_KEY_MASK |
7093 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7094 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7095 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7096 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7098 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7099 &filter_replace_buf);
7104 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7106 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7107 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7108 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7109 enum i40e_status_code status = I40E_SUCCESS;
7112 memset(&filter_replace, 0,
7113 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7114 memset(&filter_replace_buf, 0,
7115 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7116 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7117 I40E_AQC_MIRROR_CLOUD_FILTER;
7118 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7119 filter_replace.new_filter_type =
7120 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7121 /* Prepare the buffer, 2 entries */
7122 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7123 filter_replace_buf.data[0] |=
7124 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7125 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7126 filter_replace_buf.data[4] |=
7127 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7128 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7129 &filter_replace_buf);
7134 memset(&filter_replace, 0,
7135 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7136 memset(&filter_replace_buf, 0,
7137 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7139 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7140 I40E_AQC_MIRROR_CLOUD_FILTER;
7141 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7142 filter_replace.new_filter_type =
7143 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7144 /* Prepare the buffer, 2 entries */
7145 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7146 filter_replace_buf.data[0] |=
7147 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7148 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7149 filter_replace_buf.data[4] |=
7150 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7152 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7153 &filter_replace_buf);
7158 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7159 struct i40e_tunnel_filter_conf *tunnel_filter,
7164 uint8_t i, tun_type = 0;
7165 /* internal variable to convert ipv6 byte order */
7166 uint32_t convert_ipv6[4];
7168 struct i40e_pf_vf *vf = NULL;
7169 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7170 struct i40e_vsi *vsi;
7171 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7172 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7173 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7174 struct i40e_tunnel_filter *tunnel, *node;
7175 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7177 bool big_buffer = 0;
7179 cld_filter = rte_zmalloc("tunnel_filter",
7180 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7183 if (cld_filter == NULL) {
7184 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7187 pfilter = cld_filter;
7189 ether_addr_copy(&tunnel_filter->outer_mac,
7190 (struct ether_addr *)&pfilter->element.outer_mac);
7191 ether_addr_copy(&tunnel_filter->inner_mac,
7192 (struct ether_addr *)&pfilter->element.inner_mac);
7194 pfilter->element.inner_vlan =
7195 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7196 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7197 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7198 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7199 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7200 &rte_cpu_to_le_32(ipv4_addr),
7201 sizeof(pfilter->element.ipaddr.v4.data));
7203 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7204 for (i = 0; i < 4; i++) {
7206 rte_cpu_to_le_32(rte_be_to_cpu_32(
7207 tunnel_filter->ip_addr.ipv6_addr[i]));
7209 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7211 sizeof(pfilter->element.ipaddr.v6.data));
7214 /* check tunneled type */
7215 switch (tunnel_filter->tunnel_type) {
7216 case I40E_TUNNEL_TYPE_VXLAN:
7217 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7219 case I40E_TUNNEL_TYPE_NVGRE:
7220 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7222 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7223 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7225 case I40E_TUNNEL_TYPE_MPLSoUDP:
7226 if (!pf->mpls_replace_flag) {
7227 i40e_replace_mpls_l1_filter(pf);
7228 i40e_replace_mpls_cloud_filter(pf);
7229 pf->mpls_replace_flag = 1;
7231 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7232 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7234 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7235 (teid_le & 0xF) << 12;
7236 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7239 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7241 case I40E_TUNNEL_TYPE_MPLSoGRE:
7242 if (!pf->mpls_replace_flag) {
7243 i40e_replace_mpls_l1_filter(pf);
7244 i40e_replace_mpls_cloud_filter(pf);
7245 pf->mpls_replace_flag = 1;
7247 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7248 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7250 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7251 (teid_le & 0xF) << 12;
7252 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7255 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7257 case I40E_TUNNEL_TYPE_QINQ:
7258 if (!pf->qinq_replace_flag) {
7259 ret = i40e_cloud_filter_qinq_create(pf);
7262 "QinQ tunnel filter already created.");
7263 pf->qinq_replace_flag = 1;
7265 /* Add in the General fields the values of
7266 * the Outer and Inner VLAN
7267 * Big Buffer should be set, see changes in
7268 * i40e_aq_add_cloud_filters
7270 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7271 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7275 /* Other tunnel types is not supported. */
7276 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7277 rte_free(cld_filter);
7281 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7282 pfilter->element.flags =
7283 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7284 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7285 pfilter->element.flags =
7286 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7287 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7288 pfilter->element.flags |=
7289 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7291 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7292 &pfilter->element.flags);
7294 rte_free(cld_filter);
7299 pfilter->element.flags |= rte_cpu_to_le_16(
7300 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7301 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7302 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7303 pfilter->element.queue_number =
7304 rte_cpu_to_le_16(tunnel_filter->queue_id);
7306 if (!tunnel_filter->is_to_vf)
7309 if (tunnel_filter->vf_id >= pf->vf_num) {
7310 PMD_DRV_LOG(ERR, "Invalid argument.");
7313 vf = &pf->vfs[tunnel_filter->vf_id];
7317 /* Check if there is the filter in SW list */
7318 memset(&check_filter, 0, sizeof(check_filter));
7319 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7320 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7321 check_filter.vf_id = tunnel_filter->vf_id;
7322 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7324 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7328 if (!add && !node) {
7329 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7335 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7336 vsi->seid, cld_filter, 1);
7338 ret = i40e_aq_add_cloud_filters(hw,
7339 vsi->seid, &cld_filter->element, 1);
7341 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7344 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7345 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7346 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7349 ret = i40e_aq_remove_cloud_filters_big_buffer(
7350 hw, vsi->seid, cld_filter, 1);
7352 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7353 &cld_filter->element, 1);
7355 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7358 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7361 rte_free(cld_filter);
7366 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7370 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7371 if (pf->vxlan_ports[i] == port)
7379 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7383 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7385 idx = i40e_get_vxlan_port_idx(pf, port);
7387 /* Check if port already exists */
7389 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7393 /* Now check if there is space to add the new port */
7394 idx = i40e_get_vxlan_port_idx(pf, 0);
7397 "Maximum number of UDP ports reached, not adding port %d",
7402 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7405 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7409 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7412 /* New port: add it and mark its index in the bitmap */
7413 pf->vxlan_ports[idx] = port;
7414 pf->vxlan_bitmap |= (1 << idx);
7416 if (!(pf->flags & I40E_FLAG_VXLAN))
7417 pf->flags |= I40E_FLAG_VXLAN;
7423 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7426 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7428 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7429 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7433 idx = i40e_get_vxlan_port_idx(pf, port);
7436 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7440 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7441 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7445 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7448 pf->vxlan_ports[idx] = 0;
7449 pf->vxlan_bitmap &= ~(1 << idx);
7451 if (!pf->vxlan_bitmap)
7452 pf->flags &= ~I40E_FLAG_VXLAN;
7457 /* Add UDP tunneling port */
7459 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7460 struct rte_eth_udp_tunnel *udp_tunnel)
7463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7465 if (udp_tunnel == NULL)
7468 switch (udp_tunnel->prot_type) {
7469 case RTE_TUNNEL_TYPE_VXLAN:
7470 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7473 case RTE_TUNNEL_TYPE_GENEVE:
7474 case RTE_TUNNEL_TYPE_TEREDO:
7475 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7480 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7488 /* Remove UDP tunneling port */
7490 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7491 struct rte_eth_udp_tunnel *udp_tunnel)
7494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7496 if (udp_tunnel == NULL)
7499 switch (udp_tunnel->prot_type) {
7500 case RTE_TUNNEL_TYPE_VXLAN:
7501 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7503 case RTE_TUNNEL_TYPE_GENEVE:
7504 case RTE_TUNNEL_TYPE_TEREDO:
7505 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7509 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7517 /* Calculate the maximum number of contiguous PF queues that are configured */
7519 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7521 struct rte_eth_dev_data *data = pf->dev_data;
7523 struct i40e_rx_queue *rxq;
7526 for (i = 0; i < pf->lan_nb_qps; i++) {
7527 rxq = data->rx_queues[i];
7528 if (rxq && rxq->q_set)
7539 i40e_pf_config_rss(struct i40e_pf *pf)
7541 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7542 struct rte_eth_rss_conf rss_conf;
7543 uint32_t i, lut = 0;
7547 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7548 * It's necessary to calculate the actual PF queues that are configured.
7550 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7551 num = i40e_pf_calc_configured_queues_num(pf);
7553 num = pf->dev_data->nb_rx_queues;
7555 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7556 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7560 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7564 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7567 lut = (lut << 8) | (j & ((0x1 <<
7568 hw->func_caps.rss_table_entry_width) - 1));
7570 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7573 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7574 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7575 i40e_pf_disable_rss(pf);
7578 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7579 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7580 /* Random default keys */
7581 static uint32_t rss_key_default[] = {0x6b793944,
7582 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7583 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7584 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7586 rss_conf.rss_key = (uint8_t *)rss_key_default;
7587 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7591 return i40e_hw_rss_hash_set(pf, &rss_conf);
7595 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7596 struct rte_eth_tunnel_filter_conf *filter)
7598 if (pf == NULL || filter == NULL) {
7599 PMD_DRV_LOG(ERR, "Invalid parameter");
7603 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7604 PMD_DRV_LOG(ERR, "Invalid queue ID");
7608 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7609 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7613 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7614 (is_zero_ether_addr(&filter->outer_mac))) {
7615 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7619 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7620 (is_zero_ether_addr(&filter->inner_mac))) {
7621 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7628 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7629 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7631 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7636 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7637 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7640 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7641 } else if (len == 4) {
7642 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7644 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7649 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7656 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7657 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7663 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7670 switch (cfg->cfg_type) {
7671 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7672 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7675 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7683 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7684 enum rte_filter_op filter_op,
7687 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7688 int ret = I40E_ERR_PARAM;
7690 switch (filter_op) {
7691 case RTE_ETH_FILTER_SET:
7692 ret = i40e_dev_global_config_set(hw,
7693 (struct rte_eth_global_cfg *)arg);
7696 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7704 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7705 enum rte_filter_op filter_op,
7708 struct rte_eth_tunnel_filter_conf *filter;
7709 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7710 int ret = I40E_SUCCESS;
7712 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7714 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7715 return I40E_ERR_PARAM;
7717 switch (filter_op) {
7718 case RTE_ETH_FILTER_NOP:
7719 if (!(pf->flags & I40E_FLAG_VXLAN))
7720 ret = I40E_NOT_SUPPORTED;
7722 case RTE_ETH_FILTER_ADD:
7723 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7725 case RTE_ETH_FILTER_DELETE:
7726 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7729 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7730 ret = I40E_ERR_PARAM;
7738 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7741 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7744 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7745 ret = i40e_pf_config_rss(pf);
7747 i40e_pf_disable_rss(pf);
7752 /* Get the symmetric hash enable configurations per port */
7754 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7756 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7758 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7761 /* Set the symmetric hash enable configurations per port */
7763 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7765 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7768 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7770 "Symmetric hash has already been enabled");
7773 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7775 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7777 "Symmetric hash has already been disabled");
7780 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7782 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7783 I40E_WRITE_FLUSH(hw);
7787 * Get global configurations of hash function type and symmetric hash enable
7788 * per flow type (pctype). Note that global configuration means it affects all
7789 * the ports on the same NIC.
7792 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7793 struct rte_eth_hash_global_conf *g_cfg)
7795 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7799 memset(g_cfg, 0, sizeof(*g_cfg));
7800 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7801 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7802 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7804 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7805 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7806 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7809 * We work only with lowest 32 bits which is not correct, but to work
7810 * properly the valid_bit_mask size should be increased up to 64 bits
7811 * and this will brake ABI. This modification will be done in next
7814 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7816 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7817 if (!adapter->pctypes_tbl[i])
7819 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7820 j < I40E_FILTER_PCTYPE_MAX; j++) {
7821 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7822 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7823 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7824 g_cfg->sym_hash_enable_mask[0] |=
7835 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7836 const struct rte_eth_hash_global_conf *g_cfg)
7839 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
7841 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7842 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7843 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7844 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7850 * As i40e supports less than 32 flow types, only first 32 bits need to
7853 mask0 = g_cfg->valid_bit_mask[0];
7854 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7856 /* Check if any unsupported flow type configured */
7857 if ((mask0 | i40e_mask) ^ i40e_mask)
7860 if (g_cfg->valid_bit_mask[i])
7868 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7874 * Set global configurations of hash function type and symmetric hash enable
7875 * per flow type (pctype). Note any modifying global configuration will affect
7876 * all the ports on the same NIC.
7879 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7880 struct rte_eth_hash_global_conf *g_cfg)
7882 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7887 * We work only with lowest 32 bits which is not correct, but to work
7888 * properly the valid_bit_mask size should be increased up to 64 bits
7889 * and this will brake ABI. This modification will be done in next
7892 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
7893 (uint32_t)adapter->flow_types_mask;
7895 /* Check the input parameters */
7896 ret = i40e_hash_global_config_check(adapter, g_cfg);
7900 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
7901 if (mask0 & (1UL << i)) {
7902 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7903 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7905 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7906 j < I40E_FILTER_PCTYPE_MAX; j++) {
7907 if (adapter->pctypes_tbl[i] & (1ULL << j))
7908 i40e_write_rx_ctl(hw,
7915 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7916 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7918 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7920 "Hash function already set to Toeplitz");
7923 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7924 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7926 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7928 "Hash function already set to Simple XOR");
7931 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7933 /* Use the default, and keep it as it is */
7936 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7939 I40E_WRITE_FLUSH(hw);
7945 * Valid input sets for hash and flow director filters per PCTYPE
7948 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7949 enum rte_filter_type filter)
7953 static const uint64_t valid_hash_inset_table[] = {
7954 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7955 I40E_INSET_DMAC | I40E_INSET_SMAC |
7956 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7957 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7958 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7959 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7960 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7961 I40E_INSET_FLEX_PAYLOAD,
7962 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7963 I40E_INSET_DMAC | I40E_INSET_SMAC |
7964 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7965 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7966 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7967 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7968 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7969 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7970 I40E_INSET_FLEX_PAYLOAD,
7971 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7972 I40E_INSET_DMAC | I40E_INSET_SMAC |
7973 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7974 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7975 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7976 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7977 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7978 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7979 I40E_INSET_FLEX_PAYLOAD,
7980 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7981 I40E_INSET_DMAC | I40E_INSET_SMAC |
7982 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7983 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7984 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7985 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7986 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7987 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7988 I40E_INSET_FLEX_PAYLOAD,
7989 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7990 I40E_INSET_DMAC | I40E_INSET_SMAC |
7991 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7992 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7993 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7994 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7995 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7996 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7997 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7998 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7999 I40E_INSET_DMAC | I40E_INSET_SMAC |
8000 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8001 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8002 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8003 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8004 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8005 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8006 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8007 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8008 I40E_INSET_DMAC | I40E_INSET_SMAC |
8009 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8010 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8011 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8012 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8013 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8014 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8015 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8016 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8017 I40E_INSET_DMAC | I40E_INSET_SMAC |
8018 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8019 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8020 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8021 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8022 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8023 I40E_INSET_FLEX_PAYLOAD,
8024 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8025 I40E_INSET_DMAC | I40E_INSET_SMAC |
8026 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8027 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8028 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8029 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8030 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8031 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8032 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8033 I40E_INSET_DMAC | I40E_INSET_SMAC |
8034 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8035 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8036 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8037 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8038 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8039 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8040 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8041 I40E_INSET_DMAC | I40E_INSET_SMAC |
8042 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8043 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8044 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8045 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8046 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8047 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8048 I40E_INSET_FLEX_PAYLOAD,
8049 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8050 I40E_INSET_DMAC | I40E_INSET_SMAC |
8051 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8052 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8053 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8054 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8055 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8056 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8057 I40E_INSET_FLEX_PAYLOAD,
8058 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8059 I40E_INSET_DMAC | I40E_INSET_SMAC |
8060 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8061 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8062 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8063 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8064 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8065 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8066 I40E_INSET_FLEX_PAYLOAD,
8067 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8068 I40E_INSET_DMAC | I40E_INSET_SMAC |
8069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8070 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8071 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8072 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8073 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8074 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8075 I40E_INSET_FLEX_PAYLOAD,
8076 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8077 I40E_INSET_DMAC | I40E_INSET_SMAC |
8078 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8079 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8080 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8081 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8082 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8083 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8084 I40E_INSET_FLEX_PAYLOAD,
8085 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8086 I40E_INSET_DMAC | I40E_INSET_SMAC |
8087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8088 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8089 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8090 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8091 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8092 I40E_INSET_FLEX_PAYLOAD,
8093 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8094 I40E_INSET_DMAC | I40E_INSET_SMAC |
8095 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8096 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8097 I40E_INSET_FLEX_PAYLOAD,
8101 * Flow director supports only fields defined in
8102 * union rte_eth_fdir_flow.
8104 static const uint64_t valid_fdir_inset_table[] = {
8105 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8106 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8107 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8108 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8109 I40E_INSET_IPV4_TTL,
8110 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8112 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8113 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8114 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8115 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8116 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8117 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8118 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8119 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8120 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8121 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8122 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8123 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8124 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8125 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8126 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8127 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8128 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8129 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8130 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8131 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8132 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8133 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8134 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8135 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8136 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8137 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8138 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8139 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8141 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8142 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8143 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8144 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8145 I40E_INSET_IPV4_TTL,
8146 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8147 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8149 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8150 I40E_INSET_IPV6_HOP_LIMIT,
8151 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8152 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8154 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8155 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8156 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8157 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8158 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8159 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8160 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8162 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8164 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8165 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8166 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8167 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8168 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8169 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8170 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8172 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8174 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8175 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8176 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8177 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8178 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8179 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8180 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8182 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8183 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8184 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8185 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8186 I40E_INSET_IPV6_HOP_LIMIT,
8187 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8188 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189 I40E_INSET_LAST_ETHER_TYPE,
8192 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8194 if (filter == RTE_ETH_FILTER_HASH)
8195 valid = valid_hash_inset_table[pctype];
8197 valid = valid_fdir_inset_table[pctype];
8203 * Validate if the input set is allowed for a specific PCTYPE
8206 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8207 enum rte_filter_type filter, uint64_t inset)
8211 valid = i40e_get_valid_input_set(pctype, filter);
8212 if (inset & (~valid))
8218 /* default input set fields combination per pctype */
8220 i40e_get_default_input_set(uint16_t pctype)
8222 static const uint64_t default_inset_table[] = {
8223 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8224 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8225 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8226 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8227 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8228 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8229 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8230 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8231 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8232 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8233 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8234 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8235 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8236 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8237 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8238 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8239 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8240 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8241 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8242 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8244 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8245 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8246 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8247 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8248 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8249 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8250 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8251 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8252 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8253 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8254 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8255 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8256 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8257 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8258 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8259 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8260 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8261 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8262 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8263 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8264 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8265 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8267 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8268 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8269 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8270 I40E_INSET_LAST_ETHER_TYPE,
8273 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8276 return default_inset_table[pctype];
8280 * Parse the input set from index to logical bit masks
8283 i40e_parse_input_set(uint64_t *inset,
8284 enum i40e_filter_pctype pctype,
8285 enum rte_eth_input_set_field *field,
8291 static const struct {
8292 enum rte_eth_input_set_field field;
8294 } inset_convert_table[] = {
8295 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8296 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8297 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8298 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8299 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8300 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8301 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8302 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8303 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8304 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8305 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8306 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8307 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8308 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8309 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8310 I40E_INSET_IPV6_NEXT_HDR},
8311 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8312 I40E_INSET_IPV6_HOP_LIMIT},
8313 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8314 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8315 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8316 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8317 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8318 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8319 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8320 I40E_INSET_SCTP_VT},
8321 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8322 I40E_INSET_TUNNEL_DMAC},
8323 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8324 I40E_INSET_VLAN_TUNNEL},
8325 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8326 I40E_INSET_TUNNEL_ID},
8327 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8328 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8329 I40E_INSET_FLEX_PAYLOAD_W1},
8330 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8331 I40E_INSET_FLEX_PAYLOAD_W2},
8332 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8333 I40E_INSET_FLEX_PAYLOAD_W3},
8334 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8335 I40E_INSET_FLEX_PAYLOAD_W4},
8336 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8337 I40E_INSET_FLEX_PAYLOAD_W5},
8338 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8339 I40E_INSET_FLEX_PAYLOAD_W6},
8340 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8341 I40E_INSET_FLEX_PAYLOAD_W7},
8342 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8343 I40E_INSET_FLEX_PAYLOAD_W8},
8346 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8349 /* Only one item allowed for default or all */
8351 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8352 *inset = i40e_get_default_input_set(pctype);
8354 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8355 *inset = I40E_INSET_NONE;
8360 for (i = 0, *inset = 0; i < size; i++) {
8361 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8362 if (field[i] == inset_convert_table[j].field) {
8363 *inset |= inset_convert_table[j].inset;
8368 /* It contains unsupported input set, return immediately */
8369 if (j == RTE_DIM(inset_convert_table))
8377 * Translate the input set from bit masks to register aware bit masks
8381 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8391 static const struct inset_map inset_map_common[] = {
8392 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8393 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8394 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8395 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8396 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8397 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8398 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8399 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8400 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8401 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8402 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8403 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8404 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8405 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8406 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8407 {I40E_INSET_TUNNEL_DMAC,
8408 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8409 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8410 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8411 {I40E_INSET_TUNNEL_SRC_PORT,
8412 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8413 {I40E_INSET_TUNNEL_DST_PORT,
8414 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8415 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8416 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8417 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8418 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8419 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8420 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8421 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8422 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8423 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8426 /* some different registers map in x722*/
8427 static const struct inset_map inset_map_diff_x722[] = {
8428 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8429 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8430 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8431 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8434 static const struct inset_map inset_map_diff_not_x722[] = {
8435 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8436 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8437 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8438 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8444 /* Translate input set to register aware inset */
8445 if (type == I40E_MAC_X722) {
8446 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8447 if (input & inset_map_diff_x722[i].inset)
8448 val |= inset_map_diff_x722[i].inset_reg;
8451 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8452 if (input & inset_map_diff_not_x722[i].inset)
8453 val |= inset_map_diff_not_x722[i].inset_reg;
8457 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8458 if (input & inset_map_common[i].inset)
8459 val |= inset_map_common[i].inset_reg;
8466 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8469 uint64_t inset_need_mask = inset;
8471 static const struct {
8474 } inset_mask_map[] = {
8475 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8476 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8477 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8478 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8479 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8480 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8481 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8482 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8485 if (!inset || !mask || !nb_elem)
8488 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8489 /* Clear the inset bit, if no MASK is required,
8490 * for example proto + ttl
8492 if ((inset & inset_mask_map[i].inset) ==
8493 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8494 inset_need_mask &= ~inset_mask_map[i].inset;
8495 if (!inset_need_mask)
8498 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8499 if ((inset_need_mask & inset_mask_map[i].inset) ==
8500 inset_mask_map[i].inset) {
8501 if (idx >= nb_elem) {
8502 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8505 mask[idx] = inset_mask_map[i].mask;
8514 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8516 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8518 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8520 i40e_write_rx_ctl(hw, addr, val);
8521 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8522 (uint32_t)i40e_read_rx_ctl(hw, addr));
8526 i40e_filter_input_set_init(struct i40e_pf *pf)
8528 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8529 enum i40e_filter_pctype pctype;
8530 uint64_t input_set, inset_reg;
8531 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8535 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8536 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8537 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8539 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8542 input_set = i40e_get_default_input_set(pctype);
8544 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8545 I40E_INSET_MASK_NUM_REG);
8548 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8551 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8552 (uint32_t)(inset_reg & UINT32_MAX));
8553 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8554 (uint32_t)((inset_reg >>
8555 I40E_32_BIT_WIDTH) & UINT32_MAX));
8556 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8557 (uint32_t)(inset_reg & UINT32_MAX));
8558 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8559 (uint32_t)((inset_reg >>
8560 I40E_32_BIT_WIDTH) & UINT32_MAX));
8562 for (i = 0; i < num; i++) {
8563 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8565 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8568 /*clear unused mask registers of the pctype */
8569 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8570 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8572 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8575 I40E_WRITE_FLUSH(hw);
8577 /* store the default input set */
8578 pf->hash_input_set[pctype] = input_set;
8579 pf->fdir.input_set[pctype] = input_set;
8584 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8585 struct rte_eth_input_set_conf *conf)
8587 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8588 enum i40e_filter_pctype pctype;
8589 uint64_t input_set, inset_reg = 0;
8590 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8594 PMD_DRV_LOG(ERR, "Invalid pointer");
8597 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8598 conf->op != RTE_ETH_INPUT_SET_ADD) {
8599 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8603 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8604 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8605 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8609 if (hw->mac.type == I40E_MAC_X722) {
8610 /* get translated pctype value in fd pctype register */
8611 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8612 I40E_GLQF_FD_PCTYPES((int)pctype));
8615 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8618 PMD_DRV_LOG(ERR, "Failed to parse input set");
8622 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8623 /* get inset value in register */
8624 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8625 inset_reg <<= I40E_32_BIT_WIDTH;
8626 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8627 input_set |= pf->hash_input_set[pctype];
8629 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8630 I40E_INSET_MASK_NUM_REG);
8634 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8636 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8637 (uint32_t)(inset_reg & UINT32_MAX));
8638 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8639 (uint32_t)((inset_reg >>
8640 I40E_32_BIT_WIDTH) & UINT32_MAX));
8642 for (i = 0; i < num; i++)
8643 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8645 /*clear unused mask registers of the pctype */
8646 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8647 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8649 I40E_WRITE_FLUSH(hw);
8651 pf->hash_input_set[pctype] = input_set;
8656 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8657 struct rte_eth_input_set_conf *conf)
8659 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8660 enum i40e_filter_pctype pctype;
8661 uint64_t input_set, inset_reg = 0;
8662 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8666 PMD_DRV_LOG(ERR, "Invalid pointer");
8669 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8670 conf->op != RTE_ETH_INPUT_SET_ADD) {
8671 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8675 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8677 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8678 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8682 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8685 PMD_DRV_LOG(ERR, "Failed to parse input set");
8689 /* get inset value in register */
8690 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8691 inset_reg <<= I40E_32_BIT_WIDTH;
8692 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8694 /* Can not change the inset reg for flex payload for fdir,
8695 * it is done by writing I40E_PRTQF_FD_FLXINSET
8696 * in i40e_set_flex_mask_on_pctype.
8698 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8699 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8701 input_set |= pf->fdir.input_set[pctype];
8702 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8703 I40E_INSET_MASK_NUM_REG);
8707 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8709 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8710 (uint32_t)(inset_reg & UINT32_MAX));
8711 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8712 (uint32_t)((inset_reg >>
8713 I40E_32_BIT_WIDTH) & UINT32_MAX));
8715 for (i = 0; i < num; i++)
8716 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8718 /*clear unused mask registers of the pctype */
8719 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8720 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8722 I40E_WRITE_FLUSH(hw);
8724 pf->fdir.input_set[pctype] = input_set;
8729 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8734 PMD_DRV_LOG(ERR, "Invalid pointer");
8738 switch (info->info_type) {
8739 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8740 i40e_get_symmetric_hash_enable_per_port(hw,
8741 &(info->info.enable));
8743 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8744 ret = i40e_get_hash_filter_global_config(hw,
8745 &(info->info.global_conf));
8748 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8758 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8763 PMD_DRV_LOG(ERR, "Invalid pointer");
8767 switch (info->info_type) {
8768 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8769 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8771 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8772 ret = i40e_set_hash_filter_global_config(hw,
8773 &(info->info.global_conf));
8775 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8776 ret = i40e_hash_filter_inset_select(hw,
8777 &(info->info.input_set_conf));
8781 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8790 /* Operations for hash function */
8792 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8793 enum rte_filter_op filter_op,
8796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8799 switch (filter_op) {
8800 case RTE_ETH_FILTER_NOP:
8802 case RTE_ETH_FILTER_GET:
8803 ret = i40e_hash_filter_get(hw,
8804 (struct rte_eth_hash_filter_info *)arg);
8806 case RTE_ETH_FILTER_SET:
8807 ret = i40e_hash_filter_set(hw,
8808 (struct rte_eth_hash_filter_info *)arg);
8811 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8820 /* Convert ethertype filter structure */
8822 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8823 struct i40e_ethertype_filter *filter)
8825 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8826 filter->input.ether_type = input->ether_type;
8827 filter->flags = input->flags;
8828 filter->queue = input->queue;
8833 /* Check if there exists the ehtertype filter */
8834 struct i40e_ethertype_filter *
8835 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8836 const struct i40e_ethertype_filter_input *input)
8840 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8844 return ethertype_rule->hash_map[ret];
8847 /* Add ethertype filter in SW list */
8849 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8850 struct i40e_ethertype_filter *filter)
8852 struct i40e_ethertype_rule *rule = &pf->ethertype;
8855 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8858 "Failed to insert ethertype filter"
8859 " to hash table %d!",
8863 rule->hash_map[ret] = filter;
8865 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8870 /* Delete ethertype filter in SW list */
8872 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8873 struct i40e_ethertype_filter_input *input)
8875 struct i40e_ethertype_rule *rule = &pf->ethertype;
8876 struct i40e_ethertype_filter *filter;
8879 ret = rte_hash_del_key(rule->hash_table, input);
8882 "Failed to delete ethertype filter"
8883 " to hash table %d!",
8887 filter = rule->hash_map[ret];
8888 rule->hash_map[ret] = NULL;
8890 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8897 * Configure ethertype filter, which can director packet by filtering
8898 * with mac address and ether_type or only ether_type
8901 i40e_ethertype_filter_set(struct i40e_pf *pf,
8902 struct rte_eth_ethertype_filter *filter,
8905 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8906 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8907 struct i40e_ethertype_filter *ethertype_filter, *node;
8908 struct i40e_ethertype_filter check_filter;
8909 struct i40e_control_filter_stats stats;
8913 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8914 PMD_DRV_LOG(ERR, "Invalid queue ID");
8917 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8918 filter->ether_type == ETHER_TYPE_IPv6) {
8920 "unsupported ether_type(0x%04x) in control packet filter.",
8921 filter->ether_type);
8924 if (filter->ether_type == ETHER_TYPE_VLAN)
8925 PMD_DRV_LOG(WARNING,
8926 "filter vlan ether_type in first tag is not supported.");
8928 /* Check if there is the filter in SW list */
8929 memset(&check_filter, 0, sizeof(check_filter));
8930 i40e_ethertype_filter_convert(filter, &check_filter);
8931 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8932 &check_filter.input);
8934 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8938 if (!add && !node) {
8939 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8943 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8944 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8945 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8946 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8947 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8949 memset(&stats, 0, sizeof(stats));
8950 ret = i40e_aq_add_rem_control_packet_filter(hw,
8951 filter->mac_addr.addr_bytes,
8952 filter->ether_type, flags,
8954 filter->queue, add, &stats, NULL);
8957 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8958 ret, stats.mac_etype_used, stats.etype_used,
8959 stats.mac_etype_free, stats.etype_free);
8963 /* Add or delete a filter in SW list */
8965 ethertype_filter = rte_zmalloc("ethertype_filter",
8966 sizeof(*ethertype_filter), 0);
8967 rte_memcpy(ethertype_filter, &check_filter,
8968 sizeof(check_filter));
8969 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8971 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8978 * Handle operations for ethertype filter.
8981 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8982 enum rte_filter_op filter_op,
8985 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8988 if (filter_op == RTE_ETH_FILTER_NOP)
8992 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8997 switch (filter_op) {
8998 case RTE_ETH_FILTER_ADD:
8999 ret = i40e_ethertype_filter_set(pf,
9000 (struct rte_eth_ethertype_filter *)arg,
9003 case RTE_ETH_FILTER_DELETE:
9004 ret = i40e_ethertype_filter_set(pf,
9005 (struct rte_eth_ethertype_filter *)arg,
9009 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9017 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9018 enum rte_filter_type filter_type,
9019 enum rte_filter_op filter_op,
9027 switch (filter_type) {
9028 case RTE_ETH_FILTER_NONE:
9029 /* For global configuration */
9030 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9032 case RTE_ETH_FILTER_HASH:
9033 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9035 case RTE_ETH_FILTER_MACVLAN:
9036 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9038 case RTE_ETH_FILTER_ETHERTYPE:
9039 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9041 case RTE_ETH_FILTER_TUNNEL:
9042 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9044 case RTE_ETH_FILTER_FDIR:
9045 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9047 case RTE_ETH_FILTER_GENERIC:
9048 if (filter_op != RTE_ETH_FILTER_GET)
9050 *(const void **)arg = &i40e_flow_ops;
9053 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9063 * Check and enable Extended Tag.
9064 * Enabling Extended Tag is important for 40G performance.
9067 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9069 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9073 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9076 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9080 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9081 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9086 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9089 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9093 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9094 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9097 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9098 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9101 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9108 * As some registers wouldn't be reset unless a global hardware reset,
9109 * hardware initialization is needed to put those registers into an
9110 * expected initial state.
9113 i40e_hw_init(struct rte_eth_dev *dev)
9115 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9117 i40e_enable_extended_tag(dev);
9119 /* clear the PF Queue Filter control register */
9120 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9122 /* Disable symmetric hash per port */
9123 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9127 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9128 * however this function will return only one highest pctype index,
9129 * which is not quite correct. This is known problem of i40e driver
9130 * and needs to be fixed later.
9132 enum i40e_filter_pctype
9133 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9136 uint64_t pctype_mask;
9138 if (flow_type < I40E_FLOW_TYPE_MAX) {
9139 pctype_mask = adapter->pctypes_tbl[flow_type];
9140 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9141 if (pctype_mask & (1ULL << i))
9142 return (enum i40e_filter_pctype)i;
9145 return I40E_FILTER_PCTYPE_INVALID;
9149 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9150 enum i40e_filter_pctype pctype)
9153 uint64_t pctype_mask = 1ULL << pctype;
9155 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9157 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9161 return RTE_ETH_FLOW_UNKNOWN;
9165 * On X710, performance number is far from the expectation on recent firmware
9166 * versions; on XL710, performance number is also far from the expectation on
9167 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9168 * mode is enabled and port MAC address is equal to the packet destination MAC
9169 * address. The fix for this issue may not be integrated in the following
9170 * firmware version. So the workaround in software driver is needed. It needs
9171 * to modify the initial values of 3 internal only registers for both X710 and
9172 * XL710. Note that the values for X710 or XL710 could be different, and the
9173 * workaround can be removed when it is fixed in firmware in the future.
9176 /* For both X710 and XL710 */
9177 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9178 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9179 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9181 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9182 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9185 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9186 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9189 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9191 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9192 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9195 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9197 enum i40e_status_code status;
9198 struct i40e_aq_get_phy_abilities_resp phy_ab;
9202 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9206 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9209 rte_delay_us(100000);
9211 status = i40e_aq_get_phy_capabilities(hw, false,
9212 true, &phy_ab, NULL);
9220 i40e_configure_registers(struct i40e_hw *hw)
9226 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9227 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9228 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9234 for (i = 0; i < RTE_DIM(reg_table); i++) {
9235 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9236 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9238 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9239 else /* For X710/XL710/XXV710 */
9240 if (hw->aq.fw_maj_ver < 6)
9242 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9245 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9248 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9249 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9251 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9252 else /* For X710/XL710/XXV710 */
9254 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9257 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9258 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9259 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9261 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9264 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9267 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9270 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9274 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9275 reg_table[i].addr, reg);
9276 if (reg == reg_table[i].val)
9279 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9280 reg_table[i].val, NULL);
9283 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9284 reg_table[i].val, reg_table[i].addr);
9287 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9288 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9292 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9293 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9294 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9295 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9297 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9302 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9303 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9307 /* Configure for double VLAN RX stripping */
9308 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9309 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9310 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9311 ret = i40e_aq_debug_write_register(hw,
9312 I40E_VSI_TSR(vsi->vsi_id),
9315 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9317 return I40E_ERR_CONFIG;
9321 /* Configure for double VLAN TX insertion */
9322 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9323 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9324 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9325 ret = i40e_aq_debug_write_register(hw,
9326 I40E_VSI_L2TAGSTXVALID(
9327 vsi->vsi_id), reg, NULL);
9330 "Failed to update VSI_L2TAGSTXVALID[%d]",
9332 return I40E_ERR_CONFIG;
9340 * i40e_aq_add_mirror_rule
9341 * @hw: pointer to the hardware structure
9342 * @seid: VEB seid to add mirror rule to
9343 * @dst_id: destination vsi seid
9344 * @entries: Buffer which contains the entities to be mirrored
9345 * @count: number of entities contained in the buffer
9346 * @rule_id:the rule_id of the rule to be added
9348 * Add a mirror rule for a given veb.
9351 static enum i40e_status_code
9352 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9353 uint16_t seid, uint16_t dst_id,
9354 uint16_t rule_type, uint16_t *entries,
9355 uint16_t count, uint16_t *rule_id)
9357 struct i40e_aq_desc desc;
9358 struct i40e_aqc_add_delete_mirror_rule cmd;
9359 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9360 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9363 enum i40e_status_code status;
9365 i40e_fill_default_direct_cmd_desc(&desc,
9366 i40e_aqc_opc_add_mirror_rule);
9367 memset(&cmd, 0, sizeof(cmd));
9369 buff_len = sizeof(uint16_t) * count;
9370 desc.datalen = rte_cpu_to_le_16(buff_len);
9372 desc.flags |= rte_cpu_to_le_16(
9373 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9374 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9375 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9376 cmd.num_entries = rte_cpu_to_le_16(count);
9377 cmd.seid = rte_cpu_to_le_16(seid);
9378 cmd.destination = rte_cpu_to_le_16(dst_id);
9380 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9381 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9383 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9384 hw->aq.asq_last_status, resp->rule_id,
9385 resp->mirror_rules_used, resp->mirror_rules_free);
9386 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9392 * i40e_aq_del_mirror_rule
9393 * @hw: pointer to the hardware structure
9394 * @seid: VEB seid to add mirror rule to
9395 * @entries: Buffer which contains the entities to be mirrored
9396 * @count: number of entities contained in the buffer
9397 * @rule_id:the rule_id of the rule to be delete
9399 * Delete a mirror rule for a given veb.
9402 static enum i40e_status_code
9403 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9404 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9405 uint16_t count, uint16_t rule_id)
9407 struct i40e_aq_desc desc;
9408 struct i40e_aqc_add_delete_mirror_rule cmd;
9409 uint16_t buff_len = 0;
9410 enum i40e_status_code status;
9413 i40e_fill_default_direct_cmd_desc(&desc,
9414 i40e_aqc_opc_delete_mirror_rule);
9415 memset(&cmd, 0, sizeof(cmd));
9416 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9417 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9419 cmd.num_entries = count;
9420 buff_len = sizeof(uint16_t) * count;
9421 desc.datalen = rte_cpu_to_le_16(buff_len);
9422 buff = (void *)entries;
9424 /* rule id is filled in destination field for deleting mirror rule */
9425 cmd.destination = rte_cpu_to_le_16(rule_id);
9427 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9428 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9429 cmd.seid = rte_cpu_to_le_16(seid);
9431 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9432 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9438 * i40e_mirror_rule_set
9439 * @dev: pointer to the hardware structure
9440 * @mirror_conf: mirror rule info
9441 * @sw_id: mirror rule's sw_id
9442 * @on: enable/disable
9444 * set a mirror rule.
9448 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9449 struct rte_eth_mirror_conf *mirror_conf,
9450 uint8_t sw_id, uint8_t on)
9452 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9453 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9454 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9455 struct i40e_mirror_rule *parent = NULL;
9456 uint16_t seid, dst_seid, rule_id;
9460 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9462 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9464 "mirror rule can not be configured without veb or vfs.");
9467 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9468 PMD_DRV_LOG(ERR, "mirror table is full.");
9471 if (mirror_conf->dst_pool > pf->vf_num) {
9472 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9473 mirror_conf->dst_pool);
9477 seid = pf->main_vsi->veb->seid;
9479 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9480 if (sw_id <= it->index) {
9486 if (mirr_rule && sw_id == mirr_rule->index) {
9488 PMD_DRV_LOG(ERR, "mirror rule exists.");
9491 ret = i40e_aq_del_mirror_rule(hw, seid,
9492 mirr_rule->rule_type,
9494 mirr_rule->num_entries, mirr_rule->id);
9497 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9498 ret, hw->aq.asq_last_status);
9501 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9502 rte_free(mirr_rule);
9503 pf->nb_mirror_rule--;
9507 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9511 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9512 sizeof(struct i40e_mirror_rule) , 0);
9514 PMD_DRV_LOG(ERR, "failed to allocate memory");
9515 return I40E_ERR_NO_MEMORY;
9517 switch (mirror_conf->rule_type) {
9518 case ETH_MIRROR_VLAN:
9519 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9520 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9521 mirr_rule->entries[j] =
9522 mirror_conf->vlan.vlan_id[i];
9527 PMD_DRV_LOG(ERR, "vlan is not specified.");
9528 rte_free(mirr_rule);
9531 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9533 case ETH_MIRROR_VIRTUAL_POOL_UP:
9534 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9535 /* check if the specified pool bit is out of range */
9536 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9537 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9538 rte_free(mirr_rule);
9541 for (i = 0, j = 0; i < pf->vf_num; i++) {
9542 if (mirror_conf->pool_mask & (1ULL << i)) {
9543 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9547 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9548 /* add pf vsi to entries */
9549 mirr_rule->entries[j] = pf->main_vsi_seid;
9553 PMD_DRV_LOG(ERR, "pool is not specified.");
9554 rte_free(mirr_rule);
9557 /* egress and ingress in aq commands means from switch but not port */
9558 mirr_rule->rule_type =
9559 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9560 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9561 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9563 case ETH_MIRROR_UPLINK_PORT:
9564 /* egress and ingress in aq commands means from switch but not port*/
9565 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9567 case ETH_MIRROR_DOWNLINK_PORT:
9568 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9571 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9572 mirror_conf->rule_type);
9573 rte_free(mirr_rule);
9577 /* If the dst_pool is equal to vf_num, consider it as PF */
9578 if (mirror_conf->dst_pool == pf->vf_num)
9579 dst_seid = pf->main_vsi_seid;
9581 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9583 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9584 mirr_rule->rule_type, mirr_rule->entries,
9588 "failed to add mirror rule: ret = %d, aq_err = %d.",
9589 ret, hw->aq.asq_last_status);
9590 rte_free(mirr_rule);
9594 mirr_rule->index = sw_id;
9595 mirr_rule->num_entries = j;
9596 mirr_rule->id = rule_id;
9597 mirr_rule->dst_vsi_seid = dst_seid;
9600 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9602 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9604 pf->nb_mirror_rule++;
9609 * i40e_mirror_rule_reset
9610 * @dev: pointer to the device
9611 * @sw_id: mirror rule's sw_id
9613 * reset a mirror rule.
9617 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9619 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9620 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9621 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9625 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9627 seid = pf->main_vsi->veb->seid;
9629 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9630 if (sw_id == it->index) {
9636 ret = i40e_aq_del_mirror_rule(hw, seid,
9637 mirr_rule->rule_type,
9639 mirr_rule->num_entries, mirr_rule->id);
9642 "failed to remove mirror rule: status = %d, aq_err = %d.",
9643 ret, hw->aq.asq_last_status);
9646 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9647 rte_free(mirr_rule);
9648 pf->nb_mirror_rule--;
9650 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9657 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9660 uint64_t systim_cycles;
9662 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9663 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9666 return systim_cycles;
9670 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9672 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9675 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9676 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9683 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9688 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9689 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9696 i40e_start_timecounters(struct rte_eth_dev *dev)
9698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9699 struct i40e_adapter *adapter =
9700 (struct i40e_adapter *)dev->data->dev_private;
9701 struct rte_eth_link link;
9702 uint32_t tsync_inc_l;
9703 uint32_t tsync_inc_h;
9705 /* Get current link speed. */
9706 memset(&link, 0, sizeof(link));
9707 i40e_dev_link_update(dev, 1);
9708 rte_i40e_dev_atomic_read_link_status(dev, &link);
9710 switch (link.link_speed) {
9711 case ETH_SPEED_NUM_40G:
9712 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9713 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9715 case ETH_SPEED_NUM_10G:
9716 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9717 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9719 case ETH_SPEED_NUM_1G:
9720 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9721 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9728 /* Set the timesync increment value. */
9729 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9730 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9732 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9733 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9734 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9736 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9737 adapter->systime_tc.cc_shift = 0;
9738 adapter->systime_tc.nsec_mask = 0;
9740 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9741 adapter->rx_tstamp_tc.cc_shift = 0;
9742 adapter->rx_tstamp_tc.nsec_mask = 0;
9744 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9745 adapter->tx_tstamp_tc.cc_shift = 0;
9746 adapter->tx_tstamp_tc.nsec_mask = 0;
9750 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9752 struct i40e_adapter *adapter =
9753 (struct i40e_adapter *)dev->data->dev_private;
9755 adapter->systime_tc.nsec += delta;
9756 adapter->rx_tstamp_tc.nsec += delta;
9757 adapter->tx_tstamp_tc.nsec += delta;
9763 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9766 struct i40e_adapter *adapter =
9767 (struct i40e_adapter *)dev->data->dev_private;
9769 ns = rte_timespec_to_ns(ts);
9771 /* Set the timecounters to a new value. */
9772 adapter->systime_tc.nsec = ns;
9773 adapter->rx_tstamp_tc.nsec = ns;
9774 adapter->tx_tstamp_tc.nsec = ns;
9780 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9782 uint64_t ns, systime_cycles;
9783 struct i40e_adapter *adapter =
9784 (struct i40e_adapter *)dev->data->dev_private;
9786 systime_cycles = i40e_read_systime_cyclecounter(dev);
9787 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9788 *ts = rte_ns_to_timespec(ns);
9794 i40e_timesync_enable(struct rte_eth_dev *dev)
9796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9797 uint32_t tsync_ctl_l;
9798 uint32_t tsync_ctl_h;
9800 /* Stop the timesync system time. */
9801 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9802 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9803 /* Reset the timesync system time value. */
9804 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9805 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9807 i40e_start_timecounters(dev);
9809 /* Clear timesync registers. */
9810 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9811 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9812 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9813 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9814 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9815 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9817 /* Enable timestamping of PTP packets. */
9818 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9819 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9821 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9822 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9823 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9825 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9826 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9832 i40e_timesync_disable(struct rte_eth_dev *dev)
9834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9835 uint32_t tsync_ctl_l;
9836 uint32_t tsync_ctl_h;
9838 /* Disable timestamping of transmitted PTP packets. */
9839 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9840 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9842 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9843 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9845 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9846 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9848 /* Reset the timesync increment value. */
9849 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9850 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9856 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9857 struct timespec *timestamp, uint32_t flags)
9859 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9860 struct i40e_adapter *adapter =
9861 (struct i40e_adapter *)dev->data->dev_private;
9863 uint32_t sync_status;
9864 uint32_t index = flags & 0x03;
9865 uint64_t rx_tstamp_cycles;
9868 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9869 if ((sync_status & (1 << index)) == 0)
9872 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9873 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9874 *timestamp = rte_ns_to_timespec(ns);
9880 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9881 struct timespec *timestamp)
9883 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9884 struct i40e_adapter *adapter =
9885 (struct i40e_adapter *)dev->data->dev_private;
9887 uint32_t sync_status;
9888 uint64_t tx_tstamp_cycles;
9891 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9892 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9895 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9896 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9897 *timestamp = rte_ns_to_timespec(ns);
9903 * i40e_parse_dcb_configure - parse dcb configure from user
9904 * @dev: the device being configured
9905 * @dcb_cfg: pointer of the result of parse
9906 * @*tc_map: bit map of enabled traffic classes
9908 * Returns 0 on success, negative value on failure
9911 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9912 struct i40e_dcbx_config *dcb_cfg,
9915 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9916 uint8_t i, tc_bw, bw_lf;
9918 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9920 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9921 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9922 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9926 /* assume each tc has the same bw */
9927 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9928 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9929 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9930 /* to ensure the sum of tcbw is equal to 100 */
9931 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9932 for (i = 0; i < bw_lf; i++)
9933 dcb_cfg->etscfg.tcbwtable[i]++;
9935 /* assume each tc has the same Transmission Selection Algorithm */
9936 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9937 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9939 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9940 dcb_cfg->etscfg.prioritytable[i] =
9941 dcb_rx_conf->dcb_tc[i];
9943 /* FW needs one App to configure HW */
9944 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9945 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9946 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9947 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9949 if (dcb_rx_conf->nb_tcs == 0)
9950 *tc_map = 1; /* tc0 only */
9952 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9954 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9955 dcb_cfg->pfc.willing = 0;
9956 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9957 dcb_cfg->pfc.pfcenable = *tc_map;
9963 static enum i40e_status_code
9964 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9965 struct i40e_aqc_vsi_properties_data *info,
9966 uint8_t enabled_tcmap)
9968 enum i40e_status_code ret;
9969 int i, total_tc = 0;
9970 uint16_t qpnum_per_tc, bsf, qp_idx;
9971 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9972 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9973 uint16_t used_queues;
9975 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9976 if (ret != I40E_SUCCESS)
9979 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9980 if (enabled_tcmap & (1 << i))
9985 vsi->enabled_tc = enabled_tcmap;
9987 /* different VSI has different queues assigned */
9988 if (vsi->type == I40E_VSI_MAIN)
9989 used_queues = dev_data->nb_rx_queues -
9990 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9991 else if (vsi->type == I40E_VSI_VMDQ2)
9992 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9994 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9995 return I40E_ERR_NO_AVAILABLE_VSI;
9998 qpnum_per_tc = used_queues / total_tc;
9999 /* Number of queues per enabled TC */
10000 if (qpnum_per_tc == 0) {
10001 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10002 return I40E_ERR_INVALID_QP_ID;
10004 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10005 I40E_MAX_Q_PER_TC);
10006 bsf = rte_bsf32(qpnum_per_tc);
10009 * Configure TC and queue mapping parameters, for enabled TC,
10010 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10011 * default queue will serve it.
10014 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10015 if (vsi->enabled_tc & (1 << i)) {
10016 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10017 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10018 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10019 qp_idx += qpnum_per_tc;
10021 info->tc_mapping[i] = 0;
10024 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10025 if (vsi->type == I40E_VSI_SRIOV) {
10026 info->mapping_flags |=
10027 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10028 for (i = 0; i < vsi->nb_qps; i++)
10029 info->queue_mapping[i] =
10030 rte_cpu_to_le_16(vsi->base_queue + i);
10032 info->mapping_flags |=
10033 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10034 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10036 info->valid_sections |=
10037 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10039 return I40E_SUCCESS;
10043 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10044 * @veb: VEB to be configured
10045 * @tc_map: enabled TC bitmap
10047 * Returns 0 on success, negative value on failure
10049 static enum i40e_status_code
10050 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10052 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10053 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10054 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10055 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10056 enum i40e_status_code ret = I40E_SUCCESS;
10060 /* Check if enabled_tc is same as existing or new TCs */
10061 if (veb->enabled_tc == tc_map)
10064 /* configure tc bandwidth */
10065 memset(&veb_bw, 0, sizeof(veb_bw));
10066 veb_bw.tc_valid_bits = tc_map;
10067 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10068 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10069 if (tc_map & BIT_ULL(i))
10070 veb_bw.tc_bw_share_credits[i] = 1;
10072 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10076 "AQ command Config switch_comp BW allocation per TC failed = %d",
10077 hw->aq.asq_last_status);
10081 memset(&ets_query, 0, sizeof(ets_query));
10082 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10084 if (ret != I40E_SUCCESS) {
10086 "Failed to get switch_comp ETS configuration %u",
10087 hw->aq.asq_last_status);
10090 memset(&bw_query, 0, sizeof(bw_query));
10091 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10093 if (ret != I40E_SUCCESS) {
10095 "Failed to get switch_comp bandwidth configuration %u",
10096 hw->aq.asq_last_status);
10100 /* store and print out BW info */
10101 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10102 veb->bw_info.bw_max = ets_query.tc_bw_max;
10103 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10104 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10105 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10106 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10107 I40E_16_BIT_WIDTH);
10108 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10109 veb->bw_info.bw_ets_share_credits[i] =
10110 bw_query.tc_bw_share_credits[i];
10111 veb->bw_info.bw_ets_credits[i] =
10112 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10113 /* 4 bits per TC, 4th bit is reserved */
10114 veb->bw_info.bw_ets_max[i] =
10115 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10116 RTE_LEN2MASK(3, uint8_t));
10117 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10118 veb->bw_info.bw_ets_share_credits[i]);
10119 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10120 veb->bw_info.bw_ets_credits[i]);
10121 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10122 veb->bw_info.bw_ets_max[i]);
10125 veb->enabled_tc = tc_map;
10132 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10133 * @vsi: VSI to be configured
10134 * @tc_map: enabled TC bitmap
10136 * Returns 0 on success, negative value on failure
10138 static enum i40e_status_code
10139 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10141 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10142 struct i40e_vsi_context ctxt;
10143 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10144 enum i40e_status_code ret = I40E_SUCCESS;
10147 /* Check if enabled_tc is same as existing or new TCs */
10148 if (vsi->enabled_tc == tc_map)
10151 /* configure tc bandwidth */
10152 memset(&bw_data, 0, sizeof(bw_data));
10153 bw_data.tc_valid_bits = tc_map;
10154 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10155 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10156 if (tc_map & BIT_ULL(i))
10157 bw_data.tc_bw_credits[i] = 1;
10159 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10162 "AQ command Config VSI BW allocation per TC failed = %d",
10163 hw->aq.asq_last_status);
10166 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10167 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10169 /* Update Queue Pairs Mapping for currently enabled UPs */
10170 ctxt.seid = vsi->seid;
10171 ctxt.pf_num = hw->pf_id;
10173 ctxt.uplink_seid = vsi->uplink_seid;
10174 ctxt.info = vsi->info;
10176 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10180 /* Update the VSI after updating the VSI queue-mapping information */
10181 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10183 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10184 hw->aq.asq_last_status);
10187 /* update the local VSI info with updated queue map */
10188 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10189 sizeof(vsi->info.tc_mapping));
10190 rte_memcpy(&vsi->info.queue_mapping,
10191 &ctxt.info.queue_mapping,
10192 sizeof(vsi->info.queue_mapping));
10193 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10194 vsi->info.valid_sections = 0;
10196 /* query and update current VSI BW information */
10197 ret = i40e_vsi_get_bw_config(vsi);
10200 "Failed updating vsi bw info, err %s aq_err %s",
10201 i40e_stat_str(hw, ret),
10202 i40e_aq_str(hw, hw->aq.asq_last_status));
10206 vsi->enabled_tc = tc_map;
10213 * i40e_dcb_hw_configure - program the dcb setting to hw
10214 * @pf: pf the configuration is taken on
10215 * @new_cfg: new configuration
10216 * @tc_map: enabled TC bitmap
10218 * Returns 0 on success, negative value on failure
10220 static enum i40e_status_code
10221 i40e_dcb_hw_configure(struct i40e_pf *pf,
10222 struct i40e_dcbx_config *new_cfg,
10225 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10226 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10227 struct i40e_vsi *main_vsi = pf->main_vsi;
10228 struct i40e_vsi_list *vsi_list;
10229 enum i40e_status_code ret;
10233 /* Use the FW API if FW > v4.4*/
10234 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10235 (hw->aq.fw_maj_ver >= 5))) {
10237 "FW < v4.4, can not use FW LLDP API to configure DCB");
10238 return I40E_ERR_FIRMWARE_API_VERSION;
10241 /* Check if need reconfiguration */
10242 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10243 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10244 return I40E_SUCCESS;
10247 /* Copy the new config to the current config */
10248 *old_cfg = *new_cfg;
10249 old_cfg->etsrec = old_cfg->etscfg;
10250 ret = i40e_set_dcb_config(hw);
10252 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10253 i40e_stat_str(hw, ret),
10254 i40e_aq_str(hw, hw->aq.asq_last_status));
10257 /* set receive Arbiter to RR mode and ETS scheme by default */
10258 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10259 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10260 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10261 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10262 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10263 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10264 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10265 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10266 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10267 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10268 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10269 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10270 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10272 /* get local mib to check whether it is configured correctly */
10274 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10275 /* Get Local DCB Config */
10276 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10277 &hw->local_dcbx_config);
10279 /* if Veb is created, need to update TC of it at first */
10280 if (main_vsi->veb) {
10281 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10283 PMD_INIT_LOG(WARNING,
10284 "Failed configuring TC for VEB seid=%d",
10285 main_vsi->veb->seid);
10287 /* Update each VSI */
10288 i40e_vsi_config_tc(main_vsi, tc_map);
10289 if (main_vsi->veb) {
10290 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10291 /* Beside main VSI and VMDQ VSIs, only enable default
10292 * TC for other VSIs
10294 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10295 ret = i40e_vsi_config_tc(vsi_list->vsi,
10298 ret = i40e_vsi_config_tc(vsi_list->vsi,
10299 I40E_DEFAULT_TCMAP);
10301 PMD_INIT_LOG(WARNING,
10302 "Failed configuring TC for VSI seid=%d",
10303 vsi_list->vsi->seid);
10307 return I40E_SUCCESS;
10311 * i40e_dcb_init_configure - initial dcb config
10312 * @dev: device being configured
10313 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10315 * Returns 0 on success, negative value on failure
10318 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10320 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10321 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10324 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10325 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10329 /* DCB initialization:
10330 * Update DCB configuration from the Firmware and configure
10331 * LLDP MIB change event.
10333 if (sw_dcb == TRUE) {
10334 ret = i40e_init_dcb(hw);
10335 /* If lldp agent is stopped, the return value from
10336 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10337 * adminq status. Otherwise, it should return success.
10339 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10340 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10341 memset(&hw->local_dcbx_config, 0,
10342 sizeof(struct i40e_dcbx_config));
10343 /* set dcb default configuration */
10344 hw->local_dcbx_config.etscfg.willing = 0;
10345 hw->local_dcbx_config.etscfg.maxtcs = 0;
10346 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10347 hw->local_dcbx_config.etscfg.tsatable[0] =
10349 /* all UPs mapping to TC0 */
10350 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10351 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10352 hw->local_dcbx_config.etsrec =
10353 hw->local_dcbx_config.etscfg;
10354 hw->local_dcbx_config.pfc.willing = 0;
10355 hw->local_dcbx_config.pfc.pfccap =
10356 I40E_MAX_TRAFFIC_CLASS;
10357 /* FW needs one App to configure HW */
10358 hw->local_dcbx_config.numapps = 1;
10359 hw->local_dcbx_config.app[0].selector =
10360 I40E_APP_SEL_ETHTYPE;
10361 hw->local_dcbx_config.app[0].priority = 3;
10362 hw->local_dcbx_config.app[0].protocolid =
10363 I40E_APP_PROTOID_FCOE;
10364 ret = i40e_set_dcb_config(hw);
10367 "default dcb config fails. err = %d, aq_err = %d.",
10368 ret, hw->aq.asq_last_status);
10373 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10374 ret, hw->aq.asq_last_status);
10378 ret = i40e_aq_start_lldp(hw, NULL);
10379 if (ret != I40E_SUCCESS)
10380 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10382 ret = i40e_init_dcb(hw);
10384 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10386 "HW doesn't support DCBX offload.");
10391 "DCBX configuration failed, err = %d, aq_err = %d.",
10392 ret, hw->aq.asq_last_status);
10400 * i40e_dcb_setup - setup dcb related config
10401 * @dev: device being configured
10403 * Returns 0 on success, negative value on failure
10406 i40e_dcb_setup(struct rte_eth_dev *dev)
10408 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10409 struct i40e_dcbx_config dcb_cfg;
10410 uint8_t tc_map = 0;
10413 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10414 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10418 if (pf->vf_num != 0)
10419 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10421 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10423 PMD_INIT_LOG(ERR, "invalid dcb config");
10426 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10428 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10436 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10437 struct rte_eth_dcb_info *dcb_info)
10439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10441 struct i40e_vsi *vsi = pf->main_vsi;
10442 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10443 uint16_t bsf, tc_mapping;
10446 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10447 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10449 dcb_info->nb_tcs = 1;
10450 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10451 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10452 for (i = 0; i < dcb_info->nb_tcs; i++)
10453 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10455 /* get queue mapping if vmdq is disabled */
10456 if (!pf->nb_cfg_vmdq_vsi) {
10457 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10458 if (!(vsi->enabled_tc & (1 << i)))
10460 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10461 dcb_info->tc_queue.tc_rxq[j][i].base =
10462 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10463 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10464 dcb_info->tc_queue.tc_txq[j][i].base =
10465 dcb_info->tc_queue.tc_rxq[j][i].base;
10466 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10467 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10468 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10469 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10470 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10475 /* get queue mapping if vmdq is enabled */
10477 vsi = pf->vmdq[j].vsi;
10478 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10479 if (!(vsi->enabled_tc & (1 << i)))
10481 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10482 dcb_info->tc_queue.tc_rxq[j][i].base =
10483 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10484 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10485 dcb_info->tc_queue.tc_txq[j][i].base =
10486 dcb_info->tc_queue.tc_rxq[j][i].base;
10487 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10488 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10489 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10490 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10491 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10494 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10499 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10501 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10502 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10503 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10504 uint16_t interval =
10505 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10506 uint16_t msix_intr;
10508 msix_intr = intr_handle->intr_vec[queue_id];
10509 if (msix_intr == I40E_MISC_VEC_ID)
10510 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10511 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10512 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10513 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10515 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10518 I40E_PFINT_DYN_CTLN(msix_intr -
10519 I40E_RX_VEC_START),
10520 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10521 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10522 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10524 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10526 I40E_WRITE_FLUSH(hw);
10527 rte_intr_enable(&pci_dev->intr_handle);
10533 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10535 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10536 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10537 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10538 uint16_t msix_intr;
10540 msix_intr = intr_handle->intr_vec[queue_id];
10541 if (msix_intr == I40E_MISC_VEC_ID)
10542 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10545 I40E_PFINT_DYN_CTLN(msix_intr -
10546 I40E_RX_VEC_START),
10548 I40E_WRITE_FLUSH(hw);
10553 static int i40e_get_regs(struct rte_eth_dev *dev,
10554 struct rte_dev_reg_info *regs)
10556 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10557 uint32_t *ptr_data = regs->data;
10558 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10559 const struct i40e_reg_info *reg_info;
10561 if (ptr_data == NULL) {
10562 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10563 regs->width = sizeof(uint32_t);
10567 /* The first few registers have to be read using AQ operations */
10569 while (i40e_regs_adminq[reg_idx].name) {
10570 reg_info = &i40e_regs_adminq[reg_idx++];
10571 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10573 arr_idx2 <= reg_info->count2;
10575 reg_offset = arr_idx * reg_info->stride1 +
10576 arr_idx2 * reg_info->stride2;
10577 reg_offset += reg_info->base_addr;
10578 ptr_data[reg_offset >> 2] =
10579 i40e_read_rx_ctl(hw, reg_offset);
10583 /* The remaining registers can be read using primitives */
10585 while (i40e_regs_others[reg_idx].name) {
10586 reg_info = &i40e_regs_others[reg_idx++];
10587 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10589 arr_idx2 <= reg_info->count2;
10591 reg_offset = arr_idx * reg_info->stride1 +
10592 arr_idx2 * reg_info->stride2;
10593 reg_offset += reg_info->base_addr;
10594 ptr_data[reg_offset >> 2] =
10595 I40E_READ_REG(hw, reg_offset);
10602 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10606 /* Convert word count to byte count */
10607 return hw->nvm.sr_size << 1;
10610 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10611 struct rte_dev_eeprom_info *eeprom)
10613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10614 uint16_t *data = eeprom->data;
10615 uint16_t offset, length, cnt_words;
10618 offset = eeprom->offset >> 1;
10619 length = eeprom->length >> 1;
10620 cnt_words = length;
10622 if (offset > hw->nvm.sr_size ||
10623 offset + length > hw->nvm.sr_size) {
10624 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10628 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10630 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10631 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10632 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10639 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10640 struct ether_addr *mac_addr)
10642 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10644 if (!is_valid_assigned_ether_addr(mac_addr)) {
10645 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10649 /* Flags: 0x3 updates port address */
10650 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10654 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10656 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10657 struct rte_eth_dev_data *dev_data = pf->dev_data;
10658 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10661 /* check if mtu is within the allowed range */
10662 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10665 /* mtu setting is forbidden if port is start */
10666 if (dev_data->dev_started) {
10667 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10668 dev_data->port_id);
10672 if (frame_size > ETHER_MAX_LEN)
10673 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10675 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10677 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10682 /* Restore ethertype filter */
10684 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10686 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10687 struct i40e_ethertype_filter_list
10688 *ethertype_list = &pf->ethertype.ethertype_list;
10689 struct i40e_ethertype_filter *f;
10690 struct i40e_control_filter_stats stats;
10693 TAILQ_FOREACH(f, ethertype_list, rules) {
10695 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10696 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10697 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10698 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10699 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10701 memset(&stats, 0, sizeof(stats));
10702 i40e_aq_add_rem_control_packet_filter(hw,
10703 f->input.mac_addr.addr_bytes,
10704 f->input.ether_type,
10705 flags, pf->main_vsi->seid,
10706 f->queue, 1, &stats, NULL);
10708 PMD_DRV_LOG(INFO, "Ethertype filter:"
10709 " mac_etype_used = %u, etype_used = %u,"
10710 " mac_etype_free = %u, etype_free = %u",
10711 stats.mac_etype_used, stats.etype_used,
10712 stats.mac_etype_free, stats.etype_free);
10715 /* Restore tunnel filter */
10717 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10719 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10720 struct i40e_vsi *vsi;
10721 struct i40e_pf_vf *vf;
10722 struct i40e_tunnel_filter_list
10723 *tunnel_list = &pf->tunnel.tunnel_list;
10724 struct i40e_tunnel_filter *f;
10725 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10726 bool big_buffer = 0;
10728 TAILQ_FOREACH(f, tunnel_list, rules) {
10730 vsi = pf->main_vsi;
10732 vf = &pf->vfs[f->vf_id];
10735 memset(&cld_filter, 0, sizeof(cld_filter));
10736 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10737 (struct ether_addr *)&cld_filter.element.outer_mac);
10738 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10739 (struct ether_addr *)&cld_filter.element.inner_mac);
10740 cld_filter.element.inner_vlan = f->input.inner_vlan;
10741 cld_filter.element.flags = f->input.flags;
10742 cld_filter.element.tenant_id = f->input.tenant_id;
10743 cld_filter.element.queue_number = f->queue;
10744 rte_memcpy(cld_filter.general_fields,
10745 f->input.general_fields,
10746 sizeof(f->input.general_fields));
10748 if (((f->input.flags &
10749 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10750 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10752 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10753 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10755 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10756 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10760 i40e_aq_add_cloud_filters_big_buffer(hw,
10761 vsi->seid, &cld_filter, 1);
10763 i40e_aq_add_cloud_filters(hw, vsi->seid,
10764 &cld_filter.element, 1);
10769 i40e_filter_restore(struct i40e_pf *pf)
10771 i40e_ethertype_filter_restore(pf);
10772 i40e_tunnel_filter_restore(pf);
10773 i40e_fdir_filter_restore(pf);
10777 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10779 if (strcmp(dev->device->driver->name, drv->driver.name))
10786 is_i40e_supported(struct rte_eth_dev *dev)
10788 return is_device_supported(dev, &rte_i40e_pmd);
10791 struct i40e_customized_pctype*
10792 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10796 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10797 if (pf->customized_pctype[i].index == index)
10798 return &pf->customized_pctype[i];
10804 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10805 uint32_t pkg_size, uint32_t proto_num,
10806 struct rte_pmd_i40e_proto_info *proto)
10808 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10809 uint32_t pctype_num;
10810 struct rte_pmd_i40e_ptype_info *pctype;
10811 uint32_t buff_size;
10812 struct i40e_customized_pctype *new_pctype = NULL;
10814 uint8_t pctype_value;
10819 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10820 (uint8_t *)&pctype_num, sizeof(pctype_num),
10821 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10823 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10827 PMD_DRV_LOG(INFO, "No new pctype added");
10831 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
10832 pctype = rte_zmalloc("new_pctype", buff_size, 0);
10834 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10837 /* get information about new pctype list */
10838 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10839 (uint8_t *)pctype, buff_size,
10840 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
10842 PMD_DRV_LOG(ERR, "Failed to get pctype list");
10847 /* Update customized pctype. */
10848 for (i = 0; i < pctype_num; i++) {
10849 pctype_value = pctype[i].ptype_id;
10850 memset(name, 0, sizeof(name));
10851 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
10852 proto_id = pctype[i].protocols[j];
10853 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
10855 for (n = 0; n < proto_num; n++) {
10856 if (proto[n].proto_id != proto_id)
10858 strcat(name, proto[n].name);
10863 name[strlen(name) - 1] = '\0';
10864 if (!strcmp(name, "GTPC"))
10866 i40e_find_customized_pctype(pf,
10867 I40E_CUSTOMIZED_GTPC);
10868 else if (!strcmp(name, "GTPU_IPV4"))
10870 i40e_find_customized_pctype(pf,
10871 I40E_CUSTOMIZED_GTPU_IPV4);
10872 else if (!strcmp(name, "GTPU_IPV6"))
10874 i40e_find_customized_pctype(pf,
10875 I40E_CUSTOMIZED_GTPU_IPV6);
10876 else if (!strcmp(name, "GTPU"))
10878 i40e_find_customized_pctype(pf,
10879 I40E_CUSTOMIZED_GTPU);
10881 new_pctype->pctype = pctype_value;
10882 new_pctype->valid = true;
10891 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
10892 uint32_t pkg_size, uint32_t proto_num,
10893 struct rte_pmd_i40e_proto_info *proto)
10895 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
10896 uint8_t port_id = dev->data->port_id;
10897 uint32_t ptype_num;
10898 struct rte_pmd_i40e_ptype_info *ptype;
10899 uint32_t buff_size;
10906 /* get information about new ptype num */
10907 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10908 (uint8_t *)&ptype_num, sizeof(ptype_num),
10909 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
10911 PMD_DRV_LOG(ERR, "Failed to get ptype number");
10915 PMD_DRV_LOG(INFO, "No new ptype added");
10919 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
10920 ptype = rte_zmalloc("new_ptype", buff_size, 0);
10922 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10926 /* get information about new ptype list */
10927 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10928 (uint8_t *)ptype, buff_size,
10929 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
10931 PMD_DRV_LOG(ERR, "Failed to get ptype list");
10936 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
10937 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
10938 if (!ptype_mapping) {
10939 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10944 /* Update ptype mapping table. */
10945 for (i = 0; i < ptype_num; i++) {
10946 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
10947 ptype_mapping[i].sw_ptype = 0;
10949 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
10950 proto_id = ptype[i].protocols[j];
10951 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
10953 for (n = 0; n < proto_num; n++) {
10954 if (proto[n].proto_id != proto_id)
10956 memset(name, 0, sizeof(name));
10957 strcpy(name, proto[n].name);
10958 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
10959 ptype_mapping[i].sw_ptype |=
10960 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
10962 } else if (!strncmp(name, "IPV4", 4) &&
10964 ptype_mapping[i].sw_ptype |=
10965 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
10966 } else if (!strncmp(name, "IPV6", 4) &&
10968 ptype_mapping[i].sw_ptype |=
10969 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
10971 } else if (!strncmp(name, "IPV6", 4) &&
10973 ptype_mapping[i].sw_ptype |=
10974 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
10975 } else if (!strncmp(name, "IPV4FRAG", 8)) {
10976 ptype_mapping[i].sw_ptype |=
10977 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
10978 ptype_mapping[i].sw_ptype |=
10979 RTE_PTYPE_INNER_L4_FRAG;
10980 } else if (!strncmp(name, "IPV6FRAG", 8)) {
10981 ptype_mapping[i].sw_ptype |=
10982 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
10983 ptype_mapping[i].sw_ptype |=
10984 RTE_PTYPE_INNER_L4_FRAG;
10985 } else if (!strncmp(name, "GTPC", 4))
10986 ptype_mapping[i].sw_ptype |=
10987 RTE_PTYPE_TUNNEL_GTPC;
10988 else if (!strncmp(name, "GTPU", 4))
10989 ptype_mapping[i].sw_ptype |=
10990 RTE_PTYPE_TUNNEL_GTPU;
10991 else if (!strncmp(name, "UDP", 3))
10992 ptype_mapping[i].sw_ptype |=
10993 RTE_PTYPE_INNER_L4_UDP;
10994 else if (!strncmp(name, "TCP", 3))
10995 ptype_mapping[i].sw_ptype |=
10996 RTE_PTYPE_INNER_L4_TCP;
10997 else if (!strncmp(name, "SCTP", 4))
10998 ptype_mapping[i].sw_ptype |=
10999 RTE_PTYPE_INNER_L4_SCTP;
11000 else if (!strncmp(name, "ICMP", 4) ||
11001 !strncmp(name, "ICMPV6", 6))
11002 ptype_mapping[i].sw_ptype |=
11003 RTE_PTYPE_INNER_L4_ICMP;
11010 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11013 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11015 rte_free(ptype_mapping);
11021 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11024 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11025 uint32_t proto_num;
11026 struct rte_pmd_i40e_proto_info *proto;
11027 uint32_t buff_size;
11031 /* get information about protocol number */
11032 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11033 (uint8_t *)&proto_num, sizeof(proto_num),
11034 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11036 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11040 PMD_DRV_LOG(INFO, "No new protocol added");
11044 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11045 proto = rte_zmalloc("new_proto", buff_size, 0);
11047 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11051 /* get information about protocol list */
11052 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11053 (uint8_t *)proto, buff_size,
11054 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11056 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11061 /* Check if GTP is supported. */
11062 for (i = 0; i < proto_num; i++) {
11063 if (!strncmp(proto[i].name, "GTP", 3)) {
11064 pf->gtp_support = true;
11069 /* Update customized pctype info */
11070 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11073 PMD_DRV_LOG(INFO, "No pctype is updated.");
11075 /* Update customized ptype info */
11076 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11079 PMD_DRV_LOG(INFO, "No ptype is updated.");
11084 /* Create a QinQ cloud filter
11086 * The Fortville NIC has limited resources for tunnel filters,
11087 * so we can only reuse existing filters.
11089 * In step 1 we define which Field Vector fields can be used for
11091 * As we do not have the inner tag defined as a field,
11092 * we have to define it first, by reusing one of L1 entries.
11094 * In step 2 we are replacing one of existing filter types with
11095 * a new one for QinQ.
11096 * As we reusing L1 and replacing L2, some of the default filter
11097 * types will disappear,which depends on L1 and L2 entries we reuse.
11099 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11101 * 1. Create L1 filter of outer vlan (12b) which will be in use
11102 * later when we define the cloud filter.
11103 * a. Valid_flags.replace_cloud = 0
11104 * b. Old_filter = 10 (Stag_Inner_Vlan)
11105 * c. New_filter = 0x10
11106 * d. TR bit = 0xff (optional, not used here)
11107 * e. Buffer – 2 entries:
11108 * i. Byte 0 = 8 (outer vlan FV index).
11110 * Byte 2-3 = 0x0fff
11111 * ii. Byte 0 = 37 (inner vlan FV index).
11113 * Byte 2-3 = 0x0fff
11116 * 2. Create cloud filter using two L1 filters entries: stag and
11117 * new filter(outer vlan+ inner vlan)
11118 * a. Valid_flags.replace_cloud = 1
11119 * b. Old_filter = 1 (instead of outer IP)
11120 * c. New_filter = 0x10
11121 * d. Buffer – 2 entries:
11122 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11123 * Byte 1-3 = 0 (rsv)
11124 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11125 * Byte 9-11 = 0 (rsv)
11128 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11130 int ret = -ENOTSUP;
11131 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11132 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11133 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11136 memset(&filter_replace, 0,
11137 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11138 memset(&filter_replace_buf, 0,
11139 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11141 /* create L1 filter */
11142 filter_replace.old_filter_type =
11143 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11144 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
11145 filter_replace.tr_bit = 0;
11147 /* Prepare the buffer, 2 entries */
11148 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11149 filter_replace_buf.data[0] |=
11150 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11151 /* Field Vector 12b mask */
11152 filter_replace_buf.data[2] = 0xff;
11153 filter_replace_buf.data[3] = 0x0f;
11154 filter_replace_buf.data[4] =
11155 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11156 filter_replace_buf.data[4] |=
11157 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11158 /* Field Vector 12b mask */
11159 filter_replace_buf.data[6] = 0xff;
11160 filter_replace_buf.data[7] = 0x0f;
11161 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11162 &filter_replace_buf);
11163 if (ret != I40E_SUCCESS)
11166 /* Apply the second L2 cloud filter */
11167 memset(&filter_replace, 0,
11168 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11169 memset(&filter_replace_buf, 0,
11170 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11172 /* create L2 filter, input for L2 filter will be L1 filter */
11173 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11174 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11175 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
11177 /* Prepare the buffer, 2 entries */
11178 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11179 filter_replace_buf.data[0] |=
11180 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11181 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
11182 filter_replace_buf.data[4] |=
11183 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11184 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11185 &filter_replace_buf);
11189 RTE_INIT(i40e_init_log);
11191 i40e_init_log(void)
11193 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11194 if (i40e_logtype_init >= 0)
11195 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11196 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11197 if (i40e_logtype_driver >= 0)
11198 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);