4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 /* The max bandwidth of i40e is 40Gbps. */
247 #define I40E_QOS_BW_MAX 40000
248 /* The bandwidth should be the multiple of 50Mbps. */
249 #define I40E_QOS_BW_GRANULARITY 50
250 /* The min bandwidth weight is 1. */
251 #define I40E_QOS_BW_WEIGHT_MIN 1
252 /* The max bandwidth weight is 127. */
253 #define I40E_QOS_BW_WEIGHT_MAX 127
255 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
256 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
257 static int i40e_dev_configure(struct rte_eth_dev *dev);
258 static int i40e_dev_start(struct rte_eth_dev *dev);
259 static void i40e_dev_stop(struct rte_eth_dev *dev);
260 static void i40e_dev_close(struct rte_eth_dev *dev);
261 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
262 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
263 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
264 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
265 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
266 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
267 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
268 struct rte_eth_stats *stats);
269 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
270 struct rte_eth_xstat *xstats, unsigned n);
271 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
272 struct rte_eth_xstat_name *xstats_names,
274 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
275 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
279 static int i40e_fw_version_get(struct rte_eth_dev *dev,
280 char *fw_version, size_t fw_size);
281 static void i40e_dev_info_get(struct rte_eth_dev *dev,
282 struct rte_eth_dev_info *dev_info);
283 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
286 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
287 enum rte_vlan_type vlan_type,
289 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
290 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
293 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
294 static int i40e_dev_led_on(struct rte_eth_dev *dev);
295 static int i40e_dev_led_off(struct rte_eth_dev *dev);
296 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
297 struct rte_eth_fc_conf *fc_conf);
298 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
299 struct rte_eth_fc_conf *fc_conf);
300 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
301 struct rte_eth_pfc_conf *pfc_conf);
302 static void i40e_macaddr_add(struct rte_eth_dev *dev,
303 struct ether_addr *mac_addr,
306 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
307 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
308 struct rte_eth_rss_reta_entry64 *reta_conf,
310 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
311 struct rte_eth_rss_reta_entry64 *reta_conf,
314 static int i40e_get_cap(struct i40e_hw *hw);
315 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
316 static int i40e_pf_setup(struct i40e_pf *pf);
317 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
318 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
319 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
320 static int i40e_dcb_setup(struct rte_eth_dev *dev);
321 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
322 bool offset_loaded, uint64_t *offset, uint64_t *stat);
323 static void i40e_stat_update_48(struct i40e_hw *hw,
329 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
330 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
332 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
333 uint32_t base, uint32_t num);
334 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
335 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
337 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
339 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
340 static int i40e_veb_release(struct i40e_veb *veb);
341 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
342 struct i40e_vsi *vsi);
343 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
344 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
345 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
346 struct i40e_macvlan_filter *mv_f,
348 struct ether_addr *addr);
349 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
350 struct i40e_macvlan_filter *mv_f,
353 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
354 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
355 struct rte_eth_rss_conf *rss_conf);
356 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
357 struct rte_eth_rss_conf *rss_conf);
358 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
359 struct rte_eth_udp_tunnel *udp_tunnel);
360 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
361 struct rte_eth_udp_tunnel *udp_tunnel);
362 static void i40e_filter_input_set_init(struct i40e_pf *pf);
363 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
364 enum rte_filter_op filter_op,
366 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
367 enum rte_filter_type filter_type,
368 enum rte_filter_op filter_op,
370 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
371 struct rte_eth_dcb_info *dcb_info);
372 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
373 static void i40e_configure_registers(struct i40e_hw *hw);
374 static void i40e_hw_init(struct rte_eth_dev *dev);
375 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
376 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
377 struct rte_eth_mirror_conf *mirror_conf,
378 uint8_t sw_id, uint8_t on);
379 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
381 static int i40e_timesync_enable(struct rte_eth_dev *dev);
382 static int i40e_timesync_disable(struct rte_eth_dev *dev);
383 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
384 struct timespec *timestamp,
386 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
387 struct timespec *timestamp);
388 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
390 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
392 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
393 struct timespec *timestamp);
394 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
395 const struct timespec *timestamp);
397 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
399 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
402 static int i40e_get_regs(struct rte_eth_dev *dev,
403 struct rte_dev_reg_info *regs);
405 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
407 static int i40e_get_eeprom(struct rte_eth_dev *dev,
408 struct rte_dev_eeprom_info *eeprom);
410 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
411 struct ether_addr *mac_addr);
413 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
415 static int i40e_ethertype_filter_convert(
416 const struct rte_eth_ethertype_filter *input,
417 struct i40e_ethertype_filter *filter);
418 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
419 struct i40e_ethertype_filter *filter);
421 static int i40e_tunnel_filter_convert(
422 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
423 struct i40e_tunnel_filter *tunnel_filter);
424 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
425 struct i40e_tunnel_filter *tunnel_filter);
427 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
428 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
429 static void i40e_filter_restore(struct i40e_pf *pf);
431 static const struct rte_pci_id pci_id_i40e_map[] = {
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
452 { .vendor_id = 0, /* sentinel */ },
455 static const struct eth_dev_ops i40e_eth_dev_ops = {
456 .dev_configure = i40e_dev_configure,
457 .dev_start = i40e_dev_start,
458 .dev_stop = i40e_dev_stop,
459 .dev_close = i40e_dev_close,
460 .promiscuous_enable = i40e_dev_promiscuous_enable,
461 .promiscuous_disable = i40e_dev_promiscuous_disable,
462 .allmulticast_enable = i40e_dev_allmulticast_enable,
463 .allmulticast_disable = i40e_dev_allmulticast_disable,
464 .dev_set_link_up = i40e_dev_set_link_up,
465 .dev_set_link_down = i40e_dev_set_link_down,
466 .link_update = i40e_dev_link_update,
467 .stats_get = i40e_dev_stats_get,
468 .xstats_get = i40e_dev_xstats_get,
469 .xstats_get_names = i40e_dev_xstats_get_names,
470 .stats_reset = i40e_dev_stats_reset,
471 .xstats_reset = i40e_dev_stats_reset,
472 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
473 .fw_version_get = i40e_fw_version_get,
474 .dev_infos_get = i40e_dev_info_get,
475 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
476 .vlan_filter_set = i40e_vlan_filter_set,
477 .vlan_tpid_set = i40e_vlan_tpid_set,
478 .vlan_offload_set = i40e_vlan_offload_set,
479 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
480 .vlan_pvid_set = i40e_vlan_pvid_set,
481 .rx_queue_start = i40e_dev_rx_queue_start,
482 .rx_queue_stop = i40e_dev_rx_queue_stop,
483 .tx_queue_start = i40e_dev_tx_queue_start,
484 .tx_queue_stop = i40e_dev_tx_queue_stop,
485 .rx_queue_setup = i40e_dev_rx_queue_setup,
486 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
487 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
488 .rx_queue_release = i40e_dev_rx_queue_release,
489 .rx_queue_count = i40e_dev_rx_queue_count,
490 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
491 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
492 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
493 .tx_queue_setup = i40e_dev_tx_queue_setup,
494 .tx_queue_release = i40e_dev_tx_queue_release,
495 .dev_led_on = i40e_dev_led_on,
496 .dev_led_off = i40e_dev_led_off,
497 .flow_ctrl_get = i40e_flow_ctrl_get,
498 .flow_ctrl_set = i40e_flow_ctrl_set,
499 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
500 .mac_addr_add = i40e_macaddr_add,
501 .mac_addr_remove = i40e_macaddr_remove,
502 .reta_update = i40e_dev_rss_reta_update,
503 .reta_query = i40e_dev_rss_reta_query,
504 .rss_hash_update = i40e_dev_rss_hash_update,
505 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
506 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
507 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
508 .filter_ctrl = i40e_dev_filter_ctrl,
509 .rxq_info_get = i40e_rxq_info_get,
510 .txq_info_get = i40e_txq_info_get,
511 .mirror_rule_set = i40e_mirror_rule_set,
512 .mirror_rule_reset = i40e_mirror_rule_reset,
513 .timesync_enable = i40e_timesync_enable,
514 .timesync_disable = i40e_timesync_disable,
515 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
516 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
517 .get_dcb_info = i40e_dev_get_dcb_info,
518 .timesync_adjust_time = i40e_timesync_adjust_time,
519 .timesync_read_time = i40e_timesync_read_time,
520 .timesync_write_time = i40e_timesync_write_time,
521 .get_reg = i40e_get_regs,
522 .get_eeprom_length = i40e_get_eeprom_length,
523 .get_eeprom = i40e_get_eeprom,
524 .mac_addr_set = i40e_set_default_mac_addr,
525 .mtu_set = i40e_dev_mtu_set,
528 /* store statistics names and its offset in stats structure */
529 struct rte_i40e_xstats_name_off {
530 char name[RTE_ETH_XSTATS_NAME_SIZE];
534 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
535 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
536 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
537 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
538 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
539 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
540 rx_unknown_protocol)},
541 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
542 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
543 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
544 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
547 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
548 sizeof(rte_i40e_stats_strings[0]))
550 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
551 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
552 tx_dropped_link_down)},
553 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
554 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
556 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
557 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
559 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
563 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
564 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
565 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
566 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
567 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
568 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
582 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
584 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
585 mac_short_packet_dropped)},
586 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
589 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
590 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
602 {"rx_flow_director_atr_match_packets",
603 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
604 {"rx_flow_director_sb_match_packets",
605 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
606 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
608 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
610 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
617 sizeof(rte_i40e_hw_port_strings[0]))
619 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
620 {"xon_packets", offsetof(struct i40e_hw_port_stats,
622 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
627 sizeof(rte_i40e_rxq_prio_strings[0]))
629 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
630 {"xon_packets", offsetof(struct i40e_hw_port_stats,
632 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
634 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
635 priority_xon_2_xoff)},
638 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
639 sizeof(rte_i40e_txq_prio_strings[0]))
641 static struct eth_driver rte_i40e_pmd = {
643 .id_table = pci_id_i40e_map,
644 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
645 .probe = rte_eth_dev_pci_probe,
646 .remove = rte_eth_dev_pci_remove,
648 .eth_dev_init = eth_i40e_dev_init,
649 .eth_dev_uninit = eth_i40e_dev_uninit,
650 .dev_private_size = sizeof(struct i40e_adapter),
654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
655 struct rte_eth_link *link)
657 struct rte_eth_link *dst = link;
658 struct rte_eth_link *src = &(dev->data->dev_link);
660 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
661 *(uint64_t *)src) == 0)
668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
669 struct rte_eth_link *link)
671 struct rte_eth_link *dst = &(dev->data->dev_link);
672 struct rte_eth_link *src = link;
674 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
675 *(uint64_t *)src) == 0)
681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
685 #ifndef I40E_GLQF_ORT
686 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
688 #ifndef I40E_GLQF_PIT
689 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
691 #ifndef I40E_GLQF_L3_MAP
692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
698 * Initialize registers for flexible payload, which should be set by NVM.
699 * This should be removed from code once it is fixed in NVM.
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
711 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
712 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
714 /* Initialize registers for parsing packet type of QinQ */
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
716 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
719 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
722 * Add a ethertype filter to drop all flow control frames transmitted
726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
728 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
729 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
731 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
734 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
735 I40E_FLOW_CONTROL_ETHERTYPE, flags,
736 pf->main_vsi_seid, 0,
740 "Failed to add filter to drop flow control frames from VSIs.");
744 floating_veb_list_handler(__rte_unused const char *key,
745 const char *floating_veb_value,
749 unsigned int count = 0;
752 bool *vf_floating_veb = opaque;
754 while (isblank(*floating_veb_value))
755 floating_veb_value++;
757 /* Reset floating VEB configuration for VFs */
758 for (idx = 0; idx < I40E_MAX_VF; idx++)
759 vf_floating_veb[idx] = false;
763 while (isblank(*floating_veb_value))
764 floating_veb_value++;
765 if (*floating_veb_value == '\0')
768 idx = strtoul(floating_veb_value, &end, 10);
769 if (errno || end == NULL)
771 while (isblank(*end))
775 } else if ((*end == ';') || (*end == '\0')) {
777 if (min == I40E_MAX_VF)
779 if (max >= I40E_MAX_VF)
780 max = I40E_MAX_VF - 1;
781 for (idx = min; idx <= max; idx++) {
782 vf_floating_veb[idx] = true;
789 floating_veb_value = end + 1;
790 } while (*end != '\0');
799 config_vf_floating_veb(struct rte_devargs *devargs,
800 uint16_t floating_veb,
801 bool *vf_floating_veb)
803 struct rte_kvargs *kvlist;
805 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
809 /* All the VFs attach to the floating VEB by default
810 * when the floating VEB is enabled.
812 for (i = 0; i < I40E_MAX_VF; i++)
813 vf_floating_veb[i] = true;
818 kvlist = rte_kvargs_parse(devargs->args, NULL);
822 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
823 rte_kvargs_free(kvlist);
826 /* When the floating_veb_list parameter exists, all the VFs
827 * will attach to the legacy VEB firstly, then configure VFs
828 * to the floating VEB according to the floating_veb_list.
830 if (rte_kvargs_process(kvlist, floating_veb_list,
831 floating_veb_list_handler,
832 vf_floating_veb) < 0) {
833 rte_kvargs_free(kvlist);
836 rte_kvargs_free(kvlist);
840 i40e_check_floating_handler(__rte_unused const char *key,
842 __rte_unused void *opaque)
844 if (strcmp(value, "1"))
851 is_floating_veb_supported(struct rte_devargs *devargs)
853 struct rte_kvargs *kvlist;
854 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
859 kvlist = rte_kvargs_parse(devargs->args, NULL);
863 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
864 rte_kvargs_free(kvlist);
867 /* Floating VEB is enabled when there's key-value:
868 * enable_floating_veb=1
870 if (rte_kvargs_process(kvlist, floating_veb_key,
871 i40e_check_floating_handler, NULL) < 0) {
872 rte_kvargs_free(kvlist);
875 rte_kvargs_free(kvlist);
881 config_floating_veb(struct rte_eth_dev *dev)
883 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
884 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
887 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
889 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
891 is_floating_veb_supported(pci_dev->device.devargs);
892 config_vf_floating_veb(pci_dev->device.devargs,
894 pf->floating_veb_list);
896 pf->floating_veb = false;
900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
907 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
908 char ethertype_hash_name[RTE_HASH_NAMESIZE];
911 struct rte_hash_parameters ethertype_hash_params = {
912 .name = ethertype_hash_name,
913 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
914 .key_len = sizeof(struct i40e_ethertype_filter_input),
915 .hash_func = rte_hash_crc,
916 .hash_func_init_val = 0,
917 .socket_id = rte_socket_id(),
920 /* Initialize ethertype filter rule list and hash */
921 TAILQ_INIT(ðertype_rule->ethertype_list);
922 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
923 "ethertype_%s", dev->data->name);
924 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
925 if (!ethertype_rule->hash_table) {
926 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
929 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
930 sizeof(struct i40e_ethertype_filter *) *
931 I40E_MAX_ETHERTYPE_FILTER_NUM,
933 if (!ethertype_rule->hash_map) {
935 "Failed to allocate memory for ethertype hash map!");
937 goto err_ethertype_hash_map_alloc;
942 err_ethertype_hash_map_alloc:
943 rte_hash_free(ethertype_rule->hash_table);
949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
952 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
953 char tunnel_hash_name[RTE_HASH_NAMESIZE];
956 struct rte_hash_parameters tunnel_hash_params = {
957 .name = tunnel_hash_name,
958 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
959 .key_len = sizeof(struct i40e_tunnel_filter_input),
960 .hash_func = rte_hash_crc,
961 .hash_func_init_val = 0,
962 .socket_id = rte_socket_id(),
965 /* Initialize tunnel filter rule list and hash */
966 TAILQ_INIT(&tunnel_rule->tunnel_list);
967 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
968 "tunnel_%s", dev->data->name);
969 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
970 if (!tunnel_rule->hash_table) {
971 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
974 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
975 sizeof(struct i40e_tunnel_filter *) *
976 I40E_MAX_TUNNEL_FILTER_NUM,
978 if (!tunnel_rule->hash_map) {
980 "Failed to allocate memory for tunnel hash map!");
982 goto err_tunnel_hash_map_alloc;
987 err_tunnel_hash_map_alloc:
988 rte_hash_free(tunnel_rule->hash_table);
994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
997 struct i40e_fdir_info *fdir_info = &pf->fdir;
998 char fdir_hash_name[RTE_HASH_NAMESIZE];
1001 struct rte_hash_parameters fdir_hash_params = {
1002 .name = fdir_hash_name,
1003 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004 .key_len = sizeof(struct rte_eth_fdir_input),
1005 .hash_func = rte_hash_crc,
1006 .hash_func_init_val = 0,
1007 .socket_id = rte_socket_id(),
1010 /* Initialize flow director filter rule list and hash */
1011 TAILQ_INIT(&fdir_info->fdir_list);
1012 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013 "fdir_%s", dev->data->name);
1014 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015 if (!fdir_info->hash_table) {
1016 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1019 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020 sizeof(struct i40e_fdir_filter *) *
1021 I40E_MAX_FDIR_FILTER_NUM,
1023 if (!fdir_info->hash_map) {
1025 "Failed to allocate memory for fdir hash map!");
1027 goto err_fdir_hash_map_alloc;
1031 err_fdir_hash_map_alloc:
1032 rte_hash_free(fdir_info->hash_table);
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1040 struct rte_pci_device *pci_dev;
1041 struct rte_intr_handle *intr_handle;
1042 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044 struct i40e_vsi *vsi;
1047 uint8_t aq_fail = 0;
1049 PMD_INIT_FUNC_TRACE();
1051 dev->dev_ops = &i40e_eth_dev_ops;
1052 dev->rx_pkt_burst = i40e_recv_pkts;
1053 dev->tx_pkt_burst = i40e_xmit_pkts;
1054 dev->tx_pkt_prepare = i40e_prep_pkts;
1056 /* for secondary processes, we don't initialise any further as primary
1057 * has already done this work. Only check we don't need a different
1059 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060 i40e_set_rx_function(dev);
1061 i40e_set_tx_function(dev);
1064 pci_dev = I40E_DEV_TO_PCI(dev);
1065 intr_handle = &pci_dev->intr_handle;
1067 rte_eth_copy_pci_info(dev, pci_dev);
1068 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071 pf->adapter->eth_dev = dev;
1072 pf->dev_data = dev->data;
1074 hw->back = I40E_PF_TO_ADAPTER(pf);
1075 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1078 "Hardware is not available, as address is NULL");
1082 hw->vendor_id = pci_dev->id.vendor_id;
1083 hw->device_id = pci_dev->id.device_id;
1084 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086 hw->bus.device = pci_dev->addr.devid;
1087 hw->bus.func = pci_dev->addr.function;
1088 hw->adapter_stopped = 0;
1090 /* Make sure all is clean before doing PF reset */
1093 /* Initialize the hardware */
1096 /* Reset here to make sure all is clean for each PF */
1097 ret = i40e_pf_reset(hw);
1099 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103 /* Initialize the shared code (base driver) */
1104 ret = i40e_init_shared_code(hw);
1106 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1111 * To work around the NVM issue, initialize registers
1112 * for flexible payload and packet type of QinQ by
1113 * software. It should be removed once issues are fixed
1116 i40e_GLQF_reg_init(hw);
1118 /* Initialize the input set for filters (hash and fd) to default value */
1119 i40e_filter_input_set_init(pf);
1121 /* Initialize the parameters for adminq */
1122 i40e_init_adminq_parameter(hw);
1123 ret = i40e_init_adminq(hw);
1124 if (ret != I40E_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1128 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131 ((hw->nvm.version >> 12) & 0xf),
1132 ((hw->nvm.version >> 4) & 0xff),
1133 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135 /* initialise the L3_MAP register */
1136 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1139 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141 /* Need the special FW version to support floating VEB */
1142 config_floating_veb(dev);
1143 /* Clear PXE mode */
1144 i40e_clear_pxe_mode(hw);
1145 ret = i40e_dev_sync_phy_type(hw);
1147 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1148 goto err_sync_phy_type;
1151 * On X710, performance number is far from the expectation on recent
1152 * firmware versions. The fix for this issue may not be integrated in
1153 * the following firmware version. So the workaround in software driver
1154 * is needed. It needs to modify the initial values of 3 internal only
1155 * registers. Note that the workaround can be removed when it is fixed
1156 * in firmware in the future.
1158 i40e_configure_registers(hw);
1160 /* Get hw capabilities */
1161 ret = i40e_get_cap(hw);
1162 if (ret != I40E_SUCCESS) {
1163 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164 goto err_get_capabilities;
1167 /* Initialize parameters for PF */
1168 ret = i40e_pf_parameter_init(dev);
1170 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171 goto err_parameter_init;
1174 /* Initialize the queue management */
1175 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1177 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178 goto err_qp_pool_init;
1180 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181 hw->func_caps.num_msix_vectors - 1);
1183 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184 goto err_msix_pool_init;
1187 /* Initialize lan hmc */
1188 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189 hw->func_caps.num_rx_qp, 0, 0);
1190 if (ret != I40E_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192 goto err_init_lan_hmc;
1195 /* Configure lan hmc */
1196 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197 if (ret != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199 goto err_configure_lan_hmc;
1202 /* Get and check the mac address */
1203 i40e_get_mac_addr(hw, hw->mac.addr);
1204 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "mac address is not valid");
1207 goto err_get_mac_addr;
1209 /* Copy the permanent MAC address */
1210 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211 (struct ether_addr *) hw->mac.perm_addr);
1213 /* Disable flow control */
1214 hw->fc.requested_mode = I40E_FC_NONE;
1215 i40e_set_fc(hw, &aq_fail, TRUE);
1217 /* Set the global registers with default ether type value */
1218 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219 if (ret != I40E_SUCCESS) {
1221 "Failed to set the default outer VLAN ether type");
1222 goto err_setup_pf_switch;
1225 /* PF setup, which includes VSI setup */
1226 ret = i40e_pf_setup(pf);
1228 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229 goto err_setup_pf_switch;
1232 /* reset all stats of the device, including pf and main vsi */
1233 i40e_dev_stats_reset(dev);
1237 /* Disable double vlan by default */
1238 i40e_vsi_config_double_vlan(vsi, FALSE);
1240 /* Disable S-TAG identification when floating_veb is disabled */
1241 if (!pf->floating_veb) {
1242 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249 if (!vsi->max_macaddrs)
1250 len = ETHER_ADDR_LEN;
1252 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1254 /* Should be after VSI initialized */
1255 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256 if (!dev->data->mac_addrs) {
1258 "Failed to allocated memory for storing mac address");
1261 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262 &dev->data->mac_addrs[0]);
1264 /* Init dcb to sw mode by default */
1265 ret = i40e_dcb_init_configure(dev, TRUE);
1266 if (ret != I40E_SUCCESS) {
1267 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268 pf->flags &= ~I40E_FLAG_DCB;
1270 /* Update HW struct after DCB configuration */
1273 /* initialize pf host driver to setup SRIOV resource if applicable */
1274 i40e_pf_host_init(dev);
1276 /* register callback func to eal lib */
1277 rte_intr_callback_register(intr_handle,
1278 i40e_dev_interrupt_handler, dev);
1280 /* configure and enable device interrupt */
1281 i40e_pf_config_irq0(hw, TRUE);
1282 i40e_pf_enable_irq0(hw);
1284 /* enable uio intr after callback register */
1285 rte_intr_enable(intr_handle);
1287 * Add an ethertype filter to drop all flow control frames transmitted
1288 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1291 i40e_add_tx_flow_control_drop_filter(pf);
1293 /* Set the max frame size to 0x2600 by default,
1294 * in case other drivers changed the default value.
1296 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1298 /* initialize mirror rule list */
1299 TAILQ_INIT(&pf->mirror_list);
1301 ret = i40e_init_ethtype_filter_list(dev);
1303 goto err_init_ethtype_filter_list;
1304 ret = i40e_init_tunnel_filter_list(dev);
1306 goto err_init_tunnel_filter_list;
1307 ret = i40e_init_fdir_filter_list(dev);
1309 goto err_init_fdir_filter_list;
1313 err_init_fdir_filter_list:
1314 rte_free(pf->tunnel.hash_table);
1315 rte_free(pf->tunnel.hash_map);
1316 err_init_tunnel_filter_list:
1317 rte_free(pf->ethertype.hash_table);
1318 rte_free(pf->ethertype.hash_map);
1319 err_init_ethtype_filter_list:
1320 rte_free(dev->data->mac_addrs);
1322 i40e_vsi_release(pf->main_vsi);
1323 err_setup_pf_switch:
1325 err_configure_lan_hmc:
1326 (void)i40e_shutdown_lan_hmc(hw);
1328 i40e_res_pool_destroy(&pf->msix_pool);
1330 i40e_res_pool_destroy(&pf->qp_pool);
1333 err_get_capabilities:
1335 (void)i40e_shutdown_adminq(hw);
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1343 struct i40e_ethertype_filter *p_ethertype;
1344 struct i40e_ethertype_rule *ethertype_rule;
1346 ethertype_rule = &pf->ethertype;
1347 /* Remove all ethertype filter rules and hash */
1348 if (ethertype_rule->hash_map)
1349 rte_free(ethertype_rule->hash_map);
1350 if (ethertype_rule->hash_table)
1351 rte_hash_free(ethertype_rule->hash_table);
1353 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1354 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1355 p_ethertype, rules);
1356 rte_free(p_ethertype);
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1363 struct i40e_tunnel_filter *p_tunnel;
1364 struct i40e_tunnel_rule *tunnel_rule;
1366 tunnel_rule = &pf->tunnel;
1367 /* Remove all tunnel director rules and hash */
1368 if (tunnel_rule->hash_map)
1369 rte_free(tunnel_rule->hash_map);
1370 if (tunnel_rule->hash_table)
1371 rte_hash_free(tunnel_rule->hash_table);
1373 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1382 struct i40e_fdir_filter *p_fdir;
1383 struct i40e_fdir_info *fdir_info;
1385 fdir_info = &pf->fdir;
1386 /* Remove all flow director rules and hash */
1387 if (fdir_info->hash_map)
1388 rte_free(fdir_info->hash_map);
1389 if (fdir_info->hash_table)
1390 rte_hash_free(fdir_info->hash_table);
1392 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 struct rte_pci_device *pci_dev;
1403 struct rte_intr_handle *intr_handle;
1405 struct i40e_filter_control_settings settings;
1406 struct rte_flow *p_flow;
1408 uint8_t aq_fail = 0;
1410 PMD_INIT_FUNC_TRACE();
1412 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 pci_dev = I40E_DEV_TO_PCI(dev);
1418 intr_handle = &pci_dev->intr_handle;
1420 if (hw->adapter_stopped == 0)
1421 i40e_dev_close(dev);
1423 dev->dev_ops = NULL;
1424 dev->rx_pkt_burst = NULL;
1425 dev->tx_pkt_burst = NULL;
1427 /* Clear PXE mode */
1428 i40e_clear_pxe_mode(hw);
1430 /* Unconfigure filter control */
1431 memset(&settings, 0, sizeof(settings));
1432 ret = i40e_set_filter_control(hw, &settings);
1434 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437 /* Disable flow control */
1438 hw->fc.requested_mode = I40E_FC_NONE;
1439 i40e_set_fc(hw, &aq_fail, TRUE);
1441 /* uninitialize pf host driver */
1442 i40e_pf_host_uninit(dev);
1444 rte_free(dev->data->mac_addrs);
1445 dev->data->mac_addrs = NULL;
1447 /* disable uio intr before callback unregister */
1448 rte_intr_disable(intr_handle);
1450 /* register callback func to eal lib */
1451 rte_intr_callback_unregister(intr_handle,
1452 i40e_dev_interrupt_handler, dev);
1454 i40e_rm_ethtype_filter_list(pf);
1455 i40e_rm_tunnel_filter_list(pf);
1456 i40e_rm_fdir_filter_list(pf);
1458 /* Remove all flows */
1459 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1468 i40e_dev_configure(struct rte_eth_dev *dev)
1470 struct i40e_adapter *ad =
1471 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1476 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1477 * bulk allocation or vector Rx preconditions we will reset it.
1479 ad->rx_bulk_alloc_allowed = true;
1480 ad->rx_vec_allowed = true;
1481 ad->tx_simple_allowed = true;
1482 ad->tx_vec_allowed = true;
1484 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1485 ret = i40e_fdir_setup(pf);
1486 if (ret != I40E_SUCCESS) {
1487 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1490 ret = i40e_fdir_configure(dev);
1492 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1496 i40e_fdir_teardown(pf);
1498 ret = i40e_dev_init_vlan(dev);
1503 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1504 * RSS setting have different requirements.
1505 * General PMD driver call sequence are NIC init, configure,
1506 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1507 * will try to lookup the VSI that specific queue belongs to if VMDQ
1508 * applicable. So, VMDQ setting has to be done before
1509 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1510 * For RSS setting, it will try to calculate actual configured RX queue
1511 * number, which will be available after rx_queue_setup(). dev_start()
1512 * function is good to place RSS setup.
1514 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1515 ret = i40e_vmdq_setup(dev);
1520 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1521 ret = i40e_dcb_setup(dev);
1523 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1528 TAILQ_INIT(&pf->flow_list);
1533 /* need to release vmdq resource if exists */
1534 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1535 i40e_vsi_release(pf->vmdq[i].vsi);
1536 pf->vmdq[i].vsi = NULL;
1541 /* need to release fdir resource if exists */
1542 i40e_fdir_teardown(pf);
1547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1549 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1550 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1553 uint16_t msix_vect = vsi->msix_intr;
1556 for (i = 0; i < vsi->nb_qps; i++) {
1557 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1558 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1562 if (vsi->type != I40E_VSI_SRIOV) {
1563 if (!rte_intr_allow_others(intr_handle)) {
1564 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1565 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1567 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1570 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1571 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1573 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1578 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1579 vsi->user_param + (msix_vect - 1);
1581 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1582 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1584 I40E_WRITE_FLUSH(hw);
1588 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1589 int base_queue, int nb_queue)
1593 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1595 /* Bind all RX queues to allocated MSIX interrupt */
1596 for (i = 0; i < nb_queue; i++) {
1597 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1598 I40E_QINT_RQCTL_ITR_INDX_MASK |
1599 ((base_queue + i + 1) <<
1600 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1601 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1602 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1604 if (i == nb_queue - 1)
1605 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1606 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1609 /* Write first RX queue to Link list register as the head element */
1610 if (vsi->type != I40E_VSI_SRIOV) {
1612 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1614 if (msix_vect == I40E_MISC_VEC_ID) {
1615 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1617 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1619 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1621 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1624 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1626 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1628 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1630 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1637 if (msix_vect == I40E_MISC_VEC_ID) {
1639 I40E_VPINT_LNKLST0(vsi->user_param),
1641 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1643 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1645 /* num_msix_vectors_vf needs to minus irq0 */
1646 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1647 vsi->user_param + (msix_vect - 1);
1649 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1651 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1653 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1657 I40E_WRITE_FLUSH(hw);
1661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1663 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1664 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1665 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1666 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1667 uint16_t msix_vect = vsi->msix_intr;
1668 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1669 uint16_t queue_idx = 0;
1674 for (i = 0; i < vsi->nb_qps; i++) {
1675 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1676 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1679 /* INTENA flag is not auto-cleared for interrupt */
1680 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1681 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1682 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1683 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1684 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1686 /* VF bind interrupt */
1687 if (vsi->type == I40E_VSI_SRIOV) {
1688 __vsi_queues_bind_intr(vsi, msix_vect,
1689 vsi->base_queue, vsi->nb_qps);
1693 /* PF & VMDq bind interrupt */
1694 if (rte_intr_dp_is_en(intr_handle)) {
1695 if (vsi->type == I40E_VSI_MAIN) {
1698 } else if (vsi->type == I40E_VSI_VMDQ2) {
1699 struct i40e_vsi *main_vsi =
1700 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1701 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1706 for (i = 0; i < vsi->nb_used_qps; i++) {
1708 if (!rte_intr_allow_others(intr_handle))
1709 /* allow to share MISC_VEC_ID */
1710 msix_vect = I40E_MISC_VEC_ID;
1712 /* no enough msix_vect, map all to one */
1713 __vsi_queues_bind_intr(vsi, msix_vect,
1714 vsi->base_queue + i,
1715 vsi->nb_used_qps - i);
1716 for (; !!record && i < vsi->nb_used_qps; i++)
1717 intr_handle->intr_vec[queue_idx + i] =
1721 /* 1:1 queue/msix_vect mapping */
1722 __vsi_queues_bind_intr(vsi, msix_vect,
1723 vsi->base_queue + i, 1);
1725 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1735 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1736 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1737 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1738 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1739 uint16_t interval = i40e_calc_itr_interval(\
1740 RTE_LIBRTE_I40E_ITR_INTERVAL);
1741 uint16_t msix_intr, i;
1743 if (rte_intr_allow_others(intr_handle))
1744 for (i = 0; i < vsi->nb_msix; i++) {
1745 msix_intr = vsi->msix_intr + i;
1746 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1747 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1748 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1749 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1751 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1754 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1755 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1756 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1757 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1759 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1761 I40E_WRITE_FLUSH(hw);
1765 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1767 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771 uint16_t msix_intr, i;
1773 if (rte_intr_allow_others(intr_handle))
1774 for (i = 0; i < vsi->nb_msix; i++) {
1775 msix_intr = vsi->msix_intr + i;
1776 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1780 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1782 I40E_WRITE_FLUSH(hw);
1785 static inline uint8_t
1786 i40e_parse_link_speeds(uint16_t link_speeds)
1788 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1790 if (link_speeds & ETH_LINK_SPEED_40G)
1791 link_speed |= I40E_LINK_SPEED_40GB;
1792 if (link_speeds & ETH_LINK_SPEED_25G)
1793 link_speed |= I40E_LINK_SPEED_25GB;
1794 if (link_speeds & ETH_LINK_SPEED_20G)
1795 link_speed |= I40E_LINK_SPEED_20GB;
1796 if (link_speeds & ETH_LINK_SPEED_10G)
1797 link_speed |= I40E_LINK_SPEED_10GB;
1798 if (link_speeds & ETH_LINK_SPEED_1G)
1799 link_speed |= I40E_LINK_SPEED_1GB;
1800 if (link_speeds & ETH_LINK_SPEED_100M)
1801 link_speed |= I40E_LINK_SPEED_100MB;
1807 i40e_phy_conf_link(struct i40e_hw *hw,
1809 uint8_t force_speed)
1811 enum i40e_status_code status;
1812 struct i40e_aq_get_phy_abilities_resp phy_ab;
1813 struct i40e_aq_set_phy_config phy_conf;
1814 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1815 I40E_AQ_PHY_FLAG_PAUSE_RX |
1816 I40E_AQ_PHY_FLAG_PAUSE_RX |
1817 I40E_AQ_PHY_FLAG_LOW_POWER;
1818 const uint8_t advt = I40E_LINK_SPEED_40GB |
1819 I40E_LINK_SPEED_25GB |
1820 I40E_LINK_SPEED_10GB |
1821 I40E_LINK_SPEED_1GB |
1822 I40E_LINK_SPEED_100MB;
1826 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1831 memset(&phy_conf, 0, sizeof(phy_conf));
1833 /* bits 0-2 use the values from get_phy_abilities_resp */
1835 abilities |= phy_ab.abilities & mask;
1837 /* update ablities and speed */
1838 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1839 phy_conf.link_speed = advt;
1841 phy_conf.link_speed = force_speed;
1843 phy_conf.abilities = abilities;
1845 /* use get_phy_abilities_resp value for the rest */
1846 phy_conf.phy_type = phy_ab.phy_type;
1847 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1848 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1849 phy_conf.eee_capability = phy_ab.eee_capability;
1850 phy_conf.eeer = phy_ab.eeer_val;
1851 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1853 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1854 phy_ab.abilities, phy_ab.link_speed);
1855 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1856 phy_conf.abilities, phy_conf.link_speed);
1858 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1862 return I40E_SUCCESS;
1866 i40e_apply_link_speed(struct rte_eth_dev *dev)
1869 uint8_t abilities = 0;
1870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 struct rte_eth_conf *conf = &dev->data->dev_conf;
1873 speed = i40e_parse_link_speeds(conf->link_speeds);
1874 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1875 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1876 abilities |= I40E_AQ_PHY_AN_ENABLED;
1877 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1879 /* Skip changing speed on 40G interfaces, FW does not support */
1880 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1881 speed = I40E_LINK_SPEED_UNKNOWN;
1882 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885 return i40e_phy_conf_link(hw, abilities, speed);
1889 i40e_dev_start(struct rte_eth_dev *dev)
1891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893 struct i40e_vsi *main_vsi = pf->main_vsi;
1895 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1896 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897 uint32_t intr_vector = 0;
1898 struct i40e_vsi *vsi;
1900 hw->adapter_stopped = 0;
1902 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1903 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1904 dev->data->port_id);
1908 rte_intr_disable(intr_handle);
1910 if ((rte_intr_cap_multiple(intr_handle) ||
1911 !RTE_ETH_DEV_SRIOV(dev).active) &&
1912 dev->data->dev_conf.intr_conf.rxq != 0) {
1913 intr_vector = dev->data->nb_rx_queues;
1914 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1919 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1920 intr_handle->intr_vec =
1921 rte_zmalloc("intr_vec",
1922 dev->data->nb_rx_queues * sizeof(int),
1924 if (!intr_handle->intr_vec) {
1926 "Failed to allocate %d rx_queues intr_vec",
1927 dev->data->nb_rx_queues);
1932 /* Initialize VSI */
1933 ret = i40e_dev_rxtx_init(pf);
1934 if (ret != I40E_SUCCESS) {
1935 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1939 /* Map queues with MSIX interrupt */
1940 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1941 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1942 i40e_vsi_queues_bind_intr(main_vsi);
1943 i40e_vsi_enable_queues_intr(main_vsi);
1945 /* Map VMDQ VSI queues with MSIX interrupt */
1946 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1947 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1948 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1949 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1952 /* enable FDIR MSIX interrupt */
1953 if (pf->fdir.fdir_vsi) {
1954 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1955 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1958 /* Enable all queues which have been configured */
1959 ret = i40e_dev_switch_queues(pf, TRUE);
1960 if (ret != I40E_SUCCESS) {
1961 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1965 /* Enable receiving broadcast packets */
1966 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1967 if (ret != I40E_SUCCESS)
1968 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1970 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1973 if (ret != I40E_SUCCESS)
1974 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977 /* Enable the VLAN promiscuous mode. */
1979 for (i = 0; i < pf->vf_num; i++) {
1980 vsi = pf->vfs[i].vsi;
1981 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1986 /* Apply link configure */
1987 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1988 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1989 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1990 ETH_LINK_SPEED_40G)) {
1991 PMD_DRV_LOG(ERR, "Invalid link setting");
1994 ret = i40e_apply_link_speed(dev);
1995 if (I40E_SUCCESS != ret) {
1996 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2000 if (!rte_intr_allow_others(intr_handle)) {
2001 rte_intr_callback_unregister(intr_handle,
2002 i40e_dev_interrupt_handler,
2004 /* configure and enable device interrupt */
2005 i40e_pf_config_irq0(hw, FALSE);
2006 i40e_pf_enable_irq0(hw);
2008 if (dev->data->dev_conf.intr_conf.lsc != 0)
2010 "lsc won't enable because of no intr multiplex");
2011 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2012 ret = i40e_aq_set_phy_int_mask(hw,
2013 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2014 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2015 I40E_AQ_EVENT_MEDIA_NA), NULL);
2016 if (ret != I40E_SUCCESS)
2017 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2019 /* Call get_link_info aq commond to enable LSE */
2020 i40e_dev_link_update(dev, 0);
2023 /* enable uio intr after callback register */
2024 rte_intr_enable(intr_handle);
2026 i40e_filter_restore(pf);
2028 return I40E_SUCCESS;
2031 i40e_dev_switch_queues(pf, FALSE);
2032 i40e_dev_clear_queues(dev);
2038 i40e_dev_stop(struct rte_eth_dev *dev)
2040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2041 struct i40e_vsi *main_vsi = pf->main_vsi;
2042 struct i40e_mirror_rule *p_mirror;
2043 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2044 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2047 /* Disable all queues */
2048 i40e_dev_switch_queues(pf, FALSE);
2050 /* un-map queues with interrupt registers */
2051 i40e_vsi_disable_queues_intr(main_vsi);
2052 i40e_vsi_queues_unbind_intr(main_vsi);
2054 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2055 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2056 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2059 if (pf->fdir.fdir_vsi) {
2060 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2061 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2063 /* Clear all queues and release memory */
2064 i40e_dev_clear_queues(dev);
2067 i40e_dev_set_link_down(dev);
2069 /* Remove all mirror rules */
2070 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2071 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2074 pf->nb_mirror_rule = 0;
2076 if (!rte_intr_allow_others(intr_handle))
2077 /* resume to the default handler */
2078 rte_intr_callback_register(intr_handle,
2079 i40e_dev_interrupt_handler,
2082 /* Clean datapath event and queue/vec mapping */
2083 rte_intr_efd_disable(intr_handle);
2084 if (intr_handle->intr_vec) {
2085 rte_free(intr_handle->intr_vec);
2086 intr_handle->intr_vec = NULL;
2091 i40e_dev_close(struct rte_eth_dev *dev)
2093 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2096 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2100 PMD_INIT_FUNC_TRACE();
2103 hw->adapter_stopped = 1;
2104 i40e_dev_free_queues(dev);
2106 /* Disable interrupt */
2107 i40e_pf_disable_irq0(hw);
2108 rte_intr_disable(intr_handle);
2110 /* shutdown and destroy the HMC */
2111 i40e_shutdown_lan_hmc(hw);
2113 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114 i40e_vsi_release(pf->vmdq[i].vsi);
2115 pf->vmdq[i].vsi = NULL;
2120 /* release all the existing VSIs and VEBs */
2121 i40e_fdir_teardown(pf);
2122 i40e_vsi_release(pf->main_vsi);
2124 /* shutdown the adminq */
2125 i40e_aq_queue_shutdown(hw, true);
2126 i40e_shutdown_adminq(hw);
2128 i40e_res_pool_destroy(&pf->qp_pool);
2129 i40e_res_pool_destroy(&pf->msix_pool);
2131 /* force a PF reset to clean anything leftover */
2132 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2133 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2134 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2135 I40E_WRITE_FLUSH(hw);
2139 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143 struct i40e_vsi *vsi = pf->main_vsi;
2146 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2148 if (status != I40E_SUCCESS)
2149 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2151 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2153 if (status != I40E_SUCCESS)
2154 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2159 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163 struct i40e_vsi *vsi = pf->main_vsi;
2166 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2168 if (status != I40E_SUCCESS)
2169 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2171 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2173 if (status != I40E_SUCCESS)
2174 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2178 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182 struct i40e_vsi *vsi = pf->main_vsi;
2185 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2186 if (ret != I40E_SUCCESS)
2187 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2191 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2193 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 struct i40e_vsi *vsi = pf->main_vsi;
2198 if (dev->data->promiscuous == 1)
2199 return; /* must remain in all_multicast mode */
2201 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2202 vsi->seid, FALSE, NULL);
2203 if (ret != I40E_SUCCESS)
2204 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2208 * Set device link up.
2211 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2213 /* re-apply link speed setting */
2214 return i40e_apply_link_speed(dev);
2218 * Set device link down.
2221 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2223 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2224 uint8_t abilities = 0;
2225 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2228 return i40e_phy_conf_link(hw, abilities, speed);
2232 i40e_dev_link_update(struct rte_eth_dev *dev,
2233 int wait_to_complete)
2235 #define CHECK_INTERVAL 100 /* 100ms */
2236 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 struct i40e_link_status link_status;
2239 struct rte_eth_link link, old;
2241 unsigned rep_cnt = MAX_REPEAT_TIME;
2242 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2244 memset(&link, 0, sizeof(link));
2245 memset(&old, 0, sizeof(old));
2246 memset(&link_status, 0, sizeof(link_status));
2247 rte_i40e_dev_atomic_read_link_status(dev, &old);
2250 /* Get link status information from hardware */
2251 status = i40e_aq_get_link_info(hw, enable_lse,
2252 &link_status, NULL);
2253 if (status != I40E_SUCCESS) {
2254 link.link_speed = ETH_SPEED_NUM_100M;
2255 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2256 PMD_DRV_LOG(ERR, "Failed to get link info");
2260 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2261 if (!wait_to_complete || link.link_status)
2264 rte_delay_ms(CHECK_INTERVAL);
2265 } while (--rep_cnt);
2267 if (!link.link_status)
2270 /* i40e uses full duplex only */
2271 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2273 /* Parse the link status */
2274 switch (link_status.link_speed) {
2275 case I40E_LINK_SPEED_100MB:
2276 link.link_speed = ETH_SPEED_NUM_100M;
2278 case I40E_LINK_SPEED_1GB:
2279 link.link_speed = ETH_SPEED_NUM_1G;
2281 case I40E_LINK_SPEED_10GB:
2282 link.link_speed = ETH_SPEED_NUM_10G;
2284 case I40E_LINK_SPEED_20GB:
2285 link.link_speed = ETH_SPEED_NUM_20G;
2287 case I40E_LINK_SPEED_25GB:
2288 link.link_speed = ETH_SPEED_NUM_25G;
2290 case I40E_LINK_SPEED_40GB:
2291 link.link_speed = ETH_SPEED_NUM_40G;
2294 link.link_speed = ETH_SPEED_NUM_100M;
2298 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2299 ETH_LINK_SPEED_FIXED);
2302 rte_i40e_dev_atomic_write_link_status(dev, &link);
2303 if (link.link_status == old.link_status)
2309 /* Get all the statistics of a VSI */
2311 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2313 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2314 struct i40e_eth_stats *nes = &vsi->eth_stats;
2315 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2316 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2318 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2319 vsi->offset_loaded, &oes->rx_bytes,
2321 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2322 vsi->offset_loaded, &oes->rx_unicast,
2324 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2325 vsi->offset_loaded, &oes->rx_multicast,
2326 &nes->rx_multicast);
2327 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2328 vsi->offset_loaded, &oes->rx_broadcast,
2329 &nes->rx_broadcast);
2330 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2331 &oes->rx_discards, &nes->rx_discards);
2332 /* GLV_REPC not supported */
2333 /* GLV_RMPC not supported */
2334 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2335 &oes->rx_unknown_protocol,
2336 &nes->rx_unknown_protocol);
2337 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2338 vsi->offset_loaded, &oes->tx_bytes,
2340 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2341 vsi->offset_loaded, &oes->tx_unicast,
2343 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2344 vsi->offset_loaded, &oes->tx_multicast,
2345 &nes->tx_multicast);
2346 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2347 vsi->offset_loaded, &oes->tx_broadcast,
2348 &nes->tx_broadcast);
2349 /* GLV_TDPC not supported */
2350 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2351 &oes->tx_errors, &nes->tx_errors);
2352 vsi->offset_loaded = true;
2354 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2356 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2357 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2358 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2359 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2360 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2361 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2362 nes->rx_unknown_protocol);
2363 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2364 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2365 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2366 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2367 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2368 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2369 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2374 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2377 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2378 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2380 /* Get statistics of struct i40e_eth_stats */
2381 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2382 I40E_GLPRT_GORCL(hw->port),
2383 pf->offset_loaded, &os->eth.rx_bytes,
2385 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2386 I40E_GLPRT_UPRCL(hw->port),
2387 pf->offset_loaded, &os->eth.rx_unicast,
2388 &ns->eth.rx_unicast);
2389 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2390 I40E_GLPRT_MPRCL(hw->port),
2391 pf->offset_loaded, &os->eth.rx_multicast,
2392 &ns->eth.rx_multicast);
2393 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2394 I40E_GLPRT_BPRCL(hw->port),
2395 pf->offset_loaded, &os->eth.rx_broadcast,
2396 &ns->eth.rx_broadcast);
2397 /* Workaround: CRC size should not be included in byte statistics,
2398 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2400 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2401 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2403 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2404 pf->offset_loaded, &os->eth.rx_discards,
2405 &ns->eth.rx_discards);
2406 /* GLPRT_REPC not supported */
2407 /* GLPRT_RMPC not supported */
2408 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2410 &os->eth.rx_unknown_protocol,
2411 &ns->eth.rx_unknown_protocol);
2412 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2413 I40E_GLPRT_GOTCL(hw->port),
2414 pf->offset_loaded, &os->eth.tx_bytes,
2416 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2417 I40E_GLPRT_UPTCL(hw->port),
2418 pf->offset_loaded, &os->eth.tx_unicast,
2419 &ns->eth.tx_unicast);
2420 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2421 I40E_GLPRT_MPTCL(hw->port),
2422 pf->offset_loaded, &os->eth.tx_multicast,
2423 &ns->eth.tx_multicast);
2424 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2425 I40E_GLPRT_BPTCL(hw->port),
2426 pf->offset_loaded, &os->eth.tx_broadcast,
2427 &ns->eth.tx_broadcast);
2428 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2429 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2430 /* GLPRT_TEPC not supported */
2432 /* additional port specific stats */
2433 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2434 pf->offset_loaded, &os->tx_dropped_link_down,
2435 &ns->tx_dropped_link_down);
2436 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2437 pf->offset_loaded, &os->crc_errors,
2439 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2440 pf->offset_loaded, &os->illegal_bytes,
2441 &ns->illegal_bytes);
2442 /* GLPRT_ERRBC not supported */
2443 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2444 pf->offset_loaded, &os->mac_local_faults,
2445 &ns->mac_local_faults);
2446 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2447 pf->offset_loaded, &os->mac_remote_faults,
2448 &ns->mac_remote_faults);
2449 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2450 pf->offset_loaded, &os->rx_length_errors,
2451 &ns->rx_length_errors);
2452 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2453 pf->offset_loaded, &os->link_xon_rx,
2455 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2456 pf->offset_loaded, &os->link_xoff_rx,
2458 for (i = 0; i < 8; i++) {
2459 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2461 &os->priority_xon_rx[i],
2462 &ns->priority_xon_rx[i]);
2463 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2465 &os->priority_xoff_rx[i],
2466 &ns->priority_xoff_rx[i]);
2468 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2469 pf->offset_loaded, &os->link_xon_tx,
2471 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2472 pf->offset_loaded, &os->link_xoff_tx,
2474 for (i = 0; i < 8; i++) {
2475 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2477 &os->priority_xon_tx[i],
2478 &ns->priority_xon_tx[i]);
2479 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2481 &os->priority_xoff_tx[i],
2482 &ns->priority_xoff_tx[i]);
2483 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2485 &os->priority_xon_2_xoff[i],
2486 &ns->priority_xon_2_xoff[i]);
2488 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2489 I40E_GLPRT_PRC64L(hw->port),
2490 pf->offset_loaded, &os->rx_size_64,
2492 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2493 I40E_GLPRT_PRC127L(hw->port),
2494 pf->offset_loaded, &os->rx_size_127,
2496 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2497 I40E_GLPRT_PRC255L(hw->port),
2498 pf->offset_loaded, &os->rx_size_255,
2500 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2501 I40E_GLPRT_PRC511L(hw->port),
2502 pf->offset_loaded, &os->rx_size_511,
2504 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2505 I40E_GLPRT_PRC1023L(hw->port),
2506 pf->offset_loaded, &os->rx_size_1023,
2508 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2509 I40E_GLPRT_PRC1522L(hw->port),
2510 pf->offset_loaded, &os->rx_size_1522,
2512 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2513 I40E_GLPRT_PRC9522L(hw->port),
2514 pf->offset_loaded, &os->rx_size_big,
2516 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2517 pf->offset_loaded, &os->rx_undersize,
2519 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2520 pf->offset_loaded, &os->rx_fragments,
2522 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2523 pf->offset_loaded, &os->rx_oversize,
2525 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2526 pf->offset_loaded, &os->rx_jabber,
2528 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2529 I40E_GLPRT_PTC64L(hw->port),
2530 pf->offset_loaded, &os->tx_size_64,
2532 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2533 I40E_GLPRT_PTC127L(hw->port),
2534 pf->offset_loaded, &os->tx_size_127,
2536 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2537 I40E_GLPRT_PTC255L(hw->port),
2538 pf->offset_loaded, &os->tx_size_255,
2540 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2541 I40E_GLPRT_PTC511L(hw->port),
2542 pf->offset_loaded, &os->tx_size_511,
2544 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2545 I40E_GLPRT_PTC1023L(hw->port),
2546 pf->offset_loaded, &os->tx_size_1023,
2548 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2549 I40E_GLPRT_PTC1522L(hw->port),
2550 pf->offset_loaded, &os->tx_size_1522,
2552 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2553 I40E_GLPRT_PTC9522L(hw->port),
2554 pf->offset_loaded, &os->tx_size_big,
2556 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2558 &os->fd_sb_match, &ns->fd_sb_match);
2559 /* GLPRT_MSPDC not supported */
2560 /* GLPRT_XEC not supported */
2562 pf->offset_loaded = true;
2565 i40e_update_vsi_stats(pf->main_vsi);
2568 /* Get all statistics of a port */
2570 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2573 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2574 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2577 /* call read registers - updates values, now write them to struct */
2578 i40e_read_stats_registers(pf, hw);
2580 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2581 pf->main_vsi->eth_stats.rx_multicast +
2582 pf->main_vsi->eth_stats.rx_broadcast -
2583 pf->main_vsi->eth_stats.rx_discards;
2584 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2585 pf->main_vsi->eth_stats.tx_multicast +
2586 pf->main_vsi->eth_stats.tx_broadcast;
2587 stats->ibytes = ns->eth.rx_bytes;
2588 stats->obytes = ns->eth.tx_bytes;
2589 stats->oerrors = ns->eth.tx_errors +
2590 pf->main_vsi->eth_stats.tx_errors;
2593 stats->imissed = ns->eth.rx_discards +
2594 pf->main_vsi->eth_stats.rx_discards;
2595 stats->ierrors = ns->crc_errors +
2596 ns->rx_length_errors + ns->rx_undersize +
2597 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2599 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2600 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2601 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2602 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2603 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2604 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2605 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2606 ns->eth.rx_unknown_protocol);
2607 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2608 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2609 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2610 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2611 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2612 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2614 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2615 ns->tx_dropped_link_down);
2616 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2617 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2619 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2620 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2621 ns->mac_local_faults);
2622 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2623 ns->mac_remote_faults);
2624 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2625 ns->rx_length_errors);
2626 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2627 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2628 for (i = 0; i < 8; i++) {
2629 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2630 i, ns->priority_xon_rx[i]);
2631 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2632 i, ns->priority_xoff_rx[i]);
2634 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2635 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2636 for (i = 0; i < 8; i++) {
2637 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2638 i, ns->priority_xon_tx[i]);
2639 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2640 i, ns->priority_xoff_tx[i]);
2641 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2642 i, ns->priority_xon_2_xoff[i]);
2644 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2645 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2646 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2647 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2648 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2649 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2650 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2651 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2652 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2653 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2654 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2655 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2656 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2657 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2658 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2659 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2660 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2661 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2662 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2663 ns->mac_short_packet_dropped);
2664 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2665 ns->checksum_error);
2666 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2667 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2670 /* Reset the statistics */
2672 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2674 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677 /* Mark PF and VSI stats to update the offset, aka "reset" */
2678 pf->offset_loaded = false;
2680 pf->main_vsi->offset_loaded = false;
2682 /* read the stats, reading current register values into offset */
2683 i40e_read_stats_registers(pf, hw);
2687 i40e_xstats_calc_num(void)
2689 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2690 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2691 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2694 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2695 struct rte_eth_xstat_name *xstats_names,
2696 __rte_unused unsigned limit)
2701 if (xstats_names == NULL)
2702 return i40e_xstats_calc_num();
2704 /* Note: limit checked in rte_eth_xstats_names() */
2706 /* Get stats from i40e_eth_stats struct */
2707 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2708 snprintf(xstats_names[count].name,
2709 sizeof(xstats_names[count].name),
2710 "%s", rte_i40e_stats_strings[i].name);
2714 /* Get individiual stats from i40e_hw_port struct */
2715 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2716 snprintf(xstats_names[count].name,
2717 sizeof(xstats_names[count].name),
2718 "%s", rte_i40e_hw_port_strings[i].name);
2722 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2723 for (prio = 0; prio < 8; prio++) {
2724 snprintf(xstats_names[count].name,
2725 sizeof(xstats_names[count].name),
2726 "rx_priority%u_%s", prio,
2727 rte_i40e_rxq_prio_strings[i].name);
2732 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2733 for (prio = 0; prio < 8; prio++) {
2734 snprintf(xstats_names[count].name,
2735 sizeof(xstats_names[count].name),
2736 "tx_priority%u_%s", prio,
2737 rte_i40e_txq_prio_strings[i].name);
2745 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2748 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750 unsigned i, count, prio;
2751 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2753 count = i40e_xstats_calc_num();
2757 i40e_read_stats_registers(pf, hw);
2764 /* Get stats from i40e_eth_stats struct */
2765 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2766 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2767 rte_i40e_stats_strings[i].offset);
2768 xstats[count].id = count;
2772 /* Get individiual stats from i40e_hw_port struct */
2773 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2774 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2775 rte_i40e_hw_port_strings[i].offset);
2776 xstats[count].id = count;
2780 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2781 for (prio = 0; prio < 8; prio++) {
2782 xstats[count].value =
2783 *(uint64_t *)(((char *)hw_stats) +
2784 rte_i40e_rxq_prio_strings[i].offset +
2785 (sizeof(uint64_t) * prio));
2786 xstats[count].id = count;
2791 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2792 for (prio = 0; prio < 8; prio++) {
2793 xstats[count].value =
2794 *(uint64_t *)(((char *)hw_stats) +
2795 rte_i40e_txq_prio_strings[i].offset +
2796 (sizeof(uint64_t) * prio));
2797 xstats[count].id = count;
2806 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2807 __rte_unused uint16_t queue_id,
2808 __rte_unused uint8_t stat_idx,
2809 __rte_unused uint8_t is_rx)
2811 PMD_INIT_FUNC_TRACE();
2817 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825 full_ver = hw->nvm.oem_ver;
2826 ver = (u8)(full_ver >> 24);
2827 build = (u16)((full_ver >> 8) & 0xffff);
2828 patch = (u8)(full_ver & 0xff);
2830 ret = snprintf(fw_version, fw_size,
2831 "%d.%d%d 0x%08x %d.%d.%d",
2832 ((hw->nvm.version >> 12) & 0xf),
2833 ((hw->nvm.version >> 4) & 0xff),
2834 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2837 ret += 1; /* add the size of '\0' */
2838 if (fw_size < (u32)ret)
2845 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2847 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2848 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2849 struct i40e_vsi *vsi = pf->main_vsi;
2850 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2852 dev_info->pci_dev = pci_dev;
2853 dev_info->max_rx_queues = vsi->nb_qps;
2854 dev_info->max_tx_queues = vsi->nb_qps;
2855 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2856 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2857 dev_info->max_mac_addrs = vsi->max_macaddrs;
2858 dev_info->max_vfs = pci_dev->max_vfs;
2859 dev_info->rx_offload_capa =
2860 DEV_RX_OFFLOAD_VLAN_STRIP |
2861 DEV_RX_OFFLOAD_QINQ_STRIP |
2862 DEV_RX_OFFLOAD_IPV4_CKSUM |
2863 DEV_RX_OFFLOAD_UDP_CKSUM |
2864 DEV_RX_OFFLOAD_TCP_CKSUM;
2865 dev_info->tx_offload_capa =
2866 DEV_TX_OFFLOAD_VLAN_INSERT |
2867 DEV_TX_OFFLOAD_QINQ_INSERT |
2868 DEV_TX_OFFLOAD_IPV4_CKSUM |
2869 DEV_TX_OFFLOAD_UDP_CKSUM |
2870 DEV_TX_OFFLOAD_TCP_CKSUM |
2871 DEV_TX_OFFLOAD_SCTP_CKSUM |
2872 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2873 DEV_TX_OFFLOAD_TCP_TSO |
2874 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2875 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2876 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2877 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2878 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2880 dev_info->reta_size = pf->hash_lut_size;
2881 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2883 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2885 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2886 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2887 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2889 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2893 dev_info->default_txconf = (struct rte_eth_txconf) {
2895 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2896 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2897 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2899 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2900 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2901 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2902 ETH_TXQ_FLAGS_NOOFFLOADS,
2905 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2906 .nb_max = I40E_MAX_RING_DESC,
2907 .nb_min = I40E_MIN_RING_DESC,
2908 .nb_align = I40E_ALIGN_RING_DESC,
2911 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2912 .nb_max = I40E_MAX_RING_DESC,
2913 .nb_min = I40E_MIN_RING_DESC,
2914 .nb_align = I40E_ALIGN_RING_DESC,
2915 .nb_seg_max = I40E_TX_MAX_SEG,
2916 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2919 if (pf->flags & I40E_FLAG_VMDQ) {
2920 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2921 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2922 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2923 pf->max_nb_vmdq_vsi;
2924 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2925 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2926 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2929 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2931 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2932 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2934 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2937 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2941 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2943 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2944 struct i40e_vsi *vsi = pf->main_vsi;
2945 PMD_INIT_FUNC_TRACE();
2948 return i40e_vsi_add_vlan(vsi, vlan_id);
2950 return i40e_vsi_delete_vlan(vsi, vlan_id);
2954 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2955 enum rte_vlan_type vlan_type,
2958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2959 uint64_t reg_r = 0, reg_w = 0;
2960 uint16_t reg_id = 0;
2962 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2964 switch (vlan_type) {
2965 case ETH_VLAN_TYPE_OUTER:
2971 case ETH_VLAN_TYPE_INNER:
2977 "Unsupported vlan type in single vlan.");
2983 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2986 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2988 if (ret != I40E_SUCCESS) {
2990 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2996 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2999 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3000 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3001 if (reg_r == reg_w) {
3003 PMD_DRV_LOG(DEBUG, "No need to write");
3007 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3009 if (ret != I40E_SUCCESS) {
3012 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3017 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3024 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3026 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3027 struct i40e_vsi *vsi = pf->main_vsi;
3029 if (mask & ETH_VLAN_FILTER_MASK) {
3030 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3031 i40e_vsi_config_vlan_filter(vsi, TRUE);
3033 i40e_vsi_config_vlan_filter(vsi, FALSE);
3036 if (mask & ETH_VLAN_STRIP_MASK) {
3037 /* Enable or disable VLAN stripping */
3038 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3039 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3041 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3044 if (mask & ETH_VLAN_EXTEND_MASK) {
3045 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3046 i40e_vsi_config_double_vlan(vsi, TRUE);
3047 /* Set global registers with default ether type value */
3048 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3050 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3054 i40e_vsi_config_double_vlan(vsi, FALSE);
3059 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3060 __rte_unused uint16_t queue,
3061 __rte_unused int on)
3063 PMD_INIT_FUNC_TRACE();
3067 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3069 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3070 struct i40e_vsi *vsi = pf->main_vsi;
3071 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3072 struct i40e_vsi_vlan_pvid_info info;
3074 memset(&info, 0, sizeof(info));
3077 info.config.pvid = pvid;
3079 info.config.reject.tagged =
3080 data->dev_conf.txmode.hw_vlan_reject_tagged;
3081 info.config.reject.untagged =
3082 data->dev_conf.txmode.hw_vlan_reject_untagged;
3085 return i40e_vsi_vlan_pvid_set(vsi, &info);
3089 i40e_dev_led_on(struct rte_eth_dev *dev)
3091 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092 uint32_t mode = i40e_led_get(hw);
3095 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3101 i40e_dev_led_off(struct rte_eth_dev *dev)
3103 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104 uint32_t mode = i40e_led_get(hw);
3107 i40e_led_set(hw, 0, false);
3113 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3115 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3118 fc_conf->pause_time = pf->fc_conf.pause_time;
3119 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3120 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3122 /* Return current mode according to actual setting*/
3123 switch (hw->fc.current_mode) {
3125 fc_conf->mode = RTE_FC_FULL;
3127 case I40E_FC_TX_PAUSE:
3128 fc_conf->mode = RTE_FC_TX_PAUSE;
3130 case I40E_FC_RX_PAUSE:
3131 fc_conf->mode = RTE_FC_RX_PAUSE;
3135 fc_conf->mode = RTE_FC_NONE;
3142 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3144 uint32_t mflcn_reg, fctrl_reg, reg;
3145 uint32_t max_high_water;
3146 uint8_t i, aq_failure;
3150 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3151 [RTE_FC_NONE] = I40E_FC_NONE,
3152 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3153 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3154 [RTE_FC_FULL] = I40E_FC_FULL
3157 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3159 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3160 if ((fc_conf->high_water > max_high_water) ||
3161 (fc_conf->high_water < fc_conf->low_water)) {
3163 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3168 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3170 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3172 pf->fc_conf.pause_time = fc_conf->pause_time;
3173 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3174 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3176 PMD_INIT_FUNC_TRACE();
3178 /* All the link flow control related enable/disable register
3179 * configuration is handle by the F/W
3181 err = i40e_set_fc(hw, &aq_failure, true);
3185 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3186 /* Configure flow control refresh threshold,
3187 * the value for stat_tx_pause_refresh_timer[8]
3188 * is used for global pause operation.
3192 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3193 pf->fc_conf.pause_time);
3195 /* configure the timer value included in transmitted pause
3197 * the value for stat_tx_pause_quanta[8] is used for global
3200 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3201 pf->fc_conf.pause_time);
3203 fctrl_reg = I40E_READ_REG(hw,
3204 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3206 if (fc_conf->mac_ctrl_frame_fwd != 0)
3207 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3209 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3211 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3214 /* Configure pause time (2 TCs per register) */
3215 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3216 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3217 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3219 /* Configure flow control refresh threshold value */
3220 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3221 pf->fc_conf.pause_time / 2);
3223 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3225 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3226 *depending on configuration
3228 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3229 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3230 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3232 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3233 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3236 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3239 /* config the water marker both based on the packets and bytes */
3240 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3241 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3242 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3243 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3244 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3245 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3246 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3247 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3249 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3250 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3253 I40E_WRITE_FLUSH(hw);
3259 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3260 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3262 PMD_INIT_FUNC_TRACE();
3267 /* Add a MAC address, and update filters */
3269 i40e_macaddr_add(struct rte_eth_dev *dev,
3270 struct ether_addr *mac_addr,
3271 __rte_unused uint32_t index,
3274 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3275 struct i40e_mac_filter_info mac_filter;
3276 struct i40e_vsi *vsi;
3279 /* If VMDQ not enabled or configured, return */
3280 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3281 !pf->nb_cfg_vmdq_vsi)) {
3282 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3283 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3288 if (pool > pf->nb_cfg_vmdq_vsi) {
3289 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3290 pool, pf->nb_cfg_vmdq_vsi);
3294 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3295 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3296 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3298 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3303 vsi = pf->vmdq[pool - 1].vsi;
3305 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3306 if (ret != I40E_SUCCESS) {
3307 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3312 /* Remove a MAC address, and update filters */
3314 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3316 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3317 struct i40e_vsi *vsi;
3318 struct rte_eth_dev_data *data = dev->data;
3319 struct ether_addr *macaddr;
3324 macaddr = &(data->mac_addrs[index]);
3326 pool_sel = dev->data->mac_pool_sel[index];
3328 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3329 if (pool_sel & (1ULL << i)) {
3333 /* No VMDQ pool enabled or configured */
3334 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3335 (i > pf->nb_cfg_vmdq_vsi)) {
3337 "No VMDQ pool enabled/configured");
3340 vsi = pf->vmdq[i - 1].vsi;
3342 ret = i40e_vsi_delete_mac(vsi, macaddr);
3345 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3352 /* Set perfect match or hash match of MAC and VLAN for a VF */
3354 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3355 struct rte_eth_mac_filter *filter,
3359 struct i40e_mac_filter_info mac_filter;
3360 struct ether_addr old_mac;
3361 struct ether_addr *new_mac;
3362 struct i40e_pf_vf *vf = NULL;
3367 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3370 hw = I40E_PF_TO_HW(pf);
3372 if (filter == NULL) {
3373 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3377 new_mac = &filter->mac_addr;
3379 if (is_zero_ether_addr(new_mac)) {
3380 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3384 vf_id = filter->dst_id;
3386 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3387 PMD_DRV_LOG(ERR, "Invalid argument.");
3390 vf = &pf->vfs[vf_id];
3392 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3393 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3398 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3399 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3401 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3404 mac_filter.filter_type = filter->filter_type;
3405 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3406 if (ret != I40E_SUCCESS) {
3407 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3410 ether_addr_copy(new_mac, &pf->dev_addr);
3412 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3414 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3415 if (ret != I40E_SUCCESS) {
3416 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3420 /* Clear device address as it has been removed */
3421 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3422 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3428 /* MAC filter handle */
3430 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3433 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3434 struct rte_eth_mac_filter *filter;
3435 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3436 int ret = I40E_NOT_SUPPORTED;
3438 filter = (struct rte_eth_mac_filter *)(arg);
3440 switch (filter_op) {
3441 case RTE_ETH_FILTER_NOP:
3444 case RTE_ETH_FILTER_ADD:
3445 i40e_pf_disable_irq0(hw);
3447 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3448 i40e_pf_enable_irq0(hw);
3450 case RTE_ETH_FILTER_DELETE:
3451 i40e_pf_disable_irq0(hw);
3453 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3454 i40e_pf_enable_irq0(hw);
3457 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3458 ret = I40E_ERR_PARAM;
3466 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3468 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3469 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3475 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3476 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3479 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3483 uint32_t *lut_dw = (uint32_t *)lut;
3484 uint16_t i, lut_size_dw = lut_size / 4;
3486 for (i = 0; i < lut_size_dw; i++)
3487 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3494 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3503 pf = I40E_VSI_TO_PF(vsi);
3504 hw = I40E_VSI_TO_HW(vsi);
3506 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3507 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3510 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3514 uint32_t *lut_dw = (uint32_t *)lut;
3515 uint16_t i, lut_size_dw = lut_size / 4;
3517 for (i = 0; i < lut_size_dw; i++)
3518 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3519 I40E_WRITE_FLUSH(hw);
3526 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3527 struct rte_eth_rss_reta_entry64 *reta_conf,
3530 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3531 uint16_t i, lut_size = pf->hash_lut_size;
3532 uint16_t idx, shift;
3536 if (reta_size != lut_size ||
3537 reta_size > ETH_RSS_RETA_SIZE_512) {
3539 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3540 reta_size, lut_size);
3544 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3546 PMD_DRV_LOG(ERR, "No memory can be allocated");
3549 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3552 for (i = 0; i < reta_size; i++) {
3553 idx = i / RTE_RETA_GROUP_SIZE;
3554 shift = i % RTE_RETA_GROUP_SIZE;
3555 if (reta_conf[idx].mask & (1ULL << shift))
3556 lut[i] = reta_conf[idx].reta[shift];
3558 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3567 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3568 struct rte_eth_rss_reta_entry64 *reta_conf,
3571 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3572 uint16_t i, lut_size = pf->hash_lut_size;
3573 uint16_t idx, shift;
3577 if (reta_size != lut_size ||
3578 reta_size > ETH_RSS_RETA_SIZE_512) {
3580 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3581 reta_size, lut_size);
3585 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3587 PMD_DRV_LOG(ERR, "No memory can be allocated");
3591 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3594 for (i = 0; i < reta_size; i++) {
3595 idx = i / RTE_RETA_GROUP_SIZE;
3596 shift = i % RTE_RETA_GROUP_SIZE;
3597 if (reta_conf[idx].mask & (1ULL << shift))
3598 reta_conf[idx].reta[shift] = lut[i];
3608 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3609 * @hw: pointer to the HW structure
3610 * @mem: pointer to mem struct to fill out
3611 * @size: size of memory requested
3612 * @alignment: what to align the allocation to
3614 enum i40e_status_code
3615 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3616 struct i40e_dma_mem *mem,
3620 const struct rte_memzone *mz = NULL;
3621 char z_name[RTE_MEMZONE_NAMESIZE];
3624 return I40E_ERR_PARAM;
3626 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3627 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3628 alignment, RTE_PGSIZE_2M);
3630 return I40E_ERR_NO_MEMORY;
3634 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3635 mem->zone = (const void *)mz;
3637 "memzone %s allocated with physical address: %"PRIu64,
3640 return I40E_SUCCESS;
3644 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3645 * @hw: pointer to the HW structure
3646 * @mem: ptr to mem struct to free
3648 enum i40e_status_code
3649 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3650 struct i40e_dma_mem *mem)
3653 return I40E_ERR_PARAM;
3656 "memzone %s to be freed with physical address: %"PRIu64,
3657 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3658 rte_memzone_free((const struct rte_memzone *)mem->zone);
3663 return I40E_SUCCESS;
3667 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3668 * @hw: pointer to the HW structure
3669 * @mem: pointer to mem struct to fill out
3670 * @size: size of memory requested
3672 enum i40e_status_code
3673 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3674 struct i40e_virt_mem *mem,
3678 return I40E_ERR_PARAM;
3681 mem->va = rte_zmalloc("i40e", size, 0);
3684 return I40E_SUCCESS;
3686 return I40E_ERR_NO_MEMORY;
3690 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3691 * @hw: pointer to the HW structure
3692 * @mem: pointer to mem struct to free
3694 enum i40e_status_code
3695 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3696 struct i40e_virt_mem *mem)
3699 return I40E_ERR_PARAM;
3704 return I40E_SUCCESS;
3708 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3710 rte_spinlock_init(&sp->spinlock);
3714 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3716 rte_spinlock_lock(&sp->spinlock);
3720 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3722 rte_spinlock_unlock(&sp->spinlock);
3726 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3732 * Get the hardware capabilities, which will be parsed
3733 * and saved into struct i40e_hw.
3736 i40e_get_cap(struct i40e_hw *hw)
3738 struct i40e_aqc_list_capabilities_element_resp *buf;
3739 uint16_t len, size = 0;
3742 /* Calculate a huge enough buff for saving response data temporarily */
3743 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3744 I40E_MAX_CAP_ELE_NUM;
3745 buf = rte_zmalloc("i40e", len, 0);
3747 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3748 return I40E_ERR_NO_MEMORY;
3751 /* Get, parse the capabilities and save it to hw */
3752 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3753 i40e_aqc_opc_list_func_capabilities, NULL);
3754 if (ret != I40E_SUCCESS)
3755 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3757 /* Free the temporary buffer after being used */
3764 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3766 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3767 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3768 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3769 uint16_t qp_count = 0, vsi_count = 0;
3771 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3772 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3775 /* Add the parameter init for LFC */
3776 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3777 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3778 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3780 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3781 pf->max_num_vsi = hw->func_caps.num_vsis;
3782 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3783 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3784 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3786 /* FDir queue/VSI allocation */
3787 pf->fdir_qp_offset = 0;
3788 if (hw->func_caps.fd) {
3789 pf->flags |= I40E_FLAG_FDIR;
3790 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3792 pf->fdir_nb_qps = 0;
3794 qp_count += pf->fdir_nb_qps;
3797 /* LAN queue/VSI allocation */
3798 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3799 if (!hw->func_caps.rss) {
3802 pf->flags |= I40E_FLAG_RSS;
3803 if (hw->mac.type == I40E_MAC_X722)
3804 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3805 pf->lan_nb_qps = pf->lan_nb_qp_max;
3807 qp_count += pf->lan_nb_qps;
3810 /* VF queue/VSI allocation */
3811 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3812 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3813 pf->flags |= I40E_FLAG_SRIOV;
3814 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3815 pf->vf_num = pci_dev->max_vfs;
3817 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3818 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3823 qp_count += pf->vf_nb_qps * pf->vf_num;
3824 vsi_count += pf->vf_num;
3826 /* VMDq queue/VSI allocation */
3827 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3828 pf->vmdq_nb_qps = 0;
3829 pf->max_nb_vmdq_vsi = 0;
3830 if (hw->func_caps.vmdq) {
3831 if (qp_count < hw->func_caps.num_tx_qp &&
3832 vsi_count < hw->func_caps.num_vsis) {
3833 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3834 qp_count) / pf->vmdq_nb_qp_max;
3836 /* Limit the maximum number of VMDq vsi to the maximum
3837 * ethdev can support
3839 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3840 hw->func_caps.num_vsis - vsi_count);
3841 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3843 if (pf->max_nb_vmdq_vsi) {
3844 pf->flags |= I40E_FLAG_VMDQ;
3845 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3847 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3848 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3849 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3852 "No enough queues left for VMDq");
3855 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3858 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3859 vsi_count += pf->max_nb_vmdq_vsi;
3861 if (hw->func_caps.dcb)
3862 pf->flags |= I40E_FLAG_DCB;
3864 if (qp_count > hw->func_caps.num_tx_qp) {
3866 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3867 qp_count, hw->func_caps.num_tx_qp);
3870 if (vsi_count > hw->func_caps.num_vsis) {
3872 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3873 vsi_count, hw->func_caps.num_vsis);
3881 i40e_pf_get_switch_config(struct i40e_pf *pf)
3883 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3884 struct i40e_aqc_get_switch_config_resp *switch_config;
3885 struct i40e_aqc_switch_config_element_resp *element;
3886 uint16_t start_seid = 0, num_reported;
3889 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3890 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3891 if (!switch_config) {
3892 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3896 /* Get the switch configurations */
3897 ret = i40e_aq_get_switch_config(hw, switch_config,
3898 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3899 if (ret != I40E_SUCCESS) {
3900 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3903 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3904 if (num_reported != 1) { /* The number should be 1 */
3905 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3909 /* Parse the switch configuration elements */
3910 element = &(switch_config->element[0]);
3911 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3912 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3913 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3915 PMD_DRV_LOG(INFO, "Unknown element type");
3918 rte_free(switch_config);
3924 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3927 struct pool_entry *entry;
3929 if (pool == NULL || num == 0)
3932 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3933 if (entry == NULL) {
3934 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3938 /* queue heap initialize */
3939 pool->num_free = num;
3940 pool->num_alloc = 0;
3942 LIST_INIT(&pool->alloc_list);
3943 LIST_INIT(&pool->free_list);
3945 /* Initialize element */
3949 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3954 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3956 struct pool_entry *entry, *next_entry;
3961 for (entry = LIST_FIRST(&pool->alloc_list);
3962 entry && (next_entry = LIST_NEXT(entry, next), 1);
3963 entry = next_entry) {
3964 LIST_REMOVE(entry, next);
3968 for (entry = LIST_FIRST(&pool->free_list);
3969 entry && (next_entry = LIST_NEXT(entry, next), 1);
3970 entry = next_entry) {
3971 LIST_REMOVE(entry, next);
3976 pool->num_alloc = 0;
3978 LIST_INIT(&pool->alloc_list);
3979 LIST_INIT(&pool->free_list);
3983 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3986 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3987 uint32_t pool_offset;
3991 PMD_DRV_LOG(ERR, "Invalid parameter");
3995 pool_offset = base - pool->base;
3996 /* Lookup in alloc list */
3997 LIST_FOREACH(entry, &pool->alloc_list, next) {
3998 if (entry->base == pool_offset) {
3999 valid_entry = entry;
4000 LIST_REMOVE(entry, next);
4005 /* Not find, return */
4006 if (valid_entry == NULL) {
4007 PMD_DRV_LOG(ERR, "Failed to find entry");
4012 * Found it, move it to free list and try to merge.
4013 * In order to make merge easier, always sort it by qbase.
4014 * Find adjacent prev and last entries.
4017 LIST_FOREACH(entry, &pool->free_list, next) {
4018 if (entry->base > valid_entry->base) {
4026 /* Try to merge with next one*/
4028 /* Merge with next one */
4029 if (valid_entry->base + valid_entry->len == next->base) {
4030 next->base = valid_entry->base;
4031 next->len += valid_entry->len;
4032 rte_free(valid_entry);
4039 /* Merge with previous one */
4040 if (prev->base + prev->len == valid_entry->base) {
4041 prev->len += valid_entry->len;
4042 /* If it merge with next one, remove next node */
4044 LIST_REMOVE(valid_entry, next);
4045 rte_free(valid_entry);
4047 rte_free(valid_entry);
4053 /* Not find any entry to merge, insert */
4056 LIST_INSERT_AFTER(prev, valid_entry, next);
4057 else if (next != NULL)
4058 LIST_INSERT_BEFORE(next, valid_entry, next);
4059 else /* It's empty list, insert to head */
4060 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4063 pool->num_free += valid_entry->len;
4064 pool->num_alloc -= valid_entry->len;
4070 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4073 struct pool_entry *entry, *valid_entry;
4075 if (pool == NULL || num == 0) {
4076 PMD_DRV_LOG(ERR, "Invalid parameter");
4080 if (pool->num_free < num) {
4081 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4082 num, pool->num_free);
4087 /* Lookup in free list and find most fit one */
4088 LIST_FOREACH(entry, &pool->free_list, next) {
4089 if (entry->len >= num) {
4091 if (entry->len == num) {
4092 valid_entry = entry;
4095 if (valid_entry == NULL || valid_entry->len > entry->len)
4096 valid_entry = entry;
4100 /* Not find one to satisfy the request, return */
4101 if (valid_entry == NULL) {
4102 PMD_DRV_LOG(ERR, "No valid entry found");
4106 * The entry have equal queue number as requested,
4107 * remove it from alloc_list.
4109 if (valid_entry->len == num) {
4110 LIST_REMOVE(valid_entry, next);
4113 * The entry have more numbers than requested,
4114 * create a new entry for alloc_list and minus its
4115 * queue base and number in free_list.
4117 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4118 if (entry == NULL) {
4120 "Failed to allocate memory for resource pool");
4123 entry->base = valid_entry->base;
4125 valid_entry->base += num;
4126 valid_entry->len -= num;
4127 valid_entry = entry;
4130 /* Insert it into alloc list, not sorted */
4131 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4133 pool->num_free -= valid_entry->len;
4134 pool->num_alloc += valid_entry->len;
4136 return valid_entry->base + pool->base;
4140 * bitmap_is_subset - Check whether src2 is subset of src1
4143 bitmap_is_subset(uint8_t src1, uint8_t src2)
4145 return !((src1 ^ src2) & src2);
4148 static enum i40e_status_code
4149 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4151 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4153 /* If DCB is not supported, only default TC is supported */
4154 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4155 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4156 return I40E_NOT_SUPPORTED;
4159 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4161 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4162 hw->func_caps.enabled_tcmap, enabled_tcmap);
4163 return I40E_NOT_SUPPORTED;
4165 return I40E_SUCCESS;
4169 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4170 struct i40e_vsi_vlan_pvid_info *info)
4173 struct i40e_vsi_context ctxt;
4174 uint8_t vlan_flags = 0;
4177 if (vsi == NULL || info == NULL) {
4178 PMD_DRV_LOG(ERR, "invalid parameters");
4179 return I40E_ERR_PARAM;
4183 vsi->info.pvid = info->config.pvid;
4185 * If insert pvid is enabled, only tagged pkts are
4186 * allowed to be sent out.
4188 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4189 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4192 if (info->config.reject.tagged == 0)
4193 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4195 if (info->config.reject.untagged == 0)
4196 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4198 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4199 I40E_AQ_VSI_PVLAN_MODE_MASK);
4200 vsi->info.port_vlan_flags |= vlan_flags;
4201 vsi->info.valid_sections =
4202 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4203 memset(&ctxt, 0, sizeof(ctxt));
4204 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4205 ctxt.seid = vsi->seid;
4207 hw = I40E_VSI_TO_HW(vsi);
4208 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4209 if (ret != I40E_SUCCESS)
4210 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4216 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4218 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4220 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4222 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4223 if (ret != I40E_SUCCESS)
4227 PMD_DRV_LOG(ERR, "seid not valid");
4231 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4232 tc_bw_data.tc_valid_bits = enabled_tcmap;
4233 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4234 tc_bw_data.tc_bw_credits[i] =
4235 (enabled_tcmap & (1 << i)) ? 1 : 0;
4237 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4238 if (ret != I40E_SUCCESS) {
4239 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4243 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4244 sizeof(vsi->info.qs_handle));
4245 return I40E_SUCCESS;
4248 static enum i40e_status_code
4249 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4250 struct i40e_aqc_vsi_properties_data *info,
4251 uint8_t enabled_tcmap)
4253 enum i40e_status_code ret;
4254 int i, total_tc = 0;
4255 uint16_t qpnum_per_tc, bsf, qp_idx;
4257 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4258 if (ret != I40E_SUCCESS)
4261 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4262 if (enabled_tcmap & (1 << i))
4264 vsi->enabled_tc = enabled_tcmap;
4266 /* Number of queues per enabled TC */
4267 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4268 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4269 bsf = rte_bsf32(qpnum_per_tc);
4271 /* Adjust the queue number to actual queues that can be applied */
4272 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4273 vsi->nb_qps = qpnum_per_tc * total_tc;
4276 * Configure TC and queue mapping parameters, for enabled TC,
4277 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4278 * default queue will serve it.
4281 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4282 if (vsi->enabled_tc & (1 << i)) {
4283 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4284 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4285 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4286 qp_idx += qpnum_per_tc;
4288 info->tc_mapping[i] = 0;
4291 /* Associate queue number with VSI */
4292 if (vsi->type == I40E_VSI_SRIOV) {
4293 info->mapping_flags |=
4294 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4295 for (i = 0; i < vsi->nb_qps; i++)
4296 info->queue_mapping[i] =
4297 rte_cpu_to_le_16(vsi->base_queue + i);
4299 info->mapping_flags |=
4300 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4301 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4303 info->valid_sections |=
4304 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4306 return I40E_SUCCESS;
4310 i40e_veb_release(struct i40e_veb *veb)
4312 struct i40e_vsi *vsi;
4318 if (!TAILQ_EMPTY(&veb->head)) {
4319 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4322 /* associate_vsi field is NULL for floating VEB */
4323 if (veb->associate_vsi != NULL) {
4324 vsi = veb->associate_vsi;
4325 hw = I40E_VSI_TO_HW(vsi);
4327 vsi->uplink_seid = veb->uplink_seid;
4330 veb->associate_pf->main_vsi->floating_veb = NULL;
4331 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4334 i40e_aq_delete_element(hw, veb->seid, NULL);
4336 return I40E_SUCCESS;
4340 static struct i40e_veb *
4341 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4343 struct i40e_veb *veb;
4349 "veb setup failed, associated PF shouldn't null");
4352 hw = I40E_PF_TO_HW(pf);
4354 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4356 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4360 veb->associate_vsi = vsi;
4361 veb->associate_pf = pf;
4362 TAILQ_INIT(&veb->head);
4363 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4365 /* create floating veb if vsi is NULL */
4367 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4368 I40E_DEFAULT_TCMAP, false,
4369 &veb->seid, false, NULL);
4371 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4372 true, &veb->seid, false, NULL);
4375 if (ret != I40E_SUCCESS) {
4376 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4377 hw->aq.asq_last_status);
4380 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4382 /* get statistics index */
4383 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4384 &veb->stats_idx, NULL, NULL, NULL);
4385 if (ret != I40E_SUCCESS) {
4386 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4387 hw->aq.asq_last_status);
4390 /* Get VEB bandwidth, to be implemented */
4391 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4393 vsi->uplink_seid = veb->seid;
4402 i40e_vsi_release(struct i40e_vsi *vsi)
4406 struct i40e_vsi_list *vsi_list;
4409 struct i40e_mac_filter *f;
4410 uint16_t user_param;
4413 return I40E_SUCCESS;
4418 user_param = vsi->user_param;
4420 pf = I40E_VSI_TO_PF(vsi);
4421 hw = I40E_VSI_TO_HW(vsi);
4423 /* VSI has child to attach, release child first */
4425 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4426 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4429 i40e_veb_release(vsi->veb);
4432 if (vsi->floating_veb) {
4433 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4434 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4439 /* Remove all macvlan filters of the VSI */
4440 i40e_vsi_remove_all_macvlan_filter(vsi);
4441 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4444 if (vsi->type != I40E_VSI_MAIN &&
4445 ((vsi->type != I40E_VSI_SRIOV) ||
4446 !pf->floating_veb_list[user_param])) {
4447 /* Remove vsi from parent's sibling list */
4448 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4449 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4450 return I40E_ERR_PARAM;
4452 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4453 &vsi->sib_vsi_list, list);
4455 /* Remove all switch element of the VSI */
4456 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4457 if (ret != I40E_SUCCESS)
4458 PMD_DRV_LOG(ERR, "Failed to delete element");
4461 if ((vsi->type == I40E_VSI_SRIOV) &&
4462 pf->floating_veb_list[user_param]) {
4463 /* Remove vsi from parent's sibling list */
4464 if (vsi->parent_vsi == NULL ||
4465 vsi->parent_vsi->floating_veb == NULL) {
4466 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4467 return I40E_ERR_PARAM;
4469 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4470 &vsi->sib_vsi_list, list);
4472 /* Remove all switch element of the VSI */
4473 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4474 if (ret != I40E_SUCCESS)
4475 PMD_DRV_LOG(ERR, "Failed to delete element");
4478 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4480 if (vsi->type != I40E_VSI_SRIOV)
4481 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4484 return I40E_SUCCESS;
4488 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4490 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4491 struct i40e_aqc_remove_macvlan_element_data def_filter;
4492 struct i40e_mac_filter_info filter;
4495 if (vsi->type != I40E_VSI_MAIN)
4496 return I40E_ERR_CONFIG;
4497 memset(&def_filter, 0, sizeof(def_filter));
4498 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4500 def_filter.vlan_tag = 0;
4501 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4502 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4503 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4504 if (ret != I40E_SUCCESS) {
4505 struct i40e_mac_filter *f;
4506 struct ether_addr *mac;
4508 PMD_DRV_LOG(WARNING,
4509 "Cannot remove the default macvlan filter");
4510 /* It needs to add the permanent mac into mac list */
4511 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4513 PMD_DRV_LOG(ERR, "failed to allocate memory");
4514 return I40E_ERR_NO_MEMORY;
4516 mac = &f->mac_info.mac_addr;
4517 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4519 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4520 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4525 (void)rte_memcpy(&filter.mac_addr,
4526 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4527 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4528 return i40e_vsi_add_mac(vsi, &filter);
4532 * i40e_vsi_get_bw_config - Query VSI BW Information
4533 * @vsi: the VSI to be queried
4535 * Returns 0 on success, negative value on failure
4537 static enum i40e_status_code
4538 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4540 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4541 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4542 struct i40e_hw *hw = &vsi->adapter->hw;
4547 memset(&bw_config, 0, sizeof(bw_config));
4548 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4549 if (ret != I40E_SUCCESS) {
4550 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4551 hw->aq.asq_last_status);
4555 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4556 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4557 &ets_sla_config, NULL);
4558 if (ret != I40E_SUCCESS) {
4560 "VSI failed to get TC bandwdith configuration %u",
4561 hw->aq.asq_last_status);
4565 /* store and print out BW info */
4566 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4567 vsi->bw_info.bw_max = bw_config.max_bw;
4568 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4569 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4570 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4571 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4573 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4574 vsi->bw_info.bw_ets_share_credits[i] =
4575 ets_sla_config.share_credits[i];
4576 vsi->bw_info.bw_ets_credits[i] =
4577 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4578 /* 4 bits per TC, 4th bit is reserved */
4579 vsi->bw_info.bw_ets_max[i] =
4580 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4581 RTE_LEN2MASK(3, uint8_t));
4582 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4583 vsi->bw_info.bw_ets_share_credits[i]);
4584 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4585 vsi->bw_info.bw_ets_credits[i]);
4586 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4587 vsi->bw_info.bw_ets_max[i]);
4590 return I40E_SUCCESS;
4593 /* i40e_enable_pf_lb
4594 * @pf: pointer to the pf structure
4596 * allow loopback on pf
4599 i40e_enable_pf_lb(struct i40e_pf *pf)
4601 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4602 struct i40e_vsi_context ctxt;
4605 /* Use the FW API if FW >= v5.0 */
4606 if (hw->aq.fw_maj_ver < 5) {
4607 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4611 memset(&ctxt, 0, sizeof(ctxt));
4612 ctxt.seid = pf->main_vsi_seid;
4613 ctxt.pf_num = hw->pf_id;
4614 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4616 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4617 ret, hw->aq.asq_last_status);
4620 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4621 ctxt.info.valid_sections =
4622 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4623 ctxt.info.switch_id |=
4624 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4626 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4628 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4629 hw->aq.asq_last_status);
4634 i40e_vsi_setup(struct i40e_pf *pf,
4635 enum i40e_vsi_type type,
4636 struct i40e_vsi *uplink_vsi,
4637 uint16_t user_param)
4639 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4640 struct i40e_vsi *vsi;
4641 struct i40e_mac_filter_info filter;
4643 struct i40e_vsi_context ctxt;
4644 struct ether_addr broadcast =
4645 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4647 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4648 uplink_vsi == NULL) {
4650 "VSI setup failed, VSI link shouldn't be NULL");
4654 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4656 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4661 * 1.type is not MAIN and uplink vsi is not NULL
4662 * If uplink vsi didn't setup VEB, create one first under veb field
4663 * 2.type is SRIOV and the uplink is NULL
4664 * If floating VEB is NULL, create one veb under floating veb field
4667 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4668 uplink_vsi->veb == NULL) {
4669 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4671 if (uplink_vsi->veb == NULL) {
4672 PMD_DRV_LOG(ERR, "VEB setup failed");
4675 /* set ALLOWLOOPBACk on pf, when veb is created */
4676 i40e_enable_pf_lb(pf);
4679 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4680 pf->main_vsi->floating_veb == NULL) {
4681 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4683 if (pf->main_vsi->floating_veb == NULL) {
4684 PMD_DRV_LOG(ERR, "VEB setup failed");
4689 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4691 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4694 TAILQ_INIT(&vsi->mac_list);
4696 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4697 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4698 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4699 vsi->user_param = user_param;
4700 vsi->vlan_anti_spoof_on = 0;
4701 vsi->vlan_filter_on = 0;
4702 /* Allocate queues */
4703 switch (vsi->type) {
4704 case I40E_VSI_MAIN :
4705 vsi->nb_qps = pf->lan_nb_qps;
4707 case I40E_VSI_SRIOV :
4708 vsi->nb_qps = pf->vf_nb_qps;
4710 case I40E_VSI_VMDQ2:
4711 vsi->nb_qps = pf->vmdq_nb_qps;
4714 vsi->nb_qps = pf->fdir_nb_qps;
4720 * The filter status descriptor is reported in rx queue 0,
4721 * while the tx queue for fdir filter programming has no
4722 * such constraints, can be non-zero queues.
4723 * To simplify it, choose FDIR vsi use queue 0 pair.
4724 * To make sure it will use queue 0 pair, queue allocation
4725 * need be done before this function is called
4727 if (type != I40E_VSI_FDIR) {
4728 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4730 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4734 vsi->base_queue = ret;
4736 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4738 /* VF has MSIX interrupt in VF range, don't allocate here */
4739 if (type == I40E_VSI_MAIN) {
4740 ret = i40e_res_pool_alloc(&pf->msix_pool,
4741 RTE_MIN(vsi->nb_qps,
4742 RTE_MAX_RXTX_INTR_VEC_ID));
4744 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4746 goto fail_queue_alloc;
4748 vsi->msix_intr = ret;
4749 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4750 } else if (type != I40E_VSI_SRIOV) {
4751 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4753 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4754 goto fail_queue_alloc;
4756 vsi->msix_intr = ret;
4764 if (type == I40E_VSI_MAIN) {
4765 /* For main VSI, no need to add since it's default one */
4766 vsi->uplink_seid = pf->mac_seid;
4767 vsi->seid = pf->main_vsi_seid;
4768 /* Bind queues with specific MSIX interrupt */
4770 * Needs 2 interrupt at least, one for misc cause which will
4771 * enabled from OS side, Another for queues binding the
4772 * interrupt from device side only.
4775 /* Get default VSI parameters from hardware */
4776 memset(&ctxt, 0, sizeof(ctxt));
4777 ctxt.seid = vsi->seid;
4778 ctxt.pf_num = hw->pf_id;
4779 ctxt.uplink_seid = vsi->uplink_seid;
4781 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4782 if (ret != I40E_SUCCESS) {
4783 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4784 goto fail_msix_alloc;
4786 (void)rte_memcpy(&vsi->info, &ctxt.info,
4787 sizeof(struct i40e_aqc_vsi_properties_data));
4788 vsi->vsi_id = ctxt.vsi_number;
4789 vsi->info.valid_sections = 0;
4791 /* Configure tc, enabled TC0 only */
4792 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4794 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4795 goto fail_msix_alloc;
4798 /* TC, queue mapping */
4799 memset(&ctxt, 0, sizeof(ctxt));
4800 vsi->info.valid_sections |=
4801 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4802 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4803 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4804 (void)rte_memcpy(&ctxt.info, &vsi->info,
4805 sizeof(struct i40e_aqc_vsi_properties_data));
4806 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4807 I40E_DEFAULT_TCMAP);
4808 if (ret != I40E_SUCCESS) {
4810 "Failed to configure TC queue mapping");
4811 goto fail_msix_alloc;
4813 ctxt.seid = vsi->seid;
4814 ctxt.pf_num = hw->pf_id;
4815 ctxt.uplink_seid = vsi->uplink_seid;
4818 /* Update VSI parameters */
4819 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4820 if (ret != I40E_SUCCESS) {
4821 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4822 goto fail_msix_alloc;
4825 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4826 sizeof(vsi->info.tc_mapping));
4827 (void)rte_memcpy(&vsi->info.queue_mapping,
4828 &ctxt.info.queue_mapping,
4829 sizeof(vsi->info.queue_mapping));
4830 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4831 vsi->info.valid_sections = 0;
4833 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4837 * Updating default filter settings are necessary to prevent
4838 * reception of tagged packets.
4839 * Some old firmware configurations load a default macvlan
4840 * filter which accepts both tagged and untagged packets.
4841 * The updating is to use a normal filter instead if needed.
4842 * For NVM 4.2.2 or after, the updating is not needed anymore.
4843 * The firmware with correct configurations load the default
4844 * macvlan filter which is expected and cannot be removed.
4846 i40e_update_default_filter_setting(vsi);
4847 i40e_config_qinq(hw, vsi);
4848 } else if (type == I40E_VSI_SRIOV) {
4849 memset(&ctxt, 0, sizeof(ctxt));
4851 * For other VSI, the uplink_seid equals to uplink VSI's
4852 * uplink_seid since they share same VEB
4854 if (uplink_vsi == NULL)
4855 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4857 vsi->uplink_seid = uplink_vsi->uplink_seid;
4858 ctxt.pf_num = hw->pf_id;
4859 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4860 ctxt.uplink_seid = vsi->uplink_seid;
4861 ctxt.connection_type = 0x1;
4862 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4864 /* Use the VEB configuration if FW >= v5.0 */
4865 if (hw->aq.fw_maj_ver >= 5) {
4866 /* Configure switch ID */
4867 ctxt.info.valid_sections |=
4868 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4869 ctxt.info.switch_id =
4870 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4873 /* Configure port/vlan */
4874 ctxt.info.valid_sections |=
4875 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4876 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4877 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4878 hw->func_caps.enabled_tcmap);
4879 if (ret != I40E_SUCCESS) {
4881 "Failed to configure TC queue mapping");
4882 goto fail_msix_alloc;
4885 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4886 ctxt.info.valid_sections |=
4887 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4889 * Since VSI is not created yet, only configure parameter,
4890 * will add vsi below.
4893 i40e_config_qinq(hw, vsi);
4894 } else if (type == I40E_VSI_VMDQ2) {
4895 memset(&ctxt, 0, sizeof(ctxt));
4897 * For other VSI, the uplink_seid equals to uplink VSI's
4898 * uplink_seid since they share same VEB
4900 vsi->uplink_seid = uplink_vsi->uplink_seid;
4901 ctxt.pf_num = hw->pf_id;
4903 ctxt.uplink_seid = vsi->uplink_seid;
4904 ctxt.connection_type = 0x1;
4905 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4907 ctxt.info.valid_sections |=
4908 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4909 /* user_param carries flag to enable loop back */
4911 ctxt.info.switch_id =
4912 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4913 ctxt.info.switch_id |=
4914 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4917 /* Configure port/vlan */
4918 ctxt.info.valid_sections |=
4919 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4920 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4921 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4922 I40E_DEFAULT_TCMAP);
4923 if (ret != I40E_SUCCESS) {
4925 "Failed to configure TC queue mapping");
4926 goto fail_msix_alloc;
4928 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4929 ctxt.info.valid_sections |=
4930 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4931 } else if (type == I40E_VSI_FDIR) {
4932 memset(&ctxt, 0, sizeof(ctxt));
4933 vsi->uplink_seid = uplink_vsi->uplink_seid;
4934 ctxt.pf_num = hw->pf_id;
4936 ctxt.uplink_seid = vsi->uplink_seid;
4937 ctxt.connection_type = 0x1; /* regular data port */
4938 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4939 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4940 I40E_DEFAULT_TCMAP);
4941 if (ret != I40E_SUCCESS) {
4943 "Failed to configure TC queue mapping.");
4944 goto fail_msix_alloc;
4946 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4947 ctxt.info.valid_sections |=
4948 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4950 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4951 goto fail_msix_alloc;
4954 if (vsi->type != I40E_VSI_MAIN) {
4955 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4956 if (ret != I40E_SUCCESS) {
4957 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4958 hw->aq.asq_last_status);
4959 goto fail_msix_alloc;
4961 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4962 vsi->info.valid_sections = 0;
4963 vsi->seid = ctxt.seid;
4964 vsi->vsi_id = ctxt.vsi_number;
4965 vsi->sib_vsi_list.vsi = vsi;
4966 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4967 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4968 &vsi->sib_vsi_list, list);
4970 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4971 &vsi->sib_vsi_list, list);
4975 /* MAC/VLAN configuration */
4976 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4977 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4979 ret = i40e_vsi_add_mac(vsi, &filter);
4980 if (ret != I40E_SUCCESS) {
4981 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4982 goto fail_msix_alloc;
4985 /* Get VSI BW information */
4986 i40e_vsi_get_bw_config(vsi);
4989 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4991 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4997 /* Configure vlan filter on or off */
4999 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5002 struct i40e_mac_filter *f;
5004 struct i40e_mac_filter_info *mac_filter;
5005 enum rte_mac_filter_type desired_filter;
5006 int ret = I40E_SUCCESS;
5009 /* Filter to match MAC and VLAN */
5010 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5012 /* Filter to match only MAC */
5013 desired_filter = RTE_MAC_PERFECT_MATCH;
5018 mac_filter = rte_zmalloc("mac_filter_info_data",
5019 num * sizeof(*mac_filter), 0);
5020 if (mac_filter == NULL) {
5021 PMD_DRV_LOG(ERR, "failed to allocate memory");
5022 return I40E_ERR_NO_MEMORY;
5027 /* Remove all existing mac */
5028 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5029 mac_filter[i] = f->mac_info;
5030 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5032 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5033 on ? "enable" : "disable");
5039 /* Override with new filter */
5040 for (i = 0; i < num; i++) {
5041 mac_filter[i].filter_type = desired_filter;
5042 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5044 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5045 on ? "enable" : "disable");
5051 rte_free(mac_filter);
5055 /* Configure vlan stripping on or off */
5057 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5059 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5060 struct i40e_vsi_context ctxt;
5062 int ret = I40E_SUCCESS;
5064 /* Check if it has been already on or off */
5065 if (vsi->info.valid_sections &
5066 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5068 if ((vsi->info.port_vlan_flags &
5069 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5070 return 0; /* already on */
5072 if ((vsi->info.port_vlan_flags &
5073 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5074 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5075 return 0; /* already off */
5080 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5082 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5083 vsi->info.valid_sections =
5084 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5085 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5086 vsi->info.port_vlan_flags |= vlan_flags;
5087 ctxt.seid = vsi->seid;
5088 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5089 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5091 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5092 on ? "enable" : "disable");
5098 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5100 struct rte_eth_dev_data *data = dev->data;
5104 /* Apply vlan offload setting */
5105 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5106 i40e_vlan_offload_set(dev, mask);
5108 /* Apply double-vlan setting, not implemented yet */
5110 /* Apply pvid setting */
5111 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5112 data->dev_conf.txmode.hw_vlan_insert_pvid);
5114 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5120 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5122 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5124 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5128 i40e_update_flow_control(struct i40e_hw *hw)
5130 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5131 struct i40e_link_status link_status;
5132 uint32_t rxfc = 0, txfc = 0, reg;
5136 memset(&link_status, 0, sizeof(link_status));
5137 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5138 if (ret != I40E_SUCCESS) {
5139 PMD_DRV_LOG(ERR, "Failed to get link status information");
5140 goto write_reg; /* Disable flow control */
5143 an_info = hw->phy.link_info.an_info;
5144 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5145 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5146 ret = I40E_ERR_NOT_READY;
5147 goto write_reg; /* Disable flow control */
5150 * If link auto negotiation is enabled, flow control needs to
5151 * be configured according to it
5153 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5154 case I40E_LINK_PAUSE_RXTX:
5157 hw->fc.current_mode = I40E_FC_FULL;
5159 case I40E_AQ_LINK_PAUSE_RX:
5161 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5163 case I40E_AQ_LINK_PAUSE_TX:
5165 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5168 hw->fc.current_mode = I40E_FC_NONE;
5173 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5174 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5175 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5176 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5177 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5178 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5185 i40e_pf_setup(struct i40e_pf *pf)
5187 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5188 struct i40e_filter_control_settings settings;
5189 struct i40e_vsi *vsi;
5192 /* Clear all stats counters */
5193 pf->offset_loaded = FALSE;
5194 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5195 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5197 ret = i40e_pf_get_switch_config(pf);
5198 if (ret != I40E_SUCCESS) {
5199 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5202 if (pf->flags & I40E_FLAG_FDIR) {
5203 /* make queue allocated first, let FDIR use queue pair 0*/
5204 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5205 if (ret != I40E_FDIR_QUEUE_ID) {
5207 "queue allocation fails for FDIR: ret =%d",
5209 pf->flags &= ~I40E_FLAG_FDIR;
5212 /* main VSI setup */
5213 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5215 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5216 return I40E_ERR_NOT_READY;
5220 /* Configure filter control */
5221 memset(&settings, 0, sizeof(settings));
5222 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5223 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5224 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5225 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5227 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5228 hw->func_caps.rss_table_size);
5229 return I40E_ERR_PARAM;
5231 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5232 hw->func_caps.rss_table_size);
5233 pf->hash_lut_size = hw->func_caps.rss_table_size;
5235 /* Enable ethtype and macvlan filters */
5236 settings.enable_ethtype = TRUE;
5237 settings.enable_macvlan = TRUE;
5238 ret = i40e_set_filter_control(hw, &settings);
5240 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5243 /* Update flow control according to the auto negotiation */
5244 i40e_update_flow_control(hw);
5246 return I40E_SUCCESS;
5250 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5256 * Set or clear TX Queue Disable flags,
5257 * which is required by hardware.
5259 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5260 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5262 /* Wait until the request is finished */
5263 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5264 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5265 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5266 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5267 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5273 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5274 return I40E_SUCCESS; /* already on, skip next steps */
5276 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5277 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5279 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5280 return I40E_SUCCESS; /* already off, skip next steps */
5281 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5283 /* Write the register */
5284 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5285 /* Check the result */
5286 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5287 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5288 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5290 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5291 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5294 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5295 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5299 /* Check if it is timeout */
5300 if (j >= I40E_CHK_Q_ENA_COUNT) {
5301 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5302 (on ? "enable" : "disable"), q_idx);
5303 return I40E_ERR_TIMEOUT;
5306 return I40E_SUCCESS;
5309 /* Swith on or off the tx queues */
5311 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5313 struct rte_eth_dev_data *dev_data = pf->dev_data;
5314 struct i40e_tx_queue *txq;
5315 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5319 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5320 txq = dev_data->tx_queues[i];
5321 /* Don't operate the queue if not configured or
5322 * if starting only per queue */
5323 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5326 ret = i40e_dev_tx_queue_start(dev, i);
5328 ret = i40e_dev_tx_queue_stop(dev, i);
5329 if ( ret != I40E_SUCCESS)
5333 return I40E_SUCCESS;
5337 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5342 /* Wait until the request is finished */
5343 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5344 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5345 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5346 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5347 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5352 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5353 return I40E_SUCCESS; /* Already on, skip next steps */
5354 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5356 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5357 return I40E_SUCCESS; /* Already off, skip next steps */
5358 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5361 /* Write the register */
5362 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5363 /* Check the result */
5364 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5365 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5366 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5368 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5369 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5372 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5373 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5378 /* Check if it is timeout */
5379 if (j >= I40E_CHK_Q_ENA_COUNT) {
5380 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5381 (on ? "enable" : "disable"), q_idx);
5382 return I40E_ERR_TIMEOUT;
5385 return I40E_SUCCESS;
5387 /* Switch on or off the rx queues */
5389 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5391 struct rte_eth_dev_data *dev_data = pf->dev_data;
5392 struct i40e_rx_queue *rxq;
5393 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5397 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5398 rxq = dev_data->rx_queues[i];
5399 /* Don't operate the queue if not configured or
5400 * if starting only per queue */
5401 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5404 ret = i40e_dev_rx_queue_start(dev, i);
5406 ret = i40e_dev_rx_queue_stop(dev, i);
5407 if (ret != I40E_SUCCESS)
5411 return I40E_SUCCESS;
5414 /* Switch on or off all the rx/tx queues */
5416 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5421 /* enable rx queues before enabling tx queues */
5422 ret = i40e_dev_switch_rx_queues(pf, on);
5424 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5427 ret = i40e_dev_switch_tx_queues(pf, on);
5429 /* Stop tx queues before stopping rx queues */
5430 ret = i40e_dev_switch_tx_queues(pf, on);
5432 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5435 ret = i40e_dev_switch_rx_queues(pf, on);
5441 /* Initialize VSI for TX */
5443 i40e_dev_tx_init(struct i40e_pf *pf)
5445 struct rte_eth_dev_data *data = pf->dev_data;
5447 uint32_t ret = I40E_SUCCESS;
5448 struct i40e_tx_queue *txq;
5450 for (i = 0; i < data->nb_tx_queues; i++) {
5451 txq = data->tx_queues[i];
5452 if (!txq || !txq->q_set)
5454 ret = i40e_tx_queue_init(txq);
5455 if (ret != I40E_SUCCESS)
5458 if (ret == I40E_SUCCESS)
5459 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5465 /* Initialize VSI for RX */
5467 i40e_dev_rx_init(struct i40e_pf *pf)
5469 struct rte_eth_dev_data *data = pf->dev_data;
5470 int ret = I40E_SUCCESS;
5472 struct i40e_rx_queue *rxq;
5474 i40e_pf_config_mq_rx(pf);
5475 for (i = 0; i < data->nb_rx_queues; i++) {
5476 rxq = data->rx_queues[i];
5477 if (!rxq || !rxq->q_set)
5480 ret = i40e_rx_queue_init(rxq);
5481 if (ret != I40E_SUCCESS) {
5483 "Failed to do RX queue initialization");
5487 if (ret == I40E_SUCCESS)
5488 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5495 i40e_dev_rxtx_init(struct i40e_pf *pf)
5499 err = i40e_dev_tx_init(pf);
5501 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5504 err = i40e_dev_rx_init(pf);
5506 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5514 i40e_vmdq_setup(struct rte_eth_dev *dev)
5516 struct rte_eth_conf *conf = &dev->data->dev_conf;
5517 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5518 int i, err, conf_vsis, j, loop;
5519 struct i40e_vsi *vsi;
5520 struct i40e_vmdq_info *vmdq_info;
5521 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5522 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5525 * Disable interrupt to avoid message from VF. Furthermore, it will
5526 * avoid race condition in VSI creation/destroy.
5528 i40e_pf_disable_irq0(hw);
5530 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5531 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5535 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5536 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5537 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5538 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5539 pf->max_nb_vmdq_vsi);
5543 if (pf->vmdq != NULL) {
5544 PMD_INIT_LOG(INFO, "VMDQ already configured");
5548 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5549 sizeof(*vmdq_info) * conf_vsis, 0);
5551 if (pf->vmdq == NULL) {
5552 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5556 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5558 /* Create VMDQ VSI */
5559 for (i = 0; i < conf_vsis; i++) {
5560 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5561 vmdq_conf->enable_loop_back);
5563 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5567 vmdq_info = &pf->vmdq[i];
5569 vmdq_info->vsi = vsi;
5571 pf->nb_cfg_vmdq_vsi = conf_vsis;
5573 /* Configure Vlan */
5574 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5575 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5576 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5577 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5578 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5579 vmdq_conf->pool_map[i].vlan_id, j);
5581 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5582 vmdq_conf->pool_map[i].vlan_id);
5584 PMD_INIT_LOG(ERR, "Failed to add vlan");
5592 i40e_pf_enable_irq0(hw);
5597 for (i = 0; i < conf_vsis; i++)
5598 if (pf->vmdq[i].vsi == NULL)
5601 i40e_vsi_release(pf->vmdq[i].vsi);
5605 i40e_pf_enable_irq0(hw);
5610 i40e_stat_update_32(struct i40e_hw *hw,
5618 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5622 if (new_data >= *offset)
5623 *stat = (uint64_t)(new_data - *offset);
5625 *stat = (uint64_t)((new_data +
5626 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5630 i40e_stat_update_48(struct i40e_hw *hw,
5639 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5640 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5641 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5646 if (new_data >= *offset)
5647 *stat = new_data - *offset;
5649 *stat = (uint64_t)((new_data +
5650 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5652 *stat &= I40E_48_BIT_MASK;
5657 i40e_pf_disable_irq0(struct i40e_hw *hw)
5659 /* Disable all interrupt types */
5660 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5661 I40E_WRITE_FLUSH(hw);
5666 i40e_pf_enable_irq0(struct i40e_hw *hw)
5668 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5669 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5670 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5671 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5672 I40E_WRITE_FLUSH(hw);
5676 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5678 /* read pending request and disable first */
5679 i40e_pf_disable_irq0(hw);
5680 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5681 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5682 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5685 /* Link no queues with irq0 */
5686 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5687 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5691 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5694 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5697 uint32_t index, offset, val;
5702 * Try to find which VF trigger a reset, use absolute VF id to access
5703 * since the reg is global register.
5705 for (i = 0; i < pf->vf_num; i++) {
5706 abs_vf_id = hw->func_caps.vf_base_id + i;
5707 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5708 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5709 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5710 /* VFR event occured */
5711 if (val & (0x1 << offset)) {
5714 /* Clear the event first */
5715 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5717 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5719 * Only notify a VF reset event occured,
5720 * don't trigger another SW reset
5722 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5723 if (ret != I40E_SUCCESS)
5724 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5730 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5732 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5733 struct i40e_virtchnl_pf_event event;
5736 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5737 event.event_data.link_event.link_status =
5738 dev->data->dev_link.link_status;
5739 event.event_data.link_event.link_speed =
5740 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5742 for (i = 0; i < pf->vf_num; i++)
5743 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5744 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5748 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5750 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5751 struct i40e_arq_event_info info;
5752 uint16_t pending, opcode;
5755 info.buf_len = I40E_AQ_BUF_SZ;
5756 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5757 if (!info.msg_buf) {
5758 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5764 ret = i40e_clean_arq_element(hw, &info, &pending);
5766 if (ret != I40E_SUCCESS) {
5768 "Failed to read msg from AdminQ, aq_err: %u",
5769 hw->aq.asq_last_status);
5772 opcode = rte_le_to_cpu_16(info.desc.opcode);
5775 case i40e_aqc_opc_send_msg_to_pf:
5776 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5777 i40e_pf_host_handle_vf_msg(dev,
5778 rte_le_to_cpu_16(info.desc.retval),
5779 rte_le_to_cpu_32(info.desc.cookie_high),
5780 rte_le_to_cpu_32(info.desc.cookie_low),
5784 case i40e_aqc_opc_get_link_status:
5785 ret = i40e_dev_link_update(dev, 0);
5787 i40e_notify_all_vfs_link_status(dev);
5788 _rte_eth_dev_callback_process(dev,
5789 RTE_ETH_EVENT_INTR_LSC, NULL);
5793 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5798 rte_free(info.msg_buf);
5802 * Interrupt handler triggered by NIC for handling
5803 * specific interrupt.
5806 * Pointer to interrupt handle.
5808 * The address of parameter (struct rte_eth_dev *) regsitered before.
5814 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5817 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5821 /* Disable interrupt */
5822 i40e_pf_disable_irq0(hw);
5824 /* read out interrupt causes */
5825 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5827 /* No interrupt event indicated */
5828 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5829 PMD_DRV_LOG(INFO, "No interrupt event");
5832 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5833 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5834 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5835 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5836 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5837 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5838 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5839 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5840 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5841 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5842 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5843 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5844 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5845 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5846 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5847 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5849 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5850 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5851 i40e_dev_handle_vfr_event(dev);
5853 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5854 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5855 i40e_dev_handle_aq_msg(dev);
5859 /* Enable interrupt */
5860 i40e_pf_enable_irq0(hw);
5861 rte_intr_enable(intr_handle);
5865 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5866 struct i40e_macvlan_filter *filter,
5869 int ele_num, ele_buff_size;
5870 int num, actual_num, i;
5872 int ret = I40E_SUCCESS;
5873 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5874 struct i40e_aqc_add_macvlan_element_data *req_list;
5876 if (filter == NULL || total == 0)
5877 return I40E_ERR_PARAM;
5878 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5879 ele_buff_size = hw->aq.asq_buf_size;
5881 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5882 if (req_list == NULL) {
5883 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5884 return I40E_ERR_NO_MEMORY;
5889 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5890 memset(req_list, 0, ele_buff_size);
5892 for (i = 0; i < actual_num; i++) {
5893 (void)rte_memcpy(req_list[i].mac_addr,
5894 &filter[num + i].macaddr, ETH_ADDR_LEN);
5895 req_list[i].vlan_tag =
5896 rte_cpu_to_le_16(filter[num + i].vlan_id);
5898 switch (filter[num + i].filter_type) {
5899 case RTE_MAC_PERFECT_MATCH:
5900 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5901 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5903 case RTE_MACVLAN_PERFECT_MATCH:
5904 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5906 case RTE_MAC_HASH_MATCH:
5907 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5908 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5910 case RTE_MACVLAN_HASH_MATCH:
5911 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5914 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5915 ret = I40E_ERR_PARAM;
5919 req_list[i].queue_number = 0;
5921 req_list[i].flags = rte_cpu_to_le_16(flags);
5924 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5926 if (ret != I40E_SUCCESS) {
5927 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5931 } while (num < total);
5939 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5940 struct i40e_macvlan_filter *filter,
5943 int ele_num, ele_buff_size;
5944 int num, actual_num, i;
5946 int ret = I40E_SUCCESS;
5947 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5948 struct i40e_aqc_remove_macvlan_element_data *req_list;
5950 if (filter == NULL || total == 0)
5951 return I40E_ERR_PARAM;
5953 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5954 ele_buff_size = hw->aq.asq_buf_size;
5956 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5957 if (req_list == NULL) {
5958 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5959 return I40E_ERR_NO_MEMORY;
5964 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5965 memset(req_list, 0, ele_buff_size);
5967 for (i = 0; i < actual_num; i++) {
5968 (void)rte_memcpy(req_list[i].mac_addr,
5969 &filter[num + i].macaddr, ETH_ADDR_LEN);
5970 req_list[i].vlan_tag =
5971 rte_cpu_to_le_16(filter[num + i].vlan_id);
5973 switch (filter[num + i].filter_type) {
5974 case RTE_MAC_PERFECT_MATCH:
5975 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5976 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5978 case RTE_MACVLAN_PERFECT_MATCH:
5979 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5981 case RTE_MAC_HASH_MATCH:
5982 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5983 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5985 case RTE_MACVLAN_HASH_MATCH:
5986 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5989 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5990 ret = I40E_ERR_PARAM;
5993 req_list[i].flags = rte_cpu_to_le_16(flags);
5996 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5998 if (ret != I40E_SUCCESS) {
5999 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6003 } while (num < total);
6010 /* Find out specific MAC filter */
6011 static struct i40e_mac_filter *
6012 i40e_find_mac_filter(struct i40e_vsi *vsi,
6013 struct ether_addr *macaddr)
6015 struct i40e_mac_filter *f;
6017 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6018 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6026 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6029 uint32_t vid_idx, vid_bit;
6031 if (vlan_id > ETH_VLAN_ID_MAX)
6034 vid_idx = I40E_VFTA_IDX(vlan_id);
6035 vid_bit = I40E_VFTA_BIT(vlan_id);
6037 if (vsi->vfta[vid_idx] & vid_bit)
6044 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6045 uint16_t vlan_id, bool on)
6047 uint32_t vid_idx, vid_bit;
6049 vid_idx = I40E_VFTA_IDX(vlan_id);
6050 vid_bit = I40E_VFTA_BIT(vlan_id);
6053 vsi->vfta[vid_idx] |= vid_bit;
6055 vsi->vfta[vid_idx] &= ~vid_bit;
6059 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6060 uint16_t vlan_id, bool on)
6062 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6063 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6066 if (vlan_id > ETH_VLAN_ID_MAX)
6069 i40e_store_vlan_filter(vsi, vlan_id, on);
6071 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6074 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6077 ret = i40e_aq_add_vlan(hw, vsi->seid,
6078 &vlan_data, 1, NULL);
6079 if (ret != I40E_SUCCESS)
6080 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6082 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6083 &vlan_data, 1, NULL);
6084 if (ret != I40E_SUCCESS)
6086 "Failed to remove vlan filter");
6091 * Find all vlan options for specific mac addr,
6092 * return with actual vlan found.
6095 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6096 struct i40e_macvlan_filter *mv_f,
6097 int num, struct ether_addr *addr)
6103 * Not to use i40e_find_vlan_filter to decrease the loop time,
6104 * although the code looks complex.
6106 if (num < vsi->vlan_num)
6107 return I40E_ERR_PARAM;
6110 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6112 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6113 if (vsi->vfta[j] & (1 << k)) {
6116 "vlan number doesn't match");
6117 return I40E_ERR_PARAM;
6119 (void)rte_memcpy(&mv_f[i].macaddr,
6120 addr, ETH_ADDR_LEN);
6122 j * I40E_UINT32_BIT_SIZE + k;
6128 return I40E_SUCCESS;
6132 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6133 struct i40e_macvlan_filter *mv_f,
6138 struct i40e_mac_filter *f;
6140 if (num < vsi->mac_num)
6141 return I40E_ERR_PARAM;
6143 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6145 PMD_DRV_LOG(ERR, "buffer number not match");
6146 return I40E_ERR_PARAM;
6148 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6150 mv_f[i].vlan_id = vlan;
6151 mv_f[i].filter_type = f->mac_info.filter_type;
6155 return I40E_SUCCESS;
6159 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6162 struct i40e_mac_filter *f;
6163 struct i40e_macvlan_filter *mv_f;
6164 int ret = I40E_SUCCESS;
6166 if (vsi == NULL || vsi->mac_num == 0)
6167 return I40E_ERR_PARAM;
6169 /* Case that no vlan is set */
6170 if (vsi->vlan_num == 0)
6173 num = vsi->mac_num * vsi->vlan_num;
6175 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6177 PMD_DRV_LOG(ERR, "failed to allocate memory");
6178 return I40E_ERR_NO_MEMORY;
6182 if (vsi->vlan_num == 0) {
6183 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6184 (void)rte_memcpy(&mv_f[i].macaddr,
6185 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6186 mv_f[i].filter_type = f->mac_info.filter_type;
6187 mv_f[i].vlan_id = 0;
6191 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6192 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6193 vsi->vlan_num, &f->mac_info.mac_addr);
6194 if (ret != I40E_SUCCESS)
6196 for (j = i; j < i + vsi->vlan_num; j++)
6197 mv_f[j].filter_type = f->mac_info.filter_type;
6202 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6210 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6212 struct i40e_macvlan_filter *mv_f;
6214 int ret = I40E_SUCCESS;
6216 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6217 return I40E_ERR_PARAM;
6219 /* If it's already set, just return */
6220 if (i40e_find_vlan_filter(vsi,vlan))
6221 return I40E_SUCCESS;
6223 mac_num = vsi->mac_num;
6226 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6227 return I40E_ERR_PARAM;
6230 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6233 PMD_DRV_LOG(ERR, "failed to allocate memory");
6234 return I40E_ERR_NO_MEMORY;
6237 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6239 if (ret != I40E_SUCCESS)
6242 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6244 if (ret != I40E_SUCCESS)
6247 i40e_set_vlan_filter(vsi, vlan, 1);
6257 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6259 struct i40e_macvlan_filter *mv_f;
6261 int ret = I40E_SUCCESS;
6264 * Vlan 0 is the generic filter for untagged packets
6265 * and can't be removed.
6267 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6268 return I40E_ERR_PARAM;
6270 /* If can't find it, just return */
6271 if (!i40e_find_vlan_filter(vsi, vlan))
6272 return I40E_ERR_PARAM;
6274 mac_num = vsi->mac_num;
6277 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6278 return I40E_ERR_PARAM;
6281 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6284 PMD_DRV_LOG(ERR, "failed to allocate memory");
6285 return I40E_ERR_NO_MEMORY;
6288 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6290 if (ret != I40E_SUCCESS)
6293 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6295 if (ret != I40E_SUCCESS)
6298 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6299 if (vsi->vlan_num == 1) {
6300 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6301 if (ret != I40E_SUCCESS)
6304 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6305 if (ret != I40E_SUCCESS)
6309 i40e_set_vlan_filter(vsi, vlan, 0);
6319 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6321 struct i40e_mac_filter *f;
6322 struct i40e_macvlan_filter *mv_f;
6323 int i, vlan_num = 0;
6324 int ret = I40E_SUCCESS;
6326 /* If it's add and we've config it, return */
6327 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6329 return I40E_SUCCESS;
6330 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6331 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6334 * If vlan_num is 0, that's the first time to add mac,
6335 * set mask for vlan_id 0.
6337 if (vsi->vlan_num == 0) {
6338 i40e_set_vlan_filter(vsi, 0, 1);
6341 vlan_num = vsi->vlan_num;
6342 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6343 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6346 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6348 PMD_DRV_LOG(ERR, "failed to allocate memory");
6349 return I40E_ERR_NO_MEMORY;
6352 for (i = 0; i < vlan_num; i++) {
6353 mv_f[i].filter_type = mac_filter->filter_type;
6354 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6358 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6359 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6360 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6361 &mac_filter->mac_addr);
6362 if (ret != I40E_SUCCESS)
6366 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6367 if (ret != I40E_SUCCESS)
6370 /* Add the mac addr into mac list */
6371 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6373 PMD_DRV_LOG(ERR, "failed to allocate memory");
6374 ret = I40E_ERR_NO_MEMORY;
6377 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6379 f->mac_info.filter_type = mac_filter->filter_type;
6380 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6391 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6393 struct i40e_mac_filter *f;
6394 struct i40e_macvlan_filter *mv_f;
6396 enum rte_mac_filter_type filter_type;
6397 int ret = I40E_SUCCESS;
6399 /* Can't find it, return an error */
6400 f = i40e_find_mac_filter(vsi, addr);
6402 return I40E_ERR_PARAM;
6404 vlan_num = vsi->vlan_num;
6405 filter_type = f->mac_info.filter_type;
6406 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6407 filter_type == RTE_MACVLAN_HASH_MATCH) {
6408 if (vlan_num == 0) {
6409 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6410 return I40E_ERR_PARAM;
6412 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6413 filter_type == RTE_MAC_HASH_MATCH)
6416 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6418 PMD_DRV_LOG(ERR, "failed to allocate memory");
6419 return I40E_ERR_NO_MEMORY;
6422 for (i = 0; i < vlan_num; i++) {
6423 mv_f[i].filter_type = filter_type;
6424 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6427 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6428 filter_type == RTE_MACVLAN_HASH_MATCH) {
6429 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6430 if (ret != I40E_SUCCESS)
6434 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6435 if (ret != I40E_SUCCESS)
6438 /* Remove the mac addr into mac list */
6439 TAILQ_REMOVE(&vsi->mac_list, f, next);
6449 /* Configure hash enable flags for RSS */
6451 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6458 if (flags & ETH_RSS_FRAG_IPV4)
6459 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6460 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6461 if (type == I40E_MAC_X722) {
6462 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6463 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6465 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6467 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6468 if (type == I40E_MAC_X722) {
6469 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6470 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6471 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6473 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6475 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6476 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6477 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6478 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6479 if (flags & ETH_RSS_FRAG_IPV6)
6480 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6481 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6482 if (type == I40E_MAC_X722) {
6483 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6484 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6486 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6488 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6489 if (type == I40E_MAC_X722) {
6490 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6491 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6492 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6494 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6496 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6497 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6498 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6499 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6500 if (flags & ETH_RSS_L2_PAYLOAD)
6501 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6506 /* Parse the hash enable flags */
6508 i40e_parse_hena(uint64_t flags)
6510 uint64_t rss_hf = 0;
6514 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6515 rss_hf |= ETH_RSS_FRAG_IPV4;
6516 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6517 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6518 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6519 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6520 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6521 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6522 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6523 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6524 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6525 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6526 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6527 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6528 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6529 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6530 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6531 rss_hf |= ETH_RSS_FRAG_IPV6;
6532 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6533 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6534 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6535 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6536 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6537 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6538 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6539 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6540 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6541 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6542 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6543 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6544 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6545 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6546 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6547 rss_hf |= ETH_RSS_L2_PAYLOAD;
6554 i40e_pf_disable_rss(struct i40e_pf *pf)
6556 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6559 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6560 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6561 if (hw->mac.type == I40E_MAC_X722)
6562 hena &= ~I40E_RSS_HENA_ALL_X722;
6564 hena &= ~I40E_RSS_HENA_ALL;
6565 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6566 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6567 I40E_WRITE_FLUSH(hw);
6571 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6573 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6574 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6577 if (!key || key_len == 0) {
6578 PMD_DRV_LOG(DEBUG, "No key to be configured");
6580 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6582 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6586 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6587 struct i40e_aqc_get_set_rss_key_data *key_dw =
6588 (struct i40e_aqc_get_set_rss_key_data *)key;
6590 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6592 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6594 uint32_t *hash_key = (uint32_t *)key;
6597 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6598 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6599 I40E_WRITE_FLUSH(hw);
6606 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6608 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6609 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6612 if (!key || !key_len)
6615 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6616 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6617 (struct i40e_aqc_get_set_rss_key_data *)key);
6619 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6623 uint32_t *key_dw = (uint32_t *)key;
6626 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6627 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6629 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6635 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6637 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6642 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6643 rss_conf->rss_key_len);
6647 rss_hf = rss_conf->rss_hf;
6648 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6649 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6650 if (hw->mac.type == I40E_MAC_X722)
6651 hena &= ~I40E_RSS_HENA_ALL_X722;
6653 hena &= ~I40E_RSS_HENA_ALL;
6654 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6655 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6656 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6657 I40E_WRITE_FLUSH(hw);
6663 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6664 struct rte_eth_rss_conf *rss_conf)
6666 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6667 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6668 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6671 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6672 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6673 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6674 ? I40E_RSS_HENA_ALL_X722
6675 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6676 if (rss_hf != 0) /* Enable RSS */
6678 return 0; /* Nothing to do */
6681 if (rss_hf == 0) /* Disable RSS */
6684 return i40e_hw_rss_hash_set(pf, rss_conf);
6688 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6689 struct rte_eth_rss_conf *rss_conf)
6691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6692 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6695 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6696 &rss_conf->rss_key_len);
6698 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6699 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6700 rss_conf->rss_hf = i40e_parse_hena(hena);
6706 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6708 switch (filter_type) {
6709 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6710 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6712 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6713 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6715 case RTE_TUNNEL_FILTER_IMAC_TENID:
6716 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6718 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6719 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6721 case ETH_TUNNEL_FILTER_IMAC:
6722 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6724 case ETH_TUNNEL_FILTER_OIP:
6725 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6727 case ETH_TUNNEL_FILTER_IIP:
6728 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6731 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6738 /* Convert tunnel filter structure */
6740 i40e_tunnel_filter_convert(
6741 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6742 struct i40e_tunnel_filter *tunnel_filter)
6744 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6745 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6746 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6747 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6748 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6749 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6750 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6751 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6752 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6754 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6755 tunnel_filter->input.flags = cld_filter->element.flags;
6756 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6757 tunnel_filter->queue = cld_filter->element.queue_number;
6758 rte_memcpy(tunnel_filter->input.general_fields,
6759 cld_filter->general_fields,
6760 sizeof(cld_filter->general_fields));
6765 /* Check if there exists the tunnel filter */
6766 struct i40e_tunnel_filter *
6767 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6768 const struct i40e_tunnel_filter_input *input)
6772 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6776 return tunnel_rule->hash_map[ret];
6779 /* Add a tunnel filter into the SW list */
6781 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6782 struct i40e_tunnel_filter *tunnel_filter)
6784 struct i40e_tunnel_rule *rule = &pf->tunnel;
6787 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6790 "Failed to insert tunnel filter to hash table %d!",
6794 rule->hash_map[ret] = tunnel_filter;
6796 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6801 /* Delete a tunnel filter from the SW list */
6803 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6804 struct i40e_tunnel_filter_input *input)
6806 struct i40e_tunnel_rule *rule = &pf->tunnel;
6807 struct i40e_tunnel_filter *tunnel_filter;
6810 ret = rte_hash_del_key(rule->hash_table, input);
6813 "Failed to delete tunnel filter to hash table %d!",
6817 tunnel_filter = rule->hash_map[ret];
6818 rule->hash_map[ret] = NULL;
6820 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6821 rte_free(tunnel_filter);
6827 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6828 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6833 uint8_t i, tun_type = 0;
6834 /* internal varialbe to convert ipv6 byte order */
6835 uint32_t convert_ipv6[4];
6837 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6838 struct i40e_vsi *vsi = pf->main_vsi;
6839 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6840 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6841 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6842 struct i40e_tunnel_filter *tunnel, *node;
6843 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6845 cld_filter = rte_zmalloc("tunnel_filter",
6846 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6849 if (NULL == cld_filter) {
6850 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6853 pfilter = cld_filter;
6855 ether_addr_copy(&tunnel_filter->outer_mac,
6856 (struct ether_addr *)&pfilter->element.outer_mac);
6857 ether_addr_copy(&tunnel_filter->inner_mac,
6858 (struct ether_addr *)&pfilter->element.inner_mac);
6860 pfilter->element.inner_vlan =
6861 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6862 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6863 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6864 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6865 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6866 &rte_cpu_to_le_32(ipv4_addr),
6867 sizeof(pfilter->element.ipaddr.v4.data));
6869 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6870 for (i = 0; i < 4; i++) {
6872 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6874 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6876 sizeof(pfilter->element.ipaddr.v6.data));
6879 /* check tunneled type */
6880 switch (tunnel_filter->tunnel_type) {
6881 case RTE_TUNNEL_TYPE_VXLAN:
6882 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6884 case RTE_TUNNEL_TYPE_NVGRE:
6885 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6887 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6888 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6891 /* Other tunnel types is not supported. */
6892 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6893 rte_free(cld_filter);
6897 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6898 &pfilter->element.flags);
6900 rte_free(cld_filter);
6904 pfilter->element.flags |= rte_cpu_to_le_16(
6905 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6906 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6907 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6908 pfilter->element.queue_number =
6909 rte_cpu_to_le_16(tunnel_filter->queue_id);
6911 /* Check if there is the filter in SW list */
6912 memset(&check_filter, 0, sizeof(check_filter));
6913 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6914 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6916 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6920 if (!add && !node) {
6921 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6926 ret = i40e_aq_add_cloud_filters(hw,
6927 vsi->seid, &cld_filter->element, 1);
6929 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6932 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6933 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6934 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6936 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6937 &cld_filter->element, 1);
6939 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6942 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6945 rte_free(cld_filter);
6949 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6950 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6951 #define I40E_TR_GENEVE_KEY_MASK 0x8
6952 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6953 #define I40E_TR_GRE_KEY_MASK 0x400
6954 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6955 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6958 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6960 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6961 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6962 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6963 enum i40e_status_code status = I40E_SUCCESS;
6965 memset(&filter_replace, 0,
6966 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6967 memset(&filter_replace_buf, 0,
6968 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6970 /* create L1 filter */
6971 filter_replace.old_filter_type =
6972 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6973 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6974 filter_replace.tr_bit = 0;
6976 /* Prepare the buffer, 3 entries */
6977 filter_replace_buf.data[0] =
6978 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6979 filter_replace_buf.data[0] |=
6980 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6981 filter_replace_buf.data[2] = 0xFF;
6982 filter_replace_buf.data[3] = 0xFF;
6983 filter_replace_buf.data[4] =
6984 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6985 filter_replace_buf.data[4] |=
6986 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6987 filter_replace_buf.data[7] = 0xF0;
6988 filter_replace_buf.data[8]
6989 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6990 filter_replace_buf.data[8] |=
6991 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6992 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6993 I40E_TR_GENEVE_KEY_MASK |
6994 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6995 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6996 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6997 I40E_TR_GRE_NO_KEY_MASK) >> 8;
6999 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7000 &filter_replace_buf);
7005 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7007 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7008 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7009 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7010 enum i40e_status_code status = I40E_SUCCESS;
7013 memset(&filter_replace, 0,
7014 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7015 memset(&filter_replace_buf, 0,
7016 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7017 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7018 I40E_AQC_MIRROR_CLOUD_FILTER;
7019 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7020 filter_replace.new_filter_type =
7021 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7022 /* Prepare the buffer, 2 entries */
7023 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7024 filter_replace_buf.data[0] |=
7025 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7026 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7027 filter_replace_buf.data[4] |=
7028 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7029 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7030 &filter_replace_buf);
7035 memset(&filter_replace, 0,
7036 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7037 memset(&filter_replace_buf, 0,
7038 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7040 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7041 I40E_AQC_MIRROR_CLOUD_FILTER;
7042 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7043 filter_replace.new_filter_type =
7044 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7045 /* Prepare the buffer, 2 entries */
7046 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7047 filter_replace_buf.data[0] |=
7048 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7049 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7050 filter_replace_buf.data[4] |=
7051 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7053 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7054 &filter_replace_buf);
7059 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7060 struct i40e_tunnel_filter_conf *tunnel_filter,
7065 uint8_t i, tun_type = 0;
7066 /* internal variable to convert ipv6 byte order */
7067 uint32_t convert_ipv6[4];
7069 struct i40e_pf_vf *vf = NULL;
7070 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7071 struct i40e_vsi *vsi;
7072 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7073 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7074 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7075 struct i40e_tunnel_filter *tunnel, *node;
7076 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7078 bool big_buffer = 0;
7080 cld_filter = rte_zmalloc("tunnel_filter",
7081 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7084 if (cld_filter == NULL) {
7085 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7088 pfilter = cld_filter;
7090 ether_addr_copy(&tunnel_filter->outer_mac,
7091 (struct ether_addr *)&pfilter->element.outer_mac);
7092 ether_addr_copy(&tunnel_filter->inner_mac,
7093 (struct ether_addr *)&pfilter->element.inner_mac);
7095 pfilter->element.inner_vlan =
7096 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7097 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7098 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7099 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7100 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7101 &rte_cpu_to_le_32(ipv4_addr),
7102 sizeof(pfilter->element.ipaddr.v4.data));
7104 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7105 for (i = 0; i < 4; i++) {
7107 rte_cpu_to_le_32(rte_be_to_cpu_32(
7108 tunnel_filter->ip_addr.ipv6_addr[i]));
7110 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7112 sizeof(pfilter->element.ipaddr.v6.data));
7115 /* check tunneled type */
7116 switch (tunnel_filter->tunnel_type) {
7117 case I40E_TUNNEL_TYPE_VXLAN:
7118 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7120 case I40E_TUNNEL_TYPE_NVGRE:
7121 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7123 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7124 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7126 case I40E_TUNNEL_TYPE_MPLSoUDP:
7127 if (!pf->mpls_replace_flag) {
7128 i40e_replace_mpls_l1_filter(pf);
7129 i40e_replace_mpls_cloud_filter(pf);
7130 pf->mpls_replace_flag = 1;
7132 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7133 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7135 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7136 (teid_le & 0xF) << 12;
7137 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7140 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7142 case I40E_TUNNEL_TYPE_MPLSoGRE:
7143 if (!pf->mpls_replace_flag) {
7144 i40e_replace_mpls_l1_filter(pf);
7145 i40e_replace_mpls_cloud_filter(pf);
7146 pf->mpls_replace_flag = 1;
7148 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7149 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7151 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7152 (teid_le & 0xF) << 12;
7153 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7156 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7159 /* Other tunnel types is not supported. */
7160 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7161 rte_free(cld_filter);
7165 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7166 pfilter->element.flags =
7167 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7168 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7169 pfilter->element.flags =
7170 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7172 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7173 &pfilter->element.flags);
7175 rte_free(cld_filter);
7180 pfilter->element.flags |= rte_cpu_to_le_16(
7181 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7182 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7183 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7184 pfilter->element.queue_number =
7185 rte_cpu_to_le_16(tunnel_filter->queue_id);
7187 if (!tunnel_filter->is_to_vf)
7190 if (tunnel_filter->vf_id >= pf->vf_num) {
7191 PMD_DRV_LOG(ERR, "Invalid argument.");
7194 vf = &pf->vfs[tunnel_filter->vf_id];
7198 /* Check if there is the filter in SW list */
7199 memset(&check_filter, 0, sizeof(check_filter));
7200 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7201 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7203 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7207 if (!add && !node) {
7208 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7214 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7215 vsi->seid, cld_filter, 1);
7217 ret = i40e_aq_add_cloud_filters(hw,
7218 vsi->seid, &cld_filter->element, 1);
7220 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7223 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7224 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7225 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7228 ret = i40e_aq_remove_cloud_filters_big_buffer(
7229 hw, vsi->seid, cld_filter, 1);
7231 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7232 &cld_filter->element, 1);
7234 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7237 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7240 rte_free(cld_filter);
7245 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7249 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7250 if (pf->vxlan_ports[i] == port)
7258 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7262 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7264 idx = i40e_get_vxlan_port_idx(pf, port);
7266 /* Check if port already exists */
7268 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7272 /* Now check if there is space to add the new port */
7273 idx = i40e_get_vxlan_port_idx(pf, 0);
7276 "Maximum number of UDP ports reached, not adding port %d",
7281 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7284 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7288 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7291 /* New port: add it and mark its index in the bitmap */
7292 pf->vxlan_ports[idx] = port;
7293 pf->vxlan_bitmap |= (1 << idx);
7295 if (!(pf->flags & I40E_FLAG_VXLAN))
7296 pf->flags |= I40E_FLAG_VXLAN;
7302 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7305 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7307 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7308 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7312 idx = i40e_get_vxlan_port_idx(pf, port);
7315 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7319 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7320 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7324 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7327 pf->vxlan_ports[idx] = 0;
7328 pf->vxlan_bitmap &= ~(1 << idx);
7330 if (!pf->vxlan_bitmap)
7331 pf->flags &= ~I40E_FLAG_VXLAN;
7336 /* Add UDP tunneling port */
7338 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7339 struct rte_eth_udp_tunnel *udp_tunnel)
7342 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7344 if (udp_tunnel == NULL)
7347 switch (udp_tunnel->prot_type) {
7348 case RTE_TUNNEL_TYPE_VXLAN:
7349 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7352 case RTE_TUNNEL_TYPE_GENEVE:
7353 case RTE_TUNNEL_TYPE_TEREDO:
7354 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7359 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7367 /* Remove UDP tunneling port */
7369 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7370 struct rte_eth_udp_tunnel *udp_tunnel)
7373 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7375 if (udp_tunnel == NULL)
7378 switch (udp_tunnel->prot_type) {
7379 case RTE_TUNNEL_TYPE_VXLAN:
7380 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7382 case RTE_TUNNEL_TYPE_GENEVE:
7383 case RTE_TUNNEL_TYPE_TEREDO:
7384 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7388 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7396 /* Calculate the maximum number of contiguous PF queues that are configured */
7398 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7400 struct rte_eth_dev_data *data = pf->dev_data;
7402 struct i40e_rx_queue *rxq;
7405 for (i = 0; i < pf->lan_nb_qps; i++) {
7406 rxq = data->rx_queues[i];
7407 if (rxq && rxq->q_set)
7418 i40e_pf_config_rss(struct i40e_pf *pf)
7420 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7421 struct rte_eth_rss_conf rss_conf;
7422 uint32_t i, lut = 0;
7426 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7427 * It's necessary to calulate the actual PF queues that are configured.
7429 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7430 num = i40e_pf_calc_configured_queues_num(pf);
7432 num = pf->dev_data->nb_rx_queues;
7434 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7435 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7439 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7443 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7446 lut = (lut << 8) | (j & ((0x1 <<
7447 hw->func_caps.rss_table_entry_width) - 1));
7449 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7452 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7453 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7454 i40e_pf_disable_rss(pf);
7457 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7458 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7459 /* Random default keys */
7460 static uint32_t rss_key_default[] = {0x6b793944,
7461 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7462 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7463 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7465 rss_conf.rss_key = (uint8_t *)rss_key_default;
7466 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7470 return i40e_hw_rss_hash_set(pf, &rss_conf);
7474 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7475 struct rte_eth_tunnel_filter_conf *filter)
7477 if (pf == NULL || filter == NULL) {
7478 PMD_DRV_LOG(ERR, "Invalid parameter");
7482 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7483 PMD_DRV_LOG(ERR, "Invalid queue ID");
7487 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7488 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7492 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7493 (is_zero_ether_addr(&filter->outer_mac))) {
7494 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7498 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7499 (is_zero_ether_addr(&filter->inner_mac))) {
7500 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7507 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7508 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7510 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7515 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7516 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7519 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7520 } else if (len == 4) {
7521 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7523 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7528 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7535 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7536 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7542 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7549 switch (cfg->cfg_type) {
7550 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7551 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7554 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7562 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7563 enum rte_filter_op filter_op,
7566 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7567 int ret = I40E_ERR_PARAM;
7569 switch (filter_op) {
7570 case RTE_ETH_FILTER_SET:
7571 ret = i40e_dev_global_config_set(hw,
7572 (struct rte_eth_global_cfg *)arg);
7575 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7583 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7584 enum rte_filter_op filter_op,
7587 struct rte_eth_tunnel_filter_conf *filter;
7588 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7589 int ret = I40E_SUCCESS;
7591 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7593 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7594 return I40E_ERR_PARAM;
7596 switch (filter_op) {
7597 case RTE_ETH_FILTER_NOP:
7598 if (!(pf->flags & I40E_FLAG_VXLAN))
7599 ret = I40E_NOT_SUPPORTED;
7601 case RTE_ETH_FILTER_ADD:
7602 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7604 case RTE_ETH_FILTER_DELETE:
7605 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7608 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7609 ret = I40E_ERR_PARAM;
7617 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7620 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7623 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7624 ret = i40e_pf_config_rss(pf);
7626 i40e_pf_disable_rss(pf);
7631 /* Get the symmetric hash enable configurations per port */
7633 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7635 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7637 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7640 /* Set the symmetric hash enable configurations per port */
7642 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7644 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7647 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7649 "Symmetric hash has already been enabled");
7652 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7654 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7656 "Symmetric hash has already been disabled");
7659 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7661 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7662 I40E_WRITE_FLUSH(hw);
7666 * Get global configurations of hash function type and symmetric hash enable
7667 * per flow type (pctype). Note that global configuration means it affects all
7668 * the ports on the same NIC.
7671 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7672 struct rte_eth_hash_global_conf *g_cfg)
7674 uint32_t reg, mask = I40E_FLOW_TYPES;
7676 enum i40e_filter_pctype pctype;
7678 memset(g_cfg, 0, sizeof(*g_cfg));
7679 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7680 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7681 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7683 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7684 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7685 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7687 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7688 if (!(mask & (1UL << i)))
7690 mask &= ~(1UL << i);
7691 /* Bit set indicats the coresponding flow type is supported */
7692 g_cfg->valid_bit_mask[0] |= (1UL << i);
7693 /* if flowtype is invalid, continue */
7694 if (!I40E_VALID_FLOW(i))
7696 pctype = i40e_flowtype_to_pctype(i);
7697 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7698 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7699 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7706 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7709 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7711 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7712 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7713 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7714 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7720 * As i40e supports less than 32 flow types, only first 32 bits need to
7723 mask0 = g_cfg->valid_bit_mask[0];
7724 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7726 /* Check if any unsupported flow type configured */
7727 if ((mask0 | i40e_mask) ^ i40e_mask)
7730 if (g_cfg->valid_bit_mask[i])
7738 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7744 * Set global configurations of hash function type and symmetric hash enable
7745 * per flow type (pctype). Note any modifying global configuration will affect
7746 * all the ports on the same NIC.
7749 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7750 struct rte_eth_hash_global_conf *g_cfg)
7755 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7756 enum i40e_filter_pctype pctype;
7758 /* Check the input parameters */
7759 ret = i40e_hash_global_config_check(g_cfg);
7763 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7764 if (!(mask0 & (1UL << i)))
7766 mask0 &= ~(1UL << i);
7767 /* if flowtype is invalid, continue */
7768 if (!I40E_VALID_FLOW(i))
7770 pctype = i40e_flowtype_to_pctype(i);
7771 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7772 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7773 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7776 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7777 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7779 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7781 "Hash function already set to Toeplitz");
7784 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7785 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7787 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7789 "Hash function already set to Simple XOR");
7792 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7794 /* Use the default, and keep it as it is */
7797 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7800 I40E_WRITE_FLUSH(hw);
7806 * Valid input sets for hash and flow director filters per PCTYPE
7809 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7810 enum rte_filter_type filter)
7814 static const uint64_t valid_hash_inset_table[] = {
7815 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7816 I40E_INSET_DMAC | I40E_INSET_SMAC |
7817 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7818 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7819 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7820 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7821 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7822 I40E_INSET_FLEX_PAYLOAD,
7823 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7824 I40E_INSET_DMAC | I40E_INSET_SMAC |
7825 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7826 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7827 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7828 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7829 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7830 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7831 I40E_INSET_FLEX_PAYLOAD,
7832 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7833 I40E_INSET_DMAC | I40E_INSET_SMAC |
7834 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7835 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7836 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7837 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7838 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7839 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7840 I40E_INSET_FLEX_PAYLOAD,
7841 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7842 I40E_INSET_DMAC | I40E_INSET_SMAC |
7843 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7844 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7845 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7846 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7847 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7848 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7849 I40E_INSET_FLEX_PAYLOAD,
7850 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7851 I40E_INSET_DMAC | I40E_INSET_SMAC |
7852 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7853 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7854 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7855 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7856 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7857 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7858 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7859 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7860 I40E_INSET_DMAC | I40E_INSET_SMAC |
7861 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7862 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7863 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7864 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7865 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7866 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7867 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7868 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7869 I40E_INSET_DMAC | I40E_INSET_SMAC |
7870 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7871 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7872 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7873 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7874 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7875 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7876 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7877 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7878 I40E_INSET_DMAC | I40E_INSET_SMAC |
7879 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7880 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7881 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7882 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7883 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7884 I40E_INSET_FLEX_PAYLOAD,
7885 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7886 I40E_INSET_DMAC | I40E_INSET_SMAC |
7887 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7888 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7889 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7890 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7891 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7892 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7893 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7894 I40E_INSET_DMAC | I40E_INSET_SMAC |
7895 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7896 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7897 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7898 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7899 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7900 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7901 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7902 I40E_INSET_DMAC | I40E_INSET_SMAC |
7903 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7904 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7905 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7906 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7907 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7908 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7909 I40E_INSET_FLEX_PAYLOAD,
7910 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7911 I40E_INSET_DMAC | I40E_INSET_SMAC |
7912 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7913 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7914 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7915 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7916 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7917 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7918 I40E_INSET_FLEX_PAYLOAD,
7919 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7920 I40E_INSET_DMAC | I40E_INSET_SMAC |
7921 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7922 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7923 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7924 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7925 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7926 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7927 I40E_INSET_FLEX_PAYLOAD,
7928 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7929 I40E_INSET_DMAC | I40E_INSET_SMAC |
7930 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7931 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7932 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7933 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7934 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7935 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7936 I40E_INSET_FLEX_PAYLOAD,
7937 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7938 I40E_INSET_DMAC | I40E_INSET_SMAC |
7939 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7940 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7941 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7942 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7943 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7944 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7945 I40E_INSET_FLEX_PAYLOAD,
7946 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7947 I40E_INSET_DMAC | I40E_INSET_SMAC |
7948 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7949 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7950 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7951 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7952 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7953 I40E_INSET_FLEX_PAYLOAD,
7954 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7955 I40E_INSET_DMAC | I40E_INSET_SMAC |
7956 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7957 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7958 I40E_INSET_FLEX_PAYLOAD,
7962 * Flow director supports only fields defined in
7963 * union rte_eth_fdir_flow.
7965 static const uint64_t valid_fdir_inset_table[] = {
7966 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7967 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7968 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7969 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7970 I40E_INSET_IPV4_TTL,
7971 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7972 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7973 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7974 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7975 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7976 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7977 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7978 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7979 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7980 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7981 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7982 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7983 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7984 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7985 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7986 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7987 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7988 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7989 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7990 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7991 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7992 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7993 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7994 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7995 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7996 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7997 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7998 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7999 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8000 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8002 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8003 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8004 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8005 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8006 I40E_INSET_IPV4_TTL,
8007 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8008 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8009 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8010 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8011 I40E_INSET_IPV6_HOP_LIMIT,
8012 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8013 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8014 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8015 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8016 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8017 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8018 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8019 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8020 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8021 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8022 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8023 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8024 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8025 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8026 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8027 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8028 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8029 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8030 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8031 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8032 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8033 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8034 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8035 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8036 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8037 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8038 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8039 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8040 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8041 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8043 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8044 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8046 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8047 I40E_INSET_IPV6_HOP_LIMIT,
8048 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8049 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8050 I40E_INSET_LAST_ETHER_TYPE,
8053 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8055 if (filter == RTE_ETH_FILTER_HASH)
8056 valid = valid_hash_inset_table[pctype];
8058 valid = valid_fdir_inset_table[pctype];
8064 * Validate if the input set is allowed for a specific PCTYPE
8067 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8068 enum rte_filter_type filter, uint64_t inset)
8072 valid = i40e_get_valid_input_set(pctype, filter);
8073 if (inset & (~valid))
8079 /* default input set fields combination per pctype */
8081 i40e_get_default_input_set(uint16_t pctype)
8083 static const uint64_t default_inset_table[] = {
8084 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8085 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8086 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8087 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8088 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8089 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8090 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8091 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8092 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8093 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8094 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8095 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8096 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8097 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8098 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8099 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8100 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8101 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8102 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8103 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8105 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8106 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8107 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8108 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8109 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8110 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8111 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8112 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8113 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8114 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8115 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8116 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8117 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8118 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8119 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8120 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8121 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8122 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8123 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8124 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8125 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8126 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8128 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8129 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8130 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8131 I40E_INSET_LAST_ETHER_TYPE,
8134 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8137 return default_inset_table[pctype];
8141 * Parse the input set from index to logical bit masks
8144 i40e_parse_input_set(uint64_t *inset,
8145 enum i40e_filter_pctype pctype,
8146 enum rte_eth_input_set_field *field,
8152 static const struct {
8153 enum rte_eth_input_set_field field;
8155 } inset_convert_table[] = {
8156 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8157 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8158 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8159 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8160 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8161 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8162 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8163 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8164 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8165 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8166 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8167 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8168 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8169 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8170 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8171 I40E_INSET_IPV6_NEXT_HDR},
8172 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8173 I40E_INSET_IPV6_HOP_LIMIT},
8174 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8175 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8176 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8177 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8178 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8179 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8180 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8181 I40E_INSET_SCTP_VT},
8182 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8183 I40E_INSET_TUNNEL_DMAC},
8184 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8185 I40E_INSET_VLAN_TUNNEL},
8186 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8187 I40E_INSET_TUNNEL_ID},
8188 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8189 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8190 I40E_INSET_FLEX_PAYLOAD_W1},
8191 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8192 I40E_INSET_FLEX_PAYLOAD_W2},
8193 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8194 I40E_INSET_FLEX_PAYLOAD_W3},
8195 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8196 I40E_INSET_FLEX_PAYLOAD_W4},
8197 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8198 I40E_INSET_FLEX_PAYLOAD_W5},
8199 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8200 I40E_INSET_FLEX_PAYLOAD_W6},
8201 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8202 I40E_INSET_FLEX_PAYLOAD_W7},
8203 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8204 I40E_INSET_FLEX_PAYLOAD_W8},
8207 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8210 /* Only one item allowed for default or all */
8212 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8213 *inset = i40e_get_default_input_set(pctype);
8215 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8216 *inset = I40E_INSET_NONE;
8221 for (i = 0, *inset = 0; i < size; i++) {
8222 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8223 if (field[i] == inset_convert_table[j].field) {
8224 *inset |= inset_convert_table[j].inset;
8229 /* It contains unsupported input set, return immediately */
8230 if (j == RTE_DIM(inset_convert_table))
8238 * Translate the input set from bit masks to register aware bit masks
8242 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8252 static const struct inset_map inset_map_common[] = {
8253 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8254 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8255 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8256 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8257 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8258 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8259 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8260 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8261 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8262 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8263 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8264 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8265 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8266 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8267 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8268 {I40E_INSET_TUNNEL_DMAC,
8269 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8270 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8271 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8272 {I40E_INSET_TUNNEL_SRC_PORT,
8273 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8274 {I40E_INSET_TUNNEL_DST_PORT,
8275 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8276 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8277 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8278 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8279 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8280 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8281 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8282 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8283 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8284 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8287 /* some different registers map in x722*/
8288 static const struct inset_map inset_map_diff_x722[] = {
8289 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8290 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8291 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8292 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8295 static const struct inset_map inset_map_diff_not_x722[] = {
8296 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8297 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8298 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8299 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8305 /* Translate input set to register aware inset */
8306 if (type == I40E_MAC_X722) {
8307 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8308 if (input & inset_map_diff_x722[i].inset)
8309 val |= inset_map_diff_x722[i].inset_reg;
8312 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8313 if (input & inset_map_diff_not_x722[i].inset)
8314 val |= inset_map_diff_not_x722[i].inset_reg;
8318 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8319 if (input & inset_map_common[i].inset)
8320 val |= inset_map_common[i].inset_reg;
8327 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8330 uint64_t inset_need_mask = inset;
8332 static const struct {
8335 } inset_mask_map[] = {
8336 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8337 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8338 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8339 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8340 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8341 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8342 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8343 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8346 if (!inset || !mask || !nb_elem)
8349 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8350 /* Clear the inset bit, if no MASK is required,
8351 * for example proto + ttl
8353 if ((inset & inset_mask_map[i].inset) ==
8354 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8355 inset_need_mask &= ~inset_mask_map[i].inset;
8356 if (!inset_need_mask)
8359 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8360 if ((inset_need_mask & inset_mask_map[i].inset) ==
8361 inset_mask_map[i].inset) {
8362 if (idx >= nb_elem) {
8363 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8366 mask[idx] = inset_mask_map[i].mask;
8375 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8377 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8379 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8381 i40e_write_rx_ctl(hw, addr, val);
8382 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8383 (uint32_t)i40e_read_rx_ctl(hw, addr));
8387 i40e_filter_input_set_init(struct i40e_pf *pf)
8389 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8390 enum i40e_filter_pctype pctype;
8391 uint64_t input_set, inset_reg;
8392 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8395 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8396 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8397 if (hw->mac.type == I40E_MAC_X722) {
8398 if (!I40E_VALID_PCTYPE_X722(pctype))
8401 if (!I40E_VALID_PCTYPE(pctype))
8405 input_set = i40e_get_default_input_set(pctype);
8407 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8408 I40E_INSET_MASK_NUM_REG);
8411 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8414 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8415 (uint32_t)(inset_reg & UINT32_MAX));
8416 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8417 (uint32_t)((inset_reg >>
8418 I40E_32_BIT_WIDTH) & UINT32_MAX));
8419 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8420 (uint32_t)(inset_reg & UINT32_MAX));
8421 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8422 (uint32_t)((inset_reg >>
8423 I40E_32_BIT_WIDTH) & UINT32_MAX));
8425 for (i = 0; i < num; i++) {
8426 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8428 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8431 /*clear unused mask registers of the pctype */
8432 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8433 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8435 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8438 I40E_WRITE_FLUSH(hw);
8440 /* store the default input set */
8441 pf->hash_input_set[pctype] = input_set;
8442 pf->fdir.input_set[pctype] = input_set;
8447 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8448 struct rte_eth_input_set_conf *conf)
8450 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8451 enum i40e_filter_pctype pctype;
8452 uint64_t input_set, inset_reg = 0;
8453 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8457 PMD_DRV_LOG(ERR, "Invalid pointer");
8460 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8461 conf->op != RTE_ETH_INPUT_SET_ADD) {
8462 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8466 if (!I40E_VALID_FLOW(conf->flow_type)) {
8467 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8471 if (hw->mac.type == I40E_MAC_X722) {
8472 /* get translated pctype value in fd pctype register */
8473 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8474 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8477 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8479 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8482 PMD_DRV_LOG(ERR, "Failed to parse input set");
8485 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8487 PMD_DRV_LOG(ERR, "Invalid input set");
8490 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8491 /* get inset value in register */
8492 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8493 inset_reg <<= I40E_32_BIT_WIDTH;
8494 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8495 input_set |= pf->hash_input_set[pctype];
8497 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8498 I40E_INSET_MASK_NUM_REG);
8502 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8504 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8505 (uint32_t)(inset_reg & UINT32_MAX));
8506 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8507 (uint32_t)((inset_reg >>
8508 I40E_32_BIT_WIDTH) & UINT32_MAX));
8510 for (i = 0; i < num; i++)
8511 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8513 /*clear unused mask registers of the pctype */
8514 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8515 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8517 I40E_WRITE_FLUSH(hw);
8519 pf->hash_input_set[pctype] = input_set;
8524 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8525 struct rte_eth_input_set_conf *conf)
8527 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8528 enum i40e_filter_pctype pctype;
8529 uint64_t input_set, inset_reg = 0;
8530 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8534 PMD_DRV_LOG(ERR, "Invalid pointer");
8537 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8538 conf->op != RTE_ETH_INPUT_SET_ADD) {
8539 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8543 if (!I40E_VALID_FLOW(conf->flow_type)) {
8544 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8548 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8550 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8553 PMD_DRV_LOG(ERR, "Failed to parse input set");
8556 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8558 PMD_DRV_LOG(ERR, "Invalid input set");
8562 /* get inset value in register */
8563 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8564 inset_reg <<= I40E_32_BIT_WIDTH;
8565 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8567 /* Can not change the inset reg for flex payload for fdir,
8568 * it is done by writing I40E_PRTQF_FD_FLXINSET
8569 * in i40e_set_flex_mask_on_pctype.
8571 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8572 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8574 input_set |= pf->fdir.input_set[pctype];
8575 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8576 I40E_INSET_MASK_NUM_REG);
8580 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8582 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8583 (uint32_t)(inset_reg & UINT32_MAX));
8584 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8585 (uint32_t)((inset_reg >>
8586 I40E_32_BIT_WIDTH) & UINT32_MAX));
8588 for (i = 0; i < num; i++)
8589 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8591 /*clear unused mask registers of the pctype */
8592 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8593 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8595 I40E_WRITE_FLUSH(hw);
8597 pf->fdir.input_set[pctype] = input_set;
8602 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8607 PMD_DRV_LOG(ERR, "Invalid pointer");
8611 switch (info->info_type) {
8612 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8613 i40e_get_symmetric_hash_enable_per_port(hw,
8614 &(info->info.enable));
8616 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8617 ret = i40e_get_hash_filter_global_config(hw,
8618 &(info->info.global_conf));
8621 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8631 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8636 PMD_DRV_LOG(ERR, "Invalid pointer");
8640 switch (info->info_type) {
8641 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8642 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8644 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8645 ret = i40e_set_hash_filter_global_config(hw,
8646 &(info->info.global_conf));
8648 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8649 ret = i40e_hash_filter_inset_select(hw,
8650 &(info->info.input_set_conf));
8654 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8663 /* Operations for hash function */
8665 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8666 enum rte_filter_op filter_op,
8669 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8672 switch (filter_op) {
8673 case RTE_ETH_FILTER_NOP:
8675 case RTE_ETH_FILTER_GET:
8676 ret = i40e_hash_filter_get(hw,
8677 (struct rte_eth_hash_filter_info *)arg);
8679 case RTE_ETH_FILTER_SET:
8680 ret = i40e_hash_filter_set(hw,
8681 (struct rte_eth_hash_filter_info *)arg);
8684 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8693 /* Convert ethertype filter structure */
8695 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8696 struct i40e_ethertype_filter *filter)
8698 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8699 filter->input.ether_type = input->ether_type;
8700 filter->flags = input->flags;
8701 filter->queue = input->queue;
8706 /* Check if there exists the ehtertype filter */
8707 struct i40e_ethertype_filter *
8708 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8709 const struct i40e_ethertype_filter_input *input)
8713 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8717 return ethertype_rule->hash_map[ret];
8720 /* Add ethertype filter in SW list */
8722 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8723 struct i40e_ethertype_filter *filter)
8725 struct i40e_ethertype_rule *rule = &pf->ethertype;
8728 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8731 "Failed to insert ethertype filter"
8732 " to hash table %d!",
8736 rule->hash_map[ret] = filter;
8738 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8743 /* Delete ethertype filter in SW list */
8745 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8746 struct i40e_ethertype_filter_input *input)
8748 struct i40e_ethertype_rule *rule = &pf->ethertype;
8749 struct i40e_ethertype_filter *filter;
8752 ret = rte_hash_del_key(rule->hash_table, input);
8755 "Failed to delete ethertype filter"
8756 " to hash table %d!",
8760 filter = rule->hash_map[ret];
8761 rule->hash_map[ret] = NULL;
8763 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8770 * Configure ethertype filter, which can director packet by filtering
8771 * with mac address and ether_type or only ether_type
8774 i40e_ethertype_filter_set(struct i40e_pf *pf,
8775 struct rte_eth_ethertype_filter *filter,
8778 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8779 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8780 struct i40e_ethertype_filter *ethertype_filter, *node;
8781 struct i40e_ethertype_filter check_filter;
8782 struct i40e_control_filter_stats stats;
8786 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8787 PMD_DRV_LOG(ERR, "Invalid queue ID");
8790 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8791 filter->ether_type == ETHER_TYPE_IPv6) {
8793 "unsupported ether_type(0x%04x) in control packet filter.",
8794 filter->ether_type);
8797 if (filter->ether_type == ETHER_TYPE_VLAN)
8798 PMD_DRV_LOG(WARNING,
8799 "filter vlan ether_type in first tag is not supported.");
8801 /* Check if there is the filter in SW list */
8802 memset(&check_filter, 0, sizeof(check_filter));
8803 i40e_ethertype_filter_convert(filter, &check_filter);
8804 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8805 &check_filter.input);
8807 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8811 if (!add && !node) {
8812 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8816 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8817 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8818 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8819 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8820 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8822 memset(&stats, 0, sizeof(stats));
8823 ret = i40e_aq_add_rem_control_packet_filter(hw,
8824 filter->mac_addr.addr_bytes,
8825 filter->ether_type, flags,
8827 filter->queue, add, &stats, NULL);
8830 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8831 ret, stats.mac_etype_used, stats.etype_used,
8832 stats.mac_etype_free, stats.etype_free);
8836 /* Add or delete a filter in SW list */
8838 ethertype_filter = rte_zmalloc("ethertype_filter",
8839 sizeof(*ethertype_filter), 0);
8840 rte_memcpy(ethertype_filter, &check_filter,
8841 sizeof(check_filter));
8842 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8844 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8851 * Handle operations for ethertype filter.
8854 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8855 enum rte_filter_op filter_op,
8858 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8861 if (filter_op == RTE_ETH_FILTER_NOP)
8865 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8870 switch (filter_op) {
8871 case RTE_ETH_FILTER_ADD:
8872 ret = i40e_ethertype_filter_set(pf,
8873 (struct rte_eth_ethertype_filter *)arg,
8876 case RTE_ETH_FILTER_DELETE:
8877 ret = i40e_ethertype_filter_set(pf,
8878 (struct rte_eth_ethertype_filter *)arg,
8882 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8890 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8891 enum rte_filter_type filter_type,
8892 enum rte_filter_op filter_op,
8900 switch (filter_type) {
8901 case RTE_ETH_FILTER_NONE:
8902 /* For global configuration */
8903 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8905 case RTE_ETH_FILTER_HASH:
8906 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8908 case RTE_ETH_FILTER_MACVLAN:
8909 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8911 case RTE_ETH_FILTER_ETHERTYPE:
8912 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8914 case RTE_ETH_FILTER_TUNNEL:
8915 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8917 case RTE_ETH_FILTER_FDIR:
8918 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8920 case RTE_ETH_FILTER_GENERIC:
8921 if (filter_op != RTE_ETH_FILTER_GET)
8923 *(const void **)arg = &i40e_flow_ops;
8926 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8936 * Check and enable Extended Tag.
8937 * Enabling Extended Tag is important for 40G performance.
8940 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8942 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8946 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8949 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8953 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8954 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8959 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8962 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8966 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8967 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8970 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8971 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8974 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8981 * As some registers wouldn't be reset unless a global hardware reset,
8982 * hardware initialization is needed to put those registers into an
8983 * expected initial state.
8986 i40e_hw_init(struct rte_eth_dev *dev)
8988 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8990 i40e_enable_extended_tag(dev);
8992 /* clear the PF Queue Filter control register */
8993 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8995 /* Disable symmetric hash per port */
8996 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8999 enum i40e_filter_pctype
9000 i40e_flowtype_to_pctype(uint16_t flow_type)
9002 static const enum i40e_filter_pctype pctype_table[] = {
9003 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9004 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9005 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9006 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9007 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9008 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9009 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9010 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9011 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9012 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9013 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9014 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9015 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9016 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9017 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9018 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9019 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9020 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9021 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9024 return pctype_table[flow_type];
9028 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9030 static const uint16_t flowtype_table[] = {
9031 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9032 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9033 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9034 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9035 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9036 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9037 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9038 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9039 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9040 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9041 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9042 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9043 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9044 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9045 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9046 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9047 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9048 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9049 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9050 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9051 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9052 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9053 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9054 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9055 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9056 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9057 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9058 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9059 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9060 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9061 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9064 return flowtype_table[pctype];
9068 * On X710, performance number is far from the expectation on recent firmware
9069 * versions; on XL710, performance number is also far from the expectation on
9070 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9071 * mode is enabled and port MAC address is equal to the packet destination MAC
9072 * address. The fix for this issue may not be integrated in the following
9073 * firmware version. So the workaround in software driver is needed. It needs
9074 * to modify the initial values of 3 internal only registers for both X710 and
9075 * XL710. Note that the values for X710 or XL710 could be different, and the
9076 * workaround can be removed when it is fixed in firmware in the future.
9079 /* For both X710 and XL710 */
9080 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9081 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9083 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9084 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9087 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9088 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9091 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9093 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9094 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9097 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9099 enum i40e_status_code status;
9100 struct i40e_aq_get_phy_abilities_resp phy_ab;
9103 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9113 i40e_configure_registers(struct i40e_hw *hw)
9119 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9120 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9121 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9127 for (i = 0; i < RTE_DIM(reg_table); i++) {
9128 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9129 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9131 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9132 else /* For X710/XL710/XXV710 */
9134 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9137 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9138 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9140 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9141 else /* For X710/XL710/XXV710 */
9143 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9146 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9147 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9148 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9150 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9153 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9156 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9159 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9163 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9164 reg_table[i].addr, reg);
9165 if (reg == reg_table[i].val)
9168 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9169 reg_table[i].val, NULL);
9172 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9173 reg_table[i].val, reg_table[i].addr);
9176 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9177 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9181 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9182 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9183 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9184 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9186 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9191 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9192 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9196 /* Configure for double VLAN RX stripping */
9197 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9198 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9199 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9200 ret = i40e_aq_debug_write_register(hw,
9201 I40E_VSI_TSR(vsi->vsi_id),
9204 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9206 return I40E_ERR_CONFIG;
9210 /* Configure for double VLAN TX insertion */
9211 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9212 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9213 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9214 ret = i40e_aq_debug_write_register(hw,
9215 I40E_VSI_L2TAGSTXVALID(
9216 vsi->vsi_id), reg, NULL);
9219 "Failed to update VSI_L2TAGSTXVALID[%d]",
9221 return I40E_ERR_CONFIG;
9229 * i40e_aq_add_mirror_rule
9230 * @hw: pointer to the hardware structure
9231 * @seid: VEB seid to add mirror rule to
9232 * @dst_id: destination vsi seid
9233 * @entries: Buffer which contains the entities to be mirrored
9234 * @count: number of entities contained in the buffer
9235 * @rule_id:the rule_id of the rule to be added
9237 * Add a mirror rule for a given veb.
9240 static enum i40e_status_code
9241 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9242 uint16_t seid, uint16_t dst_id,
9243 uint16_t rule_type, uint16_t *entries,
9244 uint16_t count, uint16_t *rule_id)
9246 struct i40e_aq_desc desc;
9247 struct i40e_aqc_add_delete_mirror_rule cmd;
9248 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9249 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9252 enum i40e_status_code status;
9254 i40e_fill_default_direct_cmd_desc(&desc,
9255 i40e_aqc_opc_add_mirror_rule);
9256 memset(&cmd, 0, sizeof(cmd));
9258 buff_len = sizeof(uint16_t) * count;
9259 desc.datalen = rte_cpu_to_le_16(buff_len);
9261 desc.flags |= rte_cpu_to_le_16(
9262 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9263 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9264 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9265 cmd.num_entries = rte_cpu_to_le_16(count);
9266 cmd.seid = rte_cpu_to_le_16(seid);
9267 cmd.destination = rte_cpu_to_le_16(dst_id);
9269 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9270 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9272 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9273 hw->aq.asq_last_status, resp->rule_id,
9274 resp->mirror_rules_used, resp->mirror_rules_free);
9275 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9281 * i40e_aq_del_mirror_rule
9282 * @hw: pointer to the hardware structure
9283 * @seid: VEB seid to add mirror rule to
9284 * @entries: Buffer which contains the entities to be mirrored
9285 * @count: number of entities contained in the buffer
9286 * @rule_id:the rule_id of the rule to be delete
9288 * Delete a mirror rule for a given veb.
9291 static enum i40e_status_code
9292 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9293 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9294 uint16_t count, uint16_t rule_id)
9296 struct i40e_aq_desc desc;
9297 struct i40e_aqc_add_delete_mirror_rule cmd;
9298 uint16_t buff_len = 0;
9299 enum i40e_status_code status;
9302 i40e_fill_default_direct_cmd_desc(&desc,
9303 i40e_aqc_opc_delete_mirror_rule);
9304 memset(&cmd, 0, sizeof(cmd));
9305 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9306 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9308 cmd.num_entries = count;
9309 buff_len = sizeof(uint16_t) * count;
9310 desc.datalen = rte_cpu_to_le_16(buff_len);
9311 buff = (void *)entries;
9313 /* rule id is filled in destination field for deleting mirror rule */
9314 cmd.destination = rte_cpu_to_le_16(rule_id);
9316 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9317 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9318 cmd.seid = rte_cpu_to_le_16(seid);
9320 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9321 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9327 * i40e_mirror_rule_set
9328 * @dev: pointer to the hardware structure
9329 * @mirror_conf: mirror rule info
9330 * @sw_id: mirror rule's sw_id
9331 * @on: enable/disable
9333 * set a mirror rule.
9337 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9338 struct rte_eth_mirror_conf *mirror_conf,
9339 uint8_t sw_id, uint8_t on)
9341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9343 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9344 struct i40e_mirror_rule *parent = NULL;
9345 uint16_t seid, dst_seid, rule_id;
9349 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9351 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9353 "mirror rule can not be configured without veb or vfs.");
9356 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9357 PMD_DRV_LOG(ERR, "mirror table is full.");
9360 if (mirror_conf->dst_pool > pf->vf_num) {
9361 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9362 mirror_conf->dst_pool);
9366 seid = pf->main_vsi->veb->seid;
9368 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9369 if (sw_id <= it->index) {
9375 if (mirr_rule && sw_id == mirr_rule->index) {
9377 PMD_DRV_LOG(ERR, "mirror rule exists.");
9380 ret = i40e_aq_del_mirror_rule(hw, seid,
9381 mirr_rule->rule_type,
9383 mirr_rule->num_entries, mirr_rule->id);
9386 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9387 ret, hw->aq.asq_last_status);
9390 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9391 rte_free(mirr_rule);
9392 pf->nb_mirror_rule--;
9396 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9400 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9401 sizeof(struct i40e_mirror_rule) , 0);
9403 PMD_DRV_LOG(ERR, "failed to allocate memory");
9404 return I40E_ERR_NO_MEMORY;
9406 switch (mirror_conf->rule_type) {
9407 case ETH_MIRROR_VLAN:
9408 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9409 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9410 mirr_rule->entries[j] =
9411 mirror_conf->vlan.vlan_id[i];
9416 PMD_DRV_LOG(ERR, "vlan is not specified.");
9417 rte_free(mirr_rule);
9420 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9422 case ETH_MIRROR_VIRTUAL_POOL_UP:
9423 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9424 /* check if the specified pool bit is out of range */
9425 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9426 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9427 rte_free(mirr_rule);
9430 for (i = 0, j = 0; i < pf->vf_num; i++) {
9431 if (mirror_conf->pool_mask & (1ULL << i)) {
9432 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9436 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9437 /* add pf vsi to entries */
9438 mirr_rule->entries[j] = pf->main_vsi_seid;
9442 PMD_DRV_LOG(ERR, "pool is not specified.");
9443 rte_free(mirr_rule);
9446 /* egress and ingress in aq commands means from switch but not port */
9447 mirr_rule->rule_type =
9448 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9449 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9450 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9452 case ETH_MIRROR_UPLINK_PORT:
9453 /* egress and ingress in aq commands means from switch but not port*/
9454 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9456 case ETH_MIRROR_DOWNLINK_PORT:
9457 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9460 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9461 mirror_conf->rule_type);
9462 rte_free(mirr_rule);
9466 /* If the dst_pool is equal to vf_num, consider it as PF */
9467 if (mirror_conf->dst_pool == pf->vf_num)
9468 dst_seid = pf->main_vsi_seid;
9470 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9472 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9473 mirr_rule->rule_type, mirr_rule->entries,
9477 "failed to add mirror rule: ret = %d, aq_err = %d.",
9478 ret, hw->aq.asq_last_status);
9479 rte_free(mirr_rule);
9483 mirr_rule->index = sw_id;
9484 mirr_rule->num_entries = j;
9485 mirr_rule->id = rule_id;
9486 mirr_rule->dst_vsi_seid = dst_seid;
9489 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9491 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9493 pf->nb_mirror_rule++;
9498 * i40e_mirror_rule_reset
9499 * @dev: pointer to the device
9500 * @sw_id: mirror rule's sw_id
9502 * reset a mirror rule.
9506 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9509 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9510 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9514 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9516 seid = pf->main_vsi->veb->seid;
9518 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9519 if (sw_id == it->index) {
9525 ret = i40e_aq_del_mirror_rule(hw, seid,
9526 mirr_rule->rule_type,
9528 mirr_rule->num_entries, mirr_rule->id);
9531 "failed to remove mirror rule: status = %d, aq_err = %d.",
9532 ret, hw->aq.asq_last_status);
9535 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9536 rte_free(mirr_rule);
9537 pf->nb_mirror_rule--;
9539 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9546 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9549 uint64_t systim_cycles;
9551 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9552 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9555 return systim_cycles;
9559 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9561 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9564 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9565 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9572 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9574 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9577 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9578 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9585 i40e_start_timecounters(struct rte_eth_dev *dev)
9587 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9588 struct i40e_adapter *adapter =
9589 (struct i40e_adapter *)dev->data->dev_private;
9590 struct rte_eth_link link;
9591 uint32_t tsync_inc_l;
9592 uint32_t tsync_inc_h;
9594 /* Get current link speed. */
9595 memset(&link, 0, sizeof(link));
9596 i40e_dev_link_update(dev, 1);
9597 rte_i40e_dev_atomic_read_link_status(dev, &link);
9599 switch (link.link_speed) {
9600 case ETH_SPEED_NUM_40G:
9601 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9602 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9604 case ETH_SPEED_NUM_10G:
9605 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9606 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9608 case ETH_SPEED_NUM_1G:
9609 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9610 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9617 /* Set the timesync increment value. */
9618 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9619 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9621 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9622 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9623 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9625 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9626 adapter->systime_tc.cc_shift = 0;
9627 adapter->systime_tc.nsec_mask = 0;
9629 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9630 adapter->rx_tstamp_tc.cc_shift = 0;
9631 adapter->rx_tstamp_tc.nsec_mask = 0;
9633 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9634 adapter->tx_tstamp_tc.cc_shift = 0;
9635 adapter->tx_tstamp_tc.nsec_mask = 0;
9639 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9641 struct i40e_adapter *adapter =
9642 (struct i40e_adapter *)dev->data->dev_private;
9644 adapter->systime_tc.nsec += delta;
9645 adapter->rx_tstamp_tc.nsec += delta;
9646 adapter->tx_tstamp_tc.nsec += delta;
9652 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9655 struct i40e_adapter *adapter =
9656 (struct i40e_adapter *)dev->data->dev_private;
9658 ns = rte_timespec_to_ns(ts);
9660 /* Set the timecounters to a new value. */
9661 adapter->systime_tc.nsec = ns;
9662 adapter->rx_tstamp_tc.nsec = ns;
9663 adapter->tx_tstamp_tc.nsec = ns;
9669 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9671 uint64_t ns, systime_cycles;
9672 struct i40e_adapter *adapter =
9673 (struct i40e_adapter *)dev->data->dev_private;
9675 systime_cycles = i40e_read_systime_cyclecounter(dev);
9676 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9677 *ts = rte_ns_to_timespec(ns);
9683 i40e_timesync_enable(struct rte_eth_dev *dev)
9685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9686 uint32_t tsync_ctl_l;
9687 uint32_t tsync_ctl_h;
9689 /* Stop the timesync system time. */
9690 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9691 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9692 /* Reset the timesync system time value. */
9693 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9694 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9696 i40e_start_timecounters(dev);
9698 /* Clear timesync registers. */
9699 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9700 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9701 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9702 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9703 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9704 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9706 /* Enable timestamping of PTP packets. */
9707 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9708 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9710 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9711 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9712 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9714 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9715 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9721 i40e_timesync_disable(struct rte_eth_dev *dev)
9723 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9724 uint32_t tsync_ctl_l;
9725 uint32_t tsync_ctl_h;
9727 /* Disable timestamping of transmitted PTP packets. */
9728 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9729 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9731 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9732 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9734 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9735 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9737 /* Reset the timesync increment value. */
9738 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9739 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9745 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9746 struct timespec *timestamp, uint32_t flags)
9748 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9749 struct i40e_adapter *adapter =
9750 (struct i40e_adapter *)dev->data->dev_private;
9752 uint32_t sync_status;
9753 uint32_t index = flags & 0x03;
9754 uint64_t rx_tstamp_cycles;
9757 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9758 if ((sync_status & (1 << index)) == 0)
9761 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9762 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9763 *timestamp = rte_ns_to_timespec(ns);
9769 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9770 struct timespec *timestamp)
9772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9773 struct i40e_adapter *adapter =
9774 (struct i40e_adapter *)dev->data->dev_private;
9776 uint32_t sync_status;
9777 uint64_t tx_tstamp_cycles;
9780 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9781 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9784 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9785 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9786 *timestamp = rte_ns_to_timespec(ns);
9792 * i40e_parse_dcb_configure - parse dcb configure from user
9793 * @dev: the device being configured
9794 * @dcb_cfg: pointer of the result of parse
9795 * @*tc_map: bit map of enabled traffic classes
9797 * Returns 0 on success, negative value on failure
9800 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9801 struct i40e_dcbx_config *dcb_cfg,
9804 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9805 uint8_t i, tc_bw, bw_lf;
9807 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9809 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9810 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9811 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9815 /* assume each tc has the same bw */
9816 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9817 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9818 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9819 /* to ensure the sum of tcbw is equal to 100 */
9820 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9821 for (i = 0; i < bw_lf; i++)
9822 dcb_cfg->etscfg.tcbwtable[i]++;
9824 /* assume each tc has the same Transmission Selection Algorithm */
9825 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9826 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9828 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9829 dcb_cfg->etscfg.prioritytable[i] =
9830 dcb_rx_conf->dcb_tc[i];
9832 /* FW needs one App to configure HW */
9833 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9834 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9835 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9836 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9838 if (dcb_rx_conf->nb_tcs == 0)
9839 *tc_map = 1; /* tc0 only */
9841 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9843 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9844 dcb_cfg->pfc.willing = 0;
9845 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9846 dcb_cfg->pfc.pfcenable = *tc_map;
9852 static enum i40e_status_code
9853 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9854 struct i40e_aqc_vsi_properties_data *info,
9855 uint8_t enabled_tcmap)
9857 enum i40e_status_code ret;
9858 int i, total_tc = 0;
9859 uint16_t qpnum_per_tc, bsf, qp_idx;
9860 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9861 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9862 uint16_t used_queues;
9864 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9865 if (ret != I40E_SUCCESS)
9868 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9869 if (enabled_tcmap & (1 << i))
9874 vsi->enabled_tc = enabled_tcmap;
9876 /* different VSI has different queues assigned */
9877 if (vsi->type == I40E_VSI_MAIN)
9878 used_queues = dev_data->nb_rx_queues -
9879 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9880 else if (vsi->type == I40E_VSI_VMDQ2)
9881 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9883 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9884 return I40E_ERR_NO_AVAILABLE_VSI;
9887 qpnum_per_tc = used_queues / total_tc;
9888 /* Number of queues per enabled TC */
9889 if (qpnum_per_tc == 0) {
9890 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9891 return I40E_ERR_INVALID_QP_ID;
9893 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9895 bsf = rte_bsf32(qpnum_per_tc);
9898 * Configure TC and queue mapping parameters, for enabled TC,
9899 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9900 * default queue will serve it.
9903 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9904 if (vsi->enabled_tc & (1 << i)) {
9905 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9906 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9907 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9908 qp_idx += qpnum_per_tc;
9910 info->tc_mapping[i] = 0;
9913 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9914 if (vsi->type == I40E_VSI_SRIOV) {
9915 info->mapping_flags |=
9916 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9917 for (i = 0; i < vsi->nb_qps; i++)
9918 info->queue_mapping[i] =
9919 rte_cpu_to_le_16(vsi->base_queue + i);
9921 info->mapping_flags |=
9922 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9923 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9925 info->valid_sections |=
9926 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9928 return I40E_SUCCESS;
9932 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9933 * @veb: VEB to be configured
9934 * @tc_map: enabled TC bitmap
9936 * Returns 0 on success, negative value on failure
9938 static enum i40e_status_code
9939 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9941 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9942 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9943 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9944 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9945 enum i40e_status_code ret = I40E_SUCCESS;
9949 /* Check if enabled_tc is same as existing or new TCs */
9950 if (veb->enabled_tc == tc_map)
9953 /* configure tc bandwidth */
9954 memset(&veb_bw, 0, sizeof(veb_bw));
9955 veb_bw.tc_valid_bits = tc_map;
9956 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9957 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9958 if (tc_map & BIT_ULL(i))
9959 veb_bw.tc_bw_share_credits[i] = 1;
9961 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9965 "AQ command Config switch_comp BW allocation per TC failed = %d",
9966 hw->aq.asq_last_status);
9970 memset(&ets_query, 0, sizeof(ets_query));
9971 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9973 if (ret != I40E_SUCCESS) {
9975 "Failed to get switch_comp ETS configuration %u",
9976 hw->aq.asq_last_status);
9979 memset(&bw_query, 0, sizeof(bw_query));
9980 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9982 if (ret != I40E_SUCCESS) {
9984 "Failed to get switch_comp bandwidth configuration %u",
9985 hw->aq.asq_last_status);
9989 /* store and print out BW info */
9990 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9991 veb->bw_info.bw_max = ets_query.tc_bw_max;
9992 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9993 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9994 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9995 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9997 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9998 veb->bw_info.bw_ets_share_credits[i] =
9999 bw_query.tc_bw_share_credits[i];
10000 veb->bw_info.bw_ets_credits[i] =
10001 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10002 /* 4 bits per TC, 4th bit is reserved */
10003 veb->bw_info.bw_ets_max[i] =
10004 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10005 RTE_LEN2MASK(3, uint8_t));
10006 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10007 veb->bw_info.bw_ets_share_credits[i]);
10008 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10009 veb->bw_info.bw_ets_credits[i]);
10010 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10011 veb->bw_info.bw_ets_max[i]);
10014 veb->enabled_tc = tc_map;
10021 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10022 * @vsi: VSI to be configured
10023 * @tc_map: enabled TC bitmap
10025 * Returns 0 on success, negative value on failure
10027 static enum i40e_status_code
10028 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10030 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10031 struct i40e_vsi_context ctxt;
10032 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10033 enum i40e_status_code ret = I40E_SUCCESS;
10036 /* Check if enabled_tc is same as existing or new TCs */
10037 if (vsi->enabled_tc == tc_map)
10040 /* configure tc bandwidth */
10041 memset(&bw_data, 0, sizeof(bw_data));
10042 bw_data.tc_valid_bits = tc_map;
10043 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10044 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10045 if (tc_map & BIT_ULL(i))
10046 bw_data.tc_bw_credits[i] = 1;
10048 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10051 "AQ command Config VSI BW allocation per TC failed = %d",
10052 hw->aq.asq_last_status);
10055 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10056 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10058 /* Update Queue Pairs Mapping for currently enabled UPs */
10059 ctxt.seid = vsi->seid;
10060 ctxt.pf_num = hw->pf_id;
10062 ctxt.uplink_seid = vsi->uplink_seid;
10063 ctxt.info = vsi->info;
10065 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10069 /* Update the VSI after updating the VSI queue-mapping information */
10070 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10072 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10073 hw->aq.asq_last_status);
10076 /* update the local VSI info with updated queue map */
10077 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10078 sizeof(vsi->info.tc_mapping));
10079 (void)rte_memcpy(&vsi->info.queue_mapping,
10080 &ctxt.info.queue_mapping,
10081 sizeof(vsi->info.queue_mapping));
10082 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10083 vsi->info.valid_sections = 0;
10085 /* query and update current VSI BW information */
10086 ret = i40e_vsi_get_bw_config(vsi);
10089 "Failed updating vsi bw info, err %s aq_err %s",
10090 i40e_stat_str(hw, ret),
10091 i40e_aq_str(hw, hw->aq.asq_last_status));
10095 vsi->enabled_tc = tc_map;
10102 * i40e_dcb_hw_configure - program the dcb setting to hw
10103 * @pf: pf the configuration is taken on
10104 * @new_cfg: new configuration
10105 * @tc_map: enabled TC bitmap
10107 * Returns 0 on success, negative value on failure
10109 static enum i40e_status_code
10110 i40e_dcb_hw_configure(struct i40e_pf *pf,
10111 struct i40e_dcbx_config *new_cfg,
10114 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10115 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10116 struct i40e_vsi *main_vsi = pf->main_vsi;
10117 struct i40e_vsi_list *vsi_list;
10118 enum i40e_status_code ret;
10122 /* Use the FW API if FW > v4.4*/
10123 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10124 (hw->aq.fw_maj_ver >= 5))) {
10126 "FW < v4.4, can not use FW LLDP API to configure DCB");
10127 return I40E_ERR_FIRMWARE_API_VERSION;
10130 /* Check if need reconfiguration */
10131 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10132 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10133 return I40E_SUCCESS;
10136 /* Copy the new config to the current config */
10137 *old_cfg = *new_cfg;
10138 old_cfg->etsrec = old_cfg->etscfg;
10139 ret = i40e_set_dcb_config(hw);
10141 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10142 i40e_stat_str(hw, ret),
10143 i40e_aq_str(hw, hw->aq.asq_last_status));
10146 /* set receive Arbiter to RR mode and ETS scheme by default */
10147 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10148 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10149 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10150 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10151 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10152 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10153 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10154 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10155 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10156 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10157 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10158 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10159 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10161 /* get local mib to check whether it is configured correctly */
10163 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10164 /* Get Local DCB Config */
10165 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10166 &hw->local_dcbx_config);
10168 /* if Veb is created, need to update TC of it at first */
10169 if (main_vsi->veb) {
10170 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10172 PMD_INIT_LOG(WARNING,
10173 "Failed configuring TC for VEB seid=%d",
10174 main_vsi->veb->seid);
10176 /* Update each VSI */
10177 i40e_vsi_config_tc(main_vsi, tc_map);
10178 if (main_vsi->veb) {
10179 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10180 /* Beside main VSI and VMDQ VSIs, only enable default
10181 * TC for other VSIs
10183 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10184 ret = i40e_vsi_config_tc(vsi_list->vsi,
10187 ret = i40e_vsi_config_tc(vsi_list->vsi,
10188 I40E_DEFAULT_TCMAP);
10190 PMD_INIT_LOG(WARNING,
10191 "Failed configuring TC for VSI seid=%d",
10192 vsi_list->vsi->seid);
10196 return I40E_SUCCESS;
10200 * i40e_dcb_init_configure - initial dcb config
10201 * @dev: device being configured
10202 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10204 * Returns 0 on success, negative value on failure
10207 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10209 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10210 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10213 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10214 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10218 /* DCB initialization:
10219 * Update DCB configuration from the Firmware and configure
10220 * LLDP MIB change event.
10222 if (sw_dcb == TRUE) {
10223 ret = i40e_init_dcb(hw);
10224 /* If lldp agent is stopped, the return value from
10225 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10226 * adminq status. Otherwise, it should return success.
10228 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10229 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10230 memset(&hw->local_dcbx_config, 0,
10231 sizeof(struct i40e_dcbx_config));
10232 /* set dcb default configuration */
10233 hw->local_dcbx_config.etscfg.willing = 0;
10234 hw->local_dcbx_config.etscfg.maxtcs = 0;
10235 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10236 hw->local_dcbx_config.etscfg.tsatable[0] =
10238 /* all UPs mapping to TC0 */
10239 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10240 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10241 hw->local_dcbx_config.etsrec =
10242 hw->local_dcbx_config.etscfg;
10243 hw->local_dcbx_config.pfc.willing = 0;
10244 hw->local_dcbx_config.pfc.pfccap =
10245 I40E_MAX_TRAFFIC_CLASS;
10246 hw->local_dcbx_config.pfc.pfcenable =
10247 I40E_DEFAULT_TCMAP;
10248 /* FW needs one App to configure HW */
10249 hw->local_dcbx_config.numapps = 1;
10250 hw->local_dcbx_config.app[0].selector =
10251 I40E_APP_SEL_ETHTYPE;
10252 hw->local_dcbx_config.app[0].priority = 3;
10253 hw->local_dcbx_config.app[0].protocolid =
10254 I40E_APP_PROTOID_FCOE;
10255 ret = i40e_set_dcb_config(hw);
10258 "default dcb config fails. err = %d, aq_err = %d.",
10259 ret, hw->aq.asq_last_status);
10264 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10265 ret, hw->aq.asq_last_status);
10269 ret = i40e_aq_start_lldp(hw, NULL);
10270 if (ret != I40E_SUCCESS)
10271 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10273 ret = i40e_init_dcb(hw);
10275 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10277 "HW doesn't support DCBX offload.");
10282 "DCBX configuration failed, err = %d, aq_err = %d.",
10283 ret, hw->aq.asq_last_status);
10291 * i40e_dcb_setup - setup dcb related config
10292 * @dev: device being configured
10294 * Returns 0 on success, negative value on failure
10297 i40e_dcb_setup(struct rte_eth_dev *dev)
10299 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10300 struct i40e_dcbx_config dcb_cfg;
10301 uint8_t tc_map = 0;
10304 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10305 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10309 if (pf->vf_num != 0)
10310 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10312 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10314 PMD_INIT_LOG(ERR, "invalid dcb config");
10317 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10319 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10327 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10328 struct rte_eth_dcb_info *dcb_info)
10330 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10331 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10332 struct i40e_vsi *vsi = pf->main_vsi;
10333 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10334 uint16_t bsf, tc_mapping;
10337 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10338 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10340 dcb_info->nb_tcs = 1;
10341 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10342 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10343 for (i = 0; i < dcb_info->nb_tcs; i++)
10344 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10346 /* get queue mapping if vmdq is disabled */
10347 if (!pf->nb_cfg_vmdq_vsi) {
10348 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10349 if (!(vsi->enabled_tc & (1 << i)))
10351 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10352 dcb_info->tc_queue.tc_rxq[j][i].base =
10353 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10354 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10355 dcb_info->tc_queue.tc_txq[j][i].base =
10356 dcb_info->tc_queue.tc_rxq[j][i].base;
10357 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10358 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10359 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10360 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10361 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10366 /* get queue mapping if vmdq is enabled */
10368 vsi = pf->vmdq[j].vsi;
10369 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10370 if (!(vsi->enabled_tc & (1 << i)))
10372 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10373 dcb_info->tc_queue.tc_rxq[j][i].base =
10374 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10375 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10376 dcb_info->tc_queue.tc_txq[j][i].base =
10377 dcb_info->tc_queue.tc_rxq[j][i].base;
10378 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10379 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10380 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10381 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10382 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10385 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10390 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10392 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10393 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10394 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10395 uint16_t interval =
10396 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10397 uint16_t msix_intr;
10399 msix_intr = intr_handle->intr_vec[queue_id];
10400 if (msix_intr == I40E_MISC_VEC_ID)
10401 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10402 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10403 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10404 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10406 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10409 I40E_PFINT_DYN_CTLN(msix_intr -
10410 I40E_RX_VEC_START),
10411 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10412 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10413 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10415 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10417 I40E_WRITE_FLUSH(hw);
10418 rte_intr_enable(&pci_dev->intr_handle);
10424 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10426 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10427 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10428 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10429 uint16_t msix_intr;
10431 msix_intr = intr_handle->intr_vec[queue_id];
10432 if (msix_intr == I40E_MISC_VEC_ID)
10433 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10436 I40E_PFINT_DYN_CTLN(msix_intr -
10437 I40E_RX_VEC_START),
10439 I40E_WRITE_FLUSH(hw);
10444 static int i40e_get_regs(struct rte_eth_dev *dev,
10445 struct rte_dev_reg_info *regs)
10447 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10448 uint32_t *ptr_data = regs->data;
10449 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10450 const struct i40e_reg_info *reg_info;
10452 if (ptr_data == NULL) {
10453 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10454 regs->width = sizeof(uint32_t);
10458 /* The first few registers have to be read using AQ operations */
10460 while (i40e_regs_adminq[reg_idx].name) {
10461 reg_info = &i40e_regs_adminq[reg_idx++];
10462 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10464 arr_idx2 <= reg_info->count2;
10466 reg_offset = arr_idx * reg_info->stride1 +
10467 arr_idx2 * reg_info->stride2;
10468 reg_offset += reg_info->base_addr;
10469 ptr_data[reg_offset >> 2] =
10470 i40e_read_rx_ctl(hw, reg_offset);
10474 /* The remaining registers can be read using primitives */
10476 while (i40e_regs_others[reg_idx].name) {
10477 reg_info = &i40e_regs_others[reg_idx++];
10478 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10480 arr_idx2 <= reg_info->count2;
10482 reg_offset = arr_idx * reg_info->stride1 +
10483 arr_idx2 * reg_info->stride2;
10484 reg_offset += reg_info->base_addr;
10485 ptr_data[reg_offset >> 2] =
10486 I40E_READ_REG(hw, reg_offset);
10493 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10495 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10497 /* Convert word count to byte count */
10498 return hw->nvm.sr_size << 1;
10501 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10502 struct rte_dev_eeprom_info *eeprom)
10504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10505 uint16_t *data = eeprom->data;
10506 uint16_t offset, length, cnt_words;
10509 offset = eeprom->offset >> 1;
10510 length = eeprom->length >> 1;
10511 cnt_words = length;
10513 if (offset > hw->nvm.sr_size ||
10514 offset + length > hw->nvm.sr_size) {
10515 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10519 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10521 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10522 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10523 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10530 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10531 struct ether_addr *mac_addr)
10533 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10535 if (!is_valid_assigned_ether_addr(mac_addr)) {
10536 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10540 /* Flags: 0x3 updates port address */
10541 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10545 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10548 struct rte_eth_dev_data *dev_data = pf->dev_data;
10549 uint32_t frame_size = mtu + ETHER_HDR_LEN
10550 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10553 /* check if mtu is within the allowed range */
10554 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10557 /* mtu setting is forbidden if port is start */
10558 if (dev_data->dev_started) {
10559 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10560 dev_data->port_id);
10564 if (frame_size > ETHER_MAX_LEN)
10565 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10567 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10569 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10574 /* Restore ethertype filter */
10576 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10578 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10579 struct i40e_ethertype_filter_list
10580 *ethertype_list = &pf->ethertype.ethertype_list;
10581 struct i40e_ethertype_filter *f;
10582 struct i40e_control_filter_stats stats;
10585 TAILQ_FOREACH(f, ethertype_list, rules) {
10587 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10588 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10589 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10590 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10591 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10593 memset(&stats, 0, sizeof(stats));
10594 i40e_aq_add_rem_control_packet_filter(hw,
10595 f->input.mac_addr.addr_bytes,
10596 f->input.ether_type,
10597 flags, pf->main_vsi->seid,
10598 f->queue, 1, &stats, NULL);
10600 PMD_DRV_LOG(INFO, "Ethertype filter:"
10601 " mac_etype_used = %u, etype_used = %u,"
10602 " mac_etype_free = %u, etype_free = %u",
10603 stats.mac_etype_used, stats.etype_used,
10604 stats.mac_etype_free, stats.etype_free);
10607 /* Restore tunnel filter */
10609 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10611 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10612 struct i40e_vsi *vsi = pf->main_vsi;
10613 struct i40e_tunnel_filter_list
10614 *tunnel_list = &pf->tunnel.tunnel_list;
10615 struct i40e_tunnel_filter *f;
10616 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10617 bool big_buffer = 0;
10619 TAILQ_FOREACH(f, tunnel_list, rules) {
10620 memset(&cld_filter, 0, sizeof(cld_filter));
10621 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10622 (struct ether_addr *)&cld_filter.element.outer_mac);
10623 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10624 (struct ether_addr *)&cld_filter.element.inner_mac);
10625 cld_filter.element.inner_vlan = f->input.inner_vlan;
10626 cld_filter.element.flags = f->input.flags;
10627 cld_filter.element.tenant_id = f->input.tenant_id;
10628 cld_filter.element.queue_number = f->queue;
10629 rte_memcpy(cld_filter.general_fields,
10630 f->input.general_fields,
10631 sizeof(f->input.general_fields));
10633 if (((f->input.flags &
10634 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10635 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10637 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10638 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE))
10642 i40e_aq_add_cloud_filters_big_buffer(hw,
10643 vsi->seid, &cld_filter, 1);
10645 i40e_aq_add_cloud_filters(hw, vsi->seid,
10646 &cld_filter.element, 1);
10651 i40e_filter_restore(struct i40e_pf *pf)
10653 i40e_ethertype_filter_restore(pf);
10654 i40e_tunnel_filter_restore(pf);
10655 i40e_fdir_filter_restore(pf);
10659 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10661 if (strcmp(dev->driver->pci_drv.driver.name,
10662 drv->pci_drv.driver.name))
10669 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10671 struct rte_eth_dev *dev;
10672 struct i40e_pf *pf;
10674 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10676 dev = &rte_eth_devices[port];
10678 if (!is_device_supported(dev, &rte_i40e_pmd))
10681 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10683 if (vf >= pf->vf_num || !pf->vfs) {
10684 PMD_DRV_LOG(ERR, "Invalid argument.");
10688 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10694 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10696 struct rte_eth_dev *dev;
10697 struct i40e_pf *pf;
10698 struct i40e_vsi *vsi;
10699 struct i40e_hw *hw;
10700 struct i40e_vsi_context ctxt;
10703 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10705 dev = &rte_eth_devices[port];
10707 if (!is_device_supported(dev, &rte_i40e_pmd))
10710 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10712 if (vf_id >= pf->vf_num || !pf->vfs) {
10713 PMD_DRV_LOG(ERR, "Invalid argument.");
10717 vsi = pf->vfs[vf_id].vsi;
10719 PMD_DRV_LOG(ERR, "Invalid VSI.");
10723 /* Check if it has been already on or off */
10724 if (vsi->info.valid_sections &
10725 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10727 if ((vsi->info.sec_flags &
10728 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10729 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10730 return 0; /* already on */
10732 if ((vsi->info.sec_flags &
10733 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10734 return 0; /* already off */
10738 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10740 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10742 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10744 memset(&ctxt, 0, sizeof(ctxt));
10745 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10746 ctxt.seid = vsi->seid;
10748 hw = I40E_VSI_TO_HW(vsi);
10749 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10750 if (ret != I40E_SUCCESS) {
10752 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10759 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10763 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10764 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10767 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10771 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10772 if (!(vsi->vfta[j] & (1 << k)))
10775 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10779 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10781 ret = i40e_aq_add_vlan(hw, vsi->seid,
10782 &vlan_data, 1, NULL);
10784 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10785 &vlan_data, 1, NULL);
10786 if (ret != I40E_SUCCESS) {
10788 "Failed to add/rm vlan filter");
10794 return I40E_SUCCESS;
10798 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10800 struct rte_eth_dev *dev;
10801 struct i40e_pf *pf;
10802 struct i40e_vsi *vsi;
10803 struct i40e_hw *hw;
10804 struct i40e_vsi_context ctxt;
10807 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10809 dev = &rte_eth_devices[port];
10811 if (!is_device_supported(dev, &rte_i40e_pmd))
10814 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10816 if (vf_id >= pf->vf_num || !pf->vfs) {
10817 PMD_DRV_LOG(ERR, "Invalid argument.");
10821 vsi = pf->vfs[vf_id].vsi;
10823 PMD_DRV_LOG(ERR, "Invalid VSI.");
10827 /* Check if it has been already on or off */
10828 if (vsi->vlan_anti_spoof_on == on)
10829 return 0; /* already on or off */
10831 vsi->vlan_anti_spoof_on = on;
10832 if (!vsi->vlan_filter_on) {
10833 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10835 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10840 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10842 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10844 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10846 memset(&ctxt, 0, sizeof(ctxt));
10847 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10848 ctxt.seid = vsi->seid;
10850 hw = I40E_VSI_TO_HW(vsi);
10851 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10852 if (ret != I40E_SUCCESS) {
10854 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10861 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10863 struct i40e_mac_filter *f;
10864 struct i40e_macvlan_filter *mv_f;
10866 enum rte_mac_filter_type filter_type;
10867 int ret = I40E_SUCCESS;
10870 /* remove all the MACs */
10871 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10872 vlan_num = vsi->vlan_num;
10873 filter_type = f->mac_info.filter_type;
10874 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10875 filter_type == RTE_MACVLAN_HASH_MATCH) {
10876 if (vlan_num == 0) {
10877 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10878 return I40E_ERR_PARAM;
10880 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10881 filter_type == RTE_MAC_HASH_MATCH)
10884 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10886 PMD_DRV_LOG(ERR, "failed to allocate memory");
10887 return I40E_ERR_NO_MEMORY;
10890 for (i = 0; i < vlan_num; i++) {
10891 mv_f[i].filter_type = filter_type;
10892 (void)rte_memcpy(&mv_f[i].macaddr,
10893 &f->mac_info.mac_addr,
10896 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10897 filter_type == RTE_MACVLAN_HASH_MATCH) {
10898 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10899 &f->mac_info.mac_addr);
10900 if (ret != I40E_SUCCESS) {
10906 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10907 if (ret != I40E_SUCCESS) {
10913 ret = I40E_SUCCESS;
10920 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10922 struct i40e_mac_filter *f;
10923 struct i40e_macvlan_filter *mv_f;
10924 int i, vlan_num = 0;
10925 int ret = I40E_SUCCESS;
10928 /* restore all the MACs */
10929 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10930 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10931 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10933 * If vlan_num is 0, that's the first time to add mac,
10934 * set mask for vlan_id 0.
10936 if (vsi->vlan_num == 0) {
10937 i40e_set_vlan_filter(vsi, 0, 1);
10940 vlan_num = vsi->vlan_num;
10941 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10942 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10945 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10947 PMD_DRV_LOG(ERR, "failed to allocate memory");
10948 return I40E_ERR_NO_MEMORY;
10951 for (i = 0; i < vlan_num; i++) {
10952 mv_f[i].filter_type = f->mac_info.filter_type;
10953 (void)rte_memcpy(&mv_f[i].macaddr,
10954 &f->mac_info.mac_addr,
10958 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10959 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10960 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10961 &f->mac_info.mac_addr);
10962 if (ret != I40E_SUCCESS) {
10968 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10969 if (ret != I40E_SUCCESS) {
10975 ret = I40E_SUCCESS;
10982 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10984 struct i40e_vsi_context ctxt;
10985 struct i40e_hw *hw;
10991 hw = I40E_VSI_TO_HW(vsi);
10993 /* Use the FW API if FW >= v5.0 */
10994 if (hw->aq.fw_maj_ver < 5) {
10995 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10999 /* Check if it has been already on or off */
11000 if (vsi->info.valid_sections &
11001 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
11003 if ((vsi->info.switch_id &
11004 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
11005 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
11006 return 0; /* already on */
11008 if ((vsi->info.switch_id &
11009 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11010 return 0; /* already off */
11014 /* remove all the MAC and VLAN first */
11015 ret = i40e_vsi_rm_mac_filter(vsi);
11017 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11020 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11021 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11023 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11028 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11030 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11032 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11034 memset(&ctxt, 0, sizeof(ctxt));
11035 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11036 ctxt.seid = vsi->seid;
11038 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11039 if (ret != I40E_SUCCESS) {
11040 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11044 /* add all the MAC and VLAN back */
11045 ret = i40e_vsi_restore_mac_filter(vsi);
11048 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11049 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11058 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11060 struct rte_eth_dev *dev;
11061 struct i40e_pf *pf;
11062 struct i40e_pf_vf *vf;
11063 struct i40e_vsi *vsi;
11067 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11069 dev = &rte_eth_devices[port];
11071 if (!is_device_supported(dev, &rte_i40e_pmd))
11074 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11076 /* setup PF TX loopback */
11077 vsi = pf->main_vsi;
11078 ret = i40e_vsi_set_tx_loopback(vsi, on);
11082 /* setup TX loopback for all the VFs */
11084 /* if no VF, do nothing. */
11088 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11089 vf = &pf->vfs[vf_id];
11092 ret = i40e_vsi_set_tx_loopback(vsi, on);
11101 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11103 struct rte_eth_dev *dev;
11104 struct i40e_pf *pf;
11105 struct i40e_vsi *vsi;
11106 struct i40e_hw *hw;
11109 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11111 dev = &rte_eth_devices[port];
11113 if (!is_device_supported(dev, &rte_i40e_pmd))
11116 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11118 if (vf_id >= pf->vf_num || !pf->vfs) {
11119 PMD_DRV_LOG(ERR, "Invalid argument.");
11123 vsi = pf->vfs[vf_id].vsi;
11125 PMD_DRV_LOG(ERR, "Invalid VSI.");
11129 hw = I40E_VSI_TO_HW(vsi);
11131 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11133 if (ret != I40E_SUCCESS) {
11135 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11142 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11144 struct rte_eth_dev *dev;
11145 struct i40e_pf *pf;
11146 struct i40e_vsi *vsi;
11147 struct i40e_hw *hw;
11150 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11152 dev = &rte_eth_devices[port];
11154 if (!is_device_supported(dev, &rte_i40e_pmd))
11157 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11159 if (vf_id >= pf->vf_num || !pf->vfs) {
11160 PMD_DRV_LOG(ERR, "Invalid argument.");
11164 vsi = pf->vfs[vf_id].vsi;
11166 PMD_DRV_LOG(ERR, "Invalid VSI.");
11170 hw = I40E_VSI_TO_HW(vsi);
11172 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11174 if (ret != I40E_SUCCESS) {
11176 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11183 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11184 struct ether_addr *mac_addr)
11186 struct i40e_mac_filter *f;
11187 struct rte_eth_dev *dev;
11188 struct i40e_pf_vf *vf;
11189 struct i40e_vsi *vsi;
11190 struct i40e_pf *pf;
11193 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11196 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11198 dev = &rte_eth_devices[port];
11200 if (!is_device_supported(dev, &rte_i40e_pmd))
11203 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11205 if (vf_id >= pf->vf_num || !pf->vfs)
11208 vf = &pf->vfs[vf_id];
11211 PMD_DRV_LOG(ERR, "Invalid VSI.");
11215 ether_addr_copy(mac_addr, &vf->mac_addr);
11217 /* Remove all existing mac */
11218 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11219 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11224 /* Set vlan strip on/off for specific VF from host */
11226 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11228 struct rte_eth_dev *dev;
11229 struct i40e_pf *pf;
11230 struct i40e_vsi *vsi;
11233 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11235 dev = &rte_eth_devices[port];
11237 if (!is_device_supported(dev, &rte_i40e_pmd))
11240 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11242 if (vf_id >= pf->vf_num || !pf->vfs) {
11243 PMD_DRV_LOG(ERR, "Invalid argument.");
11247 vsi = pf->vfs[vf_id].vsi;
11252 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11253 if (ret != I40E_SUCCESS) {
11255 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11261 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11264 struct rte_eth_dev *dev;
11265 struct i40e_pf *pf;
11266 struct i40e_hw *hw;
11267 struct i40e_vsi *vsi;
11268 struct i40e_vsi_context ctxt;
11271 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11273 if (vlan_id > ETHER_MAX_VLAN_ID) {
11274 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11278 dev = &rte_eth_devices[port];
11280 if (!is_device_supported(dev, &rte_i40e_pmd))
11283 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11284 hw = I40E_PF_TO_HW(pf);
11287 * return -ENODEV if SRIOV not enabled, VF number not configured
11288 * or no queue assigned.
11290 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11291 pf->vf_nb_qps == 0)
11294 if (vf_id >= pf->vf_num || !pf->vfs) {
11295 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11299 vsi = pf->vfs[vf_id].vsi;
11301 PMD_DRV_LOG(ERR, "Invalid VSI.");
11305 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11306 vsi->info.pvid = vlan_id;
11308 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11310 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11312 memset(&ctxt, 0, sizeof(ctxt));
11313 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11314 ctxt.seid = vsi->seid;
11316 hw = I40E_VSI_TO_HW(vsi);
11317 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11318 if (ret != I40E_SUCCESS) {
11320 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11326 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11329 struct rte_eth_dev *dev;
11330 struct i40e_pf *pf;
11331 struct i40e_vsi *vsi;
11332 struct i40e_hw *hw;
11333 struct i40e_mac_filter_info filter;
11334 struct ether_addr broadcast = {
11335 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11338 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11341 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11345 dev = &rte_eth_devices[port];
11347 if (!is_device_supported(dev, &rte_i40e_pmd))
11350 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11351 hw = I40E_PF_TO_HW(pf);
11353 if (vf_id >= pf->vf_num || !pf->vfs) {
11354 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11359 * return -ENODEV if SRIOV not enabled, VF number not configured
11360 * or no queue assigned.
11362 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11363 pf->vf_nb_qps == 0) {
11364 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11368 vsi = pf->vfs[vf_id].vsi;
11370 PMD_DRV_LOG(ERR, "Invalid VSI.");
11375 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11376 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11377 ret = i40e_vsi_add_mac(vsi, &filter);
11379 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11382 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11384 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11392 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11394 struct rte_eth_dev *dev;
11395 struct i40e_pf *pf;
11396 struct i40e_hw *hw;
11397 struct i40e_vsi *vsi;
11398 struct i40e_vsi_context ctxt;
11401 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11404 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11408 dev = &rte_eth_devices[port];
11410 if (!is_device_supported(dev, &rte_i40e_pmd))
11413 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11414 hw = I40E_PF_TO_HW(pf);
11417 * return -ENODEV if SRIOV not enabled, VF number not configured
11418 * or no queue assigned.
11420 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11421 pf->vf_nb_qps == 0) {
11422 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11426 if (vf_id >= pf->vf_num || !pf->vfs) {
11427 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11431 vsi = pf->vfs[vf_id].vsi;
11433 PMD_DRV_LOG(ERR, "Invalid VSI.");
11437 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11439 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11440 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11442 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11443 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11446 memset(&ctxt, 0, sizeof(ctxt));
11447 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11448 ctxt.seid = vsi->seid;
11450 hw = I40E_VSI_TO_HW(vsi);
11451 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11452 if (ret != I40E_SUCCESS) {
11454 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11460 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11461 uint64_t vf_mask, uint8_t on)
11463 struct rte_eth_dev *dev;
11464 struct i40e_pf *pf;
11465 struct i40e_hw *hw;
11466 struct i40e_vsi *vsi;
11468 int ret = I40E_SUCCESS;
11470 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11472 dev = &rte_eth_devices[port];
11474 if (!is_device_supported(dev, &rte_i40e_pmd))
11477 if (vlan_id > ETHER_MAX_VLAN_ID) {
11478 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11482 if (vf_mask == 0) {
11483 PMD_DRV_LOG(ERR, "No VF.");
11488 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11492 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11493 hw = I40E_PF_TO_HW(pf);
11496 * return -ENODEV if SRIOV not enabled, VF number not configured
11497 * or no queue assigned.
11499 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11500 pf->vf_nb_qps == 0) {
11501 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11505 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11506 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11507 vsi = pf->vfs[vf_idx].vsi;
11509 if (!vsi->vlan_filter_on) {
11510 vsi->vlan_filter_on = true;
11511 if (!vsi->vlan_anti_spoof_on)
11512 i40e_add_rm_all_vlan_filter(
11515 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
11517 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11519 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11524 if (ret != I40E_SUCCESS) {
11526 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11533 rte_pmd_i40e_get_vf_stats(uint8_t port,
11535 struct rte_eth_stats *stats)
11537 struct rte_eth_dev *dev;
11538 struct i40e_pf *pf;
11539 struct i40e_vsi *vsi;
11541 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11543 dev = &rte_eth_devices[port];
11545 if (!is_device_supported(dev, &rte_i40e_pmd))
11548 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11550 if (vf_id >= pf->vf_num || !pf->vfs) {
11551 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11555 vsi = pf->vfs[vf_id].vsi;
11557 PMD_DRV_LOG(ERR, "Invalid VSI.");
11561 i40e_update_vsi_stats(vsi);
11563 stats->ipackets = vsi->eth_stats.rx_unicast +
11564 vsi->eth_stats.rx_multicast +
11565 vsi->eth_stats.rx_broadcast;
11566 stats->opackets = vsi->eth_stats.tx_unicast +
11567 vsi->eth_stats.tx_multicast +
11568 vsi->eth_stats.tx_broadcast;
11569 stats->ibytes = vsi->eth_stats.rx_bytes;
11570 stats->obytes = vsi->eth_stats.tx_bytes;
11571 stats->ierrors = vsi->eth_stats.rx_discards;
11572 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11578 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11581 struct rte_eth_dev *dev;
11582 struct i40e_pf *pf;
11583 struct i40e_vsi *vsi;
11585 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11587 dev = &rte_eth_devices[port];
11589 if (!is_device_supported(dev, &rte_i40e_pmd))
11592 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11594 if (vf_id >= pf->vf_num || !pf->vfs) {
11595 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11599 vsi = pf->vfs[vf_id].vsi;
11601 PMD_DRV_LOG(ERR, "Invalid VSI.");
11605 vsi->offset_loaded = false;
11606 i40e_update_vsi_stats(vsi);
11612 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11614 struct rte_eth_dev *dev;
11615 struct i40e_pf *pf;
11616 struct i40e_vsi *vsi;
11617 struct i40e_hw *hw;
11621 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11623 dev = &rte_eth_devices[port];
11625 if (!is_device_supported(dev, &rte_i40e_pmd))
11628 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11630 if (vf_id >= pf->vf_num || !pf->vfs) {
11631 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11635 vsi = pf->vfs[vf_id].vsi;
11637 PMD_DRV_LOG(ERR, "Invalid VSI.");
11641 if (bw > I40E_QOS_BW_MAX) {
11642 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11647 if (bw % I40E_QOS_BW_GRANULARITY) {
11648 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11649 I40E_QOS_BW_GRANULARITY);
11653 bw /= I40E_QOS_BW_GRANULARITY;
11655 hw = I40E_VSI_TO_HW(vsi);
11658 if (bw == vsi->bw_info.bw_limit) {
11660 "No change for VF max bandwidth. Nothing to do.");
11665 * VF bandwidth limitation and TC bandwidth limitation cannot be
11666 * enabled in parallel, quit if TC bandwidth limitation is enabled.
11668 * If bw is 0, means disable bandwidth limitation. Then no need to
11669 * check TC bandwidth limitation.
11672 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11673 if ((vsi->enabled_tc & BIT_ULL(i)) &&
11674 vsi->bw_info.bw_ets_credits[i])
11677 if (i != I40E_MAX_TRAFFIC_CLASS) {
11679 "TC max bandwidth has been set on this VF,"
11680 " please disable it first.");
11685 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11688 "Failed to set VF %d bandwidth, err(%d).",
11693 /* Store the configuration. */
11694 vsi->bw_info.bw_limit = (uint16_t)bw;
11695 vsi->bw_info.bw_max = 0;
11701 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11702 uint8_t tc_num, uint8_t *bw_weight)
11704 struct rte_eth_dev *dev;
11705 struct i40e_pf *pf;
11706 struct i40e_vsi *vsi;
11707 struct i40e_hw *hw;
11708 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11712 bool b_change = false;
11714 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11716 dev = &rte_eth_devices[port];
11718 if (!is_device_supported(dev, &rte_i40e_pmd))
11721 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11723 if (vf_id >= pf->vf_num || !pf->vfs) {
11724 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11728 vsi = pf->vfs[vf_id].vsi;
11730 PMD_DRV_LOG(ERR, "Invalid VSI.");
11734 if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11735 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11736 I40E_MAX_TRAFFIC_CLASS);
11741 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11742 if (vsi->enabled_tc & BIT_ULL(i))
11745 if (sum != tc_num) {
11747 "Weight should be set for all %d enabled TCs.",
11753 for (i = 0; i < tc_num; i++) {
11754 if (!bw_weight[i]) {
11756 "The weight should be 1 at least.");
11759 sum += bw_weight[i];
11763 "The summary of the TC weight should be 100.");
11768 * Create the configuration for all the TCs.
11770 memset(&tc_bw, 0, sizeof(tc_bw));
11771 tc_bw.tc_valid_bits = vsi->enabled_tc;
11773 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11774 if (vsi->enabled_tc & BIT_ULL(i)) {
11775 if (bw_weight[j] !=
11776 vsi->bw_info.bw_ets_share_credits[i])
11779 tc_bw.tc_bw_credits[i] = bw_weight[j];
11787 "No change for TC allocated bandwidth."
11788 " Nothing to do.");
11792 hw = I40E_VSI_TO_HW(vsi);
11794 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11797 "Failed to set VF %d TC bandwidth weight, err(%d).",
11802 /* Store the configuration. */
11804 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11805 if (vsi->enabled_tc & BIT_ULL(i)) {
11806 vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11815 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11816 uint8_t tc_no, uint32_t bw)
11818 struct rte_eth_dev *dev;
11819 struct i40e_pf *pf;
11820 struct i40e_vsi *vsi;
11821 struct i40e_hw *hw;
11822 struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11826 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11828 dev = &rte_eth_devices[port];
11830 if (!is_device_supported(dev, &rte_i40e_pmd))
11833 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11835 if (vf_id >= pf->vf_num || !pf->vfs) {
11836 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11840 vsi = pf->vfs[vf_id].vsi;
11842 PMD_DRV_LOG(ERR, "Invalid VSI.");
11846 if (bw > I40E_QOS_BW_MAX) {
11847 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11852 if (bw % I40E_QOS_BW_GRANULARITY) {
11853 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11854 I40E_QOS_BW_GRANULARITY);
11858 bw /= I40E_QOS_BW_GRANULARITY;
11860 if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11861 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11862 I40E_MAX_TRAFFIC_CLASS);
11866 hw = I40E_VSI_TO_HW(vsi);
11868 if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11869 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11875 if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11877 "No change for TC max bandwidth. Nothing to do.");
11882 * VF bandwidth limitation and TC bandwidth limitation cannot be
11883 * enabled in parallel, disable VF bandwidth limitation if it's
11885 * If bw is 0, means disable bandwidth limitation. Then no need to
11886 * care about VF bandwidth limitation configuration.
11888 if (bw && vsi->bw_info.bw_limit) {
11889 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11892 "Failed to disable VF(%d)"
11893 " bandwidth limitation, err(%d).",
11899 "VF max bandwidth is disabled according"
11900 " to TC max bandwidth setting.");
11904 * Get all the TCs' info to create a whole picture.
11905 * Because the incremental change isn't permitted.
11907 memset(&tc_bw, 0, sizeof(tc_bw));
11908 tc_bw.tc_valid_bits = vsi->enabled_tc;
11909 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11910 if (vsi->enabled_tc & BIT_ULL(i)) {
11911 tc_bw.tc_bw_credits[i] =
11913 vsi->bw_info.bw_ets_credits[i]);
11916 tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11918 ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11921 "Failed to set VF %d TC %d max bandwidth, err(%d).",
11922 vf_id, tc_no, ret);
11926 /* Store the configuration. */
11927 vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
11933 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
11935 struct rte_eth_dev *dev;
11936 struct i40e_pf *pf;
11937 struct i40e_vsi *vsi;
11938 struct i40e_veb *veb;
11939 struct i40e_hw *hw;
11940 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
11944 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11946 dev = &rte_eth_devices[port];
11948 if (!is_device_supported(dev, &rte_i40e_pmd))
11951 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11953 vsi = pf->main_vsi;
11955 PMD_DRV_LOG(ERR, "Invalid VSI.");
11961 PMD_DRV_LOG(ERR, "Invalid VEB.");
11965 if ((tc_map & veb->enabled_tc) != tc_map) {
11967 "TC bitmap isn't the subset of enabled TCs 0x%x.",
11972 if (tc_map == veb->strict_prio_tc) {
11973 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
11977 hw = I40E_VSI_TO_HW(vsi);
11979 /* Disable DCBx if it's the first time to set strict priority. */
11980 if (!veb->strict_prio_tc) {
11981 ret = i40e_aq_stop_lldp(hw, true, NULL);
11984 "Failed to disable DCBx as it's already"
11988 "DCBx is disabled according to strict"
11989 " priority setting.");
11992 memset(&ets_data, 0, sizeof(ets_data));
11993 ets_data.tc_valid_bits = veb->enabled_tc;
11994 ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
11995 ets_data.tc_strict_priority_flags = tc_map;
11996 /* Get all TCs' bandwidth. */
11997 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11998 if (veb->enabled_tc & BIT_ULL(i)) {
11999 /* For rubust, if bandwidth is 0, use 1 instead. */
12000 if (veb->bw_info.bw_ets_share_credits[i])
12001 ets_data.tc_bw_share_credits[i] =
12002 veb->bw_info.bw_ets_share_credits[i];
12004 ets_data.tc_bw_share_credits[i] =
12005 I40E_QOS_BW_WEIGHT_MIN;
12009 if (!veb->strict_prio_tc)
12010 ret = i40e_aq_config_switch_comp_ets(
12011 hw, veb->uplink_seid,
12012 &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12015 ret = i40e_aq_config_switch_comp_ets(
12016 hw, veb->uplink_seid,
12017 &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12020 ret = i40e_aq_config_switch_comp_ets(
12021 hw, veb->uplink_seid,
12022 &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12027 "Failed to set TCs' strict priority mode."
12032 veb->strict_prio_tc = tc_map;
12034 /* Enable DCBx again, if all the TCs' strict priority disabled. */
12036 ret = i40e_aq_start_lldp(hw, NULL);
12039 "Failed to enable DCBx, err(%d).", ret);
12044 "DCBx is enabled again according to strict"
12045 " priority setting.");
12051 #define I40E_PROFILE_INFO_SIZE 48
12052 #define I40E_MAX_PROFILE_NUM 16
12055 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12056 uint32_t track_id, uint8_t *profile_info_sec,
12059 struct i40e_profile_section_header *sec = NULL;
12060 struct i40e_profile_info *pinfo;
12062 sec = (struct i40e_profile_section_header *)profile_info_sec;
12064 sec->data_end = sizeof(struct i40e_profile_section_header) +
12065 sizeof(struct i40e_profile_info);
12066 sec->section.type = SECTION_TYPE_INFO;
12067 sec->section.offset = sizeof(struct i40e_profile_section_header);
12068 sec->section.size = sizeof(struct i40e_profile_info);
12069 pinfo = (struct i40e_profile_info *)(profile_info_sec +
12070 sec->section.offset);
12071 pinfo->track_id = track_id;
12072 memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12073 memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12075 pinfo->op = I40E_DDP_ADD_TRACKID;
12077 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12080 static enum i40e_status_code
12081 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12083 enum i40e_status_code status = I40E_SUCCESS;
12084 struct i40e_profile_section_header *sec;
12086 uint32_t offset = 0;
12089 sec = (struct i40e_profile_section_header *)profile_info_sec;
12090 track_id = ((struct i40e_profile_info *)(profile_info_sec +
12091 sec->section.offset))->track_id;
12093 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12094 track_id, &offset, &info, NULL);
12096 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12097 "offset %d, info %d",
12103 #define I40E_PROFILE_INFO_SIZE 48
12104 #define I40E_MAX_PROFILE_NUM 16
12106 /* Check if the profile info exists */
12108 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12110 struct rte_eth_dev *dev = &rte_eth_devices[port];
12111 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12113 struct rte_pmd_i40e_profile_list *p_list;
12114 struct rte_pmd_i40e_profile_info *pinfo, *p;
12118 buff = rte_zmalloc("pinfo_list",
12119 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12122 PMD_DRV_LOG(ERR, "failed to allocate memory");
12126 ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12127 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12130 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12134 p_list = (struct rte_pmd_i40e_profile_list *)buff;
12135 pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12136 sizeof(struct i40e_profile_section_header));
12137 for (i = 0; i < p_list->p_count; i++) {
12138 p = &p_list->p_info[i];
12139 if ((pinfo->track_id == p->track_id) &&
12140 !memcmp(&pinfo->version, &p->version,
12141 sizeof(struct i40e_ddp_version)) &&
12142 !memcmp(&pinfo->name, &p->name,
12143 I40E_DDP_NAME_SIZE)) {
12144 PMD_DRV_LOG(INFO, "Profile exists.");
12155 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12157 enum rte_pmd_i40e_package_op op)
12159 struct rte_eth_dev *dev;
12160 struct i40e_hw *hw;
12161 struct i40e_package_header *pkg_hdr;
12162 struct i40e_generic_seg_header *profile_seg_hdr;
12163 struct i40e_generic_seg_header *metadata_seg_hdr;
12165 uint8_t *profile_info_sec;
12167 enum i40e_status_code status = I40E_SUCCESS;
12169 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12171 dev = &rte_eth_devices[port];
12173 if (!is_device_supported(dev, &rte_i40e_pmd))
12176 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12178 if (size < (sizeof(struct i40e_package_header) +
12179 sizeof(struct i40e_metadata_segment) +
12180 sizeof(uint32_t) * 2)) {
12181 PMD_DRV_LOG(ERR, "Buff is invalid.");
12185 pkg_hdr = (struct i40e_package_header *)buff;
12188 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12192 if (pkg_hdr->segment_count < 2) {
12193 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12197 /* Find metadata segment */
12198 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12200 if (!metadata_seg_hdr) {
12201 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12204 track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12206 /* Find profile segment */
12207 profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12209 if (!profile_seg_hdr) {
12210 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12214 profile_info_sec = rte_zmalloc("i40e_profile_info",
12215 sizeof(struct i40e_profile_section_header) +
12216 sizeof(struct i40e_profile_info),
12218 if (!profile_info_sec) {
12219 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12223 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12224 /* Check if the profile exists */
12225 i40e_generate_profile_info_sec(
12226 ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12227 &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12228 track_id, profile_info_sec, 1);
12229 is_exist = i40e_check_profile_info(port, profile_info_sec);
12230 if (is_exist > 0) {
12231 PMD_DRV_LOG(ERR, "Profile already exists.");
12232 rte_free(profile_info_sec);
12234 } else if (is_exist < 0) {
12235 PMD_DRV_LOG(ERR, "Failed to check profile.");
12236 rte_free(profile_info_sec);
12240 /* Write profile to HW */
12241 status = i40e_write_profile(hw,
12242 (struct i40e_profile_segment *)profile_seg_hdr,
12245 PMD_DRV_LOG(ERR, "Failed to write profile.");
12246 rte_free(profile_info_sec);
12250 /* Add profile info to info list */
12251 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12253 PMD_DRV_LOG(ERR, "Failed to add profile info.");
12255 PMD_DRV_LOG(ERR, "Operation not supported.");
12257 rte_free(profile_info_sec);
12262 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12264 struct rte_eth_dev *dev;
12265 struct i40e_hw *hw;
12266 enum i40e_status_code status = I40E_SUCCESS;
12268 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12270 dev = &rte_eth_devices[port];
12272 if (!is_device_supported(dev, &rte_i40e_pmd))
12275 if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12278 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12280 status = i40e_aq_get_ddp_list(hw, (void *)buff,