4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
112 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
113 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
114 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
116 #define I40E_FLOW_TYPES ( \
117 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
122 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
127 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
129 /* Additional timesync values. */
130 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
131 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
132 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
133 #define I40E_PRTTSYN_TSYNENA 0x80000000
134 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
135 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
137 #define I40E_MAX_PERCENT 100
138 #define I40E_DEFAULT_DCB_APP_NUM 1
139 #define I40E_DEFAULT_DCB_APP_PRIO 3
141 #define I40E_INSET_NONE 0x00000000000000000ULL
144 #define I40E_INSET_DMAC 0x0000000000000001ULL
145 #define I40E_INSET_SMAC 0x0000000000000002ULL
146 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
147 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
148 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
151 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
152 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
153 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
154 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
155 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
156 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
157 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
159 /* bit 16 ~ bit 31 */
160 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
161 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
162 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
163 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
164 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
165 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
166 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
167 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
169 /* bit 32 ~ bit 47, tunnel fields */
170 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
171 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
172 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
173 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
174 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
175 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
177 /* bit 48 ~ bit 55 */
178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
180 /* bit 56 ~ bit 63, Flex Payload */
181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD \
190 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
191 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
192 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
193 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
196 * Below are values for writing un-exposed registers suggested
199 /* Destination MAC address */
200 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
201 /* Source MAC address */
202 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
206 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
207 /* Single VLAN tag in the inner L2 header */
208 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
209 /* Source IPv4 address */
210 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
211 /* Destination IPv4 address */
212 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
213 /* Source IPv4 address for X722 */
214 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
215 /* Destination IPv4 address for X722 */
216 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
217 /* IPv4 Protocol for X722 */
218 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
219 /* IPv4 Time to Live for X722 */
220 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
221 /* IPv4 Type of Service (TOS) */
222 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
224 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
225 /* IPv4 Time to Live */
226 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
227 /* Source IPv6 address */
228 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
229 /* Destination IPv6 address */
230 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
231 /* IPv6 Traffic Class (TC) */
232 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
233 /* IPv6 Next Header */
234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
238 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
239 /* Destination L4 port */
240 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
241 /* SCTP verification tag */
242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
245 /* Source port of tunneling UDP */
246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
247 /* Destination port of tunneling UDP */
248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
249 /* UDP Tunneling ID, NVGRE/GRE key */
250 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
251 /* Last ether type */
252 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
253 /* Tunneling outer destination IPv4 address */
254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
255 /* Tunneling outer destination IPv6 address */
256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
257 /* 1st word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
259 /* 2nd word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
261 /* 3rd word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
263 /* 4th word of flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
265 /* 5th word of flex payload */
266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
267 /* 6th word of flex payload */
268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
269 /* 7th word of flex payload */
270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
271 /* 8th word of flex payload */
272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
273 /* all 8 words flex payload */
274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
275 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
277 #define I40E_TRANSLATE_INSET 0
278 #define I40E_TRANSLATE_REG 1
280 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
281 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
282 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
283 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
285 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
287 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
290 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
292 /* PCI offset for querying capability */
293 #define PCI_DEV_CAP_REG 0xA4
294 /* PCI offset for enabling/disabling Extended Tag */
295 #define PCI_DEV_CTRL_REG 0xA8
296 /* Bit mask of Extended Tag capability */
297 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
298 /* Bit shift of Extended Tag enable/disable */
299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
300 /* Bit mask of Extended Tag enable/disable */
301 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
305 static int i40e_dev_configure(struct rte_eth_dev *dev);
306 static int i40e_dev_start(struct rte_eth_dev *dev);
307 static void i40e_dev_stop(struct rte_eth_dev *dev);
308 static void i40e_dev_close(struct rte_eth_dev *dev);
309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
316 struct rte_eth_stats *stats);
317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
318 struct rte_eth_xstat *xstats, unsigned n);
319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
320 struct rte_eth_xstat_name *xstats_names,
322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
327 static int i40e_fw_version_get(struct rte_eth_dev *dev,
328 char *fw_version, size_t fw_size);
329 static void i40e_dev_info_get(struct rte_eth_dev *dev,
330 struct rte_eth_dev_info *dev_info);
331 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
334 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
335 enum rte_vlan_type vlan_type,
337 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
338 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
341 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
342 static int i40e_dev_led_on(struct rte_eth_dev *dev);
343 static int i40e_dev_led_off(struct rte_eth_dev *dev);
344 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
345 struct rte_eth_fc_conf *fc_conf);
346 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
347 struct rte_eth_fc_conf *fc_conf);
348 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
349 struct rte_eth_pfc_conf *pfc_conf);
350 static void i40e_macaddr_add(struct rte_eth_dev *dev,
351 struct ether_addr *mac_addr,
354 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
355 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
356 struct rte_eth_rss_reta_entry64 *reta_conf,
358 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
359 struct rte_eth_rss_reta_entry64 *reta_conf,
362 static int i40e_get_cap(struct i40e_hw *hw);
363 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
364 static int i40e_pf_setup(struct i40e_pf *pf);
365 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
366 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
367 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
368 static int i40e_dcb_setup(struct rte_eth_dev *dev);
369 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
370 bool offset_loaded, uint64_t *offset, uint64_t *stat);
371 static void i40e_stat_update_48(struct i40e_hw *hw,
377 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
378 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
380 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
381 uint32_t base, uint32_t num);
382 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
383 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
385 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
387 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
388 static int i40e_veb_release(struct i40e_veb *veb);
389 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
390 struct i40e_vsi *vsi);
391 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
392 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
393 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
394 struct i40e_macvlan_filter *mv_f,
396 struct ether_addr *addr);
397 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
398 struct i40e_macvlan_filter *mv_f,
401 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
402 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
403 struct rte_eth_rss_conf *rss_conf);
404 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
405 struct rte_eth_rss_conf *rss_conf);
406 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
407 struct rte_eth_udp_tunnel *udp_tunnel);
408 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
409 struct rte_eth_udp_tunnel *udp_tunnel);
410 static void i40e_filter_input_set_init(struct i40e_pf *pf);
411 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
412 struct rte_eth_ethertype_filter *filter,
414 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
415 enum rte_filter_op filter_op,
417 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
418 enum rte_filter_type filter_type,
419 enum rte_filter_op filter_op,
421 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
422 struct rte_eth_dcb_info *dcb_info);
423 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
424 static void i40e_configure_registers(struct i40e_hw *hw);
425 static void i40e_hw_init(struct rte_eth_dev *dev);
426 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
427 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
428 struct rte_eth_mirror_conf *mirror_conf,
429 uint8_t sw_id, uint8_t on);
430 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
432 static int i40e_timesync_enable(struct rte_eth_dev *dev);
433 static int i40e_timesync_disable(struct rte_eth_dev *dev);
434 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
435 struct timespec *timestamp,
437 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
438 struct timespec *timestamp);
439 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
441 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
443 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
444 struct timespec *timestamp);
445 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
446 const struct timespec *timestamp);
448 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
450 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
453 static int i40e_get_regs(struct rte_eth_dev *dev,
454 struct rte_dev_reg_info *regs);
456 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
458 static int i40e_get_eeprom(struct rte_eth_dev *dev,
459 struct rte_dev_eeprom_info *eeprom);
461 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
462 struct ether_addr *mac_addr);
464 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
466 static const struct rte_pci_id pci_id_i40e_map[] = {
467 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
468 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
469 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
470 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
471 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
472 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
473 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
474 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
475 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
476 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
477 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
478 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
479 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
480 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
481 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
482 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
483 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
484 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
485 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
486 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
487 { .vendor_id = 0, /* sentinel */ },
490 static const struct eth_dev_ops i40e_eth_dev_ops = {
491 .dev_configure = i40e_dev_configure,
492 .dev_start = i40e_dev_start,
493 .dev_stop = i40e_dev_stop,
494 .dev_close = i40e_dev_close,
495 .promiscuous_enable = i40e_dev_promiscuous_enable,
496 .promiscuous_disable = i40e_dev_promiscuous_disable,
497 .allmulticast_enable = i40e_dev_allmulticast_enable,
498 .allmulticast_disable = i40e_dev_allmulticast_disable,
499 .dev_set_link_up = i40e_dev_set_link_up,
500 .dev_set_link_down = i40e_dev_set_link_down,
501 .link_update = i40e_dev_link_update,
502 .stats_get = i40e_dev_stats_get,
503 .xstats_get = i40e_dev_xstats_get,
504 .xstats_get_names = i40e_dev_xstats_get_names,
505 .stats_reset = i40e_dev_stats_reset,
506 .xstats_reset = i40e_dev_stats_reset,
507 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
508 .fw_version_get = i40e_fw_version_get,
509 .dev_infos_get = i40e_dev_info_get,
510 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
511 .vlan_filter_set = i40e_vlan_filter_set,
512 .vlan_tpid_set = i40e_vlan_tpid_set,
513 .vlan_offload_set = i40e_vlan_offload_set,
514 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
515 .vlan_pvid_set = i40e_vlan_pvid_set,
516 .rx_queue_start = i40e_dev_rx_queue_start,
517 .rx_queue_stop = i40e_dev_rx_queue_stop,
518 .tx_queue_start = i40e_dev_tx_queue_start,
519 .tx_queue_stop = i40e_dev_tx_queue_stop,
520 .rx_queue_setup = i40e_dev_rx_queue_setup,
521 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
522 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
523 .rx_queue_release = i40e_dev_rx_queue_release,
524 .rx_queue_count = i40e_dev_rx_queue_count,
525 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
526 .tx_queue_setup = i40e_dev_tx_queue_setup,
527 .tx_queue_release = i40e_dev_tx_queue_release,
528 .dev_led_on = i40e_dev_led_on,
529 .dev_led_off = i40e_dev_led_off,
530 .flow_ctrl_get = i40e_flow_ctrl_get,
531 .flow_ctrl_set = i40e_flow_ctrl_set,
532 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
533 .mac_addr_add = i40e_macaddr_add,
534 .mac_addr_remove = i40e_macaddr_remove,
535 .reta_update = i40e_dev_rss_reta_update,
536 .reta_query = i40e_dev_rss_reta_query,
537 .rss_hash_update = i40e_dev_rss_hash_update,
538 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
539 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
540 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
541 .filter_ctrl = i40e_dev_filter_ctrl,
542 .rxq_info_get = i40e_rxq_info_get,
543 .txq_info_get = i40e_txq_info_get,
544 .mirror_rule_set = i40e_mirror_rule_set,
545 .mirror_rule_reset = i40e_mirror_rule_reset,
546 .timesync_enable = i40e_timesync_enable,
547 .timesync_disable = i40e_timesync_disable,
548 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
549 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
550 .get_dcb_info = i40e_dev_get_dcb_info,
551 .timesync_adjust_time = i40e_timesync_adjust_time,
552 .timesync_read_time = i40e_timesync_read_time,
553 .timesync_write_time = i40e_timesync_write_time,
554 .get_reg = i40e_get_regs,
555 .get_eeprom_length = i40e_get_eeprom_length,
556 .get_eeprom = i40e_get_eeprom,
557 .mac_addr_set = i40e_set_default_mac_addr,
558 .mtu_set = i40e_dev_mtu_set,
561 /* store statistics names and its offset in stats structure */
562 struct rte_i40e_xstats_name_off {
563 char name[RTE_ETH_XSTATS_NAME_SIZE];
567 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
568 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
569 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
570 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
571 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
572 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
573 rx_unknown_protocol)},
574 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
575 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
576 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
577 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
580 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
581 sizeof(rte_i40e_stats_strings[0]))
583 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
584 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
585 tx_dropped_link_down)},
586 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
587 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
590 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
592 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
594 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
596 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
597 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
598 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
599 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
600 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
601 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
605 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
607 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
609 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
611 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
613 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
615 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
617 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
618 mac_short_packet_dropped)},
619 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
621 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
622 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
623 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
625 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
627 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
629 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
631 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
633 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
635 {"rx_flow_director_atr_match_packets",
636 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
637 {"rx_flow_director_sb_match_packets",
638 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
639 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
641 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
643 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
645 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
649 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
650 sizeof(rte_i40e_hw_port_strings[0]))
652 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
653 {"xon_packets", offsetof(struct i40e_hw_port_stats,
655 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
659 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
660 sizeof(rte_i40e_rxq_prio_strings[0]))
662 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
663 {"xon_packets", offsetof(struct i40e_hw_port_stats,
665 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
667 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
668 priority_xon_2_xoff)},
671 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
672 sizeof(rte_i40e_txq_prio_strings[0]))
674 static struct eth_driver rte_i40e_pmd = {
676 .id_table = pci_id_i40e_map,
677 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
678 .probe = rte_eth_dev_pci_probe,
679 .remove = rte_eth_dev_pci_remove,
681 .eth_dev_init = eth_i40e_dev_init,
682 .eth_dev_uninit = eth_i40e_dev_uninit,
683 .dev_private_size = sizeof(struct i40e_adapter),
687 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
688 struct rte_eth_link *link)
690 struct rte_eth_link *dst = link;
691 struct rte_eth_link *src = &(dev->data->dev_link);
693 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
694 *(uint64_t *)src) == 0)
701 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
702 struct rte_eth_link *link)
704 struct rte_eth_link *dst = &(dev->data->dev_link);
705 struct rte_eth_link *src = link;
707 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
708 *(uint64_t *)src) == 0)
714 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
715 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
716 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
718 #ifndef I40E_GLQF_ORT
719 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
721 #ifndef I40E_GLQF_PIT
722 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
725 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
728 * Initialize registers for flexible payload, which should be set by NVM.
729 * This should be removed from code once it is fixed in NVM.
731 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
732 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
733 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
734 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
735 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
736 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
737 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
738 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
739 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
740 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
741 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
742 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
744 /* Initialize registers for parsing packet type of QinQ */
745 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
746 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
749 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
752 * Add a ethertype filter to drop all flow control frames transmitted
756 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
758 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
759 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
760 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
761 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
764 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
765 I40E_FLOW_CONTROL_ETHERTYPE, flags,
766 pf->main_vsi_seid, 0,
769 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
770 " frames from VSIs.");
774 floating_veb_list_handler(__rte_unused const char *key,
775 const char *floating_veb_value,
779 unsigned int count = 0;
782 bool *vf_floating_veb = opaque;
784 while (isblank(*floating_veb_value))
785 floating_veb_value++;
787 /* Reset floating VEB configuration for VFs */
788 for (idx = 0; idx < I40E_MAX_VF; idx++)
789 vf_floating_veb[idx] = false;
793 while (isblank(*floating_veb_value))
794 floating_veb_value++;
795 if (*floating_veb_value == '\0')
798 idx = strtoul(floating_veb_value, &end, 10);
799 if (errno || end == NULL)
801 while (isblank(*end))
805 } else if ((*end == ';') || (*end == '\0')) {
807 if (min == I40E_MAX_VF)
809 if (max >= I40E_MAX_VF)
810 max = I40E_MAX_VF - 1;
811 for (idx = min; idx <= max; idx++) {
812 vf_floating_veb[idx] = true;
819 floating_veb_value = end + 1;
820 } while (*end != '\0');
829 config_vf_floating_veb(struct rte_devargs *devargs,
830 uint16_t floating_veb,
831 bool *vf_floating_veb)
833 struct rte_kvargs *kvlist;
835 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
839 /* All the VFs attach to the floating VEB by default
840 * when the floating VEB is enabled.
842 for (i = 0; i < I40E_MAX_VF; i++)
843 vf_floating_veb[i] = true;
848 kvlist = rte_kvargs_parse(devargs->args, NULL);
852 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
853 rte_kvargs_free(kvlist);
856 /* When the floating_veb_list parameter exists, all the VFs
857 * will attach to the legacy VEB firstly, then configure VFs
858 * to the floating VEB according to the floating_veb_list.
860 if (rte_kvargs_process(kvlist, floating_veb_list,
861 floating_veb_list_handler,
862 vf_floating_veb) < 0) {
863 rte_kvargs_free(kvlist);
866 rte_kvargs_free(kvlist);
870 i40e_check_floating_handler(__rte_unused const char *key,
872 __rte_unused void *opaque)
874 if (strcmp(value, "1"))
881 is_floating_veb_supported(struct rte_devargs *devargs)
883 struct rte_kvargs *kvlist;
884 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
889 kvlist = rte_kvargs_parse(devargs->args, NULL);
893 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
894 rte_kvargs_free(kvlist);
897 /* Floating VEB is enabled when there's key-value:
898 * enable_floating_veb=1
900 if (rte_kvargs_process(kvlist, floating_veb_key,
901 i40e_check_floating_handler, NULL) < 0) {
902 rte_kvargs_free(kvlist);
905 rte_kvargs_free(kvlist);
911 config_floating_veb(struct rte_eth_dev *dev)
913 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
917 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
919 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
921 is_floating_veb_supported(pci_dev->device.devargs);
922 config_vf_floating_veb(pci_dev->device.devargs,
924 pf->floating_veb_list);
926 pf->floating_veb = false;
930 #define I40E_L2_TAGS_S_TAG_SHIFT 1
931 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
934 eth_i40e_dev_init(struct rte_eth_dev *dev)
936 struct rte_pci_device *pci_dev;
937 struct rte_intr_handle *intr_handle;
938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
940 struct i40e_vsi *vsi;
945 PMD_INIT_FUNC_TRACE();
947 dev->dev_ops = &i40e_eth_dev_ops;
948 dev->rx_pkt_burst = i40e_recv_pkts;
949 dev->tx_pkt_burst = i40e_xmit_pkts;
950 dev->tx_pkt_prepare = i40e_prep_pkts;
952 /* for secondary processes, we don't initialise any further as primary
953 * has already done this work. Only check we don't need a different
955 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
956 i40e_set_rx_function(dev);
957 i40e_set_tx_function(dev);
960 pci_dev = I40E_DEV_TO_PCI(dev);
961 intr_handle = &pci_dev->intr_handle;
963 rte_eth_copy_pci_info(dev, pci_dev);
964 dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
966 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
967 pf->adapter->eth_dev = dev;
968 pf->dev_data = dev->data;
970 hw->back = I40E_PF_TO_ADAPTER(pf);
971 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
973 PMD_INIT_LOG(ERR, "Hardware is not available, "
974 "as address is NULL");
978 hw->vendor_id = pci_dev->id.vendor_id;
979 hw->device_id = pci_dev->id.device_id;
980 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
981 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
982 hw->bus.device = pci_dev->addr.devid;
983 hw->bus.func = pci_dev->addr.function;
984 hw->adapter_stopped = 0;
986 /* Make sure all is clean before doing PF reset */
989 /* Initialize the hardware */
992 /* Reset here to make sure all is clean for each PF */
993 ret = i40e_pf_reset(hw);
995 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
999 /* Initialize the shared code (base driver) */
1000 ret = i40e_init_shared_code(hw);
1002 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1007 * To work around the NVM issue, initialize registers
1008 * for flexible payload and packet type of QinQ by
1009 * software. It should be removed once issues are fixed
1012 i40e_GLQF_reg_init(hw);
1014 /* Initialize the input set for filters (hash and fd) to default value */
1015 i40e_filter_input_set_init(pf);
1017 /* Initialize the parameters for adminq */
1018 i40e_init_adminq_parameter(hw);
1019 ret = i40e_init_adminq(hw);
1020 if (ret != I40E_SUCCESS) {
1021 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1024 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1025 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1026 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1027 ((hw->nvm.version >> 12) & 0xf),
1028 ((hw->nvm.version >> 4) & 0xff),
1029 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1031 /* Need the special FW version to support floating VEB */
1032 config_floating_veb(dev);
1033 /* Clear PXE mode */
1034 i40e_clear_pxe_mode(hw);
1035 ret = i40e_dev_sync_phy_type(hw);
1037 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1038 goto err_sync_phy_type;
1041 * On X710, performance number is far from the expectation on recent
1042 * firmware versions. The fix for this issue may not be integrated in
1043 * the following firmware version. So the workaround in software driver
1044 * is needed. It needs to modify the initial values of 3 internal only
1045 * registers. Note that the workaround can be removed when it is fixed
1046 * in firmware in the future.
1048 i40e_configure_registers(hw);
1050 /* Get hw capabilities */
1051 ret = i40e_get_cap(hw);
1052 if (ret != I40E_SUCCESS) {
1053 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1054 goto err_get_capabilities;
1057 /* Initialize parameters for PF */
1058 ret = i40e_pf_parameter_init(dev);
1060 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1061 goto err_parameter_init;
1064 /* Initialize the queue management */
1065 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1067 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1068 goto err_qp_pool_init;
1070 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1071 hw->func_caps.num_msix_vectors - 1);
1073 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1074 goto err_msix_pool_init;
1077 /* Initialize lan hmc */
1078 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1079 hw->func_caps.num_rx_qp, 0, 0);
1080 if (ret != I40E_SUCCESS) {
1081 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1082 goto err_init_lan_hmc;
1085 /* Configure lan hmc */
1086 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1087 if (ret != I40E_SUCCESS) {
1088 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1089 goto err_configure_lan_hmc;
1092 /* Get and check the mac address */
1093 i40e_get_mac_addr(hw, hw->mac.addr);
1094 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1095 PMD_INIT_LOG(ERR, "mac address is not valid");
1097 goto err_get_mac_addr;
1099 /* Copy the permanent MAC address */
1100 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1101 (struct ether_addr *) hw->mac.perm_addr);
1103 /* Disable flow control */
1104 hw->fc.requested_mode = I40E_FC_NONE;
1105 i40e_set_fc(hw, &aq_fail, TRUE);
1107 /* Set the global registers with default ether type value */
1108 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1109 if (ret != I40E_SUCCESS) {
1110 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1112 goto err_setup_pf_switch;
1115 /* PF setup, which includes VSI setup */
1116 ret = i40e_pf_setup(pf);
1118 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1119 goto err_setup_pf_switch;
1122 /* reset all stats of the device, including pf and main vsi */
1123 i40e_dev_stats_reset(dev);
1127 /* Disable double vlan by default */
1128 i40e_vsi_config_double_vlan(vsi, FALSE);
1130 /* Disable S-TAG identification when floating_veb is disabled */
1131 if (!pf->floating_veb) {
1132 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1133 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1134 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1135 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1139 if (!vsi->max_macaddrs)
1140 len = ETHER_ADDR_LEN;
1142 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1144 /* Should be after VSI initialized */
1145 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1146 if (!dev->data->mac_addrs) {
1147 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1148 "for storing mac address");
1151 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1152 &dev->data->mac_addrs[0]);
1154 /* initialize pf host driver to setup SRIOV resource if applicable */
1155 i40e_pf_host_init(dev);
1157 /* register callback func to eal lib */
1158 rte_intr_callback_register(intr_handle,
1159 i40e_dev_interrupt_handler, dev);
1161 /* configure and enable device interrupt */
1162 i40e_pf_config_irq0(hw, TRUE);
1163 i40e_pf_enable_irq0(hw);
1165 /* enable uio intr after callback register */
1166 rte_intr_enable(intr_handle);
1168 * Add an ethertype filter to drop all flow control frames transmitted
1169 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1172 i40e_add_tx_flow_control_drop_filter(pf);
1174 /* Set the max frame size to 0x2600 by default,
1175 * in case other drivers changed the default value.
1177 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1179 /* initialize mirror rule list */
1180 TAILQ_INIT(&pf->mirror_list);
1182 /* Init dcb to sw mode by default */
1183 ret = i40e_dcb_init_configure(dev, TRUE);
1184 if (ret != I40E_SUCCESS) {
1185 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1186 pf->flags &= ~I40E_FLAG_DCB;
1192 i40e_vsi_release(pf->main_vsi);
1193 err_setup_pf_switch:
1195 err_configure_lan_hmc:
1196 (void)i40e_shutdown_lan_hmc(hw);
1198 i40e_res_pool_destroy(&pf->msix_pool);
1200 i40e_res_pool_destroy(&pf->qp_pool);
1203 err_get_capabilities:
1205 (void)i40e_shutdown_adminq(hw);
1211 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1213 struct rte_pci_device *pci_dev;
1214 struct rte_intr_handle *intr_handle;
1216 struct i40e_filter_control_settings settings;
1218 uint8_t aq_fail = 0;
1220 PMD_INIT_FUNC_TRACE();
1222 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1225 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226 pci_dev = I40E_DEV_TO_PCI(dev);
1227 intr_handle = &pci_dev->intr_handle;
1229 if (hw->adapter_stopped == 0)
1230 i40e_dev_close(dev);
1232 dev->dev_ops = NULL;
1233 dev->rx_pkt_burst = NULL;
1234 dev->tx_pkt_burst = NULL;
1236 /* Clear PXE mode */
1237 i40e_clear_pxe_mode(hw);
1239 /* Unconfigure filter control */
1240 memset(&settings, 0, sizeof(settings));
1241 ret = i40e_set_filter_control(hw, &settings);
1243 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1246 /* Disable flow control */
1247 hw->fc.requested_mode = I40E_FC_NONE;
1248 i40e_set_fc(hw, &aq_fail, TRUE);
1250 /* uninitialize pf host driver */
1251 i40e_pf_host_uninit(dev);
1253 rte_free(dev->data->mac_addrs);
1254 dev->data->mac_addrs = NULL;
1256 /* disable uio intr before callback unregister */
1257 rte_intr_disable(intr_handle);
1259 /* register callback func to eal lib */
1260 rte_intr_callback_unregister(intr_handle,
1261 i40e_dev_interrupt_handler, dev);
1267 i40e_dev_configure(struct rte_eth_dev *dev)
1269 struct i40e_adapter *ad =
1270 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1271 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1272 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1275 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1276 * bulk allocation or vector Rx preconditions we will reset it.
1278 ad->rx_bulk_alloc_allowed = true;
1279 ad->rx_vec_allowed = true;
1280 ad->tx_simple_allowed = true;
1281 ad->tx_vec_allowed = true;
1283 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1284 ret = i40e_fdir_setup(pf);
1285 if (ret != I40E_SUCCESS) {
1286 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1289 ret = i40e_fdir_configure(dev);
1291 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1295 i40e_fdir_teardown(pf);
1297 ret = i40e_dev_init_vlan(dev);
1302 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1303 * RSS setting have different requirements.
1304 * General PMD driver call sequence are NIC init, configure,
1305 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1306 * will try to lookup the VSI that specific queue belongs to if VMDQ
1307 * applicable. So, VMDQ setting has to be done before
1308 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1309 * For RSS setting, it will try to calculate actual configured RX queue
1310 * number, which will be available after rx_queue_setup(). dev_start()
1311 * function is good to place RSS setup.
1313 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1314 ret = i40e_vmdq_setup(dev);
1319 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1320 ret = i40e_dcb_setup(dev);
1322 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1330 /* need to release vmdq resource if exists */
1331 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1332 i40e_vsi_release(pf->vmdq[i].vsi);
1333 pf->vmdq[i].vsi = NULL;
1338 /* need to release fdir resource if exists */
1339 i40e_fdir_teardown(pf);
1344 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1346 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1347 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1348 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1349 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1350 uint16_t msix_vect = vsi->msix_intr;
1353 for (i = 0; i < vsi->nb_qps; i++) {
1354 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1355 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1359 if (vsi->type != I40E_VSI_SRIOV) {
1360 if (!rte_intr_allow_others(intr_handle)) {
1361 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1362 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1364 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1367 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1368 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1370 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1375 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1376 vsi->user_param + (msix_vect - 1);
1378 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1379 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1381 I40E_WRITE_FLUSH(hw);
1385 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1386 int base_queue, int nb_queue)
1390 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1392 /* Bind all RX queues to allocated MSIX interrupt */
1393 for (i = 0; i < nb_queue; i++) {
1394 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1395 I40E_QINT_RQCTL_ITR_INDX_MASK |
1396 ((base_queue + i + 1) <<
1397 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1398 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1399 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1401 if (i == nb_queue - 1)
1402 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1403 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1406 /* Write first RX queue to Link list register as the head element */
1407 if (vsi->type != I40E_VSI_SRIOV) {
1409 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1411 if (msix_vect == I40E_MISC_VEC_ID) {
1412 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1414 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1416 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1418 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1421 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1423 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1425 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1427 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1434 if (msix_vect == I40E_MISC_VEC_ID) {
1436 I40E_VPINT_LNKLST0(vsi->user_param),
1438 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1440 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1442 /* num_msix_vectors_vf needs to minus irq0 */
1443 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1444 vsi->user_param + (msix_vect - 1);
1446 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1448 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1450 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1454 I40E_WRITE_FLUSH(hw);
1458 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1460 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1461 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1462 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1463 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1464 uint16_t msix_vect = vsi->msix_intr;
1465 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1466 uint16_t queue_idx = 0;
1471 for (i = 0; i < vsi->nb_qps; i++) {
1472 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1473 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1476 /* INTENA flag is not auto-cleared for interrupt */
1477 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1478 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1479 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1480 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1481 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1483 /* VF bind interrupt */
1484 if (vsi->type == I40E_VSI_SRIOV) {
1485 __vsi_queues_bind_intr(vsi, msix_vect,
1486 vsi->base_queue, vsi->nb_qps);
1490 /* PF & VMDq bind interrupt */
1491 if (rte_intr_dp_is_en(intr_handle)) {
1492 if (vsi->type == I40E_VSI_MAIN) {
1495 } else if (vsi->type == I40E_VSI_VMDQ2) {
1496 struct i40e_vsi *main_vsi =
1497 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1498 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1503 for (i = 0; i < vsi->nb_used_qps; i++) {
1505 if (!rte_intr_allow_others(intr_handle))
1506 /* allow to share MISC_VEC_ID */
1507 msix_vect = I40E_MISC_VEC_ID;
1509 /* no enough msix_vect, map all to one */
1510 __vsi_queues_bind_intr(vsi, msix_vect,
1511 vsi->base_queue + i,
1512 vsi->nb_used_qps - i);
1513 for (; !!record && i < vsi->nb_used_qps; i++)
1514 intr_handle->intr_vec[queue_idx + i] =
1518 /* 1:1 queue/msix_vect mapping */
1519 __vsi_queues_bind_intr(vsi, msix_vect,
1520 vsi->base_queue + i, 1);
1522 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1530 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1532 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1533 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1534 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1535 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1536 uint16_t interval = i40e_calc_itr_interval(\
1537 RTE_LIBRTE_I40E_ITR_INTERVAL);
1538 uint16_t msix_intr, i;
1540 if (rte_intr_allow_others(intr_handle))
1541 for (i = 0; i < vsi->nb_msix; i++) {
1542 msix_intr = vsi->msix_intr + i;
1543 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1544 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1545 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1546 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1548 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1551 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1552 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1553 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1554 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1556 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1558 I40E_WRITE_FLUSH(hw);
1562 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1564 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1565 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1566 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1567 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1568 uint16_t msix_intr, i;
1570 if (rte_intr_allow_others(intr_handle))
1571 for (i = 0; i < vsi->nb_msix; i++) {
1572 msix_intr = vsi->msix_intr + i;
1573 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1577 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1579 I40E_WRITE_FLUSH(hw);
1582 static inline uint8_t
1583 i40e_parse_link_speeds(uint16_t link_speeds)
1585 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1587 if (link_speeds & ETH_LINK_SPEED_40G)
1588 link_speed |= I40E_LINK_SPEED_40GB;
1589 if (link_speeds & ETH_LINK_SPEED_25G)
1590 link_speed |= I40E_LINK_SPEED_25GB;
1591 if (link_speeds & ETH_LINK_SPEED_20G)
1592 link_speed |= I40E_LINK_SPEED_20GB;
1593 if (link_speeds & ETH_LINK_SPEED_10G)
1594 link_speed |= I40E_LINK_SPEED_10GB;
1595 if (link_speeds & ETH_LINK_SPEED_1G)
1596 link_speed |= I40E_LINK_SPEED_1GB;
1597 if (link_speeds & ETH_LINK_SPEED_100M)
1598 link_speed |= I40E_LINK_SPEED_100MB;
1604 i40e_phy_conf_link(struct i40e_hw *hw,
1606 uint8_t force_speed)
1608 enum i40e_status_code status;
1609 struct i40e_aq_get_phy_abilities_resp phy_ab;
1610 struct i40e_aq_set_phy_config phy_conf;
1611 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1612 I40E_AQ_PHY_FLAG_PAUSE_RX |
1613 I40E_AQ_PHY_FLAG_PAUSE_RX |
1614 I40E_AQ_PHY_FLAG_LOW_POWER;
1615 const uint8_t advt = I40E_LINK_SPEED_40GB |
1616 I40E_LINK_SPEED_25GB |
1617 I40E_LINK_SPEED_10GB |
1618 I40E_LINK_SPEED_1GB |
1619 I40E_LINK_SPEED_100MB;
1623 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1628 memset(&phy_conf, 0, sizeof(phy_conf));
1630 /* bits 0-2 use the values from get_phy_abilities_resp */
1632 abilities |= phy_ab.abilities & mask;
1634 /* update ablities and speed */
1635 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1636 phy_conf.link_speed = advt;
1638 phy_conf.link_speed = force_speed;
1640 phy_conf.abilities = abilities;
1642 /* use get_phy_abilities_resp value for the rest */
1643 phy_conf.phy_type = phy_ab.phy_type;
1644 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1645 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1646 phy_conf.eee_capability = phy_ab.eee_capability;
1647 phy_conf.eeer = phy_ab.eeer_val;
1648 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1650 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1651 phy_ab.abilities, phy_ab.link_speed);
1652 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1653 phy_conf.abilities, phy_conf.link_speed);
1655 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1659 return I40E_SUCCESS;
1663 i40e_apply_link_speed(struct rte_eth_dev *dev)
1666 uint8_t abilities = 0;
1667 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668 struct rte_eth_conf *conf = &dev->data->dev_conf;
1670 speed = i40e_parse_link_speeds(conf->link_speeds);
1671 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1672 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1673 abilities |= I40E_AQ_PHY_AN_ENABLED;
1674 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1676 /* Skip changing speed on 40G interfaces, FW does not support */
1677 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1678 speed = I40E_LINK_SPEED_UNKNOWN;
1679 abilities |= I40E_AQ_PHY_AN_ENABLED;
1682 return i40e_phy_conf_link(hw, abilities, speed);
1686 i40e_dev_start(struct rte_eth_dev *dev)
1688 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1689 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690 struct i40e_vsi *main_vsi = pf->main_vsi;
1692 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1693 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694 uint32_t intr_vector = 0;
1696 hw->adapter_stopped = 0;
1698 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1699 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1700 dev->data->port_id);
1704 rte_intr_disable(intr_handle);
1706 if ((rte_intr_cap_multiple(intr_handle) ||
1707 !RTE_ETH_DEV_SRIOV(dev).active) &&
1708 dev->data->dev_conf.intr_conf.rxq != 0) {
1709 intr_vector = dev->data->nb_rx_queues;
1710 if (rte_intr_efd_enable(intr_handle, intr_vector))
1714 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1715 intr_handle->intr_vec =
1716 rte_zmalloc("intr_vec",
1717 dev->data->nb_rx_queues * sizeof(int),
1719 if (!intr_handle->intr_vec) {
1720 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1721 " intr_vec\n", dev->data->nb_rx_queues);
1726 /* Initialize VSI */
1727 ret = i40e_dev_rxtx_init(pf);
1728 if (ret != I40E_SUCCESS) {
1729 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1733 /* Map queues with MSIX interrupt */
1734 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1735 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1736 i40e_vsi_queues_bind_intr(main_vsi);
1737 i40e_vsi_enable_queues_intr(main_vsi);
1739 /* Map VMDQ VSI queues with MSIX interrupt */
1740 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1741 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1742 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1743 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1746 /* enable FDIR MSIX interrupt */
1747 if (pf->fdir.fdir_vsi) {
1748 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1749 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1752 /* Enable all queues which have been configured */
1753 ret = i40e_dev_switch_queues(pf, TRUE);
1754 if (ret != I40E_SUCCESS) {
1755 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1759 /* Enable receiving broadcast packets */
1760 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1761 if (ret != I40E_SUCCESS)
1762 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1764 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1765 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1767 if (ret != I40E_SUCCESS)
1768 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1771 /* Apply link configure */
1772 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1773 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1774 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1775 ETH_LINK_SPEED_40G)) {
1776 PMD_DRV_LOG(ERR, "Invalid link setting");
1779 ret = i40e_apply_link_speed(dev);
1780 if (I40E_SUCCESS != ret) {
1781 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1785 if (!rte_intr_allow_others(intr_handle)) {
1786 rte_intr_callback_unregister(intr_handle,
1787 i40e_dev_interrupt_handler,
1789 /* configure and enable device interrupt */
1790 i40e_pf_config_irq0(hw, FALSE);
1791 i40e_pf_enable_irq0(hw);
1793 if (dev->data->dev_conf.intr_conf.lsc != 0)
1794 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1795 " no intr multiplex\n");
1796 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1797 ret = i40e_aq_set_phy_int_mask(hw,
1798 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1799 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1800 I40E_AQ_EVENT_MEDIA_NA), NULL);
1801 if (ret != I40E_SUCCESS)
1802 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1804 /* Call get_link_info aq commond to enable LSE */
1805 i40e_dev_link_update(dev, 0);
1808 /* enable uio intr after callback register */
1809 rte_intr_enable(intr_handle);
1811 return I40E_SUCCESS;
1814 i40e_dev_switch_queues(pf, FALSE);
1815 i40e_dev_clear_queues(dev);
1821 i40e_dev_stop(struct rte_eth_dev *dev)
1823 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1824 struct i40e_vsi *main_vsi = pf->main_vsi;
1825 struct i40e_mirror_rule *p_mirror;
1826 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1827 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1830 /* Disable all queues */
1831 i40e_dev_switch_queues(pf, FALSE);
1833 /* un-map queues with interrupt registers */
1834 i40e_vsi_disable_queues_intr(main_vsi);
1835 i40e_vsi_queues_unbind_intr(main_vsi);
1837 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1838 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1839 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1842 if (pf->fdir.fdir_vsi) {
1843 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1844 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1846 /* Clear all queues and release memory */
1847 i40e_dev_clear_queues(dev);
1850 i40e_dev_set_link_down(dev);
1852 /* Remove all mirror rules */
1853 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1854 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1857 pf->nb_mirror_rule = 0;
1859 if (!rte_intr_allow_others(intr_handle))
1860 /* resume to the default handler */
1861 rte_intr_callback_register(intr_handle,
1862 i40e_dev_interrupt_handler,
1865 /* Clean datapath event and queue/vec mapping */
1866 rte_intr_efd_disable(intr_handle);
1867 if (intr_handle->intr_vec) {
1868 rte_free(intr_handle->intr_vec);
1869 intr_handle->intr_vec = NULL;
1874 i40e_dev_close(struct rte_eth_dev *dev)
1876 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1877 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1878 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1879 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1883 PMD_INIT_FUNC_TRACE();
1886 hw->adapter_stopped = 1;
1887 i40e_dev_free_queues(dev);
1889 /* Disable interrupt */
1890 i40e_pf_disable_irq0(hw);
1891 rte_intr_disable(intr_handle);
1893 /* shutdown and destroy the HMC */
1894 i40e_shutdown_lan_hmc(hw);
1896 /* release all the existing VSIs and VEBs */
1897 i40e_fdir_teardown(pf);
1898 i40e_vsi_release(pf->main_vsi);
1900 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1901 i40e_vsi_release(pf->vmdq[i].vsi);
1902 pf->vmdq[i].vsi = NULL;
1908 /* shutdown the adminq */
1909 i40e_aq_queue_shutdown(hw, true);
1910 i40e_shutdown_adminq(hw);
1912 i40e_res_pool_destroy(&pf->qp_pool);
1913 i40e_res_pool_destroy(&pf->msix_pool);
1915 /* force a PF reset to clean anything leftover */
1916 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1917 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1918 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1919 I40E_WRITE_FLUSH(hw);
1923 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1925 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1926 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927 struct i40e_vsi *vsi = pf->main_vsi;
1930 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1932 if (status != I40E_SUCCESS)
1933 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1935 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1937 if (status != I40E_SUCCESS)
1938 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1943 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1946 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947 struct i40e_vsi *vsi = pf->main_vsi;
1950 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1952 if (status != I40E_SUCCESS)
1953 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1955 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1957 if (status != I40E_SUCCESS)
1958 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1962 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1965 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966 struct i40e_vsi *vsi = pf->main_vsi;
1969 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1970 if (ret != I40E_SUCCESS)
1971 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1975 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1977 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1978 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979 struct i40e_vsi *vsi = pf->main_vsi;
1982 if (dev->data->promiscuous == 1)
1983 return; /* must remain in all_multicast mode */
1985 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1986 vsi->seid, FALSE, NULL);
1987 if (ret != I40E_SUCCESS)
1988 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1992 * Set device link up.
1995 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1997 /* re-apply link speed setting */
1998 return i40e_apply_link_speed(dev);
2002 * Set device link down.
2005 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2007 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2008 uint8_t abilities = 0;
2009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2012 return i40e_phy_conf_link(hw, abilities, speed);
2016 i40e_dev_link_update(struct rte_eth_dev *dev,
2017 int wait_to_complete)
2019 #define CHECK_INTERVAL 100 /* 100ms */
2020 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2021 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022 struct i40e_link_status link_status;
2023 struct rte_eth_link link, old;
2025 unsigned rep_cnt = MAX_REPEAT_TIME;
2026 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2028 memset(&link, 0, sizeof(link));
2029 memset(&old, 0, sizeof(old));
2030 memset(&link_status, 0, sizeof(link_status));
2031 rte_i40e_dev_atomic_read_link_status(dev, &old);
2034 /* Get link status information from hardware */
2035 status = i40e_aq_get_link_info(hw, enable_lse,
2036 &link_status, NULL);
2037 if (status != I40E_SUCCESS) {
2038 link.link_speed = ETH_SPEED_NUM_100M;
2039 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2040 PMD_DRV_LOG(ERR, "Failed to get link info");
2044 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2045 if (!wait_to_complete)
2048 rte_delay_ms(CHECK_INTERVAL);
2049 } while (!link.link_status && rep_cnt--);
2051 if (!link.link_status)
2054 /* i40e uses full duplex only */
2055 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2057 /* Parse the link status */
2058 switch (link_status.link_speed) {
2059 case I40E_LINK_SPEED_100MB:
2060 link.link_speed = ETH_SPEED_NUM_100M;
2062 case I40E_LINK_SPEED_1GB:
2063 link.link_speed = ETH_SPEED_NUM_1G;
2065 case I40E_LINK_SPEED_10GB:
2066 link.link_speed = ETH_SPEED_NUM_10G;
2068 case I40E_LINK_SPEED_20GB:
2069 link.link_speed = ETH_SPEED_NUM_20G;
2071 case I40E_LINK_SPEED_25GB:
2072 link.link_speed = ETH_SPEED_NUM_25G;
2074 case I40E_LINK_SPEED_40GB:
2075 link.link_speed = ETH_SPEED_NUM_40G;
2078 link.link_speed = ETH_SPEED_NUM_100M;
2082 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2083 ETH_LINK_SPEED_FIXED);
2086 rte_i40e_dev_atomic_write_link_status(dev, &link);
2087 if (link.link_status == old.link_status)
2093 /* Get all the statistics of a VSI */
2095 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2097 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2098 struct i40e_eth_stats *nes = &vsi->eth_stats;
2099 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2100 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2102 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2103 vsi->offset_loaded, &oes->rx_bytes,
2105 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2106 vsi->offset_loaded, &oes->rx_unicast,
2108 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2109 vsi->offset_loaded, &oes->rx_multicast,
2110 &nes->rx_multicast);
2111 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2112 vsi->offset_loaded, &oes->rx_broadcast,
2113 &nes->rx_broadcast);
2114 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2115 &oes->rx_discards, &nes->rx_discards);
2116 /* GLV_REPC not supported */
2117 /* GLV_RMPC not supported */
2118 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2119 &oes->rx_unknown_protocol,
2120 &nes->rx_unknown_protocol);
2121 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2122 vsi->offset_loaded, &oes->tx_bytes,
2124 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2125 vsi->offset_loaded, &oes->tx_unicast,
2127 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2128 vsi->offset_loaded, &oes->tx_multicast,
2129 &nes->tx_multicast);
2130 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2131 vsi->offset_loaded, &oes->tx_broadcast,
2132 &nes->tx_broadcast);
2133 /* GLV_TDPC not supported */
2134 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2135 &oes->tx_errors, &nes->tx_errors);
2136 vsi->offset_loaded = true;
2138 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2140 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2141 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2142 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2143 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2144 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2145 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2146 nes->rx_unknown_protocol);
2147 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2148 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2149 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2150 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2151 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2152 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2153 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2158 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2161 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2162 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2164 /* Get statistics of struct i40e_eth_stats */
2165 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2166 I40E_GLPRT_GORCL(hw->port),
2167 pf->offset_loaded, &os->eth.rx_bytes,
2169 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2170 I40E_GLPRT_UPRCL(hw->port),
2171 pf->offset_loaded, &os->eth.rx_unicast,
2172 &ns->eth.rx_unicast);
2173 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2174 I40E_GLPRT_MPRCL(hw->port),
2175 pf->offset_loaded, &os->eth.rx_multicast,
2176 &ns->eth.rx_multicast);
2177 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2178 I40E_GLPRT_BPRCL(hw->port),
2179 pf->offset_loaded, &os->eth.rx_broadcast,
2180 &ns->eth.rx_broadcast);
2181 /* Workaround: CRC size should not be included in byte statistics,
2182 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2184 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2185 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2187 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2188 pf->offset_loaded, &os->eth.rx_discards,
2189 &ns->eth.rx_discards);
2190 /* GLPRT_REPC not supported */
2191 /* GLPRT_RMPC not supported */
2192 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2194 &os->eth.rx_unknown_protocol,
2195 &ns->eth.rx_unknown_protocol);
2196 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2197 I40E_GLPRT_GOTCL(hw->port),
2198 pf->offset_loaded, &os->eth.tx_bytes,
2200 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2201 I40E_GLPRT_UPTCL(hw->port),
2202 pf->offset_loaded, &os->eth.tx_unicast,
2203 &ns->eth.tx_unicast);
2204 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2205 I40E_GLPRT_MPTCL(hw->port),
2206 pf->offset_loaded, &os->eth.tx_multicast,
2207 &ns->eth.tx_multicast);
2208 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2209 I40E_GLPRT_BPTCL(hw->port),
2210 pf->offset_loaded, &os->eth.tx_broadcast,
2211 &ns->eth.tx_broadcast);
2212 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2213 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2214 /* GLPRT_TEPC not supported */
2216 /* additional port specific stats */
2217 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2218 pf->offset_loaded, &os->tx_dropped_link_down,
2219 &ns->tx_dropped_link_down);
2220 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2221 pf->offset_loaded, &os->crc_errors,
2223 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2224 pf->offset_loaded, &os->illegal_bytes,
2225 &ns->illegal_bytes);
2226 /* GLPRT_ERRBC not supported */
2227 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2228 pf->offset_loaded, &os->mac_local_faults,
2229 &ns->mac_local_faults);
2230 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2231 pf->offset_loaded, &os->mac_remote_faults,
2232 &ns->mac_remote_faults);
2233 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2234 pf->offset_loaded, &os->rx_length_errors,
2235 &ns->rx_length_errors);
2236 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2237 pf->offset_loaded, &os->link_xon_rx,
2239 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2240 pf->offset_loaded, &os->link_xoff_rx,
2242 for (i = 0; i < 8; i++) {
2243 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2245 &os->priority_xon_rx[i],
2246 &ns->priority_xon_rx[i]);
2247 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2249 &os->priority_xoff_rx[i],
2250 &ns->priority_xoff_rx[i]);
2252 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2253 pf->offset_loaded, &os->link_xon_tx,
2255 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2256 pf->offset_loaded, &os->link_xoff_tx,
2258 for (i = 0; i < 8; i++) {
2259 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2261 &os->priority_xon_tx[i],
2262 &ns->priority_xon_tx[i]);
2263 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2265 &os->priority_xoff_tx[i],
2266 &ns->priority_xoff_tx[i]);
2267 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2269 &os->priority_xon_2_xoff[i],
2270 &ns->priority_xon_2_xoff[i]);
2272 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2273 I40E_GLPRT_PRC64L(hw->port),
2274 pf->offset_loaded, &os->rx_size_64,
2276 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2277 I40E_GLPRT_PRC127L(hw->port),
2278 pf->offset_loaded, &os->rx_size_127,
2280 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2281 I40E_GLPRT_PRC255L(hw->port),
2282 pf->offset_loaded, &os->rx_size_255,
2284 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2285 I40E_GLPRT_PRC511L(hw->port),
2286 pf->offset_loaded, &os->rx_size_511,
2288 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2289 I40E_GLPRT_PRC1023L(hw->port),
2290 pf->offset_loaded, &os->rx_size_1023,
2292 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2293 I40E_GLPRT_PRC1522L(hw->port),
2294 pf->offset_loaded, &os->rx_size_1522,
2296 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2297 I40E_GLPRT_PRC9522L(hw->port),
2298 pf->offset_loaded, &os->rx_size_big,
2300 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2301 pf->offset_loaded, &os->rx_undersize,
2303 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2304 pf->offset_loaded, &os->rx_fragments,
2306 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2307 pf->offset_loaded, &os->rx_oversize,
2309 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2310 pf->offset_loaded, &os->rx_jabber,
2312 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2313 I40E_GLPRT_PTC64L(hw->port),
2314 pf->offset_loaded, &os->tx_size_64,
2316 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2317 I40E_GLPRT_PTC127L(hw->port),
2318 pf->offset_loaded, &os->tx_size_127,
2320 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2321 I40E_GLPRT_PTC255L(hw->port),
2322 pf->offset_loaded, &os->tx_size_255,
2324 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2325 I40E_GLPRT_PTC511L(hw->port),
2326 pf->offset_loaded, &os->tx_size_511,
2328 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2329 I40E_GLPRT_PTC1023L(hw->port),
2330 pf->offset_loaded, &os->tx_size_1023,
2332 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2333 I40E_GLPRT_PTC1522L(hw->port),
2334 pf->offset_loaded, &os->tx_size_1522,
2336 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2337 I40E_GLPRT_PTC9522L(hw->port),
2338 pf->offset_loaded, &os->tx_size_big,
2340 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2342 &os->fd_sb_match, &ns->fd_sb_match);
2343 /* GLPRT_MSPDC not supported */
2344 /* GLPRT_XEC not supported */
2346 pf->offset_loaded = true;
2349 i40e_update_vsi_stats(pf->main_vsi);
2352 /* Get all statistics of a port */
2354 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2356 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2357 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2361 /* call read registers - updates values, now write them to struct */
2362 i40e_read_stats_registers(pf, hw);
2364 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2365 pf->main_vsi->eth_stats.rx_multicast +
2366 pf->main_vsi->eth_stats.rx_broadcast -
2367 pf->main_vsi->eth_stats.rx_discards;
2368 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2369 pf->main_vsi->eth_stats.tx_multicast +
2370 pf->main_vsi->eth_stats.tx_broadcast;
2371 stats->ibytes = ns->eth.rx_bytes;
2372 stats->obytes = ns->eth.tx_bytes;
2373 stats->oerrors = ns->eth.tx_errors +
2374 pf->main_vsi->eth_stats.tx_errors;
2377 stats->imissed = ns->eth.rx_discards +
2378 pf->main_vsi->eth_stats.rx_discards;
2379 stats->ierrors = ns->crc_errors +
2380 ns->rx_length_errors + ns->rx_undersize +
2381 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2383 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2384 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2385 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2386 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2387 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2388 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2389 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2390 ns->eth.rx_unknown_protocol);
2391 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2392 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2393 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2394 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2395 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2396 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2398 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2399 ns->tx_dropped_link_down);
2400 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2401 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2403 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2404 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2405 ns->mac_local_faults);
2406 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2407 ns->mac_remote_faults);
2408 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2409 ns->rx_length_errors);
2410 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2411 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2412 for (i = 0; i < 8; i++) {
2413 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2414 i, ns->priority_xon_rx[i]);
2415 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2416 i, ns->priority_xoff_rx[i]);
2418 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2419 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2420 for (i = 0; i < 8; i++) {
2421 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2422 i, ns->priority_xon_tx[i]);
2423 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2424 i, ns->priority_xoff_tx[i]);
2425 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2426 i, ns->priority_xon_2_xoff[i]);
2428 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2429 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2430 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2431 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2432 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2433 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2434 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2435 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2436 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2437 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2438 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2439 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2440 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2441 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2442 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2443 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2444 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2445 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2446 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2447 ns->mac_short_packet_dropped);
2448 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2449 ns->checksum_error);
2450 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2451 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2454 /* Reset the statistics */
2456 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2458 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2459 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2461 /* Mark PF and VSI stats to update the offset, aka "reset" */
2462 pf->offset_loaded = false;
2464 pf->main_vsi->offset_loaded = false;
2466 /* read the stats, reading current register values into offset */
2467 i40e_read_stats_registers(pf, hw);
2471 i40e_xstats_calc_num(void)
2473 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2474 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2475 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2478 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2479 struct rte_eth_xstat_name *xstats_names,
2480 __rte_unused unsigned limit)
2485 if (xstats_names == NULL)
2486 return i40e_xstats_calc_num();
2488 /* Note: limit checked in rte_eth_xstats_names() */
2490 /* Get stats from i40e_eth_stats struct */
2491 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2492 snprintf(xstats_names[count].name,
2493 sizeof(xstats_names[count].name),
2494 "%s", rte_i40e_stats_strings[i].name);
2498 /* Get individiual stats from i40e_hw_port struct */
2499 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2500 snprintf(xstats_names[count].name,
2501 sizeof(xstats_names[count].name),
2502 "%s", rte_i40e_hw_port_strings[i].name);
2506 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2507 for (prio = 0; prio < 8; prio++) {
2508 snprintf(xstats_names[count].name,
2509 sizeof(xstats_names[count].name),
2510 "rx_priority%u_%s", prio,
2511 rte_i40e_rxq_prio_strings[i].name);
2516 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2517 for (prio = 0; prio < 8; prio++) {
2518 snprintf(xstats_names[count].name,
2519 sizeof(xstats_names[count].name),
2520 "tx_priority%u_%s", prio,
2521 rte_i40e_txq_prio_strings[i].name);
2529 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2532 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2533 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534 unsigned i, count, prio;
2535 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2537 count = i40e_xstats_calc_num();
2541 i40e_read_stats_registers(pf, hw);
2548 /* Get stats from i40e_eth_stats struct */
2549 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2550 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2551 rte_i40e_stats_strings[i].offset);
2552 xstats[count].id = count;
2556 /* Get individiual stats from i40e_hw_port struct */
2557 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2558 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2559 rte_i40e_hw_port_strings[i].offset);
2560 xstats[count].id = count;
2564 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2565 for (prio = 0; prio < 8; prio++) {
2566 xstats[count].value =
2567 *(uint64_t *)(((char *)hw_stats) +
2568 rte_i40e_rxq_prio_strings[i].offset +
2569 (sizeof(uint64_t) * prio));
2570 xstats[count].id = count;
2575 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2576 for (prio = 0; prio < 8; prio++) {
2577 xstats[count].value =
2578 *(uint64_t *)(((char *)hw_stats) +
2579 rte_i40e_txq_prio_strings[i].offset +
2580 (sizeof(uint64_t) * prio));
2581 xstats[count].id = count;
2590 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2591 __rte_unused uint16_t queue_id,
2592 __rte_unused uint8_t stat_idx,
2593 __rte_unused uint8_t is_rx)
2595 PMD_INIT_FUNC_TRACE();
2601 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2603 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2609 full_ver = hw->nvm.oem_ver;
2610 ver = (u8)(full_ver >> 24);
2611 build = (u16)((full_ver >> 8) & 0xffff);
2612 patch = (u8)(full_ver & 0xff);
2614 ret = snprintf(fw_version, fw_size,
2615 "%d.%d%d 0x%08x %d.%d.%d",
2616 ((hw->nvm.version >> 12) & 0xf),
2617 ((hw->nvm.version >> 4) & 0xff),
2618 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2621 ret += 1; /* add the size of '\0' */
2622 if (fw_size < (u32)ret)
2629 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2631 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2632 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633 struct i40e_vsi *vsi = pf->main_vsi;
2634 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2636 dev_info->pci_dev = pci_dev;
2637 dev_info->max_rx_queues = vsi->nb_qps;
2638 dev_info->max_tx_queues = vsi->nb_qps;
2639 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2640 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2641 dev_info->max_mac_addrs = vsi->max_macaddrs;
2642 dev_info->max_vfs = pci_dev->max_vfs;
2643 dev_info->rx_offload_capa =
2644 DEV_RX_OFFLOAD_VLAN_STRIP |
2645 DEV_RX_OFFLOAD_QINQ_STRIP |
2646 DEV_RX_OFFLOAD_IPV4_CKSUM |
2647 DEV_RX_OFFLOAD_UDP_CKSUM |
2648 DEV_RX_OFFLOAD_TCP_CKSUM;
2649 dev_info->tx_offload_capa =
2650 DEV_TX_OFFLOAD_VLAN_INSERT |
2651 DEV_TX_OFFLOAD_QINQ_INSERT |
2652 DEV_TX_OFFLOAD_IPV4_CKSUM |
2653 DEV_TX_OFFLOAD_UDP_CKSUM |
2654 DEV_TX_OFFLOAD_TCP_CKSUM |
2655 DEV_TX_OFFLOAD_SCTP_CKSUM |
2656 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2657 DEV_TX_OFFLOAD_TCP_TSO |
2658 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2659 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2660 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2661 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2662 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2664 dev_info->reta_size = pf->hash_lut_size;
2665 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2667 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2669 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2670 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2671 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2673 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2677 dev_info->default_txconf = (struct rte_eth_txconf) {
2679 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2680 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2681 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2683 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2684 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2685 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2686 ETH_TXQ_FLAGS_NOOFFLOADS,
2689 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2690 .nb_max = I40E_MAX_RING_DESC,
2691 .nb_min = I40E_MIN_RING_DESC,
2692 .nb_align = I40E_ALIGN_RING_DESC,
2695 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2696 .nb_max = I40E_MAX_RING_DESC,
2697 .nb_min = I40E_MIN_RING_DESC,
2698 .nb_align = I40E_ALIGN_RING_DESC,
2699 .nb_seg_max = I40E_TX_MAX_SEG,
2700 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2703 if (pf->flags & I40E_FLAG_VMDQ) {
2704 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2705 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2706 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2707 pf->max_nb_vmdq_vsi;
2708 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2709 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2710 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2713 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2715 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2716 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2718 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2721 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2725 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2727 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2728 struct i40e_vsi *vsi = pf->main_vsi;
2729 PMD_INIT_FUNC_TRACE();
2732 return i40e_vsi_add_vlan(vsi, vlan_id);
2734 return i40e_vsi_delete_vlan(vsi, vlan_id);
2738 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2739 enum rte_vlan_type vlan_type,
2742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743 uint64_t reg_r = 0, reg_w = 0;
2744 uint16_t reg_id = 0;
2746 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2748 switch (vlan_type) {
2749 case ETH_VLAN_TYPE_OUTER:
2755 case ETH_VLAN_TYPE_INNER:
2761 "Unsupported vlan type in single vlan.\n");
2767 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2770 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2772 if (ret != I40E_SUCCESS) {
2773 PMD_DRV_LOG(ERR, "Fail to debug read from "
2774 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2778 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2779 "0x%08"PRIx64"", reg_id, reg_r);
2781 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2782 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2783 if (reg_r == reg_w) {
2785 PMD_DRV_LOG(DEBUG, "No need to write");
2789 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2791 if (ret != I40E_SUCCESS) {
2793 PMD_DRV_LOG(ERR, "Fail to debug write to "
2794 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2797 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2798 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2804 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2806 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2807 struct i40e_vsi *vsi = pf->main_vsi;
2809 if (mask & ETH_VLAN_FILTER_MASK) {
2810 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2811 i40e_vsi_config_vlan_filter(vsi, TRUE);
2813 i40e_vsi_config_vlan_filter(vsi, FALSE);
2816 if (mask & ETH_VLAN_STRIP_MASK) {
2817 /* Enable or disable VLAN stripping */
2818 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2819 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2821 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2824 if (mask & ETH_VLAN_EXTEND_MASK) {
2825 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2826 i40e_vsi_config_double_vlan(vsi, TRUE);
2827 /* Set global registers with default ether type value */
2828 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2830 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2834 i40e_vsi_config_double_vlan(vsi, FALSE);
2839 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2840 __rte_unused uint16_t queue,
2841 __rte_unused int on)
2843 PMD_INIT_FUNC_TRACE();
2847 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2850 struct i40e_vsi *vsi = pf->main_vsi;
2851 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2852 struct i40e_vsi_vlan_pvid_info info;
2854 memset(&info, 0, sizeof(info));
2857 info.config.pvid = pvid;
2859 info.config.reject.tagged =
2860 data->dev_conf.txmode.hw_vlan_reject_tagged;
2861 info.config.reject.untagged =
2862 data->dev_conf.txmode.hw_vlan_reject_untagged;
2865 return i40e_vsi_vlan_pvid_set(vsi, &info);
2869 i40e_dev_led_on(struct rte_eth_dev *dev)
2871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872 uint32_t mode = i40e_led_get(hw);
2875 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2881 i40e_dev_led_off(struct rte_eth_dev *dev)
2883 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884 uint32_t mode = i40e_led_get(hw);
2887 i40e_led_set(hw, 0, false);
2893 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2895 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2898 fc_conf->pause_time = pf->fc_conf.pause_time;
2899 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2900 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2902 /* Return current mode according to actual setting*/
2903 switch (hw->fc.current_mode) {
2905 fc_conf->mode = RTE_FC_FULL;
2907 case I40E_FC_TX_PAUSE:
2908 fc_conf->mode = RTE_FC_TX_PAUSE;
2910 case I40E_FC_RX_PAUSE:
2911 fc_conf->mode = RTE_FC_RX_PAUSE;
2915 fc_conf->mode = RTE_FC_NONE;
2922 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2924 uint32_t mflcn_reg, fctrl_reg, reg;
2925 uint32_t max_high_water;
2926 uint8_t i, aq_failure;
2930 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2931 [RTE_FC_NONE] = I40E_FC_NONE,
2932 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2933 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2934 [RTE_FC_FULL] = I40E_FC_FULL
2937 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2939 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2940 if ((fc_conf->high_water > max_high_water) ||
2941 (fc_conf->high_water < fc_conf->low_water)) {
2942 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2943 "High_water must <= %d.", max_high_water);
2947 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2949 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2951 pf->fc_conf.pause_time = fc_conf->pause_time;
2952 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2953 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2955 PMD_INIT_FUNC_TRACE();
2957 /* All the link flow control related enable/disable register
2958 * configuration is handle by the F/W
2960 err = i40e_set_fc(hw, &aq_failure, true);
2964 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2965 /* Configure flow control refresh threshold,
2966 * the value for stat_tx_pause_refresh_timer[8]
2967 * is used for global pause operation.
2971 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2972 pf->fc_conf.pause_time);
2974 /* configure the timer value included in transmitted pause
2976 * the value for stat_tx_pause_quanta[8] is used for global
2979 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2980 pf->fc_conf.pause_time);
2982 fctrl_reg = I40E_READ_REG(hw,
2983 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2985 if (fc_conf->mac_ctrl_frame_fwd != 0)
2986 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2988 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2990 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2993 /* Configure pause time (2 TCs per register) */
2994 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2995 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2996 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2998 /* Configure flow control refresh threshold value */
2999 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3000 pf->fc_conf.pause_time / 2);
3002 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3004 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3005 *depending on configuration
3007 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3008 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3009 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3011 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3012 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3015 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3018 /* config the water marker both based on the packets and bytes */
3019 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3020 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3021 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3022 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3023 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3024 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3025 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3026 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3028 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3029 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3032 I40E_WRITE_FLUSH(hw);
3038 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3039 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3041 PMD_INIT_FUNC_TRACE();
3046 /* Add a MAC address, and update filters */
3048 i40e_macaddr_add(struct rte_eth_dev *dev,
3049 struct ether_addr *mac_addr,
3050 __rte_unused uint32_t index,
3053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3054 struct i40e_mac_filter_info mac_filter;
3055 struct i40e_vsi *vsi;
3058 /* If VMDQ not enabled or configured, return */
3059 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3060 !pf->nb_cfg_vmdq_vsi)) {
3061 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3062 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3067 if (pool > pf->nb_cfg_vmdq_vsi) {
3068 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3069 pool, pf->nb_cfg_vmdq_vsi);
3073 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3074 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3075 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3077 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3082 vsi = pf->vmdq[pool - 1].vsi;
3084 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3085 if (ret != I40E_SUCCESS) {
3086 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3091 /* Remove a MAC address, and update filters */
3093 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3095 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3096 struct i40e_vsi *vsi;
3097 struct rte_eth_dev_data *data = dev->data;
3098 struct ether_addr *macaddr;
3103 macaddr = &(data->mac_addrs[index]);
3105 pool_sel = dev->data->mac_pool_sel[index];
3107 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3108 if (pool_sel & (1ULL << i)) {
3112 /* No VMDQ pool enabled or configured */
3113 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3114 (i > pf->nb_cfg_vmdq_vsi)) {
3115 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3119 vsi = pf->vmdq[i - 1].vsi;
3121 ret = i40e_vsi_delete_mac(vsi, macaddr);
3124 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3131 /* Set perfect match or hash match of MAC and VLAN for a VF */
3133 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3134 struct rte_eth_mac_filter *filter,
3138 struct i40e_mac_filter_info mac_filter;
3139 struct ether_addr old_mac;
3140 struct ether_addr *new_mac;
3141 struct i40e_pf_vf *vf = NULL;
3146 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3149 hw = I40E_PF_TO_HW(pf);
3151 if (filter == NULL) {
3152 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3156 new_mac = &filter->mac_addr;
3158 if (is_zero_ether_addr(new_mac)) {
3159 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3163 vf_id = filter->dst_id;
3165 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3166 PMD_DRV_LOG(ERR, "Invalid argument.");
3169 vf = &pf->vfs[vf_id];
3171 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3172 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3177 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3178 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3180 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3183 mac_filter.filter_type = filter->filter_type;
3184 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3185 if (ret != I40E_SUCCESS) {
3186 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3189 ether_addr_copy(new_mac, &pf->dev_addr);
3191 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3193 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3194 if (ret != I40E_SUCCESS) {
3195 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3199 /* Clear device address as it has been removed */
3200 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3201 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3207 /* MAC filter handle */
3209 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3212 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3213 struct rte_eth_mac_filter *filter;
3214 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3215 int ret = I40E_NOT_SUPPORTED;
3217 filter = (struct rte_eth_mac_filter *)(arg);
3219 switch (filter_op) {
3220 case RTE_ETH_FILTER_NOP:
3223 case RTE_ETH_FILTER_ADD:
3224 i40e_pf_disable_irq0(hw);
3226 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3227 i40e_pf_enable_irq0(hw);
3229 case RTE_ETH_FILTER_DELETE:
3230 i40e_pf_disable_irq0(hw);
3232 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3233 i40e_pf_enable_irq0(hw);
3236 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3237 ret = I40E_ERR_PARAM;
3245 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3247 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3248 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3254 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3255 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3258 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3262 uint32_t *lut_dw = (uint32_t *)lut;
3263 uint16_t i, lut_size_dw = lut_size / 4;
3265 for (i = 0; i < lut_size_dw; i++)
3266 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3273 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3282 pf = I40E_VSI_TO_PF(vsi);
3283 hw = I40E_VSI_TO_HW(vsi);
3285 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3286 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3289 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3293 uint32_t *lut_dw = (uint32_t *)lut;
3294 uint16_t i, lut_size_dw = lut_size / 4;
3296 for (i = 0; i < lut_size_dw; i++)
3297 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3298 I40E_WRITE_FLUSH(hw);
3305 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3306 struct rte_eth_rss_reta_entry64 *reta_conf,
3309 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3310 uint16_t i, lut_size = pf->hash_lut_size;
3311 uint16_t idx, shift;
3315 if (reta_size != lut_size ||
3316 reta_size > ETH_RSS_RETA_SIZE_512) {
3317 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3318 "(%d) doesn't match the number hardware can supported "
3319 "(%d)\n", reta_size, lut_size);
3323 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3325 PMD_DRV_LOG(ERR, "No memory can be allocated");
3328 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3331 for (i = 0; i < reta_size; i++) {
3332 idx = i / RTE_RETA_GROUP_SIZE;
3333 shift = i % RTE_RETA_GROUP_SIZE;
3334 if (reta_conf[idx].mask & (1ULL << shift))
3335 lut[i] = reta_conf[idx].reta[shift];
3337 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3346 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3347 struct rte_eth_rss_reta_entry64 *reta_conf,
3350 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3351 uint16_t i, lut_size = pf->hash_lut_size;
3352 uint16_t idx, shift;
3356 if (reta_size != lut_size ||
3357 reta_size > ETH_RSS_RETA_SIZE_512) {
3358 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3359 "(%d) doesn't match the number hardware can supported "
3360 "(%d)\n", reta_size, lut_size);
3364 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3366 PMD_DRV_LOG(ERR, "No memory can be allocated");
3370 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3373 for (i = 0; i < reta_size; i++) {
3374 idx = i / RTE_RETA_GROUP_SIZE;
3375 shift = i % RTE_RETA_GROUP_SIZE;
3376 if (reta_conf[idx].mask & (1ULL << shift))
3377 reta_conf[idx].reta[shift] = lut[i];
3387 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3388 * @hw: pointer to the HW structure
3389 * @mem: pointer to mem struct to fill out
3390 * @size: size of memory requested
3391 * @alignment: what to align the allocation to
3393 enum i40e_status_code
3394 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3395 struct i40e_dma_mem *mem,
3399 const struct rte_memzone *mz = NULL;
3400 char z_name[RTE_MEMZONE_NAMESIZE];
3403 return I40E_ERR_PARAM;
3405 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3406 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3407 alignment, RTE_PGSIZE_2M);
3409 return I40E_ERR_NO_MEMORY;
3413 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3414 mem->zone = (const void *)mz;
3415 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3416 "%"PRIu64, mz->name, mem->pa);
3418 return I40E_SUCCESS;
3422 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3423 * @hw: pointer to the HW structure
3424 * @mem: ptr to mem struct to free
3426 enum i40e_status_code
3427 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3428 struct i40e_dma_mem *mem)
3431 return I40E_ERR_PARAM;
3433 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3434 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3436 rte_memzone_free((const struct rte_memzone *)mem->zone);
3441 return I40E_SUCCESS;
3445 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3446 * @hw: pointer to the HW structure
3447 * @mem: pointer to mem struct to fill out
3448 * @size: size of memory requested
3450 enum i40e_status_code
3451 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3452 struct i40e_virt_mem *mem,
3456 return I40E_ERR_PARAM;
3459 mem->va = rte_zmalloc("i40e", size, 0);
3462 return I40E_SUCCESS;
3464 return I40E_ERR_NO_MEMORY;
3468 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3469 * @hw: pointer to the HW structure
3470 * @mem: pointer to mem struct to free
3472 enum i40e_status_code
3473 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3474 struct i40e_virt_mem *mem)
3477 return I40E_ERR_PARAM;
3482 return I40E_SUCCESS;
3486 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3488 rte_spinlock_init(&sp->spinlock);
3492 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3494 rte_spinlock_lock(&sp->spinlock);
3498 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3500 rte_spinlock_unlock(&sp->spinlock);
3504 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3510 * Get the hardware capabilities, which will be parsed
3511 * and saved into struct i40e_hw.
3514 i40e_get_cap(struct i40e_hw *hw)
3516 struct i40e_aqc_list_capabilities_element_resp *buf;
3517 uint16_t len, size = 0;
3520 /* Calculate a huge enough buff for saving response data temporarily */
3521 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3522 I40E_MAX_CAP_ELE_NUM;
3523 buf = rte_zmalloc("i40e", len, 0);
3525 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3526 return I40E_ERR_NO_MEMORY;
3529 /* Get, parse the capabilities and save it to hw */
3530 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3531 i40e_aqc_opc_list_func_capabilities, NULL);
3532 if (ret != I40E_SUCCESS)
3533 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3535 /* Free the temporary buffer after being used */
3542 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3544 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3545 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3546 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3547 uint16_t qp_count = 0, vsi_count = 0;
3549 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3550 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3553 /* Add the parameter init for LFC */
3554 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3555 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3556 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3558 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3559 pf->max_num_vsi = hw->func_caps.num_vsis;
3560 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3561 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3562 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3564 /* FDir queue/VSI allocation */
3565 pf->fdir_qp_offset = 0;
3566 if (hw->func_caps.fd) {
3567 pf->flags |= I40E_FLAG_FDIR;
3568 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3570 pf->fdir_nb_qps = 0;
3572 qp_count += pf->fdir_nb_qps;
3575 /* LAN queue/VSI allocation */
3576 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3577 if (!hw->func_caps.rss) {
3580 pf->flags |= I40E_FLAG_RSS;
3581 if (hw->mac.type == I40E_MAC_X722)
3582 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3583 pf->lan_nb_qps = pf->lan_nb_qp_max;
3585 qp_count += pf->lan_nb_qps;
3588 /* VF queue/VSI allocation */
3589 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3590 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3591 pf->flags |= I40E_FLAG_SRIOV;
3592 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3593 pf->vf_num = pci_dev->max_vfs;
3594 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3595 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3596 pf->vf_nb_qps * pf->vf_num);
3601 qp_count += pf->vf_nb_qps * pf->vf_num;
3602 vsi_count += pf->vf_num;
3604 /* VMDq queue/VSI allocation */
3605 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3606 pf->vmdq_nb_qps = 0;
3607 pf->max_nb_vmdq_vsi = 0;
3608 if (hw->func_caps.vmdq) {
3609 if (qp_count < hw->func_caps.num_tx_qp &&
3610 vsi_count < hw->func_caps.num_vsis) {
3611 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3612 qp_count) / pf->vmdq_nb_qp_max;
3614 /* Limit the maximum number of VMDq vsi to the maximum
3615 * ethdev can support
3617 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3618 hw->func_caps.num_vsis - vsi_count);
3619 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3621 if (pf->max_nb_vmdq_vsi) {
3622 pf->flags |= I40E_FLAG_VMDQ;
3623 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3624 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3625 "per VMDQ VSI, in total %u queues",
3626 pf->max_nb_vmdq_vsi,
3627 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3628 pf->max_nb_vmdq_vsi);
3630 PMD_DRV_LOG(INFO, "No enough queues left for "
3634 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3637 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3638 vsi_count += pf->max_nb_vmdq_vsi;
3640 if (hw->func_caps.dcb)
3641 pf->flags |= I40E_FLAG_DCB;
3643 if (qp_count > hw->func_caps.num_tx_qp) {
3644 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3645 "the hardware maximum %u", qp_count,
3646 hw->func_caps.num_tx_qp);
3649 if (vsi_count > hw->func_caps.num_vsis) {
3650 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3651 "the hardware maximum %u", vsi_count,
3652 hw->func_caps.num_vsis);
3660 i40e_pf_get_switch_config(struct i40e_pf *pf)
3662 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3663 struct i40e_aqc_get_switch_config_resp *switch_config;
3664 struct i40e_aqc_switch_config_element_resp *element;
3665 uint16_t start_seid = 0, num_reported;
3668 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3669 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3670 if (!switch_config) {
3671 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3675 /* Get the switch configurations */
3676 ret = i40e_aq_get_switch_config(hw, switch_config,
3677 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3678 if (ret != I40E_SUCCESS) {
3679 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3682 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3683 if (num_reported != 1) { /* The number should be 1 */
3684 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3688 /* Parse the switch configuration elements */
3689 element = &(switch_config->element[0]);
3690 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3691 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3692 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3694 PMD_DRV_LOG(INFO, "Unknown element type");
3697 rte_free(switch_config);
3703 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3706 struct pool_entry *entry;
3708 if (pool == NULL || num == 0)
3711 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3712 if (entry == NULL) {
3713 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3717 /* queue heap initialize */
3718 pool->num_free = num;
3719 pool->num_alloc = 0;
3721 LIST_INIT(&pool->alloc_list);
3722 LIST_INIT(&pool->free_list);
3724 /* Initialize element */
3728 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3733 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3735 struct pool_entry *entry, *next_entry;
3740 for (entry = LIST_FIRST(&pool->alloc_list);
3741 entry && (next_entry = LIST_NEXT(entry, next), 1);
3742 entry = next_entry) {
3743 LIST_REMOVE(entry, next);
3747 for (entry = LIST_FIRST(&pool->free_list);
3748 entry && (next_entry = LIST_NEXT(entry, next), 1);
3749 entry = next_entry) {
3750 LIST_REMOVE(entry, next);
3755 pool->num_alloc = 0;
3757 LIST_INIT(&pool->alloc_list);
3758 LIST_INIT(&pool->free_list);
3762 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3765 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3766 uint32_t pool_offset;
3770 PMD_DRV_LOG(ERR, "Invalid parameter");
3774 pool_offset = base - pool->base;
3775 /* Lookup in alloc list */
3776 LIST_FOREACH(entry, &pool->alloc_list, next) {
3777 if (entry->base == pool_offset) {
3778 valid_entry = entry;
3779 LIST_REMOVE(entry, next);
3784 /* Not find, return */
3785 if (valid_entry == NULL) {
3786 PMD_DRV_LOG(ERR, "Failed to find entry");
3791 * Found it, move it to free list and try to merge.
3792 * In order to make merge easier, always sort it by qbase.
3793 * Find adjacent prev and last entries.
3796 LIST_FOREACH(entry, &pool->free_list, next) {
3797 if (entry->base > valid_entry->base) {
3805 /* Try to merge with next one*/
3807 /* Merge with next one */
3808 if (valid_entry->base + valid_entry->len == next->base) {
3809 next->base = valid_entry->base;
3810 next->len += valid_entry->len;
3811 rte_free(valid_entry);
3818 /* Merge with previous one */
3819 if (prev->base + prev->len == valid_entry->base) {
3820 prev->len += valid_entry->len;
3821 /* If it merge with next one, remove next node */
3823 LIST_REMOVE(valid_entry, next);
3824 rte_free(valid_entry);
3826 rte_free(valid_entry);
3832 /* Not find any entry to merge, insert */
3835 LIST_INSERT_AFTER(prev, valid_entry, next);
3836 else if (next != NULL)
3837 LIST_INSERT_BEFORE(next, valid_entry, next);
3838 else /* It's empty list, insert to head */
3839 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3842 pool->num_free += valid_entry->len;
3843 pool->num_alloc -= valid_entry->len;
3849 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3852 struct pool_entry *entry, *valid_entry;
3854 if (pool == NULL || num == 0) {
3855 PMD_DRV_LOG(ERR, "Invalid parameter");
3859 if (pool->num_free < num) {
3860 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3861 num, pool->num_free);
3866 /* Lookup in free list and find most fit one */
3867 LIST_FOREACH(entry, &pool->free_list, next) {
3868 if (entry->len >= num) {
3870 if (entry->len == num) {
3871 valid_entry = entry;
3874 if (valid_entry == NULL || valid_entry->len > entry->len)
3875 valid_entry = entry;
3879 /* Not find one to satisfy the request, return */
3880 if (valid_entry == NULL) {
3881 PMD_DRV_LOG(ERR, "No valid entry found");
3885 * The entry have equal queue number as requested,
3886 * remove it from alloc_list.
3888 if (valid_entry->len == num) {
3889 LIST_REMOVE(valid_entry, next);
3892 * The entry have more numbers than requested,
3893 * create a new entry for alloc_list and minus its
3894 * queue base and number in free_list.
3896 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3897 if (entry == NULL) {
3898 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3902 entry->base = valid_entry->base;
3904 valid_entry->base += num;
3905 valid_entry->len -= num;
3906 valid_entry = entry;
3909 /* Insert it into alloc list, not sorted */
3910 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3912 pool->num_free -= valid_entry->len;
3913 pool->num_alloc += valid_entry->len;
3915 return valid_entry->base + pool->base;
3919 * bitmap_is_subset - Check whether src2 is subset of src1
3922 bitmap_is_subset(uint8_t src1, uint8_t src2)
3924 return !((src1 ^ src2) & src2);
3927 static enum i40e_status_code
3928 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3930 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3932 /* If DCB is not supported, only default TC is supported */
3933 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3934 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3935 return I40E_NOT_SUPPORTED;
3938 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3939 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3940 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3942 return I40E_NOT_SUPPORTED;
3944 return I40E_SUCCESS;
3948 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3949 struct i40e_vsi_vlan_pvid_info *info)
3952 struct i40e_vsi_context ctxt;
3953 uint8_t vlan_flags = 0;
3956 if (vsi == NULL || info == NULL) {
3957 PMD_DRV_LOG(ERR, "invalid parameters");
3958 return I40E_ERR_PARAM;
3962 vsi->info.pvid = info->config.pvid;
3964 * If insert pvid is enabled, only tagged pkts are
3965 * allowed to be sent out.
3967 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3968 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3971 if (info->config.reject.tagged == 0)
3972 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3974 if (info->config.reject.untagged == 0)
3975 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3977 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3978 I40E_AQ_VSI_PVLAN_MODE_MASK);
3979 vsi->info.port_vlan_flags |= vlan_flags;
3980 vsi->info.valid_sections =
3981 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3982 memset(&ctxt, 0, sizeof(ctxt));
3983 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3984 ctxt.seid = vsi->seid;
3986 hw = I40E_VSI_TO_HW(vsi);
3987 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3988 if (ret != I40E_SUCCESS)
3989 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3995 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3997 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3999 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4001 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4002 if (ret != I40E_SUCCESS)
4006 PMD_DRV_LOG(ERR, "seid not valid");
4010 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4011 tc_bw_data.tc_valid_bits = enabled_tcmap;
4012 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4013 tc_bw_data.tc_bw_credits[i] =
4014 (enabled_tcmap & (1 << i)) ? 1 : 0;
4016 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4017 if (ret != I40E_SUCCESS) {
4018 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4022 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4023 sizeof(vsi->info.qs_handle));
4024 return I40E_SUCCESS;
4027 static enum i40e_status_code
4028 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4029 struct i40e_aqc_vsi_properties_data *info,
4030 uint8_t enabled_tcmap)
4032 enum i40e_status_code ret;
4033 int i, total_tc = 0;
4034 uint16_t qpnum_per_tc, bsf, qp_idx;
4036 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4037 if (ret != I40E_SUCCESS)
4040 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4041 if (enabled_tcmap & (1 << i))
4043 vsi->enabled_tc = enabled_tcmap;
4045 /* Number of queues per enabled TC */
4046 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4047 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4048 bsf = rte_bsf32(qpnum_per_tc);
4050 /* Adjust the queue number to actual queues that can be applied */
4051 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4052 vsi->nb_qps = qpnum_per_tc * total_tc;
4055 * Configure TC and queue mapping parameters, for enabled TC,
4056 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4057 * default queue will serve it.
4060 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4061 if (vsi->enabled_tc & (1 << i)) {
4062 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4063 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4064 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4065 qp_idx += qpnum_per_tc;
4067 info->tc_mapping[i] = 0;
4070 /* Associate queue number with VSI */
4071 if (vsi->type == I40E_VSI_SRIOV) {
4072 info->mapping_flags |=
4073 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4074 for (i = 0; i < vsi->nb_qps; i++)
4075 info->queue_mapping[i] =
4076 rte_cpu_to_le_16(vsi->base_queue + i);
4078 info->mapping_flags |=
4079 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4080 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4082 info->valid_sections |=
4083 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4085 return I40E_SUCCESS;
4089 i40e_veb_release(struct i40e_veb *veb)
4091 struct i40e_vsi *vsi;
4097 if (!TAILQ_EMPTY(&veb->head)) {
4098 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4101 /* associate_vsi field is NULL for floating VEB */
4102 if (veb->associate_vsi != NULL) {
4103 vsi = veb->associate_vsi;
4104 hw = I40E_VSI_TO_HW(vsi);
4106 vsi->uplink_seid = veb->uplink_seid;
4109 veb->associate_pf->main_vsi->floating_veb = NULL;
4110 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4113 i40e_aq_delete_element(hw, veb->seid, NULL);
4115 return I40E_SUCCESS;
4119 static struct i40e_veb *
4120 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4122 struct i40e_veb *veb;
4128 "veb setup failed, associated PF shouldn't null");
4131 hw = I40E_PF_TO_HW(pf);
4133 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4135 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4139 veb->associate_vsi = vsi;
4140 veb->associate_pf = pf;
4141 TAILQ_INIT(&veb->head);
4142 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4144 /* create floating veb if vsi is NULL */
4146 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4147 I40E_DEFAULT_TCMAP, false,
4148 &veb->seid, false, NULL);
4150 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4151 true, &veb->seid, false, NULL);
4154 if (ret != I40E_SUCCESS) {
4155 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4156 hw->aq.asq_last_status);
4160 /* get statistics index */
4161 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4162 &veb->stats_idx, NULL, NULL, NULL);
4163 if (ret != I40E_SUCCESS) {
4164 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4165 hw->aq.asq_last_status);
4168 /* Get VEB bandwidth, to be implemented */
4169 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4171 vsi->uplink_seid = veb->seid;
4180 i40e_vsi_release(struct i40e_vsi *vsi)
4184 struct i40e_vsi_list *vsi_list;
4187 struct i40e_mac_filter *f;
4188 uint16_t user_param;
4191 return I40E_SUCCESS;
4193 user_param = vsi->user_param;
4195 pf = I40E_VSI_TO_PF(vsi);
4196 hw = I40E_VSI_TO_HW(vsi);
4198 /* VSI has child to attach, release child first */
4200 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4201 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4204 i40e_veb_release(vsi->veb);
4207 if (vsi->floating_veb) {
4208 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4209 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4214 /* Remove all macvlan filters of the VSI */
4215 i40e_vsi_remove_all_macvlan_filter(vsi);
4216 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4219 if (vsi->type != I40E_VSI_MAIN &&
4220 ((vsi->type != I40E_VSI_SRIOV) ||
4221 !pf->floating_veb_list[user_param])) {
4222 /* Remove vsi from parent's sibling list */
4223 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4224 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4225 return I40E_ERR_PARAM;
4227 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4228 &vsi->sib_vsi_list, list);
4230 /* Remove all switch element of the VSI */
4231 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4232 if (ret != I40E_SUCCESS)
4233 PMD_DRV_LOG(ERR, "Failed to delete element");
4236 if ((vsi->type == I40E_VSI_SRIOV) &&
4237 pf->floating_veb_list[user_param]) {
4238 /* Remove vsi from parent's sibling list */
4239 if (vsi->parent_vsi == NULL ||
4240 vsi->parent_vsi->floating_veb == NULL) {
4241 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4242 return I40E_ERR_PARAM;
4244 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4245 &vsi->sib_vsi_list, list);
4247 /* Remove all switch element of the VSI */
4248 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4249 if (ret != I40E_SUCCESS)
4250 PMD_DRV_LOG(ERR, "Failed to delete element");
4253 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4255 if (vsi->type != I40E_VSI_SRIOV)
4256 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4259 return I40E_SUCCESS;
4263 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4265 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4266 struct i40e_aqc_remove_macvlan_element_data def_filter;
4267 struct i40e_mac_filter_info filter;
4270 if (vsi->type != I40E_VSI_MAIN)
4271 return I40E_ERR_CONFIG;
4272 memset(&def_filter, 0, sizeof(def_filter));
4273 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4275 def_filter.vlan_tag = 0;
4276 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4277 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4278 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4279 if (ret != I40E_SUCCESS) {
4280 struct i40e_mac_filter *f;
4281 struct ether_addr *mac;
4283 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4285 /* It needs to add the permanent mac into mac list */
4286 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4288 PMD_DRV_LOG(ERR, "failed to allocate memory");
4289 return I40E_ERR_NO_MEMORY;
4291 mac = &f->mac_info.mac_addr;
4292 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4294 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4295 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4300 (void)rte_memcpy(&filter.mac_addr,
4301 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4302 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4303 return i40e_vsi_add_mac(vsi, &filter);
4307 * i40e_vsi_get_bw_config - Query VSI BW Information
4308 * @vsi: the VSI to be queried
4310 * Returns 0 on success, negative value on failure
4312 static enum i40e_status_code
4313 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4315 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4316 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4317 struct i40e_hw *hw = &vsi->adapter->hw;
4322 memset(&bw_config, 0, sizeof(bw_config));
4323 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4324 if (ret != I40E_SUCCESS) {
4325 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4326 hw->aq.asq_last_status);
4330 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4331 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4332 &ets_sla_config, NULL);
4333 if (ret != I40E_SUCCESS) {
4334 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4335 "configuration %u", hw->aq.asq_last_status);
4339 /* store and print out BW info */
4340 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4341 vsi->bw_info.bw_max = bw_config.max_bw;
4342 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4343 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4344 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4345 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4347 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4348 vsi->bw_info.bw_ets_share_credits[i] =
4349 ets_sla_config.share_credits[i];
4350 vsi->bw_info.bw_ets_credits[i] =
4351 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4352 /* 4 bits per TC, 4th bit is reserved */
4353 vsi->bw_info.bw_ets_max[i] =
4354 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4355 RTE_LEN2MASK(3, uint8_t));
4356 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4357 vsi->bw_info.bw_ets_share_credits[i]);
4358 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4359 vsi->bw_info.bw_ets_credits[i]);
4360 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4361 vsi->bw_info.bw_ets_max[i]);
4364 return I40E_SUCCESS;
4367 /* i40e_enable_pf_lb
4368 * @pf: pointer to the pf structure
4370 * allow loopback on pf
4373 i40e_enable_pf_lb(struct i40e_pf *pf)
4375 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4376 struct i40e_vsi_context ctxt;
4379 /* Use the FW API if FW >= v5.0 */
4380 if (hw->aq.fw_maj_ver < 5) {
4381 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4385 memset(&ctxt, 0, sizeof(ctxt));
4386 ctxt.seid = pf->main_vsi_seid;
4387 ctxt.pf_num = hw->pf_id;
4388 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4390 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4391 ret, hw->aq.asq_last_status);
4394 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4395 ctxt.info.valid_sections =
4396 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4397 ctxt.info.switch_id |=
4398 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4400 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4402 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4403 hw->aq.asq_last_status);
4408 i40e_vsi_setup(struct i40e_pf *pf,
4409 enum i40e_vsi_type type,
4410 struct i40e_vsi *uplink_vsi,
4411 uint16_t user_param)
4413 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4414 struct i40e_vsi *vsi;
4415 struct i40e_mac_filter_info filter;
4417 struct i40e_vsi_context ctxt;
4418 struct ether_addr broadcast =
4419 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4421 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4422 uplink_vsi == NULL) {
4423 PMD_DRV_LOG(ERR, "VSI setup failed, "
4424 "VSI link shouldn't be NULL");
4428 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4429 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4430 "uplink VSI should be NULL");
4435 * 1.type is not MAIN and uplink vsi is not NULL
4436 * If uplink vsi didn't setup VEB, create one first under veb field
4437 * 2.type is SRIOV and the uplink is NULL
4438 * If floating VEB is NULL, create one veb under floating veb field
4441 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4442 uplink_vsi->veb == NULL) {
4443 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4445 if (uplink_vsi->veb == NULL) {
4446 PMD_DRV_LOG(ERR, "VEB setup failed");
4449 /* set ALLOWLOOPBACk on pf, when veb is created */
4450 i40e_enable_pf_lb(pf);
4453 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4454 pf->main_vsi->floating_veb == NULL) {
4455 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4457 if (pf->main_vsi->floating_veb == NULL) {
4458 PMD_DRV_LOG(ERR, "VEB setup failed");
4463 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4465 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4468 TAILQ_INIT(&vsi->mac_list);
4470 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4471 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4472 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4473 vsi->user_param = user_param;
4474 /* Allocate queues */
4475 switch (vsi->type) {
4476 case I40E_VSI_MAIN :
4477 vsi->nb_qps = pf->lan_nb_qps;
4479 case I40E_VSI_SRIOV :
4480 vsi->nb_qps = pf->vf_nb_qps;
4482 case I40E_VSI_VMDQ2:
4483 vsi->nb_qps = pf->vmdq_nb_qps;
4486 vsi->nb_qps = pf->fdir_nb_qps;
4492 * The filter status descriptor is reported in rx queue 0,
4493 * while the tx queue for fdir filter programming has no
4494 * such constraints, can be non-zero queues.
4495 * To simplify it, choose FDIR vsi use queue 0 pair.
4496 * To make sure it will use queue 0 pair, queue allocation
4497 * need be done before this function is called
4499 if (type != I40E_VSI_FDIR) {
4500 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4502 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4506 vsi->base_queue = ret;
4508 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4510 /* VF has MSIX interrupt in VF range, don't allocate here */
4511 if (type == I40E_VSI_MAIN) {
4512 ret = i40e_res_pool_alloc(&pf->msix_pool,
4513 RTE_MIN(vsi->nb_qps,
4514 RTE_MAX_RXTX_INTR_VEC_ID));
4516 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4518 goto fail_queue_alloc;
4520 vsi->msix_intr = ret;
4521 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4522 } else if (type != I40E_VSI_SRIOV) {
4523 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4525 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4526 goto fail_queue_alloc;
4528 vsi->msix_intr = ret;
4536 if (type == I40E_VSI_MAIN) {
4537 /* For main VSI, no need to add since it's default one */
4538 vsi->uplink_seid = pf->mac_seid;
4539 vsi->seid = pf->main_vsi_seid;
4540 /* Bind queues with specific MSIX interrupt */
4542 * Needs 2 interrupt at least, one for misc cause which will
4543 * enabled from OS side, Another for queues binding the
4544 * interrupt from device side only.
4547 /* Get default VSI parameters from hardware */
4548 memset(&ctxt, 0, sizeof(ctxt));
4549 ctxt.seid = vsi->seid;
4550 ctxt.pf_num = hw->pf_id;
4551 ctxt.uplink_seid = vsi->uplink_seid;
4553 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4554 if (ret != I40E_SUCCESS) {
4555 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4556 goto fail_msix_alloc;
4558 (void)rte_memcpy(&vsi->info, &ctxt.info,
4559 sizeof(struct i40e_aqc_vsi_properties_data));
4560 vsi->vsi_id = ctxt.vsi_number;
4561 vsi->info.valid_sections = 0;
4563 /* Configure tc, enabled TC0 only */
4564 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4566 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4567 goto fail_msix_alloc;
4570 /* TC, queue mapping */
4571 memset(&ctxt, 0, sizeof(ctxt));
4572 vsi->info.valid_sections |=
4573 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4574 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4575 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4576 (void)rte_memcpy(&ctxt.info, &vsi->info,
4577 sizeof(struct i40e_aqc_vsi_properties_data));
4578 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4579 I40E_DEFAULT_TCMAP);
4580 if (ret != I40E_SUCCESS) {
4581 PMD_DRV_LOG(ERR, "Failed to configure "
4582 "TC queue mapping");
4583 goto fail_msix_alloc;
4585 ctxt.seid = vsi->seid;
4586 ctxt.pf_num = hw->pf_id;
4587 ctxt.uplink_seid = vsi->uplink_seid;
4590 /* Update VSI parameters */
4591 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4592 if (ret != I40E_SUCCESS) {
4593 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4594 goto fail_msix_alloc;
4597 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4598 sizeof(vsi->info.tc_mapping));
4599 (void)rte_memcpy(&vsi->info.queue_mapping,
4600 &ctxt.info.queue_mapping,
4601 sizeof(vsi->info.queue_mapping));
4602 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4603 vsi->info.valid_sections = 0;
4605 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4609 * Updating default filter settings are necessary to prevent
4610 * reception of tagged packets.
4611 * Some old firmware configurations load a default macvlan
4612 * filter which accepts both tagged and untagged packets.
4613 * The updating is to use a normal filter instead if needed.
4614 * For NVM 4.2.2 or after, the updating is not needed anymore.
4615 * The firmware with correct configurations load the default
4616 * macvlan filter which is expected and cannot be removed.
4618 i40e_update_default_filter_setting(vsi);
4619 i40e_config_qinq(hw, vsi);
4620 } else if (type == I40E_VSI_SRIOV) {
4621 memset(&ctxt, 0, sizeof(ctxt));
4623 * For other VSI, the uplink_seid equals to uplink VSI's
4624 * uplink_seid since they share same VEB
4626 if (uplink_vsi == NULL)
4627 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4629 vsi->uplink_seid = uplink_vsi->uplink_seid;
4630 ctxt.pf_num = hw->pf_id;
4631 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4632 ctxt.uplink_seid = vsi->uplink_seid;
4633 ctxt.connection_type = 0x1;
4634 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4636 /* Use the VEB configuration if FW >= v5.0 */
4637 if (hw->aq.fw_maj_ver >= 5) {
4638 /* Configure switch ID */
4639 ctxt.info.valid_sections |=
4640 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4641 ctxt.info.switch_id =
4642 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4645 /* Configure port/vlan */
4646 ctxt.info.valid_sections |=
4647 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4648 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4649 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4650 I40E_DEFAULT_TCMAP);
4651 if (ret != I40E_SUCCESS) {
4652 PMD_DRV_LOG(ERR, "Failed to configure "
4653 "TC queue mapping");
4654 goto fail_msix_alloc;
4656 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4657 ctxt.info.valid_sections |=
4658 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4660 * Since VSI is not created yet, only configure parameter,
4661 * will add vsi below.
4664 i40e_config_qinq(hw, vsi);
4665 } else if (type == I40E_VSI_VMDQ2) {
4666 memset(&ctxt, 0, sizeof(ctxt));
4668 * For other VSI, the uplink_seid equals to uplink VSI's
4669 * uplink_seid since they share same VEB
4671 vsi->uplink_seid = uplink_vsi->uplink_seid;
4672 ctxt.pf_num = hw->pf_id;
4674 ctxt.uplink_seid = vsi->uplink_seid;
4675 ctxt.connection_type = 0x1;
4676 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4678 ctxt.info.valid_sections |=
4679 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4680 /* user_param carries flag to enable loop back */
4682 ctxt.info.switch_id =
4683 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4684 ctxt.info.switch_id |=
4685 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4688 /* Configure port/vlan */
4689 ctxt.info.valid_sections |=
4690 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4691 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4692 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4693 I40E_DEFAULT_TCMAP);
4694 if (ret != I40E_SUCCESS) {
4695 PMD_DRV_LOG(ERR, "Failed to configure "
4696 "TC queue mapping");
4697 goto fail_msix_alloc;
4699 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4700 ctxt.info.valid_sections |=
4701 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4702 } else if (type == I40E_VSI_FDIR) {
4703 memset(&ctxt, 0, sizeof(ctxt));
4704 vsi->uplink_seid = uplink_vsi->uplink_seid;
4705 ctxt.pf_num = hw->pf_id;
4707 ctxt.uplink_seid = vsi->uplink_seid;
4708 ctxt.connection_type = 0x1; /* regular data port */
4709 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4710 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4711 I40E_DEFAULT_TCMAP);
4712 if (ret != I40E_SUCCESS) {
4713 PMD_DRV_LOG(ERR, "Failed to configure "
4714 "TC queue mapping.");
4715 goto fail_msix_alloc;
4717 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4718 ctxt.info.valid_sections |=
4719 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4721 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4722 goto fail_msix_alloc;
4725 if (vsi->type != I40E_VSI_MAIN) {
4726 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4727 if (ret != I40E_SUCCESS) {
4728 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4729 hw->aq.asq_last_status);
4730 goto fail_msix_alloc;
4732 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4733 vsi->info.valid_sections = 0;
4734 vsi->seid = ctxt.seid;
4735 vsi->vsi_id = ctxt.vsi_number;
4736 vsi->sib_vsi_list.vsi = vsi;
4737 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4738 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4739 &vsi->sib_vsi_list, list);
4741 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4742 &vsi->sib_vsi_list, list);
4746 /* MAC/VLAN configuration */
4747 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4748 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4750 ret = i40e_vsi_add_mac(vsi, &filter);
4751 if (ret != I40E_SUCCESS) {
4752 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4753 goto fail_msix_alloc;
4756 /* Get VSI BW information */
4757 i40e_vsi_get_bw_config(vsi);
4760 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4762 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4768 /* Configure vlan filter on or off */
4770 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4773 struct i40e_mac_filter *f;
4775 struct i40e_mac_filter_info *mac_filter;
4776 enum rte_mac_filter_type desired_filter;
4777 int ret = I40E_SUCCESS;
4780 /* Filter to match MAC and VLAN */
4781 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4783 /* Filter to match only MAC */
4784 desired_filter = RTE_MAC_PERFECT_MATCH;
4789 mac_filter = rte_zmalloc("mac_filter_info_data",
4790 num * sizeof(*mac_filter), 0);
4791 if (mac_filter == NULL) {
4792 PMD_DRV_LOG(ERR, "failed to allocate memory");
4793 return I40E_ERR_NO_MEMORY;
4798 /* Remove all existing mac */
4799 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4800 mac_filter[i] = f->mac_info;
4801 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4803 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4804 on ? "enable" : "disable");
4810 /* Override with new filter */
4811 for (i = 0; i < num; i++) {
4812 mac_filter[i].filter_type = desired_filter;
4813 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4815 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4816 on ? "enable" : "disable");
4822 rte_free(mac_filter);
4826 /* Configure vlan stripping on or off */
4828 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4830 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4831 struct i40e_vsi_context ctxt;
4833 int ret = I40E_SUCCESS;
4835 /* Check if it has been already on or off */
4836 if (vsi->info.valid_sections &
4837 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4839 if ((vsi->info.port_vlan_flags &
4840 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4841 return 0; /* already on */
4843 if ((vsi->info.port_vlan_flags &
4844 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4845 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4846 return 0; /* already off */
4851 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4853 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4854 vsi->info.valid_sections =
4855 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4856 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4857 vsi->info.port_vlan_flags |= vlan_flags;
4858 ctxt.seid = vsi->seid;
4859 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4860 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4862 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4863 on ? "enable" : "disable");
4869 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4871 struct rte_eth_dev_data *data = dev->data;
4875 /* Apply vlan offload setting */
4876 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4877 i40e_vlan_offload_set(dev, mask);
4879 /* Apply double-vlan setting, not implemented yet */
4881 /* Apply pvid setting */
4882 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4883 data->dev_conf.txmode.hw_vlan_insert_pvid);
4885 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4891 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4893 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4895 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4899 i40e_update_flow_control(struct i40e_hw *hw)
4901 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4902 struct i40e_link_status link_status;
4903 uint32_t rxfc = 0, txfc = 0, reg;
4907 memset(&link_status, 0, sizeof(link_status));
4908 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4909 if (ret != I40E_SUCCESS) {
4910 PMD_DRV_LOG(ERR, "Failed to get link status information");
4911 goto write_reg; /* Disable flow control */
4914 an_info = hw->phy.link_info.an_info;
4915 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4916 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4917 ret = I40E_ERR_NOT_READY;
4918 goto write_reg; /* Disable flow control */
4921 * If link auto negotiation is enabled, flow control needs to
4922 * be configured according to it
4924 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4925 case I40E_LINK_PAUSE_RXTX:
4928 hw->fc.current_mode = I40E_FC_FULL;
4930 case I40E_AQ_LINK_PAUSE_RX:
4932 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4934 case I40E_AQ_LINK_PAUSE_TX:
4936 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4939 hw->fc.current_mode = I40E_FC_NONE;
4944 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4945 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4946 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4947 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4948 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4949 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4956 i40e_pf_setup(struct i40e_pf *pf)
4958 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4959 struct i40e_filter_control_settings settings;
4960 struct i40e_vsi *vsi;
4963 /* Clear all stats counters */
4964 pf->offset_loaded = FALSE;
4965 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4966 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4968 ret = i40e_pf_get_switch_config(pf);
4969 if (ret != I40E_SUCCESS) {
4970 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4973 if (pf->flags & I40E_FLAG_FDIR) {
4974 /* make queue allocated first, let FDIR use queue pair 0*/
4975 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4976 if (ret != I40E_FDIR_QUEUE_ID) {
4977 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4979 pf->flags &= ~I40E_FLAG_FDIR;
4982 /* main VSI setup */
4983 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4985 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4986 return I40E_ERR_NOT_READY;
4990 /* Configure filter control */
4991 memset(&settings, 0, sizeof(settings));
4992 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4993 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4994 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4995 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4997 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4998 hw->func_caps.rss_table_size);
4999 return I40E_ERR_PARAM;
5001 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5002 "size: %u\n", hw->func_caps.rss_table_size);
5003 pf->hash_lut_size = hw->func_caps.rss_table_size;
5005 /* Enable ethtype and macvlan filters */
5006 settings.enable_ethtype = TRUE;
5007 settings.enable_macvlan = TRUE;
5008 ret = i40e_set_filter_control(hw, &settings);
5010 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5013 /* Update flow control according to the auto negotiation */
5014 i40e_update_flow_control(hw);
5016 return I40E_SUCCESS;
5020 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5026 * Set or clear TX Queue Disable flags,
5027 * which is required by hardware.
5029 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5030 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5032 /* Wait until the request is finished */
5033 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5034 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5035 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5036 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5037 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5043 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5044 return I40E_SUCCESS; /* already on, skip next steps */
5046 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5047 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5049 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5050 return I40E_SUCCESS; /* already off, skip next steps */
5051 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5053 /* Write the register */
5054 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5055 /* Check the result */
5056 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5057 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5058 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5060 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5061 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5064 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5065 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5069 /* Check if it is timeout */
5070 if (j >= I40E_CHK_Q_ENA_COUNT) {
5071 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5072 (on ? "enable" : "disable"), q_idx);
5073 return I40E_ERR_TIMEOUT;
5076 return I40E_SUCCESS;
5079 /* Swith on or off the tx queues */
5081 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5083 struct rte_eth_dev_data *dev_data = pf->dev_data;
5084 struct i40e_tx_queue *txq;
5085 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5089 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5090 txq = dev_data->tx_queues[i];
5091 /* Don't operate the queue if not configured or
5092 * if starting only per queue */
5093 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5096 ret = i40e_dev_tx_queue_start(dev, i);
5098 ret = i40e_dev_tx_queue_stop(dev, i);
5099 if ( ret != I40E_SUCCESS)
5103 return I40E_SUCCESS;
5107 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5112 /* Wait until the request is finished */
5113 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5114 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5115 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5116 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5117 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5122 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5123 return I40E_SUCCESS; /* Already on, skip next steps */
5124 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5126 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5127 return I40E_SUCCESS; /* Already off, skip next steps */
5128 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5131 /* Write the register */
5132 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5133 /* Check the result */
5134 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5135 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5136 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5138 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5139 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5142 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5143 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5148 /* Check if it is timeout */
5149 if (j >= I40E_CHK_Q_ENA_COUNT) {
5150 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5151 (on ? "enable" : "disable"), q_idx);
5152 return I40E_ERR_TIMEOUT;
5155 return I40E_SUCCESS;
5157 /* Switch on or off the rx queues */
5159 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5161 struct rte_eth_dev_data *dev_data = pf->dev_data;
5162 struct i40e_rx_queue *rxq;
5163 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5167 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5168 rxq = dev_data->rx_queues[i];
5169 /* Don't operate the queue if not configured or
5170 * if starting only per queue */
5171 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5174 ret = i40e_dev_rx_queue_start(dev, i);
5176 ret = i40e_dev_rx_queue_stop(dev, i);
5177 if (ret != I40E_SUCCESS)
5181 return I40E_SUCCESS;
5184 /* Switch on or off all the rx/tx queues */
5186 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5191 /* enable rx queues before enabling tx queues */
5192 ret = i40e_dev_switch_rx_queues(pf, on);
5194 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5197 ret = i40e_dev_switch_tx_queues(pf, on);
5199 /* Stop tx queues before stopping rx queues */
5200 ret = i40e_dev_switch_tx_queues(pf, on);
5202 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5205 ret = i40e_dev_switch_rx_queues(pf, on);
5211 /* Initialize VSI for TX */
5213 i40e_dev_tx_init(struct i40e_pf *pf)
5215 struct rte_eth_dev_data *data = pf->dev_data;
5217 uint32_t ret = I40E_SUCCESS;
5218 struct i40e_tx_queue *txq;
5220 for (i = 0; i < data->nb_tx_queues; i++) {
5221 txq = data->tx_queues[i];
5222 if (!txq || !txq->q_set)
5224 ret = i40e_tx_queue_init(txq);
5225 if (ret != I40E_SUCCESS)
5228 if (ret == I40E_SUCCESS)
5229 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5235 /* Initialize VSI for RX */
5237 i40e_dev_rx_init(struct i40e_pf *pf)
5239 struct rte_eth_dev_data *data = pf->dev_data;
5240 int ret = I40E_SUCCESS;
5242 struct i40e_rx_queue *rxq;
5244 i40e_pf_config_mq_rx(pf);
5245 for (i = 0; i < data->nb_rx_queues; i++) {
5246 rxq = data->rx_queues[i];
5247 if (!rxq || !rxq->q_set)
5250 ret = i40e_rx_queue_init(rxq);
5251 if (ret != I40E_SUCCESS) {
5252 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5257 if (ret == I40E_SUCCESS)
5258 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5265 i40e_dev_rxtx_init(struct i40e_pf *pf)
5269 err = i40e_dev_tx_init(pf);
5271 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5274 err = i40e_dev_rx_init(pf);
5276 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5284 i40e_vmdq_setup(struct rte_eth_dev *dev)
5286 struct rte_eth_conf *conf = &dev->data->dev_conf;
5287 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5288 int i, err, conf_vsis, j, loop;
5289 struct i40e_vsi *vsi;
5290 struct i40e_vmdq_info *vmdq_info;
5291 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5292 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5295 * Disable interrupt to avoid message from VF. Furthermore, it will
5296 * avoid race condition in VSI creation/destroy.
5298 i40e_pf_disable_irq0(hw);
5300 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5301 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5305 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5306 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5307 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5308 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5309 pf->max_nb_vmdq_vsi);
5313 if (pf->vmdq != NULL) {
5314 PMD_INIT_LOG(INFO, "VMDQ already configured");
5318 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5319 sizeof(*vmdq_info) * conf_vsis, 0);
5321 if (pf->vmdq == NULL) {
5322 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5326 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5328 /* Create VMDQ VSI */
5329 for (i = 0; i < conf_vsis; i++) {
5330 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5331 vmdq_conf->enable_loop_back);
5333 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5337 vmdq_info = &pf->vmdq[i];
5339 vmdq_info->vsi = vsi;
5341 pf->nb_cfg_vmdq_vsi = conf_vsis;
5343 /* Configure Vlan */
5344 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5345 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5346 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5347 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5348 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5349 vmdq_conf->pool_map[i].vlan_id, j);
5351 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5352 vmdq_conf->pool_map[i].vlan_id);
5354 PMD_INIT_LOG(ERR, "Failed to add vlan");
5362 i40e_pf_enable_irq0(hw);
5367 for (i = 0; i < conf_vsis; i++)
5368 if (pf->vmdq[i].vsi == NULL)
5371 i40e_vsi_release(pf->vmdq[i].vsi);
5375 i40e_pf_enable_irq0(hw);
5380 i40e_stat_update_32(struct i40e_hw *hw,
5388 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5392 if (new_data >= *offset)
5393 *stat = (uint64_t)(new_data - *offset);
5395 *stat = (uint64_t)((new_data +
5396 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5400 i40e_stat_update_48(struct i40e_hw *hw,
5409 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5410 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5411 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5416 if (new_data >= *offset)
5417 *stat = new_data - *offset;
5419 *stat = (uint64_t)((new_data +
5420 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5422 *stat &= I40E_48_BIT_MASK;
5427 i40e_pf_disable_irq0(struct i40e_hw *hw)
5429 /* Disable all interrupt types */
5430 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5431 I40E_WRITE_FLUSH(hw);
5436 i40e_pf_enable_irq0(struct i40e_hw *hw)
5438 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5439 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5440 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5441 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5442 I40E_WRITE_FLUSH(hw);
5446 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5448 /* read pending request and disable first */
5449 i40e_pf_disable_irq0(hw);
5450 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5451 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5452 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5455 /* Link no queues with irq0 */
5456 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5457 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5461 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5463 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5464 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5467 uint32_t index, offset, val;
5472 * Try to find which VF trigger a reset, use absolute VF id to access
5473 * since the reg is global register.
5475 for (i = 0; i < pf->vf_num; i++) {
5476 abs_vf_id = hw->func_caps.vf_base_id + i;
5477 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5478 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5479 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5480 /* VFR event occured */
5481 if (val & (0x1 << offset)) {
5484 /* Clear the event first */
5485 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5487 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5489 * Only notify a VF reset event occured,
5490 * don't trigger another SW reset
5492 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5493 if (ret != I40E_SUCCESS)
5494 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5500 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5502 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5503 struct i40e_virtchnl_pf_event event;
5506 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5507 event.event_data.link_event.link_status =
5508 dev->data->dev_link.link_status;
5509 event.event_data.link_event.link_speed =
5510 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5512 for (i = 0; i < pf->vf_num; i++)
5513 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5514 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5518 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5520 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521 struct i40e_arq_event_info info;
5522 uint16_t pending, opcode;
5525 info.buf_len = I40E_AQ_BUF_SZ;
5526 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5527 if (!info.msg_buf) {
5528 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5534 ret = i40e_clean_arq_element(hw, &info, &pending);
5536 if (ret != I40E_SUCCESS) {
5537 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5538 "aq_err: %u", hw->aq.asq_last_status);
5541 opcode = rte_le_to_cpu_16(info.desc.opcode);
5544 case i40e_aqc_opc_send_msg_to_pf:
5545 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5546 i40e_pf_host_handle_vf_msg(dev,
5547 rte_le_to_cpu_16(info.desc.retval),
5548 rte_le_to_cpu_32(info.desc.cookie_high),
5549 rte_le_to_cpu_32(info.desc.cookie_low),
5553 case i40e_aqc_opc_get_link_status:
5554 ret = i40e_dev_link_update(dev, 0);
5556 i40e_notify_all_vfs_link_status(dev);
5557 _rte_eth_dev_callback_process(dev,
5558 RTE_ETH_EVENT_INTR_LSC, NULL);
5562 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5567 rte_free(info.msg_buf);
5571 * Interrupt handler triggered by NIC for handling
5572 * specific interrupt.
5575 * Pointer to interrupt handle.
5577 * The address of parameter (struct rte_eth_dev *) regsitered before.
5583 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5586 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5587 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5590 /* Disable interrupt */
5591 i40e_pf_disable_irq0(hw);
5593 /* read out interrupt causes */
5594 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5596 /* No interrupt event indicated */
5597 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5598 PMD_DRV_LOG(INFO, "No interrupt event");
5601 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5602 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5603 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5604 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5605 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5606 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5607 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5608 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5609 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5610 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5611 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5612 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5613 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5614 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5615 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5616 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5618 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5619 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5620 i40e_dev_handle_vfr_event(dev);
5622 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5623 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5624 i40e_dev_handle_aq_msg(dev);
5628 /* Enable interrupt */
5629 i40e_pf_enable_irq0(hw);
5630 rte_intr_enable(intr_handle);
5634 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5635 struct i40e_macvlan_filter *filter,
5638 int ele_num, ele_buff_size;
5639 int num, actual_num, i;
5641 int ret = I40E_SUCCESS;
5642 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5643 struct i40e_aqc_add_macvlan_element_data *req_list;
5645 if (filter == NULL || total == 0)
5646 return I40E_ERR_PARAM;
5647 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5648 ele_buff_size = hw->aq.asq_buf_size;
5650 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5651 if (req_list == NULL) {
5652 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5653 return I40E_ERR_NO_MEMORY;
5658 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5659 memset(req_list, 0, ele_buff_size);
5661 for (i = 0; i < actual_num; i++) {
5662 (void)rte_memcpy(req_list[i].mac_addr,
5663 &filter[num + i].macaddr, ETH_ADDR_LEN);
5664 req_list[i].vlan_tag =
5665 rte_cpu_to_le_16(filter[num + i].vlan_id);
5667 switch (filter[num + i].filter_type) {
5668 case RTE_MAC_PERFECT_MATCH:
5669 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5670 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5672 case RTE_MACVLAN_PERFECT_MATCH:
5673 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5675 case RTE_MAC_HASH_MATCH:
5676 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5677 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5679 case RTE_MACVLAN_HASH_MATCH:
5680 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5683 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5684 ret = I40E_ERR_PARAM;
5688 req_list[i].queue_number = 0;
5690 req_list[i].flags = rte_cpu_to_le_16(flags);
5693 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5695 if (ret != I40E_SUCCESS) {
5696 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5700 } while (num < total);
5708 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5709 struct i40e_macvlan_filter *filter,
5712 int ele_num, ele_buff_size;
5713 int num, actual_num, i;
5715 int ret = I40E_SUCCESS;
5716 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5717 struct i40e_aqc_remove_macvlan_element_data *req_list;
5719 if (filter == NULL || total == 0)
5720 return I40E_ERR_PARAM;
5722 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5723 ele_buff_size = hw->aq.asq_buf_size;
5725 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5726 if (req_list == NULL) {
5727 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5728 return I40E_ERR_NO_MEMORY;
5733 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5734 memset(req_list, 0, ele_buff_size);
5736 for (i = 0; i < actual_num; i++) {
5737 (void)rte_memcpy(req_list[i].mac_addr,
5738 &filter[num + i].macaddr, ETH_ADDR_LEN);
5739 req_list[i].vlan_tag =
5740 rte_cpu_to_le_16(filter[num + i].vlan_id);
5742 switch (filter[num + i].filter_type) {
5743 case RTE_MAC_PERFECT_MATCH:
5744 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5745 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5747 case RTE_MACVLAN_PERFECT_MATCH:
5748 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5750 case RTE_MAC_HASH_MATCH:
5751 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5752 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5754 case RTE_MACVLAN_HASH_MATCH:
5755 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5758 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5759 ret = I40E_ERR_PARAM;
5762 req_list[i].flags = rte_cpu_to_le_16(flags);
5765 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5767 if (ret != I40E_SUCCESS) {
5768 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5772 } while (num < total);
5779 /* Find out specific MAC filter */
5780 static struct i40e_mac_filter *
5781 i40e_find_mac_filter(struct i40e_vsi *vsi,
5782 struct ether_addr *macaddr)
5784 struct i40e_mac_filter *f;
5786 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5787 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5795 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5798 uint32_t vid_idx, vid_bit;
5800 if (vlan_id > ETH_VLAN_ID_MAX)
5803 vid_idx = I40E_VFTA_IDX(vlan_id);
5804 vid_bit = I40E_VFTA_BIT(vlan_id);
5806 if (vsi->vfta[vid_idx] & vid_bit)
5813 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5814 uint16_t vlan_id, bool on)
5816 uint32_t vid_idx, vid_bit;
5818 if (vlan_id > ETH_VLAN_ID_MAX)
5821 vid_idx = I40E_VFTA_IDX(vlan_id);
5822 vid_bit = I40E_VFTA_BIT(vlan_id);
5825 vsi->vfta[vid_idx] |= vid_bit;
5827 vsi->vfta[vid_idx] &= ~vid_bit;
5831 * Find all vlan options for specific mac addr,
5832 * return with actual vlan found.
5835 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5836 struct i40e_macvlan_filter *mv_f,
5837 int num, struct ether_addr *addr)
5843 * Not to use i40e_find_vlan_filter to decrease the loop time,
5844 * although the code looks complex.
5846 if (num < vsi->vlan_num)
5847 return I40E_ERR_PARAM;
5850 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5852 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5853 if (vsi->vfta[j] & (1 << k)) {
5855 PMD_DRV_LOG(ERR, "vlan number "
5857 return I40E_ERR_PARAM;
5859 (void)rte_memcpy(&mv_f[i].macaddr,
5860 addr, ETH_ADDR_LEN);
5862 j * I40E_UINT32_BIT_SIZE + k;
5868 return I40E_SUCCESS;
5872 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5873 struct i40e_macvlan_filter *mv_f,
5878 struct i40e_mac_filter *f;
5880 if (num < vsi->mac_num)
5881 return I40E_ERR_PARAM;
5883 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5885 PMD_DRV_LOG(ERR, "buffer number not match");
5886 return I40E_ERR_PARAM;
5888 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5890 mv_f[i].vlan_id = vlan;
5891 mv_f[i].filter_type = f->mac_info.filter_type;
5895 return I40E_SUCCESS;
5899 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5902 struct i40e_mac_filter *f;
5903 struct i40e_macvlan_filter *mv_f;
5904 int ret = I40E_SUCCESS;
5906 if (vsi == NULL || vsi->mac_num == 0)
5907 return I40E_ERR_PARAM;
5909 /* Case that no vlan is set */
5910 if (vsi->vlan_num == 0)
5913 num = vsi->mac_num * vsi->vlan_num;
5915 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5917 PMD_DRV_LOG(ERR, "failed to allocate memory");
5918 return I40E_ERR_NO_MEMORY;
5922 if (vsi->vlan_num == 0) {
5923 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5924 (void)rte_memcpy(&mv_f[i].macaddr,
5925 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5926 mv_f[i].vlan_id = 0;
5930 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5931 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5932 vsi->vlan_num, &f->mac_info.mac_addr);
5933 if (ret != I40E_SUCCESS)
5939 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5947 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5949 struct i40e_macvlan_filter *mv_f;
5951 int ret = I40E_SUCCESS;
5953 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5954 return I40E_ERR_PARAM;
5956 /* If it's already set, just return */
5957 if (i40e_find_vlan_filter(vsi,vlan))
5958 return I40E_SUCCESS;
5960 mac_num = vsi->mac_num;
5963 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5964 return I40E_ERR_PARAM;
5967 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5970 PMD_DRV_LOG(ERR, "failed to allocate memory");
5971 return I40E_ERR_NO_MEMORY;
5974 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5976 if (ret != I40E_SUCCESS)
5979 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5981 if (ret != I40E_SUCCESS)
5984 i40e_set_vlan_filter(vsi, vlan, 1);
5994 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5996 struct i40e_macvlan_filter *mv_f;
5998 int ret = I40E_SUCCESS;
6001 * Vlan 0 is the generic filter for untagged packets
6002 * and can't be removed.
6004 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6005 return I40E_ERR_PARAM;
6007 /* If can't find it, just return */
6008 if (!i40e_find_vlan_filter(vsi, vlan))
6009 return I40E_ERR_PARAM;
6011 mac_num = vsi->mac_num;
6014 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6015 return I40E_ERR_PARAM;
6018 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6021 PMD_DRV_LOG(ERR, "failed to allocate memory");
6022 return I40E_ERR_NO_MEMORY;
6025 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6027 if (ret != I40E_SUCCESS)
6030 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6032 if (ret != I40E_SUCCESS)
6035 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6036 if (vsi->vlan_num == 1) {
6037 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6038 if (ret != I40E_SUCCESS)
6041 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6042 if (ret != I40E_SUCCESS)
6046 i40e_set_vlan_filter(vsi, vlan, 0);
6056 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6058 struct i40e_mac_filter *f;
6059 struct i40e_macvlan_filter *mv_f;
6060 int i, vlan_num = 0;
6061 int ret = I40E_SUCCESS;
6063 /* If it's add and we've config it, return */
6064 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6066 return I40E_SUCCESS;
6067 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6068 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6071 * If vlan_num is 0, that's the first time to add mac,
6072 * set mask for vlan_id 0.
6074 if (vsi->vlan_num == 0) {
6075 i40e_set_vlan_filter(vsi, 0, 1);
6078 vlan_num = vsi->vlan_num;
6079 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6080 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6083 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6085 PMD_DRV_LOG(ERR, "failed to allocate memory");
6086 return I40E_ERR_NO_MEMORY;
6089 for (i = 0; i < vlan_num; i++) {
6090 mv_f[i].filter_type = mac_filter->filter_type;
6091 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6095 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6096 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6097 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6098 &mac_filter->mac_addr);
6099 if (ret != I40E_SUCCESS)
6103 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6104 if (ret != I40E_SUCCESS)
6107 /* Add the mac addr into mac list */
6108 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6110 PMD_DRV_LOG(ERR, "failed to allocate memory");
6111 ret = I40E_ERR_NO_MEMORY;
6114 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6116 f->mac_info.filter_type = mac_filter->filter_type;
6117 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6128 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6130 struct i40e_mac_filter *f;
6131 struct i40e_macvlan_filter *mv_f;
6133 enum rte_mac_filter_type filter_type;
6134 int ret = I40E_SUCCESS;
6136 /* Can't find it, return an error */
6137 f = i40e_find_mac_filter(vsi, addr);
6139 return I40E_ERR_PARAM;
6141 vlan_num = vsi->vlan_num;
6142 filter_type = f->mac_info.filter_type;
6143 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6144 filter_type == RTE_MACVLAN_HASH_MATCH) {
6145 if (vlan_num == 0) {
6146 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6147 return I40E_ERR_PARAM;
6149 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6150 filter_type == RTE_MAC_HASH_MATCH)
6153 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6155 PMD_DRV_LOG(ERR, "failed to allocate memory");
6156 return I40E_ERR_NO_MEMORY;
6159 for (i = 0; i < vlan_num; i++) {
6160 mv_f[i].filter_type = filter_type;
6161 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6164 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6165 filter_type == RTE_MACVLAN_HASH_MATCH) {
6166 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6167 if (ret != I40E_SUCCESS)
6171 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6172 if (ret != I40E_SUCCESS)
6175 /* Remove the mac addr into mac list */
6176 TAILQ_REMOVE(&vsi->mac_list, f, next);
6186 /* Configure hash enable flags for RSS */
6188 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6195 if (flags & ETH_RSS_FRAG_IPV4)
6196 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6197 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6198 if (type == I40E_MAC_X722) {
6199 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6200 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6202 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6204 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6205 if (type == I40E_MAC_X722) {
6206 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6207 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6208 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6210 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6212 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6213 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6214 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6215 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6216 if (flags & ETH_RSS_FRAG_IPV6)
6217 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6218 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6219 if (type == I40E_MAC_X722) {
6220 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6221 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6223 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6225 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6226 if (type == I40E_MAC_X722) {
6227 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6228 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6229 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6231 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6233 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6234 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6235 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6236 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6237 if (flags & ETH_RSS_L2_PAYLOAD)
6238 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6243 /* Parse the hash enable flags */
6245 i40e_parse_hena(uint64_t flags)
6247 uint64_t rss_hf = 0;
6251 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6252 rss_hf |= ETH_RSS_FRAG_IPV4;
6253 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6254 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6255 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6256 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6257 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6258 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6259 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6260 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6261 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6262 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6263 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6264 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6265 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6266 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6267 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6268 rss_hf |= ETH_RSS_FRAG_IPV6;
6269 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6270 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6271 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6272 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6273 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6274 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6275 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6276 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6277 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6278 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6279 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6280 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6281 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6282 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6283 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6284 rss_hf |= ETH_RSS_L2_PAYLOAD;
6291 i40e_pf_disable_rss(struct i40e_pf *pf)
6293 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6296 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6297 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6298 if (hw->mac.type == I40E_MAC_X722)
6299 hena &= ~I40E_RSS_HENA_ALL_X722;
6301 hena &= ~I40E_RSS_HENA_ALL;
6302 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6303 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6304 I40E_WRITE_FLUSH(hw);
6308 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6310 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6311 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6314 if (!key || key_len == 0) {
6315 PMD_DRV_LOG(DEBUG, "No key to be configured");
6317 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6319 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6323 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6324 struct i40e_aqc_get_set_rss_key_data *key_dw =
6325 (struct i40e_aqc_get_set_rss_key_data *)key;
6327 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6329 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6332 uint32_t *hash_key = (uint32_t *)key;
6335 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6336 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6337 I40E_WRITE_FLUSH(hw);
6344 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6346 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6347 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6350 if (!key || !key_len)
6353 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6354 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6355 (struct i40e_aqc_get_set_rss_key_data *)key);
6357 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6361 uint32_t *key_dw = (uint32_t *)key;
6364 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6365 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6367 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6373 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6375 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6380 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6381 rss_conf->rss_key_len);
6385 rss_hf = rss_conf->rss_hf;
6386 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6387 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6388 if (hw->mac.type == I40E_MAC_X722)
6389 hena &= ~I40E_RSS_HENA_ALL_X722;
6391 hena &= ~I40E_RSS_HENA_ALL;
6392 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6393 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6394 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6395 I40E_WRITE_FLUSH(hw);
6401 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6402 struct rte_eth_rss_conf *rss_conf)
6404 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6405 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6406 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6409 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6410 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6411 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6412 ? I40E_RSS_HENA_ALL_X722
6413 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6414 if (rss_hf != 0) /* Enable RSS */
6416 return 0; /* Nothing to do */
6419 if (rss_hf == 0) /* Disable RSS */
6422 return i40e_hw_rss_hash_set(pf, rss_conf);
6426 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6427 struct rte_eth_rss_conf *rss_conf)
6429 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6430 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6433 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6434 &rss_conf->rss_key_len);
6436 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6437 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6438 rss_conf->rss_hf = i40e_parse_hena(hena);
6444 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6446 switch (filter_type) {
6447 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6448 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6450 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6451 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6453 case RTE_TUNNEL_FILTER_IMAC_TENID:
6454 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6456 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6457 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6459 case ETH_TUNNEL_FILTER_IMAC:
6460 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6462 case ETH_TUNNEL_FILTER_OIP:
6463 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6465 case ETH_TUNNEL_FILTER_IIP:
6466 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6469 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6477 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6478 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6483 uint8_t i, tun_type = 0;
6484 /* internal varialbe to convert ipv6 byte order */
6485 uint32_t convert_ipv6[4];
6487 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6488 struct i40e_vsi *vsi = pf->main_vsi;
6489 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6490 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6492 cld_filter = rte_zmalloc("tunnel_filter",
6493 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6496 if (NULL == cld_filter) {
6497 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6500 pfilter = cld_filter;
6502 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6503 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6505 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6506 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6507 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6508 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6509 rte_memcpy(&pfilter->ipaddr.v4.data,
6510 &rte_cpu_to_le_32(ipv4_addr),
6511 sizeof(pfilter->ipaddr.v4.data));
6513 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6514 for (i = 0; i < 4; i++) {
6516 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6518 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6519 sizeof(pfilter->ipaddr.v6.data));
6522 /* check tunneled type */
6523 switch (tunnel_filter->tunnel_type) {
6524 case RTE_TUNNEL_TYPE_VXLAN:
6525 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6527 case RTE_TUNNEL_TYPE_NVGRE:
6528 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6530 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6531 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6534 /* Other tunnel types is not supported. */
6535 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6536 rte_free(cld_filter);
6540 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6543 rte_free(cld_filter);
6547 pfilter->flags |= rte_cpu_to_le_16(
6548 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6549 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6550 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6551 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6554 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6556 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6559 rte_free(cld_filter);
6564 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6568 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6569 if (pf->vxlan_ports[i] == port)
6577 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6581 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6583 idx = i40e_get_vxlan_port_idx(pf, port);
6585 /* Check if port already exists */
6587 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6591 /* Now check if there is space to add the new port */
6592 idx = i40e_get_vxlan_port_idx(pf, 0);
6594 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6595 "not adding port %d", port);
6599 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6602 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6606 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6609 /* New port: add it and mark its index in the bitmap */
6610 pf->vxlan_ports[idx] = port;
6611 pf->vxlan_bitmap |= (1 << idx);
6613 if (!(pf->flags & I40E_FLAG_VXLAN))
6614 pf->flags |= I40E_FLAG_VXLAN;
6620 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6623 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6625 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6626 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6630 idx = i40e_get_vxlan_port_idx(pf, port);
6633 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6637 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6638 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6642 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6645 pf->vxlan_ports[idx] = 0;
6646 pf->vxlan_bitmap &= ~(1 << idx);
6648 if (!pf->vxlan_bitmap)
6649 pf->flags &= ~I40E_FLAG_VXLAN;
6654 /* Add UDP tunneling port */
6656 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6657 struct rte_eth_udp_tunnel *udp_tunnel)
6660 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6662 if (udp_tunnel == NULL)
6665 switch (udp_tunnel->prot_type) {
6666 case RTE_TUNNEL_TYPE_VXLAN:
6667 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6670 case RTE_TUNNEL_TYPE_GENEVE:
6671 case RTE_TUNNEL_TYPE_TEREDO:
6672 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6677 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6685 /* Remove UDP tunneling port */
6687 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6688 struct rte_eth_udp_tunnel *udp_tunnel)
6691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6693 if (udp_tunnel == NULL)
6696 switch (udp_tunnel->prot_type) {
6697 case RTE_TUNNEL_TYPE_VXLAN:
6698 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6700 case RTE_TUNNEL_TYPE_GENEVE:
6701 case RTE_TUNNEL_TYPE_TEREDO:
6702 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6706 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6714 /* Calculate the maximum number of contiguous PF queues that are configured */
6716 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6718 struct rte_eth_dev_data *data = pf->dev_data;
6720 struct i40e_rx_queue *rxq;
6723 for (i = 0; i < pf->lan_nb_qps; i++) {
6724 rxq = data->rx_queues[i];
6725 if (rxq && rxq->q_set)
6736 i40e_pf_config_rss(struct i40e_pf *pf)
6738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6739 struct rte_eth_rss_conf rss_conf;
6740 uint32_t i, lut = 0;
6744 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6745 * It's necessary to calulate the actual PF queues that are configured.
6747 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6748 num = i40e_pf_calc_configured_queues_num(pf);
6750 num = pf->dev_data->nb_rx_queues;
6752 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6753 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6757 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6761 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6764 lut = (lut << 8) | (j & ((0x1 <<
6765 hw->func_caps.rss_table_entry_width) - 1));
6767 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6770 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6771 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6772 i40e_pf_disable_rss(pf);
6775 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6776 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6777 /* Random default keys */
6778 static uint32_t rss_key_default[] = {0x6b793944,
6779 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6780 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6781 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6783 rss_conf.rss_key = (uint8_t *)rss_key_default;
6784 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6788 return i40e_hw_rss_hash_set(pf, &rss_conf);
6792 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6793 struct rte_eth_tunnel_filter_conf *filter)
6795 if (pf == NULL || filter == NULL) {
6796 PMD_DRV_LOG(ERR, "Invalid parameter");
6800 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6801 PMD_DRV_LOG(ERR, "Invalid queue ID");
6805 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6806 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6810 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6811 (is_zero_ether_addr(&filter->outer_mac))) {
6812 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6816 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6817 (is_zero_ether_addr(&filter->inner_mac))) {
6818 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6825 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6826 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6828 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6833 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6834 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6837 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6838 } else if (len == 4) {
6839 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6841 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6846 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6853 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6854 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6860 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6867 switch (cfg->cfg_type) {
6868 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6869 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6872 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6880 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6881 enum rte_filter_op filter_op,
6884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6885 int ret = I40E_ERR_PARAM;
6887 switch (filter_op) {
6888 case RTE_ETH_FILTER_SET:
6889 ret = i40e_dev_global_config_set(hw,
6890 (struct rte_eth_global_cfg *)arg);
6893 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6901 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6902 enum rte_filter_op filter_op,
6905 struct rte_eth_tunnel_filter_conf *filter;
6906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6907 int ret = I40E_SUCCESS;
6909 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6911 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6912 return I40E_ERR_PARAM;
6914 switch (filter_op) {
6915 case RTE_ETH_FILTER_NOP:
6916 if (!(pf->flags & I40E_FLAG_VXLAN))
6917 ret = I40E_NOT_SUPPORTED;
6919 case RTE_ETH_FILTER_ADD:
6920 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6922 case RTE_ETH_FILTER_DELETE:
6923 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6926 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6927 ret = I40E_ERR_PARAM;
6935 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6938 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6941 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6942 ret = i40e_pf_config_rss(pf);
6944 i40e_pf_disable_rss(pf);
6949 /* Get the symmetric hash enable configurations per port */
6951 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6953 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6955 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6958 /* Set the symmetric hash enable configurations per port */
6960 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6962 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6965 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6966 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6970 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6972 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6973 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6977 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6979 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6980 I40E_WRITE_FLUSH(hw);
6984 * Get global configurations of hash function type and symmetric hash enable
6985 * per flow type (pctype). Note that global configuration means it affects all
6986 * the ports on the same NIC.
6989 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6990 struct rte_eth_hash_global_conf *g_cfg)
6992 uint32_t reg, mask = I40E_FLOW_TYPES;
6994 enum i40e_filter_pctype pctype;
6996 memset(g_cfg, 0, sizeof(*g_cfg));
6997 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6998 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6999 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7001 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7002 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7003 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7005 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7006 if (!(mask & (1UL << i)))
7008 mask &= ~(1UL << i);
7009 /* Bit set indicats the coresponding flow type is supported */
7010 g_cfg->valid_bit_mask[0] |= (1UL << i);
7011 /* if flowtype is invalid, continue */
7012 if (!I40E_VALID_FLOW(i))
7014 pctype = i40e_flowtype_to_pctype(i);
7015 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7016 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7017 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7024 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7027 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7029 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7030 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7031 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7032 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7038 * As i40e supports less than 32 flow types, only first 32 bits need to
7041 mask0 = g_cfg->valid_bit_mask[0];
7042 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7044 /* Check if any unsupported flow type configured */
7045 if ((mask0 | i40e_mask) ^ i40e_mask)
7048 if (g_cfg->valid_bit_mask[i])
7056 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7062 * Set global configurations of hash function type and symmetric hash enable
7063 * per flow type (pctype). Note any modifying global configuration will affect
7064 * all the ports on the same NIC.
7067 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7068 struct rte_eth_hash_global_conf *g_cfg)
7073 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7074 enum i40e_filter_pctype pctype;
7076 /* Check the input parameters */
7077 ret = i40e_hash_global_config_check(g_cfg);
7081 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7082 if (!(mask0 & (1UL << i)))
7084 mask0 &= ~(1UL << i);
7085 /* if flowtype is invalid, continue */
7086 if (!I40E_VALID_FLOW(i))
7088 pctype = i40e_flowtype_to_pctype(i);
7089 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7090 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7091 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7094 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7095 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7097 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7098 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7102 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7103 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7105 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7106 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7110 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7112 /* Use the default, and keep it as it is */
7115 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7118 I40E_WRITE_FLUSH(hw);
7124 * Valid input sets for hash and flow director filters per PCTYPE
7127 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7128 enum rte_filter_type filter)
7132 static const uint64_t valid_hash_inset_table[] = {
7133 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7134 I40E_INSET_DMAC | I40E_INSET_SMAC |
7135 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7137 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7138 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7139 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7140 I40E_INSET_FLEX_PAYLOAD,
7141 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7142 I40E_INSET_DMAC | I40E_INSET_SMAC |
7143 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7144 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7145 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7146 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7147 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7148 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7149 I40E_INSET_FLEX_PAYLOAD,
7150 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7151 I40E_INSET_DMAC | I40E_INSET_SMAC |
7152 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7153 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7154 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7155 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7156 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7157 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7158 I40E_INSET_FLEX_PAYLOAD,
7159 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7160 I40E_INSET_DMAC | I40E_INSET_SMAC |
7161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7163 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7164 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7165 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7166 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7167 I40E_INSET_FLEX_PAYLOAD,
7168 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7169 I40E_INSET_DMAC | I40E_INSET_SMAC |
7170 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7171 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7172 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7173 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7174 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7175 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7176 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7177 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7178 I40E_INSET_DMAC | I40E_INSET_SMAC |
7179 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7180 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7181 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7182 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7183 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7184 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7185 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7186 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7187 I40E_INSET_DMAC | I40E_INSET_SMAC |
7188 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7189 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7190 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7191 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7192 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7193 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7194 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7195 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7196 I40E_INSET_DMAC | I40E_INSET_SMAC |
7197 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7198 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7199 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7200 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7201 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7202 I40E_INSET_FLEX_PAYLOAD,
7203 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7204 I40E_INSET_DMAC | I40E_INSET_SMAC |
7205 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7206 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7207 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7208 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7209 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7210 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7211 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7212 I40E_INSET_DMAC | I40E_INSET_SMAC |
7213 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7214 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7215 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7216 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7217 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7218 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7219 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7220 I40E_INSET_DMAC | I40E_INSET_SMAC |
7221 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7222 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7223 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7224 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7225 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7226 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7227 I40E_INSET_FLEX_PAYLOAD,
7228 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7229 I40E_INSET_DMAC | I40E_INSET_SMAC |
7230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7231 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7232 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7233 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7234 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7235 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7236 I40E_INSET_FLEX_PAYLOAD,
7237 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7238 I40E_INSET_DMAC | I40E_INSET_SMAC |
7239 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7240 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7241 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7242 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7243 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7244 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7245 I40E_INSET_FLEX_PAYLOAD,
7246 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7247 I40E_INSET_DMAC | I40E_INSET_SMAC |
7248 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7249 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7250 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7251 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7252 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7253 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7254 I40E_INSET_FLEX_PAYLOAD,
7255 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7256 I40E_INSET_DMAC | I40E_INSET_SMAC |
7257 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7258 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7259 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7260 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7261 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7262 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7263 I40E_INSET_FLEX_PAYLOAD,
7264 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7265 I40E_INSET_DMAC | I40E_INSET_SMAC |
7266 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7267 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7268 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7269 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7270 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7271 I40E_INSET_FLEX_PAYLOAD,
7272 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7273 I40E_INSET_DMAC | I40E_INSET_SMAC |
7274 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7275 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7276 I40E_INSET_FLEX_PAYLOAD,
7280 * Flow director supports only fields defined in
7281 * union rte_eth_fdir_flow.
7283 static const uint64_t valid_fdir_inset_table[] = {
7284 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7285 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7286 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7287 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7288 I40E_INSET_IPV4_TTL,
7289 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7290 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7291 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7292 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7293 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7294 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7295 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7296 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7297 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7298 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7299 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7300 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7301 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7302 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7303 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7304 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7305 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7306 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7307 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7308 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7309 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7310 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7311 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7312 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7313 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7314 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7315 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7316 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7317 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7318 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7320 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7321 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7322 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7323 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7324 I40E_INSET_IPV4_TTL,
7325 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7326 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7327 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7328 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7329 I40E_INSET_IPV6_HOP_LIMIT,
7330 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7331 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7332 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7333 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7334 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7335 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7336 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7337 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7338 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7339 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7340 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7341 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7342 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7343 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7344 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7345 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7346 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7347 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7348 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7349 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7350 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7351 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7352 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7353 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7354 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7355 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7356 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7357 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7358 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7359 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7361 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7362 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7363 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7364 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7365 I40E_INSET_IPV6_HOP_LIMIT,
7366 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7367 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7368 I40E_INSET_LAST_ETHER_TYPE,
7371 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7373 if (filter == RTE_ETH_FILTER_HASH)
7374 valid = valid_hash_inset_table[pctype];
7376 valid = valid_fdir_inset_table[pctype];
7382 * Validate if the input set is allowed for a specific PCTYPE
7385 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7386 enum rte_filter_type filter, uint64_t inset)
7390 valid = i40e_get_valid_input_set(pctype, filter);
7391 if (inset & (~valid))
7397 /* default input set fields combination per pctype */
7399 i40e_get_default_input_set(uint16_t pctype)
7401 static const uint64_t default_inset_table[] = {
7402 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7403 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7404 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7405 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7406 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7407 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7408 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7409 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7410 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7411 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7412 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7413 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7414 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7415 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7416 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7417 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7418 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7419 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7420 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7421 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7423 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7424 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7425 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7426 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7427 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7428 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7429 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7430 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7431 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7432 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7433 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7434 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7435 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7436 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7437 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7438 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7439 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7440 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7441 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7442 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7443 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7444 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7446 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7447 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7448 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7449 I40E_INSET_LAST_ETHER_TYPE,
7452 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7455 return default_inset_table[pctype];
7459 * Parse the input set from index to logical bit masks
7462 i40e_parse_input_set(uint64_t *inset,
7463 enum i40e_filter_pctype pctype,
7464 enum rte_eth_input_set_field *field,
7470 static const struct {
7471 enum rte_eth_input_set_field field;
7473 } inset_convert_table[] = {
7474 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7475 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7476 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7477 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7478 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7479 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7480 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7481 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7482 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7483 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7484 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7485 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7486 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7487 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7488 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7489 I40E_INSET_IPV6_NEXT_HDR},
7490 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7491 I40E_INSET_IPV6_HOP_LIMIT},
7492 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7493 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7494 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7495 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7496 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7497 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7498 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7499 I40E_INSET_SCTP_VT},
7500 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7501 I40E_INSET_TUNNEL_DMAC},
7502 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7503 I40E_INSET_VLAN_TUNNEL},
7504 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7505 I40E_INSET_TUNNEL_ID},
7506 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7507 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7508 I40E_INSET_FLEX_PAYLOAD_W1},
7509 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7510 I40E_INSET_FLEX_PAYLOAD_W2},
7511 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7512 I40E_INSET_FLEX_PAYLOAD_W3},
7513 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7514 I40E_INSET_FLEX_PAYLOAD_W4},
7515 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7516 I40E_INSET_FLEX_PAYLOAD_W5},
7517 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7518 I40E_INSET_FLEX_PAYLOAD_W6},
7519 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7520 I40E_INSET_FLEX_PAYLOAD_W7},
7521 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7522 I40E_INSET_FLEX_PAYLOAD_W8},
7525 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7528 /* Only one item allowed for default or all */
7530 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7531 *inset = i40e_get_default_input_set(pctype);
7533 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7534 *inset = I40E_INSET_NONE;
7539 for (i = 0, *inset = 0; i < size; i++) {
7540 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7541 if (field[i] == inset_convert_table[j].field) {
7542 *inset |= inset_convert_table[j].inset;
7547 /* It contains unsupported input set, return immediately */
7548 if (j == RTE_DIM(inset_convert_table))
7556 * Translate the input set from bit masks to register aware bit masks
7560 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7570 static const struct inset_map inset_map_common[] = {
7571 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7572 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7573 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7574 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7575 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7576 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7577 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7578 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7579 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7580 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7581 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7582 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7583 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7584 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7585 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7586 {I40E_INSET_TUNNEL_DMAC,
7587 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7588 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7589 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7590 {I40E_INSET_TUNNEL_SRC_PORT,
7591 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7592 {I40E_INSET_TUNNEL_DST_PORT,
7593 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7594 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7595 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7596 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7597 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7598 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7599 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7600 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7601 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7602 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7605 /* some different registers map in x722*/
7606 static const struct inset_map inset_map_diff_x722[] = {
7607 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7608 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7609 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7610 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7613 static const struct inset_map inset_map_diff_not_x722[] = {
7614 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7615 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7616 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7617 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7623 /* Translate input set to register aware inset */
7624 if (type == I40E_MAC_X722) {
7625 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7626 if (input & inset_map_diff_x722[i].inset)
7627 val |= inset_map_diff_x722[i].inset_reg;
7630 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7631 if (input & inset_map_diff_not_x722[i].inset)
7632 val |= inset_map_diff_not_x722[i].inset_reg;
7636 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7637 if (input & inset_map_common[i].inset)
7638 val |= inset_map_common[i].inset_reg;
7645 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7648 uint64_t inset_need_mask = inset;
7650 static const struct {
7653 } inset_mask_map[] = {
7654 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7655 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7656 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7657 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7658 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7659 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7660 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7661 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7664 if (!inset || !mask || !nb_elem)
7667 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7668 /* Clear the inset bit, if no MASK is required,
7669 * for example proto + ttl
7671 if ((inset & inset_mask_map[i].inset) ==
7672 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7673 inset_need_mask &= ~inset_mask_map[i].inset;
7674 if (!inset_need_mask)
7677 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7678 if ((inset_need_mask & inset_mask_map[i].inset) ==
7679 inset_mask_map[i].inset) {
7680 if (idx >= nb_elem) {
7681 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7684 mask[idx] = inset_mask_map[i].mask;
7693 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7695 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7697 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7699 i40e_write_rx_ctl(hw, addr, val);
7700 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7701 (uint32_t)i40e_read_rx_ctl(hw, addr));
7705 i40e_filter_input_set_init(struct i40e_pf *pf)
7707 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7708 enum i40e_filter_pctype pctype;
7709 uint64_t input_set, inset_reg;
7710 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7713 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7714 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7715 if (hw->mac.type == I40E_MAC_X722) {
7716 if (!I40E_VALID_PCTYPE_X722(pctype))
7719 if (!I40E_VALID_PCTYPE(pctype))
7723 input_set = i40e_get_default_input_set(pctype);
7725 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7726 I40E_INSET_MASK_NUM_REG);
7729 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7732 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7733 (uint32_t)(inset_reg & UINT32_MAX));
7734 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7735 (uint32_t)((inset_reg >>
7736 I40E_32_BIT_WIDTH) & UINT32_MAX));
7737 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7738 (uint32_t)(inset_reg & UINT32_MAX));
7739 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7740 (uint32_t)((inset_reg >>
7741 I40E_32_BIT_WIDTH) & UINT32_MAX));
7743 for (i = 0; i < num; i++) {
7744 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7746 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7749 /*clear unused mask registers of the pctype */
7750 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7751 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7753 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7756 I40E_WRITE_FLUSH(hw);
7758 /* store the default input set */
7759 pf->hash_input_set[pctype] = input_set;
7760 pf->fdir.input_set[pctype] = input_set;
7765 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7766 struct rte_eth_input_set_conf *conf)
7768 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7769 enum i40e_filter_pctype pctype;
7770 uint64_t input_set, inset_reg = 0;
7771 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7775 PMD_DRV_LOG(ERR, "Invalid pointer");
7778 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7779 conf->op != RTE_ETH_INPUT_SET_ADD) {
7780 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7784 if (!I40E_VALID_FLOW(conf->flow_type)) {
7785 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7789 if (hw->mac.type == I40E_MAC_X722) {
7790 /* get translated pctype value in fd pctype register */
7791 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7792 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7795 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7797 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7800 PMD_DRV_LOG(ERR, "Failed to parse input set");
7803 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7805 PMD_DRV_LOG(ERR, "Invalid input set");
7808 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7809 /* get inset value in register */
7810 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7811 inset_reg <<= I40E_32_BIT_WIDTH;
7812 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7813 input_set |= pf->hash_input_set[pctype];
7815 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7816 I40E_INSET_MASK_NUM_REG);
7820 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7822 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7823 (uint32_t)(inset_reg & UINT32_MAX));
7824 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7825 (uint32_t)((inset_reg >>
7826 I40E_32_BIT_WIDTH) & UINT32_MAX));
7828 for (i = 0; i < num; i++)
7829 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7831 /*clear unused mask registers of the pctype */
7832 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7833 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7835 I40E_WRITE_FLUSH(hw);
7837 pf->hash_input_set[pctype] = input_set;
7842 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7843 struct rte_eth_input_set_conf *conf)
7845 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7846 enum i40e_filter_pctype pctype;
7847 uint64_t input_set, inset_reg = 0;
7848 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7852 PMD_DRV_LOG(ERR, "Invalid pointer");
7855 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7856 conf->op != RTE_ETH_INPUT_SET_ADD) {
7857 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7861 if (!I40E_VALID_FLOW(conf->flow_type)) {
7862 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7866 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7868 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7871 PMD_DRV_LOG(ERR, "Failed to parse input set");
7874 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7876 PMD_DRV_LOG(ERR, "Invalid input set");
7880 /* get inset value in register */
7881 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7882 inset_reg <<= I40E_32_BIT_WIDTH;
7883 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7885 /* Can not change the inset reg for flex payload for fdir,
7886 * it is done by writing I40E_PRTQF_FD_FLXINSET
7887 * in i40e_set_flex_mask_on_pctype.
7889 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7890 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7892 input_set |= pf->fdir.input_set[pctype];
7893 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7894 I40E_INSET_MASK_NUM_REG);
7898 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7900 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7901 (uint32_t)(inset_reg & UINT32_MAX));
7902 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7903 (uint32_t)((inset_reg >>
7904 I40E_32_BIT_WIDTH) & UINT32_MAX));
7906 for (i = 0; i < num; i++)
7907 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7909 /*clear unused mask registers of the pctype */
7910 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7911 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7913 I40E_WRITE_FLUSH(hw);
7915 pf->fdir.input_set[pctype] = input_set;
7920 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7925 PMD_DRV_LOG(ERR, "Invalid pointer");
7929 switch (info->info_type) {
7930 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7931 i40e_get_symmetric_hash_enable_per_port(hw,
7932 &(info->info.enable));
7934 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7935 ret = i40e_get_hash_filter_global_config(hw,
7936 &(info->info.global_conf));
7939 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7949 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7954 PMD_DRV_LOG(ERR, "Invalid pointer");
7958 switch (info->info_type) {
7959 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7960 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7962 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7963 ret = i40e_set_hash_filter_global_config(hw,
7964 &(info->info.global_conf));
7966 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7967 ret = i40e_hash_filter_inset_select(hw,
7968 &(info->info.input_set_conf));
7972 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7981 /* Operations for hash function */
7983 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7984 enum rte_filter_op filter_op,
7987 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7990 switch (filter_op) {
7991 case RTE_ETH_FILTER_NOP:
7993 case RTE_ETH_FILTER_GET:
7994 ret = i40e_hash_filter_get(hw,
7995 (struct rte_eth_hash_filter_info *)arg);
7997 case RTE_ETH_FILTER_SET:
7998 ret = i40e_hash_filter_set(hw,
7999 (struct rte_eth_hash_filter_info *)arg);
8002 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8012 * Configure ethertype filter, which can director packet by filtering
8013 * with mac address and ether_type or only ether_type
8016 i40e_ethertype_filter_set(struct i40e_pf *pf,
8017 struct rte_eth_ethertype_filter *filter,
8020 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8021 struct i40e_control_filter_stats stats;
8025 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8026 PMD_DRV_LOG(ERR, "Invalid queue ID");
8029 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8030 filter->ether_type == ETHER_TYPE_IPv6) {
8031 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8032 " control packet filter.", filter->ether_type);
8035 if (filter->ether_type == ETHER_TYPE_VLAN)
8036 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8039 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8040 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8041 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8042 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8043 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8045 memset(&stats, 0, sizeof(stats));
8046 ret = i40e_aq_add_rem_control_packet_filter(hw,
8047 filter->mac_addr.addr_bytes,
8048 filter->ether_type, flags,
8050 filter->queue, add, &stats, NULL);
8052 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8053 " mac_etype_used = %u, etype_used = %u,"
8054 " mac_etype_free = %u, etype_free = %u\n",
8055 ret, stats.mac_etype_used, stats.etype_used,
8056 stats.mac_etype_free, stats.etype_free);
8063 * Handle operations for ethertype filter.
8066 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8067 enum rte_filter_op filter_op,
8070 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8073 if (filter_op == RTE_ETH_FILTER_NOP)
8077 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8082 switch (filter_op) {
8083 case RTE_ETH_FILTER_ADD:
8084 ret = i40e_ethertype_filter_set(pf,
8085 (struct rte_eth_ethertype_filter *)arg,
8088 case RTE_ETH_FILTER_DELETE:
8089 ret = i40e_ethertype_filter_set(pf,
8090 (struct rte_eth_ethertype_filter *)arg,
8094 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8102 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8103 enum rte_filter_type filter_type,
8104 enum rte_filter_op filter_op,
8112 switch (filter_type) {
8113 case RTE_ETH_FILTER_NONE:
8114 /* For global configuration */
8115 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8117 case RTE_ETH_FILTER_HASH:
8118 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8120 case RTE_ETH_FILTER_MACVLAN:
8121 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8123 case RTE_ETH_FILTER_ETHERTYPE:
8124 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8126 case RTE_ETH_FILTER_TUNNEL:
8127 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8129 case RTE_ETH_FILTER_FDIR:
8130 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8133 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8143 * Check and enable Extended Tag.
8144 * Enabling Extended Tag is important for 40G performance.
8147 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8149 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8153 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8156 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8160 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8161 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8166 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8169 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8173 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8174 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8177 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8178 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8181 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8188 * As some registers wouldn't be reset unless a global hardware reset,
8189 * hardware initialization is needed to put those registers into an
8190 * expected initial state.
8193 i40e_hw_init(struct rte_eth_dev *dev)
8195 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8197 i40e_enable_extended_tag(dev);
8199 /* clear the PF Queue Filter control register */
8200 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8202 /* Disable symmetric hash per port */
8203 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8206 enum i40e_filter_pctype
8207 i40e_flowtype_to_pctype(uint16_t flow_type)
8209 static const enum i40e_filter_pctype pctype_table[] = {
8210 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8211 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8212 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8213 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8214 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8215 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8216 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8217 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8218 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8219 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8220 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8221 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8222 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8223 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8224 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8225 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8226 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8227 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8228 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8231 return pctype_table[flow_type];
8235 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8237 static const uint16_t flowtype_table[] = {
8238 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8239 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8240 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8241 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8242 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8243 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8244 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8245 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8246 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8247 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8248 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8249 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8250 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8251 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8252 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8253 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8254 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8255 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8256 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8257 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8258 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8259 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8260 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8261 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8262 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8263 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8264 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8265 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8266 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8267 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8268 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8271 return flowtype_table[pctype];
8275 * On X710, performance number is far from the expectation on recent firmware
8276 * versions; on XL710, performance number is also far from the expectation on
8277 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8278 * mode is enabled and port MAC address is equal to the packet destination MAC
8279 * address. The fix for this issue may not be integrated in the following
8280 * firmware version. So the workaround in software driver is needed. It needs
8281 * to modify the initial values of 3 internal only registers for both X710 and
8282 * XL710. Note that the values for X710 or XL710 could be different, and the
8283 * workaround can be removed when it is fixed in firmware in the future.
8286 /* For both X710 and XL710 */
8287 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8288 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8290 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8291 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8294 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8296 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8297 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8300 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8302 enum i40e_status_code status;
8303 struct i40e_aq_get_phy_abilities_resp phy_ab;
8306 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8317 i40e_configure_registers(struct i40e_hw *hw)
8323 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8324 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8325 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8331 for (i = 0; i < RTE_DIM(reg_table); i++) {
8332 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8333 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8334 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8336 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8339 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8342 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8345 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8349 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8350 reg_table[i].addr, reg);
8351 if (reg == reg_table[i].val)
8354 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8355 reg_table[i].val, NULL);
8357 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8358 "address of 0x%"PRIx32, reg_table[i].val,
8362 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8363 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8367 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8368 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8369 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8370 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8372 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8377 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8378 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8382 /* Configure for double VLAN RX stripping */
8383 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8384 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8385 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8386 ret = i40e_aq_debug_write_register(hw,
8387 I40E_VSI_TSR(vsi->vsi_id),
8390 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8392 return I40E_ERR_CONFIG;
8396 /* Configure for double VLAN TX insertion */
8397 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8398 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8399 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8400 ret = i40e_aq_debug_write_register(hw,
8401 I40E_VSI_L2TAGSTXVALID(
8402 vsi->vsi_id), reg, NULL);
8404 PMD_DRV_LOG(ERR, "Failed to update "
8405 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8406 return I40E_ERR_CONFIG;
8414 * i40e_aq_add_mirror_rule
8415 * @hw: pointer to the hardware structure
8416 * @seid: VEB seid to add mirror rule to
8417 * @dst_id: destination vsi seid
8418 * @entries: Buffer which contains the entities to be mirrored
8419 * @count: number of entities contained in the buffer
8420 * @rule_id:the rule_id of the rule to be added
8422 * Add a mirror rule for a given veb.
8425 static enum i40e_status_code
8426 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8427 uint16_t seid, uint16_t dst_id,
8428 uint16_t rule_type, uint16_t *entries,
8429 uint16_t count, uint16_t *rule_id)
8431 struct i40e_aq_desc desc;
8432 struct i40e_aqc_add_delete_mirror_rule cmd;
8433 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8434 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8437 enum i40e_status_code status;
8439 i40e_fill_default_direct_cmd_desc(&desc,
8440 i40e_aqc_opc_add_mirror_rule);
8441 memset(&cmd, 0, sizeof(cmd));
8443 buff_len = sizeof(uint16_t) * count;
8444 desc.datalen = rte_cpu_to_le_16(buff_len);
8446 desc.flags |= rte_cpu_to_le_16(
8447 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8448 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8449 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8450 cmd.num_entries = rte_cpu_to_le_16(count);
8451 cmd.seid = rte_cpu_to_le_16(seid);
8452 cmd.destination = rte_cpu_to_le_16(dst_id);
8454 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8455 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8456 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8458 " mirror_rules_used = %u, mirror_rules_free = %u,",
8459 hw->aq.asq_last_status, resp->rule_id,
8460 resp->mirror_rules_used, resp->mirror_rules_free);
8461 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8467 * i40e_aq_del_mirror_rule
8468 * @hw: pointer to the hardware structure
8469 * @seid: VEB seid to add mirror rule to
8470 * @entries: Buffer which contains the entities to be mirrored
8471 * @count: number of entities contained in the buffer
8472 * @rule_id:the rule_id of the rule to be delete
8474 * Delete a mirror rule for a given veb.
8477 static enum i40e_status_code
8478 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8479 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8480 uint16_t count, uint16_t rule_id)
8482 struct i40e_aq_desc desc;
8483 struct i40e_aqc_add_delete_mirror_rule cmd;
8484 uint16_t buff_len = 0;
8485 enum i40e_status_code status;
8488 i40e_fill_default_direct_cmd_desc(&desc,
8489 i40e_aqc_opc_delete_mirror_rule);
8490 memset(&cmd, 0, sizeof(cmd));
8491 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8492 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8494 cmd.num_entries = count;
8495 buff_len = sizeof(uint16_t) * count;
8496 desc.datalen = rte_cpu_to_le_16(buff_len);
8497 buff = (void *)entries;
8499 /* rule id is filled in destination field for deleting mirror rule */
8500 cmd.destination = rte_cpu_to_le_16(rule_id);
8502 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8503 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8504 cmd.seid = rte_cpu_to_le_16(seid);
8506 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8507 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8513 * i40e_mirror_rule_set
8514 * @dev: pointer to the hardware structure
8515 * @mirror_conf: mirror rule info
8516 * @sw_id: mirror rule's sw_id
8517 * @on: enable/disable
8519 * set a mirror rule.
8523 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8524 struct rte_eth_mirror_conf *mirror_conf,
8525 uint8_t sw_id, uint8_t on)
8527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8528 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8529 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8530 struct i40e_mirror_rule *parent = NULL;
8531 uint16_t seid, dst_seid, rule_id;
8535 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8537 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8538 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8539 " without veb or vfs.");
8542 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8543 PMD_DRV_LOG(ERR, "mirror table is full.");
8546 if (mirror_conf->dst_pool > pf->vf_num) {
8547 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8548 mirror_conf->dst_pool);
8552 seid = pf->main_vsi->veb->seid;
8554 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8555 if (sw_id <= it->index) {
8561 if (mirr_rule && sw_id == mirr_rule->index) {
8563 PMD_DRV_LOG(ERR, "mirror rule exists.");
8566 ret = i40e_aq_del_mirror_rule(hw, seid,
8567 mirr_rule->rule_type,
8569 mirr_rule->num_entries, mirr_rule->id);
8571 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8572 " ret = %d, aq_err = %d.",
8573 ret, hw->aq.asq_last_status);
8576 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8577 rte_free(mirr_rule);
8578 pf->nb_mirror_rule--;
8582 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8586 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8587 sizeof(struct i40e_mirror_rule) , 0);
8589 PMD_DRV_LOG(ERR, "failed to allocate memory");
8590 return I40E_ERR_NO_MEMORY;
8592 switch (mirror_conf->rule_type) {
8593 case ETH_MIRROR_VLAN:
8594 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8595 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8596 mirr_rule->entries[j] =
8597 mirror_conf->vlan.vlan_id[i];
8602 PMD_DRV_LOG(ERR, "vlan is not specified.");
8603 rte_free(mirr_rule);
8606 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8608 case ETH_MIRROR_VIRTUAL_POOL_UP:
8609 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8610 /* check if the specified pool bit is out of range */
8611 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8612 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8613 rte_free(mirr_rule);
8616 for (i = 0, j = 0; i < pf->vf_num; i++) {
8617 if (mirror_conf->pool_mask & (1ULL << i)) {
8618 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8622 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8623 /* add pf vsi to entries */
8624 mirr_rule->entries[j] = pf->main_vsi_seid;
8628 PMD_DRV_LOG(ERR, "pool is not specified.");
8629 rte_free(mirr_rule);
8632 /* egress and ingress in aq commands means from switch but not port */
8633 mirr_rule->rule_type =
8634 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8635 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8636 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8638 case ETH_MIRROR_UPLINK_PORT:
8639 /* egress and ingress in aq commands means from switch but not port*/
8640 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8642 case ETH_MIRROR_DOWNLINK_PORT:
8643 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8646 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8647 mirror_conf->rule_type);
8648 rte_free(mirr_rule);
8652 /* If the dst_pool is equal to vf_num, consider it as PF */
8653 if (mirror_conf->dst_pool == pf->vf_num)
8654 dst_seid = pf->main_vsi_seid;
8656 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8658 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8659 mirr_rule->rule_type, mirr_rule->entries,
8662 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8663 " ret = %d, aq_err = %d.",
8664 ret, hw->aq.asq_last_status);
8665 rte_free(mirr_rule);
8669 mirr_rule->index = sw_id;
8670 mirr_rule->num_entries = j;
8671 mirr_rule->id = rule_id;
8672 mirr_rule->dst_vsi_seid = dst_seid;
8675 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8677 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8679 pf->nb_mirror_rule++;
8684 * i40e_mirror_rule_reset
8685 * @dev: pointer to the device
8686 * @sw_id: mirror rule's sw_id
8688 * reset a mirror rule.
8692 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8694 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8695 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8696 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8700 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8702 seid = pf->main_vsi->veb->seid;
8704 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8705 if (sw_id == it->index) {
8711 ret = i40e_aq_del_mirror_rule(hw, seid,
8712 mirr_rule->rule_type,
8714 mirr_rule->num_entries, mirr_rule->id);
8716 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8717 " status = %d, aq_err = %d.",
8718 ret, hw->aq.asq_last_status);
8721 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8722 rte_free(mirr_rule);
8723 pf->nb_mirror_rule--;
8725 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8732 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8734 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8735 uint64_t systim_cycles;
8737 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8738 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8741 return systim_cycles;
8745 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8747 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8750 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8751 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8758 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8763 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8764 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8771 i40e_start_timecounters(struct rte_eth_dev *dev)
8773 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8774 struct i40e_adapter *adapter =
8775 (struct i40e_adapter *)dev->data->dev_private;
8776 struct rte_eth_link link;
8777 uint32_t tsync_inc_l;
8778 uint32_t tsync_inc_h;
8780 /* Get current link speed. */
8781 memset(&link, 0, sizeof(link));
8782 i40e_dev_link_update(dev, 1);
8783 rte_i40e_dev_atomic_read_link_status(dev, &link);
8785 switch (link.link_speed) {
8786 case ETH_SPEED_NUM_40G:
8787 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8788 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8790 case ETH_SPEED_NUM_10G:
8791 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8792 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8794 case ETH_SPEED_NUM_1G:
8795 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8796 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8803 /* Set the timesync increment value. */
8804 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8805 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8807 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8808 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8809 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8811 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8812 adapter->systime_tc.cc_shift = 0;
8813 adapter->systime_tc.nsec_mask = 0;
8815 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8816 adapter->rx_tstamp_tc.cc_shift = 0;
8817 adapter->rx_tstamp_tc.nsec_mask = 0;
8819 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8820 adapter->tx_tstamp_tc.cc_shift = 0;
8821 adapter->tx_tstamp_tc.nsec_mask = 0;
8825 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8827 struct i40e_adapter *adapter =
8828 (struct i40e_adapter *)dev->data->dev_private;
8830 adapter->systime_tc.nsec += delta;
8831 adapter->rx_tstamp_tc.nsec += delta;
8832 adapter->tx_tstamp_tc.nsec += delta;
8838 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8841 struct i40e_adapter *adapter =
8842 (struct i40e_adapter *)dev->data->dev_private;
8844 ns = rte_timespec_to_ns(ts);
8846 /* Set the timecounters to a new value. */
8847 adapter->systime_tc.nsec = ns;
8848 adapter->rx_tstamp_tc.nsec = ns;
8849 adapter->tx_tstamp_tc.nsec = ns;
8855 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8857 uint64_t ns, systime_cycles;
8858 struct i40e_adapter *adapter =
8859 (struct i40e_adapter *)dev->data->dev_private;
8861 systime_cycles = i40e_read_systime_cyclecounter(dev);
8862 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8863 *ts = rte_ns_to_timespec(ns);
8869 i40e_timesync_enable(struct rte_eth_dev *dev)
8871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8872 uint32_t tsync_ctl_l;
8873 uint32_t tsync_ctl_h;
8875 /* Stop the timesync system time. */
8876 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8877 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8878 /* Reset the timesync system time value. */
8879 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8880 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8882 i40e_start_timecounters(dev);
8884 /* Clear timesync registers. */
8885 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8886 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8887 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8888 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8889 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8890 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8892 /* Enable timestamping of PTP packets. */
8893 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8894 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8896 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8897 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8898 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8900 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8901 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8907 i40e_timesync_disable(struct rte_eth_dev *dev)
8909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8910 uint32_t tsync_ctl_l;
8911 uint32_t tsync_ctl_h;
8913 /* Disable timestamping of transmitted PTP packets. */
8914 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8915 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8917 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8918 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8920 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8921 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8923 /* Reset the timesync increment value. */
8924 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8925 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8931 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8932 struct timespec *timestamp, uint32_t flags)
8934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8935 struct i40e_adapter *adapter =
8936 (struct i40e_adapter *)dev->data->dev_private;
8938 uint32_t sync_status;
8939 uint32_t index = flags & 0x03;
8940 uint64_t rx_tstamp_cycles;
8943 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8944 if ((sync_status & (1 << index)) == 0)
8947 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8948 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8949 *timestamp = rte_ns_to_timespec(ns);
8955 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8956 struct timespec *timestamp)
8958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8959 struct i40e_adapter *adapter =
8960 (struct i40e_adapter *)dev->data->dev_private;
8962 uint32_t sync_status;
8963 uint64_t tx_tstamp_cycles;
8966 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8967 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8970 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8971 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8972 *timestamp = rte_ns_to_timespec(ns);
8978 * i40e_parse_dcb_configure - parse dcb configure from user
8979 * @dev: the device being configured
8980 * @dcb_cfg: pointer of the result of parse
8981 * @*tc_map: bit map of enabled traffic classes
8983 * Returns 0 on success, negative value on failure
8986 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8987 struct i40e_dcbx_config *dcb_cfg,
8990 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8991 uint8_t i, tc_bw, bw_lf;
8993 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8995 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8996 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8997 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9001 /* assume each tc has the same bw */
9002 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9003 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9004 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9005 /* to ensure the sum of tcbw is equal to 100 */
9006 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9007 for (i = 0; i < bw_lf; i++)
9008 dcb_cfg->etscfg.tcbwtable[i]++;
9010 /* assume each tc has the same Transmission Selection Algorithm */
9011 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9012 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9014 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9015 dcb_cfg->etscfg.prioritytable[i] =
9016 dcb_rx_conf->dcb_tc[i];
9018 /* FW needs one App to configure HW */
9019 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9020 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9021 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9022 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9024 if (dcb_rx_conf->nb_tcs == 0)
9025 *tc_map = 1; /* tc0 only */
9027 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9029 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9030 dcb_cfg->pfc.willing = 0;
9031 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9032 dcb_cfg->pfc.pfcenable = *tc_map;
9038 static enum i40e_status_code
9039 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9040 struct i40e_aqc_vsi_properties_data *info,
9041 uint8_t enabled_tcmap)
9043 enum i40e_status_code ret;
9044 int i, total_tc = 0;
9045 uint16_t qpnum_per_tc, bsf, qp_idx;
9046 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9047 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9048 uint16_t used_queues;
9050 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9051 if (ret != I40E_SUCCESS)
9054 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9055 if (enabled_tcmap & (1 << i))
9060 vsi->enabled_tc = enabled_tcmap;
9062 /* different VSI has different queues assigned */
9063 if (vsi->type == I40E_VSI_MAIN)
9064 used_queues = dev_data->nb_rx_queues -
9065 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9066 else if (vsi->type == I40E_VSI_VMDQ2)
9067 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9069 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9070 return I40E_ERR_NO_AVAILABLE_VSI;
9073 qpnum_per_tc = used_queues / total_tc;
9074 /* Number of queues per enabled TC */
9075 if (qpnum_per_tc == 0) {
9076 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9077 return I40E_ERR_INVALID_QP_ID;
9079 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9081 bsf = rte_bsf32(qpnum_per_tc);
9084 * Configure TC and queue mapping parameters, for enabled TC,
9085 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9086 * default queue will serve it.
9089 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9090 if (vsi->enabled_tc & (1 << i)) {
9091 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9092 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9093 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9094 qp_idx += qpnum_per_tc;
9096 info->tc_mapping[i] = 0;
9099 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9100 if (vsi->type == I40E_VSI_SRIOV) {
9101 info->mapping_flags |=
9102 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9103 for (i = 0; i < vsi->nb_qps; i++)
9104 info->queue_mapping[i] =
9105 rte_cpu_to_le_16(vsi->base_queue + i);
9107 info->mapping_flags |=
9108 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9109 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9111 info->valid_sections |=
9112 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9114 return I40E_SUCCESS;
9118 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9119 * @veb: VEB to be configured
9120 * @tc_map: enabled TC bitmap
9122 * Returns 0 on success, negative value on failure
9124 static enum i40e_status_code
9125 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9127 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9128 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9129 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9130 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9131 enum i40e_status_code ret = I40E_SUCCESS;
9135 /* Check if enabled_tc is same as existing or new TCs */
9136 if (veb->enabled_tc == tc_map)
9139 /* configure tc bandwidth */
9140 memset(&veb_bw, 0, sizeof(veb_bw));
9141 veb_bw.tc_valid_bits = tc_map;
9142 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9143 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9144 if (tc_map & BIT_ULL(i))
9145 veb_bw.tc_bw_share_credits[i] = 1;
9147 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9150 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9151 " per TC failed = %d",
9152 hw->aq.asq_last_status);
9156 memset(&ets_query, 0, sizeof(ets_query));
9157 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9159 if (ret != I40E_SUCCESS) {
9160 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9161 " configuration %u", hw->aq.asq_last_status);
9164 memset(&bw_query, 0, sizeof(bw_query));
9165 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9167 if (ret != I40E_SUCCESS) {
9168 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9169 " configuration %u", hw->aq.asq_last_status);
9173 /* store and print out BW info */
9174 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9175 veb->bw_info.bw_max = ets_query.tc_bw_max;
9176 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9177 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9178 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9179 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9181 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9182 veb->bw_info.bw_ets_share_credits[i] =
9183 bw_query.tc_bw_share_credits[i];
9184 veb->bw_info.bw_ets_credits[i] =
9185 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9186 /* 4 bits per TC, 4th bit is reserved */
9187 veb->bw_info.bw_ets_max[i] =
9188 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9189 RTE_LEN2MASK(3, uint8_t));
9190 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9191 veb->bw_info.bw_ets_share_credits[i]);
9192 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9193 veb->bw_info.bw_ets_credits[i]);
9194 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9195 veb->bw_info.bw_ets_max[i]);
9198 veb->enabled_tc = tc_map;
9205 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9206 * @vsi: VSI to be configured
9207 * @tc_map: enabled TC bitmap
9209 * Returns 0 on success, negative value on failure
9211 static enum i40e_status_code
9212 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9214 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9215 struct i40e_vsi_context ctxt;
9216 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9217 enum i40e_status_code ret = I40E_SUCCESS;
9220 /* Check if enabled_tc is same as existing or new TCs */
9221 if (vsi->enabled_tc == tc_map)
9224 /* configure tc bandwidth */
9225 memset(&bw_data, 0, sizeof(bw_data));
9226 bw_data.tc_valid_bits = tc_map;
9227 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9228 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9229 if (tc_map & BIT_ULL(i))
9230 bw_data.tc_bw_credits[i] = 1;
9232 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9234 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9235 " per TC failed = %d",
9236 hw->aq.asq_last_status);
9239 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9240 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9242 /* Update Queue Pairs Mapping for currently enabled UPs */
9243 ctxt.seid = vsi->seid;
9244 ctxt.pf_num = hw->pf_id;
9246 ctxt.uplink_seid = vsi->uplink_seid;
9247 ctxt.info = vsi->info;
9249 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9253 /* Update the VSI after updating the VSI queue-mapping information */
9254 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9256 PMD_INIT_LOG(ERR, "Failed to configure "
9257 "TC queue mapping = %d",
9258 hw->aq.asq_last_status);
9261 /* update the local VSI info with updated queue map */
9262 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9263 sizeof(vsi->info.tc_mapping));
9264 (void)rte_memcpy(&vsi->info.queue_mapping,
9265 &ctxt.info.queue_mapping,
9266 sizeof(vsi->info.queue_mapping));
9267 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9268 vsi->info.valid_sections = 0;
9270 /* query and update current VSI BW information */
9271 ret = i40e_vsi_get_bw_config(vsi);
9274 "Failed updating vsi bw info, err %s aq_err %s",
9275 i40e_stat_str(hw, ret),
9276 i40e_aq_str(hw, hw->aq.asq_last_status));
9280 vsi->enabled_tc = tc_map;
9287 * i40e_dcb_hw_configure - program the dcb setting to hw
9288 * @pf: pf the configuration is taken on
9289 * @new_cfg: new configuration
9290 * @tc_map: enabled TC bitmap
9292 * Returns 0 on success, negative value on failure
9294 static enum i40e_status_code
9295 i40e_dcb_hw_configure(struct i40e_pf *pf,
9296 struct i40e_dcbx_config *new_cfg,
9299 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9300 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9301 struct i40e_vsi *main_vsi = pf->main_vsi;
9302 struct i40e_vsi_list *vsi_list;
9303 enum i40e_status_code ret;
9307 /* Use the FW API if FW > v4.4*/
9308 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9309 (hw->aq.fw_maj_ver >= 5))) {
9310 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9311 " to configure DCB");
9312 return I40E_ERR_FIRMWARE_API_VERSION;
9315 /* Check if need reconfiguration */
9316 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9317 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9318 return I40E_SUCCESS;
9321 /* Copy the new config to the current config */
9322 *old_cfg = *new_cfg;
9323 old_cfg->etsrec = old_cfg->etscfg;
9324 ret = i40e_set_dcb_config(hw);
9327 "Set DCB Config failed, err %s aq_err %s\n",
9328 i40e_stat_str(hw, ret),
9329 i40e_aq_str(hw, hw->aq.asq_last_status));
9332 /* set receive Arbiter to RR mode and ETS scheme by default */
9333 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9334 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9335 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9336 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9337 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9338 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9339 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9340 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9341 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9342 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9343 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9344 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9345 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9347 /* get local mib to check whether it is configured correctly */
9349 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9350 /* Get Local DCB Config */
9351 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9352 &hw->local_dcbx_config);
9354 /* if Veb is created, need to update TC of it at first */
9355 if (main_vsi->veb) {
9356 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9358 PMD_INIT_LOG(WARNING,
9359 "Failed configuring TC for VEB seid=%d\n",
9360 main_vsi->veb->seid);
9362 /* Update each VSI */
9363 i40e_vsi_config_tc(main_vsi, tc_map);
9364 if (main_vsi->veb) {
9365 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9366 /* Beside main VSI and VMDQ VSIs, only enable default
9369 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9370 ret = i40e_vsi_config_tc(vsi_list->vsi,
9373 ret = i40e_vsi_config_tc(vsi_list->vsi,
9374 I40E_DEFAULT_TCMAP);
9376 PMD_INIT_LOG(WARNING,
9377 "Failed configuring TC for VSI seid=%d\n",
9378 vsi_list->vsi->seid);
9382 return I40E_SUCCESS;
9386 * i40e_dcb_init_configure - initial dcb config
9387 * @dev: device being configured
9388 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9390 * Returns 0 on success, negative value on failure
9393 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9395 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9396 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9399 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9400 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9404 /* DCB initialization:
9405 * Update DCB configuration from the Firmware and configure
9406 * LLDP MIB change event.
9408 if (sw_dcb == TRUE) {
9409 ret = i40e_init_dcb(hw);
9410 /* If lldp agent is stopped, the return value from
9411 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9412 * adminq status. Otherwise, it should return success.
9414 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9415 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9416 memset(&hw->local_dcbx_config, 0,
9417 sizeof(struct i40e_dcbx_config));
9418 /* set dcb default configuration */
9419 hw->local_dcbx_config.etscfg.willing = 0;
9420 hw->local_dcbx_config.etscfg.maxtcs = 0;
9421 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9422 hw->local_dcbx_config.etscfg.tsatable[0] =
9424 hw->local_dcbx_config.etsrec =
9425 hw->local_dcbx_config.etscfg;
9426 hw->local_dcbx_config.pfc.willing = 0;
9427 hw->local_dcbx_config.pfc.pfccap =
9428 I40E_MAX_TRAFFIC_CLASS;
9429 /* FW needs one App to configure HW */
9430 hw->local_dcbx_config.numapps = 1;
9431 hw->local_dcbx_config.app[0].selector =
9432 I40E_APP_SEL_ETHTYPE;
9433 hw->local_dcbx_config.app[0].priority = 3;
9434 hw->local_dcbx_config.app[0].protocolid =
9435 I40E_APP_PROTOID_FCOE;
9436 ret = i40e_set_dcb_config(hw);
9438 PMD_INIT_LOG(ERR, "default dcb config fails."
9439 " err = %d, aq_err = %d.", ret,
9440 hw->aq.asq_last_status);
9444 PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9445 " err = %d, aq_err = %d.", ret,
9446 hw->aq.asq_last_status);
9450 ret = i40e_aq_start_lldp(hw, NULL);
9451 if (ret != I40E_SUCCESS)
9452 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9454 ret = i40e_init_dcb(hw);
9456 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9457 PMD_INIT_LOG(ERR, "HW doesn't support"
9462 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9463 " aq_err = %d.", ret,
9464 hw->aq.asq_last_status);
9472 * i40e_dcb_setup - setup dcb related config
9473 * @dev: device being configured
9475 * Returns 0 on success, negative value on failure
9478 i40e_dcb_setup(struct rte_eth_dev *dev)
9480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9481 struct i40e_dcbx_config dcb_cfg;
9485 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9486 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9490 if (pf->vf_num != 0)
9491 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9493 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9495 PMD_INIT_LOG(ERR, "invalid dcb config");
9498 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9500 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9508 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9509 struct rte_eth_dcb_info *dcb_info)
9511 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9512 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9513 struct i40e_vsi *vsi = pf->main_vsi;
9514 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9515 uint16_t bsf, tc_mapping;
9518 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9519 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9521 dcb_info->nb_tcs = 1;
9522 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9523 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9524 for (i = 0; i < dcb_info->nb_tcs; i++)
9525 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9527 /* get queue mapping if vmdq is disabled */
9528 if (!pf->nb_cfg_vmdq_vsi) {
9529 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9530 if (!(vsi->enabled_tc & (1 << i)))
9532 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9533 dcb_info->tc_queue.tc_rxq[j][i].base =
9534 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9535 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9536 dcb_info->tc_queue.tc_txq[j][i].base =
9537 dcb_info->tc_queue.tc_rxq[j][i].base;
9538 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9539 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9540 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9541 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9542 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9547 /* get queue mapping if vmdq is enabled */
9549 vsi = pf->vmdq[j].vsi;
9550 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9551 if (!(vsi->enabled_tc & (1 << i)))
9553 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9554 dcb_info->tc_queue.tc_rxq[j][i].base =
9555 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9556 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9557 dcb_info->tc_queue.tc_txq[j][i].base =
9558 dcb_info->tc_queue.tc_rxq[j][i].base;
9559 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9560 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9561 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9562 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9563 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9566 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9571 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9573 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9574 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9575 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9577 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9580 msix_intr = intr_handle->intr_vec[queue_id];
9581 if (msix_intr == I40E_MISC_VEC_ID)
9582 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9583 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9584 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9585 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9587 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9590 I40E_PFINT_DYN_CTLN(msix_intr -
9592 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9593 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9594 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9596 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9598 I40E_WRITE_FLUSH(hw);
9599 rte_intr_enable(&pci_dev->intr_handle);
9605 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9607 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9608 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9609 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9612 msix_intr = intr_handle->intr_vec[queue_id];
9613 if (msix_intr == I40E_MISC_VEC_ID)
9614 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9617 I40E_PFINT_DYN_CTLN(msix_intr -
9620 I40E_WRITE_FLUSH(hw);
9625 static int i40e_get_regs(struct rte_eth_dev *dev,
9626 struct rte_dev_reg_info *regs)
9628 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9629 uint32_t *ptr_data = regs->data;
9630 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9631 const struct i40e_reg_info *reg_info;
9633 if (ptr_data == NULL) {
9634 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9635 regs->width = sizeof(uint32_t);
9639 /* The first few registers have to be read using AQ operations */
9641 while (i40e_regs_adminq[reg_idx].name) {
9642 reg_info = &i40e_regs_adminq[reg_idx++];
9643 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9645 arr_idx2 <= reg_info->count2;
9647 reg_offset = arr_idx * reg_info->stride1 +
9648 arr_idx2 * reg_info->stride2;
9649 reg_offset += reg_info->base_addr;
9650 ptr_data[reg_offset >> 2] =
9651 i40e_read_rx_ctl(hw, reg_offset);
9655 /* The remaining registers can be read using primitives */
9657 while (i40e_regs_others[reg_idx].name) {
9658 reg_info = &i40e_regs_others[reg_idx++];
9659 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9661 arr_idx2 <= reg_info->count2;
9663 reg_offset = arr_idx * reg_info->stride1 +
9664 arr_idx2 * reg_info->stride2;
9665 reg_offset += reg_info->base_addr;
9666 ptr_data[reg_offset >> 2] =
9667 I40E_READ_REG(hw, reg_offset);
9674 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9676 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9678 /* Convert word count to byte count */
9679 return hw->nvm.sr_size << 1;
9682 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9683 struct rte_dev_eeprom_info *eeprom)
9685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9686 uint16_t *data = eeprom->data;
9687 uint16_t offset, length, cnt_words;
9690 offset = eeprom->offset >> 1;
9691 length = eeprom->length >> 1;
9694 if (offset > hw->nvm.sr_size ||
9695 offset + length > hw->nvm.sr_size) {
9696 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9700 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9702 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9703 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9704 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9711 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9712 struct ether_addr *mac_addr)
9714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9716 if (!is_valid_assigned_ether_addr(mac_addr)) {
9717 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9721 /* Flags: 0x3 updates port address */
9722 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9726 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9729 struct rte_eth_dev_data *dev_data = pf->dev_data;
9730 uint32_t frame_size = mtu + ETHER_HDR_LEN
9731 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9734 /* check if mtu is within the allowed range */
9735 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9738 /* mtu setting is forbidden if port is start */
9739 if (dev_data->dev_started) {
9741 "port %d must be stopped before configuration\n",
9746 if (frame_size > ETHER_MAX_LEN)
9747 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9749 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9751 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;