drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline int
 631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 632                                      struct rte_eth_link *link)
 633 {
 634         struct rte_eth_link *dst = link;
 635         struct rte_eth_link *src = &(dev->data->dev_link);
 636
 637         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 638                                         *(uint64_t *)src) == 0)
 639                 return -1;
 640
 641         return 0;
 642 }
 643
 644 static inline int
 645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 646                                       struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = &(dev->data->dev_link);
 649         struct rte_eth_link *src = link;
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 659 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 660 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 661
 662 #ifndef I40E_GLQF_ORT
 663 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 664 #endif
 665 #ifndef I40E_GLQF_PIT
 666 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 667 #endif
 668 #ifndef I40E_GLQF_L3_MAP
 669 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 670 #endif
 671
 672 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 673 {
 674         /*
 675          * Force global configuration for flexible payload
 676          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 677          * This should be removed from code once proper
 678          * configuration API is added to avoid configuration conflicts
 679          * between ports of the same device.
 680          */
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 682         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 683         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 684
 685         /*
 686          * Initialize registers for parsing packet type of QinQ
 687          * This should be removed from code once proper
 688          * configuration API is added to avoid configuration conflicts
 689          * between ports of the same device.
 690          */
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 692         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 693 }
 694
 695 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 696
 697 /*
 698  * Add a ethertype filter to drop all flow control frames transmitted
 699  * from VSIs.
 700 */
 701 static void
 702 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 703 {
 704         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 705         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 706                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 707                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 708         int ret;
 709
 710         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 711                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 712                                 pf->main_vsi_seid, 0,
 713                                 TRUE, NULL, NULL);
 714         if (ret)
 715                 PMD_INIT_LOG(ERR,
 716                         "Failed to add filter to drop flow control frames from VSIs.");
 717 }
 718
 719 static int
 720 floating_veb_list_handler(__rte_unused const char *key,
 721                           const char *floating_veb_value,
 722                           void *opaque)
 723 {
 724         int idx = 0;
 725         unsigned int count = 0;
 726         char *end = NULL;
 727         int min, max;
 728         bool *vf_floating_veb = opaque;
 729
 730         while (isblank(*floating_veb_value))
 731                 floating_veb_value++;
 732
 733         /* Reset floating VEB configuration for VFs */
 734         for (idx = 0; idx < I40E_MAX_VF; idx++)
 735                 vf_floating_veb[idx] = false;
 736
 737         min = I40E_MAX_VF;
 738         do {
 739                 while (isblank(*floating_veb_value))
 740                         floating_veb_value++;
 741                 if (*floating_veb_value == '\0')
 742                         return -1;
 743                 errno = 0;
 744                 idx = strtoul(floating_veb_value, &end, 10);
 745                 if (errno || end == NULL)
 746                         return -1;
 747                 while (isblank(*end))
 748                         end++;
 749                 if (*end == '-') {
 750                         min = idx;
 751                 } else if ((*end == ';') || (*end == '\0')) {
 752                         max = idx;
 753                         if (min == I40E_MAX_VF)
 754                                 min = idx;
 755                         if (max >= I40E_MAX_VF)
 756                                 max = I40E_MAX_VF - 1;
 757                         for (idx = min; idx <= max; idx++) {
 758                                 vf_floating_veb[idx] = true;
 759                                 count++;
 760                         }
 761                         min = I40E_MAX_VF;
 762                 } else {
 763                         return -1;
 764                 }
 765                 floating_veb_value = end + 1;
 766         } while (*end != '\0');
 767
 768         if (count == 0)
 769                 return -1;
 770
 771         return 0;
 772 }
 773
 774 static void
 775 config_vf_floating_veb(struct rte_devargs *devargs,
 776                        uint16_t floating_veb,
 777                        bool *vf_floating_veb)
 778 {
 779         struct rte_kvargs *kvlist;
 780         int i;
 781         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 782
 783         if (!floating_veb)
 784                 return;
 785         /* All the VFs attach to the floating VEB by default
 786          * when the floating VEB is enabled.
 787          */
 788         for (i = 0; i < I40E_MAX_VF; i++)
 789                 vf_floating_veb[i] = true;
 790
 791         if (devargs == NULL)
 792                 return;
 793
 794         kvlist = rte_kvargs_parse(devargs->args, NULL);
 795         if (kvlist == NULL)
 796                 return;
 797
 798         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 799                 rte_kvargs_free(kvlist);
 800                 return;
 801         }
 802         /* When the floating_veb_list parameter exists, all the VFs
 803          * will attach to the legacy VEB firstly, then configure VFs
 804          * to the floating VEB according to the floating_veb_list.
 805          */
 806         if (rte_kvargs_process(kvlist, floating_veb_list,
 807                                floating_veb_list_handler,
 808                                vf_floating_veb) < 0) {
 809                 rte_kvargs_free(kvlist);
 810                 return;
 811         }
 812         rte_kvargs_free(kvlist);
 813 }
 814
 815 static int
 816 i40e_check_floating_handler(__rte_unused const char *key,
 817                             const char *value,
 818                             __rte_unused void *opaque)
 819 {
 820         if (strcmp(value, "1"))
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static int
 827 is_floating_veb_supported(struct rte_devargs *devargs)
 828 {
 829         struct rte_kvargs *kvlist;
 830         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 831
 832         if (devargs == NULL)
 833                 return 0;
 834
 835         kvlist = rte_kvargs_parse(devargs->args, NULL);
 836         if (kvlist == NULL)
 837                 return 0;
 838
 839         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 840                 rte_kvargs_free(kvlist);
 841                 return 0;
 842         }
 843         /* Floating VEB is enabled when there's key-value:
 844          * enable_floating_veb=1
 845          */
 846         if (rte_kvargs_process(kvlist, floating_veb_key,
 847                                i40e_check_floating_handler, NULL) < 0) {
 848                 rte_kvargs_free(kvlist);
 849                 return 0;
 850         }
 851         rte_kvargs_free(kvlist);
 852
 853         return 1;
 854 }
 855
 856 static void
 857 config_floating_veb(struct rte_eth_dev *dev)
 858 {
 859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 862
 863         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 864
 865         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 866                 pf->floating_veb =
 867                         is_floating_veb_supported(pci_dev->device.devargs);
 868                 config_vf_floating_veb(pci_dev->device.devargs,
 869                                        pf->floating_veb,
 870                                        pf->floating_veb_list);
 871         } else {
 872                 pf->floating_veb = false;
 873         }
 874 }
 875
 876 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 877 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 878
 879 static int
 880 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 881 {
 882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 883         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 884         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 885         int ret;
 886
 887         struct rte_hash_parameters ethertype_hash_params = {
 888                 .name = ethertype_hash_name,
 889                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 890                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 891                 .hash_func = rte_hash_crc,
 892                 .hash_func_init_val = 0,
 893                 .socket_id = rte_socket_id(),
 894         };
 895
 896         /* Initialize ethertype filter rule list and hash */
 897         TAILQ_INIT(&ethertype_rule->ethertype_list);
 898         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 899                  "ethertype_%s", dev->device->name);
 900         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 901         if (!ethertype_rule->hash_table) {
 902                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 903                 return -EINVAL;
 904         }
 905         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 906                                        sizeof(struct i40e_ethertype_filter *) *
 907                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 908                                        0);
 909         if (!ethertype_rule->hash_map) {
 910                 PMD_INIT_LOG(ERR,
 911                              "Failed to allocate memory for ethertype hash map!");
 912                 ret = -ENOMEM;
 913                 goto err_ethertype_hash_map_alloc;
 914         }
 915
 916         return 0;
 917
 918 err_ethertype_hash_map_alloc:
 919         rte_hash_free(ethertype_rule->hash_table);
 920
 921         return ret;
 922 }
 923
 924 static int
 925 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 926 {
 927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 928         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 929         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 930         int ret;
 931
 932         struct rte_hash_parameters tunnel_hash_params = {
 933                 .name = tunnel_hash_name,
 934                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 935                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 936                 .hash_func = rte_hash_crc,
 937                 .hash_func_init_val = 0,
 938                 .socket_id = rte_socket_id(),
 939         };
 940
 941         /* Initialize tunnel filter rule list and hash */
 942         TAILQ_INIT(&tunnel_rule->tunnel_list);
 943         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 944                  "tunnel_%s", dev->device->name);
 945         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 946         if (!tunnel_rule->hash_table) {
 947                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 948                 return -EINVAL;
 949         }
 950         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 951                                     sizeof(struct i40e_tunnel_filter *) *
 952                                     I40E_MAX_TUNNEL_FILTER_NUM,
 953                                     0);
 954         if (!tunnel_rule->hash_map) {
 955                 PMD_INIT_LOG(ERR,
 956                              "Failed to allocate memory for tunnel hash map!");
 957                 ret = -ENOMEM;
 958                 goto err_tunnel_hash_map_alloc;
 959         }
 960
 961         return 0;
 962
 963 err_tunnel_hash_map_alloc:
 964         rte_hash_free(tunnel_rule->hash_table);
 965
 966         return ret;
 967 }
 968
 969 static int
 970 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 971 {
 972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 973         struct i40e_fdir_info *fdir_info = &pf->fdir;
 974         char fdir_hash_name[RTE_HASH_NAMESIZE];
 975         int ret;
 976
 977         struct rte_hash_parameters fdir_hash_params = {
 978                 .name = fdir_hash_name,
 979                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 980                 .key_len = sizeof(struct i40e_fdir_input),
 981                 .hash_func = rte_hash_crc,
 982                 .hash_func_init_val = 0,
 983                 .socket_id = rte_socket_id(),
 984         };
 985
 986         /* Initialize flow director filter rule list and hash */
 987         TAILQ_INIT(&fdir_info->fdir_list);
 988         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 989                  "fdir_%s", dev->device->name);
 990         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 991         if (!fdir_info->hash_table) {
 992                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 993                 return -EINVAL;
 994         }
 995         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 996                                           sizeof(struct i40e_fdir_filter *) *
 997                                           I40E_MAX_FDIR_FILTER_NUM,
 998                                           0);
 999         if (!fdir_info->hash_map) {
1000                 PMD_INIT_LOG(ERR,
1001                              "Failed to allocate memory for fdir hash map!");
1002                 ret = -ENOMEM;
1003                 goto err_fdir_hash_map_alloc;
1004         }
1005         return 0;
1006
1007 err_fdir_hash_map_alloc:
1008         rte_hash_free(fdir_info->hash_table);
1009
1010         return ret;
1011 }
1012
1013 static void
1014 i40e_init_customized_info(struct i40e_pf *pf)
1015 {
1016         int i;
1017
1018         /* Initialize customized pctype */
1019         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1020                 pf->customized_pctype[i].index = i;
1021                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1022                 pf->customized_pctype[i].valid = false;
1023         }
1024
1025         pf->gtp_support = false;
1026 }
1027
1028 void
1029 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1030 {
1031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033         struct i40e_queue_regions *info = &pf->queue_region;
1034         uint16_t i;
1035
1036         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1037                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1038
1039         memset(info, 0, sizeof(struct i40e_queue_regions));
1040 }
1041
1042 static int
1043 eth_i40e_dev_init(struct rte_eth_dev *dev)
1044 {
1045         struct rte_pci_device *pci_dev;
1046         struct rte_intr_handle *intr_handle;
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         struct i40e_vsi *vsi;
1050         int ret;
1051         uint32_t len;
1052         uint8_t aq_fail = 0;
1053
1054         PMD_INIT_FUNC_TRACE();
1055
1056         dev->dev_ops = &i40e_eth_dev_ops;
1057         dev->rx_pkt_burst = i40e_recv_pkts;
1058         dev->tx_pkt_burst = i40e_xmit_pkts;
1059         dev->tx_pkt_prepare = i40e_prep_pkts;
1060
1061         /* for secondary processes, we don't initialise any further as primary
1062          * has already done this work. Only check we don't need a different
1063          * RX function */
1064         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1065                 i40e_set_rx_function(dev);
1066                 i40e_set_tx_function(dev);
1067                 return 0;
1068         }
1069         i40e_set_default_ptype_table(dev);
1070         i40e_set_default_pctype_table(dev);
1071         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1072         intr_handle = &pci_dev->intr_handle;
1073
1074         rte_eth_copy_pci_info(dev, pci_dev);
1075
1076         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1077         pf->adapter->eth_dev = dev;
1078         pf->dev_data = dev->data;
1079
1080         hw->back = I40E_PF_TO_ADAPTER(pf);
1081         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1082         if (!hw->hw_addr) {
1083                 PMD_INIT_LOG(ERR,
1084                         "Hardware is not available, as address is NULL");
1085                 return -ENODEV;
1086         }
1087
1088         hw->vendor_id = pci_dev->id.vendor_id;
1089         hw->device_id = pci_dev->id.device_id;
1090         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1091         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1092         hw->bus.device = pci_dev->addr.devid;
1093         hw->bus.func = pci_dev->addr.function;
1094         hw->adapter_stopped = 0;
1095
1096         /* Make sure all is clean before doing PF reset */
1097         i40e_clear_hw(hw);
1098
1099         /* Initialize the hardware */
1100         i40e_hw_init(dev);
1101
1102         /* Reset here to make sure all is clean for each PF */
1103         ret = i40e_pf_reset(hw);
1104         if (ret) {
1105                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1106                 return ret;
1107         }
1108
1109         /* Initialize the shared code (base driver) */
1110         ret = i40e_init_shared_code(hw);
1111         if (ret) {
1112                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1113                 return ret;
1114         }
1115
1116         /*
1117          * To work around the NVM issue, initialize registers
1118          * for flexible payload and packet type of QinQ by
1119          * software. It should be removed once issues are fixed
1120          * in NVM.
1121          */
1122         i40e_GLQF_reg_init(hw);
1123
1124         /* Initialize the input set for filters (hash and fd) to default value */
1125         i40e_filter_input_set_init(pf);
1126
1127         /* Initialize the parameters for adminq */
1128         i40e_init_adminq_parameter(hw);
1129         ret = i40e_init_adminq(hw);
1130         if (ret != I40E_SUCCESS) {
1131                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1132                 return -EIO;
1133         }
1134         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1135                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1136                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1137                      ((hw->nvm.version >> 12) & 0xf),
1138                      ((hw->nvm.version >> 4) & 0xff),
1139                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1140
1141         /* initialise the L3_MAP register */
1142         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1143                                    0x00000028,  NULL);
1144         if (ret)
1145                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1146
1147         /* Need the special FW version to support floating VEB */
1148         config_floating_veb(dev);
1149         /* Clear PXE mode */
1150         i40e_clear_pxe_mode(hw);
1151         i40e_dev_sync_phy_type(hw);
1152
1153         /*
1154          * On X710, performance number is far from the expectation on recent
1155          * firmware versions. The fix for this issue may not be integrated in
1156          * the following firmware version. So the workaround in software driver
1157          * is needed. It needs to modify the initial values of 3 internal only
1158          * registers. Note that the workaround can be removed when it is fixed
1159          * in firmware in the future.
1160          */
1161         i40e_configure_registers(hw);
1162
1163         /* Get hw capabilities */
1164         ret = i40e_get_cap(hw);
1165         if (ret != I40E_SUCCESS) {
1166                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1167                 goto err_get_capabilities;
1168         }
1169
1170         /* Initialize parameters for PF */
1171         ret = i40e_pf_parameter_init(dev);
1172         if (ret != 0) {
1173                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1174                 goto err_parameter_init;
1175         }
1176
1177         /* Initialize the queue management */
1178         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1179         if (ret < 0) {
1180                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1181                 goto err_qp_pool_init;
1182         }
1183         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1184                                 hw->func_caps.num_msix_vectors - 1);
1185         if (ret < 0) {
1186                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1187                 goto err_msix_pool_init;
1188         }
1189
1190         /* Initialize lan hmc */
1191         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1192                                 hw->func_caps.num_rx_qp, 0, 0);
1193         if (ret != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1195                 goto err_init_lan_hmc;
1196         }
1197
1198         /* Configure lan hmc */
1199         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1200         if (ret != I40E_SUCCESS) {
1201                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1202                 goto err_configure_lan_hmc;
1203         }
1204
1205         /* Get and check the mac address */
1206         i40e_get_mac_addr(hw, hw->mac.addr);
1207         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1208                 PMD_INIT_LOG(ERR, "mac address is not valid");
1209                 ret = -EIO;
1210                 goto err_get_mac_addr;
1211         }
1212         /* Copy the permanent MAC address */
1213         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1214                         (struct ether_addr *) hw->mac.perm_addr);
1215
1216         /* Disable flow control */
1217         hw->fc.requested_mode = I40E_FC_NONE;
1218         i40e_set_fc(hw, &aq_fail, TRUE);
1219
1220         /* Set the global registers with default ether type value */
1221         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1222         if (ret != I40E_SUCCESS) {
1223                 PMD_INIT_LOG(ERR,
1224                         "Failed to set the default outer VLAN ether type");
1225                 goto err_setup_pf_switch;
1226         }
1227
1228         /* PF setup, which includes VSI setup */
1229         ret = i40e_pf_setup(pf);
1230         if (ret) {
1231                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1232                 goto err_setup_pf_switch;
1233         }
1234
1235         /* reset all stats of the device, including pf and main vsi */
1236         i40e_dev_stats_reset(dev);
1237
1238         vsi = pf->main_vsi;
1239
1240         /* Disable double vlan by default */
1241         i40e_vsi_config_double_vlan(vsi, FALSE);
1242
1243         /* Disable S-TAG identification when floating_veb is disabled */
1244         if (!pf->floating_veb) {
1245                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1246                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1247                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1248                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249                 }
1250         }
1251
1252         if (!vsi->max_macaddrs)
1253                 len = ETHER_ADDR_LEN;
1254         else
1255                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1256
1257         /* Should be after VSI initialized */
1258         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1259         if (!dev->data->mac_addrs) {
1260                 PMD_INIT_LOG(ERR,
1261                         "Failed to allocated memory for storing mac address");
1262                 goto err_mac_alloc;
1263         }
1264         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1265                                         &dev->data->mac_addrs[0]);
1266
1267         /* Init dcb to sw mode by default */
1268         ret = i40e_dcb_init_configure(dev, TRUE);
1269         if (ret != I40E_SUCCESS) {
1270                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1271                 pf->flags &= ~I40E_FLAG_DCB;
1272         }
1273         /* Update HW struct after DCB configuration */
1274         i40e_get_cap(hw);
1275
1276         /* initialize pf host driver to setup SRIOV resource if applicable */
1277         i40e_pf_host_init(dev);
1278
1279         /* register callback func to eal lib */
1280         rte_intr_callback_register(intr_handle,
1281                                    i40e_dev_interrupt_handler, dev);
1282
1283         /* configure and enable device interrupt */
1284         i40e_pf_config_irq0(hw, TRUE);
1285         i40e_pf_enable_irq0(hw);
1286
1287         /* enable uio intr after callback register */
1288         rte_intr_enable(intr_handle);
1289         /*
1290          * Add an ethertype filter to drop all flow control frames transmitted
1291          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1292          * frames to wire.
1293          */
1294         i40e_add_tx_flow_control_drop_filter(pf);
1295
1296         /* Set the max frame size to 0x2600 by default,
1297          * in case other drivers changed the default value.
1298          */
1299         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1300
1301         /* initialize mirror rule list */
1302         TAILQ_INIT(&pf->mirror_list);
1303
1304         /* initialize Traffic Manager configuration */
1305         i40e_tm_conf_init(dev);
1306
1307         /* Initialize customized information */
1308         i40e_init_customized_info(pf);
1309
1310         ret = i40e_init_ethtype_filter_list(dev);
1311         if (ret < 0)
1312                 goto err_init_ethtype_filter_list;
1313         ret = i40e_init_tunnel_filter_list(dev);
1314         if (ret < 0)
1315                 goto err_init_tunnel_filter_list;
1316         ret = i40e_init_fdir_filter_list(dev);
1317         if (ret < 0)
1318                 goto err_init_fdir_filter_list;
1319
1320         /* initialize queue region configuration */
1321         i40e_init_queue_region_conf(dev);
1322
1323         return 0;
1324
1325 err_init_fdir_filter_list:
1326         rte_free(pf->tunnel.hash_table);
1327         rte_free(pf->tunnel.hash_map);
1328 err_init_tunnel_filter_list:
1329         rte_free(pf->ethertype.hash_table);
1330         rte_free(pf->ethertype.hash_map);
1331 err_init_ethtype_filter_list:
1332         rte_free(dev->data->mac_addrs);
1333 err_mac_alloc:
1334         i40e_vsi_release(pf->main_vsi);
1335 err_setup_pf_switch:
1336 err_get_mac_addr:
1337 err_configure_lan_hmc:
1338         (void)i40e_shutdown_lan_hmc(hw);
1339 err_init_lan_hmc:
1340         i40e_res_pool_destroy(&pf->msix_pool);
1341 err_msix_pool_init:
1342         i40e_res_pool_destroy(&pf->qp_pool);
1343 err_qp_pool_init:
1344 err_parameter_init:
1345 err_get_capabilities:
1346         (void)i40e_shutdown_adminq(hw);
1347
1348         return ret;
1349 }
1350
1351 static void
1352 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1353 {
1354         struct i40e_ethertype_filter *p_ethertype;
1355         struct i40e_ethertype_rule *ethertype_rule;
1356
1357         ethertype_rule = &pf->ethertype;
1358         /* Remove all ethertype filter rules and hash */
1359         if (ethertype_rule->hash_map)
1360                 rte_free(ethertype_rule->hash_map);
1361         if (ethertype_rule->hash_table)
1362                 rte_hash_free(ethertype_rule->hash_table);
1363
1364         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1365                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1366                              p_ethertype, rules);
1367                 rte_free(p_ethertype);
1368         }
1369 }
1370
1371 static void
1372 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1373 {
1374         struct i40e_tunnel_filter *p_tunnel;
1375         struct i40e_tunnel_rule *tunnel_rule;
1376
1377         tunnel_rule = &pf->tunnel;
1378         /* Remove all tunnel director rules and hash */
1379         if (tunnel_rule->hash_map)
1380                 rte_free(tunnel_rule->hash_map);
1381         if (tunnel_rule->hash_table)
1382                 rte_hash_free(tunnel_rule->hash_table);
1383
1384         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1385                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1386                 rte_free(p_tunnel);
1387         }
1388 }
1389
1390 static void
1391 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1392 {
1393         struct i40e_fdir_filter *p_fdir;
1394         struct i40e_fdir_info *fdir_info;
1395
1396         fdir_info = &pf->fdir;
1397         /* Remove all flow director rules and hash */
1398         if (fdir_info->hash_map)
1399                 rte_free(fdir_info->hash_map);
1400         if (fdir_info->hash_table)
1401                 rte_hash_free(fdir_info->hash_table);
1402
1403         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1404                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1405                 rte_free(p_fdir);
1406         }
1407 }
1408
1409 static int
1410 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1411 {
1412         struct i40e_pf *pf;
1413         struct rte_pci_device *pci_dev;
1414         struct rte_intr_handle *intr_handle;
1415         struct i40e_hw *hw;
1416         struct i40e_filter_control_settings settings;
1417         struct rte_flow *p_flow;
1418         int ret;
1419         uint8_t aq_fail = 0;
1420
1421         PMD_INIT_FUNC_TRACE();
1422
1423         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1424                 return 0;
1425
1426         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1429         intr_handle = &pci_dev->intr_handle;
1430
1431         if (hw->adapter_stopped == 0)
1432                 i40e_dev_close(dev);
1433
1434         dev->dev_ops = NULL;
1435         dev->rx_pkt_burst = NULL;
1436         dev->tx_pkt_burst = NULL;
1437
1438         /* Clear PXE mode */
1439         i40e_clear_pxe_mode(hw);
1440
1441         /* Unconfigure filter control */
1442         memset(&settings, 0, sizeof(settings));
1443         ret = i40e_set_filter_control(hw, &settings);
1444         if (ret)
1445                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1446                                         ret);
1447
1448         /* Disable flow control */
1449         hw->fc.requested_mode = I40E_FC_NONE;
1450         i40e_set_fc(hw, &aq_fail, TRUE);
1451
1452         /* uninitialize pf host driver */
1453         i40e_pf_host_uninit(dev);
1454
1455         rte_free(dev->data->mac_addrs);
1456         dev->data->mac_addrs = NULL;
1457
1458         /* disable uio intr before callback unregister */
1459         rte_intr_disable(intr_handle);
1460
1461         /* register callback func to eal lib */
1462         rte_intr_callback_unregister(intr_handle,
1463                                      i40e_dev_interrupt_handler, dev);
1464
1465         i40e_rm_ethtype_filter_list(pf);
1466         i40e_rm_tunnel_filter_list(pf);
1467         i40e_rm_fdir_filter_list(pf);
1468
1469         /* Remove all flows */
1470         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1471                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1472                 rte_free(p_flow);
1473         }
1474
1475         /* Remove all Traffic Manager configuration */
1476         i40e_tm_conf_uninit(dev);
1477
1478         return 0;
1479 }
1480
1481 static int
1482 i40e_dev_configure(struct rte_eth_dev *dev)
1483 {
1484         struct i40e_adapter *ad =
1485                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1489         int i, ret;
1490
1491         ret = i40e_dev_sync_phy_type(hw);
1492         if (ret)
1493                 return ret;
1494
1495         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1496          * bulk allocation or vector Rx preconditions we will reset it.
1497          */
1498         ad->rx_bulk_alloc_allowed = true;
1499         ad->rx_vec_allowed = true;
1500         ad->tx_simple_allowed = true;
1501         ad->tx_vec_allowed = true;
1502
1503         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1504                 ret = i40e_fdir_setup(pf);
1505                 if (ret != I40E_SUCCESS) {
1506                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1507                         return -ENOTSUP;
1508                 }
1509                 ret = i40e_fdir_configure(dev);
1510                 if (ret < 0) {
1511                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1512                         goto err;
1513                 }
1514         } else
1515                 i40e_fdir_teardown(pf);
1516
1517         ret = i40e_dev_init_vlan(dev);
1518         if (ret < 0)
1519                 goto err;
1520
1521         /* VMDQ setup.
1522          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1523          *  RSS setting have different requirements.
1524          *  General PMD driver call sequence are NIC init, configure,
1525          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1526          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1527          *  applicable. So, VMDQ setting has to be done before
1528          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1529          *  For RSS setting, it will try to calculate actual configured RX queue
1530          *  number, which will be available after rx_queue_setup(). dev_start()
1531          *  function is good to place RSS setup.
1532          */
1533         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1534                 ret = i40e_vmdq_setup(dev);
1535                 if (ret)
1536                         goto err;
1537         }
1538
1539         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1540                 ret = i40e_dcb_setup(dev);
1541                 if (ret) {
1542                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1543                         goto err_dcb;
1544                 }
1545         }
1546
1547         TAILQ_INIT(&pf->flow_list);
1548
1549         return 0;
1550
1551 err_dcb:
1552         /* need to release vmdq resource if exists */
1553         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1554                 i40e_vsi_release(pf->vmdq[i].vsi);
1555                 pf->vmdq[i].vsi = NULL;
1556         }
1557         rte_free(pf->vmdq);
1558         pf->vmdq = NULL;
1559 err:
1560         /* need to release fdir resource if exists */
1561         i40e_fdir_teardown(pf);
1562         return ret;
1563 }
1564
1565 void
1566 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1567 {
1568         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1569         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1570         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1571         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1572         uint16_t msix_vect = vsi->msix_intr;
1573         uint16_t i;
1574
1575         for (i = 0; i < vsi->nb_qps; i++) {
1576                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1577                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1578                 rte_wmb();
1579         }
1580
1581         if (vsi->type != I40E_VSI_SRIOV) {
1582                 if (!rte_intr_allow_others(intr_handle)) {
1583                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1584                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1585                         I40E_WRITE_REG(hw,
1586                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1587                                        0);
1588                 } else {
1589                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1590                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591                         I40E_WRITE_REG(hw,
1592                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1593                                                        msix_vect - 1), 0);
1594                 }
1595         } else {
1596                 uint32_t reg;
1597                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1598                         vsi->user_param + (msix_vect - 1);
1599
1600                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1601                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1602         }
1603         I40E_WRITE_FLUSH(hw);
1604 }
1605
1606 static void
1607 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1608                        int base_queue, int nb_queue,
1609                        uint16_t itr_idx)
1610 {
1611         int i;
1612         uint32_t val;
1613         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1614
1615         /* Bind all RX queues to allocated MSIX interrupt */
1616         for (i = 0; i < nb_queue; i++) {
1617                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1618                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1619                         ((base_queue + i + 1) <<
1620                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1621                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1622                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1623
1624                 if (i == nb_queue - 1)
1625                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1626                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1627         }
1628
1629         /* Write first RX queue to Link list register as the head element */
1630         if (vsi->type != I40E_VSI_SRIOV) {
1631                 uint16_t interval =
1632                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1633
1634                 if (msix_vect == I40E_MISC_VEC_ID) {
1635                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1636                                        (base_queue <<
1637                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1638                                        (0x0 <<
1639                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1640                         I40E_WRITE_REG(hw,
1641                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1642                                        interval);
1643                 } else {
1644                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1645                                        (base_queue <<
1646                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1647                                        (0x0 <<
1648                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1649                         I40E_WRITE_REG(hw,
1650                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1651                                                        msix_vect - 1),
1652                                        interval);
1653                 }
1654         } else {
1655                 uint32_t reg;
1656
1657                 if (msix_vect == I40E_MISC_VEC_ID) {
1658                         I40E_WRITE_REG(hw,
1659                                        I40E_VPINT_LNKLST0(vsi->user_param),
1660                                        (base_queue <<
1661                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1662                                        (0x0 <<
1663                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1664                 } else {
1665                         /* num_msix_vectors_vf needs to minus irq0 */
1666                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1667                                 vsi->user_param + (msix_vect - 1);
1668
1669                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1670                                        (base_queue <<
1671                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1672                                        (0x0 <<
1673                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1674                 }
1675         }
1676
1677         I40E_WRITE_FLUSH(hw);
1678 }
1679
1680 void
1681 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1682 {
1683         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1686         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1687         uint16_t msix_vect = vsi->msix_intr;
1688         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1689         uint16_t queue_idx = 0;
1690         int record = 0;
1691         uint32_t val;
1692         int i;
1693
1694         for (i = 0; i < vsi->nb_qps; i++) {
1695                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1696                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1697         }
1698
1699         /* INTENA flag is not auto-cleared for interrupt */
1700         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1701         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1702                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1703                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1704         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1705
1706         /* VF bind interrupt */
1707         if (vsi->type == I40E_VSI_SRIOV) {
1708                 __vsi_queues_bind_intr(vsi, msix_vect,
1709                                        vsi->base_queue, vsi->nb_qps,
1710                                        itr_idx);
1711                 return;
1712         }
1713
1714         /* PF & VMDq bind interrupt */
1715         if (rte_intr_dp_is_en(intr_handle)) {
1716                 if (vsi->type == I40E_VSI_MAIN) {
1717                         queue_idx = 0;
1718                         record = 1;
1719                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1720                         struct i40e_vsi *main_vsi =
1721                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1722                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1723                         record = 1;
1724                 }
1725         }
1726
1727         for (i = 0; i < vsi->nb_used_qps; i++) {
1728                 if (nb_msix <= 1) {
1729                         if (!rte_intr_allow_others(intr_handle))
1730                                 /* allow to share MISC_VEC_ID */
1731                                 msix_vect = I40E_MISC_VEC_ID;
1732
1733                         /* no enough msix_vect, map all to one */
1734                         __vsi_queues_bind_intr(vsi, msix_vect,
1735                                                vsi->base_queue + i,
1736                                                vsi->nb_used_qps - i,
1737                                                itr_idx);
1738                         for (; !!record && i < vsi->nb_used_qps; i++)
1739                                 intr_handle->intr_vec[queue_idx + i] =
1740                                         msix_vect;
1741                         break;
1742                 }
1743                 /* 1:1 queue/msix_vect mapping */
1744                 __vsi_queues_bind_intr(vsi, msix_vect,
1745                                        vsi->base_queue + i, 1,
1746                                        itr_idx);
1747                 if (!!record)
1748                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1749
1750                 msix_vect++;
1751                 nb_msix--;
1752         }
1753 }
1754
1755 static void
1756 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1757 {
1758         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1759         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1760         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1761         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1762         uint16_t interval = i40e_calc_itr_interval(\
1763                 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1764         uint16_t msix_intr, i;
1765
1766         if (rte_intr_allow_others(intr_handle))
1767                 for (i = 0; i < vsi->nb_msix; i++) {
1768                         msix_intr = vsi->msix_intr + i;
1769                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1770                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1771                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1772                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1773                                 (interval <<
1774                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1775                 }
1776         else
1777                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1778                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1779                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1780                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1781                                (interval <<
1782                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1783
1784         I40E_WRITE_FLUSH(hw);
1785 }
1786
1787 static void
1788 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1789 {
1790         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1791         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1792         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1793         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1794         uint16_t msix_intr, i;
1795
1796         if (rte_intr_allow_others(intr_handle))
1797                 for (i = 0; i < vsi->nb_msix; i++) {
1798                         msix_intr = vsi->msix_intr + i;
1799                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1800                                        0);
1801                 }
1802         else
1803                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1804
1805         I40E_WRITE_FLUSH(hw);
1806 }
1807
1808 static inline uint8_t
1809 i40e_parse_link_speeds(uint16_t link_speeds)
1810 {
1811         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1812
1813         if (link_speeds & ETH_LINK_SPEED_40G)
1814                 link_speed |= I40E_LINK_SPEED_40GB;
1815         if (link_speeds & ETH_LINK_SPEED_25G)
1816                 link_speed |= I40E_LINK_SPEED_25GB;
1817         if (link_speeds & ETH_LINK_SPEED_20G)
1818                 link_speed |= I40E_LINK_SPEED_20GB;
1819         if (link_speeds & ETH_LINK_SPEED_10G)
1820                 link_speed |= I40E_LINK_SPEED_10GB;
1821         if (link_speeds & ETH_LINK_SPEED_1G)
1822                 link_speed |= I40E_LINK_SPEED_1GB;
1823         if (link_speeds & ETH_LINK_SPEED_100M)
1824                 link_speed |= I40E_LINK_SPEED_100MB;
1825
1826         return link_speed;
1827 }
1828
1829 static int
1830 i40e_phy_conf_link(struct i40e_hw *hw,
1831                    uint8_t abilities,
1832                    uint8_t force_speed,
1833                    bool is_up)
1834 {
1835         enum i40e_status_code status;
1836         struct i40e_aq_get_phy_abilities_resp phy_ab;
1837         struct i40e_aq_set_phy_config phy_conf;
1838         enum i40e_aq_phy_type cnt;
1839         uint32_t phy_type_mask = 0;
1840
1841         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1842                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1843                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1844                         I40E_AQ_PHY_FLAG_LOW_POWER;
1845         const uint8_t advt = I40E_LINK_SPEED_40GB |
1846                         I40E_LINK_SPEED_25GB |
1847                         I40E_LINK_SPEED_10GB |
1848                         I40E_LINK_SPEED_1GB |
1849                         I40E_LINK_SPEED_100MB;
1850         int ret = -ENOTSUP;
1851
1852
1853         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1854                                               NULL);
1855         if (status)
1856                 return ret;
1857
1858         /* If link already up, no need to set up again */
1859         if (is_up && phy_ab.phy_type != 0)
1860                 return I40E_SUCCESS;
1861
1862         memset(&phy_conf, 0, sizeof(phy_conf));
1863
1864         /* bits 0-2 use the values from get_phy_abilities_resp */
1865         abilities &= ~mask;
1866         abilities |= phy_ab.abilities & mask;
1867
1868         /* update ablities and speed */
1869         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1870                 phy_conf.link_speed = advt;
1871         else
1872                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1873
1874         phy_conf.abilities = abilities;
1875
1876
1877
1878         /* To enable link, phy_type mask needs to include each type */
1879         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1880                 phy_type_mask |= 1 << cnt;
1881
1882         /* use get_phy_abilities_resp value for the rest */
1883         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1884         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1885                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1886                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1887         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1888         phy_conf.eee_capability = phy_ab.eee_capability;
1889         phy_conf.eeer = phy_ab.eeer_val;
1890         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1891
1892         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1893                     phy_ab.abilities, phy_ab.link_speed);
1894         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1895                     phy_conf.abilities, phy_conf.link_speed);
1896
1897         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1898         if (status)
1899                 return ret;
1900
1901         return I40E_SUCCESS;
1902 }
1903
1904 static int
1905 i40e_apply_link_speed(struct rte_eth_dev *dev)
1906 {
1907         uint8_t speed;
1908         uint8_t abilities = 0;
1909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         struct rte_eth_conf *conf = &dev->data->dev_conf;
1911
1912         speed = i40e_parse_link_speeds(conf->link_speeds);
1913         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1914         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1915                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1916         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1917
1918         return i40e_phy_conf_link(hw, abilities, speed, true);
1919 }
1920
1921 static int
1922 i40e_dev_start(struct rte_eth_dev *dev)
1923 {
1924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct i40e_vsi *main_vsi = pf->main_vsi;
1927         int ret, i;
1928         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1929         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1930         uint32_t intr_vector = 0;
1931         struct i40e_vsi *vsi;
1932
1933         hw->adapter_stopped = 0;
1934
1935         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1936                 PMD_INIT_LOG(ERR,
1937                 "Invalid link_speeds for port %u, autonegotiation disabled",
1938                               dev->data->port_id);
1939                 return -EINVAL;
1940         }
1941
1942         rte_intr_disable(intr_handle);
1943
1944         if ((rte_intr_cap_multiple(intr_handle) ||
1945              !RTE_ETH_DEV_SRIOV(dev).active) &&
1946             dev->data->dev_conf.intr_conf.rxq != 0) {
1947                 intr_vector = dev->data->nb_rx_queues;
1948                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1949                 if (ret)
1950                         return ret;
1951         }
1952
1953         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1954                 intr_handle->intr_vec =
1955                         rte_zmalloc("intr_vec",
1956                                     dev->data->nb_rx_queues * sizeof(int),
1957                                     0);
1958                 if (!intr_handle->intr_vec) {
1959                         PMD_INIT_LOG(ERR,
1960                                 "Failed to allocate %d rx_queues intr_vec",
1961                                 dev->data->nb_rx_queues);
1962                         return -ENOMEM;
1963                 }
1964         }
1965
1966         /* Initialize VSI */
1967         ret = i40e_dev_rxtx_init(pf);
1968         if (ret != I40E_SUCCESS) {
1969                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1970                 goto err_up;
1971         }
1972
1973         /* Map queues with MSIX interrupt */
1974         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1975                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1976         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1977         i40e_vsi_enable_queues_intr(main_vsi);
1978
1979         /* Map VMDQ VSI queues with MSIX interrupt */
1980         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1981                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1982                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1983                                           I40E_ITR_INDEX_DEFAULT);
1984                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1985         }
1986
1987         /* enable FDIR MSIX interrupt */
1988         if (pf->fdir.fdir_vsi) {
1989                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1990                                           I40E_ITR_INDEX_NONE);
1991                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1992         }
1993
1994         /* Enable all queues which have been configured */
1995         ret = i40e_dev_switch_queues(pf, TRUE);
1996         if (ret != I40E_SUCCESS) {
1997                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1998                 goto err_up;
1999         }
2000
2001         /* Enable receiving broadcast packets */
2002         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2003         if (ret != I40E_SUCCESS)
2004                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2005
2006         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2007                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2008                                                 true, NULL);
2009                 if (ret != I40E_SUCCESS)
2010                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2011         }
2012
2013         /* Enable the VLAN promiscuous mode. */
2014         if (pf->vfs) {
2015                 for (i = 0; i < pf->vf_num; i++) {
2016                         vsi = pf->vfs[i].vsi;
2017                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2018                                                      true, NULL);
2019                 }
2020         }
2021
2022         /* Enable mac loopback mode */
2023         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2024             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2025                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2026                 if (ret != I40E_SUCCESS) {
2027                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2028                         goto err_up;
2029                 }
2030         }
2031
2032         /* Apply link configure */
2033         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2034                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2035                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2036                                 ETH_LINK_SPEED_40G)) {
2037                 PMD_DRV_LOG(ERR, "Invalid link setting");
2038                 goto err_up;
2039         }
2040         ret = i40e_apply_link_speed(dev);
2041         if (I40E_SUCCESS != ret) {
2042                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2043                 goto err_up;
2044         }
2045
2046         if (!rte_intr_allow_others(intr_handle)) {
2047                 rte_intr_callback_unregister(intr_handle,
2048                                              i40e_dev_interrupt_handler,
2049                                              (void *)dev);
2050                 /* configure and enable device interrupt */
2051                 i40e_pf_config_irq0(hw, FALSE);
2052                 i40e_pf_enable_irq0(hw);
2053
2054                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2055                         PMD_INIT_LOG(INFO,
2056                                 "lsc won't enable because of no intr multiplex");
2057         } else {
2058                 ret = i40e_aq_set_phy_int_mask(hw,
2059                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2060                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2061                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2062                 if (ret != I40E_SUCCESS)
2063                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2064
2065                 /* Call get_link_info aq commond to enable/disable LSE */
2066                 i40e_dev_link_update(dev, 0);
2067         }
2068
2069         /* enable uio intr after callback register */
2070         rte_intr_enable(intr_handle);
2071
2072         i40e_filter_restore(pf);
2073
2074         if (pf->tm_conf.root && !pf->tm_conf.committed)
2075                 PMD_DRV_LOG(WARNING,
2076                             "please call hierarchy_commit() "
2077                             "before starting the port");
2078
2079         return I40E_SUCCESS;
2080
2081 err_up:
2082         i40e_dev_switch_queues(pf, FALSE);
2083         i40e_dev_clear_queues(dev);
2084
2085         return ret;
2086 }
2087
2088 static void
2089 i40e_dev_stop(struct rte_eth_dev *dev)
2090 {
2091         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093         struct i40e_vsi *main_vsi = pf->main_vsi;
2094         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2095         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2096         int i;
2097
2098         if (hw->adapter_stopped == 1)
2099                 return;
2100         /* Disable all queues */
2101         i40e_dev_switch_queues(pf, FALSE);
2102
2103         /* un-map queues with interrupt registers */
2104         i40e_vsi_disable_queues_intr(main_vsi);
2105         i40e_vsi_queues_unbind_intr(main_vsi);
2106
2107         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2108                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2109                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2110         }
2111
2112         if (pf->fdir.fdir_vsi) {
2113                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2114                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2115         }
2116         /* Clear all queues and release memory */
2117         i40e_dev_clear_queues(dev);
2118
2119         /* Set link down */
2120         i40e_dev_set_link_down(dev);
2121
2122         if (!rte_intr_allow_others(intr_handle))
2123                 /* resume to the default handler */
2124                 rte_intr_callback_register(intr_handle,
2125                                            i40e_dev_interrupt_handler,
2126                                            (void *)dev);
2127
2128         /* Clean datapath event and queue/vec mapping */
2129         rte_intr_efd_disable(intr_handle);
2130         if (intr_handle->intr_vec) {
2131                 rte_free(intr_handle->intr_vec);
2132                 intr_handle->intr_vec = NULL;
2133         }
2134
2135         /* reset hierarchy commit */
2136         pf->tm_conf.committed = false;
2137
2138         /* Remove all the queue region configuration */
2139         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2140
2141         hw->adapter_stopped = 1;
2142 }
2143
2144 static void
2145 i40e_dev_close(struct rte_eth_dev *dev)
2146 {
2147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2150         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2151         struct i40e_mirror_rule *p_mirror;
2152         uint32_t reg;
2153         int i;
2154         int ret;
2155
2156         PMD_INIT_FUNC_TRACE();
2157
2158         i40e_dev_stop(dev);
2159
2160         /* Remove all mirror rules */
2161         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2162                 ret = i40e_aq_del_mirror_rule(hw,
2163                                               pf->main_vsi->veb->seid,
2164                                               p_mirror->rule_type,
2165                                               p_mirror->entries,
2166                                               p_mirror->num_entries,
2167                                               p_mirror->id);
2168                 if (ret < 0)
2169                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2170                                     "status = %d, aq_err = %d.", ret,
2171                                     hw->aq.asq_last_status);
2172
2173                 /* remove mirror software resource anyway */
2174                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2175                 rte_free(p_mirror);
2176                 pf->nb_mirror_rule--;
2177         }
2178
2179         i40e_dev_free_queues(dev);
2180
2181         /* Disable interrupt */
2182         i40e_pf_disable_irq0(hw);
2183         rte_intr_disable(intr_handle);
2184
2185         /* shutdown and destroy the HMC */
2186         i40e_shutdown_lan_hmc(hw);
2187
2188         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2189                 i40e_vsi_release(pf->vmdq[i].vsi);
2190                 pf->vmdq[i].vsi = NULL;
2191         }
2192         rte_free(pf->vmdq);
2193         pf->vmdq = NULL;
2194
2195         /* release all the existing VSIs and VEBs */
2196         i40e_fdir_teardown(pf);
2197         i40e_vsi_release(pf->main_vsi);
2198
2199         /* shutdown the adminq */
2200         i40e_aq_queue_shutdown(hw, true);
2201         i40e_shutdown_adminq(hw);
2202
2203         i40e_res_pool_destroy(&pf->qp_pool);
2204         i40e_res_pool_destroy(&pf->msix_pool);
2205
2206         /* force a PF reset to clean anything leftover */
2207         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2208         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2209                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2210         I40E_WRITE_FLUSH(hw);
2211 }
2212
2213 /*
2214  * Reset PF device only to re-initialize resources in PMD layer
2215  */
2216 static int
2217 i40e_dev_reset(struct rte_eth_dev *dev)
2218 {
2219         int ret;
2220
2221         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2222          * its VF to make them align with it. The detailed notification
2223          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2224          * To avoid unexpected behavior in VF, currently reset of PF with
2225          * SR-IOV activation is not supported. It might be supported later.
2226          */
2227         if (dev->data->sriov.active)
2228                 return -ENOTSUP;
2229
2230         ret = eth_i40e_dev_uninit(dev);
2231         if (ret)
2232                 return ret;
2233
2234         ret = eth_i40e_dev_init(dev);
2235
2236         return ret;
2237 }
2238
2239 static void
2240 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2241 {
2242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244         struct i40e_vsi *vsi = pf->main_vsi;
2245         int status;
2246
2247         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2248                                                      true, NULL, true);
2249         if (status != I40E_SUCCESS)
2250                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2251
2252         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2253                                                         TRUE, NULL);
2254         if (status != I40E_SUCCESS)
2255                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2256
2257 }
2258
2259 static void
2260 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2261 {
2262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2263         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2264         struct i40e_vsi *vsi = pf->main_vsi;
2265         int status;
2266
2267         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2268                                                      false, NULL, true);
2269         if (status != I40E_SUCCESS)
2270                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2271
2272         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2273                                                         false, NULL);
2274         if (status != I40E_SUCCESS)
2275                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2276 }
2277
2278 static void
2279 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2280 {
2281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283         struct i40e_vsi *vsi = pf->main_vsi;
2284         int ret;
2285
2286         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2287         if (ret != I40E_SUCCESS)
2288                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2289 }
2290
2291 static void
2292 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2293 {
2294         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2295         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296         struct i40e_vsi *vsi = pf->main_vsi;
2297         int ret;
2298
2299         if (dev->data->promiscuous == 1)
2300                 return; /* must remain in all_multicast mode */
2301
2302         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2303                                 vsi->seid, FALSE, NULL);
2304         if (ret != I40E_SUCCESS)
2305                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2306 }
2307
2308 /*
2309  * Set device link up.
2310  */
2311 static int
2312 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2313 {
2314         /* re-apply link speed setting */
2315         return i40e_apply_link_speed(dev);
2316 }
2317
2318 /*
2319  * Set device link down.
2320  */
2321 static int
2322 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2323 {
2324         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2325         uint8_t abilities = 0;
2326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2327
2328         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2329         return i40e_phy_conf_link(hw, abilities, speed, false);
2330 }
2331
2332 int
2333 i40e_dev_link_update(struct rte_eth_dev *dev,
2334                      int wait_to_complete)
2335 {
2336 #define CHECK_INTERVAL 100  /* 100ms */
2337 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339         struct i40e_link_status link_status;
2340         struct rte_eth_link link, old;
2341         int status;
2342         unsigned rep_cnt = MAX_REPEAT_TIME;
2343         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2344
2345         memset(&link, 0, sizeof(link));
2346         memset(&old, 0, sizeof(old));
2347         memset(&link_status, 0, sizeof(link_status));
2348         rte_i40e_dev_atomic_read_link_status(dev, &old);
2349
2350         do {
2351                 /* Get link status information from hardware */
2352                 status = i40e_aq_get_link_info(hw, enable_lse,
2353                                                 &link_status, NULL);
2354                 if (status != I40E_SUCCESS) {
2355                         link.link_speed = ETH_SPEED_NUM_100M;
2356                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2357                         PMD_DRV_LOG(ERR, "Failed to get link info");
2358                         goto out;
2359                 }
2360
2361                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2362                 if (!wait_to_complete || link.link_status)
2363                         break;
2364
2365                 rte_delay_ms(CHECK_INTERVAL);
2366         } while (--rep_cnt);
2367
2368         if (!link.link_status)
2369                 goto out;
2370
2371         /* i40e uses full duplex only */
2372         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2373
2374         /* Parse the link status */
2375         switch (link_status.link_speed) {
2376         case I40E_LINK_SPEED_100MB:
2377                 link.link_speed = ETH_SPEED_NUM_100M;
2378                 break;
2379         case I40E_LINK_SPEED_1GB:
2380                 link.link_speed = ETH_SPEED_NUM_1G;
2381                 break;
2382         case I40E_LINK_SPEED_10GB:
2383                 link.link_speed = ETH_SPEED_NUM_10G;
2384                 break;
2385         case I40E_LINK_SPEED_20GB:
2386                 link.link_speed = ETH_SPEED_NUM_20G;
2387                 break;
2388         case I40E_LINK_SPEED_25GB:
2389                 link.link_speed = ETH_SPEED_NUM_25G;
2390                 break;
2391         case I40E_LINK_SPEED_40GB:
2392                 link.link_speed = ETH_SPEED_NUM_40G;
2393                 break;
2394         default:
2395                 link.link_speed = ETH_SPEED_NUM_100M;
2396                 break;
2397         }
2398
2399         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2400                         ETH_LINK_SPEED_FIXED);
2401
2402 out:
2403         rte_i40e_dev_atomic_write_link_status(dev, &link);
2404         if (link.link_status == old.link_status)
2405                 return -1;
2406
2407         i40e_notify_all_vfs_link_status(dev);
2408
2409         return 0;
2410 }
2411
2412 /* Get all the statistics of a VSI */
2413 void
2414 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2415 {
2416         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2417         struct i40e_eth_stats *nes = &vsi->eth_stats;
2418         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2419         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2420
2421         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2422                             vsi->offset_loaded, &oes->rx_bytes,
2423                             &nes->rx_bytes);
2424         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2425                             vsi->offset_loaded, &oes->rx_unicast,
2426                             &nes->rx_unicast);
2427         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2428                             vsi->offset_loaded, &oes->rx_multicast,
2429                             &nes->rx_multicast);
2430         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2431                             vsi->offset_loaded, &oes->rx_broadcast,
2432                             &nes->rx_broadcast);
2433         /* exclude CRC bytes */
2434         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2435                 nes->rx_broadcast) * ETHER_CRC_LEN;
2436
2437         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2438                             &oes->rx_discards, &nes->rx_discards);
2439         /* GLV_REPC not supported */
2440         /* GLV_RMPC not supported */
2441         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2442                             &oes->rx_unknown_protocol,
2443                             &nes->rx_unknown_protocol);
2444         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2445                             vsi->offset_loaded, &oes->tx_bytes,
2446                             &nes->tx_bytes);
2447         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2448                             vsi->offset_loaded, &oes->tx_unicast,
2449                             &nes->tx_unicast);
2450         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2451                             vsi->offset_loaded, &oes->tx_multicast,
2452                             &nes->tx_multicast);
2453         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2454                             vsi->offset_loaded,  &oes->tx_broadcast,
2455                             &nes->tx_broadcast);
2456         /* GLV_TDPC not supported */
2457         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2458                             &oes->tx_errors, &nes->tx_errors);
2459         vsi->offset_loaded = true;
2460
2461         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2462                     vsi->vsi_id);
2463         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2464         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2465         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2466         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2467         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2468         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2469                     nes->rx_unknown_protocol);
2470         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2471         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2472         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2473         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2474         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2475         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2476         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2477                     vsi->vsi_id);
2478 }
2479
2480 static void
2481 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2482 {
2483         unsigned int i;
2484         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2485         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2486
2487         /* Get rx/tx bytes of internal transfer packets */
2488         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2489                         I40E_GLV_GORCL(hw->port),
2490                         pf->offset_loaded,
2491                         &pf->internal_stats_offset.rx_bytes,
2492                         &pf->internal_stats.rx_bytes);
2493
2494         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2495                         I40E_GLV_GOTCL(hw->port),
2496                         pf->offset_loaded,
2497                         &pf->internal_stats_offset.tx_bytes,
2498                         &pf->internal_stats.tx_bytes);
2499         /* Get total internal rx packet count */
2500         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2501                             I40E_GLV_UPRCL(hw->port),
2502                             pf->offset_loaded,
2503                             &pf->internal_stats_offset.rx_unicast,
2504                             &pf->internal_stats.rx_unicast);
2505         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2506                             I40E_GLV_MPRCL(hw->port),
2507                             pf->offset_loaded,
2508                             &pf->internal_stats_offset.rx_multicast,
2509                             &pf->internal_stats.rx_multicast);
2510         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2511                             I40E_GLV_BPRCL(hw->port),
2512                             pf->offset_loaded,
2513                             &pf->internal_stats_offset.rx_broadcast,
2514                             &pf->internal_stats.rx_broadcast);
2515
2516         /* exclude CRC size */
2517         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2518                 pf->internal_stats.rx_multicast +
2519                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2520
2521         /* Get statistics of struct i40e_eth_stats */
2522         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2523                             I40E_GLPRT_GORCL(hw->port),
2524                             pf->offset_loaded, &os->eth.rx_bytes,
2525                             &ns->eth.rx_bytes);
2526         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2527                             I40E_GLPRT_UPRCL(hw->port),
2528                             pf->offset_loaded, &os->eth.rx_unicast,
2529                             &ns->eth.rx_unicast);
2530         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2531                             I40E_GLPRT_MPRCL(hw->port),
2532                             pf->offset_loaded, &os->eth.rx_multicast,
2533                             &ns->eth.rx_multicast);
2534         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2535                             I40E_GLPRT_BPRCL(hw->port),
2536                             pf->offset_loaded, &os->eth.rx_broadcast,
2537                             &ns->eth.rx_broadcast);
2538         /* Workaround: CRC size should not be included in byte statistics,
2539          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2540          */
2541         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2542                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2543
2544         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2545          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2546          * value.
2547          */
2548         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2549                 ns->eth.rx_bytes = 0;
2550         /* exlude internal rx bytes */
2551         else
2552                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2553
2554         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2555                             pf->offset_loaded, &os->eth.rx_discards,
2556                             &ns->eth.rx_discards);
2557         /* GLPRT_REPC not supported */
2558         /* GLPRT_RMPC not supported */
2559         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2560                             pf->offset_loaded,
2561                             &os->eth.rx_unknown_protocol,
2562                             &ns->eth.rx_unknown_protocol);
2563         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2564                             I40E_GLPRT_GOTCL(hw->port),
2565                             pf->offset_loaded, &os->eth.tx_bytes,
2566                             &ns->eth.tx_bytes);
2567         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2568                             I40E_GLPRT_UPTCL(hw->port),
2569                             pf->offset_loaded, &os->eth.tx_unicast,
2570                             &ns->eth.tx_unicast);
2571         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2572                             I40E_GLPRT_MPTCL(hw->port),
2573                             pf->offset_loaded, &os->eth.tx_multicast,
2574                             &ns->eth.tx_multicast);
2575         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2576                             I40E_GLPRT_BPTCL(hw->port),
2577                             pf->offset_loaded, &os->eth.tx_broadcast,
2578                             &ns->eth.tx_broadcast);
2579         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2580                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2581
2582         /* exclude internal tx bytes */
2583         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2584                 ns->eth.tx_bytes = 0;
2585         else
2586                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2587
2588         /* GLPRT_TEPC not supported */
2589
2590         /* additional port specific stats */
2591         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2592                             pf->offset_loaded, &os->tx_dropped_link_down,
2593                             &ns->tx_dropped_link_down);
2594         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2595                             pf->offset_loaded, &os->crc_errors,
2596                             &ns->crc_errors);
2597         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2598                             pf->offset_loaded, &os->illegal_bytes,
2599                             &ns->illegal_bytes);
2600         /* GLPRT_ERRBC not supported */
2601         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2602                             pf->offset_loaded, &os->mac_local_faults,
2603                             &ns->mac_local_faults);
2604         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2605                             pf->offset_loaded, &os->mac_remote_faults,
2606                             &ns->mac_remote_faults);
2607         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2608                             pf->offset_loaded, &os->rx_length_errors,
2609                             &ns->rx_length_errors);
2610         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2611                             pf->offset_loaded, &os->link_xon_rx,
2612                             &ns->link_xon_rx);
2613         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2614                             pf->offset_loaded, &os->link_xoff_rx,
2615                             &ns->link_xoff_rx);
2616         for (i = 0; i < 8; i++) {
2617                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2618                                     pf->offset_loaded,
2619                                     &os->priority_xon_rx[i],
2620                                     &ns->priority_xon_rx[i]);
2621                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2622                                     pf->offset_loaded,
2623                                     &os->priority_xoff_rx[i],
2624                                     &ns->priority_xoff_rx[i]);
2625         }
2626         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2627                             pf->offset_loaded, &os->link_xon_tx,
2628                             &ns->link_xon_tx);
2629         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2630                             pf->offset_loaded, &os->link_xoff_tx,
2631                             &ns->link_xoff_tx);
2632         for (i = 0; i < 8; i++) {
2633                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2634                                     pf->offset_loaded,
2635                                     &os->priority_xon_tx[i],
2636                                     &ns->priority_xon_tx[i]);
2637                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2638                                     pf->offset_loaded,
2639                                     &os->priority_xoff_tx[i],
2640                                     &ns->priority_xoff_tx[i]);
2641                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2642                                     pf->offset_loaded,
2643                                     &os->priority_xon_2_xoff[i],
2644                                     &ns->priority_xon_2_xoff[i]);
2645         }
2646         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2647                             I40E_GLPRT_PRC64L(hw->port),
2648                             pf->offset_loaded, &os->rx_size_64,
2649                             &ns->rx_size_64);
2650         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2651                             I40E_GLPRT_PRC127L(hw->port),
2652                             pf->offset_loaded, &os->rx_size_127,
2653                             &ns->rx_size_127);
2654         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2655                             I40E_GLPRT_PRC255L(hw->port),
2656                             pf->offset_loaded, &os->rx_size_255,
2657                             &ns->rx_size_255);
2658         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2659                             I40E_GLPRT_PRC511L(hw->port),
2660                             pf->offset_loaded, &os->rx_size_511,
2661                             &ns->rx_size_511);
2662         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2663                             I40E_GLPRT_PRC1023L(hw->port),
2664                             pf->offset_loaded, &os->rx_size_1023,
2665                             &ns->rx_size_1023);
2666         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2667                             I40E_GLPRT_PRC1522L(hw->port),
2668                             pf->offset_loaded, &os->rx_size_1522,
2669                             &ns->rx_size_1522);
2670         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2671                             I40E_GLPRT_PRC9522L(hw->port),
2672                             pf->offset_loaded, &os->rx_size_big,
2673                             &ns->rx_size_big);
2674         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2675                             pf->offset_loaded, &os->rx_undersize,
2676                             &ns->rx_undersize);
2677         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2678                             pf->offset_loaded, &os->rx_fragments,
2679                             &ns->rx_fragments);
2680         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2681                             pf->offset_loaded, &os->rx_oversize,
2682                             &ns->rx_oversize);
2683         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2684                             pf->offset_loaded, &os->rx_jabber,
2685                             &ns->rx_jabber);
2686         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2687                             I40E_GLPRT_PTC64L(hw->port),
2688                             pf->offset_loaded, &os->tx_size_64,
2689                             &ns->tx_size_64);
2690         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2691                             I40E_GLPRT_PTC127L(hw->port),
2692                             pf->offset_loaded, &os->tx_size_127,
2693                             &ns->tx_size_127);
2694         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2695                             I40E_GLPRT_PTC255L(hw->port),
2696                             pf->offset_loaded, &os->tx_size_255,
2697                             &ns->tx_size_255);
2698         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2699                             I40E_GLPRT_PTC511L(hw->port),
2700                             pf->offset_loaded, &os->tx_size_511,
2701                             &ns->tx_size_511);
2702         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2703                             I40E_GLPRT_PTC1023L(hw->port),
2704                             pf->offset_loaded, &os->tx_size_1023,
2705                             &ns->tx_size_1023);
2706         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2707                             I40E_GLPRT_PTC1522L(hw->port),
2708                             pf->offset_loaded, &os->tx_size_1522,
2709                             &ns->tx_size_1522);
2710         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2711                             I40E_GLPRT_PTC9522L(hw->port),
2712                             pf->offset_loaded, &os->tx_size_big,
2713                             &ns->tx_size_big);
2714         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2715                            pf->offset_loaded,
2716                            &os->fd_sb_match, &ns->fd_sb_match);
2717         /* GLPRT_MSPDC not supported */
2718         /* GLPRT_XEC not supported */
2719
2720         pf->offset_loaded = true;
2721
2722         if (pf->main_vsi)
2723                 i40e_update_vsi_stats(pf->main_vsi);
2724 }
2725
2726 /* Get all statistics of a port */
2727 static int
2728 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2729 {
2730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2733         unsigned i;
2734
2735         /* call read registers - updates values, now write them to struct */
2736         i40e_read_stats_registers(pf, hw);
2737
2738         stats->ipackets = ns->eth.rx_unicast +
2739                         ns->eth.rx_multicast +
2740                         ns->eth.rx_broadcast -
2741                         ns->eth.rx_discards -
2742                         pf->main_vsi->eth_stats.rx_discards;
2743         stats->opackets = ns->eth.tx_unicast +
2744                         ns->eth.tx_multicast +
2745                         ns->eth.tx_broadcast;
2746         stats->ibytes   = ns->eth.rx_bytes;
2747         stats->obytes   = ns->eth.tx_bytes;
2748         stats->oerrors  = ns->eth.tx_errors +
2749                         pf->main_vsi->eth_stats.tx_errors;
2750
2751         /* Rx Errors */
2752         stats->imissed  = ns->eth.rx_discards +
2753                         pf->main_vsi->eth_stats.rx_discards;
2754         stats->ierrors  = ns->crc_errors +
2755                         ns->rx_length_errors + ns->rx_undersize +
2756                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2757
2758         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2759         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2760         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2761         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2762         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2763         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2764         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2765                     ns->eth.rx_unknown_protocol);
2766         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2767         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2768         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2769         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2770         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2771         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2772
2773         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2774                     ns->tx_dropped_link_down);
2775         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2776         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2777                     ns->illegal_bytes);
2778         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2779         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2780                     ns->mac_local_faults);
2781         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2782                     ns->mac_remote_faults);
2783         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2784                     ns->rx_length_errors);
2785         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2786         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2787         for (i = 0; i < 8; i++) {
2788                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2789                                 i, ns->priority_xon_rx[i]);
2790                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2791                                 i, ns->priority_xoff_rx[i]);
2792         }
2793         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2794         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2795         for (i = 0; i < 8; i++) {
2796                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2797                                 i, ns->priority_xon_tx[i]);
2798                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2799                                 i, ns->priority_xoff_tx[i]);
2800                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2801                                 i, ns->priority_xon_2_xoff[i]);
2802         }
2803         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2804         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2805         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2806         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2807         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2808         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2809         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2810         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2811         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2812         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2813         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2814         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2815         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2816         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2817         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2818         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2819         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2820         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2821         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2822                         ns->mac_short_packet_dropped);
2823         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2824                     ns->checksum_error);
2825         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2826         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2827         return 0;
2828 }
2829
2830 /* Reset the statistics */
2831 static void
2832 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2833 {
2834         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836
2837         /* Mark PF and VSI stats to update the offset, aka "reset" */
2838         pf->offset_loaded = false;
2839         if (pf->main_vsi)
2840                 pf->main_vsi->offset_loaded = false;
2841
2842         /* read the stats, reading current register values into offset */
2843         i40e_read_stats_registers(pf, hw);
2844 }
2845
2846 static uint32_t
2847 i40e_xstats_calc_num(void)
2848 {
2849         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2850                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2851                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2852 }
2853
2854 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855                                      struct rte_eth_xstat_name *xstats_names,
2856                                      __rte_unused unsigned limit)
2857 {
2858         unsigned count = 0;
2859         unsigned i, prio;
2860
2861         if (xstats_names == NULL)
2862                 return i40e_xstats_calc_num();
2863
2864         /* Note: limit checked in rte_eth_xstats_names() */
2865
2866         /* Get stats from i40e_eth_stats struct */
2867         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2868                 snprintf(xstats_names[count].name,
2869                          sizeof(xstats_names[count].name),
2870                          "%s", rte_i40e_stats_strings[i].name);
2871                 count++;
2872         }
2873
2874         /* Get individiual stats from i40e_hw_port struct */
2875         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2876                 snprintf(xstats_names[count].name,
2877                         sizeof(xstats_names[count].name),
2878                          "%s", rte_i40e_hw_port_strings[i].name);
2879                 count++;
2880         }
2881
2882         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2883                 for (prio = 0; prio < 8; prio++) {
2884                         snprintf(xstats_names[count].name,
2885                                  sizeof(xstats_names[count].name),
2886                                  "rx_priority%u_%s", prio,
2887                                  rte_i40e_rxq_prio_strings[i].name);
2888                         count++;
2889                 }
2890         }
2891
2892         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2893                 for (prio = 0; prio < 8; prio++) {
2894                         snprintf(xstats_names[count].name,
2895                                  sizeof(xstats_names[count].name),
2896                                  "tx_priority%u_%s", prio,
2897                                  rte_i40e_txq_prio_strings[i].name);
2898                         count++;
2899                 }
2900         }
2901         return count;
2902 }
2903
2904 static int
2905 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2906                     unsigned n)
2907 {
2908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910         unsigned i, count, prio;
2911         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2912
2913         count = i40e_xstats_calc_num();
2914         if (n < count)
2915                 return count;
2916
2917         i40e_read_stats_registers(pf, hw);
2918
2919         if (xstats == NULL)
2920                 return 0;
2921
2922         count = 0;
2923
2924         /* Get stats from i40e_eth_stats struct */
2925         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2926                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2927                         rte_i40e_stats_strings[i].offset);
2928                 xstats[count].id = count;
2929                 count++;
2930         }
2931
2932         /* Get individiual stats from i40e_hw_port struct */
2933         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2934                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2935                         rte_i40e_hw_port_strings[i].offset);
2936                 xstats[count].id = count;
2937                 count++;
2938         }
2939
2940         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2941                 for (prio = 0; prio < 8; prio++) {
2942                         xstats[count].value =
2943                                 *(uint64_t *)(((char *)hw_stats) +
2944                                 rte_i40e_rxq_prio_strings[i].offset +
2945                                 (sizeof(uint64_t) * prio));
2946                         xstats[count].id = count;
2947                         count++;
2948                 }
2949         }
2950
2951         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2952                 for (prio = 0; prio < 8; prio++) {
2953                         xstats[count].value =
2954                                 *(uint64_t *)(((char *)hw_stats) +
2955                                 rte_i40e_txq_prio_strings[i].offset +
2956                                 (sizeof(uint64_t) * prio));
2957                         xstats[count].id = count;
2958                         count++;
2959                 }
2960         }
2961
2962         return count;
2963 }
2964
2965 static int
2966 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2967                                  __rte_unused uint16_t queue_id,
2968                                  __rte_unused uint8_t stat_idx,
2969                                  __rte_unused uint8_t is_rx)
2970 {
2971         PMD_INIT_FUNC_TRACE();
2972
2973         return -ENOSYS;
2974 }
2975
2976 static int
2977 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2978 {
2979         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980         u32 full_ver;
2981         u8 ver, patch;
2982         u16 build;
2983         int ret;
2984
2985         full_ver = hw->nvm.oem_ver;
2986         ver = (u8)(full_ver >> 24);
2987         build = (u16)((full_ver >> 8) & 0xffff);
2988         patch = (u8)(full_ver & 0xff);
2989
2990         ret = snprintf(fw_version, fw_size,
2991                  "%d.%d%d 0x%08x %d.%d.%d",
2992                  ((hw->nvm.version >> 12) & 0xf),
2993                  ((hw->nvm.version >> 4) & 0xff),
2994                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2995                  ver, build, patch);
2996
2997         ret += 1; /* add the size of '\0' */
2998         if (fw_size < (u32)ret)
2999                 return ret;
3000         else
3001                 return 0;
3002 }
3003
3004 static void
3005 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3006 {
3007         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009         struct i40e_vsi *vsi = pf->main_vsi;
3010         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3011
3012         dev_info->pci_dev = pci_dev;
3013         dev_info->max_rx_queues = vsi->nb_qps;
3014         dev_info->max_tx_queues = vsi->nb_qps;
3015         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3016         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3017         dev_info->max_mac_addrs = vsi->max_macaddrs;
3018         dev_info->max_vfs = pci_dev->max_vfs;
3019         dev_info->rx_offload_capa =
3020                 DEV_RX_OFFLOAD_VLAN_STRIP |
3021                 DEV_RX_OFFLOAD_QINQ_STRIP |
3022                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3023                 DEV_RX_OFFLOAD_UDP_CKSUM |
3024                 DEV_RX_OFFLOAD_TCP_CKSUM;
3025         dev_info->tx_offload_capa =
3026                 DEV_TX_OFFLOAD_VLAN_INSERT |
3027                 DEV_TX_OFFLOAD_QINQ_INSERT |
3028                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3029                 DEV_TX_OFFLOAD_UDP_CKSUM |
3030                 DEV_TX_OFFLOAD_TCP_CKSUM |
3031                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3032                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3033                 DEV_TX_OFFLOAD_TCP_TSO |
3034                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3035                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3036                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3037                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3038         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3039                                                 sizeof(uint32_t);
3040         dev_info->reta_size = pf->hash_lut_size;
3041         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3042
3043         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3044                 .rx_thresh = {
3045                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3046                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3047                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3048                 },
3049                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3050                 .rx_drop_en = 0,
3051         };
3052
3053         dev_info->default_txconf = (struct rte_eth_txconf) {
3054                 .tx_thresh = {
3055                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3056                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3057                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3058                 },
3059                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3060                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3061                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3062                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3063         };
3064
3065         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3066                 .nb_max = I40E_MAX_RING_DESC,
3067                 .nb_min = I40E_MIN_RING_DESC,
3068                 .nb_align = I40E_ALIGN_RING_DESC,
3069         };
3070
3071         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3072                 .nb_max = I40E_MAX_RING_DESC,
3073                 .nb_min = I40E_MIN_RING_DESC,
3074                 .nb_align = I40E_ALIGN_RING_DESC,
3075                 .nb_seg_max = I40E_TX_MAX_SEG,
3076                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3077         };
3078
3079         if (pf->flags & I40E_FLAG_VMDQ) {
3080                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3081                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3082                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3083                                                 pf->max_nb_vmdq_vsi;
3084                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3085                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3086                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3087         }
3088
3089         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3090                 /* For XL710 */
3091                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3092         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3093                 /* For XXV710 */
3094                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3095         else
3096                 /* For X710 */
3097                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3098 }
3099
3100 static int
3101 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3102 {
3103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3104         struct i40e_vsi *vsi = pf->main_vsi;
3105         PMD_INIT_FUNC_TRACE();
3106
3107         if (on)
3108                 return i40e_vsi_add_vlan(vsi, vlan_id);
3109         else
3110                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3111 }
3112
3113 static int
3114 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3115                                 enum rte_vlan_type vlan_type,
3116                                 uint16_t tpid, int qinq)
3117 {
3118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119         uint64_t reg_r = 0;
3120         uint64_t reg_w = 0;
3121         uint16_t reg_id = 3;
3122         int ret;
3123
3124         if (qinq) {
3125                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3126                         reg_id = 2;
3127         }
3128
3129         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3130                                           &reg_r, NULL);
3131         if (ret != I40E_SUCCESS) {
3132                 PMD_DRV_LOG(ERR,
3133                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3134                            reg_id);
3135                 return -EIO;
3136         }
3137         PMD_DRV_LOG(DEBUG,
3138                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3139                     reg_id, reg_r);
3140
3141         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3142         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3143         if (reg_r == reg_w) {
3144                 PMD_DRV_LOG(DEBUG, "No need to write");
3145                 return 0;
3146         }
3147
3148         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3149                                            reg_w, NULL);
3150         if (ret != I40E_SUCCESS) {
3151                 PMD_DRV_LOG(ERR,
3152                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3153                             reg_id);
3154                 return -EIO;
3155         }
3156         PMD_DRV_LOG(DEBUG,
3157                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3158                     reg_w, reg_id);
3159
3160         return 0;
3161 }
3162
3163 static int
3164 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3165                    enum rte_vlan_type vlan_type,
3166                    uint16_t tpid)
3167 {
3168         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3170         int ret = 0;
3171
3172         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3173              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3174             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3175                 PMD_DRV_LOG(ERR,
3176                             "Unsupported vlan type.");
3177                 return -EINVAL;
3178         }
3179         /* 802.1ad frames ability is added in NVM API 1.7*/
3180         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3181                 if (qinq) {
3182                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3183                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3184                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3185                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3186                 } else {
3187                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3188                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3189                 }
3190                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3191                 if (ret != I40E_SUCCESS) {
3192                         PMD_DRV_LOG(ERR,
3193                                     "Set switch config failed aq_err: %d",
3194                                     hw->aq.asq_last_status);
3195                         ret = -EIO;
3196                 }
3197         } else
3198                 /* If NVM API < 1.7, keep the register setting */
3199                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3200                                                       tpid, qinq);
3201
3202         return ret;
3203 }
3204
3205 static int
3206 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3207 {
3208         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3209         struct i40e_vsi *vsi = pf->main_vsi;
3210
3211         if (mask & ETH_VLAN_FILTER_MASK) {
3212                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3213                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3214                 else
3215                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3216         }
3217
3218         if (mask & ETH_VLAN_STRIP_MASK) {
3219                 /* Enable or disable VLAN stripping */
3220                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3221                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3222                 else
3223                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3224         }
3225
3226         if (mask & ETH_VLAN_EXTEND_MASK) {
3227                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3228                         i40e_vsi_config_double_vlan(vsi, TRUE);
3229                         /* Set global registers with default ethertype. */
3230                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3231                                            ETHER_TYPE_VLAN);
3232                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3233                                            ETHER_TYPE_VLAN);
3234                 }
3235                 else
3236                         i40e_vsi_config_double_vlan(vsi, FALSE);
3237         }
3238
3239         return 0;
3240 }
3241
3242 static void
3243 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3244                           __rte_unused uint16_t queue,
3245                           __rte_unused int on)
3246 {
3247         PMD_INIT_FUNC_TRACE();
3248 }
3249
3250 static int
3251 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3252 {
3253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254         struct i40e_vsi *vsi = pf->main_vsi;
3255         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3256         struct i40e_vsi_vlan_pvid_info info;
3257
3258         memset(&info, 0, sizeof(info));
3259         info.on = on;
3260         if (info.on)
3261                 info.config.pvid = pvid;
3262         else {
3263                 info.config.reject.tagged =
3264                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3265                 info.config.reject.untagged =
3266                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3267         }
3268
3269         return i40e_vsi_vlan_pvid_set(vsi, &info);
3270 }
3271
3272 static int
3273 i40e_dev_led_on(struct rte_eth_dev *dev)
3274 {
3275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276         uint32_t mode = i40e_led_get(hw);
3277
3278         if (mode == 0)
3279                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3280
3281         return 0;
3282 }
3283
3284 static int
3285 i40e_dev_led_off(struct rte_eth_dev *dev)
3286 {
3287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         uint32_t mode = i40e_led_get(hw);
3289
3290         if (mode != 0)
3291                 i40e_led_set(hw, 0, false);
3292
3293         return 0;
3294 }
3295
3296 static int
3297 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3298 {
3299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301
3302         fc_conf->pause_time = pf->fc_conf.pause_time;
3303
3304         /* read out from register, in case they are modified by other port */
3305         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3306                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3307         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3308                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3309
3310         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3311         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3312
3313          /* Return current mode according to actual setting*/
3314         switch (hw->fc.current_mode) {
3315         case I40E_FC_FULL:
3316                 fc_conf->mode = RTE_FC_FULL;
3317                 break;
3318         case I40E_FC_TX_PAUSE:
3319                 fc_conf->mode = RTE_FC_TX_PAUSE;
3320                 break;
3321         case I40E_FC_RX_PAUSE:
3322                 fc_conf->mode = RTE_FC_RX_PAUSE;
3323                 break;
3324         case I40E_FC_NONE:
3325         default:
3326                 fc_conf->mode = RTE_FC_NONE;
3327         };
3328
3329         return 0;
3330 }
3331
3332 static int
3333 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3334 {
3335         uint32_t mflcn_reg, fctrl_reg, reg;
3336         uint32_t max_high_water;
3337         uint8_t i, aq_failure;
3338         int err;
3339         struct i40e_hw *hw;
3340         struct i40e_pf *pf;
3341         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3342                 [RTE_FC_NONE] = I40E_FC_NONE,
3343                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3344                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3345                 [RTE_FC_FULL] = I40E_FC_FULL
3346         };
3347
3348         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3349
3350         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3351         if ((fc_conf->high_water > max_high_water) ||
3352                         (fc_conf->high_water < fc_conf->low_water)) {
3353                 PMD_INIT_LOG(ERR,
3354                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3355                         max_high_water);
3356                 return -EINVAL;
3357         }
3358
3359         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3362
3363         pf->fc_conf.pause_time = fc_conf->pause_time;
3364         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3365         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3366
3367         PMD_INIT_FUNC_TRACE();
3368
3369         /* All the link flow control related enable/disable register
3370          * configuration is handle by the F/W
3371          */
3372         err = i40e_set_fc(hw, &aq_failure, true);
3373         if (err < 0)
3374                 return -ENOSYS;
3375
3376         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3377                 /* Configure flow control refresh threshold,
3378                  * the value for stat_tx_pause_refresh_timer[8]
3379                  * is used for global pause operation.
3380                  */
3381
3382                 I40E_WRITE_REG(hw,
3383                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3384                                pf->fc_conf.pause_time);
3385
3386                 /* configure the timer value included in transmitted pause
3387                  * frame,
3388                  * the value for stat_tx_pause_quanta[8] is used for global
3389                  * pause operation
3390                  */
3391                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3392                                pf->fc_conf.pause_time);
3393
3394                 fctrl_reg = I40E_READ_REG(hw,
3395                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3396
3397                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3398                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3399                 else
3400                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3401
3402                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3403                                fctrl_reg);
3404         } else {
3405                 /* Configure pause time (2 TCs per register) */
3406                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3407                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3408                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3409
3410                 /* Configure flow control refresh threshold value */
3411                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3412                                pf->fc_conf.pause_time / 2);
3413
3414                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3415
3416                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3417                  *depending on configuration
3418                  */
3419                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3420                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3421                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3422                 } else {
3423                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3424                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3425                 }
3426
3427                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3428         }
3429
3430         /* config the water marker both based on the packets and bytes */
3431         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3432                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3433                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3434         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3435                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3436                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3437         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3438                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3439                        << I40E_KILOSHIFT);
3440         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3441                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3442                        << I40E_KILOSHIFT);
3443
3444         I40E_WRITE_FLUSH(hw);
3445
3446         return 0;
3447 }
3448
3449 static int
3450 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3451                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3452 {
3453         PMD_INIT_FUNC_TRACE();
3454
3455         return -ENOSYS;
3456 }
3457
3458 /* Add a MAC address, and update filters */
3459 static int
3460 i40e_macaddr_add(struct rte_eth_dev *dev,
3461                  struct ether_addr *mac_addr,
3462                  __rte_unused uint32_t index,
3463                  uint32_t pool)
3464 {
3465         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3466         struct i40e_mac_filter_info mac_filter;
3467         struct i40e_vsi *vsi;
3468         int ret;
3469
3470         /* If VMDQ not enabled or configured, return */
3471         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3472                           !pf->nb_cfg_vmdq_vsi)) {
3473                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3474                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3475                         pool);
3476                 return -ENOTSUP;
3477         }
3478
3479         if (pool > pf->nb_cfg_vmdq_vsi) {
3480                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3481                                 pool, pf->nb_cfg_vmdq_vsi);
3482                 return -EINVAL;
3483         }
3484
3485         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3486         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3487                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3488         else
3489                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3490
3491         if (pool == 0)
3492                 vsi = pf->main_vsi;
3493         else
3494                 vsi = pf->vmdq[pool - 1].vsi;
3495
3496         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3497         if (ret != I40E_SUCCESS) {
3498                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3499                 return -ENODEV;
3500         }
3501         return 0;
3502 }
3503
3504 /* Remove a MAC address, and update filters */
3505 static void
3506 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3507 {
3508         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3509         struct i40e_vsi *vsi;
3510         struct rte_eth_dev_data *data = dev->data;
3511         struct ether_addr *macaddr;
3512         int ret;
3513         uint32_t i;
3514         uint64_t pool_sel;
3515
3516         macaddr = &(data->mac_addrs[index]);
3517
3518         pool_sel = dev->data->mac_pool_sel[index];
3519
3520         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3521                 if (pool_sel & (1ULL << i)) {
3522                         if (i == 0)
3523                                 vsi = pf->main_vsi;
3524                         else {
3525                                 /* No VMDQ pool enabled or configured */
3526                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3527                                         (i > pf->nb_cfg_vmdq_vsi)) {
3528                                         PMD_DRV_LOG(ERR,
3529                                                 "No VMDQ pool enabled/configured");
3530                                         return;
3531                                 }
3532                                 vsi = pf->vmdq[i - 1].vsi;
3533                         }
3534                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3535
3536                         if (ret) {
3537                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3538                                 return;
3539                         }
3540                 }
3541         }
3542 }
3543
3544 /* Set perfect match or hash match of MAC and VLAN for a VF */
3545 static int
3546 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3547                  struct rte_eth_mac_filter *filter,
3548                  bool add)
3549 {
3550         struct i40e_hw *hw;
3551         struct i40e_mac_filter_info mac_filter;
3552         struct ether_addr old_mac;
3553         struct ether_addr *new_mac;
3554         struct i40e_pf_vf *vf = NULL;
3555         uint16_t vf_id;
3556         int ret;
3557
3558         if (pf == NULL) {
3559                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3560                 return -EINVAL;
3561         }
3562         hw = I40E_PF_TO_HW(pf);
3563
3564         if (filter == NULL) {
3565                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3566                 return -EINVAL;
3567         }
3568
3569         new_mac = &filter->mac_addr;
3570
3571         if (is_zero_ether_addr(new_mac)) {
3572                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3573                 return -EINVAL;
3574         }
3575
3576         vf_id = filter->dst_id;
3577
3578         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3579                 PMD_DRV_LOG(ERR, "Invalid argument.");
3580                 return -EINVAL;
3581         }
3582         vf = &pf->vfs[vf_id];
3583
3584         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3585                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3586                 return -EINVAL;
3587         }
3588
3589         if (add) {
3590                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3591                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3592                                 ETHER_ADDR_LEN);
3593                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3594                                  ETHER_ADDR_LEN);
3595
3596                 mac_filter.filter_type = filter->filter_type;
3597                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3598                 if (ret != I40E_SUCCESS) {
3599                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3600                         return -1;
3601                 }
3602                 ether_addr_copy(new_mac, &pf->dev_addr);
3603         } else {
3604                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3605                                 ETHER_ADDR_LEN);
3606                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3607                 if (ret != I40E_SUCCESS) {
3608                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3609                         return -1;
3610                 }
3611
3612                 /* Clear device address as it has been removed */
3613                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3614                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3615         }
3616
3617         return 0;
3618 }
3619
3620 /* MAC filter handle */
3621 static int
3622 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3623                 void *arg)
3624 {
3625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626         struct rte_eth_mac_filter *filter;
3627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3628         int ret = I40E_NOT_SUPPORTED;
3629
3630         filter = (struct rte_eth_mac_filter *)(arg);
3631
3632         switch (filter_op) {
3633         case RTE_ETH_FILTER_NOP:
3634                 ret = I40E_SUCCESS;
3635                 break;
3636         case RTE_ETH_FILTER_ADD:
3637                 i40e_pf_disable_irq0(hw);
3638                 if (filter->is_vf)
3639                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3640                 i40e_pf_enable_irq0(hw);
3641                 break;
3642         case RTE_ETH_FILTER_DELETE:
3643                 i40e_pf_disable_irq0(hw);
3644                 if (filter->is_vf)
3645                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3646                 i40e_pf_enable_irq0(hw);
3647                 break;
3648         default:
3649                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3650                 ret = I40E_ERR_PARAM;
3651                 break;
3652         }
3653
3654         return ret;
3655 }
3656
3657 static int
3658 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3659 {
3660         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3661         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3662         int ret;
3663
3664         if (!lut)
3665                 return -EINVAL;
3666
3667         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3668                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3669                                           lut, lut_size);
3670                 if (ret) {
3671                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3672                         return ret;
3673                 }
3674         } else {
3675                 uint32_t *lut_dw = (uint32_t *)lut;
3676                 uint16_t i, lut_size_dw = lut_size / 4;
3677
3678                 for (i = 0; i < lut_size_dw; i++)
3679                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3680         }
3681
3682         return 0;
3683 }
3684
3685 static int
3686 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3687 {
3688         struct i40e_pf *pf;
3689         struct i40e_hw *hw;
3690         int ret;
3691
3692         if (!vsi || !lut)
3693                 return -EINVAL;
3694
3695         pf = I40E_VSI_TO_PF(vsi);
3696         hw = I40E_VSI_TO_HW(vsi);
3697
3698         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3699                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3700                                           lut, lut_size);
3701                 if (ret) {
3702                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3703                         return ret;
3704                 }
3705         } else {
3706                 uint32_t *lut_dw = (uint32_t *)lut;
3707                 uint16_t i, lut_size_dw = lut_size / 4;
3708
3709                 for (i = 0; i < lut_size_dw; i++)
3710                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3711                 I40E_WRITE_FLUSH(hw);
3712         }
3713
3714         return 0;
3715 }
3716
3717 static int
3718 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3719                          struct rte_eth_rss_reta_entry64 *reta_conf,
3720                          uint16_t reta_size)
3721 {
3722         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3723         uint16_t i, lut_size = pf->hash_lut_size;
3724         uint16_t idx, shift;
3725         uint8_t *lut;
3726         int ret;
3727
3728         if (reta_size != lut_size ||
3729                 reta_size > ETH_RSS_RETA_SIZE_512) {
3730                 PMD_DRV_LOG(ERR,
3731                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3732                         reta_size, lut_size);
3733                 return -EINVAL;
3734         }
3735
3736         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3737         if (!lut) {
3738                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3739                 return -ENOMEM;
3740         }
3741         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3742         if (ret)
3743                 goto out;
3744         for (i = 0; i < reta_size; i++) {
3745                 idx = i / RTE_RETA_GROUP_SIZE;
3746                 shift = i % RTE_RETA_GROUP_SIZE;
3747                 if (reta_conf[idx].mask & (1ULL << shift))
3748                         lut[i] = reta_conf[idx].reta[shift];
3749         }
3750         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3751
3752 out:
3753         rte_free(lut);
3754
3755         return ret;
3756 }
3757
3758 static int
3759 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3760                         struct rte_eth_rss_reta_entry64 *reta_conf,
3761                         uint16_t reta_size)
3762 {
3763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764         uint16_t i, lut_size = pf->hash_lut_size;
3765         uint16_t idx, shift;
3766         uint8_t *lut;
3767         int ret;
3768
3769         if (reta_size != lut_size ||
3770                 reta_size > ETH_RSS_RETA_SIZE_512) {
3771                 PMD_DRV_LOG(ERR,
3772                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3773                         reta_size, lut_size);
3774                 return -EINVAL;
3775         }
3776
3777         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3778         if (!lut) {
3779                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3780                 return -ENOMEM;
3781         }
3782
3783         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3784         if (ret)
3785                 goto out;
3786         for (i = 0; i < reta_size; i++) {
3787                 idx = i / RTE_RETA_GROUP_SIZE;
3788                 shift = i % RTE_RETA_GROUP_SIZE;
3789                 if (reta_conf[idx].mask & (1ULL << shift))
3790                         reta_conf[idx].reta[shift] = lut[i];
3791         }
3792
3793 out:
3794         rte_free(lut);
3795
3796         return ret;
3797 }
3798
3799 /**
3800  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3801  * @hw:   pointer to the HW structure
3802  * @mem:  pointer to mem struct to fill out
3803  * @size: size of memory requested
3804  * @alignment: what to align the allocation to
3805  **/
3806 enum i40e_status_code
3807 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3808                         struct i40e_dma_mem *mem,
3809                         u64 size,
3810                         u32 alignment)
3811 {
3812         const struct rte_memzone *mz = NULL;
3813         char z_name[RTE_MEMZONE_NAMESIZE];
3814
3815         if (!mem)
3816                 return I40E_ERR_PARAM;
3817
3818         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3819         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3820                                          alignment, RTE_PGSIZE_2M);
3821         if (!mz)
3822                 return I40E_ERR_NO_MEMORY;
3823
3824         mem->size = size;
3825         mem->va = mz->addr;
3826         mem->pa = mz->iova;
3827         mem->zone = (const void *)mz;
3828         PMD_DRV_LOG(DEBUG,
3829                 "memzone %s allocated with physical address: %"PRIu64,
3830                 mz->name, mem->pa);
3831
3832         return I40E_SUCCESS;
3833 }
3834
3835 /**
3836  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3837  * @hw:   pointer to the HW structure
3838  * @mem:  ptr to mem struct to free
3839  **/
3840 enum i40e_status_code
3841 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3842                     struct i40e_dma_mem *mem)
3843 {
3844         if (!mem)
3845                 return I40E_ERR_PARAM;
3846
3847         PMD_DRV_LOG(DEBUG,
3848                 "memzone %s to be freed with physical address: %"PRIu64,
3849                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3850         rte_memzone_free((const struct rte_memzone *)mem->zone);
3851         mem->zone = NULL;
3852         mem->va = NULL;
3853         mem->pa = (u64)0;
3854
3855         return I40E_SUCCESS;
3856 }
3857
3858 /**
3859  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3860  * @hw:   pointer to the HW structure
3861  * @mem:  pointer to mem struct to fill out
3862  * @size: size of memory requested
3863  **/
3864 enum i40e_status_code
3865 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3866                          struct i40e_virt_mem *mem,
3867                          u32 size)
3868 {
3869         if (!mem)
3870                 return I40E_ERR_PARAM;
3871
3872         mem->size = size;
3873         mem->va = rte_zmalloc("i40e", size, 0);
3874
3875         if (mem->va)
3876                 return I40E_SUCCESS;
3877         else
3878                 return I40E_ERR_NO_MEMORY;
3879 }
3880
3881 /**
3882  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3883  * @hw:   pointer to the HW structure
3884  * @mem:  pointer to mem struct to free
3885  **/
3886 enum i40e_status_code
3887 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3888                      struct i40e_virt_mem *mem)
3889 {
3890         if (!mem)
3891                 return I40E_ERR_PARAM;
3892
3893         rte_free(mem->va);
3894         mem->va = NULL;
3895
3896         return I40E_SUCCESS;
3897 }
3898
3899 void
3900 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3901 {
3902         rte_spinlock_init(&sp->spinlock);
3903 }
3904
3905 void
3906 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3907 {
3908         rte_spinlock_lock(&sp->spinlock);
3909 }
3910
3911 void
3912 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3913 {
3914         rte_spinlock_unlock(&sp->spinlock);
3915 }
3916
3917 void
3918 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3919 {
3920         return;
3921 }
3922
3923 /**
3924  * Get the hardware capabilities, which will be parsed
3925  * and saved into struct i40e_hw.
3926  */
3927 static int
3928 i40e_get_cap(struct i40e_hw *hw)
3929 {
3930         struct i40e_aqc_list_capabilities_element_resp *buf;
3931         uint16_t len, size = 0;
3932         int ret;
3933
3934         /* Calculate a huge enough buff for saving response data temporarily */
3935         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3936                                                 I40E_MAX_CAP_ELE_NUM;
3937         buf = rte_zmalloc("i40e", len, 0);
3938         if (!buf) {
3939                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3940                 return I40E_ERR_NO_MEMORY;
3941         }
3942
3943         /* Get, parse the capabilities and save it to hw */
3944         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3945                         i40e_aqc_opc_list_func_capabilities, NULL);
3946         if (ret != I40E_SUCCESS)
3947                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3948
3949         /* Free the temporary buffer after being used */
3950         rte_free(buf);
3951
3952         return ret;
3953 }
3954
3955 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
3956 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
3957 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
3958
3959 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
3960                 const char *value,
3961                 void *opaque)
3962 {
3963         struct i40e_pf *pf;
3964         unsigned long num;
3965         char *end;
3966
3967         pf = (struct i40e_pf *)opaque;
3968         RTE_SET_USED(key);
3969
3970         errno = 0;
3971         num = strtoul(value, &end, 0);
3972         if (errno != 0 || end == value || *end != 0) {
3973                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
3974                             "kept the value = %hu", value, pf->vf_nb_qp_max);
3975                 return -(EINVAL);
3976         }
3977
3978         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
3979                 pf->vf_nb_qp_max = (uint16_t)num;
3980         else
3981                 /* here return 0 to make next valid same argument work */
3982                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
3983                             "power of 2 and equal or less than 16 !, Now it is "
3984                             "kept the value = %hu", num, pf->vf_nb_qp_max);
3985
3986         return 0;
3987 }
3988
3989 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
3990 {
3991         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
3992         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3993         struct rte_kvargs *kvlist;
3994
3995         /* set default queue number per VF as 4 */
3996         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3997
3998         if (dev->device->devargs == NULL)
3999                 return 0;
4000
4001         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4002         if (kvlist == NULL)
4003                 return -(EINVAL);
4004
4005         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4006                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4007                             "the first invalid or last valid one is used !",
4008                             QUEUE_NUM_PER_VF_ARG);
4009
4010         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4011                            i40e_pf_parse_vf_queue_number_handler, pf);
4012
4013         rte_kvargs_free(kvlist);
4014
4015         return 0;
4016 }
4017
4018 static int
4019 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4020 {
4021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4022         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4024         uint16_t qp_count = 0, vsi_count = 0;
4025
4026         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4027                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4028                 return -EINVAL;
4029         }
4030
4031         i40e_pf_config_vf_rxq_number(dev);
4032
4033         /* Add the parameter init for LFC */
4034         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4035         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4036         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4037
4038         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4039         pf->max_num_vsi = hw->func_caps.num_vsis;
4040         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4041         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4042
4043         /* FDir queue/VSI allocation */
4044         pf->fdir_qp_offset = 0;
4045         if (hw->func_caps.fd) {
4046                 pf->flags |= I40E_FLAG_FDIR;
4047                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4048         } else {
4049                 pf->fdir_nb_qps = 0;
4050         }
4051         qp_count += pf->fdir_nb_qps;
4052         vsi_count += 1;
4053
4054         /* LAN queue/VSI allocation */
4055         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4056         if (!hw->func_caps.rss) {
4057                 pf->lan_nb_qps = 1;
4058         } else {
4059                 pf->flags |= I40E_FLAG_RSS;
4060                 if (hw->mac.type == I40E_MAC_X722)
4061                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4062                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4063         }
4064         qp_count += pf->lan_nb_qps;
4065         vsi_count += 1;
4066
4067         /* VF queue/VSI allocation */
4068         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4069         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4070                 pf->flags |= I40E_FLAG_SRIOV;
4071                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4072                 pf->vf_num = pci_dev->max_vfs;
4073                 PMD_DRV_LOG(DEBUG,
4074                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4075                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4076         } else {
4077                 pf->vf_nb_qps = 0;
4078                 pf->vf_num = 0;
4079         }
4080         qp_count += pf->vf_nb_qps * pf->vf_num;
4081         vsi_count += pf->vf_num;
4082
4083         /* VMDq queue/VSI allocation */
4084         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4085         pf->vmdq_nb_qps = 0;
4086         pf->max_nb_vmdq_vsi = 0;
4087         if (hw->func_caps.vmdq) {
4088                 if (qp_count < hw->func_caps.num_tx_qp &&
4089                         vsi_count < hw->func_caps.num_vsis) {
4090                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4091                                 qp_count) / pf->vmdq_nb_qp_max;
4092
4093                         /* Limit the maximum number of VMDq vsi to the maximum
4094                          * ethdev can support
4095                          */
4096                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4097                                 hw->func_caps.num_vsis - vsi_count);
4098                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4099                                 ETH_64_POOLS);
4100                         if (pf->max_nb_vmdq_vsi) {
4101                                 pf->flags |= I40E_FLAG_VMDQ;
4102                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4103                                 PMD_DRV_LOG(DEBUG,
4104                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4105                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4106                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4107                         } else {
4108                                 PMD_DRV_LOG(INFO,
4109                                         "No enough queues left for VMDq");
4110                         }
4111                 } else {
4112                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4113                 }
4114         }
4115         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4116         vsi_count += pf->max_nb_vmdq_vsi;
4117
4118         if (hw->func_caps.dcb)
4119                 pf->flags |= I40E_FLAG_DCB;
4120
4121         if (qp_count > hw->func_caps.num_tx_qp) {
4122                 PMD_DRV_LOG(ERR,
4123                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4124                         qp_count, hw->func_caps.num_tx_qp);
4125                 return -EINVAL;
4126         }
4127         if (vsi_count > hw->func_caps.num_vsis) {
4128                 PMD_DRV_LOG(ERR,
4129                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4130                         vsi_count, hw->func_caps.num_vsis);
4131                 return -EINVAL;
4132         }
4133
4134         return 0;
4135 }
4136
4137 static int
4138 i40e_pf_get_switch_config(struct i40e_pf *pf)
4139 {
4140         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4141         struct i40e_aqc_get_switch_config_resp *switch_config;
4142         struct i40e_aqc_switch_config_element_resp *element;
4143         uint16_t start_seid = 0, num_reported;
4144         int ret;
4145
4146         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4147                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4148         if (!switch_config) {
4149                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4150                 return -ENOMEM;
4151         }
4152
4153         /* Get the switch configurations */
4154         ret = i40e_aq_get_switch_config(hw, switch_config,
4155                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4156         if (ret != I40E_SUCCESS) {
4157                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4158                 goto fail;
4159         }
4160         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4161         if (num_reported != 1) { /* The number should be 1 */
4162                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4163                 goto fail;
4164         }
4165
4166         /* Parse the switch configuration elements */
4167         element = &(switch_config->element[0]);
4168         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4169                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4170                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4171         } else
4172                 PMD_DRV_LOG(INFO, "Unknown element type");
4173
4174 fail:
4175         rte_free(switch_config);
4176
4177         return ret;
4178 }
4179
4180 static int
4181 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4182                         uint32_t num)
4183 {
4184         struct pool_entry *entry;
4185
4186         if (pool == NULL || num == 0)
4187                 return -EINVAL;
4188
4189         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4190         if (entry == NULL) {
4191                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4192                 return -ENOMEM;
4193         }
4194
4195         /* queue heap initialize */
4196         pool->num_free = num;
4197         pool->num_alloc = 0;
4198         pool->base = base;
4199         LIST_INIT(&pool->alloc_list);
4200         LIST_INIT(&pool->free_list);
4201
4202         /* Initialize element  */
4203         entry->base = 0;
4204         entry->len = num;
4205
4206         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4207         return 0;
4208 }
4209
4210 static void
4211 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4212 {
4213         struct pool_entry *entry, *next_entry;
4214
4215         if (pool == NULL)
4216                 return;
4217
4218         for (entry = LIST_FIRST(&pool->alloc_list);
4219                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4220                         entry = next_entry) {
4221                 LIST_REMOVE(entry, next);
4222                 rte_free(entry);
4223         }
4224
4225         for (entry = LIST_FIRST(&pool->free_list);
4226                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4227                         entry = next_entry) {
4228                 LIST_REMOVE(entry, next);
4229                 rte_free(entry);
4230         }
4231
4232         pool->num_free = 0;
4233         pool->num_alloc = 0;
4234         pool->base = 0;
4235         LIST_INIT(&pool->alloc_list);
4236         LIST_INIT(&pool->free_list);
4237 }
4238
4239 static int
4240 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4241                        uint32_t base)
4242 {
4243         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4244         uint32_t pool_offset;
4245         int insert;
4246
4247         if (pool == NULL) {
4248                 PMD_DRV_LOG(ERR, "Invalid parameter");
4249                 return -EINVAL;
4250         }
4251
4252         pool_offset = base - pool->base;
4253         /* Lookup in alloc list */
4254         LIST_FOREACH(entry, &pool->alloc_list, next) {
4255                 if (entry->base == pool_offset) {
4256                         valid_entry = entry;
4257                         LIST_REMOVE(entry, next);
4258                         break;
4259                 }
4260         }
4261
4262         /* Not find, return */
4263         if (valid_entry == NULL) {
4264                 PMD_DRV_LOG(ERR, "Failed to find entry");
4265                 return -EINVAL;
4266         }
4267
4268         /**
4269          * Found it, move it to free list  and try to merge.
4270          * In order to make merge easier, always sort it by qbase.
4271          * Find adjacent prev and last entries.
4272          */
4273         prev = next = NULL;
4274         LIST_FOREACH(entry, &pool->free_list, next) {
4275                 if (entry->base > valid_entry->base) {
4276                         next = entry;
4277                         break;
4278                 }
4279                 prev = entry;
4280         }
4281
4282         insert = 0;
4283         /* Try to merge with next one*/
4284         if (next != NULL) {
4285                 /* Merge with next one */
4286                 if (valid_entry->base + valid_entry->len == next->base) {
4287                         next->base = valid_entry->base;
4288                         next->len += valid_entry->len;
4289                         rte_free(valid_entry);
4290                         valid_entry = next;
4291                         insert = 1;
4292                 }
4293         }
4294
4295         if (prev != NULL) {
4296                 /* Merge with previous one */
4297                 if (prev->base + prev->len == valid_entry->base) {
4298                         prev->len += valid_entry->len;
4299                         /* If it merge with next one, remove next node */
4300                         if (insert == 1) {
4301                                 LIST_REMOVE(valid_entry, next);
4302                                 rte_free(valid_entry);
4303                         } else {
4304                                 rte_free(valid_entry);
4305                                 insert = 1;
4306                         }
4307                 }
4308         }
4309
4310         /* Not find any entry to merge, insert */
4311         if (insert == 0) {
4312                 if (prev != NULL)
4313                         LIST_INSERT_AFTER(prev, valid_entry, next);
4314                 else if (next != NULL)
4315                         LIST_INSERT_BEFORE(next, valid_entry, next);
4316                 else /* It's empty list, insert to head */
4317                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4318         }
4319
4320         pool->num_free += valid_entry->len;
4321         pool->num_alloc -= valid_entry->len;
4322
4323         return 0;
4324 }
4325
4326 static int
4327 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4328                        uint16_t num)
4329 {
4330         struct pool_entry *entry, *valid_entry;
4331
4332         if (pool == NULL || num == 0) {
4333                 PMD_DRV_LOG(ERR, "Invalid parameter");
4334                 return -EINVAL;
4335         }
4336
4337         if (pool->num_free < num) {
4338                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4339                             num, pool->num_free);
4340                 return -ENOMEM;
4341         }
4342
4343         valid_entry = NULL;
4344         /* Lookup  in free list and find most fit one */
4345         LIST_FOREACH(entry, &pool->free_list, next) {
4346                 if (entry->len >= num) {
4347                         /* Find best one */
4348                         if (entry->len == num) {
4349                                 valid_entry = entry;
4350                                 break;
4351                         }
4352                         if (valid_entry == NULL || valid_entry->len > entry->len)
4353                                 valid_entry = entry;
4354                 }
4355         }
4356
4357         /* Not find one to satisfy the request, return */
4358         if (valid_entry == NULL) {
4359                 PMD_DRV_LOG(ERR, "No valid entry found");
4360                 return -ENOMEM;
4361         }
4362         /**
4363          * The entry have equal queue number as requested,
4364          * remove it from alloc_list.
4365          */
4366         if (valid_entry->len == num) {
4367                 LIST_REMOVE(valid_entry, next);
4368         } else {
4369                 /**
4370                  * The entry have more numbers than requested,
4371                  * create a new entry for alloc_list and minus its
4372                  * queue base and number in free_list.
4373                  */
4374                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4375                 if (entry == NULL) {
4376                         PMD_DRV_LOG(ERR,
4377                                 "Failed to allocate memory for resource pool");
4378                         return -ENOMEM;
4379                 }
4380                 entry->base = valid_entry->base;
4381                 entry->len = num;
4382                 valid_entry->base += num;
4383                 valid_entry->len -= num;
4384                 valid_entry = entry;
4385         }
4386
4387         /* Insert it into alloc list, not sorted */
4388         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4389
4390         pool->num_free -= valid_entry->len;
4391         pool->num_alloc += valid_entry->len;
4392
4393         return valid_entry->base + pool->base;
4394 }
4395
4396 /**
4397  * bitmap_is_subset - Check whether src2 is subset of src1
4398  **/
4399 static inline int
4400 bitmap_is_subset(uint8_t src1, uint8_t src2)
4401 {
4402         return !((src1 ^ src2) & src2);
4403 }
4404
4405 static enum i40e_status_code
4406 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4407 {
4408         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4409
4410         /* If DCB is not supported, only default TC is supported */
4411         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4412                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4413                 return I40E_NOT_SUPPORTED;
4414         }
4415
4416         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4417                 PMD_DRV_LOG(ERR,
4418                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4419                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4420                 return I40E_NOT_SUPPORTED;
4421         }
4422         return I40E_SUCCESS;
4423 }
4424
4425 int
4426 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4427                                 struct i40e_vsi_vlan_pvid_info *info)
4428 {
4429         struct i40e_hw *hw;
4430         struct i40e_vsi_context ctxt;
4431         uint8_t vlan_flags = 0;
4432         int ret;
4433
4434         if (vsi == NULL || info == NULL) {
4435                 PMD_DRV_LOG(ERR, "invalid parameters");
4436                 return I40E_ERR_PARAM;
4437         }
4438
4439         if (info->on) {
4440                 vsi->info.pvid = info->config.pvid;
4441                 /**
4442                  * If insert pvid is enabled, only tagged pkts are
4443                  * allowed to be sent out.
4444                  */
4445                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4446                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4447         } else {
4448                 vsi->info.pvid = 0;
4449                 if (info->config.reject.tagged == 0)
4450                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4451
4452                 if (info->config.reject.untagged == 0)
4453                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4454         }
4455         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4456                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4457         vsi->info.port_vlan_flags |= vlan_flags;
4458         vsi->info.valid_sections =
4459                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4460         memset(&ctxt, 0, sizeof(ctxt));
4461         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4462         ctxt.seid = vsi->seid;
4463
4464         hw = I40E_VSI_TO_HW(vsi);
4465         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4466         if (ret != I40E_SUCCESS)
4467                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4468
4469         return ret;
4470 }
4471
4472 static int
4473 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4474 {
4475         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4476         int i, ret;
4477         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4478
4479         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4480         if (ret != I40E_SUCCESS)
4481                 return ret;
4482
4483         if (!vsi->seid) {
4484                 PMD_DRV_LOG(ERR, "seid not valid");
4485                 return -EINVAL;
4486         }
4487
4488         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4489         tc_bw_data.tc_valid_bits = enabled_tcmap;
4490         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4491                 tc_bw_data.tc_bw_credits[i] =
4492                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4493
4494         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4495         if (ret != I40E_SUCCESS) {
4496                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4497                 return ret;
4498         }
4499
4500         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4501                                         sizeof(vsi->info.qs_handle));
4502         return I40E_SUCCESS;
4503 }
4504
4505 static enum i40e_status_code
4506 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4507                                  struct i40e_aqc_vsi_properties_data *info,
4508                                  uint8_t enabled_tcmap)
4509 {
4510         enum i40e_status_code ret;
4511         int i, total_tc = 0;
4512         uint16_t qpnum_per_tc, bsf, qp_idx;
4513
4514         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4515         if (ret != I40E_SUCCESS)
4516                 return ret;
4517
4518         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4519                 if (enabled_tcmap & (1 << i))
4520                         total_tc++;
4521         if (total_tc == 0)
4522                 total_tc = 1;
4523         vsi->enabled_tc = enabled_tcmap;
4524
4525         /* Number of queues per enabled TC */
4526         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4527         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4528         bsf = rte_bsf32(qpnum_per_tc);
4529
4530         /* Adjust the queue number to actual queues that can be applied */
4531         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4532                 vsi->nb_qps = qpnum_per_tc * total_tc;
4533
4534         /**
4535          * Configure TC and queue mapping parameters, for enabled TC,
4536          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4537          * default queue will serve it.
4538          */
4539         qp_idx = 0;
4540         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4541                 if (vsi->enabled_tc & (1 << i)) {
4542                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4543                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4544                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4545                         qp_idx += qpnum_per_tc;
4546                 } else
4547                         info->tc_mapping[i] = 0;
4548         }
4549
4550         /* Associate queue number with VSI */
4551         if (vsi->type == I40E_VSI_SRIOV) {
4552                 info->mapping_flags |=
4553                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4554                 for (i = 0; i < vsi->nb_qps; i++)
4555                         info->queue_mapping[i] =
4556                                 rte_cpu_to_le_16(vsi->base_queue + i);
4557         } else {
4558                 info->mapping_flags |=
4559                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4560                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4561         }
4562         info->valid_sections |=
4563                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4564
4565         return I40E_SUCCESS;
4566 }
4567
4568 static int
4569 i40e_veb_release(struct i40e_veb *veb)
4570 {
4571         struct i40e_vsi *vsi;
4572         struct i40e_hw *hw;
4573
4574         if (veb == NULL)
4575                 return -EINVAL;
4576
4577         if (!TAILQ_EMPTY(&veb->head)) {
4578                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4579                 return -EACCES;
4580         }
4581         /* associate_vsi field is NULL for floating VEB */
4582         if (veb->associate_vsi != NULL) {
4583                 vsi = veb->associate_vsi;
4584                 hw = I40E_VSI_TO_HW(vsi);
4585
4586                 vsi->uplink_seid = veb->uplink_seid;
4587                 vsi->veb = NULL;
4588         } else {
4589                 veb->associate_pf->main_vsi->floating_veb = NULL;
4590                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4591         }
4592
4593         i40e_aq_delete_element(hw, veb->seid, NULL);
4594         rte_free(veb);
4595         return I40E_SUCCESS;
4596 }
4597
4598 /* Setup a veb */
4599 static struct i40e_veb *
4600 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4601 {
4602         struct i40e_veb *veb;
4603         int ret;
4604         struct i40e_hw *hw;
4605
4606         if (pf == NULL) {
4607                 PMD_DRV_LOG(ERR,
4608                             "veb setup failed, associated PF shouldn't null");
4609                 return NULL;
4610         }
4611         hw = I40E_PF_TO_HW(pf);
4612
4613         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4614         if (!veb) {
4615                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4616                 goto fail;
4617         }
4618
4619         veb->associate_vsi = vsi;
4620         veb->associate_pf = pf;
4621         TAILQ_INIT(&veb->head);
4622         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4623
4624         /* create floating veb if vsi is NULL */
4625         if (vsi != NULL) {
4626                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4627                                       I40E_DEFAULT_TCMAP, false,
4628                                       &veb->seid, false, NULL);
4629         } else {
4630                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4631                                       true, &veb->seid, false, NULL);
4632         }
4633
4634         if (ret != I40E_SUCCESS) {
4635                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4636                             hw->aq.asq_last_status);
4637                 goto fail;
4638         }
4639         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4640
4641         /* get statistics index */
4642         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4643                                 &veb->stats_idx, NULL, NULL, NULL);
4644         if (ret != I40E_SUCCESS) {
4645                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4646                             hw->aq.asq_last_status);
4647                 goto fail;
4648         }
4649         /* Get VEB bandwidth, to be implemented */
4650         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4651         if (vsi)
4652                 vsi->uplink_seid = veb->seid;
4653
4654         return veb;
4655 fail:
4656         rte_free(veb);
4657         return NULL;
4658 }
4659
4660 int
4661 i40e_vsi_release(struct i40e_vsi *vsi)
4662 {
4663         struct i40e_pf *pf;
4664         struct i40e_hw *hw;
4665         struct i40e_vsi_list *vsi_list;
4666         void *temp;
4667         int ret;
4668         struct i40e_mac_filter *f;
4669         uint16_t user_param;
4670
4671         if (!vsi)
4672                 return I40E_SUCCESS;
4673
4674         if (!vsi->adapter)
4675                 return -EFAULT;
4676
4677         user_param = vsi->user_param;
4678
4679         pf = I40E_VSI_TO_PF(vsi);
4680         hw = I40E_VSI_TO_HW(vsi);
4681
4682         /* VSI has child to attach, release child first */
4683         if (vsi->veb) {
4684                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4685                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4686                                 return -1;
4687                 }
4688                 i40e_veb_release(vsi->veb);
4689         }
4690
4691         if (vsi->floating_veb) {
4692                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4693                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4694                                 return -1;
4695                 }
4696         }
4697
4698         /* Remove all macvlan filters of the VSI */
4699         i40e_vsi_remove_all_macvlan_filter(vsi);
4700         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4701                 rte_free(f);
4702
4703         if (vsi->type != I40E_VSI_MAIN &&
4704             ((vsi->type != I40E_VSI_SRIOV) ||
4705             !pf->floating_veb_list[user_param])) {
4706                 /* Remove vsi from parent's sibling list */
4707                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4708                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4709                         return I40E_ERR_PARAM;
4710                 }
4711                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4712                                 &vsi->sib_vsi_list, list);
4713
4714                 /* Remove all switch element of the VSI */
4715                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4716                 if (ret != I40E_SUCCESS)
4717                         PMD_DRV_LOG(ERR, "Failed to delete element");
4718         }
4719
4720         if ((vsi->type == I40E_VSI_SRIOV) &&
4721             pf->floating_veb_list[user_param]) {
4722                 /* Remove vsi from parent's sibling list */
4723                 if (vsi->parent_vsi == NULL ||
4724                     vsi->parent_vsi->floating_veb == NULL) {
4725                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4726                         return I40E_ERR_PARAM;
4727                 }
4728                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4729                              &vsi->sib_vsi_list, list);
4730
4731                 /* Remove all switch element of the VSI */
4732                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4733                 if (ret != I40E_SUCCESS)
4734                         PMD_DRV_LOG(ERR, "Failed to delete element");
4735         }
4736
4737         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4738
4739         if (vsi->type != I40E_VSI_SRIOV)
4740                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4741         rte_free(vsi);
4742
4743         return I40E_SUCCESS;
4744 }
4745
4746 static int
4747 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4748 {
4749         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4750         struct i40e_aqc_remove_macvlan_element_data def_filter;
4751         struct i40e_mac_filter_info filter;
4752         int ret;
4753
4754         if (vsi->type != I40E_VSI_MAIN)
4755                 return I40E_ERR_CONFIG;
4756         memset(&def_filter, 0, sizeof(def_filter));
4757         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4758                                         ETH_ADDR_LEN);
4759         def_filter.vlan_tag = 0;
4760         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4761                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4762         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4763         if (ret != I40E_SUCCESS) {
4764                 struct i40e_mac_filter *f;
4765                 struct ether_addr *mac;
4766
4767                 PMD_DRV_LOG(DEBUG,
4768                             "Cannot remove the default macvlan filter");
4769                 /* It needs to add the permanent mac into mac list */
4770                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4771                 if (f == NULL) {
4772                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4773                         return I40E_ERR_NO_MEMORY;
4774                 }
4775                 mac = &f->mac_info.mac_addr;
4776                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4777                                 ETH_ADDR_LEN);
4778                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4779                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4780                 vsi->mac_num++;
4781
4782                 return ret;
4783         }
4784         rte_memcpy(&filter.mac_addr,
4785                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4786         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4787         return i40e_vsi_add_mac(vsi, &filter);
4788 }
4789
4790 /*
4791  * i40e_vsi_get_bw_config - Query VSI BW Information
4792  * @vsi: the VSI to be queried
4793  *
4794  * Returns 0 on success, negative value on failure
4795  */
4796 static enum i40e_status_code
4797 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4798 {
4799         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4800         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4801         struct i40e_hw *hw = &vsi->adapter->hw;
4802         i40e_status ret;
4803         int i;
4804         uint32_t bw_max;
4805
4806         memset(&bw_config, 0, sizeof(bw_config));
4807         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4808         if (ret != I40E_SUCCESS) {
4809                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4810                             hw->aq.asq_last_status);
4811                 return ret;
4812         }
4813
4814         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4815         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4816                                         &ets_sla_config, NULL);
4817         if (ret != I40E_SUCCESS) {
4818                 PMD_DRV_LOG(ERR,
4819                         "VSI failed to get TC bandwdith configuration %u",
4820                         hw->aq.asq_last_status);
4821                 return ret;
4822         }
4823
4824         /* store and print out BW info */
4825         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4826         vsi->bw_info.bw_max = bw_config.max_bw;
4827         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4828         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4829         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4830                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4831                      I40E_16_BIT_WIDTH);
4832         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4833                 vsi->bw_info.bw_ets_share_credits[i] =
4834                                 ets_sla_config.share_credits[i];
4835                 vsi->bw_info.bw_ets_credits[i] =
4836                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4837                 /* 4 bits per TC, 4th bit is reserved */
4838                 vsi->bw_info.bw_ets_max[i] =
4839                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4840                                   RTE_LEN2MASK(3, uint8_t));
4841                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4842                             vsi->bw_info.bw_ets_share_credits[i]);
4843                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4844                             vsi->bw_info.bw_ets_credits[i]);
4845                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4846                             vsi->bw_info.bw_ets_max[i]);
4847         }
4848
4849         return I40E_SUCCESS;
4850 }
4851
4852 /* i40e_enable_pf_lb
4853  * @pf: pointer to the pf structure
4854  *
4855  * allow loopback on pf
4856  */
4857 static inline void
4858 i40e_enable_pf_lb(struct i40e_pf *pf)
4859 {
4860         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4861         struct i40e_vsi_context ctxt;
4862         int ret;
4863
4864         /* Use the FW API if FW >= v5.0 */
4865         if (hw->aq.fw_maj_ver < 5) {
4866                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4867                 return;
4868         }
4869
4870         memset(&ctxt, 0, sizeof(ctxt));
4871         ctxt.seid = pf->main_vsi_seid;
4872         ctxt.pf_num = hw->pf_id;
4873         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4874         if (ret) {
4875                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4876                             ret, hw->aq.asq_last_status);
4877                 return;
4878         }
4879         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4880         ctxt.info.valid_sections =
4881                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4882         ctxt.info.switch_id |=
4883                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4884
4885         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4886         if (ret)
4887                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4888                             hw->aq.asq_last_status);
4889 }
4890
4891 /* Setup a VSI */
4892 struct i40e_vsi *
4893 i40e_vsi_setup(struct i40e_pf *pf,
4894                enum i40e_vsi_type type,
4895                struct i40e_vsi *uplink_vsi,
4896                uint16_t user_param)
4897 {
4898         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4899         struct i40e_vsi *vsi;
4900         struct i40e_mac_filter_info filter;
4901         int ret;
4902         struct i40e_vsi_context ctxt;
4903         struct ether_addr broadcast =
4904                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4905
4906         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4907             uplink_vsi == NULL) {
4908                 PMD_DRV_LOG(ERR,
4909                         "VSI setup failed, VSI link shouldn't be NULL");
4910                 return NULL;
4911         }
4912
4913         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4914                 PMD_DRV_LOG(ERR,
4915                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4916                 return NULL;
4917         }
4918
4919         /* two situations
4920          * 1.type is not MAIN and uplink vsi is not NULL
4921          * If uplink vsi didn't setup VEB, create one first under veb field
4922          * 2.type is SRIOV and the uplink is NULL
4923          * If floating VEB is NULL, create one veb under floating veb field
4924          */
4925
4926         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4927             uplink_vsi->veb == NULL) {
4928                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4929
4930                 if (uplink_vsi->veb == NULL) {
4931                         PMD_DRV_LOG(ERR, "VEB setup failed");
4932                         return NULL;
4933                 }
4934                 /* set ALLOWLOOPBACk on pf, when veb is created */
4935                 i40e_enable_pf_lb(pf);
4936         }
4937
4938         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4939             pf->main_vsi->floating_veb == NULL) {
4940                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4941
4942                 if (pf->main_vsi->floating_veb == NULL) {
4943                         PMD_DRV_LOG(ERR, "VEB setup failed");
4944                         return NULL;
4945                 }
4946         }
4947
4948         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4949         if (!vsi) {
4950                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4951                 return NULL;
4952         }
4953         TAILQ_INIT(&vsi->mac_list);
4954         vsi->type = type;
4955         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4956         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4957         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4958         vsi->user_param = user_param;
4959         vsi->vlan_anti_spoof_on = 0;
4960         vsi->vlan_filter_on = 0;
4961         /* Allocate queues */
4962         switch (vsi->type) {
4963         case I40E_VSI_MAIN  :
4964                 vsi->nb_qps = pf->lan_nb_qps;
4965                 break;
4966         case I40E_VSI_SRIOV :
4967                 vsi->nb_qps = pf->vf_nb_qps;
4968                 break;
4969         case I40E_VSI_VMDQ2:
4970                 vsi->nb_qps = pf->vmdq_nb_qps;
4971                 break;
4972         case I40E_VSI_FDIR:
4973                 vsi->nb_qps = pf->fdir_nb_qps;
4974                 break;
4975         default:
4976                 goto fail_mem;
4977         }
4978         /*
4979          * The filter status descriptor is reported in rx queue 0,
4980          * while the tx queue for fdir filter programming has no
4981          * such constraints, can be non-zero queues.
4982          * To simplify it, choose FDIR vsi use queue 0 pair.
4983          * To make sure it will use queue 0 pair, queue allocation
4984          * need be done before this function is called
4985          */
4986         if (type != I40E_VSI_FDIR) {
4987                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4988                         if (ret < 0) {
4989                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4990                                                 vsi->seid, ret);
4991                                 goto fail_mem;
4992                         }
4993                         vsi->base_queue = ret;
4994         } else
4995                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4996
4997         /* VF has MSIX interrupt in VF range, don't allocate here */
4998         if (type == I40E_VSI_MAIN) {
4999                 ret = i40e_res_pool_alloc(&pf->msix_pool,
5000                                           RTE_MIN(vsi->nb_qps,
5001                                                   RTE_MAX_RXTX_INTR_VEC_ID));
5002                 if (ret < 0) {
5003                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5004                                     vsi->seid, ret);
5005                         goto fail_queue_alloc;
5006                 }
5007                 vsi->msix_intr = ret;
5008                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5009         } else if (type != I40E_VSI_SRIOV) {
5010                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5011                 if (ret < 0) {
5012                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5013                         goto fail_queue_alloc;
5014                 }
5015                 vsi->msix_intr = ret;
5016                 vsi->nb_msix = 1;
5017         } else {
5018                 vsi->msix_intr = 0;
5019                 vsi->nb_msix = 0;
5020         }
5021
5022         /* Add VSI */
5023         if (type == I40E_VSI_MAIN) {
5024                 /* For main VSI, no need to add since it's default one */
5025                 vsi->uplink_seid = pf->mac_seid;
5026                 vsi->seid = pf->main_vsi_seid;
5027                 /* Bind queues with specific MSIX interrupt */
5028                 /**
5029                  * Needs 2 interrupt at least, one for misc cause which will
5030                  * enabled from OS side, Another for queues binding the
5031                  * interrupt from device side only.
5032                  */
5033
5034                 /* Get default VSI parameters from hardware */
5035                 memset(&ctxt, 0, sizeof(ctxt));
5036                 ctxt.seid = vsi->seid;
5037                 ctxt.pf_num = hw->pf_id;
5038                 ctxt.uplink_seid = vsi->uplink_seid;
5039                 ctxt.vf_num = 0;
5040                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5041                 if (ret != I40E_SUCCESS) {
5042                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5043                         goto fail_msix_alloc;
5044                 }
5045                 rte_memcpy(&vsi->info, &ctxt.info,
5046                         sizeof(struct i40e_aqc_vsi_properties_data));
5047                 vsi->vsi_id = ctxt.vsi_number;
5048                 vsi->info.valid_sections = 0;
5049
5050                 /* Configure tc, enabled TC0 only */
5051                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5052                         I40E_SUCCESS) {
5053                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5054                         goto fail_msix_alloc;
5055                 }
5056
5057                 /* TC, queue mapping */
5058                 memset(&ctxt, 0, sizeof(ctxt));
5059                 vsi->info.valid_sections |=
5060                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5061                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5062                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5063                 rte_memcpy(&ctxt.info, &vsi->info,
5064                         sizeof(struct i40e_aqc_vsi_properties_data));
5065                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5066                                                 I40E_DEFAULT_TCMAP);
5067                 if (ret != I40E_SUCCESS) {
5068                         PMD_DRV_LOG(ERR,
5069                                 "Failed to configure TC queue mapping");
5070                         goto fail_msix_alloc;
5071                 }
5072                 ctxt.seid = vsi->seid;
5073                 ctxt.pf_num = hw->pf_id;
5074                 ctxt.uplink_seid = vsi->uplink_seid;
5075                 ctxt.vf_num = 0;
5076
5077                 /* Update VSI parameters */
5078                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5079                 if (ret != I40E_SUCCESS) {
5080                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5081                         goto fail_msix_alloc;
5082                 }
5083
5084                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5085                                                 sizeof(vsi->info.tc_mapping));
5086                 rte_memcpy(&vsi->info.queue_mapping,
5087                                 &ctxt.info.queue_mapping,
5088                         sizeof(vsi->info.queue_mapping));
5089                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5090                 vsi->info.valid_sections = 0;
5091
5092                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5093                                 ETH_ADDR_LEN);
5094
5095                 /**
5096                  * Updating default filter settings are necessary to prevent
5097                  * reception of tagged packets.
5098                  * Some old firmware configurations load a default macvlan
5099                  * filter which accepts both tagged and untagged packets.
5100                  * The updating is to use a normal filter instead if needed.
5101                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5102                  * The firmware with correct configurations load the default
5103                  * macvlan filter which is expected and cannot be removed.
5104                  */
5105                 i40e_update_default_filter_setting(vsi);
5106                 i40e_config_qinq(hw, vsi);
5107         } else if (type == I40E_VSI_SRIOV) {
5108                 memset(&ctxt, 0, sizeof(ctxt));
5109                 /**
5110                  * For other VSI, the uplink_seid equals to uplink VSI's
5111                  * uplink_seid since they share same VEB
5112                  */
5113                 if (uplink_vsi == NULL)
5114                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5115                 else
5116                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5117                 ctxt.pf_num = hw->pf_id;
5118                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5119                 ctxt.uplink_seid = vsi->uplink_seid;
5120                 ctxt.connection_type = 0x1;
5121                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5122
5123                 /* Use the VEB configuration if FW >= v5.0 */
5124                 if (hw->aq.fw_maj_ver >= 5) {
5125                         /* Configure switch ID */
5126                         ctxt.info.valid_sections |=
5127                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5128                         ctxt.info.switch_id =
5129                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5130                 }
5131
5132                 /* Configure port/vlan */
5133                 ctxt.info.valid_sections |=
5134                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5135                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5136                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5137                                                 hw->func_caps.enabled_tcmap);
5138                 if (ret != I40E_SUCCESS) {
5139                         PMD_DRV_LOG(ERR,
5140                                 "Failed to configure TC queue mapping");
5141                         goto fail_msix_alloc;
5142                 }
5143
5144                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5145                 ctxt.info.valid_sections |=
5146                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5147                 /**
5148                  * Since VSI is not created yet, only configure parameter,
5149                  * will add vsi below.
5150                  */
5151
5152                 i40e_config_qinq(hw, vsi);
5153         } else if (type == I40E_VSI_VMDQ2) {
5154                 memset(&ctxt, 0, sizeof(ctxt));
5155                 /*
5156                  * For other VSI, the uplink_seid equals to uplink VSI's
5157                  * uplink_seid since they share same VEB
5158                  */
5159                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5160                 ctxt.pf_num = hw->pf_id;
5161                 ctxt.vf_num = 0;
5162                 ctxt.uplink_seid = vsi->uplink_seid;
5163                 ctxt.connection_type = 0x1;
5164                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5165
5166                 ctxt.info.valid_sections |=
5167                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5168                 /* user_param carries flag to enable loop back */
5169                 if (user_param) {
5170                         ctxt.info.switch_id =
5171                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5172                         ctxt.info.switch_id |=
5173                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5174                 }
5175
5176                 /* Configure port/vlan */
5177                 ctxt.info.valid_sections |=
5178                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5179                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5180                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5181                                                 I40E_DEFAULT_TCMAP);
5182                 if (ret != I40E_SUCCESS) {
5183                         PMD_DRV_LOG(ERR,
5184                                 "Failed to configure TC queue mapping");
5185                         goto fail_msix_alloc;
5186                 }
5187                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5188                 ctxt.info.valid_sections |=
5189                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5190         } else if (type == I40E_VSI_FDIR) {
5191                 memset(&ctxt, 0, sizeof(ctxt));
5192                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5193                 ctxt.pf_num = hw->pf_id;
5194                 ctxt.vf_num = 0;
5195                 ctxt.uplink_seid = vsi->uplink_seid;
5196                 ctxt.connection_type = 0x1;     /* regular data port */
5197                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5198                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5199                                                 I40E_DEFAULT_TCMAP);
5200                 if (ret != I40E_SUCCESS) {
5201                         PMD_DRV_LOG(ERR,
5202                                 "Failed to configure TC queue mapping.");
5203                         goto fail_msix_alloc;
5204                 }
5205                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5206                 ctxt.info.valid_sections |=
5207                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5208         } else {
5209                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5210                 goto fail_msix_alloc;
5211         }
5212
5213         if (vsi->type != I40E_VSI_MAIN) {
5214                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5215                 if (ret != I40E_SUCCESS) {
5216                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5217                                     hw->aq.asq_last_status);
5218                         goto fail_msix_alloc;
5219                 }
5220                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5221                 vsi->info.valid_sections = 0;
5222                 vsi->seid = ctxt.seid;
5223                 vsi->vsi_id = ctxt.vsi_number;
5224                 vsi->sib_vsi_list.vsi = vsi;
5225                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5226                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5227                                           &vsi->sib_vsi_list, list);
5228                 } else {
5229                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5230                                           &vsi->sib_vsi_list, list);
5231                 }
5232         }
5233
5234         /* MAC/VLAN configuration */
5235         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5236         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5237
5238         ret = i40e_vsi_add_mac(vsi, &filter);
5239         if (ret != I40E_SUCCESS) {
5240                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5241                 goto fail_msix_alloc;
5242         }
5243
5244         /* Get VSI BW information */
5245         i40e_vsi_get_bw_config(vsi);
5246         return vsi;
5247 fail_msix_alloc:
5248         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5249 fail_queue_alloc:
5250         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5251 fail_mem:
5252         rte_free(vsi);
5253         return NULL;
5254 }
5255
5256 /* Configure vlan filter on or off */
5257 int
5258 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5259 {
5260         int i, num;
5261         struct i40e_mac_filter *f;
5262         void *temp;
5263         struct i40e_mac_filter_info *mac_filter;
5264         enum rte_mac_filter_type desired_filter;
5265         int ret = I40E_SUCCESS;
5266
5267         if (on) {
5268                 /* Filter to match MAC and VLAN */
5269                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5270         } else {
5271                 /* Filter to match only MAC */
5272                 desired_filter = RTE_MAC_PERFECT_MATCH;
5273         }
5274
5275         num = vsi->mac_num;
5276
5277         mac_filter = rte_zmalloc("mac_filter_info_data",
5278                                  num * sizeof(*mac_filter), 0);
5279         if (mac_filter == NULL) {
5280                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5281                 return I40E_ERR_NO_MEMORY;
5282         }
5283
5284         i = 0;
5285
5286         /* Remove all existing mac */
5287         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5288                 mac_filter[i] = f->mac_info;
5289                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5290                 if (ret) {
5291                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5292                                     on ? "enable" : "disable");
5293                         goto DONE;
5294                 }
5295                 i++;
5296         }
5297
5298         /* Override with new filter */
5299         for (i = 0; i < num; i++) {
5300                 mac_filter[i].filter_type = desired_filter;
5301                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5302                 if (ret) {
5303                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5304                                     on ? "enable" : "disable");
5305                         goto DONE;
5306                 }
5307         }
5308
5309 DONE:
5310         rte_free(mac_filter);
5311         return ret;
5312 }
5313
5314 /* Configure vlan stripping on or off */
5315 int
5316 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5317 {
5318         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5319         struct i40e_vsi_context ctxt;
5320         uint8_t vlan_flags;
5321         int ret = I40E_SUCCESS;
5322
5323         /* Check if it has been already on or off */
5324         if (vsi->info.valid_sections &
5325                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5326                 if (on) {
5327                         if ((vsi->info.port_vlan_flags &
5328                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5329                                 return 0; /* already on */
5330                 } else {
5331                         if ((vsi->info.port_vlan_flags &
5332                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5333                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5334                                 return 0; /* already off */
5335                 }
5336         }
5337
5338         if (on)
5339                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5340         else
5341                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5342         vsi->info.valid_sections =
5343                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5344         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5345         vsi->info.port_vlan_flags |= vlan_flags;
5346         ctxt.seid = vsi->seid;
5347         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5348         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5349         if (ret)
5350                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5351                             on ? "enable" : "disable");
5352
5353         return ret;
5354 }
5355
5356 static int
5357 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5358 {
5359         struct rte_eth_dev_data *data = dev->data;
5360         int ret;
5361         int mask = 0;
5362
5363         /* Apply vlan offload setting */
5364         mask = ETH_VLAN_STRIP_MASK |
5365                ETH_VLAN_FILTER_MASK |
5366                ETH_VLAN_EXTEND_MASK;
5367         ret = i40e_vlan_offload_set(dev, mask);
5368         if (ret) {
5369                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5370                 return ret;
5371         }
5372
5373         /* Apply pvid setting */
5374         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5375                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5376         if (ret)
5377                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5378
5379         return ret;
5380 }
5381
5382 static int
5383 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5384 {
5385         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5386
5387         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5388 }
5389
5390 static int
5391 i40e_update_flow_control(struct i40e_hw *hw)
5392 {
5393 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5394         struct i40e_link_status link_status;
5395         uint32_t rxfc = 0, txfc = 0, reg;
5396         uint8_t an_info;
5397         int ret;
5398
5399         memset(&link_status, 0, sizeof(link_status));
5400         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5401         if (ret != I40E_SUCCESS) {
5402                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5403                 goto write_reg; /* Disable flow control */
5404         }
5405
5406         an_info = hw->phy.link_info.an_info;
5407         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5408                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5409                 ret = I40E_ERR_NOT_READY;
5410                 goto write_reg; /* Disable flow control */
5411         }
5412         /**
5413          * If link auto negotiation is enabled, flow control needs to
5414          * be configured according to it
5415          */
5416         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5417         case I40E_LINK_PAUSE_RXTX:
5418                 rxfc = 1;
5419                 txfc = 1;
5420                 hw->fc.current_mode = I40E_FC_FULL;
5421                 break;
5422         case I40E_AQ_LINK_PAUSE_RX:
5423                 rxfc = 1;
5424                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5425                 break;
5426         case I40E_AQ_LINK_PAUSE_TX:
5427                 txfc = 1;
5428                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5429                 break;
5430         default:
5431                 hw->fc.current_mode = I40E_FC_NONE;
5432                 break;
5433         }
5434
5435 write_reg:
5436         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5437                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5438         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5439         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5440         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5441         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5442
5443         return ret;
5444 }
5445
5446 /* PF setup */
5447 static int
5448 i40e_pf_setup(struct i40e_pf *pf)
5449 {
5450         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5451         struct i40e_filter_control_settings settings;
5452         struct i40e_vsi *vsi;
5453         int ret;
5454
5455         /* Clear all stats counters */
5456         pf->offset_loaded = FALSE;
5457         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5458         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5459         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5460         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5461
5462         ret = i40e_pf_get_switch_config(pf);
5463         if (ret != I40E_SUCCESS) {
5464                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5465                 return ret;
5466         }
5467         if (pf->flags & I40E_FLAG_FDIR) {
5468                 /* make queue allocated first, let FDIR use queue pair 0*/
5469                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5470                 if (ret != I40E_FDIR_QUEUE_ID) {
5471                         PMD_DRV_LOG(ERR,
5472                                 "queue allocation fails for FDIR: ret =%d",
5473                                 ret);
5474                         pf->flags &= ~I40E_FLAG_FDIR;
5475                 }
5476         }
5477         /*  main VSI setup */
5478         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5479         if (!vsi) {
5480                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5481                 return I40E_ERR_NOT_READY;
5482         }
5483         pf->main_vsi = vsi;
5484
5485         /* Configure filter control */
5486         memset(&settings, 0, sizeof(settings));
5487         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5488                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5489         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5490                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5491         else {
5492                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5493                         hw->func_caps.rss_table_size);
5494                 return I40E_ERR_PARAM;
5495         }
5496         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5497                 hw->func_caps.rss_table_size);
5498         pf->hash_lut_size = hw->func_caps.rss_table_size;
5499
5500         /* Enable ethtype and macvlan filters */
5501         settings.enable_ethtype = TRUE;
5502         settings.enable_macvlan = TRUE;
5503         ret = i40e_set_filter_control(hw, &settings);
5504         if (ret)
5505                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5506                                                                 ret);
5507
5508         /* Update flow control according to the auto negotiation */
5509         i40e_update_flow_control(hw);
5510
5511         return I40E_SUCCESS;
5512 }
5513
5514 int
5515 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5516 {
5517         uint32_t reg;
5518         uint16_t j;
5519
5520         /**
5521          * Set or clear TX Queue Disable flags,
5522          * which is required by hardware.
5523          */
5524         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5525         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5526
5527         /* Wait until the request is finished */
5528         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5529                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5530                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5531                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5532                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5533                                                         & 0x1))) {
5534                         break;
5535                 }
5536         }
5537         if (on) {
5538                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5539                         return I40E_SUCCESS; /* already on, skip next steps */
5540
5541                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5542                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5543         } else {
5544                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5545                         return I40E_SUCCESS; /* already off, skip next steps */
5546                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5547         }
5548         /* Write the register */
5549         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5550         /* Check the result */
5551         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5552                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5553                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5554                 if (on) {
5555                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5556                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5557                                 break;
5558                 } else {
5559                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5560                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5561                                 break;
5562                 }
5563         }
5564         /* Check if it is timeout */
5565         if (j >= I40E_CHK_Q_ENA_COUNT) {
5566                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5567                             (on ? "enable" : "disable"), q_idx);
5568                 return I40E_ERR_TIMEOUT;
5569         }
5570
5571         return I40E_SUCCESS;
5572 }
5573
5574 /* Swith on or off the tx queues */
5575 static int
5576 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5577 {
5578         struct rte_eth_dev_data *dev_data = pf->dev_data;
5579         struct i40e_tx_queue *txq;
5580         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5581         uint16_t i;
5582         int ret;
5583
5584         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5585                 txq = dev_data->tx_queues[i];
5586                 /* Don't operate the queue if not configured or
5587                  * if starting only per queue */
5588                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5589                         continue;
5590                 if (on)
5591                         ret = i40e_dev_tx_queue_start(dev, i);
5592                 else
5593                         ret = i40e_dev_tx_queue_stop(dev, i);
5594                 if ( ret != I40E_SUCCESS)
5595                         return ret;
5596         }
5597
5598         return I40E_SUCCESS;
5599 }
5600
5601 int
5602 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5603 {
5604         uint32_t reg;
5605         uint16_t j;
5606
5607         /* Wait until the request is finished */
5608         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5609                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5610                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5611                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5612                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5613                         break;
5614         }
5615
5616         if (on) {
5617                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5618                         return I40E_SUCCESS; /* Already on, skip next steps */
5619                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5620         } else {
5621                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5622                         return I40E_SUCCESS; /* Already off, skip next steps */
5623                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5624         }
5625
5626         /* Write the register */
5627         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5628         /* Check the result */
5629         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5630                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5631                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5632                 if (on) {
5633                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5634                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5635                                 break;
5636                 } else {
5637                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5638                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5639                                 break;
5640                 }
5641         }
5642
5643         /* Check if it is timeout */
5644         if (j >= I40E_CHK_Q_ENA_COUNT) {
5645                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5646                             (on ? "enable" : "disable"), q_idx);
5647                 return I40E_ERR_TIMEOUT;
5648         }
5649
5650         return I40E_SUCCESS;
5651 }
5652 /* Switch on or off the rx queues */
5653 static int
5654 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5655 {
5656         struct rte_eth_dev_data *dev_data = pf->dev_data;
5657         struct i40e_rx_queue *rxq;
5658         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5659         uint16_t i;
5660         int ret;
5661
5662         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5663                 rxq = dev_data->rx_queues[i];
5664                 /* Don't operate the queue if not configured or
5665                  * if starting only per queue */
5666                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5667                         continue;
5668                 if (on)
5669                         ret = i40e_dev_rx_queue_start(dev, i);
5670                 else
5671                         ret = i40e_dev_rx_queue_stop(dev, i);
5672                 if (ret != I40E_SUCCESS)
5673                         return ret;
5674         }
5675
5676         return I40E_SUCCESS;
5677 }
5678
5679 /* Switch on or off all the rx/tx queues */
5680 int
5681 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5682 {
5683         int ret;
5684
5685         if (on) {
5686                 /* enable rx queues before enabling tx queues */
5687                 ret = i40e_dev_switch_rx_queues(pf, on);
5688                 if (ret) {
5689                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5690                         return ret;
5691                 }
5692                 ret = i40e_dev_switch_tx_queues(pf, on);
5693         } else {
5694                 /* Stop tx queues before stopping rx queues */
5695                 ret = i40e_dev_switch_tx_queues(pf, on);
5696                 if (ret) {
5697                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5698                         return ret;
5699                 }
5700                 ret = i40e_dev_switch_rx_queues(pf, on);
5701         }
5702
5703         return ret;
5704 }
5705
5706 /* Initialize VSI for TX */
5707 static int
5708 i40e_dev_tx_init(struct i40e_pf *pf)
5709 {
5710         struct rte_eth_dev_data *data = pf->dev_data;
5711         uint16_t i;
5712         uint32_t ret = I40E_SUCCESS;
5713         struct i40e_tx_queue *txq;
5714
5715         for (i = 0; i < data->nb_tx_queues; i++) {
5716                 txq = data->tx_queues[i];
5717                 if (!txq || !txq->q_set)
5718                         continue;
5719                 ret = i40e_tx_queue_init(txq);
5720                 if (ret != I40E_SUCCESS)
5721                         break;
5722         }
5723         if (ret == I40E_SUCCESS)
5724                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5725                                      ->eth_dev);
5726
5727         return ret;
5728 }
5729
5730 /* Initialize VSI for RX */
5731 static int
5732 i40e_dev_rx_init(struct i40e_pf *pf)
5733 {
5734         struct rte_eth_dev_data *data = pf->dev_data;
5735         int ret = I40E_SUCCESS;
5736         uint16_t i;
5737         struct i40e_rx_queue *rxq;
5738
5739         i40e_pf_config_mq_rx(pf);
5740         for (i = 0; i < data->nb_rx_queues; i++) {
5741                 rxq = data->rx_queues[i];
5742                 if (!rxq || !rxq->q_set)
5743                         continue;
5744
5745                 ret = i40e_rx_queue_init(rxq);
5746                 if (ret != I40E_SUCCESS) {
5747                         PMD_DRV_LOG(ERR,
5748                                 "Failed to do RX queue initialization");
5749                         break;
5750                 }
5751         }
5752         if (ret == I40E_SUCCESS)
5753                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5754                                      ->eth_dev);
5755
5756         return ret;
5757 }
5758
5759 static int
5760 i40e_dev_rxtx_init(struct i40e_pf *pf)
5761 {
5762         int err;
5763
5764         err = i40e_dev_tx_init(pf);
5765         if (err) {
5766                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5767                 return err;
5768         }
5769         err = i40e_dev_rx_init(pf);
5770         if (err) {
5771                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5772                 return err;
5773         }
5774
5775         return err;
5776 }
5777
5778 static int
5779 i40e_vmdq_setup(struct rte_eth_dev *dev)
5780 {
5781         struct rte_eth_conf *conf = &dev->data->dev_conf;
5782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5783         int i, err, conf_vsis, j, loop;
5784         struct i40e_vsi *vsi;
5785         struct i40e_vmdq_info *vmdq_info;
5786         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5787         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5788
5789         /*
5790          * Disable interrupt to avoid message from VF. Furthermore, it will
5791          * avoid race condition in VSI creation/destroy.
5792          */
5793         i40e_pf_disable_irq0(hw);
5794
5795         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5796                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5797                 return -ENOTSUP;
5798         }
5799
5800         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5801         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5802                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5803                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5804                         pf->max_nb_vmdq_vsi);
5805                 return -ENOTSUP;
5806         }
5807
5808         if (pf->vmdq != NULL) {
5809                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5810                 return 0;
5811         }
5812
5813         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5814                                 sizeof(*vmdq_info) * conf_vsis, 0);
5815
5816         if (pf->vmdq == NULL) {
5817                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5818                 return -ENOMEM;
5819         }
5820
5821         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5822
5823         /* Create VMDQ VSI */
5824         for (i = 0; i < conf_vsis; i++) {
5825                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5826                                 vmdq_conf->enable_loop_back);
5827                 if (vsi == NULL) {
5828                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5829                         err = -1;
5830                         goto err_vsi_setup;
5831                 }
5832                 vmdq_info = &pf->vmdq[i];
5833                 vmdq_info->pf = pf;
5834                 vmdq_info->vsi = vsi;
5835         }
5836         pf->nb_cfg_vmdq_vsi = conf_vsis;
5837
5838         /* Configure Vlan */
5839         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5840         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5841                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5842                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5843                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5844                                         vmdq_conf->pool_map[i].vlan_id, j);
5845
5846                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5847                                                 vmdq_conf->pool_map[i].vlan_id);
5848                                 if (err) {
5849                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5850                                         err = -1;
5851                                         goto err_vsi_setup;
5852                                 }
5853                         }
5854                 }
5855         }
5856
5857         i40e_pf_enable_irq0(hw);
5858
5859         return 0;
5860
5861 err_vsi_setup:
5862         for (i = 0; i < conf_vsis; i++)
5863                 if (pf->vmdq[i].vsi == NULL)
5864                         break;
5865                 else
5866                         i40e_vsi_release(pf->vmdq[i].vsi);
5867
5868         rte_free(pf->vmdq);
5869         pf->vmdq = NULL;
5870         i40e_pf_enable_irq0(hw);
5871         return err;
5872 }
5873
5874 static void
5875 i40e_stat_update_32(struct i40e_hw *hw,
5876                    uint32_t reg,
5877                    bool offset_loaded,
5878                    uint64_t *offset,
5879                    uint64_t *stat)
5880 {
5881         uint64_t new_data;
5882
5883         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5884         if (!offset_loaded)
5885                 *offset = new_data;
5886
5887         if (new_data >= *offset)
5888                 *stat = (uint64_t)(new_data - *offset);
5889         else
5890                 *stat = (uint64_t)((new_data +
5891                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5892 }
5893
5894 static void
5895 i40e_stat_update_48(struct i40e_hw *hw,
5896                    uint32_t hireg,
5897                    uint32_t loreg,
5898                    bool offset_loaded,
5899                    uint64_t *offset,
5900                    uint64_t *stat)
5901 {
5902         uint64_t new_data;
5903
5904         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5905         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5906                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5907
5908         if (!offset_loaded)
5909                 *offset = new_data;
5910
5911         if (new_data >= *offset)
5912                 *stat = new_data - *offset;
5913         else
5914                 *stat = (uint64_t)((new_data +
5915                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5916
5917         *stat &= I40E_48_BIT_MASK;
5918 }
5919
5920 /* Disable IRQ0 */
5921 void
5922 i40e_pf_disable_irq0(struct i40e_hw *hw)
5923 {
5924         /* Disable all interrupt types */
5925         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5926         I40E_WRITE_FLUSH(hw);
5927 }
5928
5929 /* Enable IRQ0 */
5930 void
5931 i40e_pf_enable_irq0(struct i40e_hw *hw)
5932 {
5933         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5934                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5935                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5936                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5937         I40E_WRITE_FLUSH(hw);
5938 }
5939
5940 static void
5941 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5942 {
5943         /* read pending request and disable first */
5944         i40e_pf_disable_irq0(hw);
5945         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5946         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5947                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5948
5949         if (no_queue)
5950                 /* Link no queues with irq0 */
5951                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5952                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5953 }
5954
5955 static void
5956 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5957 {
5958         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5960         int i;
5961         uint16_t abs_vf_id;
5962         uint32_t index, offset, val;
5963
5964         if (!pf->vfs)
5965                 return;
5966         /**
5967          * Try to find which VF trigger a reset, use absolute VF id to access
5968          * since the reg is global register.
5969          */
5970         for (i = 0; i < pf->vf_num; i++) {
5971                 abs_vf_id = hw->func_caps.vf_base_id + i;
5972                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5973                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5974                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5975                 /* VFR event occurred */
5976                 if (val & (0x1 << offset)) {
5977                         int ret;
5978
5979                         /* Clear the event first */
5980                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5981                                                         (0x1 << offset));
5982                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5983                         /**
5984                          * Only notify a VF reset event occurred,
5985                          * don't trigger another SW reset
5986                          */
5987                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5988                         if (ret != I40E_SUCCESS)
5989                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5990                 }
5991         }
5992 }
5993
5994 static void
5995 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5996 {
5997         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5998         int i;
5999
6000         for (i = 0; i < pf->vf_num; i++)
6001                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6002 }
6003
6004 static void
6005 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6006 {
6007         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008         struct i40e_arq_event_info info;
6009         uint16_t pending, opcode;
6010         int ret;
6011
6012         info.buf_len = I40E_AQ_BUF_SZ;
6013         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6014         if (!info.msg_buf) {
6015                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6016                 return;
6017         }
6018
6019         pending = 1;
6020         while (pending) {
6021                 ret = i40e_clean_arq_element(hw, &info, &pending);
6022
6023                 if (ret != I40E_SUCCESS) {
6024                         PMD_DRV_LOG(INFO,
6025                                 "Failed to read msg from AdminQ, aq_err: %u",
6026                                 hw->aq.asq_last_status);
6027                         break;
6028                 }
6029                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6030
6031                 switch (opcode) {
6032                 case i40e_aqc_opc_send_msg_to_pf:
6033                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6034                         i40e_pf_host_handle_vf_msg(dev,
6035                                         rte_le_to_cpu_16(info.desc.retval),
6036                                         rte_le_to_cpu_32(info.desc.cookie_high),
6037                                         rte_le_to_cpu_32(info.desc.cookie_low),
6038                                         info.msg_buf,
6039                                         info.msg_len);
6040                         break;
6041                 case i40e_aqc_opc_get_link_status:
6042                         ret = i40e_dev_link_update(dev, 0);
6043                         if (!ret)
6044                                 _rte_eth_dev_callback_process(dev,
6045                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6046                         break;
6047                 default:
6048                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6049                                     opcode);
6050                         break;
6051                 }
6052         }
6053         rte_free(info.msg_buf);
6054 }
6055
6056 /**
6057  * Interrupt handler triggered by NIC  for handling
6058  * specific interrupt.
6059  *
6060  * @param handle
6061  *  Pointer to interrupt handle.
6062  * @param param
6063  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6064  *
6065  * @return
6066  *  void
6067  */
6068 static void
6069 i40e_dev_interrupt_handler(void *param)
6070 {
6071         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6073         uint32_t icr0;
6074
6075         /* Disable interrupt */
6076         i40e_pf_disable_irq0(hw);
6077
6078         /* read out interrupt causes */
6079         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6080
6081         /* No interrupt event indicated */
6082         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6083                 PMD_DRV_LOG(INFO, "No interrupt event");
6084                 goto done;
6085         }
6086         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6087                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6088         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6089                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6090         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6091                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6092         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6093                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6094         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6095                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6096         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6097                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6098         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6099                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6100
6101         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6102                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6103                 i40e_dev_handle_vfr_event(dev);
6104         }
6105         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6106                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6107                 i40e_dev_handle_aq_msg(dev);
6108         }
6109
6110 done:
6111         /* Enable interrupt */
6112         i40e_pf_enable_irq0(hw);
6113         rte_intr_enable(dev->intr_handle);
6114 }
6115
6116 int
6117 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6118                          struct i40e_macvlan_filter *filter,
6119                          int total)
6120 {
6121         int ele_num, ele_buff_size;
6122         int num, actual_num, i;
6123         uint16_t flags;
6124         int ret = I40E_SUCCESS;
6125         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6126         struct i40e_aqc_add_macvlan_element_data *req_list;
6127
6128         if (filter == NULL  || total == 0)
6129                 return I40E_ERR_PARAM;
6130         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6131         ele_buff_size = hw->aq.asq_buf_size;
6132
6133         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6134         if (req_list == NULL) {
6135                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6136                 return I40E_ERR_NO_MEMORY;
6137         }
6138
6139         num = 0;
6140         do {
6141                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6142                 memset(req_list, 0, ele_buff_size);
6143
6144                 for (i = 0; i < actual_num; i++) {
6145                         rte_memcpy(req_list[i].mac_addr,
6146                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6147                         req_list[i].vlan_tag =
6148                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6149
6150                         switch (filter[num + i].filter_type) {
6151                         case RTE_MAC_PERFECT_MATCH:
6152                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6153                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6154                                 break;
6155                         case RTE_MACVLAN_PERFECT_MATCH:
6156                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6157                                 break;
6158                         case RTE_MAC_HASH_MATCH:
6159                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6160                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6161                                 break;
6162                         case RTE_MACVLAN_HASH_MATCH:
6163                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6164                                 break;
6165                         default:
6166                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6167                                 ret = I40E_ERR_PARAM;
6168                                 goto DONE;
6169                         }
6170
6171                         req_list[i].queue_number = 0;
6172
6173                         req_list[i].flags = rte_cpu_to_le_16(flags);
6174                 }
6175
6176                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6177                                                 actual_num, NULL);
6178                 if (ret != I40E_SUCCESS) {
6179                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6180                         goto DONE;
6181                 }
6182                 num += actual_num;
6183         } while (num < total);
6184
6185 DONE:
6186         rte_free(req_list);
6187         return ret;
6188 }
6189
6190 int
6191 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6192                             struct i40e_macvlan_filter *filter,
6193                             int total)
6194 {
6195         int ele_num, ele_buff_size;
6196         int num, actual_num, i;
6197         uint16_t flags;
6198         int ret = I40E_SUCCESS;
6199         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6200         struct i40e_aqc_remove_macvlan_element_data *req_list;
6201
6202         if (filter == NULL  || total == 0)
6203                 return I40E_ERR_PARAM;
6204
6205         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6206         ele_buff_size = hw->aq.asq_buf_size;
6207
6208         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6209         if (req_list == NULL) {
6210                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6211                 return I40E_ERR_NO_MEMORY;
6212         }
6213
6214         num = 0;
6215         do {
6216                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6217                 memset(req_list, 0, ele_buff_size);
6218
6219                 for (i = 0; i < actual_num; i++) {
6220                         rte_memcpy(req_list[i].mac_addr,
6221                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6222                         req_list[i].vlan_tag =
6223                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6224
6225                         switch (filter[num + i].filter_type) {
6226                         case RTE_MAC_PERFECT_MATCH:
6227                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6228                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6229                                 break;
6230                         case RTE_MACVLAN_PERFECT_MATCH:
6231                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6232                                 break;
6233                         case RTE_MAC_HASH_MATCH:
6234                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6235                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6236                                 break;
6237                         case RTE_MACVLAN_HASH_MATCH:
6238                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6239                                 break;
6240                         default:
6241                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6242                                 ret = I40E_ERR_PARAM;
6243                                 goto DONE;
6244                         }
6245                         req_list[i].flags = rte_cpu_to_le_16(flags);
6246                 }
6247
6248                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6249                                                 actual_num, NULL);
6250                 if (ret != I40E_SUCCESS) {
6251                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6252                         goto DONE;
6253                 }
6254                 num += actual_num;
6255         } while (num < total);
6256
6257 DONE:
6258         rte_free(req_list);
6259         return ret;
6260 }
6261
6262 /* Find out specific MAC filter */
6263 static struct i40e_mac_filter *
6264 i40e_find_mac_filter(struct i40e_vsi *vsi,
6265                          struct ether_addr *macaddr)
6266 {
6267         struct i40e_mac_filter *f;
6268
6269         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6270                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6271                         return f;
6272         }
6273
6274         return NULL;
6275 }
6276
6277 static bool
6278 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6279                          uint16_t vlan_id)
6280 {
6281         uint32_t vid_idx, vid_bit;
6282
6283         if (vlan_id > ETH_VLAN_ID_MAX)
6284                 return 0;
6285
6286         vid_idx = I40E_VFTA_IDX(vlan_id);
6287         vid_bit = I40E_VFTA_BIT(vlan_id);
6288
6289         if (vsi->vfta[vid_idx] & vid_bit)
6290                 return 1;
6291         else
6292                 return 0;
6293 }
6294
6295 static void
6296 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6297                        uint16_t vlan_id, bool on)
6298 {
6299         uint32_t vid_idx, vid_bit;
6300
6301         vid_idx = I40E_VFTA_IDX(vlan_id);
6302         vid_bit = I40E_VFTA_BIT(vlan_id);
6303
6304         if (on)
6305                 vsi->vfta[vid_idx] |= vid_bit;
6306         else
6307                 vsi->vfta[vid_idx] &= ~vid_bit;
6308 }
6309
6310 void
6311 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6312                      uint16_t vlan_id, bool on)
6313 {
6314         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6315         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6316         int ret;
6317
6318         if (vlan_id > ETH_VLAN_ID_MAX)
6319                 return;
6320
6321         i40e_store_vlan_filter(vsi, vlan_id, on);
6322
6323         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6324                 return;
6325
6326         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6327
6328         if (on) {
6329                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6330                                        &vlan_data, 1, NULL);
6331                 if (ret != I40E_SUCCESS)
6332                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6333         } else {
6334                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6335                                           &vlan_data, 1, NULL);
6336                 if (ret != I40E_SUCCESS)
6337                         PMD_DRV_LOG(ERR,
6338                                     "Failed to remove vlan filter");
6339         }
6340 }
6341
6342 /**
6343  * Find all vlan options for specific mac addr,
6344  * return with actual vlan found.
6345  */
6346 int
6347 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6348                            struct i40e_macvlan_filter *mv_f,
6349                            int num, struct ether_addr *addr)
6350 {
6351         int i;
6352         uint32_t j, k;
6353
6354         /**
6355          * Not to use i40e_find_vlan_filter to decrease the loop time,
6356          * although the code looks complex.
6357           */
6358         if (num < vsi->vlan_num)
6359                 return I40E_ERR_PARAM;
6360
6361         i = 0;
6362         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6363                 if (vsi->vfta[j]) {
6364                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6365                                 if (vsi->vfta[j] & (1 << k)) {
6366                                         if (i > num - 1) {
6367                                                 PMD_DRV_LOG(ERR,
6368                                                         "vlan number doesn't match");
6369                                                 return I40E_ERR_PARAM;
6370                                         }
6371                                         rte_memcpy(&mv_f[i].macaddr,
6372                                                         addr, ETH_ADDR_LEN);
6373                                         mv_f[i].vlan_id =
6374                                                 j * I40E_UINT32_BIT_SIZE + k;
6375                                         i++;
6376                                 }
6377                         }
6378                 }
6379         }
6380         return I40E_SUCCESS;
6381 }
6382
6383 static inline int
6384 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6385                            struct i40e_macvlan_filter *mv_f,
6386                            int num,
6387                            uint16_t vlan)
6388 {
6389         int i = 0;
6390         struct i40e_mac_filter *f;
6391
6392         if (num < vsi->mac_num)
6393                 return I40E_ERR_PARAM;
6394
6395         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6396                 if (i > num - 1) {
6397                         PMD_DRV_LOG(ERR, "buffer number not match");
6398                         return I40E_ERR_PARAM;
6399                 }
6400                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6401                                 ETH_ADDR_LEN);
6402                 mv_f[i].vlan_id = vlan;
6403                 mv_f[i].filter_type = f->mac_info.filter_type;
6404                 i++;
6405         }
6406
6407         return I40E_SUCCESS;
6408 }
6409
6410 static int
6411 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6412 {
6413         int i, j, num;
6414         struct i40e_mac_filter *f;
6415         struct i40e_macvlan_filter *mv_f;
6416         int ret = I40E_SUCCESS;
6417
6418         if (vsi == NULL || vsi->mac_num == 0)
6419                 return I40E_ERR_PARAM;
6420
6421         /* Case that no vlan is set */
6422         if (vsi->vlan_num == 0)
6423                 num = vsi->mac_num;
6424         else
6425                 num = vsi->mac_num * vsi->vlan_num;
6426
6427         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6428         if (mv_f == NULL) {
6429                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6430                 return I40E_ERR_NO_MEMORY;
6431         }
6432
6433         i = 0;
6434         if (vsi->vlan_num == 0) {
6435                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6436                         rte_memcpy(&mv_f[i].macaddr,
6437                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6438                         mv_f[i].filter_type = f->mac_info.filter_type;
6439                         mv_f[i].vlan_id = 0;
6440                         i++;
6441                 }
6442         } else {
6443                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6444                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6445                                         vsi->vlan_num, &f->mac_info.mac_addr);
6446                         if (ret != I40E_SUCCESS)
6447                                 goto DONE;
6448                         for (j = i; j < i + vsi->vlan_num; j++)
6449                                 mv_f[j].filter_type = f->mac_info.filter_type;
6450                         i += vsi->vlan_num;
6451                 }
6452         }
6453
6454         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6455 DONE:
6456         rte_free(mv_f);
6457
6458         return ret;
6459 }
6460
6461 int
6462 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6463 {
6464         struct i40e_macvlan_filter *mv_f;
6465         int mac_num;
6466         int ret = I40E_SUCCESS;
6467
6468         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6469                 return I40E_ERR_PARAM;
6470
6471         /* If it's already set, just return */
6472         if (i40e_find_vlan_filter(vsi,vlan))
6473                 return I40E_SUCCESS;
6474
6475         mac_num = vsi->mac_num;
6476
6477         if (mac_num == 0) {
6478                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6479                 return I40E_ERR_PARAM;
6480         }
6481
6482         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6483
6484         if (mv_f == NULL) {
6485                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6486                 return I40E_ERR_NO_MEMORY;
6487         }
6488
6489         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6490
6491         if (ret != I40E_SUCCESS)
6492                 goto DONE;
6493
6494         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6495
6496         if (ret != I40E_SUCCESS)
6497                 goto DONE;
6498
6499         i40e_set_vlan_filter(vsi, vlan, 1);
6500
6501         vsi->vlan_num++;
6502         ret = I40E_SUCCESS;
6503 DONE:
6504         rte_free(mv_f);
6505         return ret;
6506 }
6507
6508 int
6509 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6510 {
6511         struct i40e_macvlan_filter *mv_f;
6512         int mac_num;
6513         int ret = I40E_SUCCESS;
6514
6515         /**
6516          * Vlan 0 is the generic filter for untagged packets
6517          * and can't be removed.
6518          */
6519         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6520                 return I40E_ERR_PARAM;
6521
6522         /* If can't find it, just return */
6523         if (!i40e_find_vlan_filter(vsi, vlan))
6524                 return I40E_ERR_PARAM;
6525
6526         mac_num = vsi->mac_num;
6527
6528         if (mac_num == 0) {
6529                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6530                 return I40E_ERR_PARAM;
6531         }
6532
6533         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6534
6535         if (mv_f == NULL) {
6536                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6537                 return I40E_ERR_NO_MEMORY;
6538         }
6539
6540         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6541
6542         if (ret != I40E_SUCCESS)
6543                 goto DONE;
6544
6545         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6546
6547         if (ret != I40E_SUCCESS)
6548                 goto DONE;
6549
6550         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6551         if (vsi->vlan_num == 1) {
6552                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6553                 if (ret != I40E_SUCCESS)
6554                         goto DONE;
6555
6556                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6557                 if (ret != I40E_SUCCESS)
6558                         goto DONE;
6559         }
6560
6561         i40e_set_vlan_filter(vsi, vlan, 0);
6562
6563         vsi->vlan_num--;
6564         ret = I40E_SUCCESS;
6565 DONE:
6566         rte_free(mv_f);
6567         return ret;
6568 }
6569
6570 int
6571 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6572 {
6573         struct i40e_mac_filter *f;
6574         struct i40e_macvlan_filter *mv_f;
6575         int i, vlan_num = 0;
6576         int ret = I40E_SUCCESS;
6577
6578         /* If it's add and we've config it, return */
6579         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6580         if (f != NULL)
6581                 return I40E_SUCCESS;
6582         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6583                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6584
6585                 /**
6586                  * If vlan_num is 0, that's the first time to add mac,
6587                  * set mask for vlan_id 0.
6588                  */
6589                 if (vsi->vlan_num == 0) {
6590                         i40e_set_vlan_filter(vsi, 0, 1);
6591                         vsi->vlan_num = 1;
6592                 }
6593                 vlan_num = vsi->vlan_num;
6594         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6595                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6596                 vlan_num = 1;
6597
6598         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6599         if (mv_f == NULL) {
6600                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6601                 return I40E_ERR_NO_MEMORY;
6602         }
6603
6604         for (i = 0; i < vlan_num; i++) {
6605                 mv_f[i].filter_type = mac_filter->filter_type;
6606                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6607                                 ETH_ADDR_LEN);
6608         }
6609
6610         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6611                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6612                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6613                                         &mac_filter->mac_addr);
6614                 if (ret != I40E_SUCCESS)
6615                         goto DONE;
6616         }
6617
6618         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6619         if (ret != I40E_SUCCESS)
6620                 goto DONE;
6621
6622         /* Add the mac addr into mac list */
6623         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6624         if (f == NULL) {
6625                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6626                 ret = I40E_ERR_NO_MEMORY;
6627                 goto DONE;
6628         }
6629         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6630                         ETH_ADDR_LEN);
6631         f->mac_info.filter_type = mac_filter->filter_type;
6632         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6633         vsi->mac_num++;
6634
6635         ret = I40E_SUCCESS;
6636 DONE:
6637         rte_free(mv_f);
6638
6639         return ret;
6640 }
6641
6642 int
6643 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6644 {
6645         struct i40e_mac_filter *f;
6646         struct i40e_macvlan_filter *mv_f;
6647         int i, vlan_num;
6648         enum rte_mac_filter_type filter_type;
6649         int ret = I40E_SUCCESS;
6650
6651         /* Can't find it, return an error */
6652         f = i40e_find_mac_filter(vsi, addr);
6653         if (f == NULL)
6654                 return I40E_ERR_PARAM;
6655
6656         vlan_num = vsi->vlan_num;
6657         filter_type = f->mac_info.filter_type;
6658         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6659                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6660                 if (vlan_num == 0) {
6661                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6662                         return I40E_ERR_PARAM;
6663                 }
6664         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6665                         filter_type == RTE_MAC_HASH_MATCH)
6666                 vlan_num = 1;
6667
6668         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6669         if (mv_f == NULL) {
6670                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6671                 return I40E_ERR_NO_MEMORY;
6672         }
6673
6674         for (i = 0; i < vlan_num; i++) {
6675                 mv_f[i].filter_type = filter_type;
6676                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6677                                 ETH_ADDR_LEN);
6678         }
6679         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6680                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6681                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6682                 if (ret != I40E_SUCCESS)
6683                         goto DONE;
6684         }
6685
6686         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6687         if (ret != I40E_SUCCESS)
6688                 goto DONE;
6689
6690         /* Remove the mac addr into mac list */
6691         TAILQ_REMOVE(&vsi->mac_list, f, next);
6692         rte_free(f);
6693         vsi->mac_num--;
6694
6695         ret = I40E_SUCCESS;
6696 DONE:
6697         rte_free(mv_f);
6698         return ret;
6699 }
6700
6701 /* Configure hash enable flags for RSS */
6702 uint64_t
6703 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6704 {
6705         uint64_t hena = 0;
6706         int i;
6707
6708         if (!flags)
6709                 return hena;
6710
6711         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6712                 if (flags & (1ULL << i))
6713                         hena |= adapter->pctypes_tbl[i];
6714         }
6715
6716         return hena;
6717 }
6718
6719 /* Parse the hash enable flags */
6720 uint64_t
6721 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6722 {
6723         uint64_t rss_hf = 0;
6724
6725         if (!flags)
6726                 return rss_hf;
6727         int i;
6728
6729         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6730                 if (flags & adapter->pctypes_tbl[i])
6731                         rss_hf |= (1ULL << i);
6732         }
6733         return rss_hf;
6734 }
6735
6736 /* Disable RSS */
6737 static void
6738 i40e_pf_disable_rss(struct i40e_pf *pf)
6739 {
6740         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6741
6742         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6743         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6744         I40E_WRITE_FLUSH(hw);
6745 }
6746
6747 static int
6748 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6749 {
6750         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6751         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6752         int ret = 0;
6753
6754         if (!key || key_len == 0) {
6755                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6756                 return 0;
6757         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6758                 sizeof(uint32_t)) {
6759                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6760                 return -EINVAL;
6761         }
6762
6763         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6764                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6765                         (struct i40e_aqc_get_set_rss_key_data *)key;
6766
6767                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6768                 if (ret)
6769                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6770         } else {
6771                 uint32_t *hash_key = (uint32_t *)key;
6772                 uint16_t i;
6773
6774                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6775                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6776                 I40E_WRITE_FLUSH(hw);
6777         }
6778
6779         return ret;
6780 }
6781
6782 static int
6783 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6784 {
6785         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6786         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6787         int ret;
6788
6789         if (!key || !key_len)
6790                 return -EINVAL;
6791
6792         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6793                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6794                         (struct i40e_aqc_get_set_rss_key_data *)key);
6795                 if (ret) {
6796                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6797                         return ret;
6798                 }
6799         } else {
6800                 uint32_t *key_dw = (uint32_t *)key;
6801                 uint16_t i;
6802
6803                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6804                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6805         }
6806         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6807
6808         return 0;
6809 }
6810
6811 static int
6812 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6813 {
6814         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6815         uint64_t hena;
6816         int ret;
6817
6818         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6819                                rss_conf->rss_key_len);
6820         if (ret)
6821                 return ret;
6822
6823         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6824         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6825         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6826         I40E_WRITE_FLUSH(hw);
6827
6828         return 0;
6829 }
6830
6831 static int
6832 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6833                          struct rte_eth_rss_conf *rss_conf)
6834 {
6835         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6837         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6838         uint64_t hena;
6839
6840         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6841         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6842
6843         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6844                 if (rss_hf != 0) /* Enable RSS */
6845                         return -EINVAL;
6846                 return 0; /* Nothing to do */
6847         }
6848         /* RSS enabled */
6849         if (rss_hf == 0) /* Disable RSS */
6850                 return -EINVAL;
6851
6852         return i40e_hw_rss_hash_set(pf, rss_conf);
6853 }
6854
6855 static int
6856 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6857                            struct rte_eth_rss_conf *rss_conf)
6858 {
6859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6861         uint64_t hena;
6862
6863         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6864                          &rss_conf->rss_key_len);
6865
6866         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6867         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6868         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6869
6870         return 0;
6871 }
6872
6873 static int
6874 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6875 {
6876         switch (filter_type) {
6877         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6878                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6879                 break;
6880         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6881                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6882                 break;
6883         case RTE_TUNNEL_FILTER_IMAC_TENID:
6884                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6885                 break;
6886         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6887                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6888                 break;
6889         case ETH_TUNNEL_FILTER_IMAC:
6890                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6891                 break;
6892         case ETH_TUNNEL_FILTER_OIP:
6893                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6894                 break;
6895         case ETH_TUNNEL_FILTER_IIP:
6896                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6897                 break;
6898         default:
6899                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6900                 return -EINVAL;
6901         }
6902
6903         return 0;
6904 }
6905
6906 /* Convert tunnel filter structure */
6907 static int
6908 i40e_tunnel_filter_convert(
6909         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6910         struct i40e_tunnel_filter *tunnel_filter)
6911 {
6912         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6913                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6914         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6915                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6916         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6917         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6918              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6919             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6920                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6921         else
6922                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6923         tunnel_filter->input.flags = cld_filter->element.flags;
6924         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6925         tunnel_filter->queue = cld_filter->element.queue_number;
6926         rte_memcpy(tunnel_filter->input.general_fields,
6927                    cld_filter->general_fields,
6928                    sizeof(cld_filter->general_fields));
6929
6930         return 0;
6931 }
6932
6933 /* Check if there exists the tunnel filter */
6934 struct i40e_tunnel_filter *
6935 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6936                              const struct i40e_tunnel_filter_input *input)
6937 {
6938         int ret;
6939
6940         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6941         if (ret < 0)
6942                 return NULL;
6943
6944         return tunnel_rule->hash_map[ret];
6945 }
6946
6947 /* Add a tunnel filter into the SW list */
6948 static int
6949 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6950                              struct i40e_tunnel_filter *tunnel_filter)
6951 {
6952         struct i40e_tunnel_rule *rule = &pf->tunnel;
6953         int ret;
6954
6955         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6956         if (ret < 0) {
6957                 PMD_DRV_LOG(ERR,
6958                             "Failed to insert tunnel filter to hash table %d!",
6959                             ret);
6960                 return ret;
6961         }
6962         rule->hash_map[ret] = tunnel_filter;
6963
6964         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6965
6966         return 0;
6967 }
6968
6969 /* Delete a tunnel filter from the SW list */
6970 int
6971 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6972                           struct i40e_tunnel_filter_input *input)
6973 {
6974         struct i40e_tunnel_rule *rule = &pf->tunnel;
6975         struct i40e_tunnel_filter *tunnel_filter;
6976         int ret;
6977
6978         ret = rte_hash_del_key(rule->hash_table, input);
6979         if (ret < 0) {
6980                 PMD_DRV_LOG(ERR,
6981                             "Failed to delete tunnel filter to hash table %d!",
6982                             ret);
6983                 return ret;
6984         }
6985         tunnel_filter = rule->hash_map[ret];
6986         rule->hash_map[ret] = NULL;
6987
6988         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6989         rte_free(tunnel_filter);
6990
6991         return 0;
6992 }
6993
6994 int
6995 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6996                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6997                         uint8_t add)
6998 {
6999         uint16_t ip_type;
7000         uint32_t ipv4_addr, ipv4_addr_le;
7001         uint8_t i, tun_type = 0;
7002         /* internal varialbe to convert ipv6 byte order */
7003         uint32_t convert_ipv6[4];
7004         int val, ret = 0;
7005         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7006         struct i40e_vsi *vsi = pf->main_vsi;
7007         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7008         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7009         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7010         struct i40e_tunnel_filter *tunnel, *node;
7011         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7012
7013         cld_filter = rte_zmalloc("tunnel_filter",
7014                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7015         0);
7016
7017         if (NULL == cld_filter) {
7018                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7019                 return -ENOMEM;
7020         }
7021         pfilter = cld_filter;
7022
7023         ether_addr_copy(&tunnel_filter->outer_mac,
7024                         (struct ether_addr *)&pfilter->element.outer_mac);
7025         ether_addr_copy(&tunnel_filter->inner_mac,
7026                         (struct ether_addr *)&pfilter->element.inner_mac);
7027
7028         pfilter->element.inner_vlan =
7029                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7030         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7031                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7032                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7033                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7034                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7035                                 &ipv4_addr_le,
7036                                 sizeof(pfilter->element.ipaddr.v4.data));
7037         } else {
7038                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7039                 for (i = 0; i < 4; i++) {
7040                         convert_ipv6[i] =
7041                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7042                 }
7043                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7044                            &convert_ipv6,
7045                            sizeof(pfilter->element.ipaddr.v6.data));
7046         }
7047
7048         /* check tunneled type */
7049         switch (tunnel_filter->tunnel_type) {
7050         case RTE_TUNNEL_TYPE_VXLAN:
7051                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7052                 break;
7053         case RTE_TUNNEL_TYPE_NVGRE:
7054                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7055                 break;
7056         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7057                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7058                 break;
7059         default:
7060                 /* Other tunnel types is not supported. */
7061                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7062                 rte_free(cld_filter);
7063                 return -EINVAL;
7064         }
7065
7066         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7067                                        &pfilter->element.flags);
7068         if (val < 0) {
7069                 rte_free(cld_filter);
7070                 return -EINVAL;
7071         }
7072
7073         pfilter->element.flags |= rte_cpu_to_le_16(
7074                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7075                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7076         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7077         pfilter->element.queue_number =
7078                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7079
7080         /* Check if there is the filter in SW list */
7081         memset(&check_filter, 0, sizeof(check_filter));
7082         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7083         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7084         if (add && node) {
7085                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7086                 return -EINVAL;
7087         }
7088
7089         if (!add && !node) {
7090                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7091                 return -EINVAL;
7092         }
7093
7094         if (add) {
7095                 ret = i40e_aq_add_cloud_filters(hw,
7096                                         vsi->seid, &cld_filter->element, 1);
7097                 if (ret < 0) {
7098                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7099                         return -ENOTSUP;
7100                 }
7101                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7102                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7103                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7104         } else {
7105                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7106                                                    &cld_filter->element, 1);
7107                 if (ret < 0) {
7108                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7109                         return -ENOTSUP;
7110                 }
7111                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7112         }
7113
7114         rte_free(cld_filter);
7115         return ret;
7116 }
7117
7118 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7119 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7120 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7121 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7122 #define I40E_TR_GRE_KEY_MASK                    0x400
7123 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7124 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7125
7126 static enum
7127 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7128 {
7129         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7130         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7131         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7132         enum i40e_status_code status = I40E_SUCCESS;
7133
7134         memset(&filter_replace, 0,
7135                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7136         memset(&filter_replace_buf, 0,
7137                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7138
7139         /* create L1 filter */
7140         filter_replace.old_filter_type =
7141                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7142         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7143         filter_replace.tr_bit = 0;
7144
7145         /* Prepare the buffer, 3 entries */
7146         filter_replace_buf.data[0] =
7147                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7148         filter_replace_buf.data[0] |=
7149                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7150         filter_replace_buf.data[2] = 0xFF;
7151         filter_replace_buf.data[3] = 0xFF;
7152         filter_replace_buf.data[4] =
7153                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7154         filter_replace_buf.data[4] |=
7155                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7156         filter_replace_buf.data[7] = 0xF0;
7157         filter_replace_buf.data[8]
7158                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7159         filter_replace_buf.data[8] |=
7160                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7161         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7162                 I40E_TR_GENEVE_KEY_MASK |
7163                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7164         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7165                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7166                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7167
7168         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7169                                                &filter_replace_buf);
7170         return status;
7171 }
7172
7173 static enum
7174 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7175 {
7176         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7177         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7178         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7179         enum i40e_status_code status = I40E_SUCCESS;
7180
7181         /* For MPLSoUDP */
7182         memset(&filter_replace, 0,
7183                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7184         memset(&filter_replace_buf, 0,
7185                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7186         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7187                 I40E_AQC_MIRROR_CLOUD_FILTER;
7188         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7189         filter_replace.new_filter_type =
7190                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7191         /* Prepare the buffer, 2 entries */
7192         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7193         filter_replace_buf.data[0] |=
7194                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7195         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7196         filter_replace_buf.data[4] |=
7197                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7198         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7199                                                &filter_replace_buf);
7200         if (status < 0)
7201                 return status;
7202
7203         /* For MPLSoGRE */
7204         memset(&filter_replace, 0,
7205                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7206         memset(&filter_replace_buf, 0,
7207                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7208
7209         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7210                 I40E_AQC_MIRROR_CLOUD_FILTER;
7211         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7212         filter_replace.new_filter_type =
7213                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7214         /* Prepare the buffer, 2 entries */
7215         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7216         filter_replace_buf.data[0] |=
7217                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7218         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7219         filter_replace_buf.data[4] |=
7220                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7221
7222         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7223                                                &filter_replace_buf);
7224         return status;
7225 }
7226
7227 static enum i40e_status_code
7228 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7229 {
7230         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7231         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7232         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7233         enum i40e_status_code status = I40E_SUCCESS;
7234
7235         /* For GTP-C */
7236         memset(&filter_replace, 0,
7237                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7238         memset(&filter_replace_buf, 0,
7239                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7240         /* create L1 filter */
7241         filter_replace.old_filter_type =
7242                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7243         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7244         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7245                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7246         /* Prepare the buffer, 2 entries */
7247         filter_replace_buf.data[0] =
7248                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7249         filter_replace_buf.data[0] |=
7250                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7251         filter_replace_buf.data[2] = 0xFF;
7252         filter_replace_buf.data[3] = 0xFF;
7253         filter_replace_buf.data[4] =
7254                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7255         filter_replace_buf.data[4] |=
7256                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7257         filter_replace_buf.data[6] = 0xFF;
7258         filter_replace_buf.data[7] = 0xFF;
7259         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7260                                                &filter_replace_buf);
7261         if (status < 0)
7262                 return status;
7263
7264         /* for GTP-U */
7265         memset(&filter_replace, 0,
7266                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7267         memset(&filter_replace_buf, 0,
7268                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7269         /* create L1 filter */
7270         filter_replace.old_filter_type =
7271                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7272         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7273         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7274                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7275         /* Prepare the buffer, 2 entries */
7276         filter_replace_buf.data[0] =
7277                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7278         filter_replace_buf.data[0] |=
7279                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7280         filter_replace_buf.data[2] = 0xFF;
7281         filter_replace_buf.data[3] = 0xFF;
7282         filter_replace_buf.data[4] =
7283                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7284         filter_replace_buf.data[4] |=
7285                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7286         filter_replace_buf.data[6] = 0xFF;
7287         filter_replace_buf.data[7] = 0xFF;
7288
7289         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7290                                                &filter_replace_buf);
7291         return status;
7292 }
7293
7294 static enum
7295 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7296 {
7297         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7298         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7299         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7300         enum i40e_status_code status = I40E_SUCCESS;
7301
7302         /* for GTP-C */
7303         memset(&filter_replace, 0,
7304                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7305         memset(&filter_replace_buf, 0,
7306                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7307         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7308         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7309         filter_replace.new_filter_type =
7310                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7311         /* Prepare the buffer, 2 entries */
7312         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7313         filter_replace_buf.data[0] |=
7314                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7315         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7316         filter_replace_buf.data[4] |=
7317                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7318         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7319                                                &filter_replace_buf);
7320         if (status < 0)
7321                 return status;
7322
7323         /* for GTP-U */
7324         memset(&filter_replace, 0,
7325                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7326         memset(&filter_replace_buf, 0,
7327                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7328         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7329         filter_replace.old_filter_type =
7330                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7331         filter_replace.new_filter_type =
7332                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7333         /* Prepare the buffer, 2 entries */
7334         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7335         filter_replace_buf.data[0] |=
7336                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7337         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7338         filter_replace_buf.data[4] |=
7339                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7340
7341         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7342                                                &filter_replace_buf);
7343         return status;
7344 }
7345
7346 int
7347 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7348                       struct i40e_tunnel_filter_conf *tunnel_filter,
7349                       uint8_t add)
7350 {
7351         uint16_t ip_type;
7352         uint32_t ipv4_addr, ipv4_addr_le;
7353         uint8_t i, tun_type = 0;
7354         /* internal variable to convert ipv6 byte order */
7355         uint32_t convert_ipv6[4];
7356         int val, ret = 0;
7357         struct i40e_pf_vf *vf = NULL;
7358         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7359         struct i40e_vsi *vsi;
7360         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7361         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7362         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7363         struct i40e_tunnel_filter *tunnel, *node;
7364         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7365         uint32_t teid_le;
7366         bool big_buffer = 0;
7367
7368         cld_filter = rte_zmalloc("tunnel_filter",
7369                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7370                          0);
7371
7372         if (cld_filter == NULL) {
7373                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7374                 return -ENOMEM;
7375         }
7376         pfilter = cld_filter;
7377
7378         ether_addr_copy(&tunnel_filter->outer_mac,
7379                         (struct ether_addr *)&pfilter->element.outer_mac);
7380         ether_addr_copy(&tunnel_filter->inner_mac,
7381                         (struct ether_addr *)&pfilter->element.inner_mac);
7382
7383         pfilter->element.inner_vlan =
7384                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7385         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7386                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7387                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7388                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7389                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7390                                 &ipv4_addr_le,
7391                                 sizeof(pfilter->element.ipaddr.v4.data));
7392         } else {
7393                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7394                 for (i = 0; i < 4; i++) {
7395                         convert_ipv6[i] =
7396                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7397                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7398                 }
7399                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7400                            &convert_ipv6,
7401                            sizeof(pfilter->element.ipaddr.v6.data));
7402         }
7403
7404         /* check tunneled type */
7405         switch (tunnel_filter->tunnel_type) {
7406         case I40E_TUNNEL_TYPE_VXLAN:
7407                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7408                 break;
7409         case I40E_TUNNEL_TYPE_NVGRE:
7410                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7411                 break;
7412         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7413                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7414                 break;
7415         case I40E_TUNNEL_TYPE_MPLSoUDP:
7416                 if (!pf->mpls_replace_flag) {
7417                         i40e_replace_mpls_l1_filter(pf);
7418                         i40e_replace_mpls_cloud_filter(pf);
7419                         pf->mpls_replace_flag = 1;
7420                 }
7421                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7422                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7423                         teid_le >> 4;
7424                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7425                         (teid_le & 0xF) << 12;
7426                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7427                         0x40;
7428                 big_buffer = 1;
7429                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7430                 break;
7431         case I40E_TUNNEL_TYPE_MPLSoGRE:
7432                 if (!pf->mpls_replace_flag) {
7433                         i40e_replace_mpls_l1_filter(pf);
7434                         i40e_replace_mpls_cloud_filter(pf);
7435                         pf->mpls_replace_flag = 1;
7436                 }
7437                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7438                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7439                         teid_le >> 4;
7440                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7441                         (teid_le & 0xF) << 12;
7442                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7443                         0x0;
7444                 big_buffer = 1;
7445                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7446                 break;
7447         case I40E_TUNNEL_TYPE_GTPC:
7448                 if (!pf->gtp_replace_flag) {
7449                         i40e_replace_gtp_l1_filter(pf);
7450                         i40e_replace_gtp_cloud_filter(pf);
7451                         pf->gtp_replace_flag = 1;
7452                 }
7453                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7454                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7455                         (teid_le >> 16) & 0xFFFF;
7456                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7457                         teid_le & 0xFFFF;
7458                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7459                         0x0;
7460                 big_buffer = 1;
7461                 break;
7462         case I40E_TUNNEL_TYPE_GTPU:
7463                 if (!pf->gtp_replace_flag) {
7464                         i40e_replace_gtp_l1_filter(pf);
7465                         i40e_replace_gtp_cloud_filter(pf);
7466                         pf->gtp_replace_flag = 1;
7467                 }
7468                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7469                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7470                         (teid_le >> 16) & 0xFFFF;
7471                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7472                         teid_le & 0xFFFF;
7473                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7474                         0x0;
7475                 big_buffer = 1;
7476                 break;
7477         case I40E_TUNNEL_TYPE_QINQ:
7478                 if (!pf->qinq_replace_flag) {
7479                         ret = i40e_cloud_filter_qinq_create(pf);
7480                         if (ret < 0)
7481                                 PMD_DRV_LOG(DEBUG,
7482                                             "QinQ tunnel filter already created.");
7483                         pf->qinq_replace_flag = 1;
7484                 }
7485                 /*      Add in the General fields the values of
7486                  *      the Outer and Inner VLAN
7487                  *      Big Buffer should be set, see changes in
7488                  *      i40e_aq_add_cloud_filters
7489                  */
7490                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7491                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7492                 big_buffer = 1;
7493                 break;
7494         default:
7495                 /* Other tunnel types is not supported. */
7496                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7497                 rte_free(cld_filter);
7498                 return -EINVAL;
7499         }
7500
7501         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7502                 pfilter->element.flags =
7503                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7504         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7505                 pfilter->element.flags =
7506                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7507         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7508                 pfilter->element.flags =
7509                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7510         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7511                 pfilter->element.flags =
7512                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7513         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7514                 pfilter->element.flags |=
7515                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7516         else {
7517                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7518                                                 &pfilter->element.flags);
7519                 if (val < 0) {
7520                         rte_free(cld_filter);
7521                         return -EINVAL;
7522                 }
7523         }
7524
7525         pfilter->element.flags |= rte_cpu_to_le_16(
7526                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7527                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7528         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7529         pfilter->element.queue_number =
7530                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7531
7532         if (!tunnel_filter->is_to_vf)
7533                 vsi = pf->main_vsi;
7534         else {
7535                 if (tunnel_filter->vf_id >= pf->vf_num) {
7536                         PMD_DRV_LOG(ERR, "Invalid argument.");
7537                         return -EINVAL;
7538                 }
7539                 vf = &pf->vfs[tunnel_filter->vf_id];
7540                 vsi = vf->vsi;
7541         }
7542
7543         /* Check if there is the filter in SW list */
7544         memset(&check_filter, 0, sizeof(check_filter));
7545         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7546         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7547         check_filter.vf_id = tunnel_filter->vf_id;
7548         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7549         if (add && node) {
7550                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7551                 return -EINVAL;
7552         }
7553
7554         if (!add && !node) {
7555                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7556                 return -EINVAL;
7557         }
7558
7559         if (add) {
7560                 if (big_buffer)
7561                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7562                                                    vsi->seid, cld_filter, 1);
7563                 else
7564                         ret = i40e_aq_add_cloud_filters(hw,
7565                                         vsi->seid, &cld_filter->element, 1);
7566                 if (ret < 0) {
7567                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7568                         return -ENOTSUP;
7569                 }
7570                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7571                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7572                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7573         } else {
7574                 if (big_buffer)
7575                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7576                                 hw, vsi->seid, cld_filter, 1);
7577                 else
7578                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7579                                                    &cld_filter->element, 1);
7580                 if (ret < 0) {
7581                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7582                         return -ENOTSUP;
7583                 }
7584                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7585         }
7586
7587         rte_free(cld_filter);
7588         return ret;
7589 }
7590
7591 static int
7592 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7593 {
7594         uint8_t i;
7595
7596         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7597                 if (pf->vxlan_ports[i] == port)
7598                         return i;
7599         }
7600
7601         return -1;
7602 }
7603
7604 static int
7605 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7606 {
7607         int  idx, ret;
7608         uint8_t filter_idx;
7609         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7610
7611         idx = i40e_get_vxlan_port_idx(pf, port);
7612
7613         /* Check if port already exists */
7614         if (idx >= 0) {
7615                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7616                 return -EINVAL;
7617         }
7618
7619         /* Now check if there is space to add the new port */
7620         idx = i40e_get_vxlan_port_idx(pf, 0);
7621         if (idx < 0) {
7622                 PMD_DRV_LOG(ERR,
7623                         "Maximum number of UDP ports reached, not adding port %d",
7624                         port);
7625                 return -ENOSPC;
7626         }
7627
7628         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7629                                         &filter_idx, NULL);
7630         if (ret < 0) {
7631                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7632                 return -1;
7633         }
7634
7635         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7636                          port,  filter_idx);
7637
7638         /* New port: add it and mark its index in the bitmap */
7639         pf->vxlan_ports[idx] = port;
7640         pf->vxlan_bitmap |= (1 << idx);
7641
7642         if (!(pf->flags & I40E_FLAG_VXLAN))
7643                 pf->flags |= I40E_FLAG_VXLAN;
7644
7645         return 0;
7646 }
7647
7648 static int
7649 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7650 {
7651         int idx;
7652         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7653
7654         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7655                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7656                 return -EINVAL;
7657         }
7658
7659         idx = i40e_get_vxlan_port_idx(pf, port);
7660
7661         if (idx < 0) {
7662                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7663                 return -EINVAL;
7664         }
7665
7666         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7667                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7668                 return -1;
7669         }
7670
7671         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7672                         port, idx);
7673
7674         pf->vxlan_ports[idx] = 0;
7675         pf->vxlan_bitmap &= ~(1 << idx);
7676
7677         if (!pf->vxlan_bitmap)
7678                 pf->flags &= ~I40E_FLAG_VXLAN;
7679
7680         return 0;
7681 }
7682
7683 /* Add UDP tunneling port */
7684 static int
7685 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7686                              struct rte_eth_udp_tunnel *udp_tunnel)
7687 {
7688         int ret = 0;
7689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7690
7691         if (udp_tunnel == NULL)
7692                 return -EINVAL;
7693
7694         switch (udp_tunnel->prot_type) {
7695         case RTE_TUNNEL_TYPE_VXLAN:
7696                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7697                 break;
7698
7699         case RTE_TUNNEL_TYPE_GENEVE:
7700         case RTE_TUNNEL_TYPE_TEREDO:
7701                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7702                 ret = -1;
7703                 break;
7704
7705         default:
7706                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7707                 ret = -1;
7708                 break;
7709         }
7710
7711         return ret;
7712 }
7713
7714 /* Remove UDP tunneling port */
7715 static int
7716 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7717                              struct rte_eth_udp_tunnel *udp_tunnel)
7718 {
7719         int ret = 0;
7720         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7721
7722         if (udp_tunnel == NULL)
7723                 return -EINVAL;
7724
7725         switch (udp_tunnel->prot_type) {
7726         case RTE_TUNNEL_TYPE_VXLAN:
7727                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7728                 break;
7729         case RTE_TUNNEL_TYPE_GENEVE:
7730         case RTE_TUNNEL_TYPE_TEREDO:
7731                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7732                 ret = -1;
7733                 break;
7734         default:
7735                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7736                 ret = -1;
7737                 break;
7738         }
7739
7740         return ret;
7741 }
7742
7743 /* Calculate the maximum number of contiguous PF queues that are configured */
7744 static int
7745 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7746 {
7747         struct rte_eth_dev_data *data = pf->dev_data;
7748         int i, num;
7749         struct i40e_rx_queue *rxq;
7750
7751         num = 0;
7752         for (i = 0; i < pf->lan_nb_qps; i++) {
7753                 rxq = data->rx_queues[i];
7754                 if (rxq && rxq->q_set)
7755                         num++;
7756                 else
7757                         break;
7758         }
7759
7760         return num;
7761 }
7762
7763 /* Configure RSS */
7764 static int
7765 i40e_pf_config_rss(struct i40e_pf *pf)
7766 {
7767         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7768         struct rte_eth_rss_conf rss_conf;
7769         uint32_t i, lut = 0;
7770         uint16_t j, num;
7771
7772         /*
7773          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7774          * It's necessary to calculate the actual PF queues that are configured.
7775          */
7776         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7777                 num = i40e_pf_calc_configured_queues_num(pf);
7778         else
7779                 num = pf->dev_data->nb_rx_queues;
7780
7781         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7782         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7783                         num);
7784
7785         if (num == 0) {
7786                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7787                 return -ENOTSUP;
7788         }
7789
7790         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7791                 if (j == num)
7792                         j = 0;
7793                 lut = (lut << 8) | (j & ((0x1 <<
7794                         hw->func_caps.rss_table_entry_width) - 1));
7795                 if ((i & 3) == 3)
7796                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7797         }
7798
7799         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7800         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7801                 i40e_pf_disable_rss(pf);
7802                 return 0;
7803         }
7804         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7805                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7806                 /* Random default keys */
7807                 static uint32_t rss_key_default[] = {0x6b793944,
7808                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7809                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7810                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7811
7812                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7813                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7814                                                         sizeof(uint32_t);
7815         }
7816
7817         return i40e_hw_rss_hash_set(pf, &rss_conf);
7818 }
7819
7820 static int
7821 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7822                                struct rte_eth_tunnel_filter_conf *filter)
7823 {
7824         if (pf == NULL || filter == NULL) {
7825                 PMD_DRV_LOG(ERR, "Invalid parameter");
7826                 return -EINVAL;
7827         }
7828
7829         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7830                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7831                 return -EINVAL;
7832         }
7833
7834         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7835                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7836                 return -EINVAL;
7837         }
7838
7839         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7840                 (is_zero_ether_addr(&filter->outer_mac))) {
7841                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7842                 return -EINVAL;
7843         }
7844
7845         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7846                 (is_zero_ether_addr(&filter->inner_mac))) {
7847                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7848                 return -EINVAL;
7849         }
7850
7851         return 0;
7852 }
7853
7854 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7855 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7856 static int
7857 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7858 {
7859         uint32_t val, reg;
7860         int ret = -EINVAL;
7861
7862         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7863         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7864
7865         if (len == 3) {
7866                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7867         } else if (len == 4) {
7868                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7869         } else {
7870                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7871                 return ret;
7872         }
7873
7874         if (reg != val) {
7875                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7876                                                    reg, NULL);
7877                 if (ret != 0)
7878                         return ret;
7879         } else {
7880                 ret = 0;
7881         }
7882         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7883                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7884
7885         return ret;
7886 }
7887
7888 static int
7889 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7890 {
7891         int ret = -EINVAL;
7892
7893         if (!hw || !cfg)
7894                 return -EINVAL;
7895
7896         switch (cfg->cfg_type) {
7897         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7898                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7899                 break;
7900         default:
7901                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7902                 break;
7903         }
7904
7905         return ret;
7906 }
7907
7908 static int
7909 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7910                                enum rte_filter_op filter_op,
7911                                void *arg)
7912 {
7913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7914         int ret = I40E_ERR_PARAM;
7915
7916         switch (filter_op) {
7917         case RTE_ETH_FILTER_SET:
7918                 ret = i40e_dev_global_config_set(hw,
7919                         (struct rte_eth_global_cfg *)arg);
7920                 break;
7921         default:
7922                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7923                 break;
7924         }
7925
7926         return ret;
7927 }
7928
7929 static int
7930 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7931                           enum rte_filter_op filter_op,
7932                           void *arg)
7933 {
7934         struct rte_eth_tunnel_filter_conf *filter;
7935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7936         int ret = I40E_SUCCESS;
7937
7938         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7939
7940         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7941                 return I40E_ERR_PARAM;
7942
7943         switch (filter_op) {
7944         case RTE_ETH_FILTER_NOP:
7945                 if (!(pf->flags & I40E_FLAG_VXLAN))
7946                         ret = I40E_NOT_SUPPORTED;
7947                 break;
7948         case RTE_ETH_FILTER_ADD:
7949                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7950                 break;
7951         case RTE_ETH_FILTER_DELETE:
7952                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7953                 break;
7954         default:
7955                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7956                 ret = I40E_ERR_PARAM;
7957                 break;
7958         }
7959
7960         return ret;
7961 }
7962
7963 static int
7964 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7965 {
7966         int ret = 0;
7967         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7968
7969         /* RSS setup */
7970         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7971                 ret = i40e_pf_config_rss(pf);
7972         else
7973                 i40e_pf_disable_rss(pf);
7974
7975         return ret;
7976 }
7977
7978 /* Get the symmetric hash enable configurations per port */
7979 static void
7980 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7981 {
7982         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7983
7984         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7985 }
7986
7987 /* Set the symmetric hash enable configurations per port */
7988 static void
7989 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7990 {
7991         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7992
7993         if (enable > 0) {
7994                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7995                         PMD_DRV_LOG(INFO,
7996                                 "Symmetric hash has already been enabled");
7997                         return;
7998                 }
7999                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8000         } else {
8001                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8002                         PMD_DRV_LOG(INFO,
8003                                 "Symmetric hash has already been disabled");
8004                         return;
8005                 }
8006                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8007         }
8008         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8009         I40E_WRITE_FLUSH(hw);
8010 }
8011
8012 /*
8013  * Get global configurations of hash function type and symmetric hash enable
8014  * per flow type (pctype). Note that global configuration means it affects all
8015  * the ports on the same NIC.
8016  */
8017 static int
8018 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8019                                    struct rte_eth_hash_global_conf *g_cfg)
8020 {
8021         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8022         uint32_t reg;
8023         uint16_t i, j;
8024
8025         memset(g_cfg, 0, sizeof(*g_cfg));
8026         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8027         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8028                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8029         else
8030                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8031         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8032                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8033
8034         /*
8035          * We work only with lowest 32 bits which is not correct, but to work
8036          * properly the valid_bit_mask size should be increased up to 64 bits
8037          * and this will brake ABI. This modification will be done in next
8038          * release
8039          */
8040         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8041
8042         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8043                 if (!adapter->pctypes_tbl[i])
8044                         continue;
8045                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8046                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8047                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8048                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8049                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8050                                         g_cfg->sym_hash_enable_mask[0] |=
8051                                                                 (1UL << i);
8052                                 }
8053                         }
8054                 }
8055         }
8056
8057         return 0;
8058 }
8059
8060 static int
8061 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8062                               const struct rte_eth_hash_global_conf *g_cfg)
8063 {
8064         uint32_t i;
8065         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8066
8067         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8068                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8069                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8070                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8071                                                 g_cfg->hash_func);
8072                 return -EINVAL;
8073         }
8074
8075         /*
8076          * As i40e supports less than 32 flow types, only first 32 bits need to
8077          * be checked.
8078          */
8079         mask0 = g_cfg->valid_bit_mask[0];
8080         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8081                 if (i == 0) {
8082                         /* Check if any unsupported flow type configured */
8083                         if ((mask0 | i40e_mask) ^ i40e_mask)
8084                                 goto mask_err;
8085                 } else {
8086                         if (g_cfg->valid_bit_mask[i])
8087                                 goto mask_err;
8088                 }
8089         }
8090
8091         return 0;
8092
8093 mask_err:
8094         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8095
8096         return -EINVAL;
8097 }
8098
8099 /*
8100  * Set global configurations of hash function type and symmetric hash enable
8101  * per flow type (pctype). Note any modifying global configuration will affect
8102  * all the ports on the same NIC.
8103  */
8104 static int
8105 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8106                                    struct rte_eth_hash_global_conf *g_cfg)
8107 {
8108         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8109         int ret;
8110         uint16_t i, j;
8111         uint32_t reg;
8112         /*
8113          * We work only with lowest 32 bits which is not correct, but to work
8114          * properly the valid_bit_mask size should be increased up to 64 bits
8115          * and this will brake ABI. This modification will be done in next
8116          * release
8117          */
8118         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8119                                         (uint32_t)adapter->flow_types_mask;
8120
8121         /* Check the input parameters */
8122         ret = i40e_hash_global_config_check(adapter, g_cfg);
8123         if (ret < 0)
8124                 return ret;
8125
8126         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8127                 if (mask0 & (1UL << i)) {
8128                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8129                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8130
8131                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8132                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8133                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8134                                         i40e_write_rx_ctl(hw,
8135                                                           I40E_GLQF_HSYM(j),
8136                                                           reg);
8137                         }
8138                 }
8139         }
8140
8141         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8142         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8143                 /* Toeplitz */
8144                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8145                         PMD_DRV_LOG(DEBUG,
8146                                 "Hash function already set to Toeplitz");
8147                         goto out;
8148                 }
8149                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8150         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8151                 /* Simple XOR */
8152                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8153                         PMD_DRV_LOG(DEBUG,
8154                                 "Hash function already set to Simple XOR");
8155                         goto out;
8156                 }
8157                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8158         } else
8159                 /* Use the default, and keep it as it is */
8160                 goto out;
8161
8162         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8163
8164 out:
8165         I40E_WRITE_FLUSH(hw);
8166
8167         return 0;
8168 }
8169
8170 /**
8171  * Valid input sets for hash and flow director filters per PCTYPE
8172  */
8173 static uint64_t
8174 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8175                 enum rte_filter_type filter)
8176 {
8177         uint64_t valid;
8178
8179         static const uint64_t valid_hash_inset_table[] = {
8180                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8181                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8182                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8183                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8184                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8185                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8186                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8187                         I40E_INSET_FLEX_PAYLOAD,
8188                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8192                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8193                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8194                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8195                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8196                         I40E_INSET_FLEX_PAYLOAD,
8197                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8198                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8199                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8200                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8201                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8202                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8203                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8204                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8205                         I40E_INSET_FLEX_PAYLOAD,
8206                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8207                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8208                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8209                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8210                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8211                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8212                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8213                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8214                         I40E_INSET_FLEX_PAYLOAD,
8215                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8216                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8217                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8218                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8219                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8220                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8221                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8222                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8223                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8224                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8225                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8226                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8227                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8228                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8229                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8230                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8231                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8232                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8233                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8234                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8235                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8236                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8237                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8238                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8239                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8240                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8241                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8242                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8243                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8244                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8245                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8246                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8247                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8248                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8249                         I40E_INSET_FLEX_PAYLOAD,
8250                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8251                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8252                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8253                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8254                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8255                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8256                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8257                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8258                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8259                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8260                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8261                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8262                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8263                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8264                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8265                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8266                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8267                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8268                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8269                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8270                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8271                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8272                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8273                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8274                         I40E_INSET_FLEX_PAYLOAD,
8275                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8276                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8277                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8278                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8279                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8280                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8281                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8282                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8283                         I40E_INSET_FLEX_PAYLOAD,
8284                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8285                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8286                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8287                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8288                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8289                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8290                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8291                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8292                         I40E_INSET_FLEX_PAYLOAD,
8293                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8294                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8295                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8296                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8297                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8298                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8299                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8300                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8301                         I40E_INSET_FLEX_PAYLOAD,
8302                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8303                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8304                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8305                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8306                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8307                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8308                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8309                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8310                         I40E_INSET_FLEX_PAYLOAD,
8311                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8312                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8313                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8315                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8316                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8317                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8318                         I40E_INSET_FLEX_PAYLOAD,
8319                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8320                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8321                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8322                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8323                         I40E_INSET_FLEX_PAYLOAD,
8324         };
8325
8326         /**
8327          * Flow director supports only fields defined in
8328          * union rte_eth_fdir_flow.
8329          */
8330         static const uint64_t valid_fdir_inset_table[] = {
8331                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8332                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8333                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8334                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8335                 I40E_INSET_IPV4_TTL,
8336                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8337                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8338                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8339                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8340                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8341                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8342                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8343                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8344                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8345                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8346                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8347                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8348                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8349                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8350                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8351                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8352                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8353                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8354                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8355                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8356                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8357                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8358                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8359                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8360                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8361                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8362                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8363                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8364                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8365                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8366                 I40E_INSET_SCTP_VT,
8367                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8368                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8369                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8370                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8371                 I40E_INSET_IPV4_TTL,
8372                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8373                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8374                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8375                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8376                 I40E_INSET_IPV6_HOP_LIMIT,
8377                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8378                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8379                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8380                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8381                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8382                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8383                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8384                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8385                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8386                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8387                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8388                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8389                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8390                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8391                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8392                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8393                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8394                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8395                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8396                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8397                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8398                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8399                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8400                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8401                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8402                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8403                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8404                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8405                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8406                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8407                 I40E_INSET_SCTP_VT,
8408                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8409                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8410                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8411                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8412                 I40E_INSET_IPV6_HOP_LIMIT,
8413                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8414                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8415                 I40E_INSET_LAST_ETHER_TYPE,
8416         };
8417
8418         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8419                 return 0;
8420         if (filter == RTE_ETH_FILTER_HASH)
8421                 valid = valid_hash_inset_table[pctype];
8422         else
8423                 valid = valid_fdir_inset_table[pctype];
8424
8425         return valid;
8426 }
8427
8428 /**
8429  * Validate if the input set is allowed for a specific PCTYPE
8430  */
8431 int
8432 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8433                 enum rte_filter_type filter, uint64_t inset)
8434 {
8435         uint64_t valid;
8436
8437         valid = i40e_get_valid_input_set(pctype, filter);
8438         if (inset & (~valid))
8439                 return -EINVAL;
8440
8441         return 0;
8442 }
8443
8444 /* default input set fields combination per pctype */
8445 uint64_t
8446 i40e_get_default_input_set(uint16_t pctype)
8447 {
8448         static const uint64_t default_inset_table[] = {
8449                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8450                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8451                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8452                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8453                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8454                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8455                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8456                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8457                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8458                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8459                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8460                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8461                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8462                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8463                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8464                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8465                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8466                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8467                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8468                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8469                         I40E_INSET_SCTP_VT,
8470                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8471                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8472                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8473                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8474                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8475                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8476                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8477                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8478                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8479                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8480                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8481                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8482                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8483                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8484                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8485                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8486                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8487                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8488                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8489                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8490                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8491                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8492                         I40E_INSET_SCTP_VT,
8493                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8494                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8495                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8496                         I40E_INSET_LAST_ETHER_TYPE,
8497         };
8498
8499         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8500                 return 0;
8501
8502         return default_inset_table[pctype];
8503 }
8504
8505 /**
8506  * Parse the input set from index to logical bit masks
8507  */
8508 static int
8509 i40e_parse_input_set(uint64_t *inset,
8510                      enum i40e_filter_pctype pctype,
8511                      enum rte_eth_input_set_field *field,
8512                      uint16_t size)
8513 {
8514         uint16_t i, j;
8515         int ret = -EINVAL;
8516
8517         static const struct {
8518                 enum rte_eth_input_set_field field;
8519                 uint64_t inset;
8520         } inset_convert_table[] = {
8521                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8522                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8523                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8524                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8525                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8526                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8527                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8528                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8529                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8530                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8531                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8532                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8533                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8534                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8535                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8536                         I40E_INSET_IPV6_NEXT_HDR},
8537                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8538                         I40E_INSET_IPV6_HOP_LIMIT},
8539                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8540                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8541                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8542                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8543                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8544                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8545                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8546                         I40E_INSET_SCTP_VT},
8547                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8548                         I40E_INSET_TUNNEL_DMAC},
8549                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8550                         I40E_INSET_VLAN_TUNNEL},
8551                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8552                         I40E_INSET_TUNNEL_ID},
8553                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8554                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8555                         I40E_INSET_FLEX_PAYLOAD_W1},
8556                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8557                         I40E_INSET_FLEX_PAYLOAD_W2},
8558                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8559                         I40E_INSET_FLEX_PAYLOAD_W3},
8560                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8561                         I40E_INSET_FLEX_PAYLOAD_W4},
8562                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8563                         I40E_INSET_FLEX_PAYLOAD_W5},
8564                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8565                         I40E_INSET_FLEX_PAYLOAD_W6},
8566                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8567                         I40E_INSET_FLEX_PAYLOAD_W7},
8568                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8569                         I40E_INSET_FLEX_PAYLOAD_W8},
8570         };
8571
8572         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8573                 return ret;
8574
8575         /* Only one item allowed for default or all */
8576         if (size == 1) {
8577                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8578                         *inset = i40e_get_default_input_set(pctype);
8579                         return 0;
8580                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8581                         *inset = I40E_INSET_NONE;
8582                         return 0;
8583                 }
8584         }
8585
8586         for (i = 0, *inset = 0; i < size; i++) {
8587                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8588                         if (field[i] == inset_convert_table[j].field) {
8589                                 *inset |= inset_convert_table[j].inset;
8590                                 break;
8591                         }
8592                 }
8593
8594                 /* It contains unsupported input set, return immediately */
8595                 if (j == RTE_DIM(inset_convert_table))
8596                         return ret;
8597         }
8598
8599         return 0;
8600 }
8601
8602 /**
8603  * Translate the input set from bit masks to register aware bit masks
8604  * and vice versa
8605  */
8606 uint64_t
8607 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8608 {
8609         uint64_t val = 0;
8610         uint16_t i;
8611
8612         struct inset_map {
8613                 uint64_t inset;
8614                 uint64_t inset_reg;
8615         };
8616
8617         static const struct inset_map inset_map_common[] = {
8618                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8619                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8620                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8621                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8622                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8623                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8624                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8625                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8626                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8627                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8628                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8629                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8630                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8631                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8632                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8633                 {I40E_INSET_TUNNEL_DMAC,
8634                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8635                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8636                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8637                 {I40E_INSET_TUNNEL_SRC_PORT,
8638                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8639                 {I40E_INSET_TUNNEL_DST_PORT,
8640                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8641                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8642                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8643                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8644                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8645                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8646                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8647                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8648                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8649                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8650         };
8651
8652     /* some different registers map in x722*/
8653         static const struct inset_map inset_map_diff_x722[] = {
8654                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8655                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8656                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8657                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8658         };
8659
8660         static const struct inset_map inset_map_diff_not_x722[] = {
8661                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8662                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8663                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8664                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8665         };
8666
8667         if (input == 0)
8668                 return val;
8669
8670         /* Translate input set to register aware inset */
8671         if (type == I40E_MAC_X722) {
8672                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8673                         if (input & inset_map_diff_x722[i].inset)
8674                                 val |= inset_map_diff_x722[i].inset_reg;
8675                 }
8676         } else {
8677                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8678                         if (input & inset_map_diff_not_x722[i].inset)
8679                                 val |= inset_map_diff_not_x722[i].inset_reg;
8680                 }
8681         }
8682
8683         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8684                 if (input & inset_map_common[i].inset)
8685                         val |= inset_map_common[i].inset_reg;
8686         }
8687
8688         return val;
8689 }
8690
8691 int
8692 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8693 {
8694         uint8_t i, idx = 0;
8695         uint64_t inset_need_mask = inset;
8696
8697         static const struct {
8698                 uint64_t inset;
8699                 uint32_t mask;
8700         } inset_mask_map[] = {
8701                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8702                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8703                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8704                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8705                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8706                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8707                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8708                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8709         };
8710
8711         if (!inset || !mask || !nb_elem)
8712                 return 0;
8713
8714         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8715                 /* Clear the inset bit, if no MASK is required,
8716                  * for example proto + ttl
8717                  */
8718                 if ((inset & inset_mask_map[i].inset) ==
8719                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8720                         inset_need_mask &= ~inset_mask_map[i].inset;
8721                 if (!inset_need_mask)
8722                         return 0;
8723         }
8724         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8725                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8726                     inset_mask_map[i].inset) {
8727                         if (idx >= nb_elem) {
8728                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8729                                 return -EINVAL;
8730                         }
8731                         mask[idx] = inset_mask_map[i].mask;
8732                         idx++;
8733                 }
8734         }
8735
8736         return idx;
8737 }
8738
8739 void
8740 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8741 {
8742         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8743
8744         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8745         if (reg != val)
8746                 i40e_write_rx_ctl(hw, addr, val);
8747         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8748                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8749 }
8750
8751 static void
8752 i40e_filter_input_set_init(struct i40e_pf *pf)
8753 {
8754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8755         enum i40e_filter_pctype pctype;
8756         uint64_t input_set, inset_reg;
8757         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8758         int num, i;
8759         uint16_t flow_type;
8760
8761         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8762              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8763                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8764
8765                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8766                         continue;
8767
8768                 input_set = i40e_get_default_input_set(pctype);
8769
8770                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8771                                                    I40E_INSET_MASK_NUM_REG);
8772                 if (num < 0)
8773                         return;
8774                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8775                                         input_set);
8776
8777                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8778                                       (uint32_t)(inset_reg & UINT32_MAX));
8779                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8780                                      (uint32_t)((inset_reg >>
8781                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8782                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8783                                       (uint32_t)(inset_reg & UINT32_MAX));
8784                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8785                                      (uint32_t)((inset_reg >>
8786                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8787
8788                 for (i = 0; i < num; i++) {
8789                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8790                                              mask_reg[i]);
8791                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8792                                              mask_reg[i]);
8793                 }
8794                 /*clear unused mask registers of the pctype */
8795                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8796                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8797                                              0);
8798                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8799                                              0);
8800                 }
8801                 I40E_WRITE_FLUSH(hw);
8802
8803                 /* store the default input set */
8804                 pf->hash_input_set[pctype] = input_set;
8805                 pf->fdir.input_set[pctype] = input_set;
8806         }
8807 }
8808
8809 int
8810 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8811                          struct rte_eth_input_set_conf *conf)
8812 {
8813         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8814         enum i40e_filter_pctype pctype;
8815         uint64_t input_set, inset_reg = 0;
8816         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8817         int ret, i, num;
8818
8819         if (!conf) {
8820                 PMD_DRV_LOG(ERR, "Invalid pointer");
8821                 return -EFAULT;
8822         }
8823         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8824             conf->op != RTE_ETH_INPUT_SET_ADD) {
8825                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8826                 return -EINVAL;
8827         }
8828
8829         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8830         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8831                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8832                 return -EINVAL;
8833         }
8834
8835         if (hw->mac.type == I40E_MAC_X722) {
8836                 /* get translated pctype value in fd pctype register */
8837                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8838                         I40E_GLQF_FD_PCTYPES((int)pctype));
8839         }
8840
8841         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8842                                    conf->inset_size);
8843         if (ret) {
8844                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8845                 return -EINVAL;
8846         }
8847
8848         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8849                 /* get inset value in register */
8850                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8851                 inset_reg <<= I40E_32_BIT_WIDTH;
8852                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8853                 input_set |= pf->hash_input_set[pctype];
8854         }
8855         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8856                                            I40E_INSET_MASK_NUM_REG);
8857         if (num < 0)
8858                 return -EINVAL;
8859
8860         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8861
8862         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8863                               (uint32_t)(inset_reg & UINT32_MAX));
8864         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8865                              (uint32_t)((inset_reg >>
8866                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8867
8868         for (i = 0; i < num; i++)
8869                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8870                                      mask_reg[i]);
8871         /*clear unused mask registers of the pctype */
8872         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8873                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8874                                      0);
8875         I40E_WRITE_FLUSH(hw);
8876
8877         pf->hash_input_set[pctype] = input_set;
8878         return 0;
8879 }
8880
8881 int
8882 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8883                          struct rte_eth_input_set_conf *conf)
8884 {
8885         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8886         enum i40e_filter_pctype pctype;
8887         uint64_t input_set, inset_reg = 0;
8888         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8889         int ret, i, num;
8890
8891         if (!hw || !conf) {
8892                 PMD_DRV_LOG(ERR, "Invalid pointer");
8893                 return -EFAULT;
8894         }
8895         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8896             conf->op != RTE_ETH_INPUT_SET_ADD) {
8897                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8898                 return -EINVAL;
8899         }
8900
8901         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8902
8903         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8904                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8905                 return -EINVAL;
8906         }
8907
8908         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8909                                    conf->inset_size);
8910         if (ret) {
8911                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8912                 return -EINVAL;
8913         }
8914
8915         /* get inset value in register */
8916         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8917         inset_reg <<= I40E_32_BIT_WIDTH;
8918         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8919
8920         /* Can not change the inset reg for flex payload for fdir,
8921          * it is done by writing I40E_PRTQF_FD_FLXINSET
8922          * in i40e_set_flex_mask_on_pctype.
8923          */
8924         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8925                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8926         else
8927                 input_set |= pf->fdir.input_set[pctype];
8928         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8929                                            I40E_INSET_MASK_NUM_REG);
8930         if (num < 0)
8931                 return -EINVAL;
8932
8933         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8934
8935         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8936                               (uint32_t)(inset_reg & UINT32_MAX));
8937         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8938                              (uint32_t)((inset_reg >>
8939                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8940
8941         for (i = 0; i < num; i++)
8942                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8943                                      mask_reg[i]);
8944         /*clear unused mask registers of the pctype */
8945         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8946                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8947                                      0);
8948         I40E_WRITE_FLUSH(hw);
8949
8950         pf->fdir.input_set[pctype] = input_set;
8951         return 0;
8952 }
8953
8954 static int
8955 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8956 {
8957         int ret = 0;
8958
8959         if (!hw || !info) {
8960                 PMD_DRV_LOG(ERR, "Invalid pointer");
8961                 return -EFAULT;
8962         }
8963
8964         switch (info->info_type) {
8965         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8966                 i40e_get_symmetric_hash_enable_per_port(hw,
8967                                         &(info->info.enable));
8968                 break;
8969         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8970                 ret = i40e_get_hash_filter_global_config(hw,
8971                                 &(info->info.global_conf));
8972                 break;
8973         default:
8974                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8975                                                         info->info_type);
8976                 ret = -EINVAL;
8977                 break;
8978         }
8979
8980         return ret;
8981 }
8982
8983 static int
8984 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8985 {
8986         int ret = 0;
8987
8988         if (!hw || !info) {
8989                 PMD_DRV_LOG(ERR, "Invalid pointer");
8990                 return -EFAULT;
8991         }
8992
8993         switch (info->info_type) {
8994         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8995                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8996                 break;
8997         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8998                 ret = i40e_set_hash_filter_global_config(hw,
8999                                 &(info->info.global_conf));
9000                 break;
9001         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9002                 ret = i40e_hash_filter_inset_select(hw,
9003                                                &(info->info.input_set_conf));
9004                 break;
9005
9006         default:
9007                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9008                                                         info->info_type);
9009                 ret = -EINVAL;
9010                 break;
9011         }
9012
9013         return ret;
9014 }
9015
9016 /* Operations for hash function */
9017 static int
9018 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9019                       enum rte_filter_op filter_op,
9020                       void *arg)
9021 {
9022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9023         int ret = 0;
9024
9025         switch (filter_op) {
9026         case RTE_ETH_FILTER_NOP:
9027                 break;
9028         case RTE_ETH_FILTER_GET:
9029                 ret = i40e_hash_filter_get(hw,
9030                         (struct rte_eth_hash_filter_info *)arg);
9031                 break;
9032         case RTE_ETH_FILTER_SET:
9033                 ret = i40e_hash_filter_set(hw,
9034                         (struct rte_eth_hash_filter_info *)arg);
9035                 break;
9036         default:
9037                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9038                                                                 filter_op);
9039                 ret = -ENOTSUP;
9040                 break;
9041         }
9042
9043         return ret;
9044 }
9045
9046 /* Convert ethertype filter structure */
9047 static int
9048 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9049                               struct i40e_ethertype_filter *filter)
9050 {
9051         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9052         filter->input.ether_type = input->ether_type;
9053         filter->flags = input->flags;
9054         filter->queue = input->queue;
9055
9056         return 0;
9057 }
9058
9059 /* Check if there exists the ehtertype filter */
9060 struct i40e_ethertype_filter *
9061 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9062                                 const struct i40e_ethertype_filter_input *input)
9063 {
9064         int ret;
9065
9066         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9067         if (ret < 0)
9068                 return NULL;
9069
9070         return ethertype_rule->hash_map[ret];
9071 }
9072
9073 /* Add ethertype filter in SW list */
9074 static int
9075 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9076                                 struct i40e_ethertype_filter *filter)
9077 {
9078         struct i40e_ethertype_rule *rule = &pf->ethertype;
9079         int ret;
9080
9081         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9082         if (ret < 0) {
9083                 PMD_DRV_LOG(ERR,
9084                             "Failed to insert ethertype filter"
9085                             " to hash table %d!",
9086                             ret);
9087                 return ret;
9088         }
9089         rule->hash_map[ret] = filter;
9090
9091         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9092
9093         return 0;
9094 }
9095
9096 /* Delete ethertype filter in SW list */
9097 int
9098 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9099                              struct i40e_ethertype_filter_input *input)
9100 {
9101         struct i40e_ethertype_rule *rule = &pf->ethertype;
9102         struct i40e_ethertype_filter *filter;
9103         int ret;
9104
9105         ret = rte_hash_del_key(rule->hash_table, input);
9106         if (ret < 0) {
9107                 PMD_DRV_LOG(ERR,
9108                             "Failed to delete ethertype filter"
9109                             " to hash table %d!",
9110                             ret);
9111                 return ret;
9112         }
9113         filter = rule->hash_map[ret];
9114         rule->hash_map[ret] = NULL;
9115
9116         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9117         rte_free(filter);
9118
9119         return 0;
9120 }
9121
9122 /*
9123  * Configure ethertype filter, which can director packet by filtering
9124  * with mac address and ether_type or only ether_type
9125  */
9126 int
9127 i40e_ethertype_filter_set(struct i40e_pf *pf,
9128                         struct rte_eth_ethertype_filter *filter,
9129                         bool add)
9130 {
9131         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9132         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9133         struct i40e_ethertype_filter *ethertype_filter, *node;
9134         struct i40e_ethertype_filter check_filter;
9135         struct i40e_control_filter_stats stats;
9136         uint16_t flags = 0;
9137         int ret;
9138
9139         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9140                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9141                 return -EINVAL;
9142         }
9143         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9144                 filter->ether_type == ETHER_TYPE_IPv6) {
9145                 PMD_DRV_LOG(ERR,
9146                         "unsupported ether_type(0x%04x) in control packet filter.",
9147                         filter->ether_type);
9148                 return -EINVAL;
9149         }
9150         if (filter->ether_type == ETHER_TYPE_VLAN)
9151                 PMD_DRV_LOG(WARNING,
9152                         "filter vlan ether_type in first tag is not supported.");
9153
9154         /* Check if there is the filter in SW list */
9155         memset(&check_filter, 0, sizeof(check_filter));
9156         i40e_ethertype_filter_convert(filter, &check_filter);
9157         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9158                                                &check_filter.input);
9159         if (add && node) {
9160                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9161                 return -EINVAL;
9162         }
9163
9164         if (!add && !node) {
9165                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9166                 return -EINVAL;
9167         }
9168
9169         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9170                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9171         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9172                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9173         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9174
9175         memset(&stats, 0, sizeof(stats));
9176         ret = i40e_aq_add_rem_control_packet_filter(hw,
9177                         filter->mac_addr.addr_bytes,
9178                         filter->ether_type, flags,
9179                         pf->main_vsi->seid,
9180                         filter->queue, add, &stats, NULL);
9181
9182         PMD_DRV_LOG(INFO,
9183                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9184                 ret, stats.mac_etype_used, stats.etype_used,
9185                 stats.mac_etype_free, stats.etype_free);
9186         if (ret < 0)
9187                 return -ENOSYS;
9188
9189         /* Add or delete a filter in SW list */
9190         if (add) {
9191                 ethertype_filter = rte_zmalloc("ethertype_filter",
9192                                        sizeof(*ethertype_filter), 0);
9193                 rte_memcpy(ethertype_filter, &check_filter,
9194                            sizeof(check_filter));
9195                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9196         } else {
9197                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9198         }
9199
9200         return ret;
9201 }
9202
9203 /*
9204  * Handle operations for ethertype filter.
9205  */
9206 static int
9207 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9208                                 enum rte_filter_op filter_op,
9209                                 void *arg)
9210 {
9211         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9212         int ret = 0;
9213
9214         if (filter_op == RTE_ETH_FILTER_NOP)
9215                 return ret;
9216
9217         if (arg == NULL) {
9218                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9219                             filter_op);
9220                 return -EINVAL;
9221         }
9222
9223         switch (filter_op) {
9224         case RTE_ETH_FILTER_ADD:
9225                 ret = i40e_ethertype_filter_set(pf,
9226                         (struct rte_eth_ethertype_filter *)arg,
9227                         TRUE);
9228                 break;
9229         case RTE_ETH_FILTER_DELETE:
9230                 ret = i40e_ethertype_filter_set(pf,
9231                         (struct rte_eth_ethertype_filter *)arg,
9232                         FALSE);
9233                 break;
9234         default:
9235                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9236                 ret = -ENOSYS;
9237                 break;
9238         }
9239         return ret;
9240 }
9241
9242 static int
9243 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9244                      enum rte_filter_type filter_type,
9245                      enum rte_filter_op filter_op,
9246                      void *arg)
9247 {
9248         int ret = 0;
9249
9250         if (dev == NULL)
9251                 return -EINVAL;
9252
9253         switch (filter_type) {
9254         case RTE_ETH_FILTER_NONE:
9255                 /* For global configuration */
9256                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9257                 break;
9258         case RTE_ETH_FILTER_HASH:
9259                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9260                 break;
9261         case RTE_ETH_FILTER_MACVLAN:
9262                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9263                 break;
9264         case RTE_ETH_FILTER_ETHERTYPE:
9265                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9266                 break;
9267         case RTE_ETH_FILTER_TUNNEL:
9268                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9269                 break;
9270         case RTE_ETH_FILTER_FDIR:
9271                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9272                 break;
9273         case RTE_ETH_FILTER_GENERIC:
9274                 if (filter_op != RTE_ETH_FILTER_GET)
9275                         return -EINVAL;
9276                 *(const void **)arg = &i40e_flow_ops;
9277                 break;
9278         default:
9279                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9280                                                         filter_type);
9281                 ret = -EINVAL;
9282                 break;
9283         }
9284
9285         return ret;
9286 }
9287
9288 /*
9289  * Check and enable Extended Tag.
9290  * Enabling Extended Tag is important for 40G performance.
9291  */
9292 static void
9293 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9294 {
9295         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9296         uint32_t buf = 0;
9297         int ret;
9298
9299         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9300                                       PCI_DEV_CAP_REG);
9301         if (ret < 0) {
9302                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9303                             PCI_DEV_CAP_REG);
9304                 return;
9305         }
9306         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9307                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9308                 return;
9309         }
9310
9311         buf = 0;
9312         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9313                                       PCI_DEV_CTRL_REG);
9314         if (ret < 0) {
9315                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9316                             PCI_DEV_CTRL_REG);
9317                 return;
9318         }
9319         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9320                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9321                 return;
9322         }
9323         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9324         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9325                                        PCI_DEV_CTRL_REG);
9326         if (ret < 0) {
9327                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9328                             PCI_DEV_CTRL_REG);
9329                 return;
9330         }
9331 }
9332
9333 /*
9334  * As some registers wouldn't be reset unless a global hardware reset,
9335  * hardware initialization is needed to put those registers into an
9336  * expected initial state.
9337  */
9338 static void
9339 i40e_hw_init(struct rte_eth_dev *dev)
9340 {
9341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9342
9343         i40e_enable_extended_tag(dev);
9344
9345         /* clear the PF Queue Filter control register */
9346         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9347
9348         /* Disable symmetric hash per port */
9349         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9350 }
9351
9352 /*
9353  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9354  * however this function will return only one highest pctype index,
9355  * which is not quite correct. This is known problem of i40e driver
9356  * and needs to be fixed later.
9357  */
9358 enum i40e_filter_pctype
9359 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9360 {
9361         int i;
9362         uint64_t pctype_mask;
9363
9364         if (flow_type < I40E_FLOW_TYPE_MAX) {
9365                 pctype_mask = adapter->pctypes_tbl[flow_type];
9366                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9367                         if (pctype_mask & (1ULL << i))
9368                                 return (enum i40e_filter_pctype)i;
9369                 }
9370         }
9371         return I40E_FILTER_PCTYPE_INVALID;
9372 }
9373
9374 uint16_t
9375 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9376                         enum i40e_filter_pctype pctype)
9377 {
9378         uint16_t flowtype;
9379         uint64_t pctype_mask = 1ULL << pctype;
9380
9381         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9382              flowtype++) {
9383                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9384                         return flowtype;
9385         }
9386
9387         return RTE_ETH_FLOW_UNKNOWN;
9388 }
9389
9390 /*
9391  * On X710, performance number is far from the expectation on recent firmware
9392  * versions; on XL710, performance number is also far from the expectation on
9393  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9394  * mode is enabled and port MAC address is equal to the packet destination MAC
9395  * address. The fix for this issue may not be integrated in the following
9396  * firmware version. So the workaround in software driver is needed. It needs
9397  * to modify the initial values of 3 internal only registers for both X710 and
9398  * XL710. Note that the values for X710 or XL710 could be different, and the
9399  * workaround can be removed when it is fixed in firmware in the future.
9400  */
9401
9402 /* For both X710 and XL710 */
9403 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9404 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9405 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9406
9407 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9408 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9409
9410 /* For X722 */
9411 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9412 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9413
9414 /* For X710 */
9415 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9416 /* For XL710 */
9417 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9418 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9419
9420 static int
9421 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9422 {
9423         enum i40e_status_code status;
9424         struct i40e_aq_get_phy_abilities_resp phy_ab;
9425         int ret = -ENOTSUP;
9426         int retries = 0;
9427
9428         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9429                                               NULL);
9430
9431         while (status) {
9432                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9433                         status);
9434                 retries++;
9435                 rte_delay_us(100000);
9436                 if  (retries < 5)
9437                         status = i40e_aq_get_phy_capabilities(hw, false,
9438                                         true, &phy_ab, NULL);
9439                 else
9440                         return ret;
9441         }
9442         return 0;
9443 }
9444
9445 static void
9446 i40e_configure_registers(struct i40e_hw *hw)
9447 {
9448         static struct {
9449                 uint32_t addr;
9450                 uint64_t val;
9451         } reg_table[] = {
9452                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9453                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9454                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9455         };
9456         uint64_t reg;
9457         uint32_t i;
9458         int ret;
9459
9460         for (i = 0; i < RTE_DIM(reg_table); i++) {
9461                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9462                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9463                                 reg_table[i].val =
9464                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9465                         else /* For X710/XL710/XXV710 */
9466                                 if (hw->aq.fw_maj_ver < 6)
9467                                         reg_table[i].val =
9468                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9469                                 else
9470                                         reg_table[i].val =
9471                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9472                 }
9473
9474                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9475                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9476                                 reg_table[i].val =
9477                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9478                         else /* For X710/XL710/XXV710 */
9479                                 reg_table[i].val =
9480                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9481                 }
9482
9483                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9484                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9485                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9486                                 reg_table[i].val =
9487                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9488                         else /* For X710 */
9489                                 reg_table[i].val =
9490                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9491                 }
9492
9493                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9494                                                         &reg, NULL);
9495                 if (ret < 0) {
9496                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9497                                                         reg_table[i].addr);
9498                         break;
9499                 }
9500                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9501                                                 reg_table[i].addr, reg);
9502                 if (reg == reg_table[i].val)
9503                         continue;
9504
9505                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9506                                                 reg_table[i].val, NULL);
9507                 if (ret < 0) {
9508                         PMD_DRV_LOG(ERR,
9509                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9510                                 reg_table[i].val, reg_table[i].addr);
9511                         break;
9512                 }
9513                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9514                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9515         }
9516 }
9517
9518 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9519 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9520 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9521 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9522 static int
9523 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9524 {
9525         uint32_t reg;
9526         int ret;
9527
9528         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9529                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9530                 return -EINVAL;
9531         }
9532
9533         /* Configure for double VLAN RX stripping */
9534         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9535         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9536                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9537                 ret = i40e_aq_debug_write_register(hw,
9538                                                    I40E_VSI_TSR(vsi->vsi_id),
9539                                                    reg, NULL);
9540                 if (ret < 0) {
9541                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9542                                     vsi->vsi_id);
9543                         return I40E_ERR_CONFIG;
9544                 }
9545         }
9546
9547         /* Configure for double VLAN TX insertion */
9548         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9549         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9550                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9551                 ret = i40e_aq_debug_write_register(hw,
9552                                                    I40E_VSI_L2TAGSTXVALID(
9553                                                    vsi->vsi_id), reg, NULL);
9554                 if (ret < 0) {
9555                         PMD_DRV_LOG(ERR,
9556                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9557                                 vsi->vsi_id);
9558                         return I40E_ERR_CONFIG;
9559                 }
9560         }
9561
9562         return 0;
9563 }
9564
9565 /**
9566  * i40e_aq_add_mirror_rule
9567  * @hw: pointer to the hardware structure
9568  * @seid: VEB seid to add mirror rule to
9569  * @dst_id: destination vsi seid
9570  * @entries: Buffer which contains the entities to be mirrored
9571  * @count: number of entities contained in the buffer
9572  * @rule_id:the rule_id of the rule to be added
9573  *
9574  * Add a mirror rule for a given veb.
9575  *
9576  **/
9577 static enum i40e_status_code
9578 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9579                         uint16_t seid, uint16_t dst_id,
9580                         uint16_t rule_type, uint16_t *entries,
9581                         uint16_t count, uint16_t *rule_id)
9582 {
9583         struct i40e_aq_desc desc;
9584         struct i40e_aqc_add_delete_mirror_rule cmd;
9585         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9586                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9587                 &desc.params.raw;
9588         uint16_t buff_len;
9589         enum i40e_status_code status;
9590
9591         i40e_fill_default_direct_cmd_desc(&desc,
9592                                           i40e_aqc_opc_add_mirror_rule);
9593         memset(&cmd, 0, sizeof(cmd));
9594
9595         buff_len = sizeof(uint16_t) * count;
9596         desc.datalen = rte_cpu_to_le_16(buff_len);
9597         if (buff_len > 0)
9598                 desc.flags |= rte_cpu_to_le_16(
9599                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9600         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9601                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9602         cmd.num_entries = rte_cpu_to_le_16(count);
9603         cmd.seid = rte_cpu_to_le_16(seid);
9604         cmd.destination = rte_cpu_to_le_16(dst_id);
9605
9606         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9607         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9608         PMD_DRV_LOG(INFO,
9609                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9610                 hw->aq.asq_last_status, resp->rule_id,
9611                 resp->mirror_rules_used, resp->mirror_rules_free);
9612         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9613
9614         return status;
9615 }
9616
9617 /**
9618  * i40e_aq_del_mirror_rule
9619  * @hw: pointer to the hardware structure
9620  * @seid: VEB seid to add mirror rule to
9621  * @entries: Buffer which contains the entities to be mirrored
9622  * @count: number of entities contained in the buffer
9623  * @rule_id:the rule_id of the rule to be delete
9624  *
9625  * Delete a mirror rule for a given veb.
9626  *
9627  **/
9628 static enum i40e_status_code
9629 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9630                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9631                 uint16_t count, uint16_t rule_id)
9632 {
9633         struct i40e_aq_desc desc;
9634         struct i40e_aqc_add_delete_mirror_rule cmd;
9635         uint16_t buff_len = 0;
9636         enum i40e_status_code status;
9637         void *buff = NULL;
9638
9639         i40e_fill_default_direct_cmd_desc(&desc,
9640                                           i40e_aqc_opc_delete_mirror_rule);
9641         memset(&cmd, 0, sizeof(cmd));
9642         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9643                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9644                                                           I40E_AQ_FLAG_RD));
9645                 cmd.num_entries = count;
9646                 buff_len = sizeof(uint16_t) * count;
9647                 desc.datalen = rte_cpu_to_le_16(buff_len);
9648                 buff = (void *)entries;
9649         } else
9650                 /* rule id is filled in destination field for deleting mirror rule */
9651                 cmd.destination = rte_cpu_to_le_16(rule_id);
9652
9653         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9654                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9655         cmd.seid = rte_cpu_to_le_16(seid);
9656
9657         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9658         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9659
9660         return status;
9661 }
9662
9663 /**
9664  * i40e_mirror_rule_set
9665  * @dev: pointer to the hardware structure
9666  * @mirror_conf: mirror rule info
9667  * @sw_id: mirror rule's sw_id
9668  * @on: enable/disable
9669  *
9670  * set a mirror rule.
9671  *
9672  **/
9673 static int
9674 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9675                         struct rte_eth_mirror_conf *mirror_conf,
9676                         uint8_t sw_id, uint8_t on)
9677 {
9678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9680         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9681         struct i40e_mirror_rule *parent = NULL;
9682         uint16_t seid, dst_seid, rule_id;
9683         uint16_t i, j = 0;
9684         int ret;
9685
9686         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9687
9688         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9689                 PMD_DRV_LOG(ERR,
9690                         "mirror rule can not be configured without veb or vfs.");
9691                 return -ENOSYS;
9692         }
9693         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9694                 PMD_DRV_LOG(ERR, "mirror table is full.");
9695                 return -ENOSPC;
9696         }
9697         if (mirror_conf->dst_pool > pf->vf_num) {
9698                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9699                                  mirror_conf->dst_pool);
9700                 return -EINVAL;
9701         }
9702
9703         seid = pf->main_vsi->veb->seid;
9704
9705         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9706                 if (sw_id <= it->index) {
9707                         mirr_rule = it;
9708                         break;
9709                 }
9710                 parent = it;
9711         }
9712         if (mirr_rule && sw_id == mirr_rule->index) {
9713                 if (on) {
9714                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9715                         return -EEXIST;
9716                 } else {
9717                         ret = i40e_aq_del_mirror_rule(hw, seid,
9718                                         mirr_rule->rule_type,
9719                                         mirr_rule->entries,
9720                                         mirr_rule->num_entries, mirr_rule->id);
9721                         if (ret < 0) {
9722                                 PMD_DRV_LOG(ERR,
9723                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9724                                         ret, hw->aq.asq_last_status);
9725                                 return -ENOSYS;
9726                         }
9727                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9728                         rte_free(mirr_rule);
9729                         pf->nb_mirror_rule--;
9730                         return 0;
9731                 }
9732         } else if (!on) {
9733                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9734                 return -ENOENT;
9735         }
9736
9737         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9738                                 sizeof(struct i40e_mirror_rule) , 0);
9739         if (!mirr_rule) {
9740                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9741                 return I40E_ERR_NO_MEMORY;
9742         }
9743         switch (mirror_conf->rule_type) {
9744         case ETH_MIRROR_VLAN:
9745                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9746                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9747                                 mirr_rule->entries[j] =
9748                                         mirror_conf->vlan.vlan_id[i];
9749                                 j++;
9750                         }
9751                 }
9752                 if (j == 0) {
9753                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9754                         rte_free(mirr_rule);
9755                         return -EINVAL;
9756                 }
9757                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9758                 break;
9759         case ETH_MIRROR_VIRTUAL_POOL_UP:
9760         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9761                 /* check if the specified pool bit is out of range */
9762                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9763                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9764                         rte_free(mirr_rule);
9765                         return -EINVAL;
9766                 }
9767                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9768                         if (mirror_conf->pool_mask & (1ULL << i)) {
9769                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9770                                 j++;
9771                         }
9772                 }
9773                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9774                         /* add pf vsi to entries */
9775                         mirr_rule->entries[j] = pf->main_vsi_seid;
9776                         j++;
9777                 }
9778                 if (j == 0) {
9779                         PMD_DRV_LOG(ERR, "pool is not specified.");
9780                         rte_free(mirr_rule);
9781                         return -EINVAL;
9782                 }
9783                 /* egress and ingress in aq commands means from switch but not port */
9784                 mirr_rule->rule_type =
9785                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9786                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9787                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9788                 break;
9789         case ETH_MIRROR_UPLINK_PORT:
9790                 /* egress and ingress in aq commands means from switch but not port*/
9791                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9792                 break;
9793         case ETH_MIRROR_DOWNLINK_PORT:
9794                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9795                 break;
9796         default:
9797                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9798                         mirror_conf->rule_type);
9799                 rte_free(mirr_rule);
9800                 return -EINVAL;
9801         }
9802
9803         /* If the dst_pool is equal to vf_num, consider it as PF */
9804         if (mirror_conf->dst_pool == pf->vf_num)
9805                 dst_seid = pf->main_vsi_seid;
9806         else
9807                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9808
9809         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9810                                       mirr_rule->rule_type, mirr_rule->entries,
9811                                       j, &rule_id);
9812         if (ret < 0) {
9813                 PMD_DRV_LOG(ERR,
9814                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9815                         ret, hw->aq.asq_last_status);
9816                 rte_free(mirr_rule);
9817                 return -ENOSYS;
9818         }
9819
9820         mirr_rule->index = sw_id;
9821         mirr_rule->num_entries = j;
9822         mirr_rule->id = rule_id;
9823         mirr_rule->dst_vsi_seid = dst_seid;
9824
9825         if (parent)
9826                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9827         else
9828                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9829
9830         pf->nb_mirror_rule++;
9831         return 0;
9832 }
9833
9834 /**
9835  * i40e_mirror_rule_reset
9836  * @dev: pointer to the device
9837  * @sw_id: mirror rule's sw_id
9838  *
9839  * reset a mirror rule.
9840  *
9841  **/
9842 static int
9843 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9844 {
9845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9847         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9848         uint16_t seid;
9849         int ret;
9850
9851         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9852
9853         seid = pf->main_vsi->veb->seid;
9854
9855         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9856                 if (sw_id == it->index) {
9857                         mirr_rule = it;
9858                         break;
9859                 }
9860         }
9861         if (mirr_rule) {
9862                 ret = i40e_aq_del_mirror_rule(hw, seid,
9863                                 mirr_rule->rule_type,
9864                                 mirr_rule->entries,
9865                                 mirr_rule->num_entries, mirr_rule->id);
9866                 if (ret < 0) {
9867                         PMD_DRV_LOG(ERR,
9868                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9869                                 ret, hw->aq.asq_last_status);
9870                         return -ENOSYS;
9871                 }
9872                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9873                 rte_free(mirr_rule);
9874                 pf->nb_mirror_rule--;
9875         } else {
9876                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9877                 return -ENOENT;
9878         }
9879         return 0;
9880 }
9881
9882 static uint64_t
9883 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9884 {
9885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9886         uint64_t systim_cycles;
9887
9888         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9889         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9890                         << 32;
9891
9892         return systim_cycles;
9893 }
9894
9895 static uint64_t
9896 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9897 {
9898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9899         uint64_t rx_tstamp;
9900
9901         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9902         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9903                         << 32;
9904
9905         return rx_tstamp;
9906 }
9907
9908 static uint64_t
9909 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9910 {
9911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9912         uint64_t tx_tstamp;
9913
9914         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9915         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9916                         << 32;
9917
9918         return tx_tstamp;
9919 }
9920
9921 static void
9922 i40e_start_timecounters(struct rte_eth_dev *dev)
9923 {
9924         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9925         struct i40e_adapter *adapter =
9926                         (struct i40e_adapter *)dev->data->dev_private;
9927         struct rte_eth_link link;
9928         uint32_t tsync_inc_l;
9929         uint32_t tsync_inc_h;
9930
9931         /* Get current link speed. */
9932         memset(&link, 0, sizeof(link));
9933         i40e_dev_link_update(dev, 1);
9934         rte_i40e_dev_atomic_read_link_status(dev, &link);
9935
9936         switch (link.link_speed) {
9937         case ETH_SPEED_NUM_40G:
9938                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9939                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9940                 break;
9941         case ETH_SPEED_NUM_10G:
9942                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9943                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9944                 break;
9945         case ETH_SPEED_NUM_1G:
9946                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9947                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9948                 break;
9949         default:
9950                 tsync_inc_l = 0x0;
9951                 tsync_inc_h = 0x0;
9952         }
9953
9954         /* Set the timesync increment value. */
9955         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9956         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9957
9958         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9959         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9960         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9961
9962         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9963         adapter->systime_tc.cc_shift = 0;
9964         adapter->systime_tc.nsec_mask = 0;
9965
9966         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9967         adapter->rx_tstamp_tc.cc_shift = 0;
9968         adapter->rx_tstamp_tc.nsec_mask = 0;
9969
9970         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9971         adapter->tx_tstamp_tc.cc_shift = 0;
9972         adapter->tx_tstamp_tc.nsec_mask = 0;
9973 }
9974
9975 static int
9976 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9977 {
9978         struct i40e_adapter *adapter =
9979                         (struct i40e_adapter *)dev->data->dev_private;
9980
9981         adapter->systime_tc.nsec += delta;
9982         adapter->rx_tstamp_tc.nsec += delta;
9983         adapter->tx_tstamp_tc.nsec += delta;
9984
9985         return 0;
9986 }
9987
9988 static int
9989 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9990 {
9991         uint64_t ns;
9992         struct i40e_adapter *adapter =
9993                         (struct i40e_adapter *)dev->data->dev_private;
9994
9995         ns = rte_timespec_to_ns(ts);
9996
9997         /* Set the timecounters to a new value. */
9998         adapter->systime_tc.nsec = ns;
9999         adapter->rx_tstamp_tc.nsec = ns;
10000         adapter->tx_tstamp_tc.nsec = ns;
10001
10002         return 0;
10003 }
10004
10005 static int
10006 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10007 {
10008         uint64_t ns, systime_cycles;
10009         struct i40e_adapter *adapter =
10010                         (struct i40e_adapter *)dev->data->dev_private;
10011
10012         systime_cycles = i40e_read_systime_cyclecounter(dev);
10013         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10014         *ts = rte_ns_to_timespec(ns);
10015
10016         return 0;
10017 }
10018
10019 static int
10020 i40e_timesync_enable(struct rte_eth_dev *dev)
10021 {
10022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10023         uint32_t tsync_ctl_l;
10024         uint32_t tsync_ctl_h;
10025
10026         /* Stop the timesync system time. */
10027         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10028         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10029         /* Reset the timesync system time value. */
10030         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10031         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10032
10033         i40e_start_timecounters(dev);
10034
10035         /* Clear timesync registers. */
10036         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10037         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10038         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10039         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10040         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10041         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10042
10043         /* Enable timestamping of PTP packets. */
10044         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10045         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10046
10047         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10048         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10049         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10050
10051         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10052         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10053
10054         return 0;
10055 }
10056
10057 static int
10058 i40e_timesync_disable(struct rte_eth_dev *dev)
10059 {
10060         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10061         uint32_t tsync_ctl_l;
10062         uint32_t tsync_ctl_h;
10063
10064         /* Disable timestamping of transmitted PTP packets. */
10065         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10066         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10067
10068         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10069         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10070
10071         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10072         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10073
10074         /* Reset the timesync increment value. */
10075         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10076         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10077
10078         return 0;
10079 }
10080
10081 static int
10082 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10083                                 struct timespec *timestamp, uint32_t flags)
10084 {
10085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10086         struct i40e_adapter *adapter =
10087                 (struct i40e_adapter *)dev->data->dev_private;
10088
10089         uint32_t sync_status;
10090         uint32_t index = flags & 0x03;
10091         uint64_t rx_tstamp_cycles;
10092         uint64_t ns;
10093
10094         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10095         if ((sync_status & (1 << index)) == 0)
10096                 return -EINVAL;
10097
10098         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10099         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10100         *timestamp = rte_ns_to_timespec(ns);
10101
10102         return 0;
10103 }
10104
10105 static int
10106 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10107                                 struct timespec *timestamp)
10108 {
10109         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10110         struct i40e_adapter *adapter =
10111                 (struct i40e_adapter *)dev->data->dev_private;
10112
10113         uint32_t sync_status;
10114         uint64_t tx_tstamp_cycles;
10115         uint64_t ns;
10116
10117         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10118         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10119                 return -EINVAL;
10120
10121         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10122         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10123         *timestamp = rte_ns_to_timespec(ns);
10124
10125         return 0;
10126 }
10127
10128 /*
10129  * i40e_parse_dcb_configure - parse dcb configure from user
10130  * @dev: the device being configured
10131  * @dcb_cfg: pointer of the result of parse
10132  * @*tc_map: bit map of enabled traffic classes
10133  *
10134  * Returns 0 on success, negative value on failure
10135  */
10136 static int
10137 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10138                          struct i40e_dcbx_config *dcb_cfg,
10139                          uint8_t *tc_map)
10140 {
10141         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10142         uint8_t i, tc_bw, bw_lf;
10143
10144         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10145
10146         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10147         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10148                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10149                 return -EINVAL;
10150         }
10151
10152         /* assume each tc has the same bw */
10153         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10154         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10155                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10156         /* to ensure the sum of tcbw is equal to 100 */
10157         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10158         for (i = 0; i < bw_lf; i++)
10159                 dcb_cfg->etscfg.tcbwtable[i]++;
10160
10161         /* assume each tc has the same Transmission Selection Algorithm */
10162         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10163                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10164
10165         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10166                 dcb_cfg->etscfg.prioritytable[i] =
10167                                 dcb_rx_conf->dcb_tc[i];
10168
10169         /* FW needs one App to configure HW */
10170         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10171         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10172         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10173         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10174
10175         if (dcb_rx_conf->nb_tcs == 0)
10176                 *tc_map = 1; /* tc0 only */
10177         else
10178                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10179
10180         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10181                 dcb_cfg->pfc.willing = 0;
10182                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10183                 dcb_cfg->pfc.pfcenable = *tc_map;
10184         }
10185         return 0;
10186 }
10187
10188
10189 static enum i40e_status_code
10190 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10191                               struct i40e_aqc_vsi_properties_data *info,
10192                               uint8_t enabled_tcmap)
10193 {
10194         enum i40e_status_code ret;
10195         int i, total_tc = 0;
10196         uint16_t qpnum_per_tc, bsf, qp_idx;
10197         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10198         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10199         uint16_t used_queues;
10200
10201         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10202         if (ret != I40E_SUCCESS)
10203                 return ret;
10204
10205         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10206                 if (enabled_tcmap & (1 << i))
10207                         total_tc++;
10208         }
10209         if (total_tc == 0)
10210                 total_tc = 1;
10211         vsi->enabled_tc = enabled_tcmap;
10212
10213         /* different VSI has different queues assigned */
10214         if (vsi->type == I40E_VSI_MAIN)
10215                 used_queues = dev_data->nb_rx_queues -
10216                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10217         else if (vsi->type == I40E_VSI_VMDQ2)
10218                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10219         else {
10220                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10221                 return I40E_ERR_NO_AVAILABLE_VSI;
10222         }
10223
10224         qpnum_per_tc = used_queues / total_tc;
10225         /* Number of queues per enabled TC */
10226         if (qpnum_per_tc == 0) {
10227                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10228                 return I40E_ERR_INVALID_QP_ID;
10229         }
10230         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10231                                 I40E_MAX_Q_PER_TC);
10232         bsf = rte_bsf32(qpnum_per_tc);
10233
10234         /**
10235          * Configure TC and queue mapping parameters, for enabled TC,
10236          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10237          * default queue will serve it.
10238          */
10239         qp_idx = 0;
10240         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10241                 if (vsi->enabled_tc & (1 << i)) {
10242                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10243                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10244                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10245                         qp_idx += qpnum_per_tc;
10246                 } else
10247                         info->tc_mapping[i] = 0;
10248         }
10249
10250         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10251         if (vsi->type == I40E_VSI_SRIOV) {
10252                 info->mapping_flags |=
10253                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10254                 for (i = 0; i < vsi->nb_qps; i++)
10255                         info->queue_mapping[i] =
10256                                 rte_cpu_to_le_16(vsi->base_queue + i);
10257         } else {
10258                 info->mapping_flags |=
10259                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10260                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10261         }
10262         info->valid_sections |=
10263                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10264
10265         return I40E_SUCCESS;
10266 }
10267
10268 /*
10269  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10270  * @veb: VEB to be configured
10271  * @tc_map: enabled TC bitmap
10272  *
10273  * Returns 0 on success, negative value on failure
10274  */
10275 static enum i40e_status_code
10276 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10277 {
10278         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10279         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10280         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10281         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10282         enum i40e_status_code ret = I40E_SUCCESS;
10283         int i;
10284         uint32_t bw_max;
10285
10286         /* Check if enabled_tc is same as existing or new TCs */
10287         if (veb->enabled_tc == tc_map)
10288                 return ret;
10289
10290         /* configure tc bandwidth */
10291         memset(&veb_bw, 0, sizeof(veb_bw));
10292         veb_bw.tc_valid_bits = tc_map;
10293         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10294         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10295                 if (tc_map & BIT_ULL(i))
10296                         veb_bw.tc_bw_share_credits[i] = 1;
10297         }
10298         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10299                                                    &veb_bw, NULL);
10300         if (ret) {
10301                 PMD_INIT_LOG(ERR,
10302                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10303                         hw->aq.asq_last_status);
10304                 return ret;
10305         }
10306
10307         memset(&ets_query, 0, sizeof(ets_query));
10308         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10309                                                    &ets_query, NULL);
10310         if (ret != I40E_SUCCESS) {
10311                 PMD_DRV_LOG(ERR,
10312                         "Failed to get switch_comp ETS configuration %u",
10313                         hw->aq.asq_last_status);
10314                 return ret;
10315         }
10316         memset(&bw_query, 0, sizeof(bw_query));
10317         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10318                                                   &bw_query, NULL);
10319         if (ret != I40E_SUCCESS) {
10320                 PMD_DRV_LOG(ERR,
10321                         "Failed to get switch_comp bandwidth configuration %u",
10322                         hw->aq.asq_last_status);
10323                 return ret;
10324         }
10325
10326         /* store and print out BW info */
10327         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10328         veb->bw_info.bw_max = ets_query.tc_bw_max;
10329         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10330         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10331         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10332                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10333                      I40E_16_BIT_WIDTH);
10334         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10335                 veb->bw_info.bw_ets_share_credits[i] =
10336                                 bw_query.tc_bw_share_credits[i];
10337                 veb->bw_info.bw_ets_credits[i] =
10338                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10339                 /* 4 bits per TC, 4th bit is reserved */
10340                 veb->bw_info.bw_ets_max[i] =
10341                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10342                                   RTE_LEN2MASK(3, uint8_t));
10343                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10344                             veb->bw_info.bw_ets_share_credits[i]);
10345                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10346                             veb->bw_info.bw_ets_credits[i]);
10347                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10348                             veb->bw_info.bw_ets_max[i]);
10349         }
10350
10351         veb->enabled_tc = tc_map;
10352
10353         return ret;
10354 }
10355
10356
10357 /*
10358  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10359  * @vsi: VSI to be configured
10360  * @tc_map: enabled TC bitmap
10361  *
10362  * Returns 0 on success, negative value on failure
10363  */
10364 static enum i40e_status_code
10365 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10366 {
10367         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10368         struct i40e_vsi_context ctxt;
10369         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10370         enum i40e_status_code ret = I40E_SUCCESS;
10371         int i;
10372
10373         /* Check if enabled_tc is same as existing or new TCs */
10374         if (vsi->enabled_tc == tc_map)
10375                 return ret;
10376
10377         /* configure tc bandwidth */
10378         memset(&bw_data, 0, sizeof(bw_data));
10379         bw_data.tc_valid_bits = tc_map;
10380         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10381         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10382                 if (tc_map & BIT_ULL(i))
10383                         bw_data.tc_bw_credits[i] = 1;
10384         }
10385         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10386         if (ret) {
10387                 PMD_INIT_LOG(ERR,
10388                         "AQ command Config VSI BW allocation per TC failed = %d",
10389                         hw->aq.asq_last_status);
10390                 goto out;
10391         }
10392         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10393                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10394
10395         /* Update Queue Pairs Mapping for currently enabled UPs */
10396         ctxt.seid = vsi->seid;
10397         ctxt.pf_num = hw->pf_id;
10398         ctxt.vf_num = 0;
10399         ctxt.uplink_seid = vsi->uplink_seid;
10400         ctxt.info = vsi->info;
10401         i40e_get_cap(hw);
10402         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10403         if (ret)
10404                 goto out;
10405
10406         /* Update the VSI after updating the VSI queue-mapping information */
10407         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10408         if (ret) {
10409                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10410                         hw->aq.asq_last_status);
10411                 goto out;
10412         }
10413         /* update the local VSI info with updated queue map */
10414         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10415                                         sizeof(vsi->info.tc_mapping));
10416         rte_memcpy(&vsi->info.queue_mapping,
10417                         &ctxt.info.queue_mapping,
10418                 sizeof(vsi->info.queue_mapping));
10419         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10420         vsi->info.valid_sections = 0;
10421
10422         /* query and update current VSI BW information */
10423         ret = i40e_vsi_get_bw_config(vsi);
10424         if (ret) {
10425                 PMD_INIT_LOG(ERR,
10426                          "Failed updating vsi bw info, err %s aq_err %s",
10427                          i40e_stat_str(hw, ret),
10428                          i40e_aq_str(hw, hw->aq.asq_last_status));
10429                 goto out;
10430         }
10431
10432         vsi->enabled_tc = tc_map;
10433
10434 out:
10435         return ret;
10436 }
10437
10438 /*
10439  * i40e_dcb_hw_configure - program the dcb setting to hw
10440  * @pf: pf the configuration is taken on
10441  * @new_cfg: new configuration
10442  * @tc_map: enabled TC bitmap
10443  *
10444  * Returns 0 on success, negative value on failure
10445  */
10446 static enum i40e_status_code
10447 i40e_dcb_hw_configure(struct i40e_pf *pf,
10448                       struct i40e_dcbx_config *new_cfg,
10449                       uint8_t tc_map)
10450 {
10451         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10452         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10453         struct i40e_vsi *main_vsi = pf->main_vsi;
10454         struct i40e_vsi_list *vsi_list;
10455         enum i40e_status_code ret;
10456         int i;
10457         uint32_t val;
10458
10459         /* Use the FW API if FW > v4.4*/
10460         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10461               (hw->aq.fw_maj_ver >= 5))) {
10462                 PMD_INIT_LOG(ERR,
10463                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10464                 return I40E_ERR_FIRMWARE_API_VERSION;
10465         }
10466
10467         /* Check if need reconfiguration */
10468         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10469                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10470                 return I40E_SUCCESS;
10471         }
10472
10473         /* Copy the new config to the current config */
10474         *old_cfg = *new_cfg;
10475         old_cfg->etsrec = old_cfg->etscfg;
10476         ret = i40e_set_dcb_config(hw);
10477         if (ret) {
10478                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10479                          i40e_stat_str(hw, ret),
10480                          i40e_aq_str(hw, hw->aq.asq_last_status));
10481                 return ret;
10482         }
10483         /* set receive Arbiter to RR mode and ETS scheme by default */
10484         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10485                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10486                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10487                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10488                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10489                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10490                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10491                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10492                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10493                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10494                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10495                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10496                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10497         }
10498         /* get local mib to check whether it is configured correctly */
10499         /* IEEE mode */
10500         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10501         /* Get Local DCB Config */
10502         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10503                                      &hw->local_dcbx_config);
10504
10505         /* if Veb is created, need to update TC of it at first */
10506         if (main_vsi->veb) {
10507                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10508                 if (ret)
10509                         PMD_INIT_LOG(WARNING,
10510                                  "Failed configuring TC for VEB seid=%d",
10511                                  main_vsi->veb->seid);
10512         }
10513         /* Update each VSI */
10514         i40e_vsi_config_tc(main_vsi, tc_map);
10515         if (main_vsi->veb) {
10516                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10517                         /* Beside main VSI and VMDQ VSIs, only enable default
10518                          * TC for other VSIs
10519                          */
10520                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10521                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10522                                                          tc_map);
10523                         else
10524                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10525                                                          I40E_DEFAULT_TCMAP);
10526                         if (ret)
10527                                 PMD_INIT_LOG(WARNING,
10528                                         "Failed configuring TC for VSI seid=%d",
10529                                         vsi_list->vsi->seid);
10530                         /* continue */
10531                 }
10532         }
10533         return I40E_SUCCESS;
10534 }
10535
10536 /*
10537  * i40e_dcb_init_configure - initial dcb config
10538  * @dev: device being configured
10539  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10540  *
10541  * Returns 0 on success, negative value on failure
10542  */
10543 int
10544 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10545 {
10546         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10547         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10548         int i, ret = 0;
10549
10550         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10551                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10552                 return -ENOTSUP;
10553         }
10554
10555         /* DCB initialization:
10556          * Update DCB configuration from the Firmware and configure
10557          * LLDP MIB change event.
10558          */
10559         if (sw_dcb == TRUE) {
10560                 ret = i40e_init_dcb(hw);
10561                 /* If lldp agent is stopped, the return value from
10562                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10563                  * adminq status. Otherwise, it should return success.
10564                  */
10565                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10566                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10567                         memset(&hw->local_dcbx_config, 0,
10568                                 sizeof(struct i40e_dcbx_config));
10569                         /* set dcb default configuration */
10570                         hw->local_dcbx_config.etscfg.willing = 0;
10571                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10572                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10573                         hw->local_dcbx_config.etscfg.tsatable[0] =
10574                                                 I40E_IEEE_TSA_ETS;
10575                         /* all UPs mapping to TC0 */
10576                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10577                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10578                         hw->local_dcbx_config.etsrec =
10579                                 hw->local_dcbx_config.etscfg;
10580                         hw->local_dcbx_config.pfc.willing = 0;
10581                         hw->local_dcbx_config.pfc.pfccap =
10582                                                 I40E_MAX_TRAFFIC_CLASS;
10583                         /* FW needs one App to configure HW */
10584                         hw->local_dcbx_config.numapps = 1;
10585                         hw->local_dcbx_config.app[0].selector =
10586                                                 I40E_APP_SEL_ETHTYPE;
10587                         hw->local_dcbx_config.app[0].priority = 3;
10588                         hw->local_dcbx_config.app[0].protocolid =
10589                                                 I40E_APP_PROTOID_FCOE;
10590                         ret = i40e_set_dcb_config(hw);
10591                         if (ret) {
10592                                 PMD_INIT_LOG(ERR,
10593                                         "default dcb config fails. err = %d, aq_err = %d.",
10594                                         ret, hw->aq.asq_last_status);
10595                                 return -ENOSYS;
10596                         }
10597                 } else {
10598                         PMD_INIT_LOG(ERR,
10599                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10600                                 ret, hw->aq.asq_last_status);
10601                         return -ENOTSUP;
10602                 }
10603         } else {
10604                 ret = i40e_aq_start_lldp(hw, NULL);
10605                 if (ret != I40E_SUCCESS)
10606                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10607
10608                 ret = i40e_init_dcb(hw);
10609                 if (!ret) {
10610                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10611                                 PMD_INIT_LOG(ERR,
10612                                         "HW doesn't support DCBX offload.");
10613                                 return -ENOTSUP;
10614                         }
10615                 } else {
10616                         PMD_INIT_LOG(ERR,
10617                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10618                                 ret, hw->aq.asq_last_status);
10619                         return -ENOTSUP;
10620                 }
10621         }
10622         return 0;
10623 }
10624
10625 /*
10626  * i40e_dcb_setup - setup dcb related config
10627  * @dev: device being configured
10628  *
10629  * Returns 0 on success, negative value on failure
10630  */
10631 static int
10632 i40e_dcb_setup(struct rte_eth_dev *dev)
10633 {
10634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10635         struct i40e_dcbx_config dcb_cfg;
10636         uint8_t tc_map = 0;
10637         int ret = 0;
10638
10639         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10640                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10641                 return -ENOTSUP;
10642         }
10643
10644         if (pf->vf_num != 0)
10645                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10646
10647         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10648         if (ret) {
10649                 PMD_INIT_LOG(ERR, "invalid dcb config");
10650                 return -EINVAL;
10651         }
10652         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10653         if (ret) {
10654                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10655                 return -ENOSYS;
10656         }
10657
10658         return 0;
10659 }
10660
10661 static int
10662 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10663                       struct rte_eth_dcb_info *dcb_info)
10664 {
10665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10667         struct i40e_vsi *vsi = pf->main_vsi;
10668         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10669         uint16_t bsf, tc_mapping;
10670         int i, j = 0;
10671
10672         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10673                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10674         else
10675                 dcb_info->nb_tcs = 1;
10676         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10677                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10678         for (i = 0; i < dcb_info->nb_tcs; i++)
10679                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10680
10681         /* get queue mapping if vmdq is disabled */
10682         if (!pf->nb_cfg_vmdq_vsi) {
10683                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10684                         if (!(vsi->enabled_tc & (1 << i)))
10685                                 continue;
10686                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10687                         dcb_info->tc_queue.tc_rxq[j][i].base =
10688                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10689                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10690                         dcb_info->tc_queue.tc_txq[j][i].base =
10691                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10692                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10693                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10694                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10695                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10696                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10697                 }
10698                 return 0;
10699         }
10700
10701         /* get queue mapping if vmdq is enabled */
10702         do {
10703                 vsi = pf->vmdq[j].vsi;
10704                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10705                         if (!(vsi->enabled_tc & (1 << i)))
10706                                 continue;
10707                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10708                         dcb_info->tc_queue.tc_rxq[j][i].base =
10709                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10710                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10711                         dcb_info->tc_queue.tc_txq[j][i].base =
10712                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10713                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10714                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10715                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10716                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10717                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10718                 }
10719                 j++;
10720         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10721         return 0;
10722 }
10723
10724 static int
10725 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10726 {
10727         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10728         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10729         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10730         uint16_t interval =
10731                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10732         uint16_t msix_intr;
10733
10734         msix_intr = intr_handle->intr_vec[queue_id];
10735         if (msix_intr == I40E_MISC_VEC_ID)
10736                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10737                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10738                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10739                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10740                                (interval <<
10741                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10742         else
10743                 I40E_WRITE_REG(hw,
10744                                I40E_PFINT_DYN_CTLN(msix_intr -
10745                                                    I40E_RX_VEC_START),
10746                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10747                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10748                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10749                                (interval <<
10750                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10751
10752         I40E_WRITE_FLUSH(hw);
10753         rte_intr_enable(&pci_dev->intr_handle);
10754
10755         return 0;
10756 }
10757
10758 static int
10759 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10760 {
10761         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10762         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10764         uint16_t msix_intr;
10765
10766         msix_intr = intr_handle->intr_vec[queue_id];
10767         if (msix_intr == I40E_MISC_VEC_ID)
10768                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10769         else
10770                 I40E_WRITE_REG(hw,
10771                                I40E_PFINT_DYN_CTLN(msix_intr -
10772                                                    I40E_RX_VEC_START),
10773                                0);
10774         I40E_WRITE_FLUSH(hw);
10775
10776         return 0;
10777 }
10778
10779 static int i40e_get_regs(struct rte_eth_dev *dev,
10780                          struct rte_dev_reg_info *regs)
10781 {
10782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10783         uint32_t *ptr_data = regs->data;
10784         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10785         const struct i40e_reg_info *reg_info;
10786
10787         if (ptr_data == NULL) {
10788                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10789                 regs->width = sizeof(uint32_t);
10790                 return 0;
10791         }
10792
10793         /* The first few registers have to be read using AQ operations */
10794         reg_idx = 0;
10795         while (i40e_regs_adminq[reg_idx].name) {
10796                 reg_info = &i40e_regs_adminq[reg_idx++];
10797                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10798                         for (arr_idx2 = 0;
10799                                         arr_idx2 <= reg_info->count2;
10800                                         arr_idx2++) {
10801                                 reg_offset = arr_idx * reg_info->stride1 +
10802                                         arr_idx2 * reg_info->stride2;
10803                                 reg_offset += reg_info->base_addr;
10804                                 ptr_data[reg_offset >> 2] =
10805                                         i40e_read_rx_ctl(hw, reg_offset);
10806                         }
10807         }
10808
10809         /* The remaining registers can be read using primitives */
10810         reg_idx = 0;
10811         while (i40e_regs_others[reg_idx].name) {
10812                 reg_info = &i40e_regs_others[reg_idx++];
10813                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10814                         for (arr_idx2 = 0;
10815                                         arr_idx2 <= reg_info->count2;
10816                                         arr_idx2++) {
10817                                 reg_offset = arr_idx * reg_info->stride1 +
10818                                         arr_idx2 * reg_info->stride2;
10819                                 reg_offset += reg_info->base_addr;
10820                                 ptr_data[reg_offset >> 2] =
10821                                         I40E_READ_REG(hw, reg_offset);
10822                         }
10823         }
10824
10825         return 0;
10826 }
10827
10828 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10829 {
10830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10831
10832         /* Convert word count to byte count */
10833         return hw->nvm.sr_size << 1;
10834 }
10835
10836 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10837                            struct rte_dev_eeprom_info *eeprom)
10838 {
10839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10840         uint16_t *data = eeprom->data;
10841         uint16_t offset, length, cnt_words;
10842         int ret_code;
10843
10844         offset = eeprom->offset >> 1;
10845         length = eeprom->length >> 1;
10846         cnt_words = length;
10847
10848         if (offset > hw->nvm.sr_size ||
10849                 offset + length > hw->nvm.sr_size) {
10850                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10851                 return -EINVAL;
10852         }
10853
10854         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10855
10856         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10857         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10858                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10859                 return -EIO;
10860         }
10861
10862         return 0;
10863 }
10864
10865 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10866                                       struct ether_addr *mac_addr)
10867 {
10868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10869
10870         if (!is_valid_assigned_ether_addr(mac_addr)) {
10871                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10872                 return;
10873         }
10874
10875         /* Flags: 0x3 updates port address */
10876         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10877 }
10878
10879 static int
10880 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10881 {
10882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10883         struct rte_eth_dev_data *dev_data = pf->dev_data;
10884         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10885         int ret = 0;
10886
10887         /* check if mtu is within the allowed range */
10888         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10889                 return -EINVAL;
10890
10891         /* mtu setting is forbidden if port is start */
10892         if (dev_data->dev_started) {
10893                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10894                             dev_data->port_id);
10895                 return -EBUSY;
10896         }
10897
10898         if (frame_size > ETHER_MAX_LEN)
10899                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10900         else
10901                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10902
10903         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10904
10905         return ret;
10906 }
10907
10908 /* Restore ethertype filter */
10909 static void
10910 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10911 {
10912         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10913         struct i40e_ethertype_filter_list
10914                 *ethertype_list = &pf->ethertype.ethertype_list;
10915         struct i40e_ethertype_filter *f;
10916         struct i40e_control_filter_stats stats;
10917         uint16_t flags;
10918
10919         TAILQ_FOREACH(f, ethertype_list, rules) {
10920                 flags = 0;
10921                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10922                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10923                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10924                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10925                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10926
10927                 memset(&stats, 0, sizeof(stats));
10928                 i40e_aq_add_rem_control_packet_filter(hw,
10929                                             f->input.mac_addr.addr_bytes,
10930                                             f->input.ether_type,
10931                                             flags, pf->main_vsi->seid,
10932                                             f->queue, 1, &stats, NULL);
10933         }
10934         PMD_DRV_LOG(INFO, "Ethertype filter:"
10935                     " mac_etype_used = %u, etype_used = %u,"
10936                     " mac_etype_free = %u, etype_free = %u",
10937                     stats.mac_etype_used, stats.etype_used,
10938                     stats.mac_etype_free, stats.etype_free);
10939 }
10940
10941 /* Restore tunnel filter */
10942 static void
10943 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10944 {
10945         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10946         struct i40e_vsi *vsi;
10947         struct i40e_pf_vf *vf;
10948         struct i40e_tunnel_filter_list
10949                 *tunnel_list = &pf->tunnel.tunnel_list;
10950         struct i40e_tunnel_filter *f;
10951         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10952         bool big_buffer = 0;
10953
10954         TAILQ_FOREACH(f, tunnel_list, rules) {
10955                 if (!f->is_to_vf)
10956                         vsi = pf->main_vsi;
10957                 else {
10958                         vf = &pf->vfs[f->vf_id];
10959                         vsi = vf->vsi;
10960                 }
10961                 memset(&cld_filter, 0, sizeof(cld_filter));
10962                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10963                         (struct ether_addr *)&cld_filter.element.outer_mac);
10964                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10965                         (struct ether_addr *)&cld_filter.element.inner_mac);
10966                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10967                 cld_filter.element.flags = f->input.flags;
10968                 cld_filter.element.tenant_id = f->input.tenant_id;
10969                 cld_filter.element.queue_number = f->queue;
10970                 rte_memcpy(cld_filter.general_fields,
10971                            f->input.general_fields,
10972                            sizeof(f->input.general_fields));
10973
10974                 if (((f->input.flags &
10975                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10976                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10977                     ((f->input.flags &
10978                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10979                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10980                     ((f->input.flags &
10981                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10982                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10983                         big_buffer = 1;
10984
10985                 if (big_buffer)
10986                         i40e_aq_add_cloud_filters_big_buffer(hw,
10987                                              vsi->seid, &cld_filter, 1);
10988                 else
10989                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10990                                                   &cld_filter.element, 1);
10991         }
10992 }
10993
10994 static void
10995 i40e_filter_restore(struct i40e_pf *pf)
10996 {
10997         i40e_ethertype_filter_restore(pf);
10998         i40e_tunnel_filter_restore(pf);
10999         i40e_fdir_filter_restore(pf);
11000 }
11001
11002 static bool
11003 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11004 {
11005         if (strcmp(dev->device->driver->name, drv->driver.name))
11006                 return false;
11007
11008         return true;
11009 }
11010
11011 bool
11012 is_i40e_supported(struct rte_eth_dev *dev)
11013 {
11014         return is_device_supported(dev, &rte_i40e_pmd);
11015 }
11016
11017 struct i40e_customized_pctype*
11018 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11019 {
11020         int i;
11021
11022         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11023                 if (pf->customized_pctype[i].index == index)
11024                         return &pf->customized_pctype[i];
11025         }
11026         return NULL;
11027 }
11028
11029 static int
11030 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11031                               uint32_t pkg_size, uint32_t proto_num,
11032                               struct rte_pmd_i40e_proto_info *proto)
11033 {
11034         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11035         uint32_t pctype_num;
11036         struct rte_pmd_i40e_ptype_info *pctype;
11037         uint32_t buff_size;
11038         struct i40e_customized_pctype *new_pctype = NULL;
11039         uint8_t proto_id;
11040         uint8_t pctype_value;
11041         char name[64];
11042         uint32_t i, j, n;
11043         int ret;
11044
11045         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11046                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11047                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11048         if (ret) {
11049                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11050                 return -1;
11051         }
11052         if (!pctype_num) {
11053                 PMD_DRV_LOG(INFO, "No new pctype added");
11054                 return -1;
11055         }
11056
11057         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11058         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11059         if (!pctype) {
11060                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11061                 return -1;
11062         }
11063         /* get information about new pctype list */
11064         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11065                                         (uint8_t *)pctype, buff_size,
11066                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11067         if (ret) {
11068                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11069                 rte_free(pctype);
11070                 return -1;
11071         }
11072
11073         /* Update customized pctype. */
11074         for (i = 0; i < pctype_num; i++) {
11075                 pctype_value = pctype[i].ptype_id;
11076                 memset(name, 0, sizeof(name));
11077                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11078                         proto_id = pctype[i].protocols[j];
11079                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11080                                 continue;
11081                         for (n = 0; n < proto_num; n++) {
11082                                 if (proto[n].proto_id != proto_id)
11083                                         continue;
11084                                 strcat(name, proto[n].name);
11085                                 strcat(name, "_");
11086                                 break;
11087                         }
11088                 }
11089                 name[strlen(name) - 1] = '\0';
11090                 if (!strcmp(name, "GTPC"))
11091                         new_pctype =
11092                                 i40e_find_customized_pctype(pf,
11093                                                       I40E_CUSTOMIZED_GTPC);
11094                 else if (!strcmp(name, "GTPU_IPV4"))
11095                         new_pctype =
11096                                 i40e_find_customized_pctype(pf,
11097                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11098                 else if (!strcmp(name, "GTPU_IPV6"))
11099                         new_pctype =
11100                                 i40e_find_customized_pctype(pf,
11101                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11102                 else if (!strcmp(name, "GTPU"))
11103                         new_pctype =
11104                                 i40e_find_customized_pctype(pf,
11105                                                       I40E_CUSTOMIZED_GTPU);
11106                 if (new_pctype) {
11107                         new_pctype->pctype = pctype_value;
11108                         new_pctype->valid = true;
11109                 }
11110         }
11111
11112         rte_free(pctype);
11113         return 0;
11114 }
11115
11116 static int
11117 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11118                                uint32_t pkg_size, uint32_t proto_num,
11119                                struct rte_pmd_i40e_proto_info *proto)
11120 {
11121         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11122         uint16_t port_id = dev->data->port_id;
11123         uint32_t ptype_num;
11124         struct rte_pmd_i40e_ptype_info *ptype;
11125         uint32_t buff_size;
11126         uint8_t proto_id;
11127         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11128         uint32_t i, j, n;
11129         bool in_tunnel;
11130         int ret;
11131
11132         /* get information about new ptype num */
11133         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11134                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11135                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11136         if (ret) {
11137                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11138                 return ret;
11139         }
11140         if (!ptype_num) {
11141                 PMD_DRV_LOG(INFO, "No new ptype added");
11142                 return -1;
11143         }
11144
11145         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11146         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11147         if (!ptype) {
11148                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11149                 return -1;
11150         }
11151
11152         /* get information about new ptype list */
11153         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11154                                         (uint8_t *)ptype, buff_size,
11155                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11156         if (ret) {
11157                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11158                 rte_free(ptype);
11159                 return ret;
11160         }
11161
11162         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11163         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11164         if (!ptype_mapping) {
11165                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11166                 rte_free(ptype);
11167                 return -1;
11168         }
11169
11170         /* Update ptype mapping table. */
11171         for (i = 0; i < ptype_num; i++) {
11172                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11173                 ptype_mapping[i].sw_ptype = 0;
11174                 in_tunnel = false;
11175                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11176                         proto_id = ptype[i].protocols[j];
11177                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11178                                 continue;
11179                         for (n = 0; n < proto_num; n++) {
11180                                 if (proto[n].proto_id != proto_id)
11181                                         continue;
11182                                 memset(name, 0, sizeof(name));
11183                                 strcpy(name, proto[n].name);
11184                                 if (!strncmp(name, "PPPOE", 5))
11185                                         ptype_mapping[i].sw_ptype |=
11186                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11187                                 else if (!strncmp(name, "OIPV4", 5)) {
11188                                         ptype_mapping[i].sw_ptype |=
11189                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11190                                         in_tunnel = true;
11191                                 } else if (!strncmp(name, "IPV4", 4) &&
11192                                            !in_tunnel)
11193                                         ptype_mapping[i].sw_ptype |=
11194                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11195                                 else if (!strncmp(name, "IPV4FRAG", 8) &&
11196                                          in_tunnel) {
11197                                         ptype_mapping[i].sw_ptype |=
11198                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11199                                         ptype_mapping[i].sw_ptype |=
11200                                                 RTE_PTYPE_INNER_L4_FRAG;
11201                                 } else if (!strncmp(name, "IPV4", 4) &&
11202                                            in_tunnel)
11203                                         ptype_mapping[i].sw_ptype |=
11204                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11205                                 else if (!strncmp(name, "OIPV6", 5)) {
11206                                         ptype_mapping[i].sw_ptype |=
11207                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11208                                         in_tunnel = true;
11209                                 } else if (!strncmp(name, "IPV6", 4) &&
11210                                            !in_tunnel)
11211                                         ptype_mapping[i].sw_ptype |=
11212                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11213                                 else if (!strncmp(name, "IPV6FRAG", 8) &&
11214                                          in_tunnel) {
11215                                         ptype_mapping[i].sw_ptype |=
11216                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11217                                         ptype_mapping[i].sw_ptype |=
11218                                                 RTE_PTYPE_INNER_L4_FRAG;
11219                                 } else if (!strncmp(name, "IPV6", 4) &&
11220                                            in_tunnel)
11221                                         ptype_mapping[i].sw_ptype |=
11222                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11223                                 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11224                                         ptype_mapping[i].sw_ptype |=
11225                                                 RTE_PTYPE_L4_UDP;
11226                                 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11227                                         ptype_mapping[i].sw_ptype |=
11228                                                 RTE_PTYPE_INNER_L4_UDP;
11229                                 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11230                                         ptype_mapping[i].sw_ptype |=
11231                                                 RTE_PTYPE_L4_TCP;
11232                                 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11233                                         ptype_mapping[i].sw_ptype |=
11234                                                 RTE_PTYPE_INNER_L4_TCP;
11235                                 else if (!strncmp(name, "SCTP", 4) &&
11236                                          !in_tunnel)
11237                                         ptype_mapping[i].sw_ptype |=
11238                                                 RTE_PTYPE_L4_SCTP;
11239                                 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11240                                         ptype_mapping[i].sw_ptype |=
11241                                                 RTE_PTYPE_INNER_L4_SCTP;
11242                                 else if ((!strncmp(name, "ICMP", 4) ||
11243                                           !strncmp(name, "ICMPV6", 6)) &&
11244                                          !in_tunnel)
11245                                         ptype_mapping[i].sw_ptype |=
11246                                                 RTE_PTYPE_L4_ICMP;
11247                                 else if ((!strncmp(name, "ICMP", 4) ||
11248                                           !strncmp(name, "ICMPV6", 6)) &&
11249                                          in_tunnel)
11250                                         ptype_mapping[i].sw_ptype |=
11251                                                 RTE_PTYPE_INNER_L4_ICMP;
11252                                 else if (!strncmp(name, "GTPC", 4)) {
11253                                         ptype_mapping[i].sw_ptype |=
11254                                                 RTE_PTYPE_TUNNEL_GTPC;
11255                                         in_tunnel = true;
11256                                 } else if (!strncmp(name, "GTPU", 4)) {
11257                                         ptype_mapping[i].sw_ptype |=
11258                                                 RTE_PTYPE_TUNNEL_GTPU;
11259                                         in_tunnel = true;
11260                                 } else if (!strncmp(name, "GRENAT", 6)) {
11261                                         ptype_mapping[i].sw_ptype |=
11262                                                 RTE_PTYPE_TUNNEL_GRENAT;
11263                                         in_tunnel = true;
11264                                 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11265                                         ptype_mapping[i].sw_ptype |=
11266                                                 RTE_PTYPE_TUNNEL_L2TP;
11267                                         in_tunnel = true;
11268                                 }
11269
11270                                 break;
11271                         }
11272                 }
11273         }
11274
11275         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11276                                                 ptype_num, 0);
11277         if (ret)
11278                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11279
11280         rte_free(ptype_mapping);
11281         rte_free(ptype);
11282         return ret;
11283 }
11284
11285 void
11286 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11287                               uint32_t pkg_size)
11288 {
11289         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11290         uint32_t proto_num;
11291         struct rte_pmd_i40e_proto_info *proto;
11292         uint32_t buff_size;
11293         uint32_t i;
11294         int ret;
11295
11296         /* get information about protocol number */
11297         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11298                                        (uint8_t *)&proto_num, sizeof(proto_num),
11299                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11300         if (ret) {
11301                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11302                 return;
11303         }
11304         if (!proto_num) {
11305                 PMD_DRV_LOG(INFO, "No new protocol added");
11306                 return;
11307         }
11308
11309         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11310         proto = rte_zmalloc("new_proto", buff_size, 0);
11311         if (!proto) {
11312                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11313                 return;
11314         }
11315
11316         /* get information about protocol list */
11317         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11318                                         (uint8_t *)proto, buff_size,
11319                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11320         if (ret) {
11321                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11322                 rte_free(proto);
11323                 return;
11324         }
11325
11326         /* Check if GTP is supported. */
11327         for (i = 0; i < proto_num; i++) {
11328                 if (!strncmp(proto[i].name, "GTP", 3)) {
11329                         pf->gtp_support = true;
11330                         break;
11331                 }
11332         }
11333
11334         /* Update customized pctype info */
11335         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11336                                             proto_num, proto);
11337         if (ret)
11338                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11339
11340         /* Update customized ptype info */
11341         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11342                                            proto_num, proto);
11343         if (ret)
11344                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11345
11346         rte_free(proto);
11347 }
11348
11349 /* Create a QinQ cloud filter
11350  *
11351  * The Fortville NIC has limited resources for tunnel filters,
11352  * so we can only reuse existing filters.
11353  *
11354  * In step 1 we define which Field Vector fields can be used for
11355  * filter types.
11356  * As we do not have the inner tag defined as a field,
11357  * we have to define it first, by reusing one of L1 entries.
11358  *
11359  * In step 2 we are replacing one of existing filter types with
11360  * a new one for QinQ.
11361  * As we reusing L1 and replacing L2, some of the default filter
11362  * types will disappear,which depends on L1 and L2 entries we reuse.
11363  *
11364  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11365  *
11366  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11367  *              later when we define the cloud filter.
11368  *      a.      Valid_flags.replace_cloud = 0
11369  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11370  *      c.      New_filter = 0x10
11371  *      d.      TR bit = 0xff (optional, not used here)
11372  *      e.      Buffer – 2 entries:
11373  *              i.      Byte 0 = 8 (outer vlan FV index).
11374  *                      Byte 1 = 0 (rsv)
11375  *                      Byte 2-3 = 0x0fff
11376  *              ii.     Byte 0 = 37 (inner vlan FV index).
11377  *                      Byte 1 =0 (rsv)
11378  *                      Byte 2-3 = 0x0fff
11379  *
11380  * Step 2:
11381  * 2.   Create cloud filter using two L1 filters entries: stag and
11382  *              new filter(outer vlan+ inner vlan)
11383  *      a.      Valid_flags.replace_cloud = 1
11384  *      b.      Old_filter = 1 (instead of outer IP)
11385  *      c.      New_filter = 0x10
11386  *      d.      Buffer – 2 entries:
11387  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11388  *                      Byte 1-3 = 0 (rsv)
11389  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11390  *                      Byte 9-11 = 0 (rsv)
11391  */
11392 static int
11393 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11394 {
11395         int ret = -ENOTSUP;
11396         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11397         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11398         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11399
11400         /* Init */
11401         memset(&filter_replace, 0,
11402                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11403         memset(&filter_replace_buf, 0,
11404                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11405
11406         /* create L1 filter */
11407         filter_replace.old_filter_type =
11408                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11409         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11410         filter_replace.tr_bit = 0;
11411
11412         /* Prepare the buffer, 2 entries */
11413         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11414         filter_replace_buf.data[0] |=
11415                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11416         /* Field Vector 12b mask */
11417         filter_replace_buf.data[2] = 0xff;
11418         filter_replace_buf.data[3] = 0x0f;
11419         filter_replace_buf.data[4] =
11420                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11421         filter_replace_buf.data[4] |=
11422                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11423         /* Field Vector 12b mask */
11424         filter_replace_buf.data[6] = 0xff;
11425         filter_replace_buf.data[7] = 0x0f;
11426         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11427                         &filter_replace_buf);
11428         if (ret != I40E_SUCCESS)
11429                 return ret;
11430
11431         /* Apply the second L2 cloud filter */
11432         memset(&filter_replace, 0,
11433                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11434         memset(&filter_replace_buf, 0,
11435                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11436
11437         /* create L2 filter, input for L2 filter will be L1 filter  */
11438         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11439         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11440         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11441
11442         /* Prepare the buffer, 2 entries */
11443         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11444         filter_replace_buf.data[0] |=
11445                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11446         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11447         filter_replace_buf.data[4] |=
11448                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11449         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11450                         &filter_replace_buf);
11451         return ret;
11452 }
11453
11454 RTE_INIT(i40e_init_log);
11455 static void
11456 i40e_init_log(void)
11457 {
11458         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11459         if (i40e_logtype_init >= 0)
11460                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11461         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11462         if (i40e_logtype_driver >= 0)
11463                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11464 }