4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_adminq_cmd.h"
57 #include "base/i40e_type.h"
58 #include "base/i40e_register.h"
59 #include "i40e_ethdev.h"
60 #include "i40e_rxtx.h"
63 /* Maximun number of MAC addresses */
64 #define I40E_NUM_MACADDR_MAX 64
65 #define I40E_CLEAR_PXE_WAIT_MS 200
67 /* Maximun number of capability elements */
68 #define I40E_MAX_CAP_ELE_NUM 128
70 /* Wait count and inteval */
71 #define I40E_CHK_Q_ENA_COUNT 1000
72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
74 /* Maximun number of VSI */
75 #define I40E_MAX_NUM_VSIS (384UL)
77 /* Default queue interrupt throttling time in microseconds */
78 #define I40E_ITR_INDEX_DEFAULT 0
79 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
80 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
82 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
92 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
93 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
94 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
95 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
97 #define I40E_FLOW_TYPES ( \
98 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
103 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
108 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
116 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
117 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
118 static int i40e_dev_configure(struct rte_eth_dev *dev);
119 static int i40e_dev_start(struct rte_eth_dev *dev);
120 static void i40e_dev_stop(struct rte_eth_dev *dev);
121 static void i40e_dev_close(struct rte_eth_dev *dev);
122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
129 struct rte_eth_stats *stats);
130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
136 struct rte_eth_dev_info *dev_info);
137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
149 struct rte_eth_fc_conf *fc_conf);
150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
151 struct rte_eth_pfc_conf *pfc_conf);
152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
153 struct ether_addr *mac_addr,
156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
158 struct rte_eth_rss_reta_entry64 *reta_conf,
160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
161 struct rte_eth_rss_reta_entry64 *reta_conf,
164 static int i40e_get_cap(struct i40e_hw *hw);
165 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
166 static int i40e_pf_setup(struct i40e_pf *pf);
167 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
168 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
169 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
170 bool offset_loaded, uint64_t *offset, uint64_t *stat);
171 static void i40e_stat_update_48(struct i40e_hw *hw,
177 static void i40e_pf_config_irq0(struct i40e_hw *hw);
178 static void i40e_dev_interrupt_handler(
179 __rte_unused struct rte_intr_handle *handle, void *param);
180 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
181 uint32_t base, uint32_t num);
182 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
183 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
185 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
187 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
188 static int i40e_veb_release(struct i40e_veb *veb);
189 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
190 struct i40e_vsi *vsi);
191 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
192 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
194 struct i40e_macvlan_filter *mv_f,
196 struct ether_addr *addr);
197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
198 struct i40e_macvlan_filter *mv_f,
201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
203 struct rte_eth_rss_conf *rss_conf);
204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
205 struct rte_eth_rss_conf *rss_conf);
206 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
207 struct rte_eth_udp_tunnel *udp_tunnel);
208 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
209 struct rte_eth_udp_tunnel *udp_tunnel);
210 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
211 struct rte_eth_ethertype_filter *filter,
213 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
214 enum rte_filter_op filter_op,
216 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
217 enum rte_filter_type filter_type,
218 enum rte_filter_op filter_op,
220 static void i40e_configure_registers(struct i40e_hw *hw);
221 static void i40e_hw_init(struct i40e_hw *hw);
222 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
223 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
224 struct rte_eth_mirror_conf *mirror_conf,
225 uint8_t sw_id, uint8_t on);
226 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
228 static int i40e_timesync_enable(struct rte_eth_dev *dev);
229 static int i40e_timesync_disable(struct rte_eth_dev *dev);
230 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
231 struct timespec *timestamp,
233 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
234 struct timespec *timestamp);
236 static const struct rte_pci_id pci_id_i40e_map[] = {
237 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
238 #include "rte_pci_dev_ids.h"
239 { .vendor_id = 0, /* sentinel */ },
242 static const struct eth_dev_ops i40e_eth_dev_ops = {
243 .dev_configure = i40e_dev_configure,
244 .dev_start = i40e_dev_start,
245 .dev_stop = i40e_dev_stop,
246 .dev_close = i40e_dev_close,
247 .promiscuous_enable = i40e_dev_promiscuous_enable,
248 .promiscuous_disable = i40e_dev_promiscuous_disable,
249 .allmulticast_enable = i40e_dev_allmulticast_enable,
250 .allmulticast_disable = i40e_dev_allmulticast_disable,
251 .dev_set_link_up = i40e_dev_set_link_up,
252 .dev_set_link_down = i40e_dev_set_link_down,
253 .link_update = i40e_dev_link_update,
254 .stats_get = i40e_dev_stats_get,
255 .stats_reset = i40e_dev_stats_reset,
256 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
257 .dev_infos_get = i40e_dev_info_get,
258 .vlan_filter_set = i40e_vlan_filter_set,
259 .vlan_tpid_set = i40e_vlan_tpid_set,
260 .vlan_offload_set = i40e_vlan_offload_set,
261 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
262 .vlan_pvid_set = i40e_vlan_pvid_set,
263 .rx_queue_start = i40e_dev_rx_queue_start,
264 .rx_queue_stop = i40e_dev_rx_queue_stop,
265 .tx_queue_start = i40e_dev_tx_queue_start,
266 .tx_queue_stop = i40e_dev_tx_queue_stop,
267 .rx_queue_setup = i40e_dev_rx_queue_setup,
268 .rx_queue_release = i40e_dev_rx_queue_release,
269 .rx_queue_count = i40e_dev_rx_queue_count,
270 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
271 .tx_queue_setup = i40e_dev_tx_queue_setup,
272 .tx_queue_release = i40e_dev_tx_queue_release,
273 .dev_led_on = i40e_dev_led_on,
274 .dev_led_off = i40e_dev_led_off,
275 .flow_ctrl_set = i40e_flow_ctrl_set,
276 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
277 .mac_addr_add = i40e_macaddr_add,
278 .mac_addr_remove = i40e_macaddr_remove,
279 .reta_update = i40e_dev_rss_reta_update,
280 .reta_query = i40e_dev_rss_reta_query,
281 .rss_hash_update = i40e_dev_rss_hash_update,
282 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
283 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
284 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
285 .filter_ctrl = i40e_dev_filter_ctrl,
286 .mirror_rule_set = i40e_mirror_rule_set,
287 .mirror_rule_reset = i40e_mirror_rule_reset,
288 .timesync_enable = i40e_timesync_enable,
289 .timesync_disable = i40e_timesync_disable,
290 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
291 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
294 static struct eth_driver rte_i40e_pmd = {
296 .name = "rte_i40e_pmd",
297 .id_table = pci_id_i40e_map,
298 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
299 RTE_PCI_DRV_DETACHABLE,
301 .eth_dev_init = eth_i40e_dev_init,
302 .eth_dev_uninit = eth_i40e_dev_uninit,
303 .dev_private_size = sizeof(struct i40e_adapter),
307 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
308 struct rte_eth_link *link)
310 struct rte_eth_link *dst = link;
311 struct rte_eth_link *src = &(dev->data->dev_link);
313 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
314 *(uint64_t *)src) == 0)
321 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
322 struct rte_eth_link *link)
324 struct rte_eth_link *dst = &(dev->data->dev_link);
325 struct rte_eth_link *src = link;
327 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
328 *(uint64_t *)src) == 0)
335 * Driver initialization routine.
336 * Invoked once at EAL init time.
337 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
340 rte_i40e_pmd_init(const char *name __rte_unused,
341 const char *params __rte_unused)
343 PMD_INIT_FUNC_TRACE();
344 rte_eth_driver_register(&rte_i40e_pmd);
349 static struct rte_driver rte_i40e_driver = {
351 .init = rte_i40e_pmd_init,
354 PMD_REGISTER_DRIVER(rte_i40e_driver);
357 * Initialize registers for flexible payload, which should be set by NVM.
358 * This should be removed from code once it is fixed in NVM.
360 #ifndef I40E_GLQF_ORT
361 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
363 #ifndef I40E_GLQF_PIT
364 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
367 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
369 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
370 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
371 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
372 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
373 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
374 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
375 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
376 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
377 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
378 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
380 /* GLQF_PIT Registers */
381 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
382 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
386 eth_i40e_dev_init(struct rte_eth_dev *dev)
388 struct rte_pci_device *pci_dev;
389 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
390 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
391 struct i40e_vsi *vsi;
396 PMD_INIT_FUNC_TRACE();
398 dev->dev_ops = &i40e_eth_dev_ops;
399 dev->rx_pkt_burst = i40e_recv_pkts;
400 dev->tx_pkt_burst = i40e_xmit_pkts;
402 /* for secondary processes, we don't initialise any further as primary
403 * has already done this work. Only check we don't need a different
405 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
406 if (dev->data->scattered_rx)
407 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
410 pci_dev = dev->pci_dev;
411 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
412 pf->adapter->eth_dev = dev;
413 pf->dev_data = dev->data;
415 hw->back = I40E_PF_TO_ADAPTER(pf);
416 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
418 PMD_INIT_LOG(ERR, "Hardware is not available, "
419 "as address is NULL");
423 hw->vendor_id = pci_dev->id.vendor_id;
424 hw->device_id = pci_dev->id.device_id;
425 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
426 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
427 hw->bus.device = pci_dev->addr.devid;
428 hw->bus.func = pci_dev->addr.function;
429 hw->adapter_stopped = 0;
431 /* Make sure all is clean before doing PF reset */
434 /* Initialize the hardware */
437 /* Reset here to make sure all is clean for each PF */
438 ret = i40e_pf_reset(hw);
440 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
444 /* Initialize the shared code (base driver) */
445 ret = i40e_init_shared_code(hw);
447 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
452 * To work around the NVM issue,initialize registers
453 * for flexible payload by software.
454 * It should be removed once issues are fixed in NVM.
456 i40e_flex_payload_reg_init(hw);
458 /* Initialize the parameters for adminq */
459 i40e_init_adminq_parameter(hw);
460 ret = i40e_init_adminq(hw);
461 if (ret != I40E_SUCCESS) {
462 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
465 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
466 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
467 hw->aq.api_maj_ver, hw->aq.api_min_ver,
468 ((hw->nvm.version >> 12) & 0xf),
469 ((hw->nvm.version >> 4) & 0xff),
470 (hw->nvm.version & 0xf), hw->nvm.eetrack);
473 ret = i40e_aq_stop_lldp(hw, true, NULL);
474 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
475 PMD_INIT_LOG(INFO, "Failed to stop lldp");
478 i40e_clear_pxe_mode(hw);
481 * On X710, performance number is far from the expectation on recent
482 * firmware versions. The fix for this issue may not be integrated in
483 * the following firmware version. So the workaround in software driver
484 * is needed. It needs to modify the initial values of 3 internal only
485 * registers. Note that the workaround can be removed when it is fixed
486 * in firmware in the future.
488 i40e_configure_registers(hw);
490 /* Get hw capabilities */
491 ret = i40e_get_cap(hw);
492 if (ret != I40E_SUCCESS) {
493 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
494 goto err_get_capabilities;
497 /* Initialize parameters for PF */
498 ret = i40e_pf_parameter_init(dev);
500 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
501 goto err_parameter_init;
504 /* Initialize the queue management */
505 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
507 PMD_INIT_LOG(ERR, "Failed to init queue pool");
508 goto err_qp_pool_init;
510 ret = i40e_res_pool_init(&pf->msix_pool, 1,
511 hw->func_caps.num_msix_vectors - 1);
513 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
514 goto err_msix_pool_init;
517 /* Initialize lan hmc */
518 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
519 hw->func_caps.num_rx_qp, 0, 0);
520 if (ret != I40E_SUCCESS) {
521 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
522 goto err_init_lan_hmc;
525 /* Configure lan hmc */
526 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
527 if (ret != I40E_SUCCESS) {
528 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
529 goto err_configure_lan_hmc;
532 /* Get and check the mac address */
533 i40e_get_mac_addr(hw, hw->mac.addr);
534 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
535 PMD_INIT_LOG(ERR, "mac address is not valid");
537 goto err_get_mac_addr;
539 /* Copy the permanent MAC address */
540 ether_addr_copy((struct ether_addr *) hw->mac.addr,
541 (struct ether_addr *) hw->mac.perm_addr);
543 /* Disable flow control */
544 hw->fc.requested_mode = I40E_FC_NONE;
545 i40e_set_fc(hw, &aq_fail, TRUE);
547 /* PF setup, which includes VSI setup */
548 ret = i40e_pf_setup(pf);
550 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
551 goto err_setup_pf_switch;
556 /* Disable double vlan by default */
557 i40e_vsi_config_double_vlan(vsi, FALSE);
559 if (!vsi->max_macaddrs)
560 len = ETHER_ADDR_LEN;
562 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
564 /* Should be after VSI initialized */
565 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
566 if (!dev->data->mac_addrs) {
567 PMD_INIT_LOG(ERR, "Failed to allocated memory "
568 "for storing mac address");
571 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
572 &dev->data->mac_addrs[0]);
574 /* initialize pf host driver to setup SRIOV resource if applicable */
575 i40e_pf_host_init(dev);
577 /* register callback func to eal lib */
578 rte_intr_callback_register(&(pci_dev->intr_handle),
579 i40e_dev_interrupt_handler, (void *)dev);
581 /* configure and enable device interrupt */
582 i40e_pf_config_irq0(hw);
583 i40e_pf_enable_irq0(hw);
585 /* enable uio intr after callback register */
586 rte_intr_enable(&(pci_dev->intr_handle));
588 /* initialize mirror rule list */
589 TAILQ_INIT(&pf->mirror_list);
594 i40e_vsi_release(pf->main_vsi);
597 err_configure_lan_hmc:
598 (void)i40e_shutdown_lan_hmc(hw);
600 i40e_res_pool_destroy(&pf->msix_pool);
602 i40e_res_pool_destroy(&pf->qp_pool);
605 err_get_capabilities:
606 (void)i40e_shutdown_adminq(hw);
612 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
614 struct rte_pci_device *pci_dev;
616 struct i40e_filter_control_settings settings;
620 PMD_INIT_FUNC_TRACE();
622 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
625 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
626 pci_dev = dev->pci_dev;
628 if (hw->adapter_stopped == 0)
632 dev->rx_pkt_burst = NULL;
633 dev->tx_pkt_burst = NULL;
636 ret = i40e_aq_stop_lldp(hw, true, NULL);
637 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
638 PMD_INIT_LOG(INFO, "Failed to stop lldp");
641 i40e_clear_pxe_mode(hw);
643 /* Unconfigure filter control */
644 memset(&settings, 0, sizeof(settings));
645 ret = i40e_set_filter_control(hw, &settings);
647 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
650 /* Disable flow control */
651 hw->fc.requested_mode = I40E_FC_NONE;
652 i40e_set_fc(hw, &aq_fail, TRUE);
654 /* uninitialize pf host driver */
655 i40e_pf_host_uninit(dev);
657 rte_free(dev->data->mac_addrs);
658 dev->data->mac_addrs = NULL;
660 /* disable uio intr before callback unregister */
661 rte_intr_disable(&(pci_dev->intr_handle));
663 /* register callback func to eal lib */
664 rte_intr_callback_unregister(&(pci_dev->intr_handle),
665 i40e_dev_interrupt_handler, (void *)dev);
671 i40e_dev_configure(struct rte_eth_dev *dev)
673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
674 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
677 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
678 ret = i40e_fdir_setup(pf);
679 if (ret != I40E_SUCCESS) {
680 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
683 ret = i40e_fdir_configure(dev);
685 PMD_DRV_LOG(ERR, "failed to configure fdir.");
689 i40e_fdir_teardown(pf);
691 ret = i40e_dev_init_vlan(dev);
696 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
697 * RSS setting have different requirements.
698 * General PMD driver call sequence are NIC init, configure,
699 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
700 * will try to lookup the VSI that specific queue belongs to if VMDQ
701 * applicable. So, VMDQ setting has to be done before
702 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
703 * For RSS setting, it will try to calculate actual configured RX queue
704 * number, which will be available after rx_queue_setup(). dev_start()
705 * function is good to place RSS setup.
707 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
708 ret = i40e_vmdq_setup(dev);
714 i40e_fdir_teardown(pf);
719 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
721 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
722 uint16_t msix_vect = vsi->msix_intr;
725 for (i = 0; i < vsi->nb_qps; i++) {
726 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
727 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
731 if (vsi->type != I40E_VSI_SRIOV) {
732 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
733 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
737 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
738 vsi->user_param + (msix_vect - 1);
740 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
742 I40E_WRITE_FLUSH(hw);
745 static inline uint16_t
746 i40e_calc_itr_interval(int16_t interval)
748 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
749 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
751 /* Convert to hardware count, as writing each 1 represents 2 us */
756 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
759 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
760 uint16_t msix_vect = vsi->msix_intr;
763 for (i = 0; i < vsi->nb_qps; i++)
764 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
766 /* Bind all RX queues to allocated MSIX interrupt */
767 for (i = 0; i < vsi->nb_qps; i++) {
768 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
769 I40E_QINT_RQCTL_ITR_INDX_MASK |
770 ((vsi->base_queue + i + 1) <<
771 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
772 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
773 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
775 if (i == vsi->nb_qps - 1)
776 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
777 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
780 /* Write first RX queue to Link list register as the head element */
781 if (vsi->type != I40E_VSI_SRIOV) {
783 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
785 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
787 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
788 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
790 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
791 msix_vect - 1), interval);
793 #ifndef I40E_GLINT_CTL
794 #define I40E_GLINT_CTL 0x0003F800
795 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
797 /* Disable auto-mask on enabling of all none-zero interrupt */
798 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
799 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
803 /* num_msix_vectors_vf needs to minus irq0 */
804 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
805 vsi->user_param + (msix_vect - 1);
807 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
808 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
809 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
812 I40E_WRITE_FLUSH(hw);
816 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
818 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
819 uint16_t interval = i40e_calc_itr_interval(\
820 RTE_LIBRTE_I40E_ITR_INTERVAL);
822 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
823 I40E_PFINT_DYN_CTLN_INTENA_MASK |
824 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
825 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
826 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
830 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
832 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
834 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
837 static inline uint8_t
838 i40e_parse_link_speed(uint16_t eth_link_speed)
840 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
842 switch (eth_link_speed) {
843 case ETH_LINK_SPEED_40G:
844 link_speed = I40E_LINK_SPEED_40GB;
846 case ETH_LINK_SPEED_20G:
847 link_speed = I40E_LINK_SPEED_20GB;
849 case ETH_LINK_SPEED_10G:
850 link_speed = I40E_LINK_SPEED_10GB;
852 case ETH_LINK_SPEED_1000:
853 link_speed = I40E_LINK_SPEED_1GB;
855 case ETH_LINK_SPEED_100:
856 link_speed = I40E_LINK_SPEED_100MB;
864 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
866 enum i40e_status_code status;
867 struct i40e_aq_get_phy_abilities_resp phy_ab;
868 struct i40e_aq_set_phy_config phy_conf;
869 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
870 I40E_AQ_PHY_FLAG_PAUSE_RX |
871 I40E_AQ_PHY_FLAG_LOW_POWER;
872 const uint8_t advt = I40E_LINK_SPEED_40GB |
873 I40E_LINK_SPEED_10GB |
874 I40E_LINK_SPEED_1GB |
875 I40E_LINK_SPEED_100MB;
878 /* Skip it on 40G interfaces, as a workaround for the link issue */
879 if (i40e_is_40G_device(hw->device_id))
882 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
887 memset(&phy_conf, 0, sizeof(phy_conf));
889 /* bits 0-2 use the values from get_phy_abilities_resp */
891 abilities |= phy_ab.abilities & mask;
893 /* update ablities and speed */
894 if (abilities & I40E_AQ_PHY_AN_ENABLED)
895 phy_conf.link_speed = advt;
897 phy_conf.link_speed = force_speed;
899 phy_conf.abilities = abilities;
901 /* use get_phy_abilities_resp value for the rest */
902 phy_conf.phy_type = phy_ab.phy_type;
903 phy_conf.eee_capability = phy_ab.eee_capability;
904 phy_conf.eeer = phy_ab.eeer_val;
905 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
907 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
908 phy_ab.abilities, phy_ab.link_speed);
909 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
910 phy_conf.abilities, phy_conf.link_speed);
912 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
920 i40e_apply_link_speed(struct rte_eth_dev *dev)
923 uint8_t abilities = 0;
924 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
925 struct rte_eth_conf *conf = &dev->data->dev_conf;
927 speed = i40e_parse_link_speed(conf->link_speed);
928 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
929 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
930 abilities |= I40E_AQ_PHY_AN_ENABLED;
932 abilities |= I40E_AQ_PHY_LINK_ENABLED;
934 return i40e_phy_conf_link(hw, abilities, speed);
938 i40e_dev_start(struct rte_eth_dev *dev)
940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
942 struct i40e_vsi *main_vsi = pf->main_vsi;
945 hw->adapter_stopped = 0;
947 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
948 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
949 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
950 dev->data->dev_conf.link_duplex,
956 ret = i40e_dev_rxtx_init(pf);
957 if (ret != I40E_SUCCESS) {
958 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
962 /* Map queues with MSIX interrupt */
963 i40e_vsi_queues_bind_intr(main_vsi);
964 i40e_vsi_enable_queues_intr(main_vsi);
966 /* Map VMDQ VSI queues with MSIX interrupt */
967 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
968 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
969 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
972 /* enable FDIR MSIX interrupt */
973 if (pf->fdir.fdir_vsi) {
974 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
975 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
978 /* Enable all queues which have been configured */
979 ret = i40e_dev_switch_queues(pf, TRUE);
980 if (ret != I40E_SUCCESS) {
981 PMD_DRV_LOG(ERR, "Failed to enable VSI");
985 /* Enable receiving broadcast packets */
986 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
987 if (ret != I40E_SUCCESS)
988 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
990 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
991 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
993 if (ret != I40E_SUCCESS)
994 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
997 /* Apply link configure */
998 ret = i40e_apply_link_speed(dev);
999 if (I40E_SUCCESS != ret) {
1000 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1004 return I40E_SUCCESS;
1007 i40e_dev_switch_queues(pf, FALSE);
1008 i40e_dev_clear_queues(dev);
1014 i40e_dev_stop(struct rte_eth_dev *dev)
1016 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017 struct i40e_vsi *main_vsi = pf->main_vsi;
1018 struct i40e_mirror_rule *p_mirror;
1021 /* Disable all queues */
1022 i40e_dev_switch_queues(pf, FALSE);
1024 /* un-map queues with interrupt registers */
1025 i40e_vsi_disable_queues_intr(main_vsi);
1026 i40e_vsi_queues_unbind_intr(main_vsi);
1028 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1029 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1030 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1033 if (pf->fdir.fdir_vsi) {
1034 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1035 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1037 /* Clear all queues and release memory */
1038 i40e_dev_clear_queues(dev);
1041 i40e_dev_set_link_down(dev);
1043 /* Remove all mirror rules */
1044 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1045 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1048 pf->nb_mirror_rule = 0;
1053 i40e_dev_close(struct rte_eth_dev *dev)
1055 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1056 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060 PMD_INIT_FUNC_TRACE();
1063 hw->adapter_stopped = 1;
1064 i40e_dev_free_queues(dev);
1066 /* Disable interrupt */
1067 i40e_pf_disable_irq0(hw);
1068 rte_intr_disable(&(dev->pci_dev->intr_handle));
1070 /* shutdown and destroy the HMC */
1071 i40e_shutdown_lan_hmc(hw);
1073 /* release all the existing VSIs and VEBs */
1074 i40e_fdir_teardown(pf);
1075 i40e_vsi_release(pf->main_vsi);
1077 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1078 i40e_vsi_release(pf->vmdq[i].vsi);
1079 pf->vmdq[i].vsi = NULL;
1085 /* shutdown the adminq */
1086 i40e_aq_queue_shutdown(hw, true);
1087 i40e_shutdown_adminq(hw);
1089 i40e_res_pool_destroy(&pf->qp_pool);
1090 i40e_res_pool_destroy(&pf->msix_pool);
1092 /* force a PF reset to clean anything leftover */
1093 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1094 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1095 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1096 I40E_WRITE_FLUSH(hw);
1100 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1102 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1103 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104 struct i40e_vsi *vsi = pf->main_vsi;
1107 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1109 if (status != I40E_SUCCESS)
1110 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1112 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1114 if (status != I40E_SUCCESS)
1115 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1120 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1122 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1123 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1124 struct i40e_vsi *vsi = pf->main_vsi;
1127 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1129 if (status != I40E_SUCCESS)
1130 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1132 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1134 if (status != I40E_SUCCESS)
1135 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1139 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1143 struct i40e_vsi *vsi = pf->main_vsi;
1146 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1147 if (ret != I40E_SUCCESS)
1148 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1152 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1154 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1156 struct i40e_vsi *vsi = pf->main_vsi;
1159 if (dev->data->promiscuous == 1)
1160 return; /* must remain in all_multicast mode */
1162 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1163 vsi->seid, FALSE, NULL);
1164 if (ret != I40E_SUCCESS)
1165 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1169 * Set device link up.
1172 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1174 /* re-apply link speed setting */
1175 return i40e_apply_link_speed(dev);
1179 * Set device link down.
1182 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1184 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1185 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188 return i40e_phy_conf_link(hw, abilities, speed);
1192 i40e_dev_link_update(struct rte_eth_dev *dev,
1193 int wait_to_complete)
1195 #define CHECK_INTERVAL 100 /* 100ms */
1196 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1197 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1198 struct i40e_link_status link_status;
1199 struct rte_eth_link link, old;
1201 unsigned rep_cnt = MAX_REPEAT_TIME;
1203 memset(&link, 0, sizeof(link));
1204 memset(&old, 0, sizeof(old));
1205 memset(&link_status, 0, sizeof(link_status));
1206 rte_i40e_dev_atomic_read_link_status(dev, &old);
1209 /* Get link status information from hardware */
1210 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1211 if (status != I40E_SUCCESS) {
1212 link.link_speed = ETH_LINK_SPEED_100;
1213 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1214 PMD_DRV_LOG(ERR, "Failed to get link info");
1218 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1219 if (!wait_to_complete)
1222 rte_delay_ms(CHECK_INTERVAL);
1223 } while (!link.link_status && rep_cnt--);
1225 if (!link.link_status)
1228 /* i40e uses full duplex only */
1229 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1231 /* Parse the link status */
1232 switch (link_status.link_speed) {
1233 case I40E_LINK_SPEED_100MB:
1234 link.link_speed = ETH_LINK_SPEED_100;
1236 case I40E_LINK_SPEED_1GB:
1237 link.link_speed = ETH_LINK_SPEED_1000;
1239 case I40E_LINK_SPEED_10GB:
1240 link.link_speed = ETH_LINK_SPEED_10G;
1242 case I40E_LINK_SPEED_20GB:
1243 link.link_speed = ETH_LINK_SPEED_20G;
1245 case I40E_LINK_SPEED_40GB:
1246 link.link_speed = ETH_LINK_SPEED_40G;
1249 link.link_speed = ETH_LINK_SPEED_100;
1254 rte_i40e_dev_atomic_write_link_status(dev, &link);
1255 if (link.link_status == old.link_status)
1261 /* Get all the statistics of a VSI */
1263 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1265 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1266 struct i40e_eth_stats *nes = &vsi->eth_stats;
1267 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1268 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1270 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1271 vsi->offset_loaded, &oes->rx_bytes,
1273 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1274 vsi->offset_loaded, &oes->rx_unicast,
1276 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1277 vsi->offset_loaded, &oes->rx_multicast,
1278 &nes->rx_multicast);
1279 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1280 vsi->offset_loaded, &oes->rx_broadcast,
1281 &nes->rx_broadcast);
1282 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1283 &oes->rx_discards, &nes->rx_discards);
1284 /* GLV_REPC not supported */
1285 /* GLV_RMPC not supported */
1286 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1287 &oes->rx_unknown_protocol,
1288 &nes->rx_unknown_protocol);
1289 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1290 vsi->offset_loaded, &oes->tx_bytes,
1292 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1293 vsi->offset_loaded, &oes->tx_unicast,
1295 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1296 vsi->offset_loaded, &oes->tx_multicast,
1297 &nes->tx_multicast);
1298 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1299 vsi->offset_loaded, &oes->tx_broadcast,
1300 &nes->tx_broadcast);
1301 /* GLV_TDPC not supported */
1302 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1303 &oes->tx_errors, &nes->tx_errors);
1304 vsi->offset_loaded = true;
1306 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1308 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1309 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1310 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1311 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1312 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1313 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1314 nes->rx_unknown_protocol);
1315 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1316 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1317 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1318 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1319 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1320 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1321 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1325 /* Get all statistics of a port */
1327 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1330 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1331 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1333 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1335 /* Get statistics of struct i40e_eth_stats */
1336 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1337 I40E_GLPRT_GORCL(hw->port),
1338 pf->offset_loaded, &os->eth.rx_bytes,
1340 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1341 I40E_GLPRT_UPRCL(hw->port),
1342 pf->offset_loaded, &os->eth.rx_unicast,
1343 &ns->eth.rx_unicast);
1344 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1345 I40E_GLPRT_MPRCL(hw->port),
1346 pf->offset_loaded, &os->eth.rx_multicast,
1347 &ns->eth.rx_multicast);
1348 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1349 I40E_GLPRT_BPRCL(hw->port),
1350 pf->offset_loaded, &os->eth.rx_broadcast,
1351 &ns->eth.rx_broadcast);
1352 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1353 pf->offset_loaded, &os->eth.rx_discards,
1354 &ns->eth.rx_discards);
1355 /* GLPRT_REPC not supported */
1356 /* GLPRT_RMPC not supported */
1357 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1359 &os->eth.rx_unknown_protocol,
1360 &ns->eth.rx_unknown_protocol);
1361 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1362 I40E_GLPRT_GOTCL(hw->port),
1363 pf->offset_loaded, &os->eth.tx_bytes,
1365 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1366 I40E_GLPRT_UPTCL(hw->port),
1367 pf->offset_loaded, &os->eth.tx_unicast,
1368 &ns->eth.tx_unicast);
1369 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1370 I40E_GLPRT_MPTCL(hw->port),
1371 pf->offset_loaded, &os->eth.tx_multicast,
1372 &ns->eth.tx_multicast);
1373 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1374 I40E_GLPRT_BPTCL(hw->port),
1375 pf->offset_loaded, &os->eth.tx_broadcast,
1376 &ns->eth.tx_broadcast);
1377 /* GLPRT_TEPC not supported */
1379 /* additional port specific stats */
1380 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1381 pf->offset_loaded, &os->tx_dropped_link_down,
1382 &ns->tx_dropped_link_down);
1383 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1384 pf->offset_loaded, &os->crc_errors,
1386 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1387 pf->offset_loaded, &os->illegal_bytes,
1388 &ns->illegal_bytes);
1389 /* GLPRT_ERRBC not supported */
1390 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1391 pf->offset_loaded, &os->mac_local_faults,
1392 &ns->mac_local_faults);
1393 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1394 pf->offset_loaded, &os->mac_remote_faults,
1395 &ns->mac_remote_faults);
1396 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1397 pf->offset_loaded, &os->rx_length_errors,
1398 &ns->rx_length_errors);
1399 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1400 pf->offset_loaded, &os->link_xon_rx,
1402 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1403 pf->offset_loaded, &os->link_xoff_rx,
1405 for (i = 0; i < 8; i++) {
1406 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1408 &os->priority_xon_rx[i],
1409 &ns->priority_xon_rx[i]);
1410 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1412 &os->priority_xoff_rx[i],
1413 &ns->priority_xoff_rx[i]);
1415 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1416 pf->offset_loaded, &os->link_xon_tx,
1418 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1419 pf->offset_loaded, &os->link_xoff_tx,
1421 for (i = 0; i < 8; i++) {
1422 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1424 &os->priority_xon_tx[i],
1425 &ns->priority_xon_tx[i]);
1426 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1428 &os->priority_xoff_tx[i],
1429 &ns->priority_xoff_tx[i]);
1430 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1432 &os->priority_xon_2_xoff[i],
1433 &ns->priority_xon_2_xoff[i]);
1435 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1436 I40E_GLPRT_PRC64L(hw->port),
1437 pf->offset_loaded, &os->rx_size_64,
1439 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1440 I40E_GLPRT_PRC127L(hw->port),
1441 pf->offset_loaded, &os->rx_size_127,
1443 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1444 I40E_GLPRT_PRC255L(hw->port),
1445 pf->offset_loaded, &os->rx_size_255,
1447 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1448 I40E_GLPRT_PRC511L(hw->port),
1449 pf->offset_loaded, &os->rx_size_511,
1451 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1452 I40E_GLPRT_PRC1023L(hw->port),
1453 pf->offset_loaded, &os->rx_size_1023,
1455 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1456 I40E_GLPRT_PRC1522L(hw->port),
1457 pf->offset_loaded, &os->rx_size_1522,
1459 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1460 I40E_GLPRT_PRC9522L(hw->port),
1461 pf->offset_loaded, &os->rx_size_big,
1463 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1464 pf->offset_loaded, &os->rx_undersize,
1466 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1467 pf->offset_loaded, &os->rx_fragments,
1469 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1470 pf->offset_loaded, &os->rx_oversize,
1472 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1473 pf->offset_loaded, &os->rx_jabber,
1475 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1476 I40E_GLPRT_PTC64L(hw->port),
1477 pf->offset_loaded, &os->tx_size_64,
1479 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1480 I40E_GLPRT_PTC127L(hw->port),
1481 pf->offset_loaded, &os->tx_size_127,
1483 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1484 I40E_GLPRT_PTC255L(hw->port),
1485 pf->offset_loaded, &os->tx_size_255,
1487 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1488 I40E_GLPRT_PTC511L(hw->port),
1489 pf->offset_loaded, &os->tx_size_511,
1491 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1492 I40E_GLPRT_PTC1023L(hw->port),
1493 pf->offset_loaded, &os->tx_size_1023,
1495 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1496 I40E_GLPRT_PTC1522L(hw->port),
1497 pf->offset_loaded, &os->tx_size_1522,
1499 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1500 I40E_GLPRT_PTC9522L(hw->port),
1501 pf->offset_loaded, &os->tx_size_big,
1503 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1505 &os->fd_sb_match, &ns->fd_sb_match);
1506 /* GLPRT_MSPDC not supported */
1507 /* GLPRT_XEC not supported */
1509 pf->offset_loaded = true;
1512 i40e_update_vsi_stats(pf->main_vsi);
1514 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1515 ns->eth.rx_broadcast;
1516 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1517 ns->eth.tx_broadcast;
1518 stats->ibytes = ns->eth.rx_bytes;
1519 stats->obytes = ns->eth.tx_bytes;
1520 stats->oerrors = ns->eth.tx_errors;
1521 stats->imcasts = ns->eth.rx_multicast;
1522 stats->fdirmatch = ns->fd_sb_match;
1525 stats->ibadcrc = ns->crc_errors;
1526 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1527 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1528 stats->imissed = ns->eth.rx_discards;
1529 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1531 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1532 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
1533 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
1534 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
1535 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
1536 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
1537 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1538 ns->eth.rx_unknown_protocol);
1539 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
1540 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
1541 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
1542 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
1543 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
1544 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
1546 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
1547 ns->tx_dropped_link_down);
1548 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
1549 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
1551 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
1552 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
1553 ns->mac_local_faults);
1554 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
1555 ns->mac_remote_faults);
1556 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
1557 ns->rx_length_errors);
1558 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
1559 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
1560 for (i = 0; i < 8; i++) {
1561 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
1562 i, ns->priority_xon_rx[i]);
1563 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
1564 i, ns->priority_xoff_rx[i]);
1566 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
1567 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
1568 for (i = 0; i < 8; i++) {
1569 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
1570 i, ns->priority_xon_tx[i]);
1571 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
1572 i, ns->priority_xoff_tx[i]);
1573 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
1574 i, ns->priority_xon_2_xoff[i]);
1576 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
1577 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
1578 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
1579 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
1580 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
1581 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
1582 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
1583 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
1584 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
1585 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
1586 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
1587 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
1588 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
1589 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
1590 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
1591 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
1592 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
1593 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
1594 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1595 ns->mac_short_packet_dropped);
1596 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
1597 ns->checksum_error);
1598 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
1599 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1602 /* Reset the statistics */
1604 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1606 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1608 /* It results in reloading the start point of each counter */
1609 pf->offset_loaded = false;
1613 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1614 __rte_unused uint16_t queue_id,
1615 __rte_unused uint8_t stat_idx,
1616 __rte_unused uint8_t is_rx)
1618 PMD_INIT_FUNC_TRACE();
1624 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1627 struct i40e_vsi *vsi = pf->main_vsi;
1629 dev_info->max_rx_queues = vsi->nb_qps;
1630 dev_info->max_tx_queues = vsi->nb_qps;
1631 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1632 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1633 dev_info->max_mac_addrs = vsi->max_macaddrs;
1634 dev_info->max_vfs = dev->pci_dev->max_vfs;
1635 dev_info->rx_offload_capa =
1636 DEV_RX_OFFLOAD_VLAN_STRIP |
1637 DEV_RX_OFFLOAD_QINQ_STRIP |
1638 DEV_RX_OFFLOAD_IPV4_CKSUM |
1639 DEV_RX_OFFLOAD_UDP_CKSUM |
1640 DEV_RX_OFFLOAD_TCP_CKSUM;
1641 dev_info->tx_offload_capa =
1642 DEV_TX_OFFLOAD_VLAN_INSERT |
1643 DEV_TX_OFFLOAD_QINQ_INSERT |
1644 DEV_TX_OFFLOAD_IPV4_CKSUM |
1645 DEV_TX_OFFLOAD_UDP_CKSUM |
1646 DEV_TX_OFFLOAD_TCP_CKSUM |
1647 DEV_TX_OFFLOAD_SCTP_CKSUM |
1648 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1649 DEV_TX_OFFLOAD_TCP_TSO;
1650 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1652 dev_info->reta_size = pf->hash_lut_size;
1653 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1655 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1657 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1658 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1659 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1661 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1665 dev_info->default_txconf = (struct rte_eth_txconf) {
1667 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1668 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1669 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1671 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1672 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1673 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1674 ETH_TXQ_FLAGS_NOOFFLOADS,
1677 if (pf->flags & I40E_FLAG_VMDQ) {
1678 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1679 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1680 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1681 pf->max_nb_vmdq_vsi;
1682 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1683 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1684 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1689 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1692 struct i40e_vsi *vsi = pf->main_vsi;
1693 PMD_INIT_FUNC_TRACE();
1696 return i40e_vsi_add_vlan(vsi, vlan_id);
1698 return i40e_vsi_delete_vlan(vsi, vlan_id);
1702 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1703 __rte_unused uint16_t tpid)
1705 PMD_INIT_FUNC_TRACE();
1709 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1712 struct i40e_vsi *vsi = pf->main_vsi;
1714 if (mask & ETH_VLAN_STRIP_MASK) {
1715 /* Enable or disable VLAN stripping */
1716 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1717 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1719 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1722 if (mask & ETH_VLAN_EXTEND_MASK) {
1723 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1724 i40e_vsi_config_double_vlan(vsi, TRUE);
1726 i40e_vsi_config_double_vlan(vsi, FALSE);
1731 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1732 __rte_unused uint16_t queue,
1733 __rte_unused int on)
1735 PMD_INIT_FUNC_TRACE();
1739 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1741 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1742 struct i40e_vsi *vsi = pf->main_vsi;
1743 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1744 struct i40e_vsi_vlan_pvid_info info;
1746 memset(&info, 0, sizeof(info));
1749 info.config.pvid = pvid;
1751 info.config.reject.tagged =
1752 data->dev_conf.txmode.hw_vlan_reject_tagged;
1753 info.config.reject.untagged =
1754 data->dev_conf.txmode.hw_vlan_reject_untagged;
1757 return i40e_vsi_vlan_pvid_set(vsi, &info);
1761 i40e_dev_led_on(struct rte_eth_dev *dev)
1763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764 uint32_t mode = i40e_led_get(hw);
1767 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1773 i40e_dev_led_off(struct rte_eth_dev *dev)
1775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776 uint32_t mode = i40e_led_get(hw);
1779 i40e_led_set(hw, 0, false);
1785 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1786 __rte_unused struct rte_eth_fc_conf *fc_conf)
1788 PMD_INIT_FUNC_TRACE();
1794 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1795 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1797 PMD_INIT_FUNC_TRACE();
1802 /* Add a MAC address, and update filters */
1804 i40e_macaddr_add(struct rte_eth_dev *dev,
1805 struct ether_addr *mac_addr,
1806 __rte_unused uint32_t index,
1809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1810 struct i40e_mac_filter_info mac_filter;
1811 struct i40e_vsi *vsi;
1814 /* If VMDQ not enabled or configured, return */
1815 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1816 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1817 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1822 if (pool > pf->nb_cfg_vmdq_vsi) {
1823 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1824 pool, pf->nb_cfg_vmdq_vsi);
1828 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1829 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1834 vsi = pf->vmdq[pool - 1].vsi;
1836 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1837 if (ret != I40E_SUCCESS) {
1838 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1843 /* Remove a MAC address, and update filters */
1845 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1847 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1848 struct i40e_vsi *vsi;
1849 struct rte_eth_dev_data *data = dev->data;
1850 struct ether_addr *macaddr;
1855 macaddr = &(data->mac_addrs[index]);
1857 pool_sel = dev->data->mac_pool_sel[index];
1859 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1860 if (pool_sel & (1ULL << i)) {
1864 /* No VMDQ pool enabled or configured */
1865 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1866 (i > pf->nb_cfg_vmdq_vsi)) {
1867 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1871 vsi = pf->vmdq[i - 1].vsi;
1873 ret = i40e_vsi_delete_mac(vsi, macaddr);
1876 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1883 /* Set perfect match or hash match of MAC and VLAN for a VF */
1885 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1886 struct rte_eth_mac_filter *filter,
1890 struct i40e_mac_filter_info mac_filter;
1891 struct ether_addr old_mac;
1892 struct ether_addr *new_mac;
1893 struct i40e_pf_vf *vf = NULL;
1898 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1901 hw = I40E_PF_TO_HW(pf);
1903 if (filter == NULL) {
1904 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1908 new_mac = &filter->mac_addr;
1910 if (is_zero_ether_addr(new_mac)) {
1911 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1915 vf_id = filter->dst_id;
1917 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1918 PMD_DRV_LOG(ERR, "Invalid argument.");
1921 vf = &pf->vfs[vf_id];
1923 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1924 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1929 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1930 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1932 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1935 mac_filter.filter_type = filter->filter_type;
1936 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1937 if (ret != I40E_SUCCESS) {
1938 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1941 ether_addr_copy(new_mac, &pf->dev_addr);
1943 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1945 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1946 if (ret != I40E_SUCCESS) {
1947 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1951 /* Clear device address as it has been removed */
1952 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1953 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1959 /* MAC filter handle */
1961 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1965 struct rte_eth_mac_filter *filter;
1966 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1967 int ret = I40E_NOT_SUPPORTED;
1969 filter = (struct rte_eth_mac_filter *)(arg);
1971 switch (filter_op) {
1972 case RTE_ETH_FILTER_NOP:
1975 case RTE_ETH_FILTER_ADD:
1976 i40e_pf_disable_irq0(hw);
1978 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1979 i40e_pf_enable_irq0(hw);
1981 case RTE_ETH_FILTER_DELETE:
1982 i40e_pf_disable_irq0(hw);
1984 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1985 i40e_pf_enable_irq0(hw);
1988 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1989 ret = I40E_ERR_PARAM;
1997 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1998 struct rte_eth_rss_reta_entry64 *reta_conf,
2001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2002 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004 uint16_t i, j, lut_size = pf->hash_lut_size;
2005 uint16_t idx, shift;
2008 if (reta_size != lut_size ||
2009 reta_size > ETH_RSS_RETA_SIZE_512) {
2010 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2011 "(%d) doesn't match the number hardware can supported "
2012 "(%d)\n", reta_size, lut_size);
2016 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2017 idx = i / RTE_RETA_GROUP_SIZE;
2018 shift = i % RTE_RETA_GROUP_SIZE;
2019 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2023 if (mask == I40E_4_BIT_MASK)
2026 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2027 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2028 if (mask & (0x1 << j))
2029 lut |= reta_conf[idx].reta[shift + j] <<
2032 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2034 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2041 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2042 struct rte_eth_rss_reta_entry64 *reta_conf,
2045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2046 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048 uint16_t i, j, lut_size = pf->hash_lut_size;
2049 uint16_t idx, shift;
2052 if (reta_size != lut_size ||
2053 reta_size > ETH_RSS_RETA_SIZE_512) {
2054 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2055 "(%d) doesn't match the number hardware can supported "
2056 "(%d)\n", reta_size, lut_size);
2060 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2061 idx = i / RTE_RETA_GROUP_SIZE;
2062 shift = i % RTE_RETA_GROUP_SIZE;
2063 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2068 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2069 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2070 if (mask & (0x1 << j))
2071 reta_conf[idx].reta[shift + j] = ((lut >>
2072 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2080 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2081 * @hw: pointer to the HW structure
2082 * @mem: pointer to mem struct to fill out
2083 * @size: size of memory requested
2084 * @alignment: what to align the allocation to
2086 enum i40e_status_code
2087 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2088 struct i40e_dma_mem *mem,
2092 static uint64_t id = 0;
2093 const struct rte_memzone *mz = NULL;
2094 char z_name[RTE_MEMZONE_NAMESIZE];
2097 return I40E_ERR_PARAM;
2100 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2101 #ifdef RTE_LIBRTE_XEN_DOM0
2102 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
2105 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2108 return I40E_ERR_NO_MEMORY;
2113 #ifdef RTE_LIBRTE_XEN_DOM0
2114 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2116 mem->pa = mz->phys_addr;
2119 return I40E_SUCCESS;
2123 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2124 * @hw: pointer to the HW structure
2125 * @mem: ptr to mem struct to free
2127 enum i40e_status_code
2128 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2129 struct i40e_dma_mem *mem)
2131 if (!mem || !mem->va)
2132 return I40E_ERR_PARAM;
2137 return I40E_SUCCESS;
2141 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2142 * @hw: pointer to the HW structure
2143 * @mem: pointer to mem struct to fill out
2144 * @size: size of memory requested
2146 enum i40e_status_code
2147 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2148 struct i40e_virt_mem *mem,
2152 return I40E_ERR_PARAM;
2155 mem->va = rte_zmalloc("i40e", size, 0);
2158 return I40E_SUCCESS;
2160 return I40E_ERR_NO_MEMORY;
2164 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2165 * @hw: pointer to the HW structure
2166 * @mem: pointer to mem struct to free
2168 enum i40e_status_code
2169 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2170 struct i40e_virt_mem *mem)
2173 return I40E_ERR_PARAM;
2178 return I40E_SUCCESS;
2182 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2184 rte_spinlock_init(&sp->spinlock);
2188 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2190 rte_spinlock_lock(&sp->spinlock);
2194 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2196 rte_spinlock_unlock(&sp->spinlock);
2200 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2206 * Get the hardware capabilities, which will be parsed
2207 * and saved into struct i40e_hw.
2210 i40e_get_cap(struct i40e_hw *hw)
2212 struct i40e_aqc_list_capabilities_element_resp *buf;
2213 uint16_t len, size = 0;
2216 /* Calculate a huge enough buff for saving response data temporarily */
2217 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2218 I40E_MAX_CAP_ELE_NUM;
2219 buf = rte_zmalloc("i40e", len, 0);
2221 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2222 return I40E_ERR_NO_MEMORY;
2225 /* Get, parse the capabilities and save it to hw */
2226 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2227 i40e_aqc_opc_list_func_capabilities, NULL);
2228 if (ret != I40E_SUCCESS)
2229 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2231 /* Free the temporary buffer after being used */
2238 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2240 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2241 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2242 uint16_t sum_queues = 0, sum_vsis, left_queues;
2244 /* First check if FW support SRIOV */
2245 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2246 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2250 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2251 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2252 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2253 /* Allocate queues for pf */
2254 if (hw->func_caps.rss) {
2255 pf->flags |= I40E_FLAG_RSS;
2256 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2257 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2258 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2261 sum_queues = pf->lan_nb_qps;
2262 /* Default VSI is not counted in */
2264 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2266 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2267 pf->flags |= I40E_FLAG_SRIOV;
2268 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2269 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2270 PMD_INIT_LOG(ERR, "Config VF number %u, "
2271 "max supported %u.",
2272 dev->pci_dev->max_vfs,
2273 hw->func_caps.num_vfs);
2276 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2277 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2278 "max support %u queues.",
2279 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2282 pf->vf_num = dev->pci_dev->max_vfs;
2283 sum_queues += pf->vf_nb_qps * pf->vf_num;
2284 sum_vsis += pf->vf_num;
2285 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2286 pf->vf_num, pf->vf_nb_qps);
2290 if (hw->func_caps.vmdq) {
2291 pf->flags |= I40E_FLAG_VMDQ;
2292 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2293 pf->max_nb_vmdq_vsi = 1;
2295 * If VMDQ available, assume a single VSI can be created. Will adjust
2298 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2299 sum_vsis += pf->max_nb_vmdq_vsi;
2301 pf->vmdq_nb_qps = 0;
2302 pf->max_nb_vmdq_vsi = 0;
2304 pf->nb_cfg_vmdq_vsi = 0;
2306 if (hw->func_caps.fd) {
2307 pf->flags |= I40E_FLAG_FDIR;
2308 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2310 * Each flow director consumes one VSI and one queue,
2311 * but can't calculate out predictably here.
2315 if (sum_vsis > pf->max_num_vsi ||
2316 sum_queues > hw->func_caps.num_rx_qp) {
2317 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2318 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2319 pf->max_num_vsi, sum_vsis);
2320 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2321 hw->func_caps.num_rx_qp, sum_queues);
2325 /* Adjust VMDQ setting to support as many VMs as possible */
2326 if (pf->flags & I40E_FLAG_VMDQ) {
2327 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2329 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2330 pf->max_num_vsi - sum_vsis);
2332 /* Limit the max VMDQ number that rte_ether that can support */
2333 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2336 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2337 pf->max_nb_vmdq_vsi);
2338 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2341 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2343 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2344 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2345 sum_vsis, hw->func_caps.num_msix_vectors);
2348 return I40E_SUCCESS;
2352 i40e_pf_get_switch_config(struct i40e_pf *pf)
2354 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2355 struct i40e_aqc_get_switch_config_resp *switch_config;
2356 struct i40e_aqc_switch_config_element_resp *element;
2357 uint16_t start_seid = 0, num_reported;
2360 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2361 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2362 if (!switch_config) {
2363 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2367 /* Get the switch configurations */
2368 ret = i40e_aq_get_switch_config(hw, switch_config,
2369 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2370 if (ret != I40E_SUCCESS) {
2371 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2374 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2375 if (num_reported != 1) { /* The number should be 1 */
2376 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2380 /* Parse the switch configuration elements */
2381 element = &(switch_config->element[0]);
2382 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2383 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2384 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2386 PMD_DRV_LOG(INFO, "Unknown element type");
2389 rte_free(switch_config);
2395 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2398 struct pool_entry *entry;
2400 if (pool == NULL || num == 0)
2403 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2404 if (entry == NULL) {
2405 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2409 /* queue heap initialize */
2410 pool->num_free = num;
2411 pool->num_alloc = 0;
2413 LIST_INIT(&pool->alloc_list);
2414 LIST_INIT(&pool->free_list);
2416 /* Initialize element */
2420 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2425 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2427 struct pool_entry *entry;
2432 LIST_FOREACH(entry, &pool->alloc_list, next) {
2433 LIST_REMOVE(entry, next);
2437 LIST_FOREACH(entry, &pool->free_list, next) {
2438 LIST_REMOVE(entry, next);
2443 pool->num_alloc = 0;
2445 LIST_INIT(&pool->alloc_list);
2446 LIST_INIT(&pool->free_list);
2450 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2453 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2454 uint32_t pool_offset;
2458 PMD_DRV_LOG(ERR, "Invalid parameter");
2462 pool_offset = base - pool->base;
2463 /* Lookup in alloc list */
2464 LIST_FOREACH(entry, &pool->alloc_list, next) {
2465 if (entry->base == pool_offset) {
2466 valid_entry = entry;
2467 LIST_REMOVE(entry, next);
2472 /* Not find, return */
2473 if (valid_entry == NULL) {
2474 PMD_DRV_LOG(ERR, "Failed to find entry");
2479 * Found it, move it to free list and try to merge.
2480 * In order to make merge easier, always sort it by qbase.
2481 * Find adjacent prev and last entries.
2484 LIST_FOREACH(entry, &pool->free_list, next) {
2485 if (entry->base > valid_entry->base) {
2493 /* Try to merge with next one*/
2495 /* Merge with next one */
2496 if (valid_entry->base + valid_entry->len == next->base) {
2497 next->base = valid_entry->base;
2498 next->len += valid_entry->len;
2499 rte_free(valid_entry);
2506 /* Merge with previous one */
2507 if (prev->base + prev->len == valid_entry->base) {
2508 prev->len += valid_entry->len;
2509 /* If it merge with next one, remove next node */
2511 LIST_REMOVE(valid_entry, next);
2512 rte_free(valid_entry);
2514 rte_free(valid_entry);
2520 /* Not find any entry to merge, insert */
2523 LIST_INSERT_AFTER(prev, valid_entry, next);
2524 else if (next != NULL)
2525 LIST_INSERT_BEFORE(next, valid_entry, next);
2526 else /* It's empty list, insert to head */
2527 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2530 pool->num_free += valid_entry->len;
2531 pool->num_alloc -= valid_entry->len;
2537 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2540 struct pool_entry *entry, *valid_entry;
2542 if (pool == NULL || num == 0) {
2543 PMD_DRV_LOG(ERR, "Invalid parameter");
2547 if (pool->num_free < num) {
2548 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2549 num, pool->num_free);
2554 /* Lookup in free list and find most fit one */
2555 LIST_FOREACH(entry, &pool->free_list, next) {
2556 if (entry->len >= num) {
2558 if (entry->len == num) {
2559 valid_entry = entry;
2562 if (valid_entry == NULL || valid_entry->len > entry->len)
2563 valid_entry = entry;
2567 /* Not find one to satisfy the request, return */
2568 if (valid_entry == NULL) {
2569 PMD_DRV_LOG(ERR, "No valid entry found");
2573 * The entry have equal queue number as requested,
2574 * remove it from alloc_list.
2576 if (valid_entry->len == num) {
2577 LIST_REMOVE(valid_entry, next);
2580 * The entry have more numbers than requested,
2581 * create a new entry for alloc_list and minus its
2582 * queue base and number in free_list.
2584 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2585 if (entry == NULL) {
2586 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2590 entry->base = valid_entry->base;
2592 valid_entry->base += num;
2593 valid_entry->len -= num;
2594 valid_entry = entry;
2597 /* Insert it into alloc list, not sorted */
2598 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2600 pool->num_free -= valid_entry->len;
2601 pool->num_alloc += valid_entry->len;
2603 return (valid_entry->base + pool->base);
2607 * bitmap_is_subset - Check whether src2 is subset of src1
2610 bitmap_is_subset(uint8_t src1, uint8_t src2)
2612 return !((src1 ^ src2) & src2);
2616 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2618 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2620 /* If DCB is not supported, only default TC is supported */
2621 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2622 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2626 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2627 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2628 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2632 return I40E_SUCCESS;
2636 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2637 struct i40e_vsi_vlan_pvid_info *info)
2640 struct i40e_vsi_context ctxt;
2641 uint8_t vlan_flags = 0;
2644 if (vsi == NULL || info == NULL) {
2645 PMD_DRV_LOG(ERR, "invalid parameters");
2646 return I40E_ERR_PARAM;
2650 vsi->info.pvid = info->config.pvid;
2652 * If insert pvid is enabled, only tagged pkts are
2653 * allowed to be sent out.
2655 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2656 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2659 if (info->config.reject.tagged == 0)
2660 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2662 if (info->config.reject.untagged == 0)
2663 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2665 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2666 I40E_AQ_VSI_PVLAN_MODE_MASK);
2667 vsi->info.port_vlan_flags |= vlan_flags;
2668 vsi->info.valid_sections =
2669 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2670 memset(&ctxt, 0, sizeof(ctxt));
2671 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2672 ctxt.seid = vsi->seid;
2674 hw = I40E_VSI_TO_HW(vsi);
2675 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2676 if (ret != I40E_SUCCESS)
2677 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2683 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2685 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2687 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2689 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2690 if (ret != I40E_SUCCESS)
2694 PMD_DRV_LOG(ERR, "seid not valid");
2698 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2699 tc_bw_data.tc_valid_bits = enabled_tcmap;
2700 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2701 tc_bw_data.tc_bw_credits[i] =
2702 (enabled_tcmap & (1 << i)) ? 1 : 0;
2704 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2705 if (ret != I40E_SUCCESS) {
2706 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2710 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2711 sizeof(vsi->info.qs_handle));
2712 return I40E_SUCCESS;
2716 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2717 struct i40e_aqc_vsi_properties_data *info,
2718 uint8_t enabled_tcmap)
2720 int ret, total_tc = 0, i;
2721 uint16_t qpnum_per_tc, bsf, qp_idx;
2723 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2724 if (ret != I40E_SUCCESS)
2727 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2728 if (enabled_tcmap & (1 << i))
2730 vsi->enabled_tc = enabled_tcmap;
2732 /* Number of queues per enabled TC */
2733 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2734 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2735 bsf = rte_bsf32(qpnum_per_tc);
2737 /* Adjust the queue number to actual queues that can be applied */
2738 vsi->nb_qps = qpnum_per_tc * total_tc;
2741 * Configure TC and queue mapping parameters, for enabled TC,
2742 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2743 * default queue will serve it.
2746 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2747 if (vsi->enabled_tc & (1 << i)) {
2748 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2749 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2750 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2751 qp_idx += qpnum_per_tc;
2753 info->tc_mapping[i] = 0;
2756 /* Associate queue number with VSI */
2757 if (vsi->type == I40E_VSI_SRIOV) {
2758 info->mapping_flags |=
2759 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2760 for (i = 0; i < vsi->nb_qps; i++)
2761 info->queue_mapping[i] =
2762 rte_cpu_to_le_16(vsi->base_queue + i);
2764 info->mapping_flags |=
2765 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2766 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2768 info->valid_sections |=
2769 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2771 return I40E_SUCCESS;
2775 i40e_veb_release(struct i40e_veb *veb)
2777 struct i40e_vsi *vsi;
2780 if (veb == NULL || veb->associate_vsi == NULL)
2783 if (!TAILQ_EMPTY(&veb->head)) {
2784 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2788 vsi = veb->associate_vsi;
2789 hw = I40E_VSI_TO_HW(vsi);
2791 vsi->uplink_seid = veb->uplink_seid;
2792 i40e_aq_delete_element(hw, veb->seid, NULL);
2795 return I40E_SUCCESS;
2799 static struct i40e_veb *
2800 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2802 struct i40e_veb *veb;
2806 if (NULL == pf || vsi == NULL) {
2807 PMD_DRV_LOG(ERR, "veb setup failed, "
2808 "associated VSI shouldn't null");
2811 hw = I40E_PF_TO_HW(pf);
2813 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2815 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2819 veb->associate_vsi = vsi;
2820 TAILQ_INIT(&veb->head);
2821 veb->uplink_seid = vsi->uplink_seid;
2823 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2824 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2826 if (ret != I40E_SUCCESS) {
2827 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2828 hw->aq.asq_last_status);
2832 /* get statistics index */
2833 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2834 &veb->stats_idx, NULL, NULL, NULL);
2835 if (ret != I40E_SUCCESS) {
2836 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2837 hw->aq.asq_last_status);
2841 /* Get VEB bandwidth, to be implemented */
2842 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2843 vsi->uplink_seid = veb->seid;
2852 i40e_vsi_release(struct i40e_vsi *vsi)
2856 struct i40e_vsi_list *vsi_list;
2858 struct i40e_mac_filter *f;
2861 return I40E_SUCCESS;
2863 pf = I40E_VSI_TO_PF(vsi);
2864 hw = I40E_VSI_TO_HW(vsi);
2866 /* VSI has child to attach, release child first */
2868 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2869 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2871 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2873 i40e_veb_release(vsi->veb);
2876 /* Remove all macvlan filters of the VSI */
2877 i40e_vsi_remove_all_macvlan_filter(vsi);
2878 TAILQ_FOREACH(f, &vsi->mac_list, next)
2881 if (vsi->type != I40E_VSI_MAIN) {
2882 /* Remove vsi from parent's sibling list */
2883 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2884 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2885 return I40E_ERR_PARAM;
2887 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2888 &vsi->sib_vsi_list, list);
2890 /* Remove all switch element of the VSI */
2891 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2892 if (ret != I40E_SUCCESS)
2893 PMD_DRV_LOG(ERR, "Failed to delete element");
2895 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2897 if (vsi->type != I40E_VSI_SRIOV)
2898 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2901 return I40E_SUCCESS;
2905 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2907 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2908 struct i40e_aqc_remove_macvlan_element_data def_filter;
2909 struct i40e_mac_filter_info filter;
2912 if (vsi->type != I40E_VSI_MAIN)
2913 return I40E_ERR_CONFIG;
2914 memset(&def_filter, 0, sizeof(def_filter));
2915 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2917 def_filter.vlan_tag = 0;
2918 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2919 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2920 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2921 if (ret != I40E_SUCCESS) {
2922 struct i40e_mac_filter *f;
2923 struct ether_addr *mac;
2925 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2927 /* It needs to add the permanent mac into mac list */
2928 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2930 PMD_DRV_LOG(ERR, "failed to allocate memory");
2931 return I40E_ERR_NO_MEMORY;
2933 mac = &f->mac_info.mac_addr;
2934 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2936 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2937 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2942 (void)rte_memcpy(&filter.mac_addr,
2943 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2944 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2945 return i40e_vsi_add_mac(vsi, &filter);
2949 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2951 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2952 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2953 struct i40e_hw *hw = &vsi->adapter->hw;
2957 memset(&bw_config, 0, sizeof(bw_config));
2958 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2959 if (ret != I40E_SUCCESS) {
2960 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2961 hw->aq.asq_last_status);
2965 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2966 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2967 &ets_sla_config, NULL);
2968 if (ret != I40E_SUCCESS) {
2969 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2970 "configuration %u", hw->aq.asq_last_status);
2974 /* Not store the info yet, just print out */
2975 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2976 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2977 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2978 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2979 ets_sla_config.share_credits[i]);
2980 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2981 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2982 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2983 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2992 i40e_vsi_setup(struct i40e_pf *pf,
2993 enum i40e_vsi_type type,
2994 struct i40e_vsi *uplink_vsi,
2995 uint16_t user_param)
2997 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2998 struct i40e_vsi *vsi;
2999 struct i40e_mac_filter_info filter;
3001 struct i40e_vsi_context ctxt;
3002 struct ether_addr broadcast =
3003 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3005 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3006 PMD_DRV_LOG(ERR, "VSI setup failed, "
3007 "VSI link shouldn't be NULL");
3011 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3012 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3013 "uplink VSI should be NULL");
3017 /* If uplink vsi didn't setup VEB, create one first */
3018 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3019 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3021 if (NULL == uplink_vsi->veb) {
3022 PMD_DRV_LOG(ERR, "VEB setup failed");
3027 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3029 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3032 TAILQ_INIT(&vsi->mac_list);
3034 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3035 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3036 vsi->parent_vsi = uplink_vsi;
3037 vsi->user_param = user_param;
3038 /* Allocate queues */
3039 switch (vsi->type) {
3040 case I40E_VSI_MAIN :
3041 vsi->nb_qps = pf->lan_nb_qps;
3043 case I40E_VSI_SRIOV :
3044 vsi->nb_qps = pf->vf_nb_qps;
3046 case I40E_VSI_VMDQ2:
3047 vsi->nb_qps = pf->vmdq_nb_qps;
3050 vsi->nb_qps = pf->fdir_nb_qps;
3056 * The filter status descriptor is reported in rx queue 0,
3057 * while the tx queue for fdir filter programming has no
3058 * such constraints, can be non-zero queues.
3059 * To simplify it, choose FDIR vsi use queue 0 pair.
3060 * To make sure it will use queue 0 pair, queue allocation
3061 * need be done before this function is called
3063 if (type != I40E_VSI_FDIR) {
3064 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3066 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3070 vsi->base_queue = ret;
3072 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3074 /* VF has MSIX interrupt in VF range, don't allocate here */
3075 if (type != I40E_VSI_SRIOV) {
3076 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3078 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3079 goto fail_queue_alloc;
3081 vsi->msix_intr = ret;
3085 if (type == I40E_VSI_MAIN) {
3086 /* For main VSI, no need to add since it's default one */
3087 vsi->uplink_seid = pf->mac_seid;
3088 vsi->seid = pf->main_vsi_seid;
3089 /* Bind queues with specific MSIX interrupt */
3091 * Needs 2 interrupt at least, one for misc cause which will
3092 * enabled from OS side, Another for queues binding the
3093 * interrupt from device side only.
3096 /* Get default VSI parameters from hardware */
3097 memset(&ctxt, 0, sizeof(ctxt));
3098 ctxt.seid = vsi->seid;
3099 ctxt.pf_num = hw->pf_id;
3100 ctxt.uplink_seid = vsi->uplink_seid;
3102 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3103 if (ret != I40E_SUCCESS) {
3104 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3105 goto fail_msix_alloc;
3107 (void)rte_memcpy(&vsi->info, &ctxt.info,
3108 sizeof(struct i40e_aqc_vsi_properties_data));
3109 vsi->vsi_id = ctxt.vsi_number;
3110 vsi->info.valid_sections = 0;
3112 /* Configure tc, enabled TC0 only */
3113 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3115 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3116 goto fail_msix_alloc;
3119 /* TC, queue mapping */
3120 memset(&ctxt, 0, sizeof(ctxt));
3121 vsi->info.valid_sections |=
3122 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3123 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3124 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3125 (void)rte_memcpy(&ctxt.info, &vsi->info,
3126 sizeof(struct i40e_aqc_vsi_properties_data));
3127 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3128 I40E_DEFAULT_TCMAP);
3129 if (ret != I40E_SUCCESS) {
3130 PMD_DRV_LOG(ERR, "Failed to configure "
3131 "TC queue mapping");
3132 goto fail_msix_alloc;
3134 ctxt.seid = vsi->seid;
3135 ctxt.pf_num = hw->pf_id;
3136 ctxt.uplink_seid = vsi->uplink_seid;
3139 /* Update VSI parameters */
3140 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3141 if (ret != I40E_SUCCESS) {
3142 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3143 goto fail_msix_alloc;
3146 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3147 sizeof(vsi->info.tc_mapping));
3148 (void)rte_memcpy(&vsi->info.queue_mapping,
3149 &ctxt.info.queue_mapping,
3150 sizeof(vsi->info.queue_mapping));
3151 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3152 vsi->info.valid_sections = 0;
3154 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3158 * Updating default filter settings are necessary to prevent
3159 * reception of tagged packets.
3160 * Some old firmware configurations load a default macvlan
3161 * filter which accepts both tagged and untagged packets.
3162 * The updating is to use a normal filter instead if needed.
3163 * For NVM 4.2.2 or after, the updating is not needed anymore.
3164 * The firmware with correct configurations load the default
3165 * macvlan filter which is expected and cannot be removed.
3167 i40e_update_default_filter_setting(vsi);
3168 i40e_config_qinq(hw, vsi);
3169 } else if (type == I40E_VSI_SRIOV) {
3170 memset(&ctxt, 0, sizeof(ctxt));
3172 * For other VSI, the uplink_seid equals to uplink VSI's
3173 * uplink_seid since they share same VEB
3175 vsi->uplink_seid = uplink_vsi->uplink_seid;
3176 ctxt.pf_num = hw->pf_id;
3177 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3178 ctxt.uplink_seid = vsi->uplink_seid;
3179 ctxt.connection_type = 0x1;
3180 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3183 * Do not configure switch ID to enable VEB switch by
3184 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3185 * if the source mac address of packet sent from VF is not
3186 * listed in the VEB's mac table, the VEB will switch the
3187 * packet back to the VF. Need to enable it when HW issue
3191 /* Configure port/vlan */
3192 ctxt.info.valid_sections |=
3193 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3194 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3195 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3196 I40E_DEFAULT_TCMAP);
3197 if (ret != I40E_SUCCESS) {
3198 PMD_DRV_LOG(ERR, "Failed to configure "
3199 "TC queue mapping");
3200 goto fail_msix_alloc;
3202 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3203 ctxt.info.valid_sections |=
3204 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3206 * Since VSI is not created yet, only configure parameter,
3207 * will add vsi below.
3210 i40e_config_qinq(hw, vsi);
3211 } else if (type == I40E_VSI_VMDQ2) {
3212 memset(&ctxt, 0, sizeof(ctxt));
3214 * For other VSI, the uplink_seid equals to uplink VSI's
3215 * uplink_seid since they share same VEB
3217 vsi->uplink_seid = uplink_vsi->uplink_seid;
3218 ctxt.pf_num = hw->pf_id;
3220 ctxt.uplink_seid = vsi->uplink_seid;
3221 ctxt.connection_type = 0x1;
3222 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3224 ctxt.info.valid_sections |=
3225 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3226 /* user_param carries flag to enable loop back */
3228 ctxt.info.switch_id =
3229 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3230 ctxt.info.switch_id |=
3231 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3234 /* Configure port/vlan */
3235 ctxt.info.valid_sections |=
3236 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3237 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3238 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3239 I40E_DEFAULT_TCMAP);
3240 if (ret != I40E_SUCCESS) {
3241 PMD_DRV_LOG(ERR, "Failed to configure "
3242 "TC queue mapping");
3243 goto fail_msix_alloc;
3245 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3246 ctxt.info.valid_sections |=
3247 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3248 } else if (type == I40E_VSI_FDIR) {
3249 memset(&ctxt, 0, sizeof(ctxt));
3250 vsi->uplink_seid = uplink_vsi->uplink_seid;
3251 ctxt.pf_num = hw->pf_id;
3253 ctxt.uplink_seid = vsi->uplink_seid;
3254 ctxt.connection_type = 0x1; /* regular data port */
3255 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3256 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3257 I40E_DEFAULT_TCMAP);
3258 if (ret != I40E_SUCCESS) {
3259 PMD_DRV_LOG(ERR, "Failed to configure "
3260 "TC queue mapping.");
3261 goto fail_msix_alloc;
3263 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3264 ctxt.info.valid_sections |=
3265 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3267 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3268 goto fail_msix_alloc;
3271 if (vsi->type != I40E_VSI_MAIN) {
3272 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3273 if (ret != I40E_SUCCESS) {
3274 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3275 hw->aq.asq_last_status);
3276 goto fail_msix_alloc;
3278 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3279 vsi->info.valid_sections = 0;
3280 vsi->seid = ctxt.seid;
3281 vsi->vsi_id = ctxt.vsi_number;
3282 vsi->sib_vsi_list.vsi = vsi;
3283 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3284 &vsi->sib_vsi_list, list);
3287 /* MAC/VLAN configuration */
3288 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3289 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3291 ret = i40e_vsi_add_mac(vsi, &filter);
3292 if (ret != I40E_SUCCESS) {
3293 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3294 goto fail_msix_alloc;
3297 /* Get VSI BW information */
3298 i40e_vsi_dump_bw_config(vsi);
3301 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3303 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3309 /* Configure vlan stripping on or off */
3311 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3313 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3314 struct i40e_vsi_context ctxt;
3316 int ret = I40E_SUCCESS;
3318 /* Check if it has been already on or off */
3319 if (vsi->info.valid_sections &
3320 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3322 if ((vsi->info.port_vlan_flags &
3323 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3324 return 0; /* already on */
3326 if ((vsi->info.port_vlan_flags &
3327 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3328 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3329 return 0; /* already off */
3334 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3336 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3337 vsi->info.valid_sections =
3338 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3339 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3340 vsi->info.port_vlan_flags |= vlan_flags;
3341 ctxt.seid = vsi->seid;
3342 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3343 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3345 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3346 on ? "enable" : "disable");
3352 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3354 struct rte_eth_dev_data *data = dev->data;
3357 /* Apply vlan offload setting */
3358 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3360 /* Apply double-vlan setting, not implemented yet */
3362 /* Apply pvid setting */
3363 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3364 data->dev_conf.txmode.hw_vlan_insert_pvid);
3366 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3372 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3374 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3376 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3380 i40e_update_flow_control(struct i40e_hw *hw)
3382 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3383 struct i40e_link_status link_status;
3384 uint32_t rxfc = 0, txfc = 0, reg;
3388 memset(&link_status, 0, sizeof(link_status));
3389 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3390 if (ret != I40E_SUCCESS) {
3391 PMD_DRV_LOG(ERR, "Failed to get link status information");
3392 goto write_reg; /* Disable flow control */
3395 an_info = hw->phy.link_info.an_info;
3396 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3397 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3398 ret = I40E_ERR_NOT_READY;
3399 goto write_reg; /* Disable flow control */
3402 * If link auto negotiation is enabled, flow control needs to
3403 * be configured according to it
3405 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3406 case I40E_LINK_PAUSE_RXTX:
3409 hw->fc.current_mode = I40E_FC_FULL;
3411 case I40E_AQ_LINK_PAUSE_RX:
3413 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3415 case I40E_AQ_LINK_PAUSE_TX:
3417 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3420 hw->fc.current_mode = I40E_FC_NONE;
3425 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3426 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3427 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3428 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3429 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3430 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3437 i40e_pf_setup(struct i40e_pf *pf)
3439 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3440 struct i40e_filter_control_settings settings;
3441 struct i40e_vsi *vsi;
3444 /* Clear all stats counters */
3445 pf->offset_loaded = FALSE;
3446 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3447 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3449 ret = i40e_pf_get_switch_config(pf);
3450 if (ret != I40E_SUCCESS) {
3451 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3454 if (pf->flags & I40E_FLAG_FDIR) {
3455 /* make queue allocated first, let FDIR use queue pair 0*/
3456 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3457 if (ret != I40E_FDIR_QUEUE_ID) {
3458 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3460 pf->flags &= ~I40E_FLAG_FDIR;
3463 /* main VSI setup */
3464 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3466 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3467 return I40E_ERR_NOT_READY;
3471 /* Configure filter control */
3472 memset(&settings, 0, sizeof(settings));
3473 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3474 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3475 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3476 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3478 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3479 hw->func_caps.rss_table_size);
3480 return I40E_ERR_PARAM;
3482 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3483 "size: %u\n", hw->func_caps.rss_table_size);
3484 pf->hash_lut_size = hw->func_caps.rss_table_size;
3486 /* Enable ethtype and macvlan filters */
3487 settings.enable_ethtype = TRUE;
3488 settings.enable_macvlan = TRUE;
3489 ret = i40e_set_filter_control(hw, &settings);
3491 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3494 /* Update flow control according to the auto negotiation */
3495 i40e_update_flow_control(hw);
3497 return I40E_SUCCESS;
3501 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3507 * Set or clear TX Queue Disable flags,
3508 * which is required by hardware.
3510 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3511 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3513 /* Wait until the request is finished */
3514 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3515 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3516 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3517 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3518 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3524 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3525 return I40E_SUCCESS; /* already on, skip next steps */
3527 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3528 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3530 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3531 return I40E_SUCCESS; /* already off, skip next steps */
3532 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3534 /* Write the register */
3535 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3536 /* Check the result */
3537 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3538 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3539 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3541 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3542 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3545 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3546 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3550 /* Check if it is timeout */
3551 if (j >= I40E_CHK_Q_ENA_COUNT) {
3552 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3553 (on ? "enable" : "disable"), q_idx);
3554 return I40E_ERR_TIMEOUT;
3557 return I40E_SUCCESS;
3560 /* Swith on or off the tx queues */
3562 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3564 struct rte_eth_dev_data *dev_data = pf->dev_data;
3565 struct i40e_tx_queue *txq;
3566 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3570 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3571 txq = dev_data->tx_queues[i];
3572 /* Don't operate the queue if not configured or
3573 * if starting only per queue */
3574 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3577 ret = i40e_dev_tx_queue_start(dev, i);
3579 ret = i40e_dev_tx_queue_stop(dev, i);
3580 if ( ret != I40E_SUCCESS)
3584 return I40E_SUCCESS;
3588 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3593 /* Wait until the request is finished */
3594 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3595 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3596 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3597 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3598 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3603 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3604 return I40E_SUCCESS; /* Already on, skip next steps */
3605 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3607 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3608 return I40E_SUCCESS; /* Already off, skip next steps */
3609 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3612 /* Write the register */
3613 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3614 /* Check the result */
3615 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3616 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3617 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3619 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3620 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3623 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3624 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3629 /* Check if it is timeout */
3630 if (j >= I40E_CHK_Q_ENA_COUNT) {
3631 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3632 (on ? "enable" : "disable"), q_idx);
3633 return I40E_ERR_TIMEOUT;
3636 return I40E_SUCCESS;
3638 /* Switch on or off the rx queues */
3640 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3642 struct rte_eth_dev_data *dev_data = pf->dev_data;
3643 struct i40e_rx_queue *rxq;
3644 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3648 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3649 rxq = dev_data->rx_queues[i];
3650 /* Don't operate the queue if not configured or
3651 * if starting only per queue */
3652 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3655 ret = i40e_dev_rx_queue_start(dev, i);
3657 ret = i40e_dev_rx_queue_stop(dev, i);
3658 if (ret != I40E_SUCCESS)
3662 return I40E_SUCCESS;
3665 /* Switch on or off all the rx/tx queues */
3667 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3672 /* enable rx queues before enabling tx queues */
3673 ret = i40e_dev_switch_rx_queues(pf, on);
3675 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3678 ret = i40e_dev_switch_tx_queues(pf, on);
3680 /* Stop tx queues before stopping rx queues */
3681 ret = i40e_dev_switch_tx_queues(pf, on);
3683 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3686 ret = i40e_dev_switch_rx_queues(pf, on);
3692 /* Initialize VSI for TX */
3694 i40e_dev_tx_init(struct i40e_pf *pf)
3696 struct rte_eth_dev_data *data = pf->dev_data;
3698 uint32_t ret = I40E_SUCCESS;
3699 struct i40e_tx_queue *txq;
3701 for (i = 0; i < data->nb_tx_queues; i++) {
3702 txq = data->tx_queues[i];
3703 if (!txq || !txq->q_set)
3705 ret = i40e_tx_queue_init(txq);
3706 if (ret != I40E_SUCCESS)
3713 /* Initialize VSI for RX */
3715 i40e_dev_rx_init(struct i40e_pf *pf)
3717 struct rte_eth_dev_data *data = pf->dev_data;
3718 int ret = I40E_SUCCESS;
3720 struct i40e_rx_queue *rxq;
3722 i40e_pf_config_mq_rx(pf);
3723 for (i = 0; i < data->nb_rx_queues; i++) {
3724 rxq = data->rx_queues[i];
3725 if (!rxq || !rxq->q_set)
3728 ret = i40e_rx_queue_init(rxq);
3729 if (ret != I40E_SUCCESS) {
3730 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3740 i40e_dev_rxtx_init(struct i40e_pf *pf)
3744 err = i40e_dev_tx_init(pf);
3746 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3749 err = i40e_dev_rx_init(pf);
3751 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3759 i40e_vmdq_setup(struct rte_eth_dev *dev)
3761 struct rte_eth_conf *conf = &dev->data->dev_conf;
3762 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3763 int i, err, conf_vsis, j, loop;
3764 struct i40e_vsi *vsi;
3765 struct i40e_vmdq_info *vmdq_info;
3766 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3767 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3770 * Disable interrupt to avoid message from VF. Furthermore, it will
3771 * avoid race condition in VSI creation/destroy.
3773 i40e_pf_disable_irq0(hw);
3775 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3776 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3780 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3781 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3782 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3783 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3784 pf->max_nb_vmdq_vsi);
3788 if (pf->vmdq != NULL) {
3789 PMD_INIT_LOG(INFO, "VMDQ already configured");
3793 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3794 sizeof(*vmdq_info) * conf_vsis, 0);
3796 if (pf->vmdq == NULL) {
3797 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3801 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3803 /* Create VMDQ VSI */
3804 for (i = 0; i < conf_vsis; i++) {
3805 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3806 vmdq_conf->enable_loop_back);
3808 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3812 vmdq_info = &pf->vmdq[i];
3814 vmdq_info->vsi = vsi;
3816 pf->nb_cfg_vmdq_vsi = conf_vsis;
3818 /* Configure Vlan */
3819 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3820 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3821 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3822 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3823 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3824 vmdq_conf->pool_map[i].vlan_id, j);
3826 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3827 vmdq_conf->pool_map[i].vlan_id);
3829 PMD_INIT_LOG(ERR, "Failed to add vlan");
3837 i40e_pf_enable_irq0(hw);
3842 for (i = 0; i < conf_vsis; i++)
3843 if (pf->vmdq[i].vsi == NULL)
3846 i40e_vsi_release(pf->vmdq[i].vsi);
3850 i40e_pf_enable_irq0(hw);
3855 i40e_stat_update_32(struct i40e_hw *hw,
3863 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3867 if (new_data >= *offset)
3868 *stat = (uint64_t)(new_data - *offset);
3870 *stat = (uint64_t)((new_data +
3871 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3875 i40e_stat_update_48(struct i40e_hw *hw,
3884 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3885 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3886 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3891 if (new_data >= *offset)
3892 *stat = new_data - *offset;
3894 *stat = (uint64_t)((new_data +
3895 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3897 *stat &= I40E_48_BIT_MASK;
3902 i40e_pf_disable_irq0(struct i40e_hw *hw)
3904 /* Disable all interrupt types */
3905 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3906 I40E_WRITE_FLUSH(hw);
3911 i40e_pf_enable_irq0(struct i40e_hw *hw)
3913 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3914 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3915 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3916 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3917 I40E_WRITE_FLUSH(hw);
3921 i40e_pf_config_irq0(struct i40e_hw *hw)
3923 /* read pending request and disable first */
3924 i40e_pf_disable_irq0(hw);
3925 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3926 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3927 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3929 /* Link no queues with irq0 */
3930 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3931 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3935 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3941 uint32_t index, offset, val;
3946 * Try to find which VF trigger a reset, use absolute VF id to access
3947 * since the reg is global register.
3949 for (i = 0; i < pf->vf_num; i++) {
3950 abs_vf_id = hw->func_caps.vf_base_id + i;
3951 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3952 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3953 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3954 /* VFR event occured */
3955 if (val & (0x1 << offset)) {
3958 /* Clear the event first */
3959 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3961 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3963 * Only notify a VF reset event occured,
3964 * don't trigger another SW reset
3966 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3967 if (ret != I40E_SUCCESS)
3968 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3974 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3976 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3977 struct i40e_arq_event_info info;
3978 uint16_t pending, opcode;
3981 info.buf_len = I40E_AQ_BUF_SZ;
3982 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3983 if (!info.msg_buf) {
3984 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3990 ret = i40e_clean_arq_element(hw, &info, &pending);
3992 if (ret != I40E_SUCCESS) {
3993 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3994 "aq_err: %u", hw->aq.asq_last_status);
3997 opcode = rte_le_to_cpu_16(info.desc.opcode);
4000 case i40e_aqc_opc_send_msg_to_pf:
4001 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4002 i40e_pf_host_handle_vf_msg(dev,
4003 rte_le_to_cpu_16(info.desc.retval),
4004 rte_le_to_cpu_32(info.desc.cookie_high),
4005 rte_le_to_cpu_32(info.desc.cookie_low),
4010 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4015 rte_free(info.msg_buf);
4019 * Interrupt handler is registered as the alarm callback for handling LSC
4020 * interrupt in a definite of time, in order to wait the NIC into a stable
4021 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4022 * no need for link down interrupt.
4025 i40e_dev_interrupt_delayed_handler(void *param)
4027 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4028 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031 /* read interrupt causes again */
4032 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4034 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4035 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4036 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4037 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4038 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4039 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4040 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4041 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4042 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4043 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4044 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4046 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4047 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4048 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4049 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4050 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4052 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4053 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4054 i40e_dev_handle_vfr_event(dev);
4056 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4057 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4058 i40e_dev_handle_aq_msg(dev);
4061 /* handle the link up interrupt in an alarm callback */
4062 i40e_dev_link_update(dev, 0);
4063 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4065 i40e_pf_enable_irq0(hw);
4066 rte_intr_enable(&(dev->pci_dev->intr_handle));
4070 * Interrupt handler triggered by NIC for handling
4071 * specific interrupt.
4074 * Pointer to interrupt handle.
4076 * The address of parameter (struct rte_eth_dev *) regsitered before.
4082 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4085 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4086 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089 /* Disable interrupt */
4090 i40e_pf_disable_irq0(hw);
4092 /* read out interrupt causes */
4093 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4095 /* No interrupt event indicated */
4096 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4097 PMD_DRV_LOG(INFO, "No interrupt event");
4100 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4101 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4102 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4103 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4104 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4105 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4106 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4107 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4108 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4109 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4110 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4111 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4112 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4113 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4114 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4115 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4117 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4118 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4119 i40e_dev_handle_vfr_event(dev);
4121 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4122 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4123 i40e_dev_handle_aq_msg(dev);
4126 /* Link Status Change interrupt */
4127 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4128 #define I40E_US_PER_SECOND 1000000
4129 struct rte_eth_link link;
4131 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4132 memset(&link, 0, sizeof(link));
4133 rte_i40e_dev_atomic_read_link_status(dev, &link);
4134 i40e_dev_link_update(dev, 0);
4137 * For link up interrupt, it needs to wait 1 second to let the
4138 * hardware be a stable state. Otherwise several consecutive
4139 * interrupts can be observed.
4140 * For link down interrupt, no need to wait.
4142 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4143 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4146 _rte_eth_dev_callback_process(dev,
4147 RTE_ETH_EVENT_INTR_LSC);
4151 /* Enable interrupt */
4152 i40e_pf_enable_irq0(hw);
4153 rte_intr_enable(&(dev->pci_dev->intr_handle));
4157 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4158 struct i40e_macvlan_filter *filter,
4161 int ele_num, ele_buff_size;
4162 int num, actual_num, i;
4164 int ret = I40E_SUCCESS;
4165 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4166 struct i40e_aqc_add_macvlan_element_data *req_list;
4168 if (filter == NULL || total == 0)
4169 return I40E_ERR_PARAM;
4170 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4171 ele_buff_size = hw->aq.asq_buf_size;
4173 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4174 if (req_list == NULL) {
4175 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4176 return I40E_ERR_NO_MEMORY;
4181 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4182 memset(req_list, 0, ele_buff_size);
4184 for (i = 0; i < actual_num; i++) {
4185 (void)rte_memcpy(req_list[i].mac_addr,
4186 &filter[num + i].macaddr, ETH_ADDR_LEN);
4187 req_list[i].vlan_tag =
4188 rte_cpu_to_le_16(filter[num + i].vlan_id);
4190 switch (filter[num + i].filter_type) {
4191 case RTE_MAC_PERFECT_MATCH:
4192 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4193 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4195 case RTE_MACVLAN_PERFECT_MATCH:
4196 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4198 case RTE_MAC_HASH_MATCH:
4199 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4200 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4202 case RTE_MACVLAN_HASH_MATCH:
4203 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4206 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4207 ret = I40E_ERR_PARAM;
4211 req_list[i].queue_number = 0;
4213 req_list[i].flags = rte_cpu_to_le_16(flags);
4216 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4218 if (ret != I40E_SUCCESS) {
4219 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4223 } while (num < total);
4231 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4232 struct i40e_macvlan_filter *filter,
4235 int ele_num, ele_buff_size;
4236 int num, actual_num, i;
4238 int ret = I40E_SUCCESS;
4239 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4240 struct i40e_aqc_remove_macvlan_element_data *req_list;
4242 if (filter == NULL || total == 0)
4243 return I40E_ERR_PARAM;
4245 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4246 ele_buff_size = hw->aq.asq_buf_size;
4248 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4249 if (req_list == NULL) {
4250 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4251 return I40E_ERR_NO_MEMORY;
4256 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4257 memset(req_list, 0, ele_buff_size);
4259 for (i = 0; i < actual_num; i++) {
4260 (void)rte_memcpy(req_list[i].mac_addr,
4261 &filter[num + i].macaddr, ETH_ADDR_LEN);
4262 req_list[i].vlan_tag =
4263 rte_cpu_to_le_16(filter[num + i].vlan_id);
4265 switch (filter[num + i].filter_type) {
4266 case RTE_MAC_PERFECT_MATCH:
4267 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4268 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4270 case RTE_MACVLAN_PERFECT_MATCH:
4271 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4273 case RTE_MAC_HASH_MATCH:
4274 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4275 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4277 case RTE_MACVLAN_HASH_MATCH:
4278 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4281 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4282 ret = I40E_ERR_PARAM;
4285 req_list[i].flags = rte_cpu_to_le_16(flags);
4288 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4290 if (ret != I40E_SUCCESS) {
4291 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4295 } while (num < total);
4302 /* Find out specific MAC filter */
4303 static struct i40e_mac_filter *
4304 i40e_find_mac_filter(struct i40e_vsi *vsi,
4305 struct ether_addr *macaddr)
4307 struct i40e_mac_filter *f;
4309 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4310 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4318 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4321 uint32_t vid_idx, vid_bit;
4323 if (vlan_id > ETH_VLAN_ID_MAX)
4326 vid_idx = I40E_VFTA_IDX(vlan_id);
4327 vid_bit = I40E_VFTA_BIT(vlan_id);
4329 if (vsi->vfta[vid_idx] & vid_bit)
4336 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4337 uint16_t vlan_id, bool on)
4339 uint32_t vid_idx, vid_bit;
4341 if (vlan_id > ETH_VLAN_ID_MAX)
4344 vid_idx = I40E_VFTA_IDX(vlan_id);
4345 vid_bit = I40E_VFTA_BIT(vlan_id);
4348 vsi->vfta[vid_idx] |= vid_bit;
4350 vsi->vfta[vid_idx] &= ~vid_bit;
4354 * Find all vlan options for specific mac addr,
4355 * return with actual vlan found.
4358 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4359 struct i40e_macvlan_filter *mv_f,
4360 int num, struct ether_addr *addr)
4366 * Not to use i40e_find_vlan_filter to decrease the loop time,
4367 * although the code looks complex.
4369 if (num < vsi->vlan_num)
4370 return I40E_ERR_PARAM;
4373 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4375 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4376 if (vsi->vfta[j] & (1 << k)) {
4378 PMD_DRV_LOG(ERR, "vlan number "
4380 return I40E_ERR_PARAM;
4382 (void)rte_memcpy(&mv_f[i].macaddr,
4383 addr, ETH_ADDR_LEN);
4385 j * I40E_UINT32_BIT_SIZE + k;
4391 return I40E_SUCCESS;
4395 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4396 struct i40e_macvlan_filter *mv_f,
4401 struct i40e_mac_filter *f;
4403 if (num < vsi->mac_num)
4404 return I40E_ERR_PARAM;
4406 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4408 PMD_DRV_LOG(ERR, "buffer number not match");
4409 return I40E_ERR_PARAM;
4411 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4413 mv_f[i].vlan_id = vlan;
4414 mv_f[i].filter_type = f->mac_info.filter_type;
4418 return I40E_SUCCESS;
4422 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4425 struct i40e_mac_filter *f;
4426 struct i40e_macvlan_filter *mv_f;
4427 int ret = I40E_SUCCESS;
4429 if (vsi == NULL || vsi->mac_num == 0)
4430 return I40E_ERR_PARAM;
4432 /* Case that no vlan is set */
4433 if (vsi->vlan_num == 0)
4436 num = vsi->mac_num * vsi->vlan_num;
4438 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4440 PMD_DRV_LOG(ERR, "failed to allocate memory");
4441 return I40E_ERR_NO_MEMORY;
4445 if (vsi->vlan_num == 0) {
4446 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4447 (void)rte_memcpy(&mv_f[i].macaddr,
4448 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4449 mv_f[i].vlan_id = 0;
4453 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4454 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4455 vsi->vlan_num, &f->mac_info.mac_addr);
4456 if (ret != I40E_SUCCESS)
4462 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4470 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4472 struct i40e_macvlan_filter *mv_f;
4474 int ret = I40E_SUCCESS;
4476 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4477 return I40E_ERR_PARAM;
4479 /* If it's already set, just return */
4480 if (i40e_find_vlan_filter(vsi,vlan))
4481 return I40E_SUCCESS;
4483 mac_num = vsi->mac_num;
4486 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4487 return I40E_ERR_PARAM;
4490 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4493 PMD_DRV_LOG(ERR, "failed to allocate memory");
4494 return I40E_ERR_NO_MEMORY;
4497 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4499 if (ret != I40E_SUCCESS)
4502 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4504 if (ret != I40E_SUCCESS)
4507 i40e_set_vlan_filter(vsi, vlan, 1);
4517 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4519 struct i40e_macvlan_filter *mv_f;
4521 int ret = I40E_SUCCESS;
4524 * Vlan 0 is the generic filter for untagged packets
4525 * and can't be removed.
4527 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4528 return I40E_ERR_PARAM;
4530 /* If can't find it, just return */
4531 if (!i40e_find_vlan_filter(vsi, vlan))
4532 return I40E_ERR_PARAM;
4534 mac_num = vsi->mac_num;
4537 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4538 return I40E_ERR_PARAM;
4541 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4544 PMD_DRV_LOG(ERR, "failed to allocate memory");
4545 return I40E_ERR_NO_MEMORY;
4548 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4550 if (ret != I40E_SUCCESS)
4553 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4555 if (ret != I40E_SUCCESS)
4558 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4559 if (vsi->vlan_num == 1) {
4560 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4561 if (ret != I40E_SUCCESS)
4564 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4565 if (ret != I40E_SUCCESS)
4569 i40e_set_vlan_filter(vsi, vlan, 0);
4579 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4581 struct i40e_mac_filter *f;
4582 struct i40e_macvlan_filter *mv_f;
4583 int i, vlan_num = 0;
4584 int ret = I40E_SUCCESS;
4586 /* If it's add and we've config it, return */
4587 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4589 return I40E_SUCCESS;
4590 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4591 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4594 * If vlan_num is 0, that's the first time to add mac,
4595 * set mask for vlan_id 0.
4597 if (vsi->vlan_num == 0) {
4598 i40e_set_vlan_filter(vsi, 0, 1);
4601 vlan_num = vsi->vlan_num;
4602 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4603 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4606 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4608 PMD_DRV_LOG(ERR, "failed to allocate memory");
4609 return I40E_ERR_NO_MEMORY;
4612 for (i = 0; i < vlan_num; i++) {
4613 mv_f[i].filter_type = mac_filter->filter_type;
4614 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4618 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4619 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4620 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4621 &mac_filter->mac_addr);
4622 if (ret != I40E_SUCCESS)
4626 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4627 if (ret != I40E_SUCCESS)
4630 /* Add the mac addr into mac list */
4631 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4633 PMD_DRV_LOG(ERR, "failed to allocate memory");
4634 ret = I40E_ERR_NO_MEMORY;
4637 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4639 f->mac_info.filter_type = mac_filter->filter_type;
4640 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4651 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4653 struct i40e_mac_filter *f;
4654 struct i40e_macvlan_filter *mv_f;
4656 enum rte_mac_filter_type filter_type;
4657 int ret = I40E_SUCCESS;
4659 /* Can't find it, return an error */
4660 f = i40e_find_mac_filter(vsi, addr);
4662 return I40E_ERR_PARAM;
4664 vlan_num = vsi->vlan_num;
4665 filter_type = f->mac_info.filter_type;
4666 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4667 filter_type == RTE_MACVLAN_HASH_MATCH) {
4668 if (vlan_num == 0) {
4669 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4670 return I40E_ERR_PARAM;
4672 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4673 filter_type == RTE_MAC_HASH_MATCH)
4676 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4678 PMD_DRV_LOG(ERR, "failed to allocate memory");
4679 return I40E_ERR_NO_MEMORY;
4682 for (i = 0; i < vlan_num; i++) {
4683 mv_f[i].filter_type = filter_type;
4684 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4687 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4688 filter_type == RTE_MACVLAN_HASH_MATCH) {
4689 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4690 if (ret != I40E_SUCCESS)
4694 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4695 if (ret != I40E_SUCCESS)
4698 /* Remove the mac addr into mac list */
4699 TAILQ_REMOVE(&vsi->mac_list, f, next);
4709 /* Configure hash enable flags for RSS */
4711 i40e_config_hena(uint64_t flags)
4718 if (flags & ETH_RSS_FRAG_IPV4)
4719 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4720 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4721 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4722 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4723 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4724 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4725 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4726 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4727 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4728 if (flags & ETH_RSS_FRAG_IPV6)
4729 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4730 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4731 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4732 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4733 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4734 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4735 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4736 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4737 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4738 if (flags & ETH_RSS_L2_PAYLOAD)
4739 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4744 /* Parse the hash enable flags */
4746 i40e_parse_hena(uint64_t flags)
4748 uint64_t rss_hf = 0;
4752 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4753 rss_hf |= ETH_RSS_FRAG_IPV4;
4754 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4755 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4756 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4757 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4758 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4759 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4760 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4761 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4762 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4763 rss_hf |= ETH_RSS_FRAG_IPV6;
4764 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4765 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4766 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4767 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4768 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4769 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4770 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4771 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4772 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4773 rss_hf |= ETH_RSS_L2_PAYLOAD;
4780 i40e_pf_disable_rss(struct i40e_pf *pf)
4782 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4785 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4786 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4787 hena &= ~I40E_RSS_HENA_ALL;
4788 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4789 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4790 I40E_WRITE_FLUSH(hw);
4794 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4797 uint8_t hash_key_len;
4802 hash_key = (uint32_t *)(rss_conf->rss_key);
4803 hash_key_len = rss_conf->rss_key_len;
4804 if (hash_key != NULL && hash_key_len >=
4805 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4806 /* Fill in RSS hash key */
4807 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4808 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4811 rss_hf = rss_conf->rss_hf;
4812 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4813 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4814 hena &= ~I40E_RSS_HENA_ALL;
4815 hena |= i40e_config_hena(rss_hf);
4816 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4817 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4818 I40E_WRITE_FLUSH(hw);
4824 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4825 struct rte_eth_rss_conf *rss_conf)
4827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4831 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4832 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4833 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4834 if (rss_hf != 0) /* Enable RSS */
4836 return 0; /* Nothing to do */
4839 if (rss_hf == 0) /* Disable RSS */
4842 return i40e_hw_rss_hash_set(hw, rss_conf);
4846 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4847 struct rte_eth_rss_conf *rss_conf)
4849 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4854 if (hash_key != NULL) {
4855 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4856 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4857 rss_conf->rss_key_len = i * sizeof(uint32_t);
4859 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4860 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4861 rss_conf->rss_hf = i40e_parse_hena(hena);
4867 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4869 switch (filter_type) {
4870 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4871 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4873 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4874 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4876 case RTE_TUNNEL_FILTER_IMAC_TENID:
4877 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4879 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4880 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4882 case ETH_TUNNEL_FILTER_IMAC:
4883 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4886 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4894 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4895 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4899 uint8_t tun_type = 0;
4901 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4902 struct i40e_vsi *vsi = pf->main_vsi;
4903 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4904 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4906 cld_filter = rte_zmalloc("tunnel_filter",
4907 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4910 if (NULL == cld_filter) {
4911 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4914 pfilter = cld_filter;
4916 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4917 sizeof(struct ether_addr));
4918 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4919 sizeof(struct ether_addr));
4921 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4922 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4923 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4924 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4925 &tunnel_filter->ip_addr,
4926 sizeof(pfilter->ipaddr.v4.data));
4928 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4929 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4930 &tunnel_filter->ip_addr,
4931 sizeof(pfilter->ipaddr.v6.data));
4934 /* check tunneled type */
4935 switch (tunnel_filter->tunnel_type) {
4936 case RTE_TUNNEL_TYPE_VXLAN:
4937 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4939 case RTE_TUNNEL_TYPE_NVGRE:
4940 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4943 /* Other tunnel types is not supported. */
4944 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4945 rte_free(cld_filter);
4949 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4952 rte_free(cld_filter);
4956 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4957 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4958 pfilter->tenant_id = tunnel_filter->tenant_id;
4959 pfilter->queue_number = tunnel_filter->queue_id;
4962 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4964 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4967 rte_free(cld_filter);
4972 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4976 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4977 if (pf->vxlan_ports[i] == port)
4985 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4989 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4991 idx = i40e_get_vxlan_port_idx(pf, port);
4993 /* Check if port already exists */
4995 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4999 /* Now check if there is space to add the new port */
5000 idx = i40e_get_vxlan_port_idx(pf, 0);
5002 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5003 "not adding port %d", port);
5007 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5010 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5014 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5017 /* New port: add it and mark its index in the bitmap */
5018 pf->vxlan_ports[idx] = port;
5019 pf->vxlan_bitmap |= (1 << idx);
5021 if (!(pf->flags & I40E_FLAG_VXLAN))
5022 pf->flags |= I40E_FLAG_VXLAN;
5028 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5031 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5033 if (!(pf->flags & I40E_FLAG_VXLAN)) {
5034 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5038 idx = i40e_get_vxlan_port_idx(pf, port);
5041 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5045 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5046 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5050 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5053 pf->vxlan_ports[idx] = 0;
5054 pf->vxlan_bitmap &= ~(1 << idx);
5056 if (!pf->vxlan_bitmap)
5057 pf->flags &= ~I40E_FLAG_VXLAN;
5062 /* Add UDP tunneling port */
5064 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5065 struct rte_eth_udp_tunnel *udp_tunnel)
5068 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5070 if (udp_tunnel == NULL)
5073 switch (udp_tunnel->prot_type) {
5074 case RTE_TUNNEL_TYPE_VXLAN:
5075 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5078 case RTE_TUNNEL_TYPE_GENEVE:
5079 case RTE_TUNNEL_TYPE_TEREDO:
5080 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5085 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5093 /* Remove UDP tunneling port */
5095 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5096 struct rte_eth_udp_tunnel *udp_tunnel)
5099 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5101 if (udp_tunnel == NULL)
5104 switch (udp_tunnel->prot_type) {
5105 case RTE_TUNNEL_TYPE_VXLAN:
5106 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5108 case RTE_TUNNEL_TYPE_GENEVE:
5109 case RTE_TUNNEL_TYPE_TEREDO:
5110 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5114 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5122 /* Calculate the maximum number of contiguous PF queues that are configured */
5124 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5126 struct rte_eth_dev_data *data = pf->dev_data;
5128 struct i40e_rx_queue *rxq;
5131 for (i = 0; i < pf->lan_nb_qps; i++) {
5132 rxq = data->rx_queues[i];
5133 if (rxq && rxq->q_set)
5144 i40e_pf_config_rss(struct i40e_pf *pf)
5146 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5147 struct rte_eth_rss_conf rss_conf;
5148 uint32_t i, lut = 0;
5152 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5153 * It's necessary to calulate the actual PF queues that are configured.
5155 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5156 num = i40e_pf_calc_configured_queues_num(pf);
5157 num = i40e_align_floor(num);
5159 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5161 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5165 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5169 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5172 lut = (lut << 8) | (j & ((0x1 <<
5173 hw->func_caps.rss_table_entry_width) - 1));
5175 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5178 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5179 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5180 i40e_pf_disable_rss(pf);
5183 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5184 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5185 /* Random default keys */
5186 static uint32_t rss_key_default[] = {0x6b793944,
5187 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5188 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5189 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5191 rss_conf.rss_key = (uint8_t *)rss_key_default;
5192 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5196 return i40e_hw_rss_hash_set(hw, &rss_conf);
5200 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5201 struct rte_eth_tunnel_filter_conf *filter)
5203 if (pf == NULL || filter == NULL) {
5204 PMD_DRV_LOG(ERR, "Invalid parameter");
5208 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5209 PMD_DRV_LOG(ERR, "Invalid queue ID");
5213 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5214 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5218 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5219 (is_zero_ether_addr(filter->outer_mac))) {
5220 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5224 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5225 (is_zero_ether_addr(filter->inner_mac))) {
5226 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5234 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5237 struct rte_eth_tunnel_filter_conf *filter;
5238 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5239 int ret = I40E_SUCCESS;
5241 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5243 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5244 return I40E_ERR_PARAM;
5246 switch (filter_op) {
5247 case RTE_ETH_FILTER_NOP:
5248 if (!(pf->flags & I40E_FLAG_VXLAN))
5249 ret = I40E_NOT_SUPPORTED;
5250 case RTE_ETH_FILTER_ADD:
5251 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5253 case RTE_ETH_FILTER_DELETE:
5254 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5257 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5258 ret = I40E_ERR_PARAM;
5266 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5269 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5271 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5272 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5277 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5278 ret = i40e_pf_config_rss(pf);
5280 i40e_pf_disable_rss(pf);
5285 /* Get the symmetric hash enable configurations per port */
5287 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5289 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5291 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5294 /* Set the symmetric hash enable configurations per port */
5296 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5298 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5301 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5302 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5306 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5308 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5309 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5313 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5315 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5316 I40E_WRITE_FLUSH(hw);
5320 * Get global configurations of hash function type and symmetric hash enable
5321 * per flow type (pctype). Note that global configuration means it affects all
5322 * the ports on the same NIC.
5325 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5326 struct rte_eth_hash_global_conf *g_cfg)
5328 uint32_t reg, mask = I40E_FLOW_TYPES;
5330 enum i40e_filter_pctype pctype;
5332 memset(g_cfg, 0, sizeof(*g_cfg));
5333 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5334 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5335 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5337 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5338 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5339 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5341 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5342 if (!(mask & (1UL << i)))
5344 mask &= ~(1UL << i);
5345 /* Bit set indicats the coresponding flow type is supported */
5346 g_cfg->valid_bit_mask[0] |= (1UL << i);
5347 pctype = i40e_flowtype_to_pctype(i);
5348 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5349 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5350 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5357 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5360 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5362 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5363 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5364 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5365 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5371 * As i40e supports less than 32 flow types, only first 32 bits need to
5374 mask0 = g_cfg->valid_bit_mask[0];
5375 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5377 /* Check if any unsupported flow type configured */
5378 if ((mask0 | i40e_mask) ^ i40e_mask)
5381 if (g_cfg->valid_bit_mask[i])
5389 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5395 * Set global configurations of hash function type and symmetric hash enable
5396 * per flow type (pctype). Note any modifying global configuration will affect
5397 * all the ports on the same NIC.
5400 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5401 struct rte_eth_hash_global_conf *g_cfg)
5406 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5407 enum i40e_filter_pctype pctype;
5409 /* Check the input parameters */
5410 ret = i40e_hash_global_config_check(g_cfg);
5414 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5415 if (!(mask0 & (1UL << i)))
5417 mask0 &= ~(1UL << i);
5418 pctype = i40e_flowtype_to_pctype(i);
5419 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5420 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5421 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5424 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5425 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5427 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5428 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5432 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5433 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5435 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5436 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5440 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5442 /* Use the default, and keep it as it is */
5445 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5448 I40E_WRITE_FLUSH(hw);
5454 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5459 PMD_DRV_LOG(ERR, "Invalid pointer");
5463 switch (info->info_type) {
5464 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5465 i40e_get_symmetric_hash_enable_per_port(hw,
5466 &(info->info.enable));
5468 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5469 ret = i40e_get_hash_filter_global_config(hw,
5470 &(info->info.global_conf));
5473 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5483 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5488 PMD_DRV_LOG(ERR, "Invalid pointer");
5492 switch (info->info_type) {
5493 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5494 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5496 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5497 ret = i40e_set_hash_filter_global_config(hw,
5498 &(info->info.global_conf));
5501 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5510 /* Operations for hash function */
5512 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5513 enum rte_filter_op filter_op,
5516 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5519 switch (filter_op) {
5520 case RTE_ETH_FILTER_NOP:
5522 case RTE_ETH_FILTER_GET:
5523 ret = i40e_hash_filter_get(hw,
5524 (struct rte_eth_hash_filter_info *)arg);
5526 case RTE_ETH_FILTER_SET:
5527 ret = i40e_hash_filter_set(hw,
5528 (struct rte_eth_hash_filter_info *)arg);
5531 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5541 * Configure ethertype filter, which can director packet by filtering
5542 * with mac address and ether_type or only ether_type
5545 i40e_ethertype_filter_set(struct i40e_pf *pf,
5546 struct rte_eth_ethertype_filter *filter,
5549 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5550 struct i40e_control_filter_stats stats;
5554 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5555 PMD_DRV_LOG(ERR, "Invalid queue ID");
5558 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5559 filter->ether_type == ETHER_TYPE_IPv6) {
5560 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5561 " control packet filter.", filter->ether_type);
5564 if (filter->ether_type == ETHER_TYPE_VLAN)
5565 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5568 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5569 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5570 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5571 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5572 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5574 memset(&stats, 0, sizeof(stats));
5575 ret = i40e_aq_add_rem_control_packet_filter(hw,
5576 filter->mac_addr.addr_bytes,
5577 filter->ether_type, flags,
5579 filter->queue, add, &stats, NULL);
5581 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5582 " mac_etype_used = %u, etype_used = %u,"
5583 " mac_etype_free = %u, etype_free = %u\n",
5584 ret, stats.mac_etype_used, stats.etype_used,
5585 stats.mac_etype_free, stats.etype_free);
5592 * Handle operations for ethertype filter.
5595 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5596 enum rte_filter_op filter_op,
5599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5602 if (filter_op == RTE_ETH_FILTER_NOP)
5606 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5611 switch (filter_op) {
5612 case RTE_ETH_FILTER_ADD:
5613 ret = i40e_ethertype_filter_set(pf,
5614 (struct rte_eth_ethertype_filter *)arg,
5617 case RTE_ETH_FILTER_DELETE:
5618 ret = i40e_ethertype_filter_set(pf,
5619 (struct rte_eth_ethertype_filter *)arg,
5623 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5631 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5632 enum rte_filter_type filter_type,
5633 enum rte_filter_op filter_op,
5641 switch (filter_type) {
5642 case RTE_ETH_FILTER_HASH:
5643 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5645 case RTE_ETH_FILTER_MACVLAN:
5646 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5648 case RTE_ETH_FILTER_ETHERTYPE:
5649 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5651 case RTE_ETH_FILTER_TUNNEL:
5652 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5654 case RTE_ETH_FILTER_FDIR:
5655 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5658 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5668 * As some registers wouldn't be reset unless a global hardware reset,
5669 * hardware initialization is needed to put those registers into an
5670 * expected initial state.
5673 i40e_hw_init(struct i40e_hw *hw)
5675 /* clear the PF Queue Filter control register */
5676 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5678 /* Disable symmetric hash per port */
5679 i40e_set_symmetric_hash_enable_per_port(hw, 0);
5682 enum i40e_filter_pctype
5683 i40e_flowtype_to_pctype(uint16_t flow_type)
5685 static const enum i40e_filter_pctype pctype_table[] = {
5686 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5687 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5688 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5689 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5690 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5691 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5692 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5693 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5694 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5695 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5696 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5697 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5698 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5699 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5700 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5701 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5702 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5703 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5704 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5707 return pctype_table[flow_type];
5711 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5713 static const uint16_t flowtype_table[] = {
5714 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5715 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5716 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5717 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5718 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5719 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5720 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5721 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5722 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5723 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5724 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5725 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5726 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5727 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5728 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5729 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5730 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5731 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5732 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5735 return flowtype_table[pctype];
5739 * On X710, performance number is far from the expectation on recent firmware
5740 * versions; on XL710, performance number is also far from the expectation on
5741 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5742 * mode is enabled and port MAC address is equal to the packet destination MAC
5743 * address. The fix for this issue may not be integrated in the following
5744 * firmware version. So the workaround in software driver is needed. It needs
5745 * to modify the initial values of 3 internal only registers for both X710 and
5746 * XL710. Note that the values for X710 or XL710 could be different, and the
5747 * workaround can be removed when it is fixed in firmware in the future.
5750 /* For both X710 and XL710 */
5751 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5752 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
5754 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5755 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
5758 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
5760 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
5761 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
5764 i40e_configure_registers(struct i40e_hw *hw)
5770 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5771 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5772 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5778 for (i = 0; i < RTE_DIM(reg_table); i++) {
5779 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5780 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5782 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5785 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5788 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5791 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5795 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5796 reg_table[i].addr, reg);
5797 if (reg == reg_table[i].val)
5800 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5801 reg_table[i].val, NULL);
5803 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5804 "address of 0x%"PRIx32, reg_table[i].val,
5808 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5809 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5813 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
5814 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
5815 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
5816 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5818 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5823 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5824 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5828 /* Configure for double VLAN RX stripping */
5829 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5830 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5831 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5832 ret = i40e_aq_debug_write_register(hw,
5833 I40E_VSI_TSR(vsi->vsi_id),
5836 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5838 return I40E_ERR_CONFIG;
5842 /* Configure for double VLAN TX insertion */
5843 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5844 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5845 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5846 ret = i40e_aq_debug_write_register(hw,
5847 I40E_VSI_L2TAGSTXVALID(
5848 vsi->vsi_id), reg, NULL);
5850 PMD_DRV_LOG(ERR, "Failed to update "
5851 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5852 return I40E_ERR_CONFIG;
5860 * i40e_aq_add_mirror_rule
5861 * @hw: pointer to the hardware structure
5862 * @seid: VEB seid to add mirror rule to
5863 * @dst_id: destination vsi seid
5864 * @entries: Buffer which contains the entities to be mirrored
5865 * @count: number of entities contained in the buffer
5866 * @rule_id:the rule_id of the rule to be added
5868 * Add a mirror rule for a given veb.
5871 static enum i40e_status_code
5872 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5873 uint16_t seid, uint16_t dst_id,
5874 uint16_t rule_type, uint16_t *entries,
5875 uint16_t count, uint16_t *rule_id)
5877 struct i40e_aq_desc desc;
5878 struct i40e_aqc_add_delete_mirror_rule cmd;
5879 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5880 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5883 enum i40e_status_code status;
5885 i40e_fill_default_direct_cmd_desc(&desc,
5886 i40e_aqc_opc_add_mirror_rule);
5887 memset(&cmd, 0, sizeof(cmd));
5889 buff_len = sizeof(uint16_t) * count;
5890 desc.datalen = rte_cpu_to_le_16(buff_len);
5892 desc.flags |= rte_cpu_to_le_16(
5893 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5894 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5895 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5896 cmd.num_entries = rte_cpu_to_le_16(count);
5897 cmd.seid = rte_cpu_to_le_16(seid);
5898 cmd.destination = rte_cpu_to_le_16(dst_id);
5900 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5901 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5902 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5904 " mirror_rules_used = %u, mirror_rules_free = %u,",
5905 hw->aq.asq_last_status, resp->rule_id,
5906 resp->mirror_rules_used, resp->mirror_rules_free);
5907 *rule_id = rte_le_to_cpu_16(resp->rule_id);
5913 * i40e_aq_del_mirror_rule
5914 * @hw: pointer to the hardware structure
5915 * @seid: VEB seid to add mirror rule to
5916 * @entries: Buffer which contains the entities to be mirrored
5917 * @count: number of entities contained in the buffer
5918 * @rule_id:the rule_id of the rule to be delete
5920 * Delete a mirror rule for a given veb.
5923 static enum i40e_status_code
5924 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5925 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5926 uint16_t count, uint16_t rule_id)
5928 struct i40e_aq_desc desc;
5929 struct i40e_aqc_add_delete_mirror_rule cmd;
5930 uint16_t buff_len = 0;
5931 enum i40e_status_code status;
5934 i40e_fill_default_direct_cmd_desc(&desc,
5935 i40e_aqc_opc_delete_mirror_rule);
5936 memset(&cmd, 0, sizeof(cmd));
5937 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5938 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5940 cmd.num_entries = count;
5941 buff_len = sizeof(uint16_t) * count;
5942 desc.datalen = rte_cpu_to_le_16(buff_len);
5943 buff = (void *)entries;
5945 /* rule id is filled in destination field for deleting mirror rule */
5946 cmd.destination = rte_cpu_to_le_16(rule_id);
5948 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5949 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5950 cmd.seid = rte_cpu_to_le_16(seid);
5952 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5953 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5959 * i40e_mirror_rule_set
5960 * @dev: pointer to the hardware structure
5961 * @mirror_conf: mirror rule info
5962 * @sw_id: mirror rule's sw_id
5963 * @on: enable/disable
5965 * set a mirror rule.
5969 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5970 struct rte_eth_mirror_conf *mirror_conf,
5971 uint8_t sw_id, uint8_t on)
5973 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5975 struct i40e_mirror_rule *it, *mirr_rule = NULL;
5976 struct i40e_mirror_rule *parent = NULL;
5977 uint16_t seid, dst_seid, rule_id;
5981 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5983 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5984 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5985 " without veb or vfs.");
5988 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5989 PMD_DRV_LOG(ERR, "mirror table is full.");
5992 if (mirror_conf->dst_pool > pf->vf_num) {
5993 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
5994 mirror_conf->dst_pool);
5998 seid = pf->main_vsi->veb->seid;
6000 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6001 if (sw_id <= it->index) {
6007 if (mirr_rule && sw_id == mirr_rule->index) {
6009 PMD_DRV_LOG(ERR, "mirror rule exists.");
6012 ret = i40e_aq_del_mirror_rule(hw, seid,
6013 mirr_rule->rule_type,
6015 mirr_rule->num_entries, mirr_rule->id);
6017 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6018 " ret = %d, aq_err = %d.",
6019 ret, hw->aq.asq_last_status);
6022 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6023 rte_free(mirr_rule);
6024 pf->nb_mirror_rule--;
6028 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6032 mirr_rule = rte_zmalloc("i40e_mirror_rule",
6033 sizeof(struct i40e_mirror_rule) , 0);
6035 PMD_DRV_LOG(ERR, "failed to allocate memory");
6036 return I40E_ERR_NO_MEMORY;
6038 switch (mirror_conf->rule_type) {
6039 case ETH_MIRROR_VLAN:
6040 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6041 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6042 mirr_rule->entries[j] =
6043 mirror_conf->vlan.vlan_id[i];
6048 PMD_DRV_LOG(ERR, "vlan is not specified.");
6049 rte_free(mirr_rule);
6052 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6054 case ETH_MIRROR_VIRTUAL_POOL_UP:
6055 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6056 /* check if the specified pool bit is out of range */
6057 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6058 PMD_DRV_LOG(ERR, "pool mask is out of range.");
6059 rte_free(mirr_rule);
6062 for (i = 0, j = 0; i < pf->vf_num; i++) {
6063 if (mirror_conf->pool_mask & (1ULL << i)) {
6064 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6068 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6069 /* add pf vsi to entries */
6070 mirr_rule->entries[j] = pf->main_vsi_seid;
6074 PMD_DRV_LOG(ERR, "pool is not specified.");
6075 rte_free(mirr_rule);
6078 /* egress and ingress in aq commands means from switch but not port */
6079 mirr_rule->rule_type =
6080 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6081 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6082 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6084 case ETH_MIRROR_UPLINK_PORT:
6085 /* egress and ingress in aq commands means from switch but not port*/
6086 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6088 case ETH_MIRROR_DOWNLINK_PORT:
6089 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6092 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6093 mirror_conf->rule_type);
6094 rte_free(mirr_rule);
6098 /* If the dst_pool is equal to vf_num, consider it as PF */
6099 if (mirror_conf->dst_pool == pf->vf_num)
6100 dst_seid = pf->main_vsi_seid;
6102 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6104 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6105 mirr_rule->rule_type, mirr_rule->entries,
6108 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6109 " ret = %d, aq_err = %d.",
6110 ret, hw->aq.asq_last_status);
6111 rte_free(mirr_rule);
6115 mirr_rule->index = sw_id;
6116 mirr_rule->num_entries = j;
6117 mirr_rule->id = rule_id;
6118 mirr_rule->dst_vsi_seid = dst_seid;
6121 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6123 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6125 pf->nb_mirror_rule++;
6130 * i40e_mirror_rule_reset
6131 * @dev: pointer to the device
6132 * @sw_id: mirror rule's sw_id
6134 * reset a mirror rule.
6138 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6140 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6141 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6142 struct i40e_mirror_rule *it, *mirr_rule = NULL;
6146 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6148 seid = pf->main_vsi->veb->seid;
6150 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6151 if (sw_id == it->index) {
6157 ret = i40e_aq_del_mirror_rule(hw, seid,
6158 mirr_rule->rule_type,
6160 mirr_rule->num_entries, mirr_rule->id);
6162 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6163 " status = %d, aq_err = %d.",
6164 ret, hw->aq.asq_last_status);
6167 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6168 rte_free(mirr_rule);
6169 pf->nb_mirror_rule--;
6171 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6178 i40e_timesync_enable(struct rte_eth_dev *dev)
6180 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6181 struct rte_eth_link *link = &dev->data->dev_link;
6182 uint32_t tsync_ctl_l;
6183 uint32_t tsync_ctl_h;
6184 uint32_t tsync_inc_l;
6185 uint32_t tsync_inc_h;
6187 switch (link->link_speed) {
6188 case ETH_LINK_SPEED_40G:
6189 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6190 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6192 case ETH_LINK_SPEED_10G:
6193 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6194 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6196 case ETH_LINK_SPEED_1000:
6197 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6198 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6205 /* Clear timesync registers. */
6206 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6207 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6208 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6209 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6210 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6211 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6212 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6214 /* Set the timesync increment value. */
6215 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6216 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6218 /* Enable timestamping of PTP packets. */
6219 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6220 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6222 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6223 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6224 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6226 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6227 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6233 i40e_timesync_disable(struct rte_eth_dev *dev)
6235 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6236 uint32_t tsync_ctl_l;
6237 uint32_t tsync_ctl_h;
6239 /* Disable timestamping of transmitted PTP packets. */
6240 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6241 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6243 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6244 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6246 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6247 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6249 /* Set the timesync increment value. */
6250 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6251 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6257 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6258 struct timespec *timestamp, uint32_t flags)
6260 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6261 uint32_t sync_status;
6264 uint32_t index = flags & 0x03;
6266 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6267 if ((sync_status & (1 << index)) == 0)
6270 rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6271 rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6273 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6274 timestamp->tv_nsec = 0;
6280 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6281 struct timespec *timestamp)
6283 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6284 uint32_t sync_status;
6288 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6289 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6292 tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6293 tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6295 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6296 timestamp->tv_nsec = 0;