4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Flow control default high water */
99 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
101 /* Flow control default low water */
102 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static int i40e_dev_reset(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
261 struct rte_eth_stats *stats);
262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
263 struct rte_eth_xstat *xstats, unsigned n);
264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
265 struct rte_eth_xstat_name *xstats_names,
267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
273 char *fw_version, size_t fw_size);
274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
275 struct rte_eth_dev_info *dev_info);
276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
280 enum rte_vlan_type vlan_type,
282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_fc_conf *fc_conf);
293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
294 struct rte_eth_pfc_conf *pfc_conf);
295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
296 struct ether_addr *mac_addr,
299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
301 struct rte_eth_rss_reta_entry64 *reta_conf,
303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
304 struct rte_eth_rss_reta_entry64 *reta_conf,
307 static int i40e_get_cap(struct i40e_hw *hw);
308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
309 static int i40e_pf_setup(struct i40e_pf *pf);
310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
315 bool offset_loaded, uint64_t *offset, uint64_t *stat);
316 static void i40e_stat_update_48(struct i40e_hw *hw,
322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
323 static void i40e_dev_interrupt_handler(void *param);
324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
325 uint32_t base, uint32_t num);
326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
332 static int i40e_veb_release(struct i40e_veb *veb);
333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
334 struct i40e_vsi *vsi);
335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
338 struct i40e_macvlan_filter *mv_f,
341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
343 struct rte_eth_rss_conf *rss_conf);
344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
345 struct rte_eth_rss_conf *rss_conf);
346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
347 struct rte_eth_udp_tunnel *udp_tunnel);
348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
349 struct rte_eth_udp_tunnel *udp_tunnel);
350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
352 enum rte_filter_op filter_op,
354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
355 enum rte_filter_type filter_type,
356 enum rte_filter_op filter_op,
358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
359 struct rte_eth_dcb_info *dcb_info);
360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
361 static void i40e_configure_registers(struct i40e_hw *hw);
362 static void i40e_hw_init(struct rte_eth_dev *dev);
363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
364 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
370 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
371 struct rte_eth_mirror_conf *mirror_conf,
372 uint8_t sw_id, uint8_t on);
373 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
375 static int i40e_timesync_enable(struct rte_eth_dev *dev);
376 static int i40e_timesync_disable(struct rte_eth_dev *dev);
377 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp,
380 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
381 struct timespec *timestamp);
382 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
384 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
386 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
387 struct timespec *timestamp);
388 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
389 const struct timespec *timestamp);
391 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
393 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
396 static int i40e_get_regs(struct rte_eth_dev *dev,
397 struct rte_dev_reg_info *regs);
399 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
401 static int i40e_get_eeprom(struct rte_eth_dev *dev,
402 struct rte_dev_eeprom_info *eeprom);
404 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
405 struct ether_addr *mac_addr);
407 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
409 static int i40e_ethertype_filter_convert(
410 const struct rte_eth_ethertype_filter *input,
411 struct i40e_ethertype_filter *filter);
412 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
413 struct i40e_ethertype_filter *filter);
415 static int i40e_tunnel_filter_convert(
416 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
417 struct i40e_tunnel_filter *tunnel_filter);
418 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
419 struct i40e_tunnel_filter *tunnel_filter);
420 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
422 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
423 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
424 static void i40e_filter_restore(struct i40e_pf *pf);
425 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
427 int i40e_logtype_init;
428 int i40e_logtype_driver;
430 static const struct rte_pci_id pci_id_i40e_map[] = {
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
451 { .vendor_id = 0, /* sentinel */ },
454 static const struct eth_dev_ops i40e_eth_dev_ops = {
455 .dev_configure = i40e_dev_configure,
456 .dev_start = i40e_dev_start,
457 .dev_stop = i40e_dev_stop,
458 .dev_close = i40e_dev_close,
459 .dev_reset = i40e_dev_reset,
460 .promiscuous_enable = i40e_dev_promiscuous_enable,
461 .promiscuous_disable = i40e_dev_promiscuous_disable,
462 .allmulticast_enable = i40e_dev_allmulticast_enable,
463 .allmulticast_disable = i40e_dev_allmulticast_disable,
464 .dev_set_link_up = i40e_dev_set_link_up,
465 .dev_set_link_down = i40e_dev_set_link_down,
466 .link_update = i40e_dev_link_update,
467 .stats_get = i40e_dev_stats_get,
468 .xstats_get = i40e_dev_xstats_get,
469 .xstats_get_names = i40e_dev_xstats_get_names,
470 .stats_reset = i40e_dev_stats_reset,
471 .xstats_reset = i40e_dev_stats_reset,
472 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
473 .fw_version_get = i40e_fw_version_get,
474 .dev_infos_get = i40e_dev_info_get,
475 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
476 .vlan_filter_set = i40e_vlan_filter_set,
477 .vlan_tpid_set = i40e_vlan_tpid_set,
478 .vlan_offload_set = i40e_vlan_offload_set,
479 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
480 .vlan_pvid_set = i40e_vlan_pvid_set,
481 .rx_queue_start = i40e_dev_rx_queue_start,
482 .rx_queue_stop = i40e_dev_rx_queue_stop,
483 .tx_queue_start = i40e_dev_tx_queue_start,
484 .tx_queue_stop = i40e_dev_tx_queue_stop,
485 .rx_queue_setup = i40e_dev_rx_queue_setup,
486 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
487 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
488 .rx_queue_release = i40e_dev_rx_queue_release,
489 .rx_queue_count = i40e_dev_rx_queue_count,
490 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
491 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
492 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
493 .tx_queue_setup = i40e_dev_tx_queue_setup,
494 .tx_queue_release = i40e_dev_tx_queue_release,
495 .dev_led_on = i40e_dev_led_on,
496 .dev_led_off = i40e_dev_led_off,
497 .flow_ctrl_get = i40e_flow_ctrl_get,
498 .flow_ctrl_set = i40e_flow_ctrl_set,
499 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
500 .mac_addr_add = i40e_macaddr_add,
501 .mac_addr_remove = i40e_macaddr_remove,
502 .reta_update = i40e_dev_rss_reta_update,
503 .reta_query = i40e_dev_rss_reta_query,
504 .rss_hash_update = i40e_dev_rss_hash_update,
505 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
506 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
507 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
508 .filter_ctrl = i40e_dev_filter_ctrl,
509 .rxq_info_get = i40e_rxq_info_get,
510 .txq_info_get = i40e_txq_info_get,
511 .mirror_rule_set = i40e_mirror_rule_set,
512 .mirror_rule_reset = i40e_mirror_rule_reset,
513 .timesync_enable = i40e_timesync_enable,
514 .timesync_disable = i40e_timesync_disable,
515 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
516 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
517 .get_dcb_info = i40e_dev_get_dcb_info,
518 .timesync_adjust_time = i40e_timesync_adjust_time,
519 .timesync_read_time = i40e_timesync_read_time,
520 .timesync_write_time = i40e_timesync_write_time,
521 .get_reg = i40e_get_regs,
522 .get_eeprom_length = i40e_get_eeprom_length,
523 .get_eeprom = i40e_get_eeprom,
524 .mac_addr_set = i40e_set_default_mac_addr,
525 .mtu_set = i40e_dev_mtu_set,
526 .tm_ops_get = i40e_tm_ops_get,
529 /* store statistics names and its offset in stats structure */
530 struct rte_i40e_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
536 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
537 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
538 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
539 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
540 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
541 rx_unknown_protocol)},
542 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
543 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
544 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
545 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
548 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
549 sizeof(rte_i40e_stats_strings[0]))
551 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
552 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
553 tx_dropped_link_down)},
554 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
555 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
557 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
558 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
560 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
562 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
564 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
565 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
566 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
567 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
568 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
569 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
586 mac_short_packet_dropped)},
587 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
590 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
591 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_flow_director_atr_match_packets",
604 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
605 {"rx_flow_director_sb_match_packets",
606 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
607 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
611 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
618 sizeof(rte_i40e_hw_port_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
627 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
628 sizeof(rte_i40e_rxq_prio_strings[0]))
630 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
631 {"xon_packets", offsetof(struct i40e_hw_port_stats,
633 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
635 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
636 priority_xon_2_xoff)},
639 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
640 sizeof(rte_i40e_txq_prio_strings[0]))
642 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
643 struct rte_pci_device *pci_dev)
645 return rte_eth_dev_pci_generic_probe(pci_dev,
646 sizeof(struct i40e_adapter), eth_i40e_dev_init);
649 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
651 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
654 static struct rte_pci_driver rte_i40e_pmd = {
655 .id_table = pci_id_i40e_map,
656 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
657 .probe = eth_i40e_pci_probe,
658 .remove = eth_i40e_pci_remove,
662 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
663 struct rte_eth_link *link)
665 struct rte_eth_link *dst = link;
666 struct rte_eth_link *src = &(dev->data->dev_link);
668 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
669 *(uint64_t *)src) == 0)
676 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
677 struct rte_eth_link *link)
679 struct rte_eth_link *dst = &(dev->data->dev_link);
680 struct rte_eth_link *src = link;
682 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
683 *(uint64_t *)src) == 0)
689 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
690 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
691 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
693 #ifndef I40E_GLQF_ORT
694 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
696 #ifndef I40E_GLQF_PIT
697 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
699 #ifndef I40E_GLQF_L3_MAP
700 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
703 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
706 * Initialize registers for flexible payload, which should be set by NVM.
707 * This should be removed from code once it is fixed in NVM.
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
719 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
720 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
722 /* Initialize registers for parsing packet type of QinQ */
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
724 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
727 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
730 * Add a ethertype filter to drop all flow control frames transmitted
734 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
736 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
737 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
738 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
739 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
742 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
743 I40E_FLOW_CONTROL_ETHERTYPE, flags,
744 pf->main_vsi_seid, 0,
748 "Failed to add filter to drop flow control frames from VSIs.");
752 floating_veb_list_handler(__rte_unused const char *key,
753 const char *floating_veb_value,
757 unsigned int count = 0;
760 bool *vf_floating_veb = opaque;
762 while (isblank(*floating_veb_value))
763 floating_veb_value++;
765 /* Reset floating VEB configuration for VFs */
766 for (idx = 0; idx < I40E_MAX_VF; idx++)
767 vf_floating_veb[idx] = false;
771 while (isblank(*floating_veb_value))
772 floating_veb_value++;
773 if (*floating_veb_value == '\0')
776 idx = strtoul(floating_veb_value, &end, 10);
777 if (errno || end == NULL)
779 while (isblank(*end))
783 } else if ((*end == ';') || (*end == '\0')) {
785 if (min == I40E_MAX_VF)
787 if (max >= I40E_MAX_VF)
788 max = I40E_MAX_VF - 1;
789 for (idx = min; idx <= max; idx++) {
790 vf_floating_veb[idx] = true;
797 floating_veb_value = end + 1;
798 } while (*end != '\0');
807 config_vf_floating_veb(struct rte_devargs *devargs,
808 uint16_t floating_veb,
809 bool *vf_floating_veb)
811 struct rte_kvargs *kvlist;
813 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
817 /* All the VFs attach to the floating VEB by default
818 * when the floating VEB is enabled.
820 for (i = 0; i < I40E_MAX_VF; i++)
821 vf_floating_veb[i] = true;
826 kvlist = rte_kvargs_parse(devargs->args, NULL);
830 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
831 rte_kvargs_free(kvlist);
834 /* When the floating_veb_list parameter exists, all the VFs
835 * will attach to the legacy VEB firstly, then configure VFs
836 * to the floating VEB according to the floating_veb_list.
838 if (rte_kvargs_process(kvlist, floating_veb_list,
839 floating_veb_list_handler,
840 vf_floating_veb) < 0) {
841 rte_kvargs_free(kvlist);
844 rte_kvargs_free(kvlist);
848 i40e_check_floating_handler(__rte_unused const char *key,
850 __rte_unused void *opaque)
852 if (strcmp(value, "1"))
859 is_floating_veb_supported(struct rte_devargs *devargs)
861 struct rte_kvargs *kvlist;
862 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
867 kvlist = rte_kvargs_parse(devargs->args, NULL);
871 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
872 rte_kvargs_free(kvlist);
875 /* Floating VEB is enabled when there's key-value:
876 * enable_floating_veb=1
878 if (rte_kvargs_process(kvlist, floating_veb_key,
879 i40e_check_floating_handler, NULL) < 0) {
880 rte_kvargs_free(kvlist);
883 rte_kvargs_free(kvlist);
889 config_floating_veb(struct rte_eth_dev *dev)
891 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
895 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
897 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
899 is_floating_veb_supported(pci_dev->device.devargs);
900 config_vf_floating_veb(pci_dev->device.devargs,
902 pf->floating_veb_list);
904 pf->floating_veb = false;
908 #define I40E_L2_TAGS_S_TAG_SHIFT 1
909 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
912 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
914 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
915 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
916 char ethertype_hash_name[RTE_HASH_NAMESIZE];
919 struct rte_hash_parameters ethertype_hash_params = {
920 .name = ethertype_hash_name,
921 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
922 .key_len = sizeof(struct i40e_ethertype_filter_input),
923 .hash_func = rte_hash_crc,
924 .hash_func_init_val = 0,
925 .socket_id = rte_socket_id(),
928 /* Initialize ethertype filter rule list and hash */
929 TAILQ_INIT(ðertype_rule->ethertype_list);
930 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
931 "ethertype_%s", dev->device->name);
932 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
933 if (!ethertype_rule->hash_table) {
934 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
937 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
938 sizeof(struct i40e_ethertype_filter *) *
939 I40E_MAX_ETHERTYPE_FILTER_NUM,
941 if (!ethertype_rule->hash_map) {
943 "Failed to allocate memory for ethertype hash map!");
945 goto err_ethertype_hash_map_alloc;
950 err_ethertype_hash_map_alloc:
951 rte_hash_free(ethertype_rule->hash_table);
957 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
960 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
961 char tunnel_hash_name[RTE_HASH_NAMESIZE];
964 struct rte_hash_parameters tunnel_hash_params = {
965 .name = tunnel_hash_name,
966 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
967 .key_len = sizeof(struct i40e_tunnel_filter_input),
968 .hash_func = rte_hash_crc,
969 .hash_func_init_val = 0,
970 .socket_id = rte_socket_id(),
973 /* Initialize tunnel filter rule list and hash */
974 TAILQ_INIT(&tunnel_rule->tunnel_list);
975 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
976 "tunnel_%s", dev->device->name);
977 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
978 if (!tunnel_rule->hash_table) {
979 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
982 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
983 sizeof(struct i40e_tunnel_filter *) *
984 I40E_MAX_TUNNEL_FILTER_NUM,
986 if (!tunnel_rule->hash_map) {
988 "Failed to allocate memory for tunnel hash map!");
990 goto err_tunnel_hash_map_alloc;
995 err_tunnel_hash_map_alloc:
996 rte_hash_free(tunnel_rule->hash_table);
1002 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1004 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1005 struct i40e_fdir_info *fdir_info = &pf->fdir;
1006 char fdir_hash_name[RTE_HASH_NAMESIZE];
1009 struct rte_hash_parameters fdir_hash_params = {
1010 .name = fdir_hash_name,
1011 .entries = I40E_MAX_FDIR_FILTER_NUM,
1012 .key_len = sizeof(struct rte_eth_fdir_input),
1013 .hash_func = rte_hash_crc,
1014 .hash_func_init_val = 0,
1015 .socket_id = rte_socket_id(),
1018 /* Initialize flow director filter rule list and hash */
1019 TAILQ_INIT(&fdir_info->fdir_list);
1020 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1021 "fdir_%s", dev->device->name);
1022 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1023 if (!fdir_info->hash_table) {
1024 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1027 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1028 sizeof(struct i40e_fdir_filter *) *
1029 I40E_MAX_FDIR_FILTER_NUM,
1031 if (!fdir_info->hash_map) {
1033 "Failed to allocate memory for fdir hash map!");
1035 goto err_fdir_hash_map_alloc;
1039 err_fdir_hash_map_alloc:
1040 rte_hash_free(fdir_info->hash_table);
1046 eth_i40e_dev_init(struct rte_eth_dev *dev)
1048 struct rte_pci_device *pci_dev;
1049 struct rte_intr_handle *intr_handle;
1050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1051 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052 struct i40e_vsi *vsi;
1055 uint8_t aq_fail = 0;
1057 PMD_INIT_FUNC_TRACE();
1059 dev->dev_ops = &i40e_eth_dev_ops;
1060 dev->rx_pkt_burst = i40e_recv_pkts;
1061 dev->tx_pkt_burst = i40e_xmit_pkts;
1062 dev->tx_pkt_prepare = i40e_prep_pkts;
1064 /* for secondary processes, we don't initialise any further as primary
1065 * has already done this work. Only check we don't need a different
1067 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1068 i40e_set_rx_function(dev);
1069 i40e_set_tx_function(dev);
1072 i40e_set_default_ptype_table(dev);
1073 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1074 intr_handle = &pci_dev->intr_handle;
1076 rte_eth_copy_pci_info(dev, pci_dev);
1077 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1079 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1080 pf->adapter->eth_dev = dev;
1081 pf->dev_data = dev->data;
1083 hw->back = I40E_PF_TO_ADAPTER(pf);
1084 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1087 "Hardware is not available, as address is NULL");
1091 hw->vendor_id = pci_dev->id.vendor_id;
1092 hw->device_id = pci_dev->id.device_id;
1093 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1094 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1095 hw->bus.device = pci_dev->addr.devid;
1096 hw->bus.func = pci_dev->addr.function;
1097 hw->adapter_stopped = 0;
1099 /* Make sure all is clean before doing PF reset */
1102 /* Initialize the hardware */
1105 /* Reset here to make sure all is clean for each PF */
1106 ret = i40e_pf_reset(hw);
1108 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1112 /* Initialize the shared code (base driver) */
1113 ret = i40e_init_shared_code(hw);
1115 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1120 * To work around the NVM issue, initialize registers
1121 * for flexible payload and packet type of QinQ by
1122 * software. It should be removed once issues are fixed
1125 i40e_GLQF_reg_init(hw);
1127 /* Initialize the input set for filters (hash and fd) to default value */
1128 i40e_filter_input_set_init(pf);
1130 /* Initialize the parameters for adminq */
1131 i40e_init_adminq_parameter(hw);
1132 ret = i40e_init_adminq(hw);
1133 if (ret != I40E_SUCCESS) {
1134 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1137 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1138 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1139 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1140 ((hw->nvm.version >> 12) & 0xf),
1141 ((hw->nvm.version >> 4) & 0xff),
1142 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1144 /* initialise the L3_MAP register */
1145 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1148 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1150 /* Need the special FW version to support floating VEB */
1151 config_floating_veb(dev);
1152 /* Clear PXE mode */
1153 i40e_clear_pxe_mode(hw);
1154 i40e_dev_sync_phy_type(hw);
1157 * On X710, performance number is far from the expectation on recent
1158 * firmware versions. The fix for this issue may not be integrated in
1159 * the following firmware version. So the workaround in software driver
1160 * is needed. It needs to modify the initial values of 3 internal only
1161 * registers. Note that the workaround can be removed when it is fixed
1162 * in firmware in the future.
1164 i40e_configure_registers(hw);
1166 /* Get hw capabilities */
1167 ret = i40e_get_cap(hw);
1168 if (ret != I40E_SUCCESS) {
1169 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1170 goto err_get_capabilities;
1173 /* Initialize parameters for PF */
1174 ret = i40e_pf_parameter_init(dev);
1176 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1177 goto err_parameter_init;
1180 /* Initialize the queue management */
1181 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1183 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1184 goto err_qp_pool_init;
1186 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1187 hw->func_caps.num_msix_vectors - 1);
1189 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1190 goto err_msix_pool_init;
1193 /* Initialize lan hmc */
1194 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1195 hw->func_caps.num_rx_qp, 0, 0);
1196 if (ret != I40E_SUCCESS) {
1197 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1198 goto err_init_lan_hmc;
1201 /* Configure lan hmc */
1202 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1203 if (ret != I40E_SUCCESS) {
1204 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1205 goto err_configure_lan_hmc;
1208 /* Get and check the mac address */
1209 i40e_get_mac_addr(hw, hw->mac.addr);
1210 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1211 PMD_INIT_LOG(ERR, "mac address is not valid");
1213 goto err_get_mac_addr;
1215 /* Copy the permanent MAC address */
1216 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1217 (struct ether_addr *) hw->mac.perm_addr);
1219 /* Disable flow control */
1220 hw->fc.requested_mode = I40E_FC_NONE;
1221 i40e_set_fc(hw, &aq_fail, TRUE);
1223 /* Set the global registers with default ether type value */
1224 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1225 if (ret != I40E_SUCCESS) {
1227 "Failed to set the default outer VLAN ether type");
1228 goto err_setup_pf_switch;
1231 /* PF setup, which includes VSI setup */
1232 ret = i40e_pf_setup(pf);
1234 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1235 goto err_setup_pf_switch;
1238 /* reset all stats of the device, including pf and main vsi */
1239 i40e_dev_stats_reset(dev);
1243 /* Disable double vlan by default */
1244 i40e_vsi_config_double_vlan(vsi, FALSE);
1246 /* Disable S-TAG identification when floating_veb is disabled */
1247 if (!pf->floating_veb) {
1248 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1249 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1250 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1251 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1255 if (!vsi->max_macaddrs)
1256 len = ETHER_ADDR_LEN;
1258 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1260 /* Should be after VSI initialized */
1261 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1262 if (!dev->data->mac_addrs) {
1264 "Failed to allocated memory for storing mac address");
1267 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1268 &dev->data->mac_addrs[0]);
1270 /* Init dcb to sw mode by default */
1271 ret = i40e_dcb_init_configure(dev, TRUE);
1272 if (ret != I40E_SUCCESS) {
1273 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1274 pf->flags &= ~I40E_FLAG_DCB;
1276 /* Update HW struct after DCB configuration */
1279 /* initialize pf host driver to setup SRIOV resource if applicable */
1280 i40e_pf_host_init(dev);
1282 /* register callback func to eal lib */
1283 rte_intr_callback_register(intr_handle,
1284 i40e_dev_interrupt_handler, dev);
1286 /* configure and enable device interrupt */
1287 i40e_pf_config_irq0(hw, TRUE);
1288 i40e_pf_enable_irq0(hw);
1290 /* enable uio intr after callback register */
1291 rte_intr_enable(intr_handle);
1293 * Add an ethertype filter to drop all flow control frames transmitted
1294 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1297 i40e_add_tx_flow_control_drop_filter(pf);
1299 /* Set the max frame size to 0x2600 by default,
1300 * in case other drivers changed the default value.
1302 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1304 /* initialize mirror rule list */
1305 TAILQ_INIT(&pf->mirror_list);
1307 /* initialize Traffic Manager configuration */
1308 i40e_tm_conf_init(dev);
1310 ret = i40e_init_ethtype_filter_list(dev);
1312 goto err_init_ethtype_filter_list;
1313 ret = i40e_init_tunnel_filter_list(dev);
1315 goto err_init_tunnel_filter_list;
1316 ret = i40e_init_fdir_filter_list(dev);
1318 goto err_init_fdir_filter_list;
1322 err_init_fdir_filter_list:
1323 rte_free(pf->tunnel.hash_table);
1324 rte_free(pf->tunnel.hash_map);
1325 err_init_tunnel_filter_list:
1326 rte_free(pf->ethertype.hash_table);
1327 rte_free(pf->ethertype.hash_map);
1328 err_init_ethtype_filter_list:
1329 rte_free(dev->data->mac_addrs);
1331 i40e_vsi_release(pf->main_vsi);
1332 err_setup_pf_switch:
1334 err_configure_lan_hmc:
1335 (void)i40e_shutdown_lan_hmc(hw);
1337 i40e_res_pool_destroy(&pf->msix_pool);
1339 i40e_res_pool_destroy(&pf->qp_pool);
1342 err_get_capabilities:
1343 (void)i40e_shutdown_adminq(hw);
1349 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1351 struct i40e_ethertype_filter *p_ethertype;
1352 struct i40e_ethertype_rule *ethertype_rule;
1354 ethertype_rule = &pf->ethertype;
1355 /* Remove all ethertype filter rules and hash */
1356 if (ethertype_rule->hash_map)
1357 rte_free(ethertype_rule->hash_map);
1358 if (ethertype_rule->hash_table)
1359 rte_hash_free(ethertype_rule->hash_table);
1361 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1362 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1363 p_ethertype, rules);
1364 rte_free(p_ethertype);
1369 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1371 struct i40e_tunnel_filter *p_tunnel;
1372 struct i40e_tunnel_rule *tunnel_rule;
1374 tunnel_rule = &pf->tunnel;
1375 /* Remove all tunnel director rules and hash */
1376 if (tunnel_rule->hash_map)
1377 rte_free(tunnel_rule->hash_map);
1378 if (tunnel_rule->hash_table)
1379 rte_hash_free(tunnel_rule->hash_table);
1381 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1382 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1388 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1390 struct i40e_fdir_filter *p_fdir;
1391 struct i40e_fdir_info *fdir_info;
1393 fdir_info = &pf->fdir;
1394 /* Remove all flow director rules and hash */
1395 if (fdir_info->hash_map)
1396 rte_free(fdir_info->hash_map);
1397 if (fdir_info->hash_table)
1398 rte_hash_free(fdir_info->hash_table);
1400 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1401 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1407 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1410 struct rte_pci_device *pci_dev;
1411 struct rte_intr_handle *intr_handle;
1413 struct i40e_filter_control_settings settings;
1414 struct rte_flow *p_flow;
1416 uint8_t aq_fail = 0;
1418 PMD_INIT_FUNC_TRACE();
1420 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1423 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1424 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1426 intr_handle = &pci_dev->intr_handle;
1428 if (hw->adapter_stopped == 0)
1429 i40e_dev_close(dev);
1431 dev->dev_ops = NULL;
1432 dev->rx_pkt_burst = NULL;
1433 dev->tx_pkt_burst = NULL;
1435 /* Clear PXE mode */
1436 i40e_clear_pxe_mode(hw);
1438 /* Unconfigure filter control */
1439 memset(&settings, 0, sizeof(settings));
1440 ret = i40e_set_filter_control(hw, &settings);
1442 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1445 /* Disable flow control */
1446 hw->fc.requested_mode = I40E_FC_NONE;
1447 i40e_set_fc(hw, &aq_fail, TRUE);
1449 /* uninitialize pf host driver */
1450 i40e_pf_host_uninit(dev);
1452 rte_free(dev->data->mac_addrs);
1453 dev->data->mac_addrs = NULL;
1455 /* disable uio intr before callback unregister */
1456 rte_intr_disable(intr_handle);
1458 /* register callback func to eal lib */
1459 rte_intr_callback_unregister(intr_handle,
1460 i40e_dev_interrupt_handler, dev);
1462 i40e_rm_ethtype_filter_list(pf);
1463 i40e_rm_tunnel_filter_list(pf);
1464 i40e_rm_fdir_filter_list(pf);
1466 /* Remove all flows */
1467 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1468 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1472 /* Remove all Traffic Manager configuration */
1473 i40e_tm_conf_uninit(dev);
1479 i40e_dev_configure(struct rte_eth_dev *dev)
1481 struct i40e_adapter *ad =
1482 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1483 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1484 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1488 ret = i40e_dev_sync_phy_type(hw);
1492 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1493 * bulk allocation or vector Rx preconditions we will reset it.
1495 ad->rx_bulk_alloc_allowed = true;
1496 ad->rx_vec_allowed = true;
1497 ad->tx_simple_allowed = true;
1498 ad->tx_vec_allowed = true;
1500 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1501 ret = i40e_fdir_setup(pf);
1502 if (ret != I40E_SUCCESS) {
1503 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1506 ret = i40e_fdir_configure(dev);
1508 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1512 i40e_fdir_teardown(pf);
1514 ret = i40e_dev_init_vlan(dev);
1519 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1520 * RSS setting have different requirements.
1521 * General PMD driver call sequence are NIC init, configure,
1522 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1523 * will try to lookup the VSI that specific queue belongs to if VMDQ
1524 * applicable. So, VMDQ setting has to be done before
1525 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1526 * For RSS setting, it will try to calculate actual configured RX queue
1527 * number, which will be available after rx_queue_setup(). dev_start()
1528 * function is good to place RSS setup.
1530 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1531 ret = i40e_vmdq_setup(dev);
1536 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1537 ret = i40e_dcb_setup(dev);
1539 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1544 TAILQ_INIT(&pf->flow_list);
1549 /* need to release vmdq resource if exists */
1550 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1551 i40e_vsi_release(pf->vmdq[i].vsi);
1552 pf->vmdq[i].vsi = NULL;
1557 /* need to release fdir resource if exists */
1558 i40e_fdir_teardown(pf);
1563 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1565 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1566 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1567 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1568 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1569 uint16_t msix_vect = vsi->msix_intr;
1572 for (i = 0; i < vsi->nb_qps; i++) {
1573 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1574 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1578 if (vsi->type != I40E_VSI_SRIOV) {
1579 if (!rte_intr_allow_others(intr_handle)) {
1580 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1581 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1583 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1586 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1587 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1589 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1594 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1595 vsi->user_param + (msix_vect - 1);
1597 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1598 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1600 I40E_WRITE_FLUSH(hw);
1604 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1605 int base_queue, int nb_queue,
1610 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1612 /* Bind all RX queues to allocated MSIX interrupt */
1613 for (i = 0; i < nb_queue; i++) {
1614 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1615 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1616 ((base_queue + i + 1) <<
1617 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1618 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1619 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1621 if (i == nb_queue - 1)
1622 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1623 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1626 /* Write first RX queue to Link list register as the head element */
1627 if (vsi->type != I40E_VSI_SRIOV) {
1629 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1631 if (msix_vect == I40E_MISC_VEC_ID) {
1632 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1634 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1636 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1638 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1641 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1643 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1645 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1647 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1654 if (msix_vect == I40E_MISC_VEC_ID) {
1656 I40E_VPINT_LNKLST0(vsi->user_param),
1658 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1660 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1662 /* num_msix_vectors_vf needs to minus irq0 */
1663 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1664 vsi->user_param + (msix_vect - 1);
1666 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1668 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1670 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1674 I40E_WRITE_FLUSH(hw);
1678 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1680 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1681 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1682 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1683 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1684 uint16_t msix_vect = vsi->msix_intr;
1685 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1686 uint16_t queue_idx = 0;
1691 for (i = 0; i < vsi->nb_qps; i++) {
1692 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1693 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1696 /* INTENA flag is not auto-cleared for interrupt */
1697 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1698 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1699 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1700 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1701 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1703 /* VF bind interrupt */
1704 if (vsi->type == I40E_VSI_SRIOV) {
1705 __vsi_queues_bind_intr(vsi, msix_vect,
1706 vsi->base_queue, vsi->nb_qps,
1711 /* PF & VMDq bind interrupt */
1712 if (rte_intr_dp_is_en(intr_handle)) {
1713 if (vsi->type == I40E_VSI_MAIN) {
1716 } else if (vsi->type == I40E_VSI_VMDQ2) {
1717 struct i40e_vsi *main_vsi =
1718 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1719 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1724 for (i = 0; i < vsi->nb_used_qps; i++) {
1726 if (!rte_intr_allow_others(intr_handle))
1727 /* allow to share MISC_VEC_ID */
1728 msix_vect = I40E_MISC_VEC_ID;
1730 /* no enough msix_vect, map all to one */
1731 __vsi_queues_bind_intr(vsi, msix_vect,
1732 vsi->base_queue + i,
1733 vsi->nb_used_qps - i,
1735 for (; !!record && i < vsi->nb_used_qps; i++)
1736 intr_handle->intr_vec[queue_idx + i] =
1740 /* 1:1 queue/msix_vect mapping */
1741 __vsi_queues_bind_intr(vsi, msix_vect,
1742 vsi->base_queue + i, 1,
1745 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1753 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1755 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1756 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1757 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1758 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1759 uint16_t interval = i40e_calc_itr_interval(\
1760 RTE_LIBRTE_I40E_ITR_INTERVAL);
1761 uint16_t msix_intr, i;
1763 if (rte_intr_allow_others(intr_handle))
1764 for (i = 0; i < vsi->nb_msix; i++) {
1765 msix_intr = vsi->msix_intr + i;
1766 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1767 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1768 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1769 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1771 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1774 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1775 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1776 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1777 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1779 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1781 I40E_WRITE_FLUSH(hw);
1785 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1787 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1789 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1791 uint16_t msix_intr, i;
1793 if (rte_intr_allow_others(intr_handle))
1794 for (i = 0; i < vsi->nb_msix; i++) {
1795 msix_intr = vsi->msix_intr + i;
1796 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1800 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1802 I40E_WRITE_FLUSH(hw);
1805 static inline uint8_t
1806 i40e_parse_link_speeds(uint16_t link_speeds)
1808 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1810 if (link_speeds & ETH_LINK_SPEED_40G)
1811 link_speed |= I40E_LINK_SPEED_40GB;
1812 if (link_speeds & ETH_LINK_SPEED_25G)
1813 link_speed |= I40E_LINK_SPEED_25GB;
1814 if (link_speeds & ETH_LINK_SPEED_20G)
1815 link_speed |= I40E_LINK_SPEED_20GB;
1816 if (link_speeds & ETH_LINK_SPEED_10G)
1817 link_speed |= I40E_LINK_SPEED_10GB;
1818 if (link_speeds & ETH_LINK_SPEED_1G)
1819 link_speed |= I40E_LINK_SPEED_1GB;
1820 if (link_speeds & ETH_LINK_SPEED_100M)
1821 link_speed |= I40E_LINK_SPEED_100MB;
1827 i40e_phy_conf_link(struct i40e_hw *hw,
1829 uint8_t force_speed,
1832 enum i40e_status_code status;
1833 struct i40e_aq_get_phy_abilities_resp phy_ab;
1834 struct i40e_aq_set_phy_config phy_conf;
1835 enum i40e_aq_phy_type cnt;
1836 uint32_t phy_type_mask = 0;
1838 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1839 I40E_AQ_PHY_FLAG_PAUSE_RX |
1840 I40E_AQ_PHY_FLAG_PAUSE_RX |
1841 I40E_AQ_PHY_FLAG_LOW_POWER;
1842 const uint8_t advt = I40E_LINK_SPEED_40GB |
1843 I40E_LINK_SPEED_25GB |
1844 I40E_LINK_SPEED_10GB |
1845 I40E_LINK_SPEED_1GB |
1846 I40E_LINK_SPEED_100MB;
1850 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1855 /* If link already up, no need to set up again */
1856 if (is_up && phy_ab.phy_type != 0)
1857 return I40E_SUCCESS;
1859 memset(&phy_conf, 0, sizeof(phy_conf));
1861 /* bits 0-2 use the values from get_phy_abilities_resp */
1863 abilities |= phy_ab.abilities & mask;
1865 /* update ablities and speed */
1866 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1867 phy_conf.link_speed = advt;
1869 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1871 phy_conf.abilities = abilities;
1875 /* To enable link, phy_type mask needs to include each type */
1876 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1877 phy_type_mask |= 1 << cnt;
1879 /* use get_phy_abilities_resp value for the rest */
1880 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1881 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1882 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1883 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1884 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1885 phy_conf.eee_capability = phy_ab.eee_capability;
1886 phy_conf.eeer = phy_ab.eeer_val;
1887 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1889 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1890 phy_ab.abilities, phy_ab.link_speed);
1891 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1892 phy_conf.abilities, phy_conf.link_speed);
1894 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1898 return I40E_SUCCESS;
1902 i40e_apply_link_speed(struct rte_eth_dev *dev)
1905 uint8_t abilities = 0;
1906 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907 struct rte_eth_conf *conf = &dev->data->dev_conf;
1909 speed = i40e_parse_link_speeds(conf->link_speeds);
1910 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1911 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1912 abilities |= I40E_AQ_PHY_AN_ENABLED;
1913 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1915 return i40e_phy_conf_link(hw, abilities, speed, true);
1919 i40e_dev_start(struct rte_eth_dev *dev)
1921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923 struct i40e_vsi *main_vsi = pf->main_vsi;
1925 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1926 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1927 uint32_t intr_vector = 0;
1928 struct i40e_vsi *vsi;
1930 hw->adapter_stopped = 0;
1932 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1933 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1934 dev->data->port_id);
1938 rte_intr_disable(intr_handle);
1940 if ((rte_intr_cap_multiple(intr_handle) ||
1941 !RTE_ETH_DEV_SRIOV(dev).active) &&
1942 dev->data->dev_conf.intr_conf.rxq != 0) {
1943 intr_vector = dev->data->nb_rx_queues;
1944 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1949 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1950 intr_handle->intr_vec =
1951 rte_zmalloc("intr_vec",
1952 dev->data->nb_rx_queues * sizeof(int),
1954 if (!intr_handle->intr_vec) {
1956 "Failed to allocate %d rx_queues intr_vec",
1957 dev->data->nb_rx_queues);
1962 /* Initialize VSI */
1963 ret = i40e_dev_rxtx_init(pf);
1964 if (ret != I40E_SUCCESS) {
1965 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1969 /* Map queues with MSIX interrupt */
1970 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1971 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1972 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1973 i40e_vsi_enable_queues_intr(main_vsi);
1975 /* Map VMDQ VSI queues with MSIX interrupt */
1976 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1977 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1978 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1979 I40E_ITR_INDEX_DEFAULT);
1980 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1983 /* enable FDIR MSIX interrupt */
1984 if (pf->fdir.fdir_vsi) {
1985 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1986 I40E_ITR_INDEX_NONE);
1987 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1990 /* Enable all queues which have been configured */
1991 ret = i40e_dev_switch_queues(pf, TRUE);
1992 if (ret != I40E_SUCCESS) {
1993 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1997 /* Enable receiving broadcast packets */
1998 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1999 if (ret != I40E_SUCCESS)
2000 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2002 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2003 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2005 if (ret != I40E_SUCCESS)
2006 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2009 /* Enable the VLAN promiscuous mode. */
2011 for (i = 0; i < pf->vf_num; i++) {
2012 vsi = pf->vfs[i].vsi;
2013 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2018 /* Apply link configure */
2019 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2020 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2021 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2022 ETH_LINK_SPEED_40G)) {
2023 PMD_DRV_LOG(ERR, "Invalid link setting");
2026 ret = i40e_apply_link_speed(dev);
2027 if (I40E_SUCCESS != ret) {
2028 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2032 if (!rte_intr_allow_others(intr_handle)) {
2033 rte_intr_callback_unregister(intr_handle,
2034 i40e_dev_interrupt_handler,
2036 /* configure and enable device interrupt */
2037 i40e_pf_config_irq0(hw, FALSE);
2038 i40e_pf_enable_irq0(hw);
2040 if (dev->data->dev_conf.intr_conf.lsc != 0)
2042 "lsc won't enable because of no intr multiplex");
2044 ret = i40e_aq_set_phy_int_mask(hw,
2045 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2046 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2047 I40E_AQ_EVENT_MEDIA_NA), NULL);
2048 if (ret != I40E_SUCCESS)
2049 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2051 /* Call get_link_info aq commond to enable/disable LSE */
2052 i40e_dev_link_update(dev, 0);
2055 /* enable uio intr after callback register */
2056 rte_intr_enable(intr_handle);
2058 i40e_filter_restore(pf);
2060 if (pf->tm_conf.root && !pf->tm_conf.committed)
2061 PMD_DRV_LOG(WARNING,
2062 "please call hierarchy_commit() "
2063 "before starting the port");
2065 return I40E_SUCCESS;
2068 i40e_dev_switch_queues(pf, FALSE);
2069 i40e_dev_clear_queues(dev);
2075 i40e_dev_stop(struct rte_eth_dev *dev)
2077 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 struct i40e_vsi *main_vsi = pf->main_vsi;
2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2084 if (hw->adapter_stopped == 1)
2086 /* Disable all queues */
2087 i40e_dev_switch_queues(pf, FALSE);
2089 /* un-map queues with interrupt registers */
2090 i40e_vsi_disable_queues_intr(main_vsi);
2091 i40e_vsi_queues_unbind_intr(main_vsi);
2093 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2094 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2095 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2098 if (pf->fdir.fdir_vsi) {
2099 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2100 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2102 /* Clear all queues and release memory */
2103 i40e_dev_clear_queues(dev);
2106 i40e_dev_set_link_down(dev);
2108 if (!rte_intr_allow_others(intr_handle))
2109 /* resume to the default handler */
2110 rte_intr_callback_register(intr_handle,
2111 i40e_dev_interrupt_handler,
2114 /* Clean datapath event and queue/vec mapping */
2115 rte_intr_efd_disable(intr_handle);
2116 if (intr_handle->intr_vec) {
2117 rte_free(intr_handle->intr_vec);
2118 intr_handle->intr_vec = NULL;
2121 /* reset hierarchy commit */
2122 pf->tm_conf.committed = false;
2124 hw->adapter_stopped = 1;
2128 i40e_dev_close(struct rte_eth_dev *dev)
2130 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2133 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2134 struct i40e_mirror_rule *p_mirror;
2139 PMD_INIT_FUNC_TRACE();
2143 /* Remove all mirror rules */
2144 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2145 ret = i40e_aq_del_mirror_rule(hw,
2146 pf->main_vsi->veb->seid,
2147 p_mirror->rule_type,
2149 p_mirror->num_entries,
2152 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2153 "status = %d, aq_err = %d.", ret,
2154 hw->aq.asq_last_status);
2156 /* remove mirror software resource anyway */
2157 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2159 pf->nb_mirror_rule--;
2162 i40e_dev_free_queues(dev);
2164 /* Disable interrupt */
2165 i40e_pf_disable_irq0(hw);
2166 rte_intr_disable(intr_handle);
2168 /* shutdown and destroy the HMC */
2169 i40e_shutdown_lan_hmc(hw);
2171 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2172 i40e_vsi_release(pf->vmdq[i].vsi);
2173 pf->vmdq[i].vsi = NULL;
2178 /* release all the existing VSIs and VEBs */
2179 i40e_fdir_teardown(pf);
2180 i40e_vsi_release(pf->main_vsi);
2182 /* shutdown the adminq */
2183 i40e_aq_queue_shutdown(hw, true);
2184 i40e_shutdown_adminq(hw);
2186 i40e_res_pool_destroy(&pf->qp_pool);
2187 i40e_res_pool_destroy(&pf->msix_pool);
2189 /* force a PF reset to clean anything leftover */
2190 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2191 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2192 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2193 I40E_WRITE_FLUSH(hw);
2197 * Reset PF device only to re-initialize resources in PMD layer
2200 i40e_dev_reset(struct rte_eth_dev *dev)
2204 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2205 * its VF to make them align with it. The detailed notification
2206 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2207 * To avoid unexpected behavior in VF, currently reset of PF with
2208 * SR-IOV activation is not supported. It might be supported later.
2210 if (dev->data->sriov.active)
2213 ret = eth_i40e_dev_uninit(dev);
2217 ret = eth_i40e_dev_init(dev);
2223 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2225 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 struct i40e_vsi *vsi = pf->main_vsi;
2230 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2232 if (status != I40E_SUCCESS)
2233 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2235 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2237 if (status != I40E_SUCCESS)
2238 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2243 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2246 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247 struct i40e_vsi *vsi = pf->main_vsi;
2250 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2252 if (status != I40E_SUCCESS)
2253 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2255 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2257 if (status != I40E_SUCCESS)
2258 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2262 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2264 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2265 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2266 struct i40e_vsi *vsi = pf->main_vsi;
2269 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2270 if (ret != I40E_SUCCESS)
2271 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2275 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2277 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2278 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279 struct i40e_vsi *vsi = pf->main_vsi;
2282 if (dev->data->promiscuous == 1)
2283 return; /* must remain in all_multicast mode */
2285 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2286 vsi->seid, FALSE, NULL);
2287 if (ret != I40E_SUCCESS)
2288 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2292 * Set device link up.
2295 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2297 /* re-apply link speed setting */
2298 return i40e_apply_link_speed(dev);
2302 * Set device link down.
2305 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2307 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2308 uint8_t abilities = 0;
2309 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2311 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2312 return i40e_phy_conf_link(hw, abilities, speed, false);
2316 i40e_dev_link_update(struct rte_eth_dev *dev,
2317 int wait_to_complete)
2319 #define CHECK_INTERVAL 100 /* 100ms */
2320 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2321 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322 struct i40e_link_status link_status;
2323 struct rte_eth_link link, old;
2325 unsigned rep_cnt = MAX_REPEAT_TIME;
2326 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2328 memset(&link, 0, sizeof(link));
2329 memset(&old, 0, sizeof(old));
2330 memset(&link_status, 0, sizeof(link_status));
2331 rte_i40e_dev_atomic_read_link_status(dev, &old);
2334 /* Get link status information from hardware */
2335 status = i40e_aq_get_link_info(hw, enable_lse,
2336 &link_status, NULL);
2337 if (status != I40E_SUCCESS) {
2338 link.link_speed = ETH_SPEED_NUM_100M;
2339 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2340 PMD_DRV_LOG(ERR, "Failed to get link info");
2344 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2345 if (!wait_to_complete || link.link_status)
2348 rte_delay_ms(CHECK_INTERVAL);
2349 } while (--rep_cnt);
2351 if (!link.link_status)
2354 /* i40e uses full duplex only */
2355 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2357 /* Parse the link status */
2358 switch (link_status.link_speed) {
2359 case I40E_LINK_SPEED_100MB:
2360 link.link_speed = ETH_SPEED_NUM_100M;
2362 case I40E_LINK_SPEED_1GB:
2363 link.link_speed = ETH_SPEED_NUM_1G;
2365 case I40E_LINK_SPEED_10GB:
2366 link.link_speed = ETH_SPEED_NUM_10G;
2368 case I40E_LINK_SPEED_20GB:
2369 link.link_speed = ETH_SPEED_NUM_20G;
2371 case I40E_LINK_SPEED_25GB:
2372 link.link_speed = ETH_SPEED_NUM_25G;
2374 case I40E_LINK_SPEED_40GB:
2375 link.link_speed = ETH_SPEED_NUM_40G;
2378 link.link_speed = ETH_SPEED_NUM_100M;
2382 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2383 ETH_LINK_SPEED_FIXED);
2386 rte_i40e_dev_atomic_write_link_status(dev, &link);
2387 if (link.link_status == old.link_status)
2390 i40e_notify_all_vfs_link_status(dev);
2395 /* Get all the statistics of a VSI */
2397 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2399 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2400 struct i40e_eth_stats *nes = &vsi->eth_stats;
2401 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2402 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2404 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2405 vsi->offset_loaded, &oes->rx_bytes,
2407 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2408 vsi->offset_loaded, &oes->rx_unicast,
2410 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2411 vsi->offset_loaded, &oes->rx_multicast,
2412 &nes->rx_multicast);
2413 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2414 vsi->offset_loaded, &oes->rx_broadcast,
2415 &nes->rx_broadcast);
2416 /* exclude CRC bytes */
2417 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2418 nes->rx_broadcast) * ETHER_CRC_LEN;
2420 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2421 &oes->rx_discards, &nes->rx_discards);
2422 /* GLV_REPC not supported */
2423 /* GLV_RMPC not supported */
2424 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2425 &oes->rx_unknown_protocol,
2426 &nes->rx_unknown_protocol);
2427 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2428 vsi->offset_loaded, &oes->tx_bytes,
2430 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2431 vsi->offset_loaded, &oes->tx_unicast,
2433 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2434 vsi->offset_loaded, &oes->tx_multicast,
2435 &nes->tx_multicast);
2436 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2437 vsi->offset_loaded, &oes->tx_broadcast,
2438 &nes->tx_broadcast);
2439 /* GLV_TDPC not supported */
2440 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2441 &oes->tx_errors, &nes->tx_errors);
2442 vsi->offset_loaded = true;
2444 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2446 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2447 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2448 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2449 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2450 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2451 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2452 nes->rx_unknown_protocol);
2453 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2454 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2455 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2456 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2457 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2458 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2459 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2464 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2467 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2468 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2470 /* Get rx/tx bytes of internal transfer packets */
2471 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2472 I40E_GLV_GORCL(hw->port),
2474 &pf->internal_stats_offset.rx_bytes,
2475 &pf->internal_stats.rx_bytes);
2477 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2478 I40E_GLV_GOTCL(hw->port),
2480 &pf->internal_stats_offset.tx_bytes,
2481 &pf->internal_stats.tx_bytes);
2482 /* Get total internal rx packet count */
2483 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2484 I40E_GLV_UPRCL(hw->port),
2486 &pf->internal_stats_offset.rx_unicast,
2487 &pf->internal_stats.rx_unicast);
2488 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2489 I40E_GLV_MPRCL(hw->port),
2491 &pf->internal_stats_offset.rx_multicast,
2492 &pf->internal_stats.rx_multicast);
2493 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2494 I40E_GLV_BPRCL(hw->port),
2496 &pf->internal_stats_offset.rx_broadcast,
2497 &pf->internal_stats.rx_broadcast);
2499 /* exclude CRC size */
2500 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2501 pf->internal_stats.rx_multicast +
2502 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2504 /* Get statistics of struct i40e_eth_stats */
2505 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2506 I40E_GLPRT_GORCL(hw->port),
2507 pf->offset_loaded, &os->eth.rx_bytes,
2509 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2510 I40E_GLPRT_UPRCL(hw->port),
2511 pf->offset_loaded, &os->eth.rx_unicast,
2512 &ns->eth.rx_unicast);
2513 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2514 I40E_GLPRT_MPRCL(hw->port),
2515 pf->offset_loaded, &os->eth.rx_multicast,
2516 &ns->eth.rx_multicast);
2517 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2518 I40E_GLPRT_BPRCL(hw->port),
2519 pf->offset_loaded, &os->eth.rx_broadcast,
2520 &ns->eth.rx_broadcast);
2521 /* Workaround: CRC size should not be included in byte statistics,
2522 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2524 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2525 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2527 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2528 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2531 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2532 ns->eth.rx_bytes = 0;
2533 /* exlude internal rx bytes */
2535 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2537 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2538 pf->offset_loaded, &os->eth.rx_discards,
2539 &ns->eth.rx_discards);
2540 /* GLPRT_REPC not supported */
2541 /* GLPRT_RMPC not supported */
2542 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2544 &os->eth.rx_unknown_protocol,
2545 &ns->eth.rx_unknown_protocol);
2546 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2547 I40E_GLPRT_GOTCL(hw->port),
2548 pf->offset_loaded, &os->eth.tx_bytes,
2550 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2551 I40E_GLPRT_UPTCL(hw->port),
2552 pf->offset_loaded, &os->eth.tx_unicast,
2553 &ns->eth.tx_unicast);
2554 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2555 I40E_GLPRT_MPTCL(hw->port),
2556 pf->offset_loaded, &os->eth.tx_multicast,
2557 &ns->eth.tx_multicast);
2558 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2559 I40E_GLPRT_BPTCL(hw->port),
2560 pf->offset_loaded, &os->eth.tx_broadcast,
2561 &ns->eth.tx_broadcast);
2562 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2563 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2565 /* exclude internal tx bytes */
2566 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2567 ns->eth.tx_bytes = 0;
2569 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2571 /* GLPRT_TEPC not supported */
2573 /* additional port specific stats */
2574 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2575 pf->offset_loaded, &os->tx_dropped_link_down,
2576 &ns->tx_dropped_link_down);
2577 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2578 pf->offset_loaded, &os->crc_errors,
2580 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2581 pf->offset_loaded, &os->illegal_bytes,
2582 &ns->illegal_bytes);
2583 /* GLPRT_ERRBC not supported */
2584 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2585 pf->offset_loaded, &os->mac_local_faults,
2586 &ns->mac_local_faults);
2587 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2588 pf->offset_loaded, &os->mac_remote_faults,
2589 &ns->mac_remote_faults);
2590 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2591 pf->offset_loaded, &os->rx_length_errors,
2592 &ns->rx_length_errors);
2593 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2594 pf->offset_loaded, &os->link_xon_rx,
2596 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2597 pf->offset_loaded, &os->link_xoff_rx,
2599 for (i = 0; i < 8; i++) {
2600 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2602 &os->priority_xon_rx[i],
2603 &ns->priority_xon_rx[i]);
2604 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2606 &os->priority_xoff_rx[i],
2607 &ns->priority_xoff_rx[i]);
2609 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2610 pf->offset_loaded, &os->link_xon_tx,
2612 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2613 pf->offset_loaded, &os->link_xoff_tx,
2615 for (i = 0; i < 8; i++) {
2616 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2618 &os->priority_xon_tx[i],
2619 &ns->priority_xon_tx[i]);
2620 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2622 &os->priority_xoff_tx[i],
2623 &ns->priority_xoff_tx[i]);
2624 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2626 &os->priority_xon_2_xoff[i],
2627 &ns->priority_xon_2_xoff[i]);
2629 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2630 I40E_GLPRT_PRC64L(hw->port),
2631 pf->offset_loaded, &os->rx_size_64,
2633 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2634 I40E_GLPRT_PRC127L(hw->port),
2635 pf->offset_loaded, &os->rx_size_127,
2637 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2638 I40E_GLPRT_PRC255L(hw->port),
2639 pf->offset_loaded, &os->rx_size_255,
2641 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2642 I40E_GLPRT_PRC511L(hw->port),
2643 pf->offset_loaded, &os->rx_size_511,
2645 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2646 I40E_GLPRT_PRC1023L(hw->port),
2647 pf->offset_loaded, &os->rx_size_1023,
2649 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2650 I40E_GLPRT_PRC1522L(hw->port),
2651 pf->offset_loaded, &os->rx_size_1522,
2653 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2654 I40E_GLPRT_PRC9522L(hw->port),
2655 pf->offset_loaded, &os->rx_size_big,
2657 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2658 pf->offset_loaded, &os->rx_undersize,
2660 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2661 pf->offset_loaded, &os->rx_fragments,
2663 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2664 pf->offset_loaded, &os->rx_oversize,
2666 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2667 pf->offset_loaded, &os->rx_jabber,
2669 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2670 I40E_GLPRT_PTC64L(hw->port),
2671 pf->offset_loaded, &os->tx_size_64,
2673 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2674 I40E_GLPRT_PTC127L(hw->port),
2675 pf->offset_loaded, &os->tx_size_127,
2677 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2678 I40E_GLPRT_PTC255L(hw->port),
2679 pf->offset_loaded, &os->tx_size_255,
2681 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2682 I40E_GLPRT_PTC511L(hw->port),
2683 pf->offset_loaded, &os->tx_size_511,
2685 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2686 I40E_GLPRT_PTC1023L(hw->port),
2687 pf->offset_loaded, &os->tx_size_1023,
2689 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2690 I40E_GLPRT_PTC1522L(hw->port),
2691 pf->offset_loaded, &os->tx_size_1522,
2693 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2694 I40E_GLPRT_PTC9522L(hw->port),
2695 pf->offset_loaded, &os->tx_size_big,
2697 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2699 &os->fd_sb_match, &ns->fd_sb_match);
2700 /* GLPRT_MSPDC not supported */
2701 /* GLPRT_XEC not supported */
2703 pf->offset_loaded = true;
2706 i40e_update_vsi_stats(pf->main_vsi);
2709 /* Get all statistics of a port */
2711 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2713 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2718 /* call read registers - updates values, now write them to struct */
2719 i40e_read_stats_registers(pf, hw);
2721 stats->ipackets = ns->eth.rx_unicast +
2722 ns->eth.rx_multicast +
2723 ns->eth.rx_broadcast -
2724 ns->eth.rx_discards -
2725 pf->main_vsi->eth_stats.rx_discards;
2726 stats->opackets = ns->eth.tx_unicast +
2727 ns->eth.tx_multicast +
2728 ns->eth.tx_broadcast;
2729 stats->ibytes = ns->eth.rx_bytes;
2730 stats->obytes = ns->eth.tx_bytes;
2731 stats->oerrors = ns->eth.tx_errors +
2732 pf->main_vsi->eth_stats.tx_errors;
2735 stats->imissed = ns->eth.rx_discards +
2736 pf->main_vsi->eth_stats.rx_discards;
2737 stats->ierrors = ns->crc_errors +
2738 ns->rx_length_errors + ns->rx_undersize +
2739 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2741 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2742 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2743 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2744 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2745 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2746 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2747 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2748 ns->eth.rx_unknown_protocol);
2749 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2750 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2751 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2752 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2753 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2754 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2756 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2757 ns->tx_dropped_link_down);
2758 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2759 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2761 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2762 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2763 ns->mac_local_faults);
2764 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2765 ns->mac_remote_faults);
2766 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2767 ns->rx_length_errors);
2768 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2769 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2770 for (i = 0; i < 8; i++) {
2771 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2772 i, ns->priority_xon_rx[i]);
2773 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2774 i, ns->priority_xoff_rx[i]);
2776 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2777 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2778 for (i = 0; i < 8; i++) {
2779 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2780 i, ns->priority_xon_tx[i]);
2781 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2782 i, ns->priority_xoff_tx[i]);
2783 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2784 i, ns->priority_xon_2_xoff[i]);
2786 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2787 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2788 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2789 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2790 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2791 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2792 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2793 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2794 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2795 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2796 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2797 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2798 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2799 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2800 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2801 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2802 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2803 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2804 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2805 ns->mac_short_packet_dropped);
2806 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2807 ns->checksum_error);
2808 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2809 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2812 /* Reset the statistics */
2814 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2816 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2817 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819 /* Mark PF and VSI stats to update the offset, aka "reset" */
2820 pf->offset_loaded = false;
2822 pf->main_vsi->offset_loaded = false;
2824 /* read the stats, reading current register values into offset */
2825 i40e_read_stats_registers(pf, hw);
2829 i40e_xstats_calc_num(void)
2831 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2832 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2833 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2836 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2837 struct rte_eth_xstat_name *xstats_names,
2838 __rte_unused unsigned limit)
2843 if (xstats_names == NULL)
2844 return i40e_xstats_calc_num();
2846 /* Note: limit checked in rte_eth_xstats_names() */
2848 /* Get stats from i40e_eth_stats struct */
2849 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2850 snprintf(xstats_names[count].name,
2851 sizeof(xstats_names[count].name),
2852 "%s", rte_i40e_stats_strings[i].name);
2856 /* Get individiual stats from i40e_hw_port struct */
2857 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2858 snprintf(xstats_names[count].name,
2859 sizeof(xstats_names[count].name),
2860 "%s", rte_i40e_hw_port_strings[i].name);
2864 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2865 for (prio = 0; prio < 8; prio++) {
2866 snprintf(xstats_names[count].name,
2867 sizeof(xstats_names[count].name),
2868 "rx_priority%u_%s", prio,
2869 rte_i40e_rxq_prio_strings[i].name);
2874 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2875 for (prio = 0; prio < 8; prio++) {
2876 snprintf(xstats_names[count].name,
2877 sizeof(xstats_names[count].name),
2878 "tx_priority%u_%s", prio,
2879 rte_i40e_txq_prio_strings[i].name);
2887 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2892 unsigned i, count, prio;
2893 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2895 count = i40e_xstats_calc_num();
2899 i40e_read_stats_registers(pf, hw);
2906 /* Get stats from i40e_eth_stats struct */
2907 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2908 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2909 rte_i40e_stats_strings[i].offset);
2910 xstats[count].id = count;
2914 /* Get individiual stats from i40e_hw_port struct */
2915 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2916 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2917 rte_i40e_hw_port_strings[i].offset);
2918 xstats[count].id = count;
2922 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2923 for (prio = 0; prio < 8; prio++) {
2924 xstats[count].value =
2925 *(uint64_t *)(((char *)hw_stats) +
2926 rte_i40e_rxq_prio_strings[i].offset +
2927 (sizeof(uint64_t) * prio));
2928 xstats[count].id = count;
2933 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2934 for (prio = 0; prio < 8; prio++) {
2935 xstats[count].value =
2936 *(uint64_t *)(((char *)hw_stats) +
2937 rte_i40e_txq_prio_strings[i].offset +
2938 (sizeof(uint64_t) * prio));
2939 xstats[count].id = count;
2948 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2949 __rte_unused uint16_t queue_id,
2950 __rte_unused uint8_t stat_idx,
2951 __rte_unused uint8_t is_rx)
2953 PMD_INIT_FUNC_TRACE();
2959 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967 full_ver = hw->nvm.oem_ver;
2968 ver = (u8)(full_ver >> 24);
2969 build = (u16)((full_ver >> 8) & 0xffff);
2970 patch = (u8)(full_ver & 0xff);
2972 ret = snprintf(fw_version, fw_size,
2973 "%d.%d%d 0x%08x %d.%d.%d",
2974 ((hw->nvm.version >> 12) & 0xf),
2975 ((hw->nvm.version >> 4) & 0xff),
2976 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2979 ret += 1; /* add the size of '\0' */
2980 if (fw_size < (u32)ret)
2987 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2989 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2990 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2991 struct i40e_vsi *vsi = pf->main_vsi;
2992 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2994 dev_info->pci_dev = pci_dev;
2995 dev_info->max_rx_queues = vsi->nb_qps;
2996 dev_info->max_tx_queues = vsi->nb_qps;
2997 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2998 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2999 dev_info->max_mac_addrs = vsi->max_macaddrs;
3000 dev_info->max_vfs = pci_dev->max_vfs;
3001 dev_info->rx_offload_capa =
3002 DEV_RX_OFFLOAD_VLAN_STRIP |
3003 DEV_RX_OFFLOAD_QINQ_STRIP |
3004 DEV_RX_OFFLOAD_IPV4_CKSUM |
3005 DEV_RX_OFFLOAD_UDP_CKSUM |
3006 DEV_RX_OFFLOAD_TCP_CKSUM;
3007 dev_info->tx_offload_capa =
3008 DEV_TX_OFFLOAD_VLAN_INSERT |
3009 DEV_TX_OFFLOAD_QINQ_INSERT |
3010 DEV_TX_OFFLOAD_IPV4_CKSUM |
3011 DEV_TX_OFFLOAD_UDP_CKSUM |
3012 DEV_TX_OFFLOAD_TCP_CKSUM |
3013 DEV_TX_OFFLOAD_SCTP_CKSUM |
3014 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3015 DEV_TX_OFFLOAD_TCP_TSO |
3016 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3017 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3018 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3019 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3020 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3022 dev_info->reta_size = pf->hash_lut_size;
3023 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
3025 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3027 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3028 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3029 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3031 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3035 dev_info->default_txconf = (struct rte_eth_txconf) {
3037 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3038 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3039 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3041 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3042 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3043 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3044 ETH_TXQ_FLAGS_NOOFFLOADS,
3047 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3048 .nb_max = I40E_MAX_RING_DESC,
3049 .nb_min = I40E_MIN_RING_DESC,
3050 .nb_align = I40E_ALIGN_RING_DESC,
3053 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3054 .nb_max = I40E_MAX_RING_DESC,
3055 .nb_min = I40E_MIN_RING_DESC,
3056 .nb_align = I40E_ALIGN_RING_DESC,
3057 .nb_seg_max = I40E_TX_MAX_SEG,
3058 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3061 if (pf->flags & I40E_FLAG_VMDQ) {
3062 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3063 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3064 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3065 pf->max_nb_vmdq_vsi;
3066 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3067 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3068 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3071 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3073 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3074 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3076 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3079 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3083 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3085 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3086 struct i40e_vsi *vsi = pf->main_vsi;
3087 PMD_INIT_FUNC_TRACE();
3090 return i40e_vsi_add_vlan(vsi, vlan_id);
3092 return i40e_vsi_delete_vlan(vsi, vlan_id);
3096 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3097 enum rte_vlan_type vlan_type,
3098 uint16_t tpid, int qinq)
3100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3103 uint16_t reg_id = 3;
3107 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3111 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3113 if (ret != I40E_SUCCESS) {
3115 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3120 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3123 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3124 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3125 if (reg_r == reg_w) {
3126 PMD_DRV_LOG(DEBUG, "No need to write");
3130 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3132 if (ret != I40E_SUCCESS) {
3134 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3139 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3146 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3147 enum rte_vlan_type vlan_type,
3150 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3151 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3154 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3155 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3156 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3158 "Unsupported vlan type.");
3161 /* 802.1ad frames ability is added in NVM API 1.7*/
3162 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3164 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3165 hw->first_tag = rte_cpu_to_le_16(tpid);
3166 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3167 hw->second_tag = rte_cpu_to_le_16(tpid);
3169 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3170 hw->second_tag = rte_cpu_to_le_16(tpid);
3172 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3173 if (ret != I40E_SUCCESS) {
3175 "Set switch config failed aq_err: %d",
3176 hw->aq.asq_last_status);
3180 /* If NVM API < 1.7, keep the register setting */
3181 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3188 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3190 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3191 struct i40e_vsi *vsi = pf->main_vsi;
3193 if (mask & ETH_VLAN_FILTER_MASK) {
3194 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3195 i40e_vsi_config_vlan_filter(vsi, TRUE);
3197 i40e_vsi_config_vlan_filter(vsi, FALSE);
3200 if (mask & ETH_VLAN_STRIP_MASK) {
3201 /* Enable or disable VLAN stripping */
3202 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3203 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3205 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3208 if (mask & ETH_VLAN_EXTEND_MASK) {
3209 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3210 i40e_vsi_config_double_vlan(vsi, TRUE);
3211 /* Set global registers with default ethertype. */
3212 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3214 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3218 i40e_vsi_config_double_vlan(vsi, FALSE);
3223 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3224 __rte_unused uint16_t queue,
3225 __rte_unused int on)
3227 PMD_INIT_FUNC_TRACE();
3231 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3233 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3234 struct i40e_vsi *vsi = pf->main_vsi;
3235 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3236 struct i40e_vsi_vlan_pvid_info info;
3238 memset(&info, 0, sizeof(info));
3241 info.config.pvid = pvid;
3243 info.config.reject.tagged =
3244 data->dev_conf.txmode.hw_vlan_reject_tagged;
3245 info.config.reject.untagged =
3246 data->dev_conf.txmode.hw_vlan_reject_untagged;
3249 return i40e_vsi_vlan_pvid_set(vsi, &info);
3253 i40e_dev_led_on(struct rte_eth_dev *dev)
3255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3256 uint32_t mode = i40e_led_get(hw);
3259 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3265 i40e_dev_led_off(struct rte_eth_dev *dev)
3267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268 uint32_t mode = i40e_led_get(hw);
3271 i40e_led_set(hw, 0, false);
3277 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3279 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3280 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3282 fc_conf->pause_time = pf->fc_conf.pause_time;
3284 /* read out from register, in case they are modified by other port */
3285 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3286 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3287 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3288 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3290 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3291 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3293 /* Return current mode according to actual setting*/
3294 switch (hw->fc.current_mode) {
3296 fc_conf->mode = RTE_FC_FULL;
3298 case I40E_FC_TX_PAUSE:
3299 fc_conf->mode = RTE_FC_TX_PAUSE;
3301 case I40E_FC_RX_PAUSE:
3302 fc_conf->mode = RTE_FC_RX_PAUSE;
3306 fc_conf->mode = RTE_FC_NONE;
3313 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3315 uint32_t mflcn_reg, fctrl_reg, reg;
3316 uint32_t max_high_water;
3317 uint8_t i, aq_failure;
3321 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3322 [RTE_FC_NONE] = I40E_FC_NONE,
3323 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3324 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3325 [RTE_FC_FULL] = I40E_FC_FULL
3328 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3330 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3331 if ((fc_conf->high_water > max_high_water) ||
3332 (fc_conf->high_water < fc_conf->low_water)) {
3334 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3339 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3341 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3343 pf->fc_conf.pause_time = fc_conf->pause_time;
3344 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3345 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3347 PMD_INIT_FUNC_TRACE();
3349 /* All the link flow control related enable/disable register
3350 * configuration is handle by the F/W
3352 err = i40e_set_fc(hw, &aq_failure, true);
3356 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3357 /* Configure flow control refresh threshold,
3358 * the value for stat_tx_pause_refresh_timer[8]
3359 * is used for global pause operation.
3363 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3364 pf->fc_conf.pause_time);
3366 /* configure the timer value included in transmitted pause
3368 * the value for stat_tx_pause_quanta[8] is used for global
3371 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3372 pf->fc_conf.pause_time);
3374 fctrl_reg = I40E_READ_REG(hw,
3375 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3377 if (fc_conf->mac_ctrl_frame_fwd != 0)
3378 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3380 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3382 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3385 /* Configure pause time (2 TCs per register) */
3386 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3387 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3388 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3390 /* Configure flow control refresh threshold value */
3391 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3392 pf->fc_conf.pause_time / 2);
3394 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3396 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3397 *depending on configuration
3399 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3400 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3401 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3403 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3404 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3407 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3410 /* config the water marker both based on the packets and bytes */
3411 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3412 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3413 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3414 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3415 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3416 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3417 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3418 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3420 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3421 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3424 I40E_WRITE_FLUSH(hw);
3430 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3431 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3433 PMD_INIT_FUNC_TRACE();
3438 /* Add a MAC address, and update filters */
3440 i40e_macaddr_add(struct rte_eth_dev *dev,
3441 struct ether_addr *mac_addr,
3442 __rte_unused uint32_t index,
3445 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446 struct i40e_mac_filter_info mac_filter;
3447 struct i40e_vsi *vsi;
3450 /* If VMDQ not enabled or configured, return */
3451 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3452 !pf->nb_cfg_vmdq_vsi)) {
3453 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3454 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3459 if (pool > pf->nb_cfg_vmdq_vsi) {
3460 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3461 pool, pf->nb_cfg_vmdq_vsi);
3465 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3466 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3467 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3469 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3474 vsi = pf->vmdq[pool - 1].vsi;
3476 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3477 if (ret != I40E_SUCCESS) {
3478 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3484 /* Remove a MAC address, and update filters */
3486 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3488 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3489 struct i40e_vsi *vsi;
3490 struct rte_eth_dev_data *data = dev->data;
3491 struct ether_addr *macaddr;
3496 macaddr = &(data->mac_addrs[index]);
3498 pool_sel = dev->data->mac_pool_sel[index];
3500 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3501 if (pool_sel & (1ULL << i)) {
3505 /* No VMDQ pool enabled or configured */
3506 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3507 (i > pf->nb_cfg_vmdq_vsi)) {
3509 "No VMDQ pool enabled/configured");
3512 vsi = pf->vmdq[i - 1].vsi;
3514 ret = i40e_vsi_delete_mac(vsi, macaddr);
3517 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3524 /* Set perfect match or hash match of MAC and VLAN for a VF */
3526 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3527 struct rte_eth_mac_filter *filter,
3531 struct i40e_mac_filter_info mac_filter;
3532 struct ether_addr old_mac;
3533 struct ether_addr *new_mac;
3534 struct i40e_pf_vf *vf = NULL;
3539 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3542 hw = I40E_PF_TO_HW(pf);
3544 if (filter == NULL) {
3545 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3549 new_mac = &filter->mac_addr;
3551 if (is_zero_ether_addr(new_mac)) {
3552 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3556 vf_id = filter->dst_id;
3558 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3559 PMD_DRV_LOG(ERR, "Invalid argument.");
3562 vf = &pf->vfs[vf_id];
3564 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3565 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3570 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3571 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3573 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3576 mac_filter.filter_type = filter->filter_type;
3577 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3578 if (ret != I40E_SUCCESS) {
3579 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3582 ether_addr_copy(new_mac, &pf->dev_addr);
3584 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3586 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3587 if (ret != I40E_SUCCESS) {
3588 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3592 /* Clear device address as it has been removed */
3593 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3594 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3600 /* MAC filter handle */
3602 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3605 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3606 struct rte_eth_mac_filter *filter;
3607 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3608 int ret = I40E_NOT_SUPPORTED;
3610 filter = (struct rte_eth_mac_filter *)(arg);
3612 switch (filter_op) {
3613 case RTE_ETH_FILTER_NOP:
3616 case RTE_ETH_FILTER_ADD:
3617 i40e_pf_disable_irq0(hw);
3619 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3620 i40e_pf_enable_irq0(hw);
3622 case RTE_ETH_FILTER_DELETE:
3623 i40e_pf_disable_irq0(hw);
3625 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3626 i40e_pf_enable_irq0(hw);
3629 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3630 ret = I40E_ERR_PARAM;
3638 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3640 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3641 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3647 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3648 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3651 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3655 uint32_t *lut_dw = (uint32_t *)lut;
3656 uint16_t i, lut_size_dw = lut_size / 4;
3658 for (i = 0; i < lut_size_dw; i++)
3659 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3666 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3675 pf = I40E_VSI_TO_PF(vsi);
3676 hw = I40E_VSI_TO_HW(vsi);
3678 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3679 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3682 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3686 uint32_t *lut_dw = (uint32_t *)lut;
3687 uint16_t i, lut_size_dw = lut_size / 4;
3689 for (i = 0; i < lut_size_dw; i++)
3690 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3691 I40E_WRITE_FLUSH(hw);
3698 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3699 struct rte_eth_rss_reta_entry64 *reta_conf,
3702 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3703 uint16_t i, lut_size = pf->hash_lut_size;
3704 uint16_t idx, shift;
3708 if (reta_size != lut_size ||
3709 reta_size > ETH_RSS_RETA_SIZE_512) {
3711 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3712 reta_size, lut_size);
3716 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3718 PMD_DRV_LOG(ERR, "No memory can be allocated");
3721 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3724 for (i = 0; i < reta_size; i++) {
3725 idx = i / RTE_RETA_GROUP_SIZE;
3726 shift = i % RTE_RETA_GROUP_SIZE;
3727 if (reta_conf[idx].mask & (1ULL << shift))
3728 lut[i] = reta_conf[idx].reta[shift];
3730 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3739 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3740 struct rte_eth_rss_reta_entry64 *reta_conf,
3743 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3744 uint16_t i, lut_size = pf->hash_lut_size;
3745 uint16_t idx, shift;
3749 if (reta_size != lut_size ||
3750 reta_size > ETH_RSS_RETA_SIZE_512) {
3752 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3753 reta_size, lut_size);
3757 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3759 PMD_DRV_LOG(ERR, "No memory can be allocated");
3763 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3766 for (i = 0; i < reta_size; i++) {
3767 idx = i / RTE_RETA_GROUP_SIZE;
3768 shift = i % RTE_RETA_GROUP_SIZE;
3769 if (reta_conf[idx].mask & (1ULL << shift))
3770 reta_conf[idx].reta[shift] = lut[i];
3780 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3781 * @hw: pointer to the HW structure
3782 * @mem: pointer to mem struct to fill out
3783 * @size: size of memory requested
3784 * @alignment: what to align the allocation to
3786 enum i40e_status_code
3787 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3788 struct i40e_dma_mem *mem,
3792 const struct rte_memzone *mz = NULL;
3793 char z_name[RTE_MEMZONE_NAMESIZE];
3796 return I40E_ERR_PARAM;
3798 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3799 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3800 alignment, RTE_PGSIZE_2M);
3802 return I40E_ERR_NO_MEMORY;
3806 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3807 mem->zone = (const void *)mz;
3809 "memzone %s allocated with physical address: %"PRIu64,
3812 return I40E_SUCCESS;
3816 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3817 * @hw: pointer to the HW structure
3818 * @mem: ptr to mem struct to free
3820 enum i40e_status_code
3821 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3822 struct i40e_dma_mem *mem)
3825 return I40E_ERR_PARAM;
3828 "memzone %s to be freed with physical address: %"PRIu64,
3829 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3830 rte_memzone_free((const struct rte_memzone *)mem->zone);
3835 return I40E_SUCCESS;
3839 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3840 * @hw: pointer to the HW structure
3841 * @mem: pointer to mem struct to fill out
3842 * @size: size of memory requested
3844 enum i40e_status_code
3845 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3846 struct i40e_virt_mem *mem,
3850 return I40E_ERR_PARAM;
3853 mem->va = rte_zmalloc("i40e", size, 0);
3856 return I40E_SUCCESS;
3858 return I40E_ERR_NO_MEMORY;
3862 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3863 * @hw: pointer to the HW structure
3864 * @mem: pointer to mem struct to free
3866 enum i40e_status_code
3867 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3868 struct i40e_virt_mem *mem)
3871 return I40E_ERR_PARAM;
3876 return I40E_SUCCESS;
3880 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3882 rte_spinlock_init(&sp->spinlock);
3886 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3888 rte_spinlock_lock(&sp->spinlock);
3892 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3894 rte_spinlock_unlock(&sp->spinlock);
3898 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3904 * Get the hardware capabilities, which will be parsed
3905 * and saved into struct i40e_hw.
3908 i40e_get_cap(struct i40e_hw *hw)
3910 struct i40e_aqc_list_capabilities_element_resp *buf;
3911 uint16_t len, size = 0;
3914 /* Calculate a huge enough buff for saving response data temporarily */
3915 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3916 I40E_MAX_CAP_ELE_NUM;
3917 buf = rte_zmalloc("i40e", len, 0);
3919 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3920 return I40E_ERR_NO_MEMORY;
3923 /* Get, parse the capabilities and save it to hw */
3924 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3925 i40e_aqc_opc_list_func_capabilities, NULL);
3926 if (ret != I40E_SUCCESS)
3927 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3929 /* Free the temporary buffer after being used */
3936 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3939 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3940 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3941 uint16_t qp_count = 0, vsi_count = 0;
3943 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3944 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3947 /* Add the parameter init for LFC */
3948 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3949 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3950 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3952 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3953 pf->max_num_vsi = hw->func_caps.num_vsis;
3954 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3955 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3956 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3958 /* FDir queue/VSI allocation */
3959 pf->fdir_qp_offset = 0;
3960 if (hw->func_caps.fd) {
3961 pf->flags |= I40E_FLAG_FDIR;
3962 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3964 pf->fdir_nb_qps = 0;
3966 qp_count += pf->fdir_nb_qps;
3969 /* LAN queue/VSI allocation */
3970 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3971 if (!hw->func_caps.rss) {
3974 pf->flags |= I40E_FLAG_RSS;
3975 if (hw->mac.type == I40E_MAC_X722)
3976 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3977 pf->lan_nb_qps = pf->lan_nb_qp_max;
3979 qp_count += pf->lan_nb_qps;
3982 /* VF queue/VSI allocation */
3983 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3984 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3985 pf->flags |= I40E_FLAG_SRIOV;
3986 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3987 pf->vf_num = pci_dev->max_vfs;
3989 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3990 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3995 qp_count += pf->vf_nb_qps * pf->vf_num;
3996 vsi_count += pf->vf_num;
3998 /* VMDq queue/VSI allocation */
3999 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4000 pf->vmdq_nb_qps = 0;
4001 pf->max_nb_vmdq_vsi = 0;
4002 if (hw->func_caps.vmdq) {
4003 if (qp_count < hw->func_caps.num_tx_qp &&
4004 vsi_count < hw->func_caps.num_vsis) {
4005 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4006 qp_count) / pf->vmdq_nb_qp_max;
4008 /* Limit the maximum number of VMDq vsi to the maximum
4009 * ethdev can support
4011 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4012 hw->func_caps.num_vsis - vsi_count);
4013 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4015 if (pf->max_nb_vmdq_vsi) {
4016 pf->flags |= I40E_FLAG_VMDQ;
4017 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4019 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4020 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4021 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4024 "No enough queues left for VMDq");
4027 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4030 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4031 vsi_count += pf->max_nb_vmdq_vsi;
4033 if (hw->func_caps.dcb)
4034 pf->flags |= I40E_FLAG_DCB;
4036 if (qp_count > hw->func_caps.num_tx_qp) {
4038 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4039 qp_count, hw->func_caps.num_tx_qp);
4042 if (vsi_count > hw->func_caps.num_vsis) {
4044 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4045 vsi_count, hw->func_caps.num_vsis);
4053 i40e_pf_get_switch_config(struct i40e_pf *pf)
4055 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4056 struct i40e_aqc_get_switch_config_resp *switch_config;
4057 struct i40e_aqc_switch_config_element_resp *element;
4058 uint16_t start_seid = 0, num_reported;
4061 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4062 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4063 if (!switch_config) {
4064 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4068 /* Get the switch configurations */
4069 ret = i40e_aq_get_switch_config(hw, switch_config,
4070 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4071 if (ret != I40E_SUCCESS) {
4072 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4075 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4076 if (num_reported != 1) { /* The number should be 1 */
4077 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4081 /* Parse the switch configuration elements */
4082 element = &(switch_config->element[0]);
4083 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4084 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4085 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4087 PMD_DRV_LOG(INFO, "Unknown element type");
4090 rte_free(switch_config);
4096 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4099 struct pool_entry *entry;
4101 if (pool == NULL || num == 0)
4104 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4105 if (entry == NULL) {
4106 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4110 /* queue heap initialize */
4111 pool->num_free = num;
4112 pool->num_alloc = 0;
4114 LIST_INIT(&pool->alloc_list);
4115 LIST_INIT(&pool->free_list);
4117 /* Initialize element */
4121 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4126 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4128 struct pool_entry *entry, *next_entry;
4133 for (entry = LIST_FIRST(&pool->alloc_list);
4134 entry && (next_entry = LIST_NEXT(entry, next), 1);
4135 entry = next_entry) {
4136 LIST_REMOVE(entry, next);
4140 for (entry = LIST_FIRST(&pool->free_list);
4141 entry && (next_entry = LIST_NEXT(entry, next), 1);
4142 entry = next_entry) {
4143 LIST_REMOVE(entry, next);
4148 pool->num_alloc = 0;
4150 LIST_INIT(&pool->alloc_list);
4151 LIST_INIT(&pool->free_list);
4155 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4158 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4159 uint32_t pool_offset;
4163 PMD_DRV_LOG(ERR, "Invalid parameter");
4167 pool_offset = base - pool->base;
4168 /* Lookup in alloc list */
4169 LIST_FOREACH(entry, &pool->alloc_list, next) {
4170 if (entry->base == pool_offset) {
4171 valid_entry = entry;
4172 LIST_REMOVE(entry, next);
4177 /* Not find, return */
4178 if (valid_entry == NULL) {
4179 PMD_DRV_LOG(ERR, "Failed to find entry");
4184 * Found it, move it to free list and try to merge.
4185 * In order to make merge easier, always sort it by qbase.
4186 * Find adjacent prev and last entries.
4189 LIST_FOREACH(entry, &pool->free_list, next) {
4190 if (entry->base > valid_entry->base) {
4198 /* Try to merge with next one*/
4200 /* Merge with next one */
4201 if (valid_entry->base + valid_entry->len == next->base) {
4202 next->base = valid_entry->base;
4203 next->len += valid_entry->len;
4204 rte_free(valid_entry);
4211 /* Merge with previous one */
4212 if (prev->base + prev->len == valid_entry->base) {
4213 prev->len += valid_entry->len;
4214 /* If it merge with next one, remove next node */
4216 LIST_REMOVE(valid_entry, next);
4217 rte_free(valid_entry);
4219 rte_free(valid_entry);
4225 /* Not find any entry to merge, insert */
4228 LIST_INSERT_AFTER(prev, valid_entry, next);
4229 else if (next != NULL)
4230 LIST_INSERT_BEFORE(next, valid_entry, next);
4231 else /* It's empty list, insert to head */
4232 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4235 pool->num_free += valid_entry->len;
4236 pool->num_alloc -= valid_entry->len;
4242 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4245 struct pool_entry *entry, *valid_entry;
4247 if (pool == NULL || num == 0) {
4248 PMD_DRV_LOG(ERR, "Invalid parameter");
4252 if (pool->num_free < num) {
4253 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4254 num, pool->num_free);
4259 /* Lookup in free list and find most fit one */
4260 LIST_FOREACH(entry, &pool->free_list, next) {
4261 if (entry->len >= num) {
4263 if (entry->len == num) {
4264 valid_entry = entry;
4267 if (valid_entry == NULL || valid_entry->len > entry->len)
4268 valid_entry = entry;
4272 /* Not find one to satisfy the request, return */
4273 if (valid_entry == NULL) {
4274 PMD_DRV_LOG(ERR, "No valid entry found");
4278 * The entry have equal queue number as requested,
4279 * remove it from alloc_list.
4281 if (valid_entry->len == num) {
4282 LIST_REMOVE(valid_entry, next);
4285 * The entry have more numbers than requested,
4286 * create a new entry for alloc_list and minus its
4287 * queue base and number in free_list.
4289 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4290 if (entry == NULL) {
4292 "Failed to allocate memory for resource pool");
4295 entry->base = valid_entry->base;
4297 valid_entry->base += num;
4298 valid_entry->len -= num;
4299 valid_entry = entry;
4302 /* Insert it into alloc list, not sorted */
4303 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4305 pool->num_free -= valid_entry->len;
4306 pool->num_alloc += valid_entry->len;
4308 return valid_entry->base + pool->base;
4312 * bitmap_is_subset - Check whether src2 is subset of src1
4315 bitmap_is_subset(uint8_t src1, uint8_t src2)
4317 return !((src1 ^ src2) & src2);
4320 static enum i40e_status_code
4321 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4323 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4325 /* If DCB is not supported, only default TC is supported */
4326 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4327 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4328 return I40E_NOT_SUPPORTED;
4331 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4333 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4334 hw->func_caps.enabled_tcmap, enabled_tcmap);
4335 return I40E_NOT_SUPPORTED;
4337 return I40E_SUCCESS;
4341 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4342 struct i40e_vsi_vlan_pvid_info *info)
4345 struct i40e_vsi_context ctxt;
4346 uint8_t vlan_flags = 0;
4349 if (vsi == NULL || info == NULL) {
4350 PMD_DRV_LOG(ERR, "invalid parameters");
4351 return I40E_ERR_PARAM;
4355 vsi->info.pvid = info->config.pvid;
4357 * If insert pvid is enabled, only tagged pkts are
4358 * allowed to be sent out.
4360 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4361 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4364 if (info->config.reject.tagged == 0)
4365 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4367 if (info->config.reject.untagged == 0)
4368 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4370 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4371 I40E_AQ_VSI_PVLAN_MODE_MASK);
4372 vsi->info.port_vlan_flags |= vlan_flags;
4373 vsi->info.valid_sections =
4374 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4375 memset(&ctxt, 0, sizeof(ctxt));
4376 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4377 ctxt.seid = vsi->seid;
4379 hw = I40E_VSI_TO_HW(vsi);
4380 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4381 if (ret != I40E_SUCCESS)
4382 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4388 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4390 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4392 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4394 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4395 if (ret != I40E_SUCCESS)
4399 PMD_DRV_LOG(ERR, "seid not valid");
4403 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4404 tc_bw_data.tc_valid_bits = enabled_tcmap;
4405 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4406 tc_bw_data.tc_bw_credits[i] =
4407 (enabled_tcmap & (1 << i)) ? 1 : 0;
4409 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4410 if (ret != I40E_SUCCESS) {
4411 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4415 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4416 sizeof(vsi->info.qs_handle));
4417 return I40E_SUCCESS;
4420 static enum i40e_status_code
4421 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4422 struct i40e_aqc_vsi_properties_data *info,
4423 uint8_t enabled_tcmap)
4425 enum i40e_status_code ret;
4426 int i, total_tc = 0;
4427 uint16_t qpnum_per_tc, bsf, qp_idx;
4429 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4430 if (ret != I40E_SUCCESS)
4433 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4434 if (enabled_tcmap & (1 << i))
4438 vsi->enabled_tc = enabled_tcmap;
4440 /* Number of queues per enabled TC */
4441 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4442 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4443 bsf = rte_bsf32(qpnum_per_tc);
4445 /* Adjust the queue number to actual queues that can be applied */
4446 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4447 vsi->nb_qps = qpnum_per_tc * total_tc;
4450 * Configure TC and queue mapping parameters, for enabled TC,
4451 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4452 * default queue will serve it.
4455 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4456 if (vsi->enabled_tc & (1 << i)) {
4457 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4458 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4459 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4460 qp_idx += qpnum_per_tc;
4462 info->tc_mapping[i] = 0;
4465 /* Associate queue number with VSI */
4466 if (vsi->type == I40E_VSI_SRIOV) {
4467 info->mapping_flags |=
4468 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4469 for (i = 0; i < vsi->nb_qps; i++)
4470 info->queue_mapping[i] =
4471 rte_cpu_to_le_16(vsi->base_queue + i);
4473 info->mapping_flags |=
4474 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4475 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4477 info->valid_sections |=
4478 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4480 return I40E_SUCCESS;
4484 i40e_veb_release(struct i40e_veb *veb)
4486 struct i40e_vsi *vsi;
4492 if (!TAILQ_EMPTY(&veb->head)) {
4493 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4496 /* associate_vsi field is NULL for floating VEB */
4497 if (veb->associate_vsi != NULL) {
4498 vsi = veb->associate_vsi;
4499 hw = I40E_VSI_TO_HW(vsi);
4501 vsi->uplink_seid = veb->uplink_seid;
4504 veb->associate_pf->main_vsi->floating_veb = NULL;
4505 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4508 i40e_aq_delete_element(hw, veb->seid, NULL);
4510 return I40E_SUCCESS;
4514 static struct i40e_veb *
4515 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4517 struct i40e_veb *veb;
4523 "veb setup failed, associated PF shouldn't null");
4526 hw = I40E_PF_TO_HW(pf);
4528 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4530 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4534 veb->associate_vsi = vsi;
4535 veb->associate_pf = pf;
4536 TAILQ_INIT(&veb->head);
4537 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4539 /* create floating veb if vsi is NULL */
4541 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4542 I40E_DEFAULT_TCMAP, false,
4543 &veb->seid, false, NULL);
4545 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4546 true, &veb->seid, false, NULL);
4549 if (ret != I40E_SUCCESS) {
4550 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4551 hw->aq.asq_last_status);
4554 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4556 /* get statistics index */
4557 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4558 &veb->stats_idx, NULL, NULL, NULL);
4559 if (ret != I40E_SUCCESS) {
4560 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4561 hw->aq.asq_last_status);
4564 /* Get VEB bandwidth, to be implemented */
4565 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4567 vsi->uplink_seid = veb->seid;
4576 i40e_vsi_release(struct i40e_vsi *vsi)
4580 struct i40e_vsi_list *vsi_list;
4583 struct i40e_mac_filter *f;
4584 uint16_t user_param;
4587 return I40E_SUCCESS;
4592 user_param = vsi->user_param;
4594 pf = I40E_VSI_TO_PF(vsi);
4595 hw = I40E_VSI_TO_HW(vsi);
4597 /* VSI has child to attach, release child first */
4599 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4600 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4603 i40e_veb_release(vsi->veb);
4606 if (vsi->floating_veb) {
4607 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4608 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4613 /* Remove all macvlan filters of the VSI */
4614 i40e_vsi_remove_all_macvlan_filter(vsi);
4615 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4618 if (vsi->type != I40E_VSI_MAIN &&
4619 ((vsi->type != I40E_VSI_SRIOV) ||
4620 !pf->floating_veb_list[user_param])) {
4621 /* Remove vsi from parent's sibling list */
4622 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4623 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4624 return I40E_ERR_PARAM;
4626 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4627 &vsi->sib_vsi_list, list);
4629 /* Remove all switch element of the VSI */
4630 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4631 if (ret != I40E_SUCCESS)
4632 PMD_DRV_LOG(ERR, "Failed to delete element");
4635 if ((vsi->type == I40E_VSI_SRIOV) &&
4636 pf->floating_veb_list[user_param]) {
4637 /* Remove vsi from parent's sibling list */
4638 if (vsi->parent_vsi == NULL ||
4639 vsi->parent_vsi->floating_veb == NULL) {
4640 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4641 return I40E_ERR_PARAM;
4643 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4644 &vsi->sib_vsi_list, list);
4646 /* Remove all switch element of the VSI */
4647 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4648 if (ret != I40E_SUCCESS)
4649 PMD_DRV_LOG(ERR, "Failed to delete element");
4652 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4654 if (vsi->type != I40E_VSI_SRIOV)
4655 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4658 return I40E_SUCCESS;
4662 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4664 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4665 struct i40e_aqc_remove_macvlan_element_data def_filter;
4666 struct i40e_mac_filter_info filter;
4669 if (vsi->type != I40E_VSI_MAIN)
4670 return I40E_ERR_CONFIG;
4671 memset(&def_filter, 0, sizeof(def_filter));
4672 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4674 def_filter.vlan_tag = 0;
4675 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4676 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4677 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4678 if (ret != I40E_SUCCESS) {
4679 struct i40e_mac_filter *f;
4680 struct ether_addr *mac;
4683 "Cannot remove the default macvlan filter");
4684 /* It needs to add the permanent mac into mac list */
4685 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4687 PMD_DRV_LOG(ERR, "failed to allocate memory");
4688 return I40E_ERR_NO_MEMORY;
4690 mac = &f->mac_info.mac_addr;
4691 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4693 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4694 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4699 rte_memcpy(&filter.mac_addr,
4700 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4701 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4702 return i40e_vsi_add_mac(vsi, &filter);
4706 * i40e_vsi_get_bw_config - Query VSI BW Information
4707 * @vsi: the VSI to be queried
4709 * Returns 0 on success, negative value on failure
4711 static enum i40e_status_code
4712 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4714 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4715 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4716 struct i40e_hw *hw = &vsi->adapter->hw;
4721 memset(&bw_config, 0, sizeof(bw_config));
4722 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4723 if (ret != I40E_SUCCESS) {
4724 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4725 hw->aq.asq_last_status);
4729 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4730 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4731 &ets_sla_config, NULL);
4732 if (ret != I40E_SUCCESS) {
4734 "VSI failed to get TC bandwdith configuration %u",
4735 hw->aq.asq_last_status);
4739 /* store and print out BW info */
4740 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4741 vsi->bw_info.bw_max = bw_config.max_bw;
4742 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4743 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4744 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4745 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4747 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4748 vsi->bw_info.bw_ets_share_credits[i] =
4749 ets_sla_config.share_credits[i];
4750 vsi->bw_info.bw_ets_credits[i] =
4751 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4752 /* 4 bits per TC, 4th bit is reserved */
4753 vsi->bw_info.bw_ets_max[i] =
4754 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4755 RTE_LEN2MASK(3, uint8_t));
4756 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4757 vsi->bw_info.bw_ets_share_credits[i]);
4758 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4759 vsi->bw_info.bw_ets_credits[i]);
4760 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4761 vsi->bw_info.bw_ets_max[i]);
4764 return I40E_SUCCESS;
4767 /* i40e_enable_pf_lb
4768 * @pf: pointer to the pf structure
4770 * allow loopback on pf
4773 i40e_enable_pf_lb(struct i40e_pf *pf)
4775 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4776 struct i40e_vsi_context ctxt;
4779 /* Use the FW API if FW >= v5.0 */
4780 if (hw->aq.fw_maj_ver < 5) {
4781 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4785 memset(&ctxt, 0, sizeof(ctxt));
4786 ctxt.seid = pf->main_vsi_seid;
4787 ctxt.pf_num = hw->pf_id;
4788 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4790 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4791 ret, hw->aq.asq_last_status);
4794 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4795 ctxt.info.valid_sections =
4796 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4797 ctxt.info.switch_id |=
4798 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4800 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4802 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4803 hw->aq.asq_last_status);
4808 i40e_vsi_setup(struct i40e_pf *pf,
4809 enum i40e_vsi_type type,
4810 struct i40e_vsi *uplink_vsi,
4811 uint16_t user_param)
4813 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4814 struct i40e_vsi *vsi;
4815 struct i40e_mac_filter_info filter;
4817 struct i40e_vsi_context ctxt;
4818 struct ether_addr broadcast =
4819 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4821 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4822 uplink_vsi == NULL) {
4824 "VSI setup failed, VSI link shouldn't be NULL");
4828 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4830 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4835 * 1.type is not MAIN and uplink vsi is not NULL
4836 * If uplink vsi didn't setup VEB, create one first under veb field
4837 * 2.type is SRIOV and the uplink is NULL
4838 * If floating VEB is NULL, create one veb under floating veb field
4841 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4842 uplink_vsi->veb == NULL) {
4843 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4845 if (uplink_vsi->veb == NULL) {
4846 PMD_DRV_LOG(ERR, "VEB setup failed");
4849 /* set ALLOWLOOPBACk on pf, when veb is created */
4850 i40e_enable_pf_lb(pf);
4853 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4854 pf->main_vsi->floating_veb == NULL) {
4855 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4857 if (pf->main_vsi->floating_veb == NULL) {
4858 PMD_DRV_LOG(ERR, "VEB setup failed");
4863 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4865 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4868 TAILQ_INIT(&vsi->mac_list);
4870 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4871 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4872 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4873 vsi->user_param = user_param;
4874 vsi->vlan_anti_spoof_on = 0;
4875 vsi->vlan_filter_on = 0;
4876 /* Allocate queues */
4877 switch (vsi->type) {
4878 case I40E_VSI_MAIN :
4879 vsi->nb_qps = pf->lan_nb_qps;
4881 case I40E_VSI_SRIOV :
4882 vsi->nb_qps = pf->vf_nb_qps;
4884 case I40E_VSI_VMDQ2:
4885 vsi->nb_qps = pf->vmdq_nb_qps;
4888 vsi->nb_qps = pf->fdir_nb_qps;
4894 * The filter status descriptor is reported in rx queue 0,
4895 * while the tx queue for fdir filter programming has no
4896 * such constraints, can be non-zero queues.
4897 * To simplify it, choose FDIR vsi use queue 0 pair.
4898 * To make sure it will use queue 0 pair, queue allocation
4899 * need be done before this function is called
4901 if (type != I40E_VSI_FDIR) {
4902 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4904 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4908 vsi->base_queue = ret;
4910 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4912 /* VF has MSIX interrupt in VF range, don't allocate here */
4913 if (type == I40E_VSI_MAIN) {
4914 ret = i40e_res_pool_alloc(&pf->msix_pool,
4915 RTE_MIN(vsi->nb_qps,
4916 RTE_MAX_RXTX_INTR_VEC_ID));
4918 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4920 goto fail_queue_alloc;
4922 vsi->msix_intr = ret;
4923 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4924 } else if (type != I40E_VSI_SRIOV) {
4925 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4927 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4928 goto fail_queue_alloc;
4930 vsi->msix_intr = ret;
4938 if (type == I40E_VSI_MAIN) {
4939 /* For main VSI, no need to add since it's default one */
4940 vsi->uplink_seid = pf->mac_seid;
4941 vsi->seid = pf->main_vsi_seid;
4942 /* Bind queues with specific MSIX interrupt */
4944 * Needs 2 interrupt at least, one for misc cause which will
4945 * enabled from OS side, Another for queues binding the
4946 * interrupt from device side only.
4949 /* Get default VSI parameters from hardware */
4950 memset(&ctxt, 0, sizeof(ctxt));
4951 ctxt.seid = vsi->seid;
4952 ctxt.pf_num = hw->pf_id;
4953 ctxt.uplink_seid = vsi->uplink_seid;
4955 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4956 if (ret != I40E_SUCCESS) {
4957 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4958 goto fail_msix_alloc;
4960 rte_memcpy(&vsi->info, &ctxt.info,
4961 sizeof(struct i40e_aqc_vsi_properties_data));
4962 vsi->vsi_id = ctxt.vsi_number;
4963 vsi->info.valid_sections = 0;
4965 /* Configure tc, enabled TC0 only */
4966 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4968 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4969 goto fail_msix_alloc;
4972 /* TC, queue mapping */
4973 memset(&ctxt, 0, sizeof(ctxt));
4974 vsi->info.valid_sections |=
4975 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4976 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4977 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4978 rte_memcpy(&ctxt.info, &vsi->info,
4979 sizeof(struct i40e_aqc_vsi_properties_data));
4980 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4981 I40E_DEFAULT_TCMAP);
4982 if (ret != I40E_SUCCESS) {
4984 "Failed to configure TC queue mapping");
4985 goto fail_msix_alloc;
4987 ctxt.seid = vsi->seid;
4988 ctxt.pf_num = hw->pf_id;
4989 ctxt.uplink_seid = vsi->uplink_seid;
4992 /* Update VSI parameters */
4993 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4994 if (ret != I40E_SUCCESS) {
4995 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4996 goto fail_msix_alloc;
4999 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5000 sizeof(vsi->info.tc_mapping));
5001 rte_memcpy(&vsi->info.queue_mapping,
5002 &ctxt.info.queue_mapping,
5003 sizeof(vsi->info.queue_mapping));
5004 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5005 vsi->info.valid_sections = 0;
5007 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5011 * Updating default filter settings are necessary to prevent
5012 * reception of tagged packets.
5013 * Some old firmware configurations load a default macvlan
5014 * filter which accepts both tagged and untagged packets.
5015 * The updating is to use a normal filter instead if needed.
5016 * For NVM 4.2.2 or after, the updating is not needed anymore.
5017 * The firmware with correct configurations load the default
5018 * macvlan filter which is expected and cannot be removed.
5020 i40e_update_default_filter_setting(vsi);
5021 i40e_config_qinq(hw, vsi);
5022 } else if (type == I40E_VSI_SRIOV) {
5023 memset(&ctxt, 0, sizeof(ctxt));
5025 * For other VSI, the uplink_seid equals to uplink VSI's
5026 * uplink_seid since they share same VEB
5028 if (uplink_vsi == NULL)
5029 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5031 vsi->uplink_seid = uplink_vsi->uplink_seid;
5032 ctxt.pf_num = hw->pf_id;
5033 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5034 ctxt.uplink_seid = vsi->uplink_seid;
5035 ctxt.connection_type = 0x1;
5036 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5038 /* Use the VEB configuration if FW >= v5.0 */
5039 if (hw->aq.fw_maj_ver >= 5) {
5040 /* Configure switch ID */
5041 ctxt.info.valid_sections |=
5042 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5043 ctxt.info.switch_id =
5044 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5047 /* Configure port/vlan */
5048 ctxt.info.valid_sections |=
5049 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5050 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5051 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5052 hw->func_caps.enabled_tcmap);
5053 if (ret != I40E_SUCCESS) {
5055 "Failed to configure TC queue mapping");
5056 goto fail_msix_alloc;
5059 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5060 ctxt.info.valid_sections |=
5061 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5063 * Since VSI is not created yet, only configure parameter,
5064 * will add vsi below.
5067 i40e_config_qinq(hw, vsi);
5068 } else if (type == I40E_VSI_VMDQ2) {
5069 memset(&ctxt, 0, sizeof(ctxt));
5071 * For other VSI, the uplink_seid equals to uplink VSI's
5072 * uplink_seid since they share same VEB
5074 vsi->uplink_seid = uplink_vsi->uplink_seid;
5075 ctxt.pf_num = hw->pf_id;
5077 ctxt.uplink_seid = vsi->uplink_seid;
5078 ctxt.connection_type = 0x1;
5079 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5081 ctxt.info.valid_sections |=
5082 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5083 /* user_param carries flag to enable loop back */
5085 ctxt.info.switch_id =
5086 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5087 ctxt.info.switch_id |=
5088 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5091 /* Configure port/vlan */
5092 ctxt.info.valid_sections |=
5093 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5094 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5095 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5096 I40E_DEFAULT_TCMAP);
5097 if (ret != I40E_SUCCESS) {
5099 "Failed to configure TC queue mapping");
5100 goto fail_msix_alloc;
5102 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5103 ctxt.info.valid_sections |=
5104 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5105 } else if (type == I40E_VSI_FDIR) {
5106 memset(&ctxt, 0, sizeof(ctxt));
5107 vsi->uplink_seid = uplink_vsi->uplink_seid;
5108 ctxt.pf_num = hw->pf_id;
5110 ctxt.uplink_seid = vsi->uplink_seid;
5111 ctxt.connection_type = 0x1; /* regular data port */
5112 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5113 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5114 I40E_DEFAULT_TCMAP);
5115 if (ret != I40E_SUCCESS) {
5117 "Failed to configure TC queue mapping.");
5118 goto fail_msix_alloc;
5120 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5121 ctxt.info.valid_sections |=
5122 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5124 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5125 goto fail_msix_alloc;
5128 if (vsi->type != I40E_VSI_MAIN) {
5129 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5130 if (ret != I40E_SUCCESS) {
5131 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5132 hw->aq.asq_last_status);
5133 goto fail_msix_alloc;
5135 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5136 vsi->info.valid_sections = 0;
5137 vsi->seid = ctxt.seid;
5138 vsi->vsi_id = ctxt.vsi_number;
5139 vsi->sib_vsi_list.vsi = vsi;
5140 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5141 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5142 &vsi->sib_vsi_list, list);
5144 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5145 &vsi->sib_vsi_list, list);
5149 /* MAC/VLAN configuration */
5150 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5151 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5153 ret = i40e_vsi_add_mac(vsi, &filter);
5154 if (ret != I40E_SUCCESS) {
5155 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5156 goto fail_msix_alloc;
5159 /* Get VSI BW information */
5160 i40e_vsi_get_bw_config(vsi);
5163 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5165 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5171 /* Configure vlan filter on or off */
5173 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5176 struct i40e_mac_filter *f;
5178 struct i40e_mac_filter_info *mac_filter;
5179 enum rte_mac_filter_type desired_filter;
5180 int ret = I40E_SUCCESS;
5183 /* Filter to match MAC and VLAN */
5184 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5186 /* Filter to match only MAC */
5187 desired_filter = RTE_MAC_PERFECT_MATCH;
5192 mac_filter = rte_zmalloc("mac_filter_info_data",
5193 num * sizeof(*mac_filter), 0);
5194 if (mac_filter == NULL) {
5195 PMD_DRV_LOG(ERR, "failed to allocate memory");
5196 return I40E_ERR_NO_MEMORY;
5201 /* Remove all existing mac */
5202 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5203 mac_filter[i] = f->mac_info;
5204 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5206 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5207 on ? "enable" : "disable");
5213 /* Override with new filter */
5214 for (i = 0; i < num; i++) {
5215 mac_filter[i].filter_type = desired_filter;
5216 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5218 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5219 on ? "enable" : "disable");
5225 rte_free(mac_filter);
5229 /* Configure vlan stripping on or off */
5231 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5233 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5234 struct i40e_vsi_context ctxt;
5236 int ret = I40E_SUCCESS;
5238 /* Check if it has been already on or off */
5239 if (vsi->info.valid_sections &
5240 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5242 if ((vsi->info.port_vlan_flags &
5243 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5244 return 0; /* already on */
5246 if ((vsi->info.port_vlan_flags &
5247 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5248 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5249 return 0; /* already off */
5254 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5256 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5257 vsi->info.valid_sections =
5258 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5259 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5260 vsi->info.port_vlan_flags |= vlan_flags;
5261 ctxt.seid = vsi->seid;
5262 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5263 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5265 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5266 on ? "enable" : "disable");
5272 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5274 struct rte_eth_dev_data *data = dev->data;
5278 /* Apply vlan offload setting */
5279 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5280 i40e_vlan_offload_set(dev, mask);
5282 /* Apply double-vlan setting, not implemented yet */
5284 /* Apply pvid setting */
5285 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5286 data->dev_conf.txmode.hw_vlan_insert_pvid);
5288 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5294 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5296 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5298 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5302 i40e_update_flow_control(struct i40e_hw *hw)
5304 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5305 struct i40e_link_status link_status;
5306 uint32_t rxfc = 0, txfc = 0, reg;
5310 memset(&link_status, 0, sizeof(link_status));
5311 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5312 if (ret != I40E_SUCCESS) {
5313 PMD_DRV_LOG(ERR, "Failed to get link status information");
5314 goto write_reg; /* Disable flow control */
5317 an_info = hw->phy.link_info.an_info;
5318 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5319 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5320 ret = I40E_ERR_NOT_READY;
5321 goto write_reg; /* Disable flow control */
5324 * If link auto negotiation is enabled, flow control needs to
5325 * be configured according to it
5327 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5328 case I40E_LINK_PAUSE_RXTX:
5331 hw->fc.current_mode = I40E_FC_FULL;
5333 case I40E_AQ_LINK_PAUSE_RX:
5335 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5337 case I40E_AQ_LINK_PAUSE_TX:
5339 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5342 hw->fc.current_mode = I40E_FC_NONE;
5347 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5348 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5349 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5350 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5351 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5352 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5359 i40e_pf_setup(struct i40e_pf *pf)
5361 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5362 struct i40e_filter_control_settings settings;
5363 struct i40e_vsi *vsi;
5366 /* Clear all stats counters */
5367 pf->offset_loaded = FALSE;
5368 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5369 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5370 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5371 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5373 ret = i40e_pf_get_switch_config(pf);
5374 if (ret != I40E_SUCCESS) {
5375 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5378 if (pf->flags & I40E_FLAG_FDIR) {
5379 /* make queue allocated first, let FDIR use queue pair 0*/
5380 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5381 if (ret != I40E_FDIR_QUEUE_ID) {
5383 "queue allocation fails for FDIR: ret =%d",
5385 pf->flags &= ~I40E_FLAG_FDIR;
5388 /* main VSI setup */
5389 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5391 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5392 return I40E_ERR_NOT_READY;
5396 /* Configure filter control */
5397 memset(&settings, 0, sizeof(settings));
5398 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5399 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5400 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5401 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5403 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5404 hw->func_caps.rss_table_size);
5405 return I40E_ERR_PARAM;
5407 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5408 hw->func_caps.rss_table_size);
5409 pf->hash_lut_size = hw->func_caps.rss_table_size;
5411 /* Enable ethtype and macvlan filters */
5412 settings.enable_ethtype = TRUE;
5413 settings.enable_macvlan = TRUE;
5414 ret = i40e_set_filter_control(hw, &settings);
5416 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5419 /* Update flow control according to the auto negotiation */
5420 i40e_update_flow_control(hw);
5422 return I40E_SUCCESS;
5426 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5432 * Set or clear TX Queue Disable flags,
5433 * which is required by hardware.
5435 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5436 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5438 /* Wait until the request is finished */
5439 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5440 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5441 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5442 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5443 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5449 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5450 return I40E_SUCCESS; /* already on, skip next steps */
5452 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5453 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5455 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5456 return I40E_SUCCESS; /* already off, skip next steps */
5457 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5459 /* Write the register */
5460 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5461 /* Check the result */
5462 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5463 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5464 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5466 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5467 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5470 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5471 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5475 /* Check if it is timeout */
5476 if (j >= I40E_CHK_Q_ENA_COUNT) {
5477 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5478 (on ? "enable" : "disable"), q_idx);
5479 return I40E_ERR_TIMEOUT;
5482 return I40E_SUCCESS;
5485 /* Swith on or off the tx queues */
5487 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5489 struct rte_eth_dev_data *dev_data = pf->dev_data;
5490 struct i40e_tx_queue *txq;
5491 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5495 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5496 txq = dev_data->tx_queues[i];
5497 /* Don't operate the queue if not configured or
5498 * if starting only per queue */
5499 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5502 ret = i40e_dev_tx_queue_start(dev, i);
5504 ret = i40e_dev_tx_queue_stop(dev, i);
5505 if ( ret != I40E_SUCCESS)
5509 return I40E_SUCCESS;
5513 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5518 /* Wait until the request is finished */
5519 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5520 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5521 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5522 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5523 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5528 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5529 return I40E_SUCCESS; /* Already on, skip next steps */
5530 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5532 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5533 return I40E_SUCCESS; /* Already off, skip next steps */
5534 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5537 /* Write the register */
5538 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5539 /* Check the result */
5540 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5541 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5542 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5544 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5545 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5548 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5549 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5554 /* Check if it is timeout */
5555 if (j >= I40E_CHK_Q_ENA_COUNT) {
5556 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5557 (on ? "enable" : "disable"), q_idx);
5558 return I40E_ERR_TIMEOUT;
5561 return I40E_SUCCESS;
5563 /* Switch on or off the rx queues */
5565 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5567 struct rte_eth_dev_data *dev_data = pf->dev_data;
5568 struct i40e_rx_queue *rxq;
5569 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5573 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5574 rxq = dev_data->rx_queues[i];
5575 /* Don't operate the queue if not configured or
5576 * if starting only per queue */
5577 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5580 ret = i40e_dev_rx_queue_start(dev, i);
5582 ret = i40e_dev_rx_queue_stop(dev, i);
5583 if (ret != I40E_SUCCESS)
5587 return I40E_SUCCESS;
5590 /* Switch on or off all the rx/tx queues */
5592 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5597 /* enable rx queues before enabling tx queues */
5598 ret = i40e_dev_switch_rx_queues(pf, on);
5600 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5603 ret = i40e_dev_switch_tx_queues(pf, on);
5605 /* Stop tx queues before stopping rx queues */
5606 ret = i40e_dev_switch_tx_queues(pf, on);
5608 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5611 ret = i40e_dev_switch_rx_queues(pf, on);
5617 /* Initialize VSI for TX */
5619 i40e_dev_tx_init(struct i40e_pf *pf)
5621 struct rte_eth_dev_data *data = pf->dev_data;
5623 uint32_t ret = I40E_SUCCESS;
5624 struct i40e_tx_queue *txq;
5626 for (i = 0; i < data->nb_tx_queues; i++) {
5627 txq = data->tx_queues[i];
5628 if (!txq || !txq->q_set)
5630 ret = i40e_tx_queue_init(txq);
5631 if (ret != I40E_SUCCESS)
5634 if (ret == I40E_SUCCESS)
5635 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5641 /* Initialize VSI for RX */
5643 i40e_dev_rx_init(struct i40e_pf *pf)
5645 struct rte_eth_dev_data *data = pf->dev_data;
5646 int ret = I40E_SUCCESS;
5648 struct i40e_rx_queue *rxq;
5650 i40e_pf_config_mq_rx(pf);
5651 for (i = 0; i < data->nb_rx_queues; i++) {
5652 rxq = data->rx_queues[i];
5653 if (!rxq || !rxq->q_set)
5656 ret = i40e_rx_queue_init(rxq);
5657 if (ret != I40E_SUCCESS) {
5659 "Failed to do RX queue initialization");
5663 if (ret == I40E_SUCCESS)
5664 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5671 i40e_dev_rxtx_init(struct i40e_pf *pf)
5675 err = i40e_dev_tx_init(pf);
5677 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5680 err = i40e_dev_rx_init(pf);
5682 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5690 i40e_vmdq_setup(struct rte_eth_dev *dev)
5692 struct rte_eth_conf *conf = &dev->data->dev_conf;
5693 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5694 int i, err, conf_vsis, j, loop;
5695 struct i40e_vsi *vsi;
5696 struct i40e_vmdq_info *vmdq_info;
5697 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5698 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5701 * Disable interrupt to avoid message from VF. Furthermore, it will
5702 * avoid race condition in VSI creation/destroy.
5704 i40e_pf_disable_irq0(hw);
5706 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5707 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5711 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5712 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5713 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5714 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5715 pf->max_nb_vmdq_vsi);
5719 if (pf->vmdq != NULL) {
5720 PMD_INIT_LOG(INFO, "VMDQ already configured");
5724 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5725 sizeof(*vmdq_info) * conf_vsis, 0);
5727 if (pf->vmdq == NULL) {
5728 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5732 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5734 /* Create VMDQ VSI */
5735 for (i = 0; i < conf_vsis; i++) {
5736 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5737 vmdq_conf->enable_loop_back);
5739 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5743 vmdq_info = &pf->vmdq[i];
5745 vmdq_info->vsi = vsi;
5747 pf->nb_cfg_vmdq_vsi = conf_vsis;
5749 /* Configure Vlan */
5750 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5751 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5752 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5753 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5754 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5755 vmdq_conf->pool_map[i].vlan_id, j);
5757 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5758 vmdq_conf->pool_map[i].vlan_id);
5760 PMD_INIT_LOG(ERR, "Failed to add vlan");
5768 i40e_pf_enable_irq0(hw);
5773 for (i = 0; i < conf_vsis; i++)
5774 if (pf->vmdq[i].vsi == NULL)
5777 i40e_vsi_release(pf->vmdq[i].vsi);
5781 i40e_pf_enable_irq0(hw);
5786 i40e_stat_update_32(struct i40e_hw *hw,
5794 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5798 if (new_data >= *offset)
5799 *stat = (uint64_t)(new_data - *offset);
5801 *stat = (uint64_t)((new_data +
5802 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5806 i40e_stat_update_48(struct i40e_hw *hw,
5815 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5816 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5817 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5822 if (new_data >= *offset)
5823 *stat = new_data - *offset;
5825 *stat = (uint64_t)((new_data +
5826 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5828 *stat &= I40E_48_BIT_MASK;
5833 i40e_pf_disable_irq0(struct i40e_hw *hw)
5835 /* Disable all interrupt types */
5836 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5837 I40E_WRITE_FLUSH(hw);
5842 i40e_pf_enable_irq0(struct i40e_hw *hw)
5844 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5845 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5846 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5847 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5848 I40E_WRITE_FLUSH(hw);
5852 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5854 /* read pending request and disable first */
5855 i40e_pf_disable_irq0(hw);
5856 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5857 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5858 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5861 /* Link no queues with irq0 */
5862 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5863 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5867 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5869 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5873 uint32_t index, offset, val;
5878 * Try to find which VF trigger a reset, use absolute VF id to access
5879 * since the reg is global register.
5881 for (i = 0; i < pf->vf_num; i++) {
5882 abs_vf_id = hw->func_caps.vf_base_id + i;
5883 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5884 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5885 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5886 /* VFR event occurred */
5887 if (val & (0x1 << offset)) {
5890 /* Clear the event first */
5891 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5893 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5895 * Only notify a VF reset event occurred,
5896 * don't trigger another SW reset
5898 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5899 if (ret != I40E_SUCCESS)
5900 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5906 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5911 for (i = 0; i < pf->vf_num; i++)
5912 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5916 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5918 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5919 struct i40e_arq_event_info info;
5920 uint16_t pending, opcode;
5923 info.buf_len = I40E_AQ_BUF_SZ;
5924 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5925 if (!info.msg_buf) {
5926 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5932 ret = i40e_clean_arq_element(hw, &info, &pending);
5934 if (ret != I40E_SUCCESS) {
5936 "Failed to read msg from AdminQ, aq_err: %u",
5937 hw->aq.asq_last_status);
5940 opcode = rte_le_to_cpu_16(info.desc.opcode);
5943 case i40e_aqc_opc_send_msg_to_pf:
5944 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5945 i40e_pf_host_handle_vf_msg(dev,
5946 rte_le_to_cpu_16(info.desc.retval),
5947 rte_le_to_cpu_32(info.desc.cookie_high),
5948 rte_le_to_cpu_32(info.desc.cookie_low),
5952 case i40e_aqc_opc_get_link_status:
5953 ret = i40e_dev_link_update(dev, 0);
5955 _rte_eth_dev_callback_process(dev,
5956 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5959 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5964 rte_free(info.msg_buf);
5968 * Interrupt handler triggered by NIC for handling
5969 * specific interrupt.
5972 * Pointer to interrupt handle.
5974 * The address of parameter (struct rte_eth_dev *) regsitered before.
5980 i40e_dev_interrupt_handler(void *param)
5982 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5983 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5986 /* Disable interrupt */
5987 i40e_pf_disable_irq0(hw);
5989 /* read out interrupt causes */
5990 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5992 /* No interrupt event indicated */
5993 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5994 PMD_DRV_LOG(INFO, "No interrupt event");
5997 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5998 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5999 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6000 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6001 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6002 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6003 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6004 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6005 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6006 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6007 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6008 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6009 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6010 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6012 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6013 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6014 i40e_dev_handle_vfr_event(dev);
6016 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6017 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6018 i40e_dev_handle_aq_msg(dev);
6022 /* Enable interrupt */
6023 i40e_pf_enable_irq0(hw);
6024 rte_intr_enable(dev->intr_handle);
6028 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6029 struct i40e_macvlan_filter *filter,
6032 int ele_num, ele_buff_size;
6033 int num, actual_num, i;
6035 int ret = I40E_SUCCESS;
6036 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6037 struct i40e_aqc_add_macvlan_element_data *req_list;
6039 if (filter == NULL || total == 0)
6040 return I40E_ERR_PARAM;
6041 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6042 ele_buff_size = hw->aq.asq_buf_size;
6044 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6045 if (req_list == NULL) {
6046 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6047 return I40E_ERR_NO_MEMORY;
6052 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6053 memset(req_list, 0, ele_buff_size);
6055 for (i = 0; i < actual_num; i++) {
6056 rte_memcpy(req_list[i].mac_addr,
6057 &filter[num + i].macaddr, ETH_ADDR_LEN);
6058 req_list[i].vlan_tag =
6059 rte_cpu_to_le_16(filter[num + i].vlan_id);
6061 switch (filter[num + i].filter_type) {
6062 case RTE_MAC_PERFECT_MATCH:
6063 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6064 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6066 case RTE_MACVLAN_PERFECT_MATCH:
6067 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6069 case RTE_MAC_HASH_MATCH:
6070 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6071 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6073 case RTE_MACVLAN_HASH_MATCH:
6074 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6077 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6078 ret = I40E_ERR_PARAM;
6082 req_list[i].queue_number = 0;
6084 req_list[i].flags = rte_cpu_to_le_16(flags);
6087 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6089 if (ret != I40E_SUCCESS) {
6090 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6094 } while (num < total);
6102 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6103 struct i40e_macvlan_filter *filter,
6106 int ele_num, ele_buff_size;
6107 int num, actual_num, i;
6109 int ret = I40E_SUCCESS;
6110 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6111 struct i40e_aqc_remove_macvlan_element_data *req_list;
6113 if (filter == NULL || total == 0)
6114 return I40E_ERR_PARAM;
6116 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6117 ele_buff_size = hw->aq.asq_buf_size;
6119 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6120 if (req_list == NULL) {
6121 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6122 return I40E_ERR_NO_MEMORY;
6127 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6128 memset(req_list, 0, ele_buff_size);
6130 for (i = 0; i < actual_num; i++) {
6131 rte_memcpy(req_list[i].mac_addr,
6132 &filter[num + i].macaddr, ETH_ADDR_LEN);
6133 req_list[i].vlan_tag =
6134 rte_cpu_to_le_16(filter[num + i].vlan_id);
6136 switch (filter[num + i].filter_type) {
6137 case RTE_MAC_PERFECT_MATCH:
6138 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6139 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6141 case RTE_MACVLAN_PERFECT_MATCH:
6142 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6144 case RTE_MAC_HASH_MATCH:
6145 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6146 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6148 case RTE_MACVLAN_HASH_MATCH:
6149 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6152 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6153 ret = I40E_ERR_PARAM;
6156 req_list[i].flags = rte_cpu_to_le_16(flags);
6159 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6161 if (ret != I40E_SUCCESS) {
6162 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6166 } while (num < total);
6173 /* Find out specific MAC filter */
6174 static struct i40e_mac_filter *
6175 i40e_find_mac_filter(struct i40e_vsi *vsi,
6176 struct ether_addr *macaddr)
6178 struct i40e_mac_filter *f;
6180 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6181 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6189 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6192 uint32_t vid_idx, vid_bit;
6194 if (vlan_id > ETH_VLAN_ID_MAX)
6197 vid_idx = I40E_VFTA_IDX(vlan_id);
6198 vid_bit = I40E_VFTA_BIT(vlan_id);
6200 if (vsi->vfta[vid_idx] & vid_bit)
6207 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6208 uint16_t vlan_id, bool on)
6210 uint32_t vid_idx, vid_bit;
6212 vid_idx = I40E_VFTA_IDX(vlan_id);
6213 vid_bit = I40E_VFTA_BIT(vlan_id);
6216 vsi->vfta[vid_idx] |= vid_bit;
6218 vsi->vfta[vid_idx] &= ~vid_bit;
6222 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6223 uint16_t vlan_id, bool on)
6225 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6226 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6229 if (vlan_id > ETH_VLAN_ID_MAX)
6232 i40e_store_vlan_filter(vsi, vlan_id, on);
6234 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6237 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6240 ret = i40e_aq_add_vlan(hw, vsi->seid,
6241 &vlan_data, 1, NULL);
6242 if (ret != I40E_SUCCESS)
6243 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6245 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6246 &vlan_data, 1, NULL);
6247 if (ret != I40E_SUCCESS)
6249 "Failed to remove vlan filter");
6254 * Find all vlan options for specific mac addr,
6255 * return with actual vlan found.
6258 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6259 struct i40e_macvlan_filter *mv_f,
6260 int num, struct ether_addr *addr)
6266 * Not to use i40e_find_vlan_filter to decrease the loop time,
6267 * although the code looks complex.
6269 if (num < vsi->vlan_num)
6270 return I40E_ERR_PARAM;
6273 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6275 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6276 if (vsi->vfta[j] & (1 << k)) {
6279 "vlan number doesn't match");
6280 return I40E_ERR_PARAM;
6282 rte_memcpy(&mv_f[i].macaddr,
6283 addr, ETH_ADDR_LEN);
6285 j * I40E_UINT32_BIT_SIZE + k;
6291 return I40E_SUCCESS;
6295 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6296 struct i40e_macvlan_filter *mv_f,
6301 struct i40e_mac_filter *f;
6303 if (num < vsi->mac_num)
6304 return I40E_ERR_PARAM;
6306 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6308 PMD_DRV_LOG(ERR, "buffer number not match");
6309 return I40E_ERR_PARAM;
6311 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6313 mv_f[i].vlan_id = vlan;
6314 mv_f[i].filter_type = f->mac_info.filter_type;
6318 return I40E_SUCCESS;
6322 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6325 struct i40e_mac_filter *f;
6326 struct i40e_macvlan_filter *mv_f;
6327 int ret = I40E_SUCCESS;
6329 if (vsi == NULL || vsi->mac_num == 0)
6330 return I40E_ERR_PARAM;
6332 /* Case that no vlan is set */
6333 if (vsi->vlan_num == 0)
6336 num = vsi->mac_num * vsi->vlan_num;
6338 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6340 PMD_DRV_LOG(ERR, "failed to allocate memory");
6341 return I40E_ERR_NO_MEMORY;
6345 if (vsi->vlan_num == 0) {
6346 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6347 rte_memcpy(&mv_f[i].macaddr,
6348 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6349 mv_f[i].filter_type = f->mac_info.filter_type;
6350 mv_f[i].vlan_id = 0;
6354 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6355 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6356 vsi->vlan_num, &f->mac_info.mac_addr);
6357 if (ret != I40E_SUCCESS)
6359 for (j = i; j < i + vsi->vlan_num; j++)
6360 mv_f[j].filter_type = f->mac_info.filter_type;
6365 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6373 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6375 struct i40e_macvlan_filter *mv_f;
6377 int ret = I40E_SUCCESS;
6379 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6380 return I40E_ERR_PARAM;
6382 /* If it's already set, just return */
6383 if (i40e_find_vlan_filter(vsi,vlan))
6384 return I40E_SUCCESS;
6386 mac_num = vsi->mac_num;
6389 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6390 return I40E_ERR_PARAM;
6393 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6396 PMD_DRV_LOG(ERR, "failed to allocate memory");
6397 return I40E_ERR_NO_MEMORY;
6400 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6402 if (ret != I40E_SUCCESS)
6405 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6407 if (ret != I40E_SUCCESS)
6410 i40e_set_vlan_filter(vsi, vlan, 1);
6420 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6422 struct i40e_macvlan_filter *mv_f;
6424 int ret = I40E_SUCCESS;
6427 * Vlan 0 is the generic filter for untagged packets
6428 * and can't be removed.
6430 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6431 return I40E_ERR_PARAM;
6433 /* If can't find it, just return */
6434 if (!i40e_find_vlan_filter(vsi, vlan))
6435 return I40E_ERR_PARAM;
6437 mac_num = vsi->mac_num;
6440 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6441 return I40E_ERR_PARAM;
6444 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6447 PMD_DRV_LOG(ERR, "failed to allocate memory");
6448 return I40E_ERR_NO_MEMORY;
6451 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6453 if (ret != I40E_SUCCESS)
6456 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6458 if (ret != I40E_SUCCESS)
6461 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6462 if (vsi->vlan_num == 1) {
6463 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6464 if (ret != I40E_SUCCESS)
6467 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6468 if (ret != I40E_SUCCESS)
6472 i40e_set_vlan_filter(vsi, vlan, 0);
6482 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6484 struct i40e_mac_filter *f;
6485 struct i40e_macvlan_filter *mv_f;
6486 int i, vlan_num = 0;
6487 int ret = I40E_SUCCESS;
6489 /* If it's add and we've config it, return */
6490 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6492 return I40E_SUCCESS;
6493 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6494 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6497 * If vlan_num is 0, that's the first time to add mac,
6498 * set mask for vlan_id 0.
6500 if (vsi->vlan_num == 0) {
6501 i40e_set_vlan_filter(vsi, 0, 1);
6504 vlan_num = vsi->vlan_num;
6505 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6506 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6509 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6511 PMD_DRV_LOG(ERR, "failed to allocate memory");
6512 return I40E_ERR_NO_MEMORY;
6515 for (i = 0; i < vlan_num; i++) {
6516 mv_f[i].filter_type = mac_filter->filter_type;
6517 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6521 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6522 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6523 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6524 &mac_filter->mac_addr);
6525 if (ret != I40E_SUCCESS)
6529 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6530 if (ret != I40E_SUCCESS)
6533 /* Add the mac addr into mac list */
6534 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6536 PMD_DRV_LOG(ERR, "failed to allocate memory");
6537 ret = I40E_ERR_NO_MEMORY;
6540 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6542 f->mac_info.filter_type = mac_filter->filter_type;
6543 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6554 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6556 struct i40e_mac_filter *f;
6557 struct i40e_macvlan_filter *mv_f;
6559 enum rte_mac_filter_type filter_type;
6560 int ret = I40E_SUCCESS;
6562 /* Can't find it, return an error */
6563 f = i40e_find_mac_filter(vsi, addr);
6565 return I40E_ERR_PARAM;
6567 vlan_num = vsi->vlan_num;
6568 filter_type = f->mac_info.filter_type;
6569 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6570 filter_type == RTE_MACVLAN_HASH_MATCH) {
6571 if (vlan_num == 0) {
6572 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6573 return I40E_ERR_PARAM;
6575 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6576 filter_type == RTE_MAC_HASH_MATCH)
6579 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6581 PMD_DRV_LOG(ERR, "failed to allocate memory");
6582 return I40E_ERR_NO_MEMORY;
6585 for (i = 0; i < vlan_num; i++) {
6586 mv_f[i].filter_type = filter_type;
6587 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6590 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6591 filter_type == RTE_MACVLAN_HASH_MATCH) {
6592 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6593 if (ret != I40E_SUCCESS)
6597 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6598 if (ret != I40E_SUCCESS)
6601 /* Remove the mac addr into mac list */
6602 TAILQ_REMOVE(&vsi->mac_list, f, next);
6612 /* Configure hash enable flags for RSS */
6614 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6621 if (flags & ETH_RSS_FRAG_IPV4)
6622 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6623 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6624 if (type == I40E_MAC_X722) {
6625 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6626 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6628 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6630 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6631 if (type == I40E_MAC_X722) {
6632 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6633 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6634 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6636 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6638 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6639 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6640 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6641 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6642 if (flags & ETH_RSS_FRAG_IPV6)
6643 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6644 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6645 if (type == I40E_MAC_X722) {
6646 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6647 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6649 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6651 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6652 if (type == I40E_MAC_X722) {
6653 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6654 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6655 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6657 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6659 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6660 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6661 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6662 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6663 if (flags & ETH_RSS_L2_PAYLOAD)
6664 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6669 /* Parse the hash enable flags */
6671 i40e_parse_hena(uint64_t flags)
6673 uint64_t rss_hf = 0;
6677 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6678 rss_hf |= ETH_RSS_FRAG_IPV4;
6679 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6680 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6681 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6682 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6683 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6684 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6685 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6686 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6687 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6688 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6689 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6690 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6691 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6692 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6693 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6694 rss_hf |= ETH_RSS_FRAG_IPV6;
6695 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6696 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6697 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6698 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6699 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6700 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6701 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6702 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6703 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6704 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6705 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6706 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6707 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6708 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6709 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6710 rss_hf |= ETH_RSS_L2_PAYLOAD;
6717 i40e_pf_disable_rss(struct i40e_pf *pf)
6719 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6721 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6722 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6723 I40E_WRITE_FLUSH(hw);
6727 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6729 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6730 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6733 if (!key || key_len == 0) {
6734 PMD_DRV_LOG(DEBUG, "No key to be configured");
6736 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6738 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6742 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6743 struct i40e_aqc_get_set_rss_key_data *key_dw =
6744 (struct i40e_aqc_get_set_rss_key_data *)key;
6746 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6748 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6750 uint32_t *hash_key = (uint32_t *)key;
6753 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6754 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6755 I40E_WRITE_FLUSH(hw);
6762 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6764 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6765 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6768 if (!key || !key_len)
6771 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6772 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6773 (struct i40e_aqc_get_set_rss_key_data *)key);
6775 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6779 uint32_t *key_dw = (uint32_t *)key;
6782 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6783 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6785 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6791 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6797 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6798 rss_conf->rss_key_len);
6802 hena = i40e_config_hena(rss_conf->rss_hf, hw->mac.type);
6803 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6804 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6805 I40E_WRITE_FLUSH(hw);
6811 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6812 struct rte_eth_rss_conf *rss_conf)
6814 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6815 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6816 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6819 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6820 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6821 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6822 ? I40E_RSS_HENA_ALL_X722
6823 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6824 if (rss_hf != 0) /* Enable RSS */
6826 return 0; /* Nothing to do */
6829 if (rss_hf == 0) /* Disable RSS */
6832 return i40e_hw_rss_hash_set(pf, rss_conf);
6836 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6837 struct rte_eth_rss_conf *rss_conf)
6839 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6840 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6843 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6844 &rss_conf->rss_key_len);
6846 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6847 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6848 rss_conf->rss_hf = i40e_parse_hena(hena);
6854 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6856 switch (filter_type) {
6857 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6858 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6860 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6861 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6863 case RTE_TUNNEL_FILTER_IMAC_TENID:
6864 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6866 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6867 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6869 case ETH_TUNNEL_FILTER_IMAC:
6870 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6872 case ETH_TUNNEL_FILTER_OIP:
6873 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6875 case ETH_TUNNEL_FILTER_IIP:
6876 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6879 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6886 /* Convert tunnel filter structure */
6888 i40e_tunnel_filter_convert(
6889 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6890 struct i40e_tunnel_filter *tunnel_filter)
6892 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6893 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6894 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6895 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6896 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6897 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6898 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6899 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6900 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6902 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6903 tunnel_filter->input.flags = cld_filter->element.flags;
6904 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6905 tunnel_filter->queue = cld_filter->element.queue_number;
6906 rte_memcpy(tunnel_filter->input.general_fields,
6907 cld_filter->general_fields,
6908 sizeof(cld_filter->general_fields));
6913 /* Check if there exists the tunnel filter */
6914 struct i40e_tunnel_filter *
6915 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6916 const struct i40e_tunnel_filter_input *input)
6920 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6924 return tunnel_rule->hash_map[ret];
6927 /* Add a tunnel filter into the SW list */
6929 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6930 struct i40e_tunnel_filter *tunnel_filter)
6932 struct i40e_tunnel_rule *rule = &pf->tunnel;
6935 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6938 "Failed to insert tunnel filter to hash table %d!",
6942 rule->hash_map[ret] = tunnel_filter;
6944 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6949 /* Delete a tunnel filter from the SW list */
6951 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6952 struct i40e_tunnel_filter_input *input)
6954 struct i40e_tunnel_rule *rule = &pf->tunnel;
6955 struct i40e_tunnel_filter *tunnel_filter;
6958 ret = rte_hash_del_key(rule->hash_table, input);
6961 "Failed to delete tunnel filter to hash table %d!",
6965 tunnel_filter = rule->hash_map[ret];
6966 rule->hash_map[ret] = NULL;
6968 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6969 rte_free(tunnel_filter);
6975 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6976 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6981 uint8_t i, tun_type = 0;
6982 /* internal varialbe to convert ipv6 byte order */
6983 uint32_t convert_ipv6[4];
6985 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6986 struct i40e_vsi *vsi = pf->main_vsi;
6987 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6988 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6989 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6990 struct i40e_tunnel_filter *tunnel, *node;
6991 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6993 cld_filter = rte_zmalloc("tunnel_filter",
6994 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6997 if (NULL == cld_filter) {
6998 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7001 pfilter = cld_filter;
7003 ether_addr_copy(&tunnel_filter->outer_mac,
7004 (struct ether_addr *)&pfilter->element.outer_mac);
7005 ether_addr_copy(&tunnel_filter->inner_mac,
7006 (struct ether_addr *)&pfilter->element.inner_mac);
7008 pfilter->element.inner_vlan =
7009 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7010 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7011 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7012 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7013 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7014 &rte_cpu_to_le_32(ipv4_addr),
7015 sizeof(pfilter->element.ipaddr.v4.data));
7017 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7018 for (i = 0; i < 4; i++) {
7020 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7022 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7024 sizeof(pfilter->element.ipaddr.v6.data));
7027 /* check tunneled type */
7028 switch (tunnel_filter->tunnel_type) {
7029 case RTE_TUNNEL_TYPE_VXLAN:
7030 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7032 case RTE_TUNNEL_TYPE_NVGRE:
7033 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7035 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7036 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7039 /* Other tunnel types is not supported. */
7040 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7041 rte_free(cld_filter);
7045 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7046 &pfilter->element.flags);
7048 rte_free(cld_filter);
7052 pfilter->element.flags |= rte_cpu_to_le_16(
7053 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7054 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7055 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7056 pfilter->element.queue_number =
7057 rte_cpu_to_le_16(tunnel_filter->queue_id);
7059 /* Check if there is the filter in SW list */
7060 memset(&check_filter, 0, sizeof(check_filter));
7061 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7062 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7064 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7068 if (!add && !node) {
7069 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7074 ret = i40e_aq_add_cloud_filters(hw,
7075 vsi->seid, &cld_filter->element, 1);
7077 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7080 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7081 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7082 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7084 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7085 &cld_filter->element, 1);
7087 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7090 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7093 rte_free(cld_filter);
7097 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7098 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7099 #define I40E_TR_GENEVE_KEY_MASK 0x8
7100 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7101 #define I40E_TR_GRE_KEY_MASK 0x400
7102 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7103 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7106 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7108 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7109 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7110 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7111 enum i40e_status_code status = I40E_SUCCESS;
7113 memset(&filter_replace, 0,
7114 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7115 memset(&filter_replace_buf, 0,
7116 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7118 /* create L1 filter */
7119 filter_replace.old_filter_type =
7120 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7121 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7122 filter_replace.tr_bit = 0;
7124 /* Prepare the buffer, 3 entries */
7125 filter_replace_buf.data[0] =
7126 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7127 filter_replace_buf.data[0] |=
7128 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7129 filter_replace_buf.data[2] = 0xFF;
7130 filter_replace_buf.data[3] = 0xFF;
7131 filter_replace_buf.data[4] =
7132 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7133 filter_replace_buf.data[4] |=
7134 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7135 filter_replace_buf.data[7] = 0xF0;
7136 filter_replace_buf.data[8]
7137 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7138 filter_replace_buf.data[8] |=
7139 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7140 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7141 I40E_TR_GENEVE_KEY_MASK |
7142 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7143 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7144 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7145 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7147 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7148 &filter_replace_buf);
7153 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7155 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7156 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7157 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7158 enum i40e_status_code status = I40E_SUCCESS;
7161 memset(&filter_replace, 0,
7162 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7163 memset(&filter_replace_buf, 0,
7164 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7165 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7166 I40E_AQC_MIRROR_CLOUD_FILTER;
7167 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7168 filter_replace.new_filter_type =
7169 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7170 /* Prepare the buffer, 2 entries */
7171 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7172 filter_replace_buf.data[0] |=
7173 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7174 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7175 filter_replace_buf.data[4] |=
7176 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7177 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7178 &filter_replace_buf);
7183 memset(&filter_replace, 0,
7184 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7185 memset(&filter_replace_buf, 0,
7186 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7188 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7189 I40E_AQC_MIRROR_CLOUD_FILTER;
7190 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7191 filter_replace.new_filter_type =
7192 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7193 /* Prepare the buffer, 2 entries */
7194 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7195 filter_replace_buf.data[0] |=
7196 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7197 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7198 filter_replace_buf.data[4] |=
7199 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7201 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7202 &filter_replace_buf);
7207 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7208 struct i40e_tunnel_filter_conf *tunnel_filter,
7213 uint8_t i, tun_type = 0;
7214 /* internal variable to convert ipv6 byte order */
7215 uint32_t convert_ipv6[4];
7217 struct i40e_pf_vf *vf = NULL;
7218 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7219 struct i40e_vsi *vsi;
7220 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7221 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7222 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7223 struct i40e_tunnel_filter *tunnel, *node;
7224 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7226 bool big_buffer = 0;
7228 cld_filter = rte_zmalloc("tunnel_filter",
7229 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7232 if (cld_filter == NULL) {
7233 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7236 pfilter = cld_filter;
7238 ether_addr_copy(&tunnel_filter->outer_mac,
7239 (struct ether_addr *)&pfilter->element.outer_mac);
7240 ether_addr_copy(&tunnel_filter->inner_mac,
7241 (struct ether_addr *)&pfilter->element.inner_mac);
7243 pfilter->element.inner_vlan =
7244 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7245 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7246 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7247 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7248 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7249 &rte_cpu_to_le_32(ipv4_addr),
7250 sizeof(pfilter->element.ipaddr.v4.data));
7252 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7253 for (i = 0; i < 4; i++) {
7255 rte_cpu_to_le_32(rte_be_to_cpu_32(
7256 tunnel_filter->ip_addr.ipv6_addr[i]));
7258 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7260 sizeof(pfilter->element.ipaddr.v6.data));
7263 /* check tunneled type */
7264 switch (tunnel_filter->tunnel_type) {
7265 case I40E_TUNNEL_TYPE_VXLAN:
7266 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7268 case I40E_TUNNEL_TYPE_NVGRE:
7269 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7271 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7272 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7274 case I40E_TUNNEL_TYPE_MPLSoUDP:
7275 if (!pf->mpls_replace_flag) {
7276 i40e_replace_mpls_l1_filter(pf);
7277 i40e_replace_mpls_cloud_filter(pf);
7278 pf->mpls_replace_flag = 1;
7280 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7281 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7283 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7284 (teid_le & 0xF) << 12;
7285 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7288 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7290 case I40E_TUNNEL_TYPE_MPLSoGRE:
7291 if (!pf->mpls_replace_flag) {
7292 i40e_replace_mpls_l1_filter(pf);
7293 i40e_replace_mpls_cloud_filter(pf);
7294 pf->mpls_replace_flag = 1;
7296 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7297 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7299 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7300 (teid_le & 0xF) << 12;
7301 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7304 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7306 case I40E_TUNNEL_TYPE_QINQ:
7307 if (!pf->qinq_replace_flag) {
7308 ret = i40e_cloud_filter_qinq_create(pf);
7311 "QinQ tunnel filter already created.");
7312 pf->qinq_replace_flag = 1;
7314 /* Add in the General fields the values of
7315 * the Outer and Inner VLAN
7316 * Big Buffer should be set, see changes in
7317 * i40e_aq_add_cloud_filters
7319 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7320 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7324 /* Other tunnel types is not supported. */
7325 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7326 rte_free(cld_filter);
7330 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7331 pfilter->element.flags =
7332 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7333 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7334 pfilter->element.flags =
7335 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7336 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7337 pfilter->element.flags |=
7338 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7340 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7341 &pfilter->element.flags);
7343 rte_free(cld_filter);
7348 pfilter->element.flags |= rte_cpu_to_le_16(
7349 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7350 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7351 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7352 pfilter->element.queue_number =
7353 rte_cpu_to_le_16(tunnel_filter->queue_id);
7355 if (!tunnel_filter->is_to_vf)
7358 if (tunnel_filter->vf_id >= pf->vf_num) {
7359 PMD_DRV_LOG(ERR, "Invalid argument.");
7362 vf = &pf->vfs[tunnel_filter->vf_id];
7366 /* Check if there is the filter in SW list */
7367 memset(&check_filter, 0, sizeof(check_filter));
7368 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7369 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7370 check_filter.vf_id = tunnel_filter->vf_id;
7371 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7373 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7377 if (!add && !node) {
7378 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7384 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7385 vsi->seid, cld_filter, 1);
7387 ret = i40e_aq_add_cloud_filters(hw,
7388 vsi->seid, &cld_filter->element, 1);
7390 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7393 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7394 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7395 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7398 ret = i40e_aq_remove_cloud_filters_big_buffer(
7399 hw, vsi->seid, cld_filter, 1);
7401 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7402 &cld_filter->element, 1);
7404 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7407 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7410 rte_free(cld_filter);
7415 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7419 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7420 if (pf->vxlan_ports[i] == port)
7428 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7432 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7434 idx = i40e_get_vxlan_port_idx(pf, port);
7436 /* Check if port already exists */
7438 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7442 /* Now check if there is space to add the new port */
7443 idx = i40e_get_vxlan_port_idx(pf, 0);
7446 "Maximum number of UDP ports reached, not adding port %d",
7451 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7454 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7458 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7461 /* New port: add it and mark its index in the bitmap */
7462 pf->vxlan_ports[idx] = port;
7463 pf->vxlan_bitmap |= (1 << idx);
7465 if (!(pf->flags & I40E_FLAG_VXLAN))
7466 pf->flags |= I40E_FLAG_VXLAN;
7472 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7475 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7477 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7478 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7482 idx = i40e_get_vxlan_port_idx(pf, port);
7485 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7489 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7490 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7494 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7497 pf->vxlan_ports[idx] = 0;
7498 pf->vxlan_bitmap &= ~(1 << idx);
7500 if (!pf->vxlan_bitmap)
7501 pf->flags &= ~I40E_FLAG_VXLAN;
7506 /* Add UDP tunneling port */
7508 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7509 struct rte_eth_udp_tunnel *udp_tunnel)
7512 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7514 if (udp_tunnel == NULL)
7517 switch (udp_tunnel->prot_type) {
7518 case RTE_TUNNEL_TYPE_VXLAN:
7519 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7522 case RTE_TUNNEL_TYPE_GENEVE:
7523 case RTE_TUNNEL_TYPE_TEREDO:
7524 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7529 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7537 /* Remove UDP tunneling port */
7539 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7540 struct rte_eth_udp_tunnel *udp_tunnel)
7543 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7545 if (udp_tunnel == NULL)
7548 switch (udp_tunnel->prot_type) {
7549 case RTE_TUNNEL_TYPE_VXLAN:
7550 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7552 case RTE_TUNNEL_TYPE_GENEVE:
7553 case RTE_TUNNEL_TYPE_TEREDO:
7554 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7558 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7566 /* Calculate the maximum number of contiguous PF queues that are configured */
7568 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7570 struct rte_eth_dev_data *data = pf->dev_data;
7572 struct i40e_rx_queue *rxq;
7575 for (i = 0; i < pf->lan_nb_qps; i++) {
7576 rxq = data->rx_queues[i];
7577 if (rxq && rxq->q_set)
7588 i40e_pf_config_rss(struct i40e_pf *pf)
7590 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7591 struct rte_eth_rss_conf rss_conf;
7592 uint32_t i, lut = 0;
7596 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7597 * It's necessary to calculate the actual PF queues that are configured.
7599 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7600 num = i40e_pf_calc_configured_queues_num(pf);
7602 num = pf->dev_data->nb_rx_queues;
7604 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7605 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7609 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7613 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7616 lut = (lut << 8) | (j & ((0x1 <<
7617 hw->func_caps.rss_table_entry_width) - 1));
7619 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7622 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7623 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7624 i40e_pf_disable_rss(pf);
7627 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7628 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7629 /* Random default keys */
7630 static uint32_t rss_key_default[] = {0x6b793944,
7631 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7632 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7633 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7635 rss_conf.rss_key = (uint8_t *)rss_key_default;
7636 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7640 return i40e_hw_rss_hash_set(pf, &rss_conf);
7644 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7645 struct rte_eth_tunnel_filter_conf *filter)
7647 if (pf == NULL || filter == NULL) {
7648 PMD_DRV_LOG(ERR, "Invalid parameter");
7652 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7653 PMD_DRV_LOG(ERR, "Invalid queue ID");
7657 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7658 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7662 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7663 (is_zero_ether_addr(&filter->outer_mac))) {
7664 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7668 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7669 (is_zero_ether_addr(&filter->inner_mac))) {
7670 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7677 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7678 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7680 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7685 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7686 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7689 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7690 } else if (len == 4) {
7691 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7693 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7698 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7705 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7706 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7712 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7719 switch (cfg->cfg_type) {
7720 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7721 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7724 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7732 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7733 enum rte_filter_op filter_op,
7736 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7737 int ret = I40E_ERR_PARAM;
7739 switch (filter_op) {
7740 case RTE_ETH_FILTER_SET:
7741 ret = i40e_dev_global_config_set(hw,
7742 (struct rte_eth_global_cfg *)arg);
7745 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7753 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7754 enum rte_filter_op filter_op,
7757 struct rte_eth_tunnel_filter_conf *filter;
7758 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7759 int ret = I40E_SUCCESS;
7761 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7763 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7764 return I40E_ERR_PARAM;
7766 switch (filter_op) {
7767 case RTE_ETH_FILTER_NOP:
7768 if (!(pf->flags & I40E_FLAG_VXLAN))
7769 ret = I40E_NOT_SUPPORTED;
7771 case RTE_ETH_FILTER_ADD:
7772 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7774 case RTE_ETH_FILTER_DELETE:
7775 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7778 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7779 ret = I40E_ERR_PARAM;
7787 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7790 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7793 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7794 ret = i40e_pf_config_rss(pf);
7796 i40e_pf_disable_rss(pf);
7801 /* Get the symmetric hash enable configurations per port */
7803 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7805 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7807 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7810 /* Set the symmetric hash enable configurations per port */
7812 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7814 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7817 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7819 "Symmetric hash has already been enabled");
7822 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7824 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7826 "Symmetric hash has already been disabled");
7829 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7831 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7832 I40E_WRITE_FLUSH(hw);
7836 * Get global configurations of hash function type and symmetric hash enable
7837 * per flow type (pctype). Note that global configuration means it affects all
7838 * the ports on the same NIC.
7841 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7842 struct rte_eth_hash_global_conf *g_cfg)
7844 uint32_t reg, mask = I40E_FLOW_TYPES;
7846 enum i40e_filter_pctype pctype;
7848 memset(g_cfg, 0, sizeof(*g_cfg));
7849 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7850 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7851 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7853 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7854 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7855 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7857 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7858 if (!(mask & (1UL << i)))
7860 mask &= ~(1UL << i);
7861 /* Bit set indicats the coresponding flow type is supported */
7862 g_cfg->valid_bit_mask[0] |= (1UL << i);
7863 /* if flowtype is invalid, continue */
7864 if (!I40E_VALID_FLOW(i))
7866 pctype = i40e_flowtype_to_pctype(i);
7867 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7868 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7869 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7876 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7879 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7881 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7882 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7883 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7884 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7890 * As i40e supports less than 32 flow types, only first 32 bits need to
7893 mask0 = g_cfg->valid_bit_mask[0];
7894 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7896 /* Check if any unsupported flow type configured */
7897 if ((mask0 | i40e_mask) ^ i40e_mask)
7900 if (g_cfg->valid_bit_mask[i])
7908 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7914 * Set global configurations of hash function type and symmetric hash enable
7915 * per flow type (pctype). Note any modifying global configuration will affect
7916 * all the ports on the same NIC.
7919 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7920 struct rte_eth_hash_global_conf *g_cfg)
7925 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7926 enum i40e_filter_pctype pctype;
7928 /* Check the input parameters */
7929 ret = i40e_hash_global_config_check(g_cfg);
7933 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7934 if (!(mask0 & (1UL << i)))
7936 mask0 &= ~(1UL << i);
7937 /* if flowtype is invalid, continue */
7938 if (!I40E_VALID_FLOW(i))
7940 pctype = i40e_flowtype_to_pctype(i);
7941 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7942 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7943 if (hw->mac.type == I40E_MAC_X722) {
7944 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7945 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7946 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7947 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7948 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7950 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7951 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7953 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7954 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7955 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7956 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7957 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7959 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7960 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7961 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7962 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7963 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7965 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7966 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7968 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7969 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7970 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7971 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7972 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7975 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7979 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7983 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7984 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7986 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7988 "Hash function already set to Toeplitz");
7991 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7992 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7994 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7996 "Hash function already set to Simple XOR");
7999 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8001 /* Use the default, and keep it as it is */
8004 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8007 I40E_WRITE_FLUSH(hw);
8013 * Valid input sets for hash and flow director filters per PCTYPE
8016 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8017 enum rte_filter_type filter)
8021 static const uint64_t valid_hash_inset_table[] = {
8022 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8023 I40E_INSET_DMAC | I40E_INSET_SMAC |
8024 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8025 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8026 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8027 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8028 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8029 I40E_INSET_FLEX_PAYLOAD,
8030 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8031 I40E_INSET_DMAC | I40E_INSET_SMAC |
8032 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8033 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8034 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8035 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8036 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8037 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8038 I40E_INSET_FLEX_PAYLOAD,
8039 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8040 I40E_INSET_DMAC | I40E_INSET_SMAC |
8041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8042 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8043 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8044 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8045 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8046 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8047 I40E_INSET_FLEX_PAYLOAD,
8048 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8049 I40E_INSET_DMAC | I40E_INSET_SMAC |
8050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8051 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8052 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8053 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8054 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8055 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8056 I40E_INSET_FLEX_PAYLOAD,
8057 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8058 I40E_INSET_DMAC | I40E_INSET_SMAC |
8059 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8060 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8061 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8062 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8063 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8064 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8065 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8066 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8067 I40E_INSET_DMAC | I40E_INSET_SMAC |
8068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8069 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8070 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8071 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8072 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8073 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8074 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8075 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8076 I40E_INSET_DMAC | I40E_INSET_SMAC |
8077 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8078 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8079 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8080 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8081 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8082 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8083 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8084 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8085 I40E_INSET_DMAC | I40E_INSET_SMAC |
8086 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8087 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8088 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8089 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8090 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8091 I40E_INSET_FLEX_PAYLOAD,
8092 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8093 I40E_INSET_DMAC | I40E_INSET_SMAC |
8094 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8095 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8096 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8097 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8098 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8099 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8100 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8101 I40E_INSET_DMAC | I40E_INSET_SMAC |
8102 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8103 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8104 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8105 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8106 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8107 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8108 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8109 I40E_INSET_DMAC | I40E_INSET_SMAC |
8110 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8111 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8112 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8113 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8114 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8115 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8116 I40E_INSET_FLEX_PAYLOAD,
8117 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8118 I40E_INSET_DMAC | I40E_INSET_SMAC |
8119 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8120 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8121 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8122 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8123 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8124 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8125 I40E_INSET_FLEX_PAYLOAD,
8126 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8127 I40E_INSET_DMAC | I40E_INSET_SMAC |
8128 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8129 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8130 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8131 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8132 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8133 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8134 I40E_INSET_FLEX_PAYLOAD,
8135 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8136 I40E_INSET_DMAC | I40E_INSET_SMAC |
8137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8138 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8139 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8140 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8141 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8142 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8143 I40E_INSET_FLEX_PAYLOAD,
8144 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8145 I40E_INSET_DMAC | I40E_INSET_SMAC |
8146 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8147 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8148 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8149 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8150 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8151 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8152 I40E_INSET_FLEX_PAYLOAD,
8153 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8154 I40E_INSET_DMAC | I40E_INSET_SMAC |
8155 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8156 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8157 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8158 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8159 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8160 I40E_INSET_FLEX_PAYLOAD,
8161 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8162 I40E_INSET_DMAC | I40E_INSET_SMAC |
8163 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8164 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8165 I40E_INSET_FLEX_PAYLOAD,
8169 * Flow director supports only fields defined in
8170 * union rte_eth_fdir_flow.
8172 static const uint64_t valid_fdir_inset_table[] = {
8173 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8174 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8175 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8176 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8177 I40E_INSET_IPV4_TTL,
8178 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8179 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8180 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8181 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8182 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8183 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8184 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8186 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8187 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8188 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8190 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8191 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8192 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8193 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8194 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8196 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8198 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8200 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8201 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8203 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8204 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8205 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8206 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8207 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8209 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8210 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8211 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8212 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8213 I40E_INSET_IPV4_TTL,
8214 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8215 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8216 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8217 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8218 I40E_INSET_IPV6_HOP_LIMIT,
8219 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8220 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8221 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8222 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8223 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8224 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8225 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8226 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8227 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8228 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8229 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8231 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8232 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8233 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8234 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8235 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8236 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8237 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8238 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8240 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8241 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8242 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8243 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8244 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8245 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8246 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8247 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8248 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8250 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8251 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8252 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8253 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8254 I40E_INSET_IPV6_HOP_LIMIT,
8255 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8256 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8257 I40E_INSET_LAST_ETHER_TYPE,
8260 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8262 if (filter == RTE_ETH_FILTER_HASH)
8263 valid = valid_hash_inset_table[pctype];
8265 valid = valid_fdir_inset_table[pctype];
8271 * Validate if the input set is allowed for a specific PCTYPE
8274 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8275 enum rte_filter_type filter, uint64_t inset)
8279 valid = i40e_get_valid_input_set(pctype, filter);
8280 if (inset & (~valid))
8286 /* default input set fields combination per pctype */
8288 i40e_get_default_input_set(uint16_t pctype)
8290 static const uint64_t default_inset_table[] = {
8291 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8292 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8293 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8294 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8296 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8297 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8298 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8299 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8300 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8301 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8302 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8303 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8304 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8305 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8306 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8307 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8308 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8309 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8310 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8312 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8313 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8314 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8315 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8316 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8317 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8318 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8319 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8320 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8321 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8322 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8323 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8324 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8325 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8326 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8327 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8328 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8329 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8330 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8331 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8332 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8333 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8335 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8336 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8337 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8338 I40E_INSET_LAST_ETHER_TYPE,
8341 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8344 return default_inset_table[pctype];
8348 * Parse the input set from index to logical bit masks
8351 i40e_parse_input_set(uint64_t *inset,
8352 enum i40e_filter_pctype pctype,
8353 enum rte_eth_input_set_field *field,
8359 static const struct {
8360 enum rte_eth_input_set_field field;
8362 } inset_convert_table[] = {
8363 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8364 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8365 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8366 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8367 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8368 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8369 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8370 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8371 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8372 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8373 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8374 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8375 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8376 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8377 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8378 I40E_INSET_IPV6_NEXT_HDR},
8379 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8380 I40E_INSET_IPV6_HOP_LIMIT},
8381 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8382 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8383 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8384 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8385 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8386 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8387 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8388 I40E_INSET_SCTP_VT},
8389 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8390 I40E_INSET_TUNNEL_DMAC},
8391 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8392 I40E_INSET_VLAN_TUNNEL},
8393 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8394 I40E_INSET_TUNNEL_ID},
8395 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8396 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8397 I40E_INSET_FLEX_PAYLOAD_W1},
8398 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8399 I40E_INSET_FLEX_PAYLOAD_W2},
8400 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8401 I40E_INSET_FLEX_PAYLOAD_W3},
8402 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8403 I40E_INSET_FLEX_PAYLOAD_W4},
8404 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8405 I40E_INSET_FLEX_PAYLOAD_W5},
8406 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8407 I40E_INSET_FLEX_PAYLOAD_W6},
8408 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8409 I40E_INSET_FLEX_PAYLOAD_W7},
8410 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8411 I40E_INSET_FLEX_PAYLOAD_W8},
8414 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8417 /* Only one item allowed for default or all */
8419 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8420 *inset = i40e_get_default_input_set(pctype);
8422 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8423 *inset = I40E_INSET_NONE;
8428 for (i = 0, *inset = 0; i < size; i++) {
8429 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8430 if (field[i] == inset_convert_table[j].field) {
8431 *inset |= inset_convert_table[j].inset;
8436 /* It contains unsupported input set, return immediately */
8437 if (j == RTE_DIM(inset_convert_table))
8445 * Translate the input set from bit masks to register aware bit masks
8449 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8459 static const struct inset_map inset_map_common[] = {
8460 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8461 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8462 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8463 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8464 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8465 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8466 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8467 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8468 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8469 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8470 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8471 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8472 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8473 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8474 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8475 {I40E_INSET_TUNNEL_DMAC,
8476 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8477 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8478 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8479 {I40E_INSET_TUNNEL_SRC_PORT,
8480 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8481 {I40E_INSET_TUNNEL_DST_PORT,
8482 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8483 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8484 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8485 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8486 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8487 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8488 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8489 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8490 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8491 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8494 /* some different registers map in x722*/
8495 static const struct inset_map inset_map_diff_x722[] = {
8496 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8497 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8498 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8499 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8502 static const struct inset_map inset_map_diff_not_x722[] = {
8503 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8504 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8505 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8506 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8512 /* Translate input set to register aware inset */
8513 if (type == I40E_MAC_X722) {
8514 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8515 if (input & inset_map_diff_x722[i].inset)
8516 val |= inset_map_diff_x722[i].inset_reg;
8519 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8520 if (input & inset_map_diff_not_x722[i].inset)
8521 val |= inset_map_diff_not_x722[i].inset_reg;
8525 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8526 if (input & inset_map_common[i].inset)
8527 val |= inset_map_common[i].inset_reg;
8534 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8537 uint64_t inset_need_mask = inset;
8539 static const struct {
8542 } inset_mask_map[] = {
8543 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8544 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8545 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8546 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8547 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8548 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8549 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8550 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8553 if (!inset || !mask || !nb_elem)
8556 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8557 /* Clear the inset bit, if no MASK is required,
8558 * for example proto + ttl
8560 if ((inset & inset_mask_map[i].inset) ==
8561 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8562 inset_need_mask &= ~inset_mask_map[i].inset;
8563 if (!inset_need_mask)
8566 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8567 if ((inset_need_mask & inset_mask_map[i].inset) ==
8568 inset_mask_map[i].inset) {
8569 if (idx >= nb_elem) {
8570 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8573 mask[idx] = inset_mask_map[i].mask;
8582 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8584 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8586 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8588 i40e_write_rx_ctl(hw, addr, val);
8589 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8590 (uint32_t)i40e_read_rx_ctl(hw, addr));
8594 i40e_filter_input_set_init(struct i40e_pf *pf)
8596 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8597 enum i40e_filter_pctype pctype;
8598 uint64_t input_set, inset_reg;
8599 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8602 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8603 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8604 if (hw->mac.type == I40E_MAC_X722) {
8605 if (!I40E_VALID_PCTYPE_X722(pctype))
8608 if (!I40E_VALID_PCTYPE(pctype))
8612 input_set = i40e_get_default_input_set(pctype);
8614 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8615 I40E_INSET_MASK_NUM_REG);
8618 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8621 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8622 (uint32_t)(inset_reg & UINT32_MAX));
8623 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8624 (uint32_t)((inset_reg >>
8625 I40E_32_BIT_WIDTH) & UINT32_MAX));
8626 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8627 (uint32_t)(inset_reg & UINT32_MAX));
8628 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8629 (uint32_t)((inset_reg >>
8630 I40E_32_BIT_WIDTH) & UINT32_MAX));
8632 for (i = 0; i < num; i++) {
8633 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8635 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8638 /*clear unused mask registers of the pctype */
8639 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8640 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8642 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8645 I40E_WRITE_FLUSH(hw);
8647 /* store the default input set */
8648 pf->hash_input_set[pctype] = input_set;
8649 pf->fdir.input_set[pctype] = input_set;
8654 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8655 struct rte_eth_input_set_conf *conf)
8657 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8658 enum i40e_filter_pctype pctype;
8659 uint64_t input_set, inset_reg = 0;
8660 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8664 PMD_DRV_LOG(ERR, "Invalid pointer");
8667 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8668 conf->op != RTE_ETH_INPUT_SET_ADD) {
8669 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8673 if (!I40E_VALID_FLOW(conf->flow_type)) {
8674 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8678 if (hw->mac.type == I40E_MAC_X722) {
8679 /* get translated pctype value in fd pctype register */
8680 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8681 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8684 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8686 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8689 PMD_DRV_LOG(ERR, "Failed to parse input set");
8692 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8694 PMD_DRV_LOG(ERR, "Invalid input set");
8697 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8698 /* get inset value in register */
8699 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8700 inset_reg <<= I40E_32_BIT_WIDTH;
8701 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8702 input_set |= pf->hash_input_set[pctype];
8704 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8705 I40E_INSET_MASK_NUM_REG);
8709 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8711 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8712 (uint32_t)(inset_reg & UINT32_MAX));
8713 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8714 (uint32_t)((inset_reg >>
8715 I40E_32_BIT_WIDTH) & UINT32_MAX));
8717 for (i = 0; i < num; i++)
8718 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8720 /*clear unused mask registers of the pctype */
8721 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8722 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8724 I40E_WRITE_FLUSH(hw);
8726 pf->hash_input_set[pctype] = input_set;
8731 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8732 struct rte_eth_input_set_conf *conf)
8734 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8735 enum i40e_filter_pctype pctype;
8736 uint64_t input_set, inset_reg = 0;
8737 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8741 PMD_DRV_LOG(ERR, "Invalid pointer");
8744 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8745 conf->op != RTE_ETH_INPUT_SET_ADD) {
8746 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8750 if (!I40E_VALID_FLOW(conf->flow_type)) {
8751 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8755 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8757 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8760 PMD_DRV_LOG(ERR, "Failed to parse input set");
8763 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8765 PMD_DRV_LOG(ERR, "Invalid input set");
8769 /* get inset value in register */
8770 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8771 inset_reg <<= I40E_32_BIT_WIDTH;
8772 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8774 /* Can not change the inset reg for flex payload for fdir,
8775 * it is done by writing I40E_PRTQF_FD_FLXINSET
8776 * in i40e_set_flex_mask_on_pctype.
8778 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8779 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8781 input_set |= pf->fdir.input_set[pctype];
8782 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8783 I40E_INSET_MASK_NUM_REG);
8787 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8789 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8790 (uint32_t)(inset_reg & UINT32_MAX));
8791 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8792 (uint32_t)((inset_reg >>
8793 I40E_32_BIT_WIDTH) & UINT32_MAX));
8795 for (i = 0; i < num; i++)
8796 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8798 /*clear unused mask registers of the pctype */
8799 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8800 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8802 I40E_WRITE_FLUSH(hw);
8804 pf->fdir.input_set[pctype] = input_set;
8809 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8814 PMD_DRV_LOG(ERR, "Invalid pointer");
8818 switch (info->info_type) {
8819 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8820 i40e_get_symmetric_hash_enable_per_port(hw,
8821 &(info->info.enable));
8823 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8824 ret = i40e_get_hash_filter_global_config(hw,
8825 &(info->info.global_conf));
8828 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8838 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8843 PMD_DRV_LOG(ERR, "Invalid pointer");
8847 switch (info->info_type) {
8848 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8849 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8851 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8852 ret = i40e_set_hash_filter_global_config(hw,
8853 &(info->info.global_conf));
8855 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8856 ret = i40e_hash_filter_inset_select(hw,
8857 &(info->info.input_set_conf));
8861 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8870 /* Operations for hash function */
8872 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8873 enum rte_filter_op filter_op,
8876 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8879 switch (filter_op) {
8880 case RTE_ETH_FILTER_NOP:
8882 case RTE_ETH_FILTER_GET:
8883 ret = i40e_hash_filter_get(hw,
8884 (struct rte_eth_hash_filter_info *)arg);
8886 case RTE_ETH_FILTER_SET:
8887 ret = i40e_hash_filter_set(hw,
8888 (struct rte_eth_hash_filter_info *)arg);
8891 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8900 /* Convert ethertype filter structure */
8902 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8903 struct i40e_ethertype_filter *filter)
8905 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8906 filter->input.ether_type = input->ether_type;
8907 filter->flags = input->flags;
8908 filter->queue = input->queue;
8913 /* Check if there exists the ehtertype filter */
8914 struct i40e_ethertype_filter *
8915 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8916 const struct i40e_ethertype_filter_input *input)
8920 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8924 return ethertype_rule->hash_map[ret];
8927 /* Add ethertype filter in SW list */
8929 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8930 struct i40e_ethertype_filter *filter)
8932 struct i40e_ethertype_rule *rule = &pf->ethertype;
8935 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8938 "Failed to insert ethertype filter"
8939 " to hash table %d!",
8943 rule->hash_map[ret] = filter;
8945 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8950 /* Delete ethertype filter in SW list */
8952 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8953 struct i40e_ethertype_filter_input *input)
8955 struct i40e_ethertype_rule *rule = &pf->ethertype;
8956 struct i40e_ethertype_filter *filter;
8959 ret = rte_hash_del_key(rule->hash_table, input);
8962 "Failed to delete ethertype filter"
8963 " to hash table %d!",
8967 filter = rule->hash_map[ret];
8968 rule->hash_map[ret] = NULL;
8970 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8977 * Configure ethertype filter, which can director packet by filtering
8978 * with mac address and ether_type or only ether_type
8981 i40e_ethertype_filter_set(struct i40e_pf *pf,
8982 struct rte_eth_ethertype_filter *filter,
8985 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8986 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8987 struct i40e_ethertype_filter *ethertype_filter, *node;
8988 struct i40e_ethertype_filter check_filter;
8989 struct i40e_control_filter_stats stats;
8993 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8994 PMD_DRV_LOG(ERR, "Invalid queue ID");
8997 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8998 filter->ether_type == ETHER_TYPE_IPv6) {
9000 "unsupported ether_type(0x%04x) in control packet filter.",
9001 filter->ether_type);
9004 if (filter->ether_type == ETHER_TYPE_VLAN)
9005 PMD_DRV_LOG(WARNING,
9006 "filter vlan ether_type in first tag is not supported.");
9008 /* Check if there is the filter in SW list */
9009 memset(&check_filter, 0, sizeof(check_filter));
9010 i40e_ethertype_filter_convert(filter, &check_filter);
9011 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9012 &check_filter.input);
9014 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9018 if (!add && !node) {
9019 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9023 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9024 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9025 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9026 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9027 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9029 memset(&stats, 0, sizeof(stats));
9030 ret = i40e_aq_add_rem_control_packet_filter(hw,
9031 filter->mac_addr.addr_bytes,
9032 filter->ether_type, flags,
9034 filter->queue, add, &stats, NULL);
9037 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9038 ret, stats.mac_etype_used, stats.etype_used,
9039 stats.mac_etype_free, stats.etype_free);
9043 /* Add or delete a filter in SW list */
9045 ethertype_filter = rte_zmalloc("ethertype_filter",
9046 sizeof(*ethertype_filter), 0);
9047 rte_memcpy(ethertype_filter, &check_filter,
9048 sizeof(check_filter));
9049 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9051 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9058 * Handle operations for ethertype filter.
9061 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9062 enum rte_filter_op filter_op,
9065 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9068 if (filter_op == RTE_ETH_FILTER_NOP)
9072 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9077 switch (filter_op) {
9078 case RTE_ETH_FILTER_ADD:
9079 ret = i40e_ethertype_filter_set(pf,
9080 (struct rte_eth_ethertype_filter *)arg,
9083 case RTE_ETH_FILTER_DELETE:
9084 ret = i40e_ethertype_filter_set(pf,
9085 (struct rte_eth_ethertype_filter *)arg,
9089 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9097 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9098 enum rte_filter_type filter_type,
9099 enum rte_filter_op filter_op,
9107 switch (filter_type) {
9108 case RTE_ETH_FILTER_NONE:
9109 /* For global configuration */
9110 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9112 case RTE_ETH_FILTER_HASH:
9113 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9115 case RTE_ETH_FILTER_MACVLAN:
9116 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9118 case RTE_ETH_FILTER_ETHERTYPE:
9119 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9121 case RTE_ETH_FILTER_TUNNEL:
9122 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9124 case RTE_ETH_FILTER_FDIR:
9125 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9127 case RTE_ETH_FILTER_GENERIC:
9128 if (filter_op != RTE_ETH_FILTER_GET)
9130 *(const void **)arg = &i40e_flow_ops;
9133 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9143 * Check and enable Extended Tag.
9144 * Enabling Extended Tag is important for 40G performance.
9147 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9149 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9153 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9156 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9160 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9161 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9166 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9169 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9173 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9174 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9177 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9178 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9181 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9188 * As some registers wouldn't be reset unless a global hardware reset,
9189 * hardware initialization is needed to put those registers into an
9190 * expected initial state.
9193 i40e_hw_init(struct rte_eth_dev *dev)
9195 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9197 i40e_enable_extended_tag(dev);
9199 /* clear the PF Queue Filter control register */
9200 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9202 /* Disable symmetric hash per port */
9203 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9206 enum i40e_filter_pctype
9207 i40e_flowtype_to_pctype(uint16_t flow_type)
9209 static const enum i40e_filter_pctype pctype_table[] = {
9210 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9211 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9212 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9213 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9214 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9215 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9216 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9217 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9218 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9219 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9220 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9221 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9222 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9223 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9224 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9225 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9226 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9227 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9228 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9231 return pctype_table[flow_type];
9235 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9237 static const uint16_t flowtype_table[] = {
9238 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9239 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9240 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9241 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9242 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9243 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9244 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9245 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9246 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9247 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9248 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9249 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9250 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9251 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9252 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9253 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9254 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9255 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9256 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9257 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9258 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9259 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9260 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9261 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9262 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9263 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9264 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9265 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9266 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9267 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9268 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9271 return flowtype_table[pctype];
9275 * On X710, performance number is far from the expectation on recent firmware
9276 * versions; on XL710, performance number is also far from the expectation on
9277 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9278 * mode is enabled and port MAC address is equal to the packet destination MAC
9279 * address. The fix for this issue may not be integrated in the following
9280 * firmware version. So the workaround in software driver is needed. It needs
9281 * to modify the initial values of 3 internal only registers for both X710 and
9282 * XL710. Note that the values for X710 or XL710 could be different, and the
9283 * workaround can be removed when it is fixed in firmware in the future.
9286 /* For both X710 and XL710 */
9287 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9288 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9289 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9291 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9292 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9295 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9296 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9299 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9301 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9302 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9305 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9307 enum i40e_status_code status;
9308 struct i40e_aq_get_phy_abilities_resp phy_ab;
9312 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9316 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9319 rte_delay_us(100000);
9321 status = i40e_aq_get_phy_capabilities(hw, false,
9322 true, &phy_ab, NULL);
9330 i40e_configure_registers(struct i40e_hw *hw)
9336 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9337 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9338 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9344 for (i = 0; i < RTE_DIM(reg_table); i++) {
9345 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9346 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9348 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9349 else /* For X710/XL710/XXV710 */
9350 if (hw->aq.fw_maj_ver < 6)
9352 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9355 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9358 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9359 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9361 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9362 else /* For X710/XL710/XXV710 */
9364 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9367 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9368 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9369 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9371 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9374 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9377 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9380 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9384 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9385 reg_table[i].addr, reg);
9386 if (reg == reg_table[i].val)
9389 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9390 reg_table[i].val, NULL);
9393 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9394 reg_table[i].val, reg_table[i].addr);
9397 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9398 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9402 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9403 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9404 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9405 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9407 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9412 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9413 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9417 /* Configure for double VLAN RX stripping */
9418 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9419 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9420 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9421 ret = i40e_aq_debug_write_register(hw,
9422 I40E_VSI_TSR(vsi->vsi_id),
9425 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9427 return I40E_ERR_CONFIG;
9431 /* Configure for double VLAN TX insertion */
9432 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9433 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9434 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9435 ret = i40e_aq_debug_write_register(hw,
9436 I40E_VSI_L2TAGSTXVALID(
9437 vsi->vsi_id), reg, NULL);
9440 "Failed to update VSI_L2TAGSTXVALID[%d]",
9442 return I40E_ERR_CONFIG;
9450 * i40e_aq_add_mirror_rule
9451 * @hw: pointer to the hardware structure
9452 * @seid: VEB seid to add mirror rule to
9453 * @dst_id: destination vsi seid
9454 * @entries: Buffer which contains the entities to be mirrored
9455 * @count: number of entities contained in the buffer
9456 * @rule_id:the rule_id of the rule to be added
9458 * Add a mirror rule for a given veb.
9461 static enum i40e_status_code
9462 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9463 uint16_t seid, uint16_t dst_id,
9464 uint16_t rule_type, uint16_t *entries,
9465 uint16_t count, uint16_t *rule_id)
9467 struct i40e_aq_desc desc;
9468 struct i40e_aqc_add_delete_mirror_rule cmd;
9469 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9470 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9473 enum i40e_status_code status;
9475 i40e_fill_default_direct_cmd_desc(&desc,
9476 i40e_aqc_opc_add_mirror_rule);
9477 memset(&cmd, 0, sizeof(cmd));
9479 buff_len = sizeof(uint16_t) * count;
9480 desc.datalen = rte_cpu_to_le_16(buff_len);
9482 desc.flags |= rte_cpu_to_le_16(
9483 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9484 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9485 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9486 cmd.num_entries = rte_cpu_to_le_16(count);
9487 cmd.seid = rte_cpu_to_le_16(seid);
9488 cmd.destination = rte_cpu_to_le_16(dst_id);
9490 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9491 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9493 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9494 hw->aq.asq_last_status, resp->rule_id,
9495 resp->mirror_rules_used, resp->mirror_rules_free);
9496 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9502 * i40e_aq_del_mirror_rule
9503 * @hw: pointer to the hardware structure
9504 * @seid: VEB seid to add mirror rule to
9505 * @entries: Buffer which contains the entities to be mirrored
9506 * @count: number of entities contained in the buffer
9507 * @rule_id:the rule_id of the rule to be delete
9509 * Delete a mirror rule for a given veb.
9512 static enum i40e_status_code
9513 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9514 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9515 uint16_t count, uint16_t rule_id)
9517 struct i40e_aq_desc desc;
9518 struct i40e_aqc_add_delete_mirror_rule cmd;
9519 uint16_t buff_len = 0;
9520 enum i40e_status_code status;
9523 i40e_fill_default_direct_cmd_desc(&desc,
9524 i40e_aqc_opc_delete_mirror_rule);
9525 memset(&cmd, 0, sizeof(cmd));
9526 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9527 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9529 cmd.num_entries = count;
9530 buff_len = sizeof(uint16_t) * count;
9531 desc.datalen = rte_cpu_to_le_16(buff_len);
9532 buff = (void *)entries;
9534 /* rule id is filled in destination field for deleting mirror rule */
9535 cmd.destination = rte_cpu_to_le_16(rule_id);
9537 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9538 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9539 cmd.seid = rte_cpu_to_le_16(seid);
9541 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9542 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9548 * i40e_mirror_rule_set
9549 * @dev: pointer to the hardware structure
9550 * @mirror_conf: mirror rule info
9551 * @sw_id: mirror rule's sw_id
9552 * @on: enable/disable
9554 * set a mirror rule.
9558 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9559 struct rte_eth_mirror_conf *mirror_conf,
9560 uint8_t sw_id, uint8_t on)
9562 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9563 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9564 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9565 struct i40e_mirror_rule *parent = NULL;
9566 uint16_t seid, dst_seid, rule_id;
9570 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9572 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9574 "mirror rule can not be configured without veb or vfs.");
9577 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9578 PMD_DRV_LOG(ERR, "mirror table is full.");
9581 if (mirror_conf->dst_pool > pf->vf_num) {
9582 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9583 mirror_conf->dst_pool);
9587 seid = pf->main_vsi->veb->seid;
9589 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9590 if (sw_id <= it->index) {
9596 if (mirr_rule && sw_id == mirr_rule->index) {
9598 PMD_DRV_LOG(ERR, "mirror rule exists.");
9601 ret = i40e_aq_del_mirror_rule(hw, seid,
9602 mirr_rule->rule_type,
9604 mirr_rule->num_entries, mirr_rule->id);
9607 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9608 ret, hw->aq.asq_last_status);
9611 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9612 rte_free(mirr_rule);
9613 pf->nb_mirror_rule--;
9617 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9621 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9622 sizeof(struct i40e_mirror_rule) , 0);
9624 PMD_DRV_LOG(ERR, "failed to allocate memory");
9625 return I40E_ERR_NO_MEMORY;
9627 switch (mirror_conf->rule_type) {
9628 case ETH_MIRROR_VLAN:
9629 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9630 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9631 mirr_rule->entries[j] =
9632 mirror_conf->vlan.vlan_id[i];
9637 PMD_DRV_LOG(ERR, "vlan is not specified.");
9638 rte_free(mirr_rule);
9641 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9643 case ETH_MIRROR_VIRTUAL_POOL_UP:
9644 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9645 /* check if the specified pool bit is out of range */
9646 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9647 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9648 rte_free(mirr_rule);
9651 for (i = 0, j = 0; i < pf->vf_num; i++) {
9652 if (mirror_conf->pool_mask & (1ULL << i)) {
9653 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9657 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9658 /* add pf vsi to entries */
9659 mirr_rule->entries[j] = pf->main_vsi_seid;
9663 PMD_DRV_LOG(ERR, "pool is not specified.");
9664 rte_free(mirr_rule);
9667 /* egress and ingress in aq commands means from switch but not port */
9668 mirr_rule->rule_type =
9669 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9670 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9671 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9673 case ETH_MIRROR_UPLINK_PORT:
9674 /* egress and ingress in aq commands means from switch but not port*/
9675 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9677 case ETH_MIRROR_DOWNLINK_PORT:
9678 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9681 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9682 mirror_conf->rule_type);
9683 rte_free(mirr_rule);
9687 /* If the dst_pool is equal to vf_num, consider it as PF */
9688 if (mirror_conf->dst_pool == pf->vf_num)
9689 dst_seid = pf->main_vsi_seid;
9691 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9693 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9694 mirr_rule->rule_type, mirr_rule->entries,
9698 "failed to add mirror rule: ret = %d, aq_err = %d.",
9699 ret, hw->aq.asq_last_status);
9700 rte_free(mirr_rule);
9704 mirr_rule->index = sw_id;
9705 mirr_rule->num_entries = j;
9706 mirr_rule->id = rule_id;
9707 mirr_rule->dst_vsi_seid = dst_seid;
9710 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9712 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9714 pf->nb_mirror_rule++;
9719 * i40e_mirror_rule_reset
9720 * @dev: pointer to the device
9721 * @sw_id: mirror rule's sw_id
9723 * reset a mirror rule.
9727 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9729 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9730 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9731 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9735 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9737 seid = pf->main_vsi->veb->seid;
9739 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9740 if (sw_id == it->index) {
9746 ret = i40e_aq_del_mirror_rule(hw, seid,
9747 mirr_rule->rule_type,
9749 mirr_rule->num_entries, mirr_rule->id);
9752 "failed to remove mirror rule: status = %d, aq_err = %d.",
9753 ret, hw->aq.asq_last_status);
9756 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9757 rte_free(mirr_rule);
9758 pf->nb_mirror_rule--;
9760 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9767 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9770 uint64_t systim_cycles;
9772 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9773 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9776 return systim_cycles;
9780 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9785 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9786 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9793 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9795 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9798 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9799 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9806 i40e_start_timecounters(struct rte_eth_dev *dev)
9808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9809 struct i40e_adapter *adapter =
9810 (struct i40e_adapter *)dev->data->dev_private;
9811 struct rte_eth_link link;
9812 uint32_t tsync_inc_l;
9813 uint32_t tsync_inc_h;
9815 /* Get current link speed. */
9816 memset(&link, 0, sizeof(link));
9817 i40e_dev_link_update(dev, 1);
9818 rte_i40e_dev_atomic_read_link_status(dev, &link);
9820 switch (link.link_speed) {
9821 case ETH_SPEED_NUM_40G:
9822 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9823 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9825 case ETH_SPEED_NUM_10G:
9826 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9827 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9829 case ETH_SPEED_NUM_1G:
9830 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9831 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9838 /* Set the timesync increment value. */
9839 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9840 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9842 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9843 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9844 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9846 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9847 adapter->systime_tc.cc_shift = 0;
9848 adapter->systime_tc.nsec_mask = 0;
9850 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9851 adapter->rx_tstamp_tc.cc_shift = 0;
9852 adapter->rx_tstamp_tc.nsec_mask = 0;
9854 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9855 adapter->tx_tstamp_tc.cc_shift = 0;
9856 adapter->tx_tstamp_tc.nsec_mask = 0;
9860 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9862 struct i40e_adapter *adapter =
9863 (struct i40e_adapter *)dev->data->dev_private;
9865 adapter->systime_tc.nsec += delta;
9866 adapter->rx_tstamp_tc.nsec += delta;
9867 adapter->tx_tstamp_tc.nsec += delta;
9873 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9876 struct i40e_adapter *adapter =
9877 (struct i40e_adapter *)dev->data->dev_private;
9879 ns = rte_timespec_to_ns(ts);
9881 /* Set the timecounters to a new value. */
9882 adapter->systime_tc.nsec = ns;
9883 adapter->rx_tstamp_tc.nsec = ns;
9884 adapter->tx_tstamp_tc.nsec = ns;
9890 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9892 uint64_t ns, systime_cycles;
9893 struct i40e_adapter *adapter =
9894 (struct i40e_adapter *)dev->data->dev_private;
9896 systime_cycles = i40e_read_systime_cyclecounter(dev);
9897 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9898 *ts = rte_ns_to_timespec(ns);
9904 i40e_timesync_enable(struct rte_eth_dev *dev)
9906 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9907 uint32_t tsync_ctl_l;
9908 uint32_t tsync_ctl_h;
9910 /* Stop the timesync system time. */
9911 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9912 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9913 /* Reset the timesync system time value. */
9914 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9915 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9917 i40e_start_timecounters(dev);
9919 /* Clear timesync registers. */
9920 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9921 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9922 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9923 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9924 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9925 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9927 /* Enable timestamping of PTP packets. */
9928 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9929 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9931 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9932 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9933 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9935 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9936 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9942 i40e_timesync_disable(struct rte_eth_dev *dev)
9944 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9945 uint32_t tsync_ctl_l;
9946 uint32_t tsync_ctl_h;
9948 /* Disable timestamping of transmitted PTP packets. */
9949 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9950 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9952 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9953 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9955 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9956 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9958 /* Reset the timesync increment value. */
9959 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9960 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9966 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9967 struct timespec *timestamp, uint32_t flags)
9969 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9970 struct i40e_adapter *adapter =
9971 (struct i40e_adapter *)dev->data->dev_private;
9973 uint32_t sync_status;
9974 uint32_t index = flags & 0x03;
9975 uint64_t rx_tstamp_cycles;
9978 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9979 if ((sync_status & (1 << index)) == 0)
9982 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9983 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9984 *timestamp = rte_ns_to_timespec(ns);
9990 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9991 struct timespec *timestamp)
9993 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9994 struct i40e_adapter *adapter =
9995 (struct i40e_adapter *)dev->data->dev_private;
9997 uint32_t sync_status;
9998 uint64_t tx_tstamp_cycles;
10001 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10002 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10005 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10006 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10007 *timestamp = rte_ns_to_timespec(ns);
10013 * i40e_parse_dcb_configure - parse dcb configure from user
10014 * @dev: the device being configured
10015 * @dcb_cfg: pointer of the result of parse
10016 * @*tc_map: bit map of enabled traffic classes
10018 * Returns 0 on success, negative value on failure
10021 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10022 struct i40e_dcbx_config *dcb_cfg,
10025 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10026 uint8_t i, tc_bw, bw_lf;
10028 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10030 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10031 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10032 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10036 /* assume each tc has the same bw */
10037 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10038 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10039 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10040 /* to ensure the sum of tcbw is equal to 100 */
10041 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10042 for (i = 0; i < bw_lf; i++)
10043 dcb_cfg->etscfg.tcbwtable[i]++;
10045 /* assume each tc has the same Transmission Selection Algorithm */
10046 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10047 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10049 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10050 dcb_cfg->etscfg.prioritytable[i] =
10051 dcb_rx_conf->dcb_tc[i];
10053 /* FW needs one App to configure HW */
10054 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10055 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10056 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10057 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10059 if (dcb_rx_conf->nb_tcs == 0)
10060 *tc_map = 1; /* tc0 only */
10062 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10064 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10065 dcb_cfg->pfc.willing = 0;
10066 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10067 dcb_cfg->pfc.pfcenable = *tc_map;
10073 static enum i40e_status_code
10074 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10075 struct i40e_aqc_vsi_properties_data *info,
10076 uint8_t enabled_tcmap)
10078 enum i40e_status_code ret;
10079 int i, total_tc = 0;
10080 uint16_t qpnum_per_tc, bsf, qp_idx;
10081 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10082 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10083 uint16_t used_queues;
10085 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10086 if (ret != I40E_SUCCESS)
10089 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10090 if (enabled_tcmap & (1 << i))
10095 vsi->enabled_tc = enabled_tcmap;
10097 /* different VSI has different queues assigned */
10098 if (vsi->type == I40E_VSI_MAIN)
10099 used_queues = dev_data->nb_rx_queues -
10100 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10101 else if (vsi->type == I40E_VSI_VMDQ2)
10102 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10104 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10105 return I40E_ERR_NO_AVAILABLE_VSI;
10108 qpnum_per_tc = used_queues / total_tc;
10109 /* Number of queues per enabled TC */
10110 if (qpnum_per_tc == 0) {
10111 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10112 return I40E_ERR_INVALID_QP_ID;
10114 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10115 I40E_MAX_Q_PER_TC);
10116 bsf = rte_bsf32(qpnum_per_tc);
10119 * Configure TC and queue mapping parameters, for enabled TC,
10120 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10121 * default queue will serve it.
10124 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10125 if (vsi->enabled_tc & (1 << i)) {
10126 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10127 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10128 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10129 qp_idx += qpnum_per_tc;
10131 info->tc_mapping[i] = 0;
10134 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10135 if (vsi->type == I40E_VSI_SRIOV) {
10136 info->mapping_flags |=
10137 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10138 for (i = 0; i < vsi->nb_qps; i++)
10139 info->queue_mapping[i] =
10140 rte_cpu_to_le_16(vsi->base_queue + i);
10142 info->mapping_flags |=
10143 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10144 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10146 info->valid_sections |=
10147 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10149 return I40E_SUCCESS;
10153 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10154 * @veb: VEB to be configured
10155 * @tc_map: enabled TC bitmap
10157 * Returns 0 on success, negative value on failure
10159 static enum i40e_status_code
10160 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10162 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10163 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10164 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10165 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10166 enum i40e_status_code ret = I40E_SUCCESS;
10170 /* Check if enabled_tc is same as existing or new TCs */
10171 if (veb->enabled_tc == tc_map)
10174 /* configure tc bandwidth */
10175 memset(&veb_bw, 0, sizeof(veb_bw));
10176 veb_bw.tc_valid_bits = tc_map;
10177 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10178 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10179 if (tc_map & BIT_ULL(i))
10180 veb_bw.tc_bw_share_credits[i] = 1;
10182 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10186 "AQ command Config switch_comp BW allocation per TC failed = %d",
10187 hw->aq.asq_last_status);
10191 memset(&ets_query, 0, sizeof(ets_query));
10192 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10194 if (ret != I40E_SUCCESS) {
10196 "Failed to get switch_comp ETS configuration %u",
10197 hw->aq.asq_last_status);
10200 memset(&bw_query, 0, sizeof(bw_query));
10201 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10203 if (ret != I40E_SUCCESS) {
10205 "Failed to get switch_comp bandwidth configuration %u",
10206 hw->aq.asq_last_status);
10210 /* store and print out BW info */
10211 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10212 veb->bw_info.bw_max = ets_query.tc_bw_max;
10213 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10214 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10215 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10216 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10217 I40E_16_BIT_WIDTH);
10218 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10219 veb->bw_info.bw_ets_share_credits[i] =
10220 bw_query.tc_bw_share_credits[i];
10221 veb->bw_info.bw_ets_credits[i] =
10222 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10223 /* 4 bits per TC, 4th bit is reserved */
10224 veb->bw_info.bw_ets_max[i] =
10225 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10226 RTE_LEN2MASK(3, uint8_t));
10227 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10228 veb->bw_info.bw_ets_share_credits[i]);
10229 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10230 veb->bw_info.bw_ets_credits[i]);
10231 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10232 veb->bw_info.bw_ets_max[i]);
10235 veb->enabled_tc = tc_map;
10242 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10243 * @vsi: VSI to be configured
10244 * @tc_map: enabled TC bitmap
10246 * Returns 0 on success, negative value on failure
10248 static enum i40e_status_code
10249 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10251 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10252 struct i40e_vsi_context ctxt;
10253 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10254 enum i40e_status_code ret = I40E_SUCCESS;
10257 /* Check if enabled_tc is same as existing or new TCs */
10258 if (vsi->enabled_tc == tc_map)
10261 /* configure tc bandwidth */
10262 memset(&bw_data, 0, sizeof(bw_data));
10263 bw_data.tc_valid_bits = tc_map;
10264 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10265 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10266 if (tc_map & BIT_ULL(i))
10267 bw_data.tc_bw_credits[i] = 1;
10269 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10272 "AQ command Config VSI BW allocation per TC failed = %d",
10273 hw->aq.asq_last_status);
10276 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10277 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10279 /* Update Queue Pairs Mapping for currently enabled UPs */
10280 ctxt.seid = vsi->seid;
10281 ctxt.pf_num = hw->pf_id;
10283 ctxt.uplink_seid = vsi->uplink_seid;
10284 ctxt.info = vsi->info;
10286 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10290 /* Update the VSI after updating the VSI queue-mapping information */
10291 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10293 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10294 hw->aq.asq_last_status);
10297 /* update the local VSI info with updated queue map */
10298 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10299 sizeof(vsi->info.tc_mapping));
10300 rte_memcpy(&vsi->info.queue_mapping,
10301 &ctxt.info.queue_mapping,
10302 sizeof(vsi->info.queue_mapping));
10303 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10304 vsi->info.valid_sections = 0;
10306 /* query and update current VSI BW information */
10307 ret = i40e_vsi_get_bw_config(vsi);
10310 "Failed updating vsi bw info, err %s aq_err %s",
10311 i40e_stat_str(hw, ret),
10312 i40e_aq_str(hw, hw->aq.asq_last_status));
10316 vsi->enabled_tc = tc_map;
10323 * i40e_dcb_hw_configure - program the dcb setting to hw
10324 * @pf: pf the configuration is taken on
10325 * @new_cfg: new configuration
10326 * @tc_map: enabled TC bitmap
10328 * Returns 0 on success, negative value on failure
10330 static enum i40e_status_code
10331 i40e_dcb_hw_configure(struct i40e_pf *pf,
10332 struct i40e_dcbx_config *new_cfg,
10335 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10336 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10337 struct i40e_vsi *main_vsi = pf->main_vsi;
10338 struct i40e_vsi_list *vsi_list;
10339 enum i40e_status_code ret;
10343 /* Use the FW API if FW > v4.4*/
10344 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10345 (hw->aq.fw_maj_ver >= 5))) {
10347 "FW < v4.4, can not use FW LLDP API to configure DCB");
10348 return I40E_ERR_FIRMWARE_API_VERSION;
10351 /* Check if need reconfiguration */
10352 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10353 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10354 return I40E_SUCCESS;
10357 /* Copy the new config to the current config */
10358 *old_cfg = *new_cfg;
10359 old_cfg->etsrec = old_cfg->etscfg;
10360 ret = i40e_set_dcb_config(hw);
10362 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10363 i40e_stat_str(hw, ret),
10364 i40e_aq_str(hw, hw->aq.asq_last_status));
10367 /* set receive Arbiter to RR mode and ETS scheme by default */
10368 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10369 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10370 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10371 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10372 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10373 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10374 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10375 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10376 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10377 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10378 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10379 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10380 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10382 /* get local mib to check whether it is configured correctly */
10384 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10385 /* Get Local DCB Config */
10386 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10387 &hw->local_dcbx_config);
10389 /* if Veb is created, need to update TC of it at first */
10390 if (main_vsi->veb) {
10391 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10393 PMD_INIT_LOG(WARNING,
10394 "Failed configuring TC for VEB seid=%d",
10395 main_vsi->veb->seid);
10397 /* Update each VSI */
10398 i40e_vsi_config_tc(main_vsi, tc_map);
10399 if (main_vsi->veb) {
10400 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10401 /* Beside main VSI and VMDQ VSIs, only enable default
10402 * TC for other VSIs
10404 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10405 ret = i40e_vsi_config_tc(vsi_list->vsi,
10408 ret = i40e_vsi_config_tc(vsi_list->vsi,
10409 I40E_DEFAULT_TCMAP);
10411 PMD_INIT_LOG(WARNING,
10412 "Failed configuring TC for VSI seid=%d",
10413 vsi_list->vsi->seid);
10417 return I40E_SUCCESS;
10421 * i40e_dcb_init_configure - initial dcb config
10422 * @dev: device being configured
10423 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10425 * Returns 0 on success, negative value on failure
10428 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10434 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10435 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10439 /* DCB initialization:
10440 * Update DCB configuration from the Firmware and configure
10441 * LLDP MIB change event.
10443 if (sw_dcb == TRUE) {
10444 ret = i40e_init_dcb(hw);
10445 /* If lldp agent is stopped, the return value from
10446 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10447 * adminq status. Otherwise, it should return success.
10449 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10450 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10451 memset(&hw->local_dcbx_config, 0,
10452 sizeof(struct i40e_dcbx_config));
10453 /* set dcb default configuration */
10454 hw->local_dcbx_config.etscfg.willing = 0;
10455 hw->local_dcbx_config.etscfg.maxtcs = 0;
10456 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10457 hw->local_dcbx_config.etscfg.tsatable[0] =
10459 /* all UPs mapping to TC0 */
10460 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10461 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10462 hw->local_dcbx_config.etsrec =
10463 hw->local_dcbx_config.etscfg;
10464 hw->local_dcbx_config.pfc.willing = 0;
10465 hw->local_dcbx_config.pfc.pfccap =
10466 I40E_MAX_TRAFFIC_CLASS;
10467 /* FW needs one App to configure HW */
10468 hw->local_dcbx_config.numapps = 1;
10469 hw->local_dcbx_config.app[0].selector =
10470 I40E_APP_SEL_ETHTYPE;
10471 hw->local_dcbx_config.app[0].priority = 3;
10472 hw->local_dcbx_config.app[0].protocolid =
10473 I40E_APP_PROTOID_FCOE;
10474 ret = i40e_set_dcb_config(hw);
10477 "default dcb config fails. err = %d, aq_err = %d.",
10478 ret, hw->aq.asq_last_status);
10483 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10484 ret, hw->aq.asq_last_status);
10488 ret = i40e_aq_start_lldp(hw, NULL);
10489 if (ret != I40E_SUCCESS)
10490 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10492 ret = i40e_init_dcb(hw);
10494 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10496 "HW doesn't support DCBX offload.");
10501 "DCBX configuration failed, err = %d, aq_err = %d.",
10502 ret, hw->aq.asq_last_status);
10510 * i40e_dcb_setup - setup dcb related config
10511 * @dev: device being configured
10513 * Returns 0 on success, negative value on failure
10516 i40e_dcb_setup(struct rte_eth_dev *dev)
10518 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10519 struct i40e_dcbx_config dcb_cfg;
10520 uint8_t tc_map = 0;
10523 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10524 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10528 if (pf->vf_num != 0)
10529 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10531 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10533 PMD_INIT_LOG(ERR, "invalid dcb config");
10536 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10538 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10546 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10547 struct rte_eth_dcb_info *dcb_info)
10549 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10550 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10551 struct i40e_vsi *vsi = pf->main_vsi;
10552 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10553 uint16_t bsf, tc_mapping;
10556 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10557 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10559 dcb_info->nb_tcs = 1;
10560 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10561 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10562 for (i = 0; i < dcb_info->nb_tcs; i++)
10563 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10565 /* get queue mapping if vmdq is disabled */
10566 if (!pf->nb_cfg_vmdq_vsi) {
10567 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10568 if (!(vsi->enabled_tc & (1 << i)))
10570 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10571 dcb_info->tc_queue.tc_rxq[j][i].base =
10572 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10573 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10574 dcb_info->tc_queue.tc_txq[j][i].base =
10575 dcb_info->tc_queue.tc_rxq[j][i].base;
10576 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10577 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10578 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10579 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10580 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10585 /* get queue mapping if vmdq is enabled */
10587 vsi = pf->vmdq[j].vsi;
10588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10589 if (!(vsi->enabled_tc & (1 << i)))
10591 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10592 dcb_info->tc_queue.tc_rxq[j][i].base =
10593 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10594 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10595 dcb_info->tc_queue.tc_txq[j][i].base =
10596 dcb_info->tc_queue.tc_rxq[j][i].base;
10597 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10598 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10599 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10600 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10601 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10604 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10609 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10611 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10612 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10614 uint16_t interval =
10615 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10616 uint16_t msix_intr;
10618 msix_intr = intr_handle->intr_vec[queue_id];
10619 if (msix_intr == I40E_MISC_VEC_ID)
10620 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10621 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10622 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10623 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10625 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10628 I40E_PFINT_DYN_CTLN(msix_intr -
10629 I40E_RX_VEC_START),
10630 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10631 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10632 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10634 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10636 I40E_WRITE_FLUSH(hw);
10637 rte_intr_enable(&pci_dev->intr_handle);
10643 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10645 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10646 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10648 uint16_t msix_intr;
10650 msix_intr = intr_handle->intr_vec[queue_id];
10651 if (msix_intr == I40E_MISC_VEC_ID)
10652 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10655 I40E_PFINT_DYN_CTLN(msix_intr -
10656 I40E_RX_VEC_START),
10658 I40E_WRITE_FLUSH(hw);
10663 static int i40e_get_regs(struct rte_eth_dev *dev,
10664 struct rte_dev_reg_info *regs)
10666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10667 uint32_t *ptr_data = regs->data;
10668 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10669 const struct i40e_reg_info *reg_info;
10671 if (ptr_data == NULL) {
10672 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10673 regs->width = sizeof(uint32_t);
10677 /* The first few registers have to be read using AQ operations */
10679 while (i40e_regs_adminq[reg_idx].name) {
10680 reg_info = &i40e_regs_adminq[reg_idx++];
10681 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10683 arr_idx2 <= reg_info->count2;
10685 reg_offset = arr_idx * reg_info->stride1 +
10686 arr_idx2 * reg_info->stride2;
10687 reg_offset += reg_info->base_addr;
10688 ptr_data[reg_offset >> 2] =
10689 i40e_read_rx_ctl(hw, reg_offset);
10693 /* The remaining registers can be read using primitives */
10695 while (i40e_regs_others[reg_idx].name) {
10696 reg_info = &i40e_regs_others[reg_idx++];
10697 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10699 arr_idx2 <= reg_info->count2;
10701 reg_offset = arr_idx * reg_info->stride1 +
10702 arr_idx2 * reg_info->stride2;
10703 reg_offset += reg_info->base_addr;
10704 ptr_data[reg_offset >> 2] =
10705 I40E_READ_REG(hw, reg_offset);
10712 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10716 /* Convert word count to byte count */
10717 return hw->nvm.sr_size << 1;
10720 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10721 struct rte_dev_eeprom_info *eeprom)
10723 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10724 uint16_t *data = eeprom->data;
10725 uint16_t offset, length, cnt_words;
10728 offset = eeprom->offset >> 1;
10729 length = eeprom->length >> 1;
10730 cnt_words = length;
10732 if (offset > hw->nvm.sr_size ||
10733 offset + length > hw->nvm.sr_size) {
10734 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10738 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10740 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10741 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10742 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10749 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10750 struct ether_addr *mac_addr)
10752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10754 if (!is_valid_assigned_ether_addr(mac_addr)) {
10755 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10759 /* Flags: 0x3 updates port address */
10760 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10764 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10766 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10767 struct rte_eth_dev_data *dev_data = pf->dev_data;
10768 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10771 /* check if mtu is within the allowed range */
10772 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10775 /* mtu setting is forbidden if port is start */
10776 if (dev_data->dev_started) {
10777 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10778 dev_data->port_id);
10782 if (frame_size > ETHER_MAX_LEN)
10783 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10785 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10787 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10792 /* Restore ethertype filter */
10794 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10796 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10797 struct i40e_ethertype_filter_list
10798 *ethertype_list = &pf->ethertype.ethertype_list;
10799 struct i40e_ethertype_filter *f;
10800 struct i40e_control_filter_stats stats;
10803 TAILQ_FOREACH(f, ethertype_list, rules) {
10805 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10806 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10807 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10808 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10809 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10811 memset(&stats, 0, sizeof(stats));
10812 i40e_aq_add_rem_control_packet_filter(hw,
10813 f->input.mac_addr.addr_bytes,
10814 f->input.ether_type,
10815 flags, pf->main_vsi->seid,
10816 f->queue, 1, &stats, NULL);
10818 PMD_DRV_LOG(INFO, "Ethertype filter:"
10819 " mac_etype_used = %u, etype_used = %u,"
10820 " mac_etype_free = %u, etype_free = %u",
10821 stats.mac_etype_used, stats.etype_used,
10822 stats.mac_etype_free, stats.etype_free);
10825 /* Restore tunnel filter */
10827 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10829 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10830 struct i40e_vsi *vsi;
10831 struct i40e_pf_vf *vf;
10832 struct i40e_tunnel_filter_list
10833 *tunnel_list = &pf->tunnel.tunnel_list;
10834 struct i40e_tunnel_filter *f;
10835 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10836 bool big_buffer = 0;
10838 TAILQ_FOREACH(f, tunnel_list, rules) {
10840 vsi = pf->main_vsi;
10842 vf = &pf->vfs[f->vf_id];
10845 memset(&cld_filter, 0, sizeof(cld_filter));
10846 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10847 (struct ether_addr *)&cld_filter.element.outer_mac);
10848 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10849 (struct ether_addr *)&cld_filter.element.inner_mac);
10850 cld_filter.element.inner_vlan = f->input.inner_vlan;
10851 cld_filter.element.flags = f->input.flags;
10852 cld_filter.element.tenant_id = f->input.tenant_id;
10853 cld_filter.element.queue_number = f->queue;
10854 rte_memcpy(cld_filter.general_fields,
10855 f->input.general_fields,
10856 sizeof(f->input.general_fields));
10858 if (((f->input.flags &
10859 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10860 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10862 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10863 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10865 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10866 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10870 i40e_aq_add_cloud_filters_big_buffer(hw,
10871 vsi->seid, &cld_filter, 1);
10873 i40e_aq_add_cloud_filters(hw, vsi->seid,
10874 &cld_filter.element, 1);
10879 i40e_filter_restore(struct i40e_pf *pf)
10881 i40e_ethertype_filter_restore(pf);
10882 i40e_tunnel_filter_restore(pf);
10883 i40e_fdir_filter_restore(pf);
10887 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10889 if (strcmp(dev->device->driver->name, drv->driver.name))
10896 is_i40e_supported(struct rte_eth_dev *dev)
10898 return is_device_supported(dev, &rte_i40e_pmd);
10901 /* Create a QinQ cloud filter
10903 * The Fortville NIC has limited resources for tunnel filters,
10904 * so we can only reuse existing filters.
10906 * In step 1 we define which Field Vector fields can be used for
10908 * As we do not have the inner tag defined as a field,
10909 * we have to define it first, by reusing one of L1 entries.
10911 * In step 2 we are replacing one of existing filter types with
10912 * a new one for QinQ.
10913 * As we reusing L1 and replacing L2, some of the default filter
10914 * types will disappear,which depends on L1 and L2 entries we reuse.
10916 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10918 * 1. Create L1 filter of outer vlan (12b) which will be in use
10919 * later when we define the cloud filter.
10920 * a. Valid_flags.replace_cloud = 0
10921 * b. Old_filter = 10 (Stag_Inner_Vlan)
10922 * c. New_filter = 0x10
10923 * d. TR bit = 0xff (optional, not used here)
10924 * e. Buffer – 2 entries:
10925 * i. Byte 0 = 8 (outer vlan FV index).
10927 * Byte 2-3 = 0x0fff
10928 * ii. Byte 0 = 37 (inner vlan FV index).
10930 * Byte 2-3 = 0x0fff
10933 * 2. Create cloud filter using two L1 filters entries: stag and
10934 * new filter(outer vlan+ inner vlan)
10935 * a. Valid_flags.replace_cloud = 1
10936 * b. Old_filter = 1 (instead of outer IP)
10937 * c. New_filter = 0x10
10938 * d. Buffer – 2 entries:
10939 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10940 * Byte 1-3 = 0 (rsv)
10941 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10942 * Byte 9-11 = 0 (rsv)
10945 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10947 int ret = -ENOTSUP;
10948 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10949 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10950 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10953 memset(&filter_replace, 0,
10954 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10955 memset(&filter_replace_buf, 0,
10956 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10958 /* create L1 filter */
10959 filter_replace.old_filter_type =
10960 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10961 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10962 filter_replace.tr_bit = 0;
10964 /* Prepare the buffer, 2 entries */
10965 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10966 filter_replace_buf.data[0] |=
10967 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10968 /* Field Vector 12b mask */
10969 filter_replace_buf.data[2] = 0xff;
10970 filter_replace_buf.data[3] = 0x0f;
10971 filter_replace_buf.data[4] =
10972 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10973 filter_replace_buf.data[4] |=
10974 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10975 /* Field Vector 12b mask */
10976 filter_replace_buf.data[6] = 0xff;
10977 filter_replace_buf.data[7] = 0x0f;
10978 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10979 &filter_replace_buf);
10980 if (ret != I40E_SUCCESS)
10983 /* Apply the second L2 cloud filter */
10984 memset(&filter_replace, 0,
10985 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10986 memset(&filter_replace_buf, 0,
10987 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10989 /* create L2 filter, input for L2 filter will be L1 filter */
10990 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10991 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10992 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10994 /* Prepare the buffer, 2 entries */
10995 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10996 filter_replace_buf.data[0] |=
10997 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10998 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10999 filter_replace_buf.data[4] |=
11000 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11001 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11002 &filter_replace_buf);
11006 RTE_INIT(i40e_init_log);
11008 i40e_init_log(void)
11010 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11011 if (i40e_logtype_init >= 0)
11012 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11013 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11014 if (i40e_logtype_driver >= 0)
11015 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);