1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct rte_ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static void i40e_dev_alarm_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct rte_ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 static const char *const valid_keys[] = {
402 ETH_I40E_FLOATING_VEB_ARG,
403 ETH_I40E_FLOATING_VEB_LIST_ARG,
404 ETH_I40E_SUPPORT_MULTI_DRIVER,
405 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
406 ETH_I40E_USE_LATEST_VEC,
410 static const struct rte_pci_id pci_id_i40e_map[] = {
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .fw_version_get = i40e_fw_version_get,
459 .dev_infos_get = i40e_dev_info_get,
460 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
461 .vlan_filter_set = i40e_vlan_filter_set,
462 .vlan_tpid_set = i40e_vlan_tpid_set,
463 .vlan_offload_set = i40e_vlan_offload_set,
464 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
465 .vlan_pvid_set = i40e_vlan_pvid_set,
466 .rx_queue_start = i40e_dev_rx_queue_start,
467 .rx_queue_stop = i40e_dev_rx_queue_stop,
468 .tx_queue_start = i40e_dev_tx_queue_start,
469 .tx_queue_stop = i40e_dev_tx_queue_stop,
470 .rx_queue_setup = i40e_dev_rx_queue_setup,
471 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
472 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
473 .rx_queue_release = i40e_dev_rx_queue_release,
474 .rx_queue_count = i40e_dev_rx_queue_count,
475 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
476 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
477 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
478 .tx_queue_setup = i40e_dev_tx_queue_setup,
479 .tx_queue_release = i40e_dev_tx_queue_release,
480 .dev_led_on = i40e_dev_led_on,
481 .dev_led_off = i40e_dev_led_off,
482 .flow_ctrl_get = i40e_flow_ctrl_get,
483 .flow_ctrl_set = i40e_flow_ctrl_set,
484 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
485 .mac_addr_add = i40e_macaddr_add,
486 .mac_addr_remove = i40e_macaddr_remove,
487 .reta_update = i40e_dev_rss_reta_update,
488 .reta_query = i40e_dev_rss_reta_query,
489 .rss_hash_update = i40e_dev_rss_hash_update,
490 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
491 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
492 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
493 .filter_ctrl = i40e_dev_filter_ctrl,
494 .rxq_info_get = i40e_rxq_info_get,
495 .txq_info_get = i40e_txq_info_get,
496 .rx_burst_mode_get = i40e_rx_burst_mode_get,
497 .tx_burst_mode_get = i40e_tx_burst_mode_get,
498 .mirror_rule_set = i40e_mirror_rule_set,
499 .mirror_rule_reset = i40e_mirror_rule_reset,
500 .timesync_enable = i40e_timesync_enable,
501 .timesync_disable = i40e_timesync_disable,
502 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
503 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
504 .get_dcb_info = i40e_dev_get_dcb_info,
505 .timesync_adjust_time = i40e_timesync_adjust_time,
506 .timesync_read_time = i40e_timesync_read_time,
507 .timesync_write_time = i40e_timesync_write_time,
508 .get_reg = i40e_get_regs,
509 .get_eeprom_length = i40e_get_eeprom_length,
510 .get_eeprom = i40e_get_eeprom,
511 .get_module_info = i40e_get_module_info,
512 .get_module_eeprom = i40e_get_module_eeprom,
513 .mac_addr_set = i40e_set_default_mac_addr,
514 .mtu_set = i40e_dev_mtu_set,
515 .tm_ops_get = i40e_tm_ops_get,
516 .tx_done_cleanup = i40e_tx_done_cleanup,
519 /* store statistics names and its offset in stats structure */
520 struct rte_i40e_xstats_name_off {
521 char name[RTE_ETH_XSTATS_NAME_SIZE];
525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
526 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
527 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
528 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
529 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
530 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
531 rx_unknown_protocol)},
532 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
533 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
534 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
535 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
539 sizeof(rte_i40e_stats_strings[0]))
541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
542 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
543 tx_dropped_link_down)},
544 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
545 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
548 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
550 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
554 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
555 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
556 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
557 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
558 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
559 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
575 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
576 mac_short_packet_dropped)},
577 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
580 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
581 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_flow_director_atr_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
595 {"rx_flow_director_sb_match_packets",
596 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
597 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
601 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
603 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
608 sizeof(rte_i40e_hw_port_strings[0]))
610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
611 {"xon_packets", offsetof(struct i40e_hw_port_stats,
613 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
618 sizeof(rte_i40e_rxq_prio_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
625 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
626 priority_xon_2_xoff)},
629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
630 sizeof(rte_i40e_txq_prio_strings[0]))
633 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 char name[RTE_ETH_NAME_MAX_LEN];
637 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
640 if (pci_dev->device.devargs) {
641 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
647 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
648 sizeof(struct i40e_adapter),
649 eth_dev_pci_specific_init, pci_dev,
650 eth_i40e_dev_init, NULL);
652 if (retval || eth_da.nb_representor_ports < 1)
655 /* probe VF representor ports */
656 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
657 pci_dev->device.name);
659 if (pf_ethdev == NULL)
662 for (i = 0; i < eth_da.nb_representor_ports; i++) {
663 struct i40e_vf_representor representor = {
664 .vf_id = eth_da.representor_ports[i],
665 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
666 pf_ethdev->data->dev_private)->switch_domain_id,
667 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
668 pf_ethdev->data->dev_private)
671 /* representor port net_bdf_port */
672 snprintf(name, sizeof(name), "net_%s_representor_%d",
673 pci_dev->device.name, eth_da.representor_ports[i]);
675 retval = rte_eth_dev_create(&pci_dev->device, name,
676 sizeof(struct i40e_vf_representor), NULL, NULL,
677 i40e_vf_representor_init, &representor);
680 PMD_DRV_LOG(ERR, "failed to create i40e vf "
681 "representor %s.", name);
687 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
689 struct rte_eth_dev *ethdev;
691 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
695 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
696 return rte_eth_dev_pci_generic_remove(pci_dev,
697 i40e_vf_representor_uninit);
699 return rte_eth_dev_pci_generic_remove(pci_dev,
700 eth_i40e_dev_uninit);
703 static struct rte_pci_driver rte_i40e_pmd = {
704 .id_table = pci_id_i40e_map,
705 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
706 .probe = eth_i40e_pci_probe,
707 .remove = eth_i40e_pci_remove,
711 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
714 uint32_t ori_reg_val;
715 struct rte_eth_dev *dev;
717 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
718 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
719 i40e_write_rx_ctl(hw, reg_addr, reg_val);
720 if (ori_reg_val != reg_val)
722 "i40e device %s changed global register [0x%08x]."
723 " original: 0x%08x, new: 0x%08x",
724 dev->device->name, reg_addr, ori_reg_val, reg_val);
727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
731 #ifndef I40E_GLQF_ORT
732 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
734 #ifndef I40E_GLQF_PIT
735 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
737 #ifndef I40E_GLQF_L3_MAP
738 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
744 * Initialize registers for parsing packet type of QinQ
745 * This should be removed from code once proper
746 * configuration API is added to avoid configuration conflicts
747 * between ports of the same device.
749 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
750 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
753 static inline void i40e_config_automask(struct i40e_pf *pf)
755 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
758 /* INTENA flag is not auto-cleared for interrupt */
759 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
760 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
761 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
763 /* If support multi-driver, PF will use INT0. */
764 if (!pf->support_multi_driver)
765 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
767 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
770 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
773 * Add a ethertype filter to drop all flow control frames transmitted
777 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
780 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
781 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
782 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
785 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
786 I40E_FLOW_CONTROL_ETHERTYPE, flags,
787 pf->main_vsi_seid, 0,
791 "Failed to add filter to drop flow control frames from VSIs.");
795 floating_veb_list_handler(__rte_unused const char *key,
796 const char *floating_veb_value,
800 unsigned int count = 0;
803 bool *vf_floating_veb = opaque;
805 while (isblank(*floating_veb_value))
806 floating_veb_value++;
808 /* Reset floating VEB configuration for VFs */
809 for (idx = 0; idx < I40E_MAX_VF; idx++)
810 vf_floating_veb[idx] = false;
814 while (isblank(*floating_veb_value))
815 floating_veb_value++;
816 if (*floating_veb_value == '\0')
819 idx = strtoul(floating_veb_value, &end, 10);
820 if (errno || end == NULL)
822 while (isblank(*end))
826 } else if ((*end == ';') || (*end == '\0')) {
828 if (min == I40E_MAX_VF)
830 if (max >= I40E_MAX_VF)
831 max = I40E_MAX_VF - 1;
832 for (idx = min; idx <= max; idx++) {
833 vf_floating_veb[idx] = true;
840 floating_veb_value = end + 1;
841 } while (*end != '\0');
850 config_vf_floating_veb(struct rte_devargs *devargs,
851 uint16_t floating_veb,
852 bool *vf_floating_veb)
854 struct rte_kvargs *kvlist;
856 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
860 /* All the VFs attach to the floating VEB by default
861 * when the floating VEB is enabled.
863 for (i = 0; i < I40E_MAX_VF; i++)
864 vf_floating_veb[i] = true;
869 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
873 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
874 rte_kvargs_free(kvlist);
877 /* When the floating_veb_list parameter exists, all the VFs
878 * will attach to the legacy VEB firstly, then configure VFs
879 * to the floating VEB according to the floating_veb_list.
881 if (rte_kvargs_process(kvlist, floating_veb_list,
882 floating_veb_list_handler,
883 vf_floating_veb) < 0) {
884 rte_kvargs_free(kvlist);
887 rte_kvargs_free(kvlist);
891 i40e_check_floating_handler(__rte_unused const char *key,
893 __rte_unused void *opaque)
895 if (strcmp(value, "1"))
902 is_floating_veb_supported(struct rte_devargs *devargs)
904 struct rte_kvargs *kvlist;
905 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
910 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
914 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
915 rte_kvargs_free(kvlist);
918 /* Floating VEB is enabled when there's key-value:
919 * enable_floating_veb=1
921 if (rte_kvargs_process(kvlist, floating_veb_key,
922 i40e_check_floating_handler, NULL) < 0) {
923 rte_kvargs_free(kvlist);
926 rte_kvargs_free(kvlist);
932 config_floating_veb(struct rte_eth_dev *dev)
934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
938 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
940 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
942 is_floating_veb_supported(pci_dev->device.devargs);
943 config_vf_floating_veb(pci_dev->device.devargs,
945 pf->floating_veb_list);
947 pf->floating_veb = false;
951 #define I40E_L2_TAGS_S_TAG_SHIFT 1
952 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
955 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
958 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
959 char ethertype_hash_name[RTE_HASH_NAMESIZE];
962 struct rte_hash_parameters ethertype_hash_params = {
963 .name = ethertype_hash_name,
964 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
965 .key_len = sizeof(struct i40e_ethertype_filter_input),
966 .hash_func = rte_hash_crc,
967 .hash_func_init_val = 0,
968 .socket_id = rte_socket_id(),
971 /* Initialize ethertype filter rule list and hash */
972 TAILQ_INIT(ðertype_rule->ethertype_list);
973 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
974 "ethertype_%s", dev->device->name);
975 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
976 if (!ethertype_rule->hash_table) {
977 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
980 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
981 sizeof(struct i40e_ethertype_filter *) *
982 I40E_MAX_ETHERTYPE_FILTER_NUM,
984 if (!ethertype_rule->hash_map) {
986 "Failed to allocate memory for ethertype hash map!");
988 goto err_ethertype_hash_map_alloc;
993 err_ethertype_hash_map_alloc:
994 rte_hash_free(ethertype_rule->hash_table);
1000 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1004 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1007 struct rte_hash_parameters tunnel_hash_params = {
1008 .name = tunnel_hash_name,
1009 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1010 .key_len = sizeof(struct i40e_tunnel_filter_input),
1011 .hash_func = rte_hash_crc,
1012 .hash_func_init_val = 0,
1013 .socket_id = rte_socket_id(),
1016 /* Initialize tunnel filter rule list and hash */
1017 TAILQ_INIT(&tunnel_rule->tunnel_list);
1018 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1019 "tunnel_%s", dev->device->name);
1020 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1021 if (!tunnel_rule->hash_table) {
1022 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1025 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1026 sizeof(struct i40e_tunnel_filter *) *
1027 I40E_MAX_TUNNEL_FILTER_NUM,
1029 if (!tunnel_rule->hash_map) {
1031 "Failed to allocate memory for tunnel hash map!");
1033 goto err_tunnel_hash_map_alloc;
1038 err_tunnel_hash_map_alloc:
1039 rte_hash_free(tunnel_rule->hash_table);
1045 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1047 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048 struct i40e_fdir_info *fdir_info = &pf->fdir;
1049 char fdir_hash_name[RTE_HASH_NAMESIZE];
1052 struct rte_hash_parameters fdir_hash_params = {
1053 .name = fdir_hash_name,
1054 .entries = I40E_MAX_FDIR_FILTER_NUM,
1055 .key_len = sizeof(struct i40e_fdir_input),
1056 .hash_func = rte_hash_crc,
1057 .hash_func_init_val = 0,
1058 .socket_id = rte_socket_id(),
1061 /* Initialize flow director filter rule list and hash */
1062 TAILQ_INIT(&fdir_info->fdir_list);
1063 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1064 "fdir_%s", dev->device->name);
1065 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1066 if (!fdir_info->hash_table) {
1067 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1070 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1071 sizeof(struct i40e_fdir_filter *) *
1072 I40E_MAX_FDIR_FILTER_NUM,
1074 if (!fdir_info->hash_map) {
1076 "Failed to allocate memory for fdir hash map!");
1078 goto err_fdir_hash_map_alloc;
1082 err_fdir_hash_map_alloc:
1083 rte_hash_free(fdir_info->hash_table);
1089 i40e_init_customized_info(struct i40e_pf *pf)
1093 /* Initialize customized pctype */
1094 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1095 pf->customized_pctype[i].index = i;
1096 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1097 pf->customized_pctype[i].valid = false;
1100 pf->gtp_support = false;
1101 pf->esp_support = false;
1105 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1108 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1109 struct i40e_queue_regions *info = &pf->queue_region;
1112 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1113 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1115 memset(info, 0, sizeof(struct i40e_queue_regions));
1119 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1124 unsigned long support_multi_driver;
1127 pf = (struct i40e_pf *)opaque;
1130 support_multi_driver = strtoul(value, &end, 10);
1131 if (errno != 0 || end == value || *end != 0) {
1132 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1136 if (support_multi_driver == 1 || support_multi_driver == 0)
1137 pf->support_multi_driver = (bool)support_multi_driver;
1139 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1140 "enable global configuration by default."
1141 ETH_I40E_SUPPORT_MULTI_DRIVER);
1146 i40e_support_multi_driver(struct rte_eth_dev *dev)
1148 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1149 struct rte_kvargs *kvlist;
1152 /* Enable global configuration by default */
1153 pf->support_multi_driver = false;
1155 if (!dev->device->devargs)
1158 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1162 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1163 if (!kvargs_count) {
1164 rte_kvargs_free(kvlist);
1168 if (kvargs_count > 1)
1169 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1170 "the first invalid or last valid one is used !",
1171 ETH_I40E_SUPPORT_MULTI_DRIVER);
1173 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1174 i40e_parse_multi_drv_handler, pf) < 0) {
1175 rte_kvargs_free(kvlist);
1179 rte_kvargs_free(kvlist);
1184 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1185 uint32_t reg_addr, uint64_t reg_val,
1186 struct i40e_asq_cmd_details *cmd_details)
1188 uint64_t ori_reg_val;
1189 struct rte_eth_dev *dev;
1192 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1193 if (ret != I40E_SUCCESS) {
1195 "Fail to debug read from 0x%08x",
1199 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1201 if (ori_reg_val != reg_val)
1202 PMD_DRV_LOG(WARNING,
1203 "i40e device %s changed global register [0x%08x]."
1204 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1205 dev->device->name, reg_addr, ori_reg_val, reg_val);
1207 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1211 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1215 struct i40e_adapter *ad = opaque;
1218 use_latest_vec = atoi(value);
1220 if (use_latest_vec != 0 && use_latest_vec != 1)
1221 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1223 ad->use_latest_vec = (uint8_t)use_latest_vec;
1229 i40e_use_latest_vec(struct rte_eth_dev *dev)
1231 struct i40e_adapter *ad =
1232 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1233 struct rte_kvargs *kvlist;
1236 ad->use_latest_vec = false;
1238 if (!dev->device->devargs)
1241 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1245 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1246 if (!kvargs_count) {
1247 rte_kvargs_free(kvlist);
1251 if (kvargs_count > 1)
1252 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1253 "the first invalid or last valid one is used !",
1254 ETH_I40E_USE_LATEST_VEC);
1256 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1257 i40e_parse_latest_vec_handler, ad) < 0) {
1258 rte_kvargs_free(kvlist);
1262 rte_kvargs_free(kvlist);
1267 read_vf_msg_config(__rte_unused const char *key,
1271 struct i40e_vf_msg_cfg *cfg = opaque;
1273 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1274 &cfg->ignore_second) != 3) {
1275 memset(cfg, 0, sizeof(*cfg));
1276 PMD_DRV_LOG(ERR, "format error! example: "
1277 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1282 * If the message validation function been enabled, the 'period'
1283 * and 'ignore_second' must greater than 0.
1285 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1286 memset(cfg, 0, sizeof(*cfg));
1287 PMD_DRV_LOG(ERR, "%s error! the second and third"
1288 " number must be greater than 0!",
1289 ETH_I40E_VF_MSG_CFG);
1297 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1298 struct i40e_vf_msg_cfg *msg_cfg)
1300 struct rte_kvargs *kvlist;
1304 memset(msg_cfg, 0, sizeof(*msg_cfg));
1306 if (!dev->device->devargs)
1309 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1313 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1317 if (kvargs_count > 1) {
1318 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1319 ETH_I40E_VF_MSG_CFG);
1324 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1325 read_vf_msg_config, msg_cfg) < 0)
1329 rte_kvargs_free(kvlist);
1333 #define I40E_ALARM_INTERVAL 50000 /* us */
1336 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1338 struct rte_pci_device *pci_dev;
1339 struct rte_intr_handle *intr_handle;
1340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342 struct i40e_vsi *vsi;
1345 uint8_t aq_fail = 0;
1347 PMD_INIT_FUNC_TRACE();
1349 dev->dev_ops = &i40e_eth_dev_ops;
1350 dev->rx_pkt_burst = i40e_recv_pkts;
1351 dev->tx_pkt_burst = i40e_xmit_pkts;
1352 dev->tx_pkt_prepare = i40e_prep_pkts;
1354 /* for secondary processes, we don't initialise any further as primary
1355 * has already done this work. Only check we don't need a different
1357 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1358 i40e_set_rx_function(dev);
1359 i40e_set_tx_function(dev);
1362 i40e_set_default_ptype_table(dev);
1363 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1364 intr_handle = &pci_dev->intr_handle;
1366 rte_eth_copy_pci_info(dev, pci_dev);
1368 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1369 pf->adapter->eth_dev = dev;
1370 pf->dev_data = dev->data;
1372 hw->back = I40E_PF_TO_ADAPTER(pf);
1373 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1376 "Hardware is not available, as address is NULL");
1380 hw->vendor_id = pci_dev->id.vendor_id;
1381 hw->device_id = pci_dev->id.device_id;
1382 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1383 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1384 hw->bus.device = pci_dev->addr.devid;
1385 hw->bus.func = pci_dev->addr.function;
1386 hw->adapter_stopped = 0;
1387 hw->adapter_closed = 0;
1389 /* Init switch device pointer */
1390 hw->switch_dev = NULL;
1393 * Switch Tag value should not be identical to either the First Tag
1394 * or Second Tag values. So set something other than common Ethertype
1395 * for internal switching.
1397 hw->switch_tag = 0xffff;
1399 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1400 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1401 PMD_INIT_LOG(ERR, "\nERROR: "
1402 "Firmware recovery mode detected. Limiting functionality.\n"
1403 "Refer to the Intel(R) Ethernet Adapters and Devices "
1404 "User Guide for details on firmware recovery mode.");
1408 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1409 /* Check if need to support multi-driver */
1410 i40e_support_multi_driver(dev);
1411 /* Check if users want the latest supported vec path */
1412 i40e_use_latest_vec(dev);
1414 /* Make sure all is clean before doing PF reset */
1417 /* Reset here to make sure all is clean for each PF */
1418 ret = i40e_pf_reset(hw);
1420 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1424 /* Initialize the shared code (base driver) */
1425 ret = i40e_init_shared_code(hw);
1427 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1431 /* Initialize the parameters for adminq */
1432 i40e_init_adminq_parameter(hw);
1433 ret = i40e_init_adminq(hw);
1434 if (ret != I40E_SUCCESS) {
1435 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1438 /* Firmware of SFP x722 does not support adminq option */
1439 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1440 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1442 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1443 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1444 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1445 ((hw->nvm.version >> 12) & 0xf),
1446 ((hw->nvm.version >> 4) & 0xff),
1447 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1449 /* Initialize the hardware */
1452 i40e_config_automask(pf);
1454 i40e_set_default_pctype_table(dev);
1457 * To work around the NVM issue, initialize registers
1458 * for packet type of QinQ by software.
1459 * It should be removed once issues are fixed in NVM.
1461 if (!pf->support_multi_driver)
1462 i40e_GLQF_reg_init(hw);
1464 /* Initialize the input set for filters (hash and fd) to default value */
1465 i40e_filter_input_set_init(pf);
1467 /* initialise the L3_MAP register */
1468 if (!pf->support_multi_driver) {
1469 ret = i40e_aq_debug_write_global_register(hw,
1470 I40E_GLQF_L3_MAP(40),
1473 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1476 "Global register 0x%08x is changed with 0x28",
1477 I40E_GLQF_L3_MAP(40));
1480 /* Need the special FW version to support floating VEB */
1481 config_floating_veb(dev);
1482 /* Clear PXE mode */
1483 i40e_clear_pxe_mode(hw);
1484 i40e_dev_sync_phy_type(hw);
1487 * On X710, performance number is far from the expectation on recent
1488 * firmware versions. The fix for this issue may not be integrated in
1489 * the following firmware version. So the workaround in software driver
1490 * is needed. It needs to modify the initial values of 3 internal only
1491 * registers. Note that the workaround can be removed when it is fixed
1492 * in firmware in the future.
1494 i40e_configure_registers(hw);
1496 /* Get hw capabilities */
1497 ret = i40e_get_cap(hw);
1498 if (ret != I40E_SUCCESS) {
1499 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1500 goto err_get_capabilities;
1503 /* Initialize parameters for PF */
1504 ret = i40e_pf_parameter_init(dev);
1506 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1507 goto err_parameter_init;
1510 /* Initialize the queue management */
1511 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1513 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1514 goto err_qp_pool_init;
1516 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1517 hw->func_caps.num_msix_vectors - 1);
1519 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1520 goto err_msix_pool_init;
1523 /* Initialize lan hmc */
1524 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1525 hw->func_caps.num_rx_qp, 0, 0);
1526 if (ret != I40E_SUCCESS) {
1527 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1528 goto err_init_lan_hmc;
1531 /* Configure lan hmc */
1532 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1533 if (ret != I40E_SUCCESS) {
1534 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1535 goto err_configure_lan_hmc;
1538 /* Get and check the mac address */
1539 i40e_get_mac_addr(hw, hw->mac.addr);
1540 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1541 PMD_INIT_LOG(ERR, "mac address is not valid");
1543 goto err_get_mac_addr;
1545 /* Copy the permanent MAC address */
1546 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1547 (struct rte_ether_addr *)hw->mac.perm_addr);
1549 /* Disable flow control */
1550 hw->fc.requested_mode = I40E_FC_NONE;
1551 i40e_set_fc(hw, &aq_fail, TRUE);
1553 /* Set the global registers with default ether type value */
1554 if (!pf->support_multi_driver) {
1555 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1556 RTE_ETHER_TYPE_VLAN);
1557 if (ret != I40E_SUCCESS) {
1559 "Failed to set the default outer "
1561 goto err_setup_pf_switch;
1565 /* PF setup, which includes VSI setup */
1566 ret = i40e_pf_setup(pf);
1568 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1569 goto err_setup_pf_switch;
1574 /* Disable double vlan by default */
1575 i40e_vsi_config_double_vlan(vsi, FALSE);
1577 /* Disable S-TAG identification when floating_veb is disabled */
1578 if (!pf->floating_veb) {
1579 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1580 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1581 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1582 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1586 if (!vsi->max_macaddrs)
1587 len = RTE_ETHER_ADDR_LEN;
1589 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1591 /* Should be after VSI initialized */
1592 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1593 if (!dev->data->mac_addrs) {
1595 "Failed to allocated memory for storing mac address");
1598 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1599 &dev->data->mac_addrs[0]);
1601 /* Pass the information to the rte_eth_dev_close() that it should also
1602 * release the private port resources.
1604 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1606 /* Init dcb to sw mode by default */
1607 ret = i40e_dcb_init_configure(dev, TRUE);
1608 if (ret != I40E_SUCCESS) {
1609 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1610 pf->flags &= ~I40E_FLAG_DCB;
1612 /* Update HW struct after DCB configuration */
1615 /* initialize pf host driver to setup SRIOV resource if applicable */
1616 i40e_pf_host_init(dev);
1618 /* register callback func to eal lib */
1619 rte_intr_callback_register(intr_handle,
1620 i40e_dev_interrupt_handler, dev);
1622 /* configure and enable device interrupt */
1623 i40e_pf_config_irq0(hw, TRUE);
1624 i40e_pf_enable_irq0(hw);
1626 /* enable uio intr after callback register */
1627 rte_intr_enable(intr_handle);
1629 /* By default disable flexible payload in global configuration */
1630 if (!pf->support_multi_driver)
1631 i40e_flex_payload_reg_set_default(hw);
1634 * Add an ethertype filter to drop all flow control frames transmitted
1635 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1638 i40e_add_tx_flow_control_drop_filter(pf);
1640 /* Set the max frame size to 0x2600 by default,
1641 * in case other drivers changed the default value.
1643 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1645 /* initialize mirror rule list */
1646 TAILQ_INIT(&pf->mirror_list);
1648 /* initialize RSS rule list */
1649 TAILQ_INIT(&pf->rss_config_list);
1651 /* initialize Traffic Manager configuration */
1652 i40e_tm_conf_init(dev);
1654 /* Initialize customized information */
1655 i40e_init_customized_info(pf);
1657 ret = i40e_init_ethtype_filter_list(dev);
1659 goto err_init_ethtype_filter_list;
1660 ret = i40e_init_tunnel_filter_list(dev);
1662 goto err_init_tunnel_filter_list;
1663 ret = i40e_init_fdir_filter_list(dev);
1665 goto err_init_fdir_filter_list;
1667 /* initialize queue region configuration */
1668 i40e_init_queue_region_conf(dev);
1670 /* initialize RSS configuration from rte_flow */
1671 memset(&pf->rss_info, 0,
1672 sizeof(struct i40e_rte_flow_rss_conf));
1674 /* reset all stats of the device, including pf and main vsi */
1675 i40e_dev_stats_reset(dev);
1679 err_init_fdir_filter_list:
1680 rte_free(pf->tunnel.hash_table);
1681 rte_free(pf->tunnel.hash_map);
1682 err_init_tunnel_filter_list:
1683 rte_free(pf->ethertype.hash_table);
1684 rte_free(pf->ethertype.hash_map);
1685 err_init_ethtype_filter_list:
1686 rte_free(dev->data->mac_addrs);
1687 dev->data->mac_addrs = NULL;
1689 i40e_vsi_release(pf->main_vsi);
1690 err_setup_pf_switch:
1692 err_configure_lan_hmc:
1693 (void)i40e_shutdown_lan_hmc(hw);
1695 i40e_res_pool_destroy(&pf->msix_pool);
1697 i40e_res_pool_destroy(&pf->qp_pool);
1700 err_get_capabilities:
1701 (void)i40e_shutdown_adminq(hw);
1707 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1709 struct i40e_ethertype_filter *p_ethertype;
1710 struct i40e_ethertype_rule *ethertype_rule;
1712 ethertype_rule = &pf->ethertype;
1713 /* Remove all ethertype filter rules and hash */
1714 if (ethertype_rule->hash_map)
1715 rte_free(ethertype_rule->hash_map);
1716 if (ethertype_rule->hash_table)
1717 rte_hash_free(ethertype_rule->hash_table);
1719 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1720 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1721 p_ethertype, rules);
1722 rte_free(p_ethertype);
1727 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1729 struct i40e_tunnel_filter *p_tunnel;
1730 struct i40e_tunnel_rule *tunnel_rule;
1732 tunnel_rule = &pf->tunnel;
1733 /* Remove all tunnel director rules and hash */
1734 if (tunnel_rule->hash_map)
1735 rte_free(tunnel_rule->hash_map);
1736 if (tunnel_rule->hash_table)
1737 rte_hash_free(tunnel_rule->hash_table);
1739 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1740 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1746 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1748 struct i40e_fdir_filter *p_fdir;
1749 struct i40e_fdir_info *fdir_info;
1751 fdir_info = &pf->fdir;
1752 /* Remove all flow director rules and hash */
1753 if (fdir_info->hash_map)
1754 rte_free(fdir_info->hash_map);
1755 if (fdir_info->hash_table)
1756 rte_hash_free(fdir_info->hash_table);
1758 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1759 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1764 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1767 * Disable by default flexible payload
1768 * for corresponding L2/L3/L4 layers.
1770 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1771 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1772 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1776 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1780 PMD_INIT_FUNC_TRACE();
1782 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1785 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787 if (hw->adapter_closed == 0)
1788 i40e_dev_close(dev);
1794 i40e_dev_configure(struct rte_eth_dev *dev)
1796 struct i40e_adapter *ad =
1797 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1803 ret = i40e_dev_sync_phy_type(hw);
1807 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1808 * bulk allocation or vector Rx preconditions we will reset it.
1810 ad->rx_bulk_alloc_allowed = true;
1811 ad->rx_vec_allowed = true;
1812 ad->tx_simple_allowed = true;
1813 ad->tx_vec_allowed = true;
1815 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1816 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1818 /* Only legacy filter API needs the following fdir config. So when the
1819 * legacy filter API is deprecated, the following codes should also be
1822 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1823 ret = i40e_fdir_setup(pf);
1824 if (ret != I40E_SUCCESS) {
1825 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1828 ret = i40e_fdir_configure(dev);
1830 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1834 i40e_fdir_teardown(pf);
1836 ret = i40e_dev_init_vlan(dev);
1841 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1842 * RSS setting have different requirements.
1843 * General PMD driver call sequence are NIC init, configure,
1844 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1845 * will try to lookup the VSI that specific queue belongs to if VMDQ
1846 * applicable. So, VMDQ setting has to be done before
1847 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1848 * For RSS setting, it will try to calculate actual configured RX queue
1849 * number, which will be available after rx_queue_setup(). dev_start()
1850 * function is good to place RSS setup.
1852 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1853 ret = i40e_vmdq_setup(dev);
1858 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1859 ret = i40e_dcb_setup(dev);
1861 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1866 TAILQ_INIT(&pf->flow_list);
1871 /* need to release vmdq resource if exists */
1872 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1873 i40e_vsi_release(pf->vmdq[i].vsi);
1874 pf->vmdq[i].vsi = NULL;
1879 /* Need to release fdir resource if exists.
1880 * Only legacy filter API needs the following fdir config. So when the
1881 * legacy filter API is deprecated, the following code should also be
1884 i40e_fdir_teardown(pf);
1889 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1891 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1892 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1893 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1894 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1895 uint16_t msix_vect = vsi->msix_intr;
1898 for (i = 0; i < vsi->nb_qps; i++) {
1899 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1900 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1904 if (vsi->type != I40E_VSI_SRIOV) {
1905 if (!rte_intr_allow_others(intr_handle)) {
1906 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1907 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1909 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1912 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1913 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1915 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1920 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1921 vsi->user_param + (msix_vect - 1);
1923 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1924 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1926 I40E_WRITE_FLUSH(hw);
1930 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1931 int base_queue, int nb_queue,
1936 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1937 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1939 /* Bind all RX queues to allocated MSIX interrupt */
1940 for (i = 0; i < nb_queue; i++) {
1941 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1942 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1943 ((base_queue + i + 1) <<
1944 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1945 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1946 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1948 if (i == nb_queue - 1)
1949 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1950 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1953 /* Write first RX queue to Link list register as the head element */
1954 if (vsi->type != I40E_VSI_SRIOV) {
1956 i40e_calc_itr_interval(1, pf->support_multi_driver);
1958 if (msix_vect == I40E_MISC_VEC_ID) {
1959 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1961 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1963 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1965 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1968 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1970 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1972 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1974 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1981 if (msix_vect == I40E_MISC_VEC_ID) {
1983 I40E_VPINT_LNKLST0(vsi->user_param),
1985 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1987 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1989 /* num_msix_vectors_vf needs to minus irq0 */
1990 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1991 vsi->user_param + (msix_vect - 1);
1993 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1995 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1997 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2001 I40E_WRITE_FLUSH(hw);
2005 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2007 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011 uint16_t msix_vect = vsi->msix_intr;
2012 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2013 uint16_t queue_idx = 0;
2017 for (i = 0; i < vsi->nb_qps; i++) {
2018 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2019 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2022 /* VF bind interrupt */
2023 if (vsi->type == I40E_VSI_SRIOV) {
2024 __vsi_queues_bind_intr(vsi, msix_vect,
2025 vsi->base_queue, vsi->nb_qps,
2030 /* PF & VMDq bind interrupt */
2031 if (rte_intr_dp_is_en(intr_handle)) {
2032 if (vsi->type == I40E_VSI_MAIN) {
2035 } else if (vsi->type == I40E_VSI_VMDQ2) {
2036 struct i40e_vsi *main_vsi =
2037 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2038 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2043 for (i = 0; i < vsi->nb_used_qps; i++) {
2045 if (!rte_intr_allow_others(intr_handle))
2046 /* allow to share MISC_VEC_ID */
2047 msix_vect = I40E_MISC_VEC_ID;
2049 /* no enough msix_vect, map all to one */
2050 __vsi_queues_bind_intr(vsi, msix_vect,
2051 vsi->base_queue + i,
2052 vsi->nb_used_qps - i,
2054 for (; !!record && i < vsi->nb_used_qps; i++)
2055 intr_handle->intr_vec[queue_idx + i] =
2059 /* 1:1 queue/msix_vect mapping */
2060 __vsi_queues_bind_intr(vsi, msix_vect,
2061 vsi->base_queue + i, 1,
2064 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2072 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2074 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2075 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2076 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2077 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2078 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2079 uint16_t msix_intr, i;
2081 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2082 for (i = 0; i < vsi->nb_msix; i++) {
2083 msix_intr = vsi->msix_intr + i;
2084 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2085 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2086 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2087 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2090 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2091 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2092 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2093 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2095 I40E_WRITE_FLUSH(hw);
2099 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2101 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2102 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2103 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2104 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2105 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2106 uint16_t msix_intr, i;
2108 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2109 for (i = 0; i < vsi->nb_msix; i++) {
2110 msix_intr = vsi->msix_intr + i;
2111 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2112 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2115 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2116 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2118 I40E_WRITE_FLUSH(hw);
2121 static inline uint8_t
2122 i40e_parse_link_speeds(uint16_t link_speeds)
2124 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2126 if (link_speeds & ETH_LINK_SPEED_40G)
2127 link_speed |= I40E_LINK_SPEED_40GB;
2128 if (link_speeds & ETH_LINK_SPEED_25G)
2129 link_speed |= I40E_LINK_SPEED_25GB;
2130 if (link_speeds & ETH_LINK_SPEED_20G)
2131 link_speed |= I40E_LINK_SPEED_20GB;
2132 if (link_speeds & ETH_LINK_SPEED_10G)
2133 link_speed |= I40E_LINK_SPEED_10GB;
2134 if (link_speeds & ETH_LINK_SPEED_1G)
2135 link_speed |= I40E_LINK_SPEED_1GB;
2136 if (link_speeds & ETH_LINK_SPEED_100M)
2137 link_speed |= I40E_LINK_SPEED_100MB;
2143 i40e_phy_conf_link(struct i40e_hw *hw,
2145 uint8_t force_speed,
2148 enum i40e_status_code status;
2149 struct i40e_aq_get_phy_abilities_resp phy_ab;
2150 struct i40e_aq_set_phy_config phy_conf;
2151 enum i40e_aq_phy_type cnt;
2152 uint8_t avail_speed;
2153 uint32_t phy_type_mask = 0;
2155 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2156 I40E_AQ_PHY_FLAG_PAUSE_RX |
2157 I40E_AQ_PHY_FLAG_PAUSE_RX |
2158 I40E_AQ_PHY_FLAG_LOW_POWER;
2161 /* To get phy capabilities of available speeds. */
2162 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2165 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2169 avail_speed = phy_ab.link_speed;
2171 /* To get the current phy config. */
2172 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2175 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2180 /* If link needs to go up and it is in autoneg mode the speed is OK,
2181 * no need to set up again.
2183 if (is_up && phy_ab.phy_type != 0 &&
2184 abilities & I40E_AQ_PHY_AN_ENABLED &&
2185 phy_ab.link_speed != 0)
2186 return I40E_SUCCESS;
2188 memset(&phy_conf, 0, sizeof(phy_conf));
2190 /* bits 0-2 use the values from get_phy_abilities_resp */
2192 abilities |= phy_ab.abilities & mask;
2194 phy_conf.abilities = abilities;
2196 /* If link needs to go up, but the force speed is not supported,
2197 * Warn users and config the default available speeds.
2199 if (is_up && !(force_speed & avail_speed)) {
2200 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2201 phy_conf.link_speed = avail_speed;
2203 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2206 /* PHY type mask needs to include each type except PHY type extension */
2207 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2208 phy_type_mask |= 1 << cnt;
2210 /* use get_phy_abilities_resp value for the rest */
2211 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2212 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2213 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2214 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2215 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2216 phy_conf.eee_capability = phy_ab.eee_capability;
2217 phy_conf.eeer = phy_ab.eeer_val;
2218 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2220 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2221 phy_ab.abilities, phy_ab.link_speed);
2222 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2223 phy_conf.abilities, phy_conf.link_speed);
2225 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2229 return I40E_SUCCESS;
2233 i40e_apply_link_speed(struct rte_eth_dev *dev)
2236 uint8_t abilities = 0;
2237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 struct rte_eth_conf *conf = &dev->data->dev_conf;
2240 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2241 I40E_AQ_PHY_LINK_ENABLED;
2243 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2244 conf->link_speeds = ETH_LINK_SPEED_40G |
2245 ETH_LINK_SPEED_25G |
2246 ETH_LINK_SPEED_20G |
2247 ETH_LINK_SPEED_10G |
2249 ETH_LINK_SPEED_100M;
2251 abilities |= I40E_AQ_PHY_AN_ENABLED;
2253 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2255 speed = i40e_parse_link_speeds(conf->link_speeds);
2257 return i40e_phy_conf_link(hw, abilities, speed, true);
2261 i40e_dev_start(struct rte_eth_dev *dev)
2263 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2264 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265 struct i40e_vsi *main_vsi = pf->main_vsi;
2267 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2268 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2269 uint32_t intr_vector = 0;
2270 struct i40e_vsi *vsi;
2271 uint16_t nb_rxq, nb_txq;
2273 hw->adapter_stopped = 0;
2275 rte_intr_disable(intr_handle);
2277 if ((rte_intr_cap_multiple(intr_handle) ||
2278 !RTE_ETH_DEV_SRIOV(dev).active) &&
2279 dev->data->dev_conf.intr_conf.rxq != 0) {
2280 intr_vector = dev->data->nb_rx_queues;
2281 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2286 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2287 intr_handle->intr_vec =
2288 rte_zmalloc("intr_vec",
2289 dev->data->nb_rx_queues * sizeof(int),
2291 if (!intr_handle->intr_vec) {
2293 "Failed to allocate %d rx_queues intr_vec",
2294 dev->data->nb_rx_queues);
2299 /* Initialize VSI */
2300 ret = i40e_dev_rxtx_init(pf);
2301 if (ret != I40E_SUCCESS) {
2302 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2306 /* Map queues with MSIX interrupt */
2307 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2308 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2309 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2310 i40e_vsi_enable_queues_intr(main_vsi);
2312 /* Map VMDQ VSI queues with MSIX interrupt */
2313 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2314 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2315 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2316 I40E_ITR_INDEX_DEFAULT);
2317 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2320 /* enable FDIR MSIX interrupt */
2321 if (pf->fdir.fdir_vsi) {
2322 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2323 I40E_ITR_INDEX_NONE);
2324 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2327 /* Enable all queues which have been configured */
2328 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2329 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2334 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2335 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2340 /* Enable receiving broadcast packets */
2341 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2342 if (ret != I40E_SUCCESS)
2343 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2345 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2346 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2348 if (ret != I40E_SUCCESS)
2349 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2352 /* Enable the VLAN promiscuous mode. */
2354 for (i = 0; i < pf->vf_num; i++) {
2355 vsi = pf->vfs[i].vsi;
2356 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2361 /* Enable mac loopback mode */
2362 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2363 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2364 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2365 if (ret != I40E_SUCCESS) {
2366 PMD_DRV_LOG(ERR, "fail to set loopback link");
2371 /* Apply link configure */
2372 ret = i40e_apply_link_speed(dev);
2373 if (I40E_SUCCESS != ret) {
2374 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2378 if (!rte_intr_allow_others(intr_handle)) {
2379 rte_intr_callback_unregister(intr_handle,
2380 i40e_dev_interrupt_handler,
2382 /* configure and enable device interrupt */
2383 i40e_pf_config_irq0(hw, FALSE);
2384 i40e_pf_enable_irq0(hw);
2386 if (dev->data->dev_conf.intr_conf.lsc != 0)
2388 "lsc won't enable because of no intr multiplex");
2390 ret = i40e_aq_set_phy_int_mask(hw,
2391 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2392 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2393 I40E_AQ_EVENT_MEDIA_NA), NULL);
2394 if (ret != I40E_SUCCESS)
2395 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2397 /* Call get_link_info aq commond to enable/disable LSE */
2398 i40e_dev_link_update(dev, 0);
2401 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2402 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2403 i40e_dev_alarm_handler, dev);
2405 /* enable uio intr after callback register */
2406 rte_intr_enable(intr_handle);
2409 i40e_filter_restore(pf);
2411 if (pf->tm_conf.root && !pf->tm_conf.committed)
2412 PMD_DRV_LOG(WARNING,
2413 "please call hierarchy_commit() "
2414 "before starting the port");
2416 return I40E_SUCCESS;
2419 for (i = 0; i < nb_txq; i++)
2420 i40e_dev_tx_queue_stop(dev, i);
2422 for (i = 0; i < nb_rxq; i++)
2423 i40e_dev_rx_queue_stop(dev, i);
2429 i40e_dev_stop(struct rte_eth_dev *dev)
2431 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2432 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433 struct i40e_vsi *main_vsi = pf->main_vsi;
2434 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2435 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2438 if (hw->adapter_stopped == 1)
2441 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2442 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2443 rte_intr_enable(intr_handle);
2446 /* Disable all queues */
2447 for (i = 0; i < dev->data->nb_tx_queues; i++)
2448 i40e_dev_tx_queue_stop(dev, i);
2450 for (i = 0; i < dev->data->nb_rx_queues; i++)
2451 i40e_dev_rx_queue_stop(dev, i);
2453 /* un-map queues with interrupt registers */
2454 i40e_vsi_disable_queues_intr(main_vsi);
2455 i40e_vsi_queues_unbind_intr(main_vsi);
2457 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2458 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2459 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2462 if (pf->fdir.fdir_vsi) {
2463 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2464 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2466 /* Clear all queues and release memory */
2467 i40e_dev_clear_queues(dev);
2470 i40e_dev_set_link_down(dev);
2472 if (!rte_intr_allow_others(intr_handle))
2473 /* resume to the default handler */
2474 rte_intr_callback_register(intr_handle,
2475 i40e_dev_interrupt_handler,
2478 /* Clean datapath event and queue/vec mapping */
2479 rte_intr_efd_disable(intr_handle);
2480 if (intr_handle->intr_vec) {
2481 rte_free(intr_handle->intr_vec);
2482 intr_handle->intr_vec = NULL;
2485 /* reset hierarchy commit */
2486 pf->tm_conf.committed = false;
2488 hw->adapter_stopped = 1;
2490 pf->adapter->rss_reta_updated = 0;
2494 i40e_dev_close(struct rte_eth_dev *dev)
2496 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2497 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2499 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2500 struct i40e_mirror_rule *p_mirror;
2501 struct i40e_filter_control_settings settings;
2502 struct rte_flow *p_flow;
2506 uint8_t aq_fail = 0;
2509 PMD_INIT_FUNC_TRACE();
2511 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2513 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2518 /* Remove all mirror rules */
2519 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2520 ret = i40e_aq_del_mirror_rule(hw,
2521 pf->main_vsi->veb->seid,
2522 p_mirror->rule_type,
2524 p_mirror->num_entries,
2527 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2528 "status = %d, aq_err = %d.", ret,
2529 hw->aq.asq_last_status);
2531 /* remove mirror software resource anyway */
2532 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2534 pf->nb_mirror_rule--;
2537 i40e_dev_free_queues(dev);
2539 /* Disable interrupt */
2540 i40e_pf_disable_irq0(hw);
2541 rte_intr_disable(intr_handle);
2544 * Only legacy filter API needs the following fdir config. So when the
2545 * legacy filter API is deprecated, the following code should also be
2548 i40e_fdir_teardown(pf);
2550 /* shutdown and destroy the HMC */
2551 i40e_shutdown_lan_hmc(hw);
2553 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2554 i40e_vsi_release(pf->vmdq[i].vsi);
2555 pf->vmdq[i].vsi = NULL;
2560 /* release all the existing VSIs and VEBs */
2561 i40e_vsi_release(pf->main_vsi);
2563 /* shutdown the adminq */
2564 i40e_aq_queue_shutdown(hw, true);
2565 i40e_shutdown_adminq(hw);
2567 i40e_res_pool_destroy(&pf->qp_pool);
2568 i40e_res_pool_destroy(&pf->msix_pool);
2570 /* Disable flexible payload in global configuration */
2571 if (!pf->support_multi_driver)
2572 i40e_flex_payload_reg_set_default(hw);
2574 /* force a PF reset to clean anything leftover */
2575 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2576 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2577 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2578 I40E_WRITE_FLUSH(hw);
2580 dev->dev_ops = NULL;
2581 dev->rx_pkt_burst = NULL;
2582 dev->tx_pkt_burst = NULL;
2584 /* Clear PXE mode */
2585 i40e_clear_pxe_mode(hw);
2587 /* Unconfigure filter control */
2588 memset(&settings, 0, sizeof(settings));
2589 ret = i40e_set_filter_control(hw, &settings);
2591 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2594 /* Disable flow control */
2595 hw->fc.requested_mode = I40E_FC_NONE;
2596 i40e_set_fc(hw, &aq_fail, TRUE);
2598 /* uninitialize pf host driver */
2599 i40e_pf_host_uninit(dev);
2602 ret = rte_intr_callback_unregister(intr_handle,
2603 i40e_dev_interrupt_handler, dev);
2604 if (ret >= 0 || ret == -ENOENT) {
2606 } else if (ret != -EAGAIN) {
2608 "intr callback unregister failed: %d",
2611 i40e_msec_delay(500);
2612 } while (retries++ < 5);
2614 i40e_rm_ethtype_filter_list(pf);
2615 i40e_rm_tunnel_filter_list(pf);
2616 i40e_rm_fdir_filter_list(pf);
2618 /* Remove all flows */
2619 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2620 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2624 /* Remove all Traffic Manager configuration */
2625 i40e_tm_conf_uninit(dev);
2627 hw->adapter_closed = 1;
2631 * Reset PF device only to re-initialize resources in PMD layer
2634 i40e_dev_reset(struct rte_eth_dev *dev)
2638 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2639 * its VF to make them align with it. The detailed notification
2640 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2641 * To avoid unexpected behavior in VF, currently reset of PF with
2642 * SR-IOV activation is not supported. It might be supported later.
2644 if (dev->data->sriov.active)
2647 ret = eth_i40e_dev_uninit(dev);
2651 ret = eth_i40e_dev_init(dev, NULL);
2657 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2659 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661 struct i40e_vsi *vsi = pf->main_vsi;
2664 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2666 if (status != I40E_SUCCESS) {
2667 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2671 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2673 if (status != I40E_SUCCESS) {
2674 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2675 /* Rollback unicast promiscuous mode */
2676 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2685 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689 struct i40e_vsi *vsi = pf->main_vsi;
2692 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2694 if (status != I40E_SUCCESS) {
2695 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2699 /* must remain in all_multicast mode */
2700 if (dev->data->all_multicast == 1)
2703 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2705 if (status != I40E_SUCCESS) {
2706 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2707 /* Rollback unicast promiscuous mode */
2708 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2717 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721 struct i40e_vsi *vsi = pf->main_vsi;
2724 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2725 if (ret != I40E_SUCCESS) {
2726 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2734 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2736 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738 struct i40e_vsi *vsi = pf->main_vsi;
2741 if (dev->data->promiscuous == 1)
2742 return 0; /* must remain in all_multicast mode */
2744 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2745 vsi->seid, FALSE, NULL);
2746 if (ret != I40E_SUCCESS) {
2747 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2755 * Set device link up.
2758 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2760 /* re-apply link speed setting */
2761 return i40e_apply_link_speed(dev);
2765 * Set device link down.
2768 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2770 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2771 uint8_t abilities = 0;
2772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2775 return i40e_phy_conf_link(hw, abilities, speed, false);
2778 static __rte_always_inline void
2779 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2781 /* Link status registers and values*/
2782 #define I40E_PRTMAC_LINKSTA 0x001E2420
2783 #define I40E_REG_LINK_UP 0x40000080
2784 #define I40E_PRTMAC_MACC 0x001E24E0
2785 #define I40E_REG_MACC_25GB 0x00020000
2786 #define I40E_REG_SPEED_MASK 0x38000000
2787 #define I40E_REG_SPEED_0 0x00000000
2788 #define I40E_REG_SPEED_1 0x08000000
2789 #define I40E_REG_SPEED_2 0x10000000
2790 #define I40E_REG_SPEED_3 0x18000000
2791 #define I40E_REG_SPEED_4 0x20000000
2792 uint32_t link_speed;
2795 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2796 link_speed = reg_val & I40E_REG_SPEED_MASK;
2797 reg_val &= I40E_REG_LINK_UP;
2798 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2800 if (unlikely(link->link_status == 0))
2803 /* Parse the link status */
2804 switch (link_speed) {
2805 case I40E_REG_SPEED_0:
2806 link->link_speed = ETH_SPEED_NUM_100M;
2808 case I40E_REG_SPEED_1:
2809 link->link_speed = ETH_SPEED_NUM_1G;
2811 case I40E_REG_SPEED_2:
2812 if (hw->mac.type == I40E_MAC_X722)
2813 link->link_speed = ETH_SPEED_NUM_2_5G;
2815 link->link_speed = ETH_SPEED_NUM_10G;
2817 case I40E_REG_SPEED_3:
2818 if (hw->mac.type == I40E_MAC_X722) {
2819 link->link_speed = ETH_SPEED_NUM_5G;
2821 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2823 if (reg_val & I40E_REG_MACC_25GB)
2824 link->link_speed = ETH_SPEED_NUM_25G;
2826 link->link_speed = ETH_SPEED_NUM_40G;
2829 case I40E_REG_SPEED_4:
2830 if (hw->mac.type == I40E_MAC_X722)
2831 link->link_speed = ETH_SPEED_NUM_10G;
2833 link->link_speed = ETH_SPEED_NUM_20G;
2836 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2841 static __rte_always_inline void
2842 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2843 bool enable_lse, int wait_to_complete)
2845 #define CHECK_INTERVAL 100 /* 100ms */
2846 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2847 uint32_t rep_cnt = MAX_REPEAT_TIME;
2848 struct i40e_link_status link_status;
2851 memset(&link_status, 0, sizeof(link_status));
2854 memset(&link_status, 0, sizeof(link_status));
2856 /* Get link status information from hardware */
2857 status = i40e_aq_get_link_info(hw, enable_lse,
2858 &link_status, NULL);
2859 if (unlikely(status != I40E_SUCCESS)) {
2860 link->link_speed = ETH_SPEED_NUM_NONE;
2861 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2862 PMD_DRV_LOG(ERR, "Failed to get link info");
2866 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2867 if (!wait_to_complete || link->link_status)
2870 rte_delay_ms(CHECK_INTERVAL);
2871 } while (--rep_cnt);
2873 /* Parse the link status */
2874 switch (link_status.link_speed) {
2875 case I40E_LINK_SPEED_100MB:
2876 link->link_speed = ETH_SPEED_NUM_100M;
2878 case I40E_LINK_SPEED_1GB:
2879 link->link_speed = ETH_SPEED_NUM_1G;
2881 case I40E_LINK_SPEED_10GB:
2882 link->link_speed = ETH_SPEED_NUM_10G;
2884 case I40E_LINK_SPEED_20GB:
2885 link->link_speed = ETH_SPEED_NUM_20G;
2887 case I40E_LINK_SPEED_25GB:
2888 link->link_speed = ETH_SPEED_NUM_25G;
2890 case I40E_LINK_SPEED_40GB:
2891 link->link_speed = ETH_SPEED_NUM_40G;
2894 link->link_speed = ETH_SPEED_NUM_NONE;
2900 i40e_dev_link_update(struct rte_eth_dev *dev,
2901 int wait_to_complete)
2903 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904 struct rte_eth_link link;
2905 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2908 memset(&link, 0, sizeof(link));
2910 /* i40e uses full duplex only */
2911 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2912 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2913 ETH_LINK_SPEED_FIXED);
2915 if (!wait_to_complete && !enable_lse)
2916 update_link_reg(hw, &link);
2918 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2921 rte_eth_linkstatus_get(hw->switch_dev, &link);
2923 ret = rte_eth_linkstatus_set(dev, &link);
2924 i40e_notify_all_vfs_link_status(dev);
2929 /* Get all the statistics of a VSI */
2931 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2933 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2934 struct i40e_eth_stats *nes = &vsi->eth_stats;
2935 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2936 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2938 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2939 vsi->offset_loaded, &oes->rx_bytes,
2941 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2942 vsi->offset_loaded, &oes->rx_unicast,
2944 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2945 vsi->offset_loaded, &oes->rx_multicast,
2946 &nes->rx_multicast);
2947 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2948 vsi->offset_loaded, &oes->rx_broadcast,
2949 &nes->rx_broadcast);
2950 /* exclude CRC bytes */
2951 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2952 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2954 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2955 &oes->rx_discards, &nes->rx_discards);
2956 /* GLV_REPC not supported */
2957 /* GLV_RMPC not supported */
2958 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2959 &oes->rx_unknown_protocol,
2960 &nes->rx_unknown_protocol);
2961 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2962 vsi->offset_loaded, &oes->tx_bytes,
2964 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2965 vsi->offset_loaded, &oes->tx_unicast,
2967 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2968 vsi->offset_loaded, &oes->tx_multicast,
2969 &nes->tx_multicast);
2970 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2971 vsi->offset_loaded, &oes->tx_broadcast,
2972 &nes->tx_broadcast);
2973 /* GLV_TDPC not supported */
2974 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2975 &oes->tx_errors, &nes->tx_errors);
2976 vsi->offset_loaded = true;
2978 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2980 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2981 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2982 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2983 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2984 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2985 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2986 nes->rx_unknown_protocol);
2987 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2988 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2989 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2990 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2991 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2992 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2993 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2998 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3001 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3002 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3004 /* Get rx/tx bytes of internal transfer packets */
3005 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3006 I40E_GLV_GORCL(hw->port),
3008 &pf->internal_stats_offset.rx_bytes,
3009 &pf->internal_stats.rx_bytes);
3011 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3012 I40E_GLV_GOTCL(hw->port),
3014 &pf->internal_stats_offset.tx_bytes,
3015 &pf->internal_stats.tx_bytes);
3016 /* Get total internal rx packet count */
3017 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3018 I40E_GLV_UPRCL(hw->port),
3020 &pf->internal_stats_offset.rx_unicast,
3021 &pf->internal_stats.rx_unicast);
3022 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3023 I40E_GLV_MPRCL(hw->port),
3025 &pf->internal_stats_offset.rx_multicast,
3026 &pf->internal_stats.rx_multicast);
3027 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3028 I40E_GLV_BPRCL(hw->port),
3030 &pf->internal_stats_offset.rx_broadcast,
3031 &pf->internal_stats.rx_broadcast);
3032 /* Get total internal tx packet count */
3033 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3034 I40E_GLV_UPTCL(hw->port),
3036 &pf->internal_stats_offset.tx_unicast,
3037 &pf->internal_stats.tx_unicast);
3038 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3039 I40E_GLV_MPTCL(hw->port),
3041 &pf->internal_stats_offset.tx_multicast,
3042 &pf->internal_stats.tx_multicast);
3043 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3044 I40E_GLV_BPTCL(hw->port),
3046 &pf->internal_stats_offset.tx_broadcast,
3047 &pf->internal_stats.tx_broadcast);
3049 /* exclude CRC size */
3050 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3051 pf->internal_stats.rx_multicast +
3052 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3054 /* Get statistics of struct i40e_eth_stats */
3055 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3056 I40E_GLPRT_GORCL(hw->port),
3057 pf->offset_loaded, &os->eth.rx_bytes,
3059 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3060 I40E_GLPRT_UPRCL(hw->port),
3061 pf->offset_loaded, &os->eth.rx_unicast,
3062 &ns->eth.rx_unicast);
3063 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3064 I40E_GLPRT_MPRCL(hw->port),
3065 pf->offset_loaded, &os->eth.rx_multicast,
3066 &ns->eth.rx_multicast);
3067 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3068 I40E_GLPRT_BPRCL(hw->port),
3069 pf->offset_loaded, &os->eth.rx_broadcast,
3070 &ns->eth.rx_broadcast);
3071 /* Workaround: CRC size should not be included in byte statistics,
3072 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3075 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3076 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3078 /* exclude internal rx bytes
3079 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3080 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3082 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3084 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3085 ns->eth.rx_bytes = 0;
3087 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3089 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3090 ns->eth.rx_unicast = 0;
3092 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3094 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3095 ns->eth.rx_multicast = 0;
3097 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3099 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3100 ns->eth.rx_broadcast = 0;
3102 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3104 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3105 pf->offset_loaded, &os->eth.rx_discards,
3106 &ns->eth.rx_discards);
3107 /* GLPRT_REPC not supported */
3108 /* GLPRT_RMPC not supported */
3109 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3111 &os->eth.rx_unknown_protocol,
3112 &ns->eth.rx_unknown_protocol);
3113 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3114 I40E_GLPRT_GOTCL(hw->port),
3115 pf->offset_loaded, &os->eth.tx_bytes,
3117 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3118 I40E_GLPRT_UPTCL(hw->port),
3119 pf->offset_loaded, &os->eth.tx_unicast,
3120 &ns->eth.tx_unicast);
3121 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3122 I40E_GLPRT_MPTCL(hw->port),
3123 pf->offset_loaded, &os->eth.tx_multicast,
3124 &ns->eth.tx_multicast);
3125 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3126 I40E_GLPRT_BPTCL(hw->port),
3127 pf->offset_loaded, &os->eth.tx_broadcast,
3128 &ns->eth.tx_broadcast);
3129 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3130 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3132 /* exclude internal tx bytes
3133 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3134 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3136 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3138 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3139 ns->eth.tx_bytes = 0;
3141 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3143 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3144 ns->eth.tx_unicast = 0;
3146 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3148 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3149 ns->eth.tx_multicast = 0;
3151 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3153 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3154 ns->eth.tx_broadcast = 0;
3156 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3158 /* GLPRT_TEPC not supported */
3160 /* additional port specific stats */
3161 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3162 pf->offset_loaded, &os->tx_dropped_link_down,
3163 &ns->tx_dropped_link_down);
3164 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3165 pf->offset_loaded, &os->crc_errors,
3167 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3168 pf->offset_loaded, &os->illegal_bytes,
3169 &ns->illegal_bytes);
3170 /* GLPRT_ERRBC not supported */
3171 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3172 pf->offset_loaded, &os->mac_local_faults,
3173 &ns->mac_local_faults);
3174 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3175 pf->offset_loaded, &os->mac_remote_faults,
3176 &ns->mac_remote_faults);
3177 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3178 pf->offset_loaded, &os->rx_length_errors,
3179 &ns->rx_length_errors);
3180 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3181 pf->offset_loaded, &os->link_xon_rx,
3183 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3184 pf->offset_loaded, &os->link_xoff_rx,
3186 for (i = 0; i < 8; i++) {
3187 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3189 &os->priority_xon_rx[i],
3190 &ns->priority_xon_rx[i]);
3191 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3193 &os->priority_xoff_rx[i],
3194 &ns->priority_xoff_rx[i]);
3196 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3197 pf->offset_loaded, &os->link_xon_tx,
3199 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3200 pf->offset_loaded, &os->link_xoff_tx,
3202 for (i = 0; i < 8; i++) {
3203 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3205 &os->priority_xon_tx[i],
3206 &ns->priority_xon_tx[i]);
3207 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3209 &os->priority_xoff_tx[i],
3210 &ns->priority_xoff_tx[i]);
3211 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3213 &os->priority_xon_2_xoff[i],
3214 &ns->priority_xon_2_xoff[i]);
3216 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3217 I40E_GLPRT_PRC64L(hw->port),
3218 pf->offset_loaded, &os->rx_size_64,
3220 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3221 I40E_GLPRT_PRC127L(hw->port),
3222 pf->offset_loaded, &os->rx_size_127,
3224 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3225 I40E_GLPRT_PRC255L(hw->port),
3226 pf->offset_loaded, &os->rx_size_255,
3228 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3229 I40E_GLPRT_PRC511L(hw->port),
3230 pf->offset_loaded, &os->rx_size_511,
3232 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3233 I40E_GLPRT_PRC1023L(hw->port),
3234 pf->offset_loaded, &os->rx_size_1023,
3236 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3237 I40E_GLPRT_PRC1522L(hw->port),
3238 pf->offset_loaded, &os->rx_size_1522,
3240 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3241 I40E_GLPRT_PRC9522L(hw->port),
3242 pf->offset_loaded, &os->rx_size_big,
3244 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3245 pf->offset_loaded, &os->rx_undersize,
3247 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3248 pf->offset_loaded, &os->rx_fragments,
3250 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3251 pf->offset_loaded, &os->rx_oversize,
3253 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3254 pf->offset_loaded, &os->rx_jabber,
3256 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3257 I40E_GLPRT_PTC64L(hw->port),
3258 pf->offset_loaded, &os->tx_size_64,
3260 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3261 I40E_GLPRT_PTC127L(hw->port),
3262 pf->offset_loaded, &os->tx_size_127,
3264 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3265 I40E_GLPRT_PTC255L(hw->port),
3266 pf->offset_loaded, &os->tx_size_255,
3268 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3269 I40E_GLPRT_PTC511L(hw->port),
3270 pf->offset_loaded, &os->tx_size_511,
3272 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3273 I40E_GLPRT_PTC1023L(hw->port),
3274 pf->offset_loaded, &os->tx_size_1023,
3276 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3277 I40E_GLPRT_PTC1522L(hw->port),
3278 pf->offset_loaded, &os->tx_size_1522,
3280 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3281 I40E_GLPRT_PTC9522L(hw->port),
3282 pf->offset_loaded, &os->tx_size_big,
3284 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3286 &os->fd_sb_match, &ns->fd_sb_match);
3287 /* GLPRT_MSPDC not supported */
3288 /* GLPRT_XEC not supported */
3290 pf->offset_loaded = true;
3293 i40e_update_vsi_stats(pf->main_vsi);
3296 /* Get all statistics of a port */
3298 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3303 struct i40e_vsi *vsi;
3306 /* call read registers - updates values, now write them to struct */
3307 i40e_read_stats_registers(pf, hw);
3309 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3310 pf->main_vsi->eth_stats.rx_multicast +
3311 pf->main_vsi->eth_stats.rx_broadcast -
3312 pf->main_vsi->eth_stats.rx_discards;
3313 stats->opackets = ns->eth.tx_unicast +
3314 ns->eth.tx_multicast +
3315 ns->eth.tx_broadcast;
3316 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3317 stats->obytes = ns->eth.tx_bytes;
3318 stats->oerrors = ns->eth.tx_errors +
3319 pf->main_vsi->eth_stats.tx_errors;
3322 stats->imissed = ns->eth.rx_discards +
3323 pf->main_vsi->eth_stats.rx_discards;
3324 stats->ierrors = ns->crc_errors +
3325 ns->rx_length_errors + ns->rx_undersize +
3326 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3329 for (i = 0; i < pf->vf_num; i++) {
3330 vsi = pf->vfs[i].vsi;
3331 i40e_update_vsi_stats(vsi);
3333 stats->ipackets += (vsi->eth_stats.rx_unicast +
3334 vsi->eth_stats.rx_multicast +
3335 vsi->eth_stats.rx_broadcast -
3336 vsi->eth_stats.rx_discards);
3337 stats->ibytes += vsi->eth_stats.rx_bytes;
3338 stats->oerrors += vsi->eth_stats.tx_errors;
3339 stats->imissed += vsi->eth_stats.rx_discards;
3343 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3344 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3345 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3346 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3347 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3348 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3349 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3350 ns->eth.rx_unknown_protocol);
3351 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3352 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3353 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3354 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3355 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3356 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3358 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3359 ns->tx_dropped_link_down);
3360 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3361 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3363 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3364 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3365 ns->mac_local_faults);
3366 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3367 ns->mac_remote_faults);
3368 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3369 ns->rx_length_errors);
3370 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3371 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3372 for (i = 0; i < 8; i++) {
3373 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3374 i, ns->priority_xon_rx[i]);
3375 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3376 i, ns->priority_xoff_rx[i]);
3378 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3379 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3380 for (i = 0; i < 8; i++) {
3381 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3382 i, ns->priority_xon_tx[i]);
3383 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3384 i, ns->priority_xoff_tx[i]);
3385 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3386 i, ns->priority_xon_2_xoff[i]);
3388 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3389 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3390 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3391 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3392 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3393 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3394 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3395 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3396 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3397 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3398 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3399 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3400 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3401 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3402 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3403 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3404 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3405 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3406 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3407 ns->mac_short_packet_dropped);
3408 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3409 ns->checksum_error);
3410 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3411 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3415 /* Reset the statistics */
3417 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3419 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422 /* Mark PF and VSI stats to update the offset, aka "reset" */
3423 pf->offset_loaded = false;
3425 pf->main_vsi->offset_loaded = false;
3427 /* read the stats, reading current register values into offset */
3428 i40e_read_stats_registers(pf, hw);
3434 i40e_xstats_calc_num(void)
3436 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3437 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3438 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3441 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3442 struct rte_eth_xstat_name *xstats_names,
3443 __rte_unused unsigned limit)
3448 if (xstats_names == NULL)
3449 return i40e_xstats_calc_num();
3451 /* Note: limit checked in rte_eth_xstats_names() */
3453 /* Get stats from i40e_eth_stats struct */
3454 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3455 strlcpy(xstats_names[count].name,
3456 rte_i40e_stats_strings[i].name,
3457 sizeof(xstats_names[count].name));
3461 /* Get individiual stats from i40e_hw_port struct */
3462 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3463 strlcpy(xstats_names[count].name,
3464 rte_i40e_hw_port_strings[i].name,
3465 sizeof(xstats_names[count].name));
3469 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3470 for (prio = 0; prio < 8; prio++) {
3471 snprintf(xstats_names[count].name,
3472 sizeof(xstats_names[count].name),
3473 "rx_priority%u_%s", prio,
3474 rte_i40e_rxq_prio_strings[i].name);
3479 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3480 for (prio = 0; prio < 8; prio++) {
3481 snprintf(xstats_names[count].name,
3482 sizeof(xstats_names[count].name),
3483 "tx_priority%u_%s", prio,
3484 rte_i40e_txq_prio_strings[i].name);
3492 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3495 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3496 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3497 unsigned i, count, prio;
3498 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3500 count = i40e_xstats_calc_num();
3504 i40e_read_stats_registers(pf, hw);
3511 /* Get stats from i40e_eth_stats struct */
3512 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3513 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3514 rte_i40e_stats_strings[i].offset);
3515 xstats[count].id = count;
3519 /* Get individiual stats from i40e_hw_port struct */
3520 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3521 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3522 rte_i40e_hw_port_strings[i].offset);
3523 xstats[count].id = count;
3527 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3528 for (prio = 0; prio < 8; prio++) {
3529 xstats[count].value =
3530 *(uint64_t *)(((char *)hw_stats) +
3531 rte_i40e_rxq_prio_strings[i].offset +
3532 (sizeof(uint64_t) * prio));
3533 xstats[count].id = count;
3538 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3539 for (prio = 0; prio < 8; prio++) {
3540 xstats[count].value =
3541 *(uint64_t *)(((char *)hw_stats) +
3542 rte_i40e_txq_prio_strings[i].offset +
3543 (sizeof(uint64_t) * prio));
3544 xstats[count].id = count;
3553 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3555 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561 full_ver = hw->nvm.oem_ver;
3562 ver = (u8)(full_ver >> 24);
3563 build = (u16)((full_ver >> 8) & 0xffff);
3564 patch = (u8)(full_ver & 0xff);
3566 ret = snprintf(fw_version, fw_size,
3567 "%d.%d%d 0x%08x %d.%d.%d",
3568 ((hw->nvm.version >> 12) & 0xf),
3569 ((hw->nvm.version >> 4) & 0xff),
3570 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3573 ret += 1; /* add the size of '\0' */
3574 if (fw_size < (u32)ret)
3581 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3582 * the Rx data path does not hang if the FW LLDP is stopped.
3583 * return true if lldp need to stop
3584 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3587 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3590 char ver_str[64] = {0};
3591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593 i40e_fw_version_get(dev, ver_str, 64);
3594 nvm_ver = atof(ver_str);
3595 if ((hw->mac.type == I40E_MAC_X722 ||
3596 hw->mac.type == I40E_MAC_X722_VF) &&
3597 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3599 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3606 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3608 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3609 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610 struct i40e_vsi *vsi = pf->main_vsi;
3611 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3613 dev_info->max_rx_queues = vsi->nb_qps;
3614 dev_info->max_tx_queues = vsi->nb_qps;
3615 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3616 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3617 dev_info->max_mac_addrs = vsi->max_macaddrs;
3618 dev_info->max_vfs = pci_dev->max_vfs;
3619 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3620 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3621 dev_info->rx_queue_offload_capa = 0;
3622 dev_info->rx_offload_capa =
3623 DEV_RX_OFFLOAD_VLAN_STRIP |
3624 DEV_RX_OFFLOAD_QINQ_STRIP |
3625 DEV_RX_OFFLOAD_IPV4_CKSUM |
3626 DEV_RX_OFFLOAD_UDP_CKSUM |
3627 DEV_RX_OFFLOAD_TCP_CKSUM |
3628 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3629 DEV_RX_OFFLOAD_KEEP_CRC |
3630 DEV_RX_OFFLOAD_SCATTER |
3631 DEV_RX_OFFLOAD_VLAN_EXTEND |
3632 DEV_RX_OFFLOAD_VLAN_FILTER |
3633 DEV_RX_OFFLOAD_JUMBO_FRAME |
3634 DEV_RX_OFFLOAD_RSS_HASH;
3636 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3637 dev_info->tx_offload_capa =
3638 DEV_TX_OFFLOAD_VLAN_INSERT |
3639 DEV_TX_OFFLOAD_QINQ_INSERT |
3640 DEV_TX_OFFLOAD_IPV4_CKSUM |
3641 DEV_TX_OFFLOAD_UDP_CKSUM |
3642 DEV_TX_OFFLOAD_TCP_CKSUM |
3643 DEV_TX_OFFLOAD_SCTP_CKSUM |
3644 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3645 DEV_TX_OFFLOAD_TCP_TSO |
3646 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3647 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3648 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3649 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3650 DEV_TX_OFFLOAD_MULTI_SEGS |
3651 dev_info->tx_queue_offload_capa;
3652 dev_info->dev_capa =
3653 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3654 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3656 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3658 dev_info->reta_size = pf->hash_lut_size;
3659 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3661 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3663 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3664 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3665 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3667 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3672 dev_info->default_txconf = (struct rte_eth_txconf) {
3674 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3675 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3676 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3678 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3679 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3683 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3684 .nb_max = I40E_MAX_RING_DESC,
3685 .nb_min = I40E_MIN_RING_DESC,
3686 .nb_align = I40E_ALIGN_RING_DESC,
3689 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3690 .nb_max = I40E_MAX_RING_DESC,
3691 .nb_min = I40E_MIN_RING_DESC,
3692 .nb_align = I40E_ALIGN_RING_DESC,
3693 .nb_seg_max = I40E_TX_MAX_SEG,
3694 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3697 if (pf->flags & I40E_FLAG_VMDQ) {
3698 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3699 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3700 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3701 pf->max_nb_vmdq_vsi;
3702 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3703 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3704 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3707 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3709 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3710 dev_info->default_rxportconf.nb_queues = 2;
3711 dev_info->default_txportconf.nb_queues = 2;
3712 if (dev->data->nb_rx_queues == 1)
3713 dev_info->default_rxportconf.ring_size = 2048;
3715 dev_info->default_rxportconf.ring_size = 1024;
3716 if (dev->data->nb_tx_queues == 1)
3717 dev_info->default_txportconf.ring_size = 1024;
3719 dev_info->default_txportconf.ring_size = 512;
3721 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3723 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3724 dev_info->default_rxportconf.nb_queues = 1;
3725 dev_info->default_txportconf.nb_queues = 1;
3726 dev_info->default_rxportconf.ring_size = 256;
3727 dev_info->default_txportconf.ring_size = 256;
3730 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3731 dev_info->default_rxportconf.nb_queues = 1;
3732 dev_info->default_txportconf.nb_queues = 1;
3733 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3734 dev_info->default_rxportconf.ring_size = 512;
3735 dev_info->default_txportconf.ring_size = 256;
3737 dev_info->default_rxportconf.ring_size = 256;
3738 dev_info->default_txportconf.ring_size = 256;
3741 dev_info->default_rxportconf.burst_size = 32;
3742 dev_info->default_txportconf.burst_size = 32;
3748 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3751 struct i40e_vsi *vsi = pf->main_vsi;
3752 PMD_INIT_FUNC_TRACE();
3755 return i40e_vsi_add_vlan(vsi, vlan_id);
3757 return i40e_vsi_delete_vlan(vsi, vlan_id);
3761 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3762 enum rte_vlan_type vlan_type,
3763 uint16_t tpid, int qinq)
3765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3768 uint16_t reg_id = 3;
3772 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3776 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3778 if (ret != I40E_SUCCESS) {
3780 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3785 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3788 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3789 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3790 if (reg_r == reg_w) {
3791 PMD_DRV_LOG(DEBUG, "No need to write");
3795 ret = i40e_aq_debug_write_global_register(hw,
3796 I40E_GL_SWT_L2TAGCTRL(reg_id),
3798 if (ret != I40E_SUCCESS) {
3800 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3805 "Global register 0x%08x is changed with value 0x%08x",
3806 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3812 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3813 enum rte_vlan_type vlan_type,
3816 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3818 int qinq = dev->data->dev_conf.rxmode.offloads &
3819 DEV_RX_OFFLOAD_VLAN_EXTEND;
3822 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3823 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3824 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3826 "Unsupported vlan type.");
3830 if (pf->support_multi_driver) {
3831 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3835 /* 802.1ad frames ability is added in NVM API 1.7*/
3836 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3838 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3839 hw->first_tag = rte_cpu_to_le_16(tpid);
3840 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3841 hw->second_tag = rte_cpu_to_le_16(tpid);
3843 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3844 hw->second_tag = rte_cpu_to_le_16(tpid);
3846 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3847 if (ret != I40E_SUCCESS) {
3849 "Set switch config failed aq_err: %d",
3850 hw->aq.asq_last_status);
3854 /* If NVM API < 1.7, keep the register setting */
3855 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3862 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3864 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3865 struct i40e_vsi *vsi = pf->main_vsi;
3866 struct rte_eth_rxmode *rxmode;
3868 if (mask & ETH_QINQ_STRIP_MASK) {
3869 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3873 rxmode = &dev->data->dev_conf.rxmode;
3874 if (mask & ETH_VLAN_FILTER_MASK) {
3875 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3876 i40e_vsi_config_vlan_filter(vsi, TRUE);
3878 i40e_vsi_config_vlan_filter(vsi, FALSE);
3881 if (mask & ETH_VLAN_STRIP_MASK) {
3882 /* Enable or disable VLAN stripping */
3883 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3884 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3886 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3889 if (mask & ETH_VLAN_EXTEND_MASK) {
3890 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3891 i40e_vsi_config_double_vlan(vsi, TRUE);
3892 /* Set global registers with default ethertype. */
3893 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3894 RTE_ETHER_TYPE_VLAN);
3895 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3896 RTE_ETHER_TYPE_VLAN);
3899 i40e_vsi_config_double_vlan(vsi, FALSE);
3906 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3907 __rte_unused uint16_t queue,
3908 __rte_unused int on)
3910 PMD_INIT_FUNC_TRACE();
3914 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3916 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3917 struct i40e_vsi *vsi = pf->main_vsi;
3918 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3919 struct i40e_vsi_vlan_pvid_info info;
3921 memset(&info, 0, sizeof(info));
3924 info.config.pvid = pvid;
3926 info.config.reject.tagged =
3927 data->dev_conf.txmode.hw_vlan_reject_tagged;
3928 info.config.reject.untagged =
3929 data->dev_conf.txmode.hw_vlan_reject_untagged;
3932 return i40e_vsi_vlan_pvid_set(vsi, &info);
3936 i40e_dev_led_on(struct rte_eth_dev *dev)
3938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939 uint32_t mode = i40e_led_get(hw);
3942 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3948 i40e_dev_led_off(struct rte_eth_dev *dev)
3950 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951 uint32_t mode = i40e_led_get(hw);
3954 i40e_led_set(hw, 0, false);
3960 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3962 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3963 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3965 fc_conf->pause_time = pf->fc_conf.pause_time;
3967 /* read out from register, in case they are modified by other port */
3968 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3969 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3970 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3971 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3973 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3974 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3976 /* Return current mode according to actual setting*/
3977 switch (hw->fc.current_mode) {
3979 fc_conf->mode = RTE_FC_FULL;
3981 case I40E_FC_TX_PAUSE:
3982 fc_conf->mode = RTE_FC_TX_PAUSE;
3984 case I40E_FC_RX_PAUSE:
3985 fc_conf->mode = RTE_FC_RX_PAUSE;
3989 fc_conf->mode = RTE_FC_NONE;
3996 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3998 uint32_t mflcn_reg, fctrl_reg, reg;
3999 uint32_t max_high_water;
4000 uint8_t i, aq_failure;
4004 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4005 [RTE_FC_NONE] = I40E_FC_NONE,
4006 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4007 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4008 [RTE_FC_FULL] = I40E_FC_FULL
4011 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4013 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4014 if ((fc_conf->high_water > max_high_water) ||
4015 (fc_conf->high_water < fc_conf->low_water)) {
4017 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4022 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4023 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4024 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4026 pf->fc_conf.pause_time = fc_conf->pause_time;
4027 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4028 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4030 PMD_INIT_FUNC_TRACE();
4032 /* All the link flow control related enable/disable register
4033 * configuration is handle by the F/W
4035 err = i40e_set_fc(hw, &aq_failure, true);
4039 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4040 /* Configure flow control refresh threshold,
4041 * the value for stat_tx_pause_refresh_timer[8]
4042 * is used for global pause operation.
4046 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4047 pf->fc_conf.pause_time);
4049 /* configure the timer value included in transmitted pause
4051 * the value for stat_tx_pause_quanta[8] is used for global
4054 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4055 pf->fc_conf.pause_time);
4057 fctrl_reg = I40E_READ_REG(hw,
4058 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4060 if (fc_conf->mac_ctrl_frame_fwd != 0)
4061 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4063 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4065 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4068 /* Configure pause time (2 TCs per register) */
4069 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4070 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4071 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4073 /* Configure flow control refresh threshold value */
4074 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4075 pf->fc_conf.pause_time / 2);
4077 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4079 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4080 *depending on configuration
4082 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4083 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4084 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4086 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4087 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4090 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4093 if (!pf->support_multi_driver) {
4094 /* config water marker both based on the packets and bytes */
4095 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4096 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4097 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4098 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4099 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4100 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4101 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4102 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4104 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4105 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4109 "Water marker configuration is not supported.");
4112 I40E_WRITE_FLUSH(hw);
4118 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4119 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4121 PMD_INIT_FUNC_TRACE();
4126 /* Add a MAC address, and update filters */
4128 i40e_macaddr_add(struct rte_eth_dev *dev,
4129 struct rte_ether_addr *mac_addr,
4130 __rte_unused uint32_t index,
4133 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4134 struct i40e_mac_filter_info mac_filter;
4135 struct i40e_vsi *vsi;
4136 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4139 /* If VMDQ not enabled or configured, return */
4140 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4141 !pf->nb_cfg_vmdq_vsi)) {
4142 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4143 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4148 if (pool > pf->nb_cfg_vmdq_vsi) {
4149 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4150 pool, pf->nb_cfg_vmdq_vsi);
4154 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4155 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4156 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4158 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4163 vsi = pf->vmdq[pool - 1].vsi;
4165 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4166 if (ret != I40E_SUCCESS) {
4167 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4173 /* Remove a MAC address, and update filters */
4175 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4177 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4178 struct i40e_vsi *vsi;
4179 struct rte_eth_dev_data *data = dev->data;
4180 struct rte_ether_addr *macaddr;
4185 macaddr = &(data->mac_addrs[index]);
4187 pool_sel = dev->data->mac_pool_sel[index];
4189 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4190 if (pool_sel & (1ULL << i)) {
4194 /* No VMDQ pool enabled or configured */
4195 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4196 (i > pf->nb_cfg_vmdq_vsi)) {
4198 "No VMDQ pool enabled/configured");
4201 vsi = pf->vmdq[i - 1].vsi;
4203 ret = i40e_vsi_delete_mac(vsi, macaddr);
4206 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4213 /* Set perfect match or hash match of MAC and VLAN for a VF */
4215 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4216 struct rte_eth_mac_filter *filter,
4220 struct i40e_mac_filter_info mac_filter;
4221 struct rte_ether_addr old_mac;
4222 struct rte_ether_addr *new_mac;
4223 struct i40e_pf_vf *vf = NULL;
4228 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4231 hw = I40E_PF_TO_HW(pf);
4233 if (filter == NULL) {
4234 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4238 new_mac = &filter->mac_addr;
4240 if (rte_is_zero_ether_addr(new_mac)) {
4241 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4245 vf_id = filter->dst_id;
4247 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4248 PMD_DRV_LOG(ERR, "Invalid argument.");
4251 vf = &pf->vfs[vf_id];
4253 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4254 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4259 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4260 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4261 RTE_ETHER_ADDR_LEN);
4262 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4263 RTE_ETHER_ADDR_LEN);
4265 mac_filter.filter_type = filter->filter_type;
4266 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4267 if (ret != I40E_SUCCESS) {
4268 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4271 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4273 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4274 RTE_ETHER_ADDR_LEN);
4275 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4276 if (ret != I40E_SUCCESS) {
4277 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4281 /* Clear device address as it has been removed */
4282 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4283 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4289 /* MAC filter handle */
4291 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4294 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4295 struct rte_eth_mac_filter *filter;
4296 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4297 int ret = I40E_NOT_SUPPORTED;
4299 filter = (struct rte_eth_mac_filter *)(arg);
4301 switch (filter_op) {
4302 case RTE_ETH_FILTER_NOP:
4305 case RTE_ETH_FILTER_ADD:
4306 i40e_pf_disable_irq0(hw);
4308 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4309 i40e_pf_enable_irq0(hw);
4311 case RTE_ETH_FILTER_DELETE:
4312 i40e_pf_disable_irq0(hw);
4314 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4315 i40e_pf_enable_irq0(hw);
4318 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4319 ret = I40E_ERR_PARAM;
4327 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4329 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4330 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4337 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4338 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4339 vsi->type != I40E_VSI_SRIOV,
4342 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4346 uint32_t *lut_dw = (uint32_t *)lut;
4347 uint16_t i, lut_size_dw = lut_size / 4;
4349 if (vsi->type == I40E_VSI_SRIOV) {
4350 for (i = 0; i <= lut_size_dw; i++) {
4351 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4352 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4355 for (i = 0; i < lut_size_dw; i++)
4356 lut_dw[i] = I40E_READ_REG(hw,
4365 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4374 pf = I40E_VSI_TO_PF(vsi);
4375 hw = I40E_VSI_TO_HW(vsi);
4377 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4378 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4379 vsi->type != I40E_VSI_SRIOV,
4382 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4386 uint32_t *lut_dw = (uint32_t *)lut;
4387 uint16_t i, lut_size_dw = lut_size / 4;
4389 if (vsi->type == I40E_VSI_SRIOV) {
4390 for (i = 0; i < lut_size_dw; i++)
4393 I40E_VFQF_HLUT1(i, vsi->user_param),
4396 for (i = 0; i < lut_size_dw; i++)
4397 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4400 I40E_WRITE_FLUSH(hw);
4407 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4408 struct rte_eth_rss_reta_entry64 *reta_conf,
4411 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4412 uint16_t i, lut_size = pf->hash_lut_size;
4413 uint16_t idx, shift;
4417 if (reta_size != lut_size ||
4418 reta_size > ETH_RSS_RETA_SIZE_512) {
4420 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4421 reta_size, lut_size);
4425 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4427 PMD_DRV_LOG(ERR, "No memory can be allocated");
4430 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4433 for (i = 0; i < reta_size; i++) {
4434 idx = i / RTE_RETA_GROUP_SIZE;
4435 shift = i % RTE_RETA_GROUP_SIZE;
4436 if (reta_conf[idx].mask & (1ULL << shift))
4437 lut[i] = reta_conf[idx].reta[shift];
4439 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4441 pf->adapter->rss_reta_updated = 1;
4450 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4451 struct rte_eth_rss_reta_entry64 *reta_conf,
4454 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4455 uint16_t i, lut_size = pf->hash_lut_size;
4456 uint16_t idx, shift;
4460 if (reta_size != lut_size ||
4461 reta_size > ETH_RSS_RETA_SIZE_512) {
4463 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4464 reta_size, lut_size);
4468 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4470 PMD_DRV_LOG(ERR, "No memory can be allocated");
4474 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4477 for (i = 0; i < reta_size; i++) {
4478 idx = i / RTE_RETA_GROUP_SIZE;
4479 shift = i % RTE_RETA_GROUP_SIZE;
4480 if (reta_conf[idx].mask & (1ULL << shift))
4481 reta_conf[idx].reta[shift] = lut[i];
4491 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4492 * @hw: pointer to the HW structure
4493 * @mem: pointer to mem struct to fill out
4494 * @size: size of memory requested
4495 * @alignment: what to align the allocation to
4497 enum i40e_status_code
4498 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4499 struct i40e_dma_mem *mem,
4503 const struct rte_memzone *mz = NULL;
4504 char z_name[RTE_MEMZONE_NAMESIZE];
4507 return I40E_ERR_PARAM;
4509 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4510 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4511 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4513 return I40E_ERR_NO_MEMORY;
4518 mem->zone = (const void *)mz;
4520 "memzone %s allocated with physical address: %"PRIu64,
4523 return I40E_SUCCESS;
4527 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4528 * @hw: pointer to the HW structure
4529 * @mem: ptr to mem struct to free
4531 enum i40e_status_code
4532 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4533 struct i40e_dma_mem *mem)
4536 return I40E_ERR_PARAM;
4539 "memzone %s to be freed with physical address: %"PRIu64,
4540 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4541 rte_memzone_free((const struct rte_memzone *)mem->zone);
4546 return I40E_SUCCESS;
4550 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4551 * @hw: pointer to the HW structure
4552 * @mem: pointer to mem struct to fill out
4553 * @size: size of memory requested
4555 enum i40e_status_code
4556 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4557 struct i40e_virt_mem *mem,
4561 return I40E_ERR_PARAM;
4564 mem->va = rte_zmalloc("i40e", size, 0);
4567 return I40E_SUCCESS;
4569 return I40E_ERR_NO_MEMORY;
4573 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4574 * @hw: pointer to the HW structure
4575 * @mem: pointer to mem struct to free
4577 enum i40e_status_code
4578 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4579 struct i40e_virt_mem *mem)
4582 return I40E_ERR_PARAM;
4587 return I40E_SUCCESS;
4591 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4593 rte_spinlock_init(&sp->spinlock);
4597 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4599 rte_spinlock_lock(&sp->spinlock);
4603 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4605 rte_spinlock_unlock(&sp->spinlock);
4609 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4615 * Get the hardware capabilities, which will be parsed
4616 * and saved into struct i40e_hw.
4619 i40e_get_cap(struct i40e_hw *hw)
4621 struct i40e_aqc_list_capabilities_element_resp *buf;
4622 uint16_t len, size = 0;
4625 /* Calculate a huge enough buff for saving response data temporarily */
4626 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4627 I40E_MAX_CAP_ELE_NUM;
4628 buf = rte_zmalloc("i40e", len, 0);
4630 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4631 return I40E_ERR_NO_MEMORY;
4634 /* Get, parse the capabilities and save it to hw */
4635 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4636 i40e_aqc_opc_list_func_capabilities, NULL);
4637 if (ret != I40E_SUCCESS)
4638 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4640 /* Free the temporary buffer after being used */
4646 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4648 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4656 pf = (struct i40e_pf *)opaque;
4660 num = strtoul(value, &end, 0);
4661 if (errno != 0 || end == value || *end != 0) {
4662 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4663 "kept the value = %hu", value, pf->vf_nb_qp_max);
4667 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4668 pf->vf_nb_qp_max = (uint16_t)num;
4670 /* here return 0 to make next valid same argument work */
4671 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4672 "power of 2 and equal or less than 16 !, Now it is "
4673 "kept the value = %hu", num, pf->vf_nb_qp_max);
4678 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4680 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4681 struct rte_kvargs *kvlist;
4684 /* set default queue number per VF as 4 */
4685 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4687 if (dev->device->devargs == NULL)
4690 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4694 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4695 if (!kvargs_count) {
4696 rte_kvargs_free(kvlist);
4700 if (kvargs_count > 1)
4701 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4702 "the first invalid or last valid one is used !",
4703 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4705 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4706 i40e_pf_parse_vf_queue_number_handler, pf);
4708 rte_kvargs_free(kvlist);
4714 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4716 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4717 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4718 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4719 uint16_t qp_count = 0, vsi_count = 0;
4721 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4722 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4726 i40e_pf_config_vf_rxq_number(dev);
4728 /* Add the parameter init for LFC */
4729 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4730 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4731 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4733 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4734 pf->max_num_vsi = hw->func_caps.num_vsis;
4735 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4736 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4738 /* FDir queue/VSI allocation */
4739 pf->fdir_qp_offset = 0;
4740 if (hw->func_caps.fd) {
4741 pf->flags |= I40E_FLAG_FDIR;
4742 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4744 pf->fdir_nb_qps = 0;
4746 qp_count += pf->fdir_nb_qps;
4749 /* LAN queue/VSI allocation */
4750 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4751 if (!hw->func_caps.rss) {
4754 pf->flags |= I40E_FLAG_RSS;
4755 if (hw->mac.type == I40E_MAC_X722)
4756 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4757 pf->lan_nb_qps = pf->lan_nb_qp_max;
4759 qp_count += pf->lan_nb_qps;
4762 /* VF queue/VSI allocation */
4763 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4764 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4765 pf->flags |= I40E_FLAG_SRIOV;
4766 pf->vf_nb_qps = pf->vf_nb_qp_max;
4767 pf->vf_num = pci_dev->max_vfs;
4769 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4770 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4775 qp_count += pf->vf_nb_qps * pf->vf_num;
4776 vsi_count += pf->vf_num;
4778 /* VMDq queue/VSI allocation */
4779 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4780 pf->vmdq_nb_qps = 0;
4781 pf->max_nb_vmdq_vsi = 0;
4782 if (hw->func_caps.vmdq) {
4783 if (qp_count < hw->func_caps.num_tx_qp &&
4784 vsi_count < hw->func_caps.num_vsis) {
4785 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4786 qp_count) / pf->vmdq_nb_qp_max;
4788 /* Limit the maximum number of VMDq vsi to the maximum
4789 * ethdev can support
4791 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4792 hw->func_caps.num_vsis - vsi_count);
4793 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4795 if (pf->max_nb_vmdq_vsi) {
4796 pf->flags |= I40E_FLAG_VMDQ;
4797 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4799 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4800 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4801 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4804 "No enough queues left for VMDq");
4807 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4810 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4811 vsi_count += pf->max_nb_vmdq_vsi;
4813 if (hw->func_caps.dcb)
4814 pf->flags |= I40E_FLAG_DCB;
4816 if (qp_count > hw->func_caps.num_tx_qp) {
4818 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4819 qp_count, hw->func_caps.num_tx_qp);
4822 if (vsi_count > hw->func_caps.num_vsis) {
4824 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4825 vsi_count, hw->func_caps.num_vsis);
4833 i40e_pf_get_switch_config(struct i40e_pf *pf)
4835 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4836 struct i40e_aqc_get_switch_config_resp *switch_config;
4837 struct i40e_aqc_switch_config_element_resp *element;
4838 uint16_t start_seid = 0, num_reported;
4841 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4842 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4843 if (!switch_config) {
4844 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4848 /* Get the switch configurations */
4849 ret = i40e_aq_get_switch_config(hw, switch_config,
4850 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4851 if (ret != I40E_SUCCESS) {
4852 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4855 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4856 if (num_reported != 1) { /* The number should be 1 */
4857 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4861 /* Parse the switch configuration elements */
4862 element = &(switch_config->element[0]);
4863 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4864 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4865 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4867 PMD_DRV_LOG(INFO, "Unknown element type");
4870 rte_free(switch_config);
4876 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4879 struct pool_entry *entry;
4881 if (pool == NULL || num == 0)
4884 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4885 if (entry == NULL) {
4886 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4890 /* queue heap initialize */
4891 pool->num_free = num;
4892 pool->num_alloc = 0;
4894 LIST_INIT(&pool->alloc_list);
4895 LIST_INIT(&pool->free_list);
4897 /* Initialize element */
4901 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4906 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4908 struct pool_entry *entry, *next_entry;
4913 for (entry = LIST_FIRST(&pool->alloc_list);
4914 entry && (next_entry = LIST_NEXT(entry, next), 1);
4915 entry = next_entry) {
4916 LIST_REMOVE(entry, next);
4920 for (entry = LIST_FIRST(&pool->free_list);
4921 entry && (next_entry = LIST_NEXT(entry, next), 1);
4922 entry = next_entry) {
4923 LIST_REMOVE(entry, next);
4928 pool->num_alloc = 0;
4930 LIST_INIT(&pool->alloc_list);
4931 LIST_INIT(&pool->free_list);
4935 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4938 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4939 uint32_t pool_offset;
4944 PMD_DRV_LOG(ERR, "Invalid parameter");
4948 pool_offset = base - pool->base;
4949 /* Lookup in alloc list */
4950 LIST_FOREACH(entry, &pool->alloc_list, next) {
4951 if (entry->base == pool_offset) {
4952 valid_entry = entry;
4953 LIST_REMOVE(entry, next);
4958 /* Not find, return */
4959 if (valid_entry == NULL) {
4960 PMD_DRV_LOG(ERR, "Failed to find entry");
4965 * Found it, move it to free list and try to merge.
4966 * In order to make merge easier, always sort it by qbase.
4967 * Find adjacent prev and last entries.
4970 LIST_FOREACH(entry, &pool->free_list, next) {
4971 if (entry->base > valid_entry->base) {
4979 len = valid_entry->len;
4980 /* Try to merge with next one*/
4982 /* Merge with next one */
4983 if (valid_entry->base + len == next->base) {
4984 next->base = valid_entry->base;
4986 rte_free(valid_entry);
4993 /* Merge with previous one */
4994 if (prev->base + prev->len == valid_entry->base) {
4996 /* If it merge with next one, remove next node */
4998 LIST_REMOVE(valid_entry, next);
4999 rte_free(valid_entry);
5002 rte_free(valid_entry);
5009 /* Not find any entry to merge, insert */
5012 LIST_INSERT_AFTER(prev, valid_entry, next);
5013 else if (next != NULL)
5014 LIST_INSERT_BEFORE(next, valid_entry, next);
5015 else /* It's empty list, insert to head */
5016 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5019 pool->num_free += len;
5020 pool->num_alloc -= len;
5026 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5029 struct pool_entry *entry, *valid_entry;
5031 if (pool == NULL || num == 0) {
5032 PMD_DRV_LOG(ERR, "Invalid parameter");
5036 if (pool->num_free < num) {
5037 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5038 num, pool->num_free);
5043 /* Lookup in free list and find most fit one */
5044 LIST_FOREACH(entry, &pool->free_list, next) {
5045 if (entry->len >= num) {
5047 if (entry->len == num) {
5048 valid_entry = entry;
5051 if (valid_entry == NULL || valid_entry->len > entry->len)
5052 valid_entry = entry;
5056 /* Not find one to satisfy the request, return */
5057 if (valid_entry == NULL) {
5058 PMD_DRV_LOG(ERR, "No valid entry found");
5062 * The entry have equal queue number as requested,
5063 * remove it from alloc_list.
5065 if (valid_entry->len == num) {
5066 LIST_REMOVE(valid_entry, next);
5069 * The entry have more numbers than requested,
5070 * create a new entry for alloc_list and minus its
5071 * queue base and number in free_list.
5073 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5074 if (entry == NULL) {
5076 "Failed to allocate memory for resource pool");
5079 entry->base = valid_entry->base;
5081 valid_entry->base += num;
5082 valid_entry->len -= num;
5083 valid_entry = entry;
5086 /* Insert it into alloc list, not sorted */
5087 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5089 pool->num_free -= valid_entry->len;
5090 pool->num_alloc += valid_entry->len;
5092 return valid_entry->base + pool->base;
5096 * bitmap_is_subset - Check whether src2 is subset of src1
5099 bitmap_is_subset(uint8_t src1, uint8_t src2)
5101 return !((src1 ^ src2) & src2);
5104 static enum i40e_status_code
5105 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5107 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5109 /* If DCB is not supported, only default TC is supported */
5110 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5111 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5112 return I40E_NOT_SUPPORTED;
5115 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5117 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5118 hw->func_caps.enabled_tcmap, enabled_tcmap);
5119 return I40E_NOT_SUPPORTED;
5121 return I40E_SUCCESS;
5125 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5126 struct i40e_vsi_vlan_pvid_info *info)
5129 struct i40e_vsi_context ctxt;
5130 uint8_t vlan_flags = 0;
5133 if (vsi == NULL || info == NULL) {
5134 PMD_DRV_LOG(ERR, "invalid parameters");
5135 return I40E_ERR_PARAM;
5139 vsi->info.pvid = info->config.pvid;
5141 * If insert pvid is enabled, only tagged pkts are
5142 * allowed to be sent out.
5144 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5145 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5148 if (info->config.reject.tagged == 0)
5149 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5151 if (info->config.reject.untagged == 0)
5152 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5154 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5155 I40E_AQ_VSI_PVLAN_MODE_MASK);
5156 vsi->info.port_vlan_flags |= vlan_flags;
5157 vsi->info.valid_sections =
5158 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5159 memset(&ctxt, 0, sizeof(ctxt));
5160 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5161 ctxt.seid = vsi->seid;
5163 hw = I40E_VSI_TO_HW(vsi);
5164 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5165 if (ret != I40E_SUCCESS)
5166 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5172 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5174 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5176 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5178 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5179 if (ret != I40E_SUCCESS)
5183 PMD_DRV_LOG(ERR, "seid not valid");
5187 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5188 tc_bw_data.tc_valid_bits = enabled_tcmap;
5189 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5190 tc_bw_data.tc_bw_credits[i] =
5191 (enabled_tcmap & (1 << i)) ? 1 : 0;
5193 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5194 if (ret != I40E_SUCCESS) {
5195 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5199 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5200 sizeof(vsi->info.qs_handle));
5201 return I40E_SUCCESS;
5204 static enum i40e_status_code
5205 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5206 struct i40e_aqc_vsi_properties_data *info,
5207 uint8_t enabled_tcmap)
5209 enum i40e_status_code ret;
5210 int i, total_tc = 0;
5211 uint16_t qpnum_per_tc, bsf, qp_idx;
5213 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5214 if (ret != I40E_SUCCESS)
5217 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5218 if (enabled_tcmap & (1 << i))
5222 vsi->enabled_tc = enabled_tcmap;
5224 /* Number of queues per enabled TC */
5225 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5226 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5227 bsf = rte_bsf32(qpnum_per_tc);
5229 /* Adjust the queue number to actual queues that can be applied */
5230 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5231 vsi->nb_qps = qpnum_per_tc * total_tc;
5234 * Configure TC and queue mapping parameters, for enabled TC,
5235 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5236 * default queue will serve it.
5239 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5240 if (vsi->enabled_tc & (1 << i)) {
5241 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5242 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5243 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5244 qp_idx += qpnum_per_tc;
5246 info->tc_mapping[i] = 0;
5249 /* Associate queue number with VSI */
5250 if (vsi->type == I40E_VSI_SRIOV) {
5251 info->mapping_flags |=
5252 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5253 for (i = 0; i < vsi->nb_qps; i++)
5254 info->queue_mapping[i] =
5255 rte_cpu_to_le_16(vsi->base_queue + i);
5257 info->mapping_flags |=
5258 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5259 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5261 info->valid_sections |=
5262 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5264 return I40E_SUCCESS;
5268 i40e_veb_release(struct i40e_veb *veb)
5270 struct i40e_vsi *vsi;
5276 if (!TAILQ_EMPTY(&veb->head)) {
5277 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5280 /* associate_vsi field is NULL for floating VEB */
5281 if (veb->associate_vsi != NULL) {
5282 vsi = veb->associate_vsi;
5283 hw = I40E_VSI_TO_HW(vsi);
5285 vsi->uplink_seid = veb->uplink_seid;
5288 veb->associate_pf->main_vsi->floating_veb = NULL;
5289 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5292 i40e_aq_delete_element(hw, veb->seid, NULL);
5294 return I40E_SUCCESS;
5298 static struct i40e_veb *
5299 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5301 struct i40e_veb *veb;
5307 "veb setup failed, associated PF shouldn't null");
5310 hw = I40E_PF_TO_HW(pf);
5312 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5314 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5318 veb->associate_vsi = vsi;
5319 veb->associate_pf = pf;
5320 TAILQ_INIT(&veb->head);
5321 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5323 /* create floating veb if vsi is NULL */
5325 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5326 I40E_DEFAULT_TCMAP, false,
5327 &veb->seid, false, NULL);
5329 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5330 true, &veb->seid, false, NULL);
5333 if (ret != I40E_SUCCESS) {
5334 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5335 hw->aq.asq_last_status);
5338 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5340 /* get statistics index */
5341 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5342 &veb->stats_idx, NULL, NULL, NULL);
5343 if (ret != I40E_SUCCESS) {
5344 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5345 hw->aq.asq_last_status);
5348 /* Get VEB bandwidth, to be implemented */
5349 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5351 vsi->uplink_seid = veb->seid;
5360 i40e_vsi_release(struct i40e_vsi *vsi)
5364 struct i40e_vsi_list *vsi_list;
5367 struct i40e_mac_filter *f;
5368 uint16_t user_param;
5371 return I40E_SUCCESS;
5376 user_param = vsi->user_param;
5378 pf = I40E_VSI_TO_PF(vsi);
5379 hw = I40E_VSI_TO_HW(vsi);
5381 /* VSI has child to attach, release child first */
5383 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5384 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5387 i40e_veb_release(vsi->veb);
5390 if (vsi->floating_veb) {
5391 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5392 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5397 /* Remove all macvlan filters of the VSI */
5398 i40e_vsi_remove_all_macvlan_filter(vsi);
5399 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5402 if (vsi->type != I40E_VSI_MAIN &&
5403 ((vsi->type != I40E_VSI_SRIOV) ||
5404 !pf->floating_veb_list[user_param])) {
5405 /* Remove vsi from parent's sibling list */
5406 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5407 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5408 return I40E_ERR_PARAM;
5410 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5411 &vsi->sib_vsi_list, list);
5413 /* Remove all switch element of the VSI */
5414 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5415 if (ret != I40E_SUCCESS)
5416 PMD_DRV_LOG(ERR, "Failed to delete element");
5419 if ((vsi->type == I40E_VSI_SRIOV) &&
5420 pf->floating_veb_list[user_param]) {
5421 /* Remove vsi from parent's sibling list */
5422 if (vsi->parent_vsi == NULL ||
5423 vsi->parent_vsi->floating_veb == NULL) {
5424 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5425 return I40E_ERR_PARAM;
5427 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5428 &vsi->sib_vsi_list, list);
5430 /* Remove all switch element of the VSI */
5431 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5432 if (ret != I40E_SUCCESS)
5433 PMD_DRV_LOG(ERR, "Failed to delete element");
5436 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5438 if (vsi->type != I40E_VSI_SRIOV)
5439 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5442 return I40E_SUCCESS;
5446 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5448 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5449 struct i40e_aqc_remove_macvlan_element_data def_filter;
5450 struct i40e_mac_filter_info filter;
5453 if (vsi->type != I40E_VSI_MAIN)
5454 return I40E_ERR_CONFIG;
5455 memset(&def_filter, 0, sizeof(def_filter));
5456 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5458 def_filter.vlan_tag = 0;
5459 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5460 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5461 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5462 if (ret != I40E_SUCCESS) {
5463 struct i40e_mac_filter *f;
5464 struct rte_ether_addr *mac;
5467 "Cannot remove the default macvlan filter");
5468 /* It needs to add the permanent mac into mac list */
5469 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5471 PMD_DRV_LOG(ERR, "failed to allocate memory");
5472 return I40E_ERR_NO_MEMORY;
5474 mac = &f->mac_info.mac_addr;
5475 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5477 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5478 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5483 rte_memcpy(&filter.mac_addr,
5484 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5485 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5486 return i40e_vsi_add_mac(vsi, &filter);
5490 * i40e_vsi_get_bw_config - Query VSI BW Information
5491 * @vsi: the VSI to be queried
5493 * Returns 0 on success, negative value on failure
5495 static enum i40e_status_code
5496 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5498 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5499 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5500 struct i40e_hw *hw = &vsi->adapter->hw;
5505 memset(&bw_config, 0, sizeof(bw_config));
5506 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5507 if (ret != I40E_SUCCESS) {
5508 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5509 hw->aq.asq_last_status);
5513 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5514 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5515 &ets_sla_config, NULL);
5516 if (ret != I40E_SUCCESS) {
5518 "VSI failed to get TC bandwdith configuration %u",
5519 hw->aq.asq_last_status);
5523 /* store and print out BW info */
5524 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5525 vsi->bw_info.bw_max = bw_config.max_bw;
5526 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5527 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5528 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5529 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5531 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5532 vsi->bw_info.bw_ets_share_credits[i] =
5533 ets_sla_config.share_credits[i];
5534 vsi->bw_info.bw_ets_credits[i] =
5535 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5536 /* 4 bits per TC, 4th bit is reserved */
5537 vsi->bw_info.bw_ets_max[i] =
5538 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5539 RTE_LEN2MASK(3, uint8_t));
5540 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5541 vsi->bw_info.bw_ets_share_credits[i]);
5542 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5543 vsi->bw_info.bw_ets_credits[i]);
5544 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5545 vsi->bw_info.bw_ets_max[i]);
5548 return I40E_SUCCESS;
5551 /* i40e_enable_pf_lb
5552 * @pf: pointer to the pf structure
5554 * allow loopback on pf
5557 i40e_enable_pf_lb(struct i40e_pf *pf)
5559 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5560 struct i40e_vsi_context ctxt;
5563 /* Use the FW API if FW >= v5.0 */
5564 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5565 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5569 memset(&ctxt, 0, sizeof(ctxt));
5570 ctxt.seid = pf->main_vsi_seid;
5571 ctxt.pf_num = hw->pf_id;
5572 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5574 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5575 ret, hw->aq.asq_last_status);
5578 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5579 ctxt.info.valid_sections =
5580 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5581 ctxt.info.switch_id |=
5582 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5584 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5586 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5587 hw->aq.asq_last_status);
5592 i40e_vsi_setup(struct i40e_pf *pf,
5593 enum i40e_vsi_type type,
5594 struct i40e_vsi *uplink_vsi,
5595 uint16_t user_param)
5597 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5598 struct i40e_vsi *vsi;
5599 struct i40e_mac_filter_info filter;
5601 struct i40e_vsi_context ctxt;
5602 struct rte_ether_addr broadcast =
5603 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5605 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5606 uplink_vsi == NULL) {
5608 "VSI setup failed, VSI link shouldn't be NULL");
5612 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5614 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5619 * 1.type is not MAIN and uplink vsi is not NULL
5620 * If uplink vsi didn't setup VEB, create one first under veb field
5621 * 2.type is SRIOV and the uplink is NULL
5622 * If floating VEB is NULL, create one veb under floating veb field
5625 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5626 uplink_vsi->veb == NULL) {
5627 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5629 if (uplink_vsi->veb == NULL) {
5630 PMD_DRV_LOG(ERR, "VEB setup failed");
5633 /* set ALLOWLOOPBACk on pf, when veb is created */
5634 i40e_enable_pf_lb(pf);
5637 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5638 pf->main_vsi->floating_veb == NULL) {
5639 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5641 if (pf->main_vsi->floating_veb == NULL) {
5642 PMD_DRV_LOG(ERR, "VEB setup failed");
5647 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5649 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5652 TAILQ_INIT(&vsi->mac_list);
5654 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5655 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5656 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5657 vsi->user_param = user_param;
5658 vsi->vlan_anti_spoof_on = 0;
5659 vsi->vlan_filter_on = 0;
5660 /* Allocate queues */
5661 switch (vsi->type) {
5662 case I40E_VSI_MAIN :
5663 vsi->nb_qps = pf->lan_nb_qps;
5665 case I40E_VSI_SRIOV :
5666 vsi->nb_qps = pf->vf_nb_qps;
5668 case I40E_VSI_VMDQ2:
5669 vsi->nb_qps = pf->vmdq_nb_qps;
5672 vsi->nb_qps = pf->fdir_nb_qps;
5678 * The filter status descriptor is reported in rx queue 0,
5679 * while the tx queue for fdir filter programming has no
5680 * such constraints, can be non-zero queues.
5681 * To simplify it, choose FDIR vsi use queue 0 pair.
5682 * To make sure it will use queue 0 pair, queue allocation
5683 * need be done before this function is called
5685 if (type != I40E_VSI_FDIR) {
5686 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5688 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5692 vsi->base_queue = ret;
5694 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5696 /* VF has MSIX interrupt in VF range, don't allocate here */
5697 if (type == I40E_VSI_MAIN) {
5698 if (pf->support_multi_driver) {
5699 /* If support multi-driver, need to use INT0 instead of
5700 * allocating from msix pool. The Msix pool is init from
5701 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5702 * to 1 without calling i40e_res_pool_alloc.
5707 ret = i40e_res_pool_alloc(&pf->msix_pool,
5708 RTE_MIN(vsi->nb_qps,
5709 RTE_MAX_RXTX_INTR_VEC_ID));
5712 "VSI MAIN %d get heap failed %d",
5714 goto fail_queue_alloc;
5716 vsi->msix_intr = ret;
5717 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5718 RTE_MAX_RXTX_INTR_VEC_ID);
5720 } else if (type != I40E_VSI_SRIOV) {
5721 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5723 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5724 goto fail_queue_alloc;
5726 vsi->msix_intr = ret;
5734 if (type == I40E_VSI_MAIN) {
5735 /* For main VSI, no need to add since it's default one */
5736 vsi->uplink_seid = pf->mac_seid;
5737 vsi->seid = pf->main_vsi_seid;
5738 /* Bind queues with specific MSIX interrupt */
5740 * Needs 2 interrupt at least, one for misc cause which will
5741 * enabled from OS side, Another for queues binding the
5742 * interrupt from device side only.
5745 /* Get default VSI parameters from hardware */
5746 memset(&ctxt, 0, sizeof(ctxt));
5747 ctxt.seid = vsi->seid;
5748 ctxt.pf_num = hw->pf_id;
5749 ctxt.uplink_seid = vsi->uplink_seid;
5751 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5752 if (ret != I40E_SUCCESS) {
5753 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5754 goto fail_msix_alloc;
5756 rte_memcpy(&vsi->info, &ctxt.info,
5757 sizeof(struct i40e_aqc_vsi_properties_data));
5758 vsi->vsi_id = ctxt.vsi_number;
5759 vsi->info.valid_sections = 0;
5761 /* Configure tc, enabled TC0 only */
5762 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5764 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5765 goto fail_msix_alloc;
5768 /* TC, queue mapping */
5769 memset(&ctxt, 0, sizeof(ctxt));
5770 vsi->info.valid_sections |=
5771 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5772 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5773 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5774 rte_memcpy(&ctxt.info, &vsi->info,
5775 sizeof(struct i40e_aqc_vsi_properties_data));
5776 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5777 I40E_DEFAULT_TCMAP);
5778 if (ret != I40E_SUCCESS) {
5780 "Failed to configure TC queue mapping");
5781 goto fail_msix_alloc;
5783 ctxt.seid = vsi->seid;
5784 ctxt.pf_num = hw->pf_id;
5785 ctxt.uplink_seid = vsi->uplink_seid;
5788 /* Update VSI parameters */
5789 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5790 if (ret != I40E_SUCCESS) {
5791 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5792 goto fail_msix_alloc;
5795 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5796 sizeof(vsi->info.tc_mapping));
5797 rte_memcpy(&vsi->info.queue_mapping,
5798 &ctxt.info.queue_mapping,
5799 sizeof(vsi->info.queue_mapping));
5800 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5801 vsi->info.valid_sections = 0;
5803 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5807 * Updating default filter settings are necessary to prevent
5808 * reception of tagged packets.
5809 * Some old firmware configurations load a default macvlan
5810 * filter which accepts both tagged and untagged packets.
5811 * The updating is to use a normal filter instead if needed.
5812 * For NVM 4.2.2 or after, the updating is not needed anymore.
5813 * The firmware with correct configurations load the default
5814 * macvlan filter which is expected and cannot be removed.
5816 i40e_update_default_filter_setting(vsi);
5817 i40e_config_qinq(hw, vsi);
5818 } else if (type == I40E_VSI_SRIOV) {
5819 memset(&ctxt, 0, sizeof(ctxt));
5821 * For other VSI, the uplink_seid equals to uplink VSI's
5822 * uplink_seid since they share same VEB
5824 if (uplink_vsi == NULL)
5825 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5827 vsi->uplink_seid = uplink_vsi->uplink_seid;
5828 ctxt.pf_num = hw->pf_id;
5829 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5830 ctxt.uplink_seid = vsi->uplink_seid;
5831 ctxt.connection_type = 0x1;
5832 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5834 /* Use the VEB configuration if FW >= v5.0 */
5835 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5836 /* Configure switch ID */
5837 ctxt.info.valid_sections |=
5838 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5839 ctxt.info.switch_id =
5840 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5843 /* Configure port/vlan */
5844 ctxt.info.valid_sections |=
5845 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5846 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5847 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5848 hw->func_caps.enabled_tcmap);
5849 if (ret != I40E_SUCCESS) {
5851 "Failed to configure TC queue mapping");
5852 goto fail_msix_alloc;
5855 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5856 ctxt.info.valid_sections |=
5857 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5859 * Since VSI is not created yet, only configure parameter,
5860 * will add vsi below.
5863 i40e_config_qinq(hw, vsi);
5864 } else if (type == I40E_VSI_VMDQ2) {
5865 memset(&ctxt, 0, sizeof(ctxt));
5867 * For other VSI, the uplink_seid equals to uplink VSI's
5868 * uplink_seid since they share same VEB
5870 vsi->uplink_seid = uplink_vsi->uplink_seid;
5871 ctxt.pf_num = hw->pf_id;
5873 ctxt.uplink_seid = vsi->uplink_seid;
5874 ctxt.connection_type = 0x1;
5875 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5877 ctxt.info.valid_sections |=
5878 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5879 /* user_param carries flag to enable loop back */
5881 ctxt.info.switch_id =
5882 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5883 ctxt.info.switch_id |=
5884 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5887 /* Configure port/vlan */
5888 ctxt.info.valid_sections |=
5889 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5890 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5891 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5892 I40E_DEFAULT_TCMAP);
5893 if (ret != I40E_SUCCESS) {
5895 "Failed to configure TC queue mapping");
5896 goto fail_msix_alloc;
5898 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5899 ctxt.info.valid_sections |=
5900 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5901 } else if (type == I40E_VSI_FDIR) {
5902 memset(&ctxt, 0, sizeof(ctxt));
5903 vsi->uplink_seid = uplink_vsi->uplink_seid;
5904 ctxt.pf_num = hw->pf_id;
5906 ctxt.uplink_seid = vsi->uplink_seid;
5907 ctxt.connection_type = 0x1; /* regular data port */
5908 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5909 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5910 I40E_DEFAULT_TCMAP);
5911 if (ret != I40E_SUCCESS) {
5913 "Failed to configure TC queue mapping.");
5914 goto fail_msix_alloc;
5916 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5917 ctxt.info.valid_sections |=
5918 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5920 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5921 goto fail_msix_alloc;
5924 if (vsi->type != I40E_VSI_MAIN) {
5925 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5926 if (ret != I40E_SUCCESS) {
5927 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5928 hw->aq.asq_last_status);
5929 goto fail_msix_alloc;
5931 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5932 vsi->info.valid_sections = 0;
5933 vsi->seid = ctxt.seid;
5934 vsi->vsi_id = ctxt.vsi_number;
5935 vsi->sib_vsi_list.vsi = vsi;
5936 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5937 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5938 &vsi->sib_vsi_list, list);
5940 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5941 &vsi->sib_vsi_list, list);
5945 /* MAC/VLAN configuration */
5946 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5947 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5949 ret = i40e_vsi_add_mac(vsi, &filter);
5950 if (ret != I40E_SUCCESS) {
5951 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5952 goto fail_msix_alloc;
5955 /* Get VSI BW information */
5956 i40e_vsi_get_bw_config(vsi);
5959 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5961 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5967 /* Configure vlan filter on or off */
5969 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5972 struct i40e_mac_filter *f;
5974 struct i40e_mac_filter_info *mac_filter;
5975 enum rte_mac_filter_type desired_filter;
5976 int ret = I40E_SUCCESS;
5979 /* Filter to match MAC and VLAN */
5980 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5982 /* Filter to match only MAC */
5983 desired_filter = RTE_MAC_PERFECT_MATCH;
5988 mac_filter = rte_zmalloc("mac_filter_info_data",
5989 num * sizeof(*mac_filter), 0);
5990 if (mac_filter == NULL) {
5991 PMD_DRV_LOG(ERR, "failed to allocate memory");
5992 return I40E_ERR_NO_MEMORY;
5997 /* Remove all existing mac */
5998 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5999 mac_filter[i] = f->mac_info;
6000 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6002 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6003 on ? "enable" : "disable");
6009 /* Override with new filter */
6010 for (i = 0; i < num; i++) {
6011 mac_filter[i].filter_type = desired_filter;
6012 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6014 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6015 on ? "enable" : "disable");
6021 rte_free(mac_filter);
6025 /* Configure vlan stripping on or off */
6027 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6029 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6030 struct i40e_vsi_context ctxt;
6032 int ret = I40E_SUCCESS;
6034 /* Check if it has been already on or off */
6035 if (vsi->info.valid_sections &
6036 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6038 if ((vsi->info.port_vlan_flags &
6039 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6040 return 0; /* already on */
6042 if ((vsi->info.port_vlan_flags &
6043 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6044 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6045 return 0; /* already off */
6050 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6052 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6053 vsi->info.valid_sections =
6054 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6055 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6056 vsi->info.port_vlan_flags |= vlan_flags;
6057 ctxt.seid = vsi->seid;
6058 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6059 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6061 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6062 on ? "enable" : "disable");
6068 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6070 struct rte_eth_dev_data *data = dev->data;
6074 /* Apply vlan offload setting */
6075 mask = ETH_VLAN_STRIP_MASK |
6076 ETH_VLAN_FILTER_MASK |
6077 ETH_VLAN_EXTEND_MASK;
6078 ret = i40e_vlan_offload_set(dev, mask);
6080 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6084 /* Apply pvid setting */
6085 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6086 data->dev_conf.txmode.hw_vlan_insert_pvid);
6088 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6094 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6096 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6098 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6102 i40e_update_flow_control(struct i40e_hw *hw)
6104 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6105 struct i40e_link_status link_status;
6106 uint32_t rxfc = 0, txfc = 0, reg;
6110 memset(&link_status, 0, sizeof(link_status));
6111 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6112 if (ret != I40E_SUCCESS) {
6113 PMD_DRV_LOG(ERR, "Failed to get link status information");
6114 goto write_reg; /* Disable flow control */
6117 an_info = hw->phy.link_info.an_info;
6118 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6119 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6120 ret = I40E_ERR_NOT_READY;
6121 goto write_reg; /* Disable flow control */
6124 * If link auto negotiation is enabled, flow control needs to
6125 * be configured according to it
6127 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6128 case I40E_LINK_PAUSE_RXTX:
6131 hw->fc.current_mode = I40E_FC_FULL;
6133 case I40E_AQ_LINK_PAUSE_RX:
6135 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6137 case I40E_AQ_LINK_PAUSE_TX:
6139 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6142 hw->fc.current_mode = I40E_FC_NONE;
6147 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6148 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6149 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6150 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6151 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6152 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6159 i40e_pf_setup(struct i40e_pf *pf)
6161 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6162 struct i40e_filter_control_settings settings;
6163 struct i40e_vsi *vsi;
6166 /* Clear all stats counters */
6167 pf->offset_loaded = FALSE;
6168 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6169 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6170 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6171 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6173 ret = i40e_pf_get_switch_config(pf);
6174 if (ret != I40E_SUCCESS) {
6175 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6179 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6181 PMD_INIT_LOG(WARNING,
6182 "failed to allocate switch domain for device %d", ret);
6184 if (pf->flags & I40E_FLAG_FDIR) {
6185 /* make queue allocated first, let FDIR use queue pair 0*/
6186 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6187 if (ret != I40E_FDIR_QUEUE_ID) {
6189 "queue allocation fails for FDIR: ret =%d",
6191 pf->flags &= ~I40E_FLAG_FDIR;
6194 /* main VSI setup */
6195 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6197 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6198 return I40E_ERR_NOT_READY;
6202 /* Configure filter control */
6203 memset(&settings, 0, sizeof(settings));
6204 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6205 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6206 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6207 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6209 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6210 hw->func_caps.rss_table_size);
6211 return I40E_ERR_PARAM;
6213 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6214 hw->func_caps.rss_table_size);
6215 pf->hash_lut_size = hw->func_caps.rss_table_size;
6217 /* Enable ethtype and macvlan filters */
6218 settings.enable_ethtype = TRUE;
6219 settings.enable_macvlan = TRUE;
6220 ret = i40e_set_filter_control(hw, &settings);
6222 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6225 /* Update flow control according to the auto negotiation */
6226 i40e_update_flow_control(hw);
6228 return I40E_SUCCESS;
6232 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6238 * Set or clear TX Queue Disable flags,
6239 * which is required by hardware.
6241 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6242 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6244 /* Wait until the request is finished */
6245 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6246 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6247 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6248 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6249 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6255 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6256 return I40E_SUCCESS; /* already on, skip next steps */
6258 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6259 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6261 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6262 return I40E_SUCCESS; /* already off, skip next steps */
6263 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6265 /* Write the register */
6266 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6267 /* Check the result */
6268 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6269 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6270 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6272 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6273 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6276 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6277 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6281 /* Check if it is timeout */
6282 if (j >= I40E_CHK_Q_ENA_COUNT) {
6283 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6284 (on ? "enable" : "disable"), q_idx);
6285 return I40E_ERR_TIMEOUT;
6288 return I40E_SUCCESS;
6292 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6297 /* Wait until the request is finished */
6298 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6299 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6300 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6301 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6302 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6307 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6308 return I40E_SUCCESS; /* Already on, skip next steps */
6309 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6311 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6312 return I40E_SUCCESS; /* Already off, skip next steps */
6313 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6316 /* Write the register */
6317 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6318 /* Check the result */
6319 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6320 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6321 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6323 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6324 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6327 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6328 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6333 /* Check if it is timeout */
6334 if (j >= I40E_CHK_Q_ENA_COUNT) {
6335 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6336 (on ? "enable" : "disable"), q_idx);
6337 return I40E_ERR_TIMEOUT;
6340 return I40E_SUCCESS;
6343 /* Initialize VSI for TX */
6345 i40e_dev_tx_init(struct i40e_pf *pf)
6347 struct rte_eth_dev_data *data = pf->dev_data;
6349 uint32_t ret = I40E_SUCCESS;
6350 struct i40e_tx_queue *txq;
6352 for (i = 0; i < data->nb_tx_queues; i++) {
6353 txq = data->tx_queues[i];
6354 if (!txq || !txq->q_set)
6356 ret = i40e_tx_queue_init(txq);
6357 if (ret != I40E_SUCCESS)
6360 if (ret == I40E_SUCCESS)
6361 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6367 /* Initialize VSI for RX */
6369 i40e_dev_rx_init(struct i40e_pf *pf)
6371 struct rte_eth_dev_data *data = pf->dev_data;
6372 int ret = I40E_SUCCESS;
6374 struct i40e_rx_queue *rxq;
6376 i40e_pf_config_mq_rx(pf);
6377 for (i = 0; i < data->nb_rx_queues; i++) {
6378 rxq = data->rx_queues[i];
6379 if (!rxq || !rxq->q_set)
6382 ret = i40e_rx_queue_init(rxq);
6383 if (ret != I40E_SUCCESS) {
6385 "Failed to do RX queue initialization");
6389 if (ret == I40E_SUCCESS)
6390 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6397 i40e_dev_rxtx_init(struct i40e_pf *pf)
6401 err = i40e_dev_tx_init(pf);
6403 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6406 err = i40e_dev_rx_init(pf);
6408 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6416 i40e_vmdq_setup(struct rte_eth_dev *dev)
6418 struct rte_eth_conf *conf = &dev->data->dev_conf;
6419 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6420 int i, err, conf_vsis, j, loop;
6421 struct i40e_vsi *vsi;
6422 struct i40e_vmdq_info *vmdq_info;
6423 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6424 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6427 * Disable interrupt to avoid message from VF. Furthermore, it will
6428 * avoid race condition in VSI creation/destroy.
6430 i40e_pf_disable_irq0(hw);
6432 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6433 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6437 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6438 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6439 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6440 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6441 pf->max_nb_vmdq_vsi);
6445 if (pf->vmdq != NULL) {
6446 PMD_INIT_LOG(INFO, "VMDQ already configured");
6450 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6451 sizeof(*vmdq_info) * conf_vsis, 0);
6453 if (pf->vmdq == NULL) {
6454 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6458 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6460 /* Create VMDQ VSI */
6461 for (i = 0; i < conf_vsis; i++) {
6462 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6463 vmdq_conf->enable_loop_back);
6465 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6469 vmdq_info = &pf->vmdq[i];
6471 vmdq_info->vsi = vsi;
6473 pf->nb_cfg_vmdq_vsi = conf_vsis;
6475 /* Configure Vlan */
6476 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6477 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6478 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6479 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6480 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6481 vmdq_conf->pool_map[i].vlan_id, j);
6483 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6484 vmdq_conf->pool_map[i].vlan_id);
6486 PMD_INIT_LOG(ERR, "Failed to add vlan");
6494 i40e_pf_enable_irq0(hw);
6499 for (i = 0; i < conf_vsis; i++)
6500 if (pf->vmdq[i].vsi == NULL)
6503 i40e_vsi_release(pf->vmdq[i].vsi);
6507 i40e_pf_enable_irq0(hw);
6512 i40e_stat_update_32(struct i40e_hw *hw,
6520 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6524 if (new_data >= *offset)
6525 *stat = (uint64_t)(new_data - *offset);
6527 *stat = (uint64_t)((new_data +
6528 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6532 i40e_stat_update_48(struct i40e_hw *hw,
6541 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6542 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6543 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6548 if (new_data >= *offset)
6549 *stat = new_data - *offset;
6551 *stat = (uint64_t)((new_data +
6552 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6554 *stat &= I40E_48_BIT_MASK;
6559 i40e_pf_disable_irq0(struct i40e_hw *hw)
6561 /* Disable all interrupt types */
6562 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6563 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6564 I40E_WRITE_FLUSH(hw);
6569 i40e_pf_enable_irq0(struct i40e_hw *hw)
6571 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6572 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6573 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6574 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6575 I40E_WRITE_FLUSH(hw);
6579 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6581 /* read pending request and disable first */
6582 i40e_pf_disable_irq0(hw);
6583 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6584 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6585 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6588 /* Link no queues with irq0 */
6589 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6590 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6594 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6597 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6600 uint32_t index, offset, val;
6605 * Try to find which VF trigger a reset, use absolute VF id to access
6606 * since the reg is global register.
6608 for (i = 0; i < pf->vf_num; i++) {
6609 abs_vf_id = hw->func_caps.vf_base_id + i;
6610 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6611 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6612 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6613 /* VFR event occurred */
6614 if (val & (0x1 << offset)) {
6617 /* Clear the event first */
6618 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6620 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6622 * Only notify a VF reset event occurred,
6623 * don't trigger another SW reset
6625 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6626 if (ret != I40E_SUCCESS)
6627 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6633 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6635 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6638 for (i = 0; i < pf->vf_num; i++)
6639 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6643 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6645 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6646 struct i40e_arq_event_info info;
6647 uint16_t pending, opcode;
6650 info.buf_len = I40E_AQ_BUF_SZ;
6651 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6652 if (!info.msg_buf) {
6653 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6659 ret = i40e_clean_arq_element(hw, &info, &pending);
6661 if (ret != I40E_SUCCESS) {
6663 "Failed to read msg from AdminQ, aq_err: %u",
6664 hw->aq.asq_last_status);
6667 opcode = rte_le_to_cpu_16(info.desc.opcode);
6670 case i40e_aqc_opc_send_msg_to_pf:
6671 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6672 i40e_pf_host_handle_vf_msg(dev,
6673 rte_le_to_cpu_16(info.desc.retval),
6674 rte_le_to_cpu_32(info.desc.cookie_high),
6675 rte_le_to_cpu_32(info.desc.cookie_low),
6679 case i40e_aqc_opc_get_link_status:
6680 ret = i40e_dev_link_update(dev, 0);
6682 _rte_eth_dev_callback_process(dev,
6683 RTE_ETH_EVENT_INTR_LSC, NULL);
6686 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6691 rte_free(info.msg_buf);
6695 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6697 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6698 #define I40E_MDD_CLEAR16 0xFFFF
6699 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6701 bool mdd_detected = false;
6702 struct i40e_pf_vf *vf;
6706 /* find what triggered the MDD event */
6707 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6708 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6709 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6710 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6711 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6712 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6713 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6714 I40E_GL_MDET_TX_EVENT_SHIFT;
6715 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6716 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6717 hw->func_caps.base_queue;
6718 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6719 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6720 event, queue, pf_num, vf_num, dev->data->name);
6721 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6722 mdd_detected = true;
6724 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6725 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6726 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6727 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6728 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6729 I40E_GL_MDET_RX_EVENT_SHIFT;
6730 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6731 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6732 hw->func_caps.base_queue;
6734 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6735 "queue %d of function 0x%02x device %s\n",
6736 event, queue, func, dev->data->name);
6737 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6738 mdd_detected = true;
6742 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6743 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6744 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6745 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6747 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6748 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6749 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6751 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6755 /* see if one of the VFs needs its hand slapped */
6756 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6758 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6759 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6760 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6762 vf->num_mdd_events++;
6763 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6765 i, vf->num_mdd_events);
6768 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6769 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6770 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6772 vf->num_mdd_events++;
6773 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6775 i, vf->num_mdd_events);
6781 * Interrupt handler triggered by NIC for handling
6782 * specific interrupt.
6785 * Pointer to interrupt handle.
6787 * The address of parameter (struct rte_eth_dev *) regsitered before.
6793 i40e_dev_interrupt_handler(void *param)
6795 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799 /* Disable interrupt */
6800 i40e_pf_disable_irq0(hw);
6802 /* read out interrupt causes */
6803 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6805 /* No interrupt event indicated */
6806 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6807 PMD_DRV_LOG(INFO, "No interrupt event");
6810 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6811 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6812 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6813 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6814 i40e_handle_mdd_event(dev);
6816 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6817 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6818 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6819 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6820 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6821 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6822 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6823 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6824 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6825 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6827 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6828 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6829 i40e_dev_handle_vfr_event(dev);
6831 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6832 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6833 i40e_dev_handle_aq_msg(dev);
6837 /* Enable interrupt */
6838 i40e_pf_enable_irq0(hw);
6842 i40e_dev_alarm_handler(void *param)
6844 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6848 /* Disable interrupt */
6849 i40e_pf_disable_irq0(hw);
6851 /* read out interrupt causes */
6852 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6854 /* No interrupt event indicated */
6855 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6857 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6858 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6859 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6860 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6861 i40e_handle_mdd_event(dev);
6863 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6864 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6865 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6866 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6867 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6868 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6869 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6870 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6871 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6872 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6874 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6875 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6876 i40e_dev_handle_vfr_event(dev);
6878 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6879 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6880 i40e_dev_handle_aq_msg(dev);
6884 /* Enable interrupt */
6885 i40e_pf_enable_irq0(hw);
6886 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6887 i40e_dev_alarm_handler, dev);
6891 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6892 struct i40e_macvlan_filter *filter,
6895 int ele_num, ele_buff_size;
6896 int num, actual_num, i;
6898 int ret = I40E_SUCCESS;
6899 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6900 struct i40e_aqc_add_macvlan_element_data *req_list;
6902 if (filter == NULL || total == 0)
6903 return I40E_ERR_PARAM;
6904 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6905 ele_buff_size = hw->aq.asq_buf_size;
6907 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6908 if (req_list == NULL) {
6909 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6910 return I40E_ERR_NO_MEMORY;
6915 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6916 memset(req_list, 0, ele_buff_size);
6918 for (i = 0; i < actual_num; i++) {
6919 rte_memcpy(req_list[i].mac_addr,
6920 &filter[num + i].macaddr, ETH_ADDR_LEN);
6921 req_list[i].vlan_tag =
6922 rte_cpu_to_le_16(filter[num + i].vlan_id);
6924 switch (filter[num + i].filter_type) {
6925 case RTE_MAC_PERFECT_MATCH:
6926 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6927 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6929 case RTE_MACVLAN_PERFECT_MATCH:
6930 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6932 case RTE_MAC_HASH_MATCH:
6933 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6934 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6936 case RTE_MACVLAN_HASH_MATCH:
6937 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6940 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6941 ret = I40E_ERR_PARAM;
6945 req_list[i].queue_number = 0;
6947 req_list[i].flags = rte_cpu_to_le_16(flags);
6950 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6952 if (ret != I40E_SUCCESS) {
6953 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6957 } while (num < total);
6965 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6966 struct i40e_macvlan_filter *filter,
6969 int ele_num, ele_buff_size;
6970 int num, actual_num, i;
6972 int ret = I40E_SUCCESS;
6973 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6974 struct i40e_aqc_remove_macvlan_element_data *req_list;
6976 if (filter == NULL || total == 0)
6977 return I40E_ERR_PARAM;
6979 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6980 ele_buff_size = hw->aq.asq_buf_size;
6982 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6983 if (req_list == NULL) {
6984 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6985 return I40E_ERR_NO_MEMORY;
6990 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6991 memset(req_list, 0, ele_buff_size);
6993 for (i = 0; i < actual_num; i++) {
6994 rte_memcpy(req_list[i].mac_addr,
6995 &filter[num + i].macaddr, ETH_ADDR_LEN);
6996 req_list[i].vlan_tag =
6997 rte_cpu_to_le_16(filter[num + i].vlan_id);
6999 switch (filter[num + i].filter_type) {
7000 case RTE_MAC_PERFECT_MATCH:
7001 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7002 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7004 case RTE_MACVLAN_PERFECT_MATCH:
7005 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7007 case RTE_MAC_HASH_MATCH:
7008 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7009 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7011 case RTE_MACVLAN_HASH_MATCH:
7012 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7015 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7016 ret = I40E_ERR_PARAM;
7019 req_list[i].flags = rte_cpu_to_le_16(flags);
7022 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7024 if (ret != I40E_SUCCESS) {
7025 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7029 } while (num < total);
7036 /* Find out specific MAC filter */
7037 static struct i40e_mac_filter *
7038 i40e_find_mac_filter(struct i40e_vsi *vsi,
7039 struct rte_ether_addr *macaddr)
7041 struct i40e_mac_filter *f;
7043 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7044 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7052 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7055 uint32_t vid_idx, vid_bit;
7057 if (vlan_id > ETH_VLAN_ID_MAX)
7060 vid_idx = I40E_VFTA_IDX(vlan_id);
7061 vid_bit = I40E_VFTA_BIT(vlan_id);
7063 if (vsi->vfta[vid_idx] & vid_bit)
7070 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7071 uint16_t vlan_id, bool on)
7073 uint32_t vid_idx, vid_bit;
7075 vid_idx = I40E_VFTA_IDX(vlan_id);
7076 vid_bit = I40E_VFTA_BIT(vlan_id);
7079 vsi->vfta[vid_idx] |= vid_bit;
7081 vsi->vfta[vid_idx] &= ~vid_bit;
7085 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7086 uint16_t vlan_id, bool on)
7088 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7089 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7092 if (vlan_id > ETH_VLAN_ID_MAX)
7095 i40e_store_vlan_filter(vsi, vlan_id, on);
7097 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7100 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7103 ret = i40e_aq_add_vlan(hw, vsi->seid,
7104 &vlan_data, 1, NULL);
7105 if (ret != I40E_SUCCESS)
7106 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7108 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7109 &vlan_data, 1, NULL);
7110 if (ret != I40E_SUCCESS)
7112 "Failed to remove vlan filter");
7117 * Find all vlan options for specific mac addr,
7118 * return with actual vlan found.
7121 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7122 struct i40e_macvlan_filter *mv_f,
7123 int num, struct rte_ether_addr *addr)
7129 * Not to use i40e_find_vlan_filter to decrease the loop time,
7130 * although the code looks complex.
7132 if (num < vsi->vlan_num)
7133 return I40E_ERR_PARAM;
7136 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7138 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7139 if (vsi->vfta[j] & (1 << k)) {
7142 "vlan number doesn't match");
7143 return I40E_ERR_PARAM;
7145 rte_memcpy(&mv_f[i].macaddr,
7146 addr, ETH_ADDR_LEN);
7148 j * I40E_UINT32_BIT_SIZE + k;
7154 return I40E_SUCCESS;
7158 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7159 struct i40e_macvlan_filter *mv_f,
7164 struct i40e_mac_filter *f;
7166 if (num < vsi->mac_num)
7167 return I40E_ERR_PARAM;
7169 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7171 PMD_DRV_LOG(ERR, "buffer number not match");
7172 return I40E_ERR_PARAM;
7174 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7176 mv_f[i].vlan_id = vlan;
7177 mv_f[i].filter_type = f->mac_info.filter_type;
7181 return I40E_SUCCESS;
7185 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7188 struct i40e_mac_filter *f;
7189 struct i40e_macvlan_filter *mv_f;
7190 int ret = I40E_SUCCESS;
7192 if (vsi == NULL || vsi->mac_num == 0)
7193 return I40E_ERR_PARAM;
7195 /* Case that no vlan is set */
7196 if (vsi->vlan_num == 0)
7199 num = vsi->mac_num * vsi->vlan_num;
7201 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7203 PMD_DRV_LOG(ERR, "failed to allocate memory");
7204 return I40E_ERR_NO_MEMORY;
7208 if (vsi->vlan_num == 0) {
7209 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7210 rte_memcpy(&mv_f[i].macaddr,
7211 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7212 mv_f[i].filter_type = f->mac_info.filter_type;
7213 mv_f[i].vlan_id = 0;
7217 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7218 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7219 vsi->vlan_num, &f->mac_info.mac_addr);
7220 if (ret != I40E_SUCCESS)
7222 for (j = i; j < i + vsi->vlan_num; j++)
7223 mv_f[j].filter_type = f->mac_info.filter_type;
7228 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7236 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7238 struct i40e_macvlan_filter *mv_f;
7240 int ret = I40E_SUCCESS;
7242 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7243 return I40E_ERR_PARAM;
7245 /* If it's already set, just return */
7246 if (i40e_find_vlan_filter(vsi,vlan))
7247 return I40E_SUCCESS;
7249 mac_num = vsi->mac_num;
7252 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7253 return I40E_ERR_PARAM;
7256 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7259 PMD_DRV_LOG(ERR, "failed to allocate memory");
7260 return I40E_ERR_NO_MEMORY;
7263 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7265 if (ret != I40E_SUCCESS)
7268 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7270 if (ret != I40E_SUCCESS)
7273 i40e_set_vlan_filter(vsi, vlan, 1);
7283 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7285 struct i40e_macvlan_filter *mv_f;
7287 int ret = I40E_SUCCESS;
7290 * Vlan 0 is the generic filter for untagged packets
7291 * and can't be removed.
7293 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7294 return I40E_ERR_PARAM;
7296 /* If can't find it, just return */
7297 if (!i40e_find_vlan_filter(vsi, vlan))
7298 return I40E_ERR_PARAM;
7300 mac_num = vsi->mac_num;
7303 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7304 return I40E_ERR_PARAM;
7307 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7310 PMD_DRV_LOG(ERR, "failed to allocate memory");
7311 return I40E_ERR_NO_MEMORY;
7314 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7316 if (ret != I40E_SUCCESS)
7319 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7321 if (ret != I40E_SUCCESS)
7324 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7325 if (vsi->vlan_num == 1) {
7326 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7327 if (ret != I40E_SUCCESS)
7330 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7331 if (ret != I40E_SUCCESS)
7335 i40e_set_vlan_filter(vsi, vlan, 0);
7345 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7347 struct i40e_mac_filter *f;
7348 struct i40e_macvlan_filter *mv_f;
7349 int i, vlan_num = 0;
7350 int ret = I40E_SUCCESS;
7352 /* If it's add and we've config it, return */
7353 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7355 return I40E_SUCCESS;
7356 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7357 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7360 * If vlan_num is 0, that's the first time to add mac,
7361 * set mask for vlan_id 0.
7363 if (vsi->vlan_num == 0) {
7364 i40e_set_vlan_filter(vsi, 0, 1);
7367 vlan_num = vsi->vlan_num;
7368 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7369 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7372 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7374 PMD_DRV_LOG(ERR, "failed to allocate memory");
7375 return I40E_ERR_NO_MEMORY;
7378 for (i = 0; i < vlan_num; i++) {
7379 mv_f[i].filter_type = mac_filter->filter_type;
7380 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7384 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7385 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7386 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7387 &mac_filter->mac_addr);
7388 if (ret != I40E_SUCCESS)
7392 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7393 if (ret != I40E_SUCCESS)
7396 /* Add the mac addr into mac list */
7397 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7399 PMD_DRV_LOG(ERR, "failed to allocate memory");
7400 ret = I40E_ERR_NO_MEMORY;
7403 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7405 f->mac_info.filter_type = mac_filter->filter_type;
7406 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7417 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7419 struct i40e_mac_filter *f;
7420 struct i40e_macvlan_filter *mv_f;
7422 enum rte_mac_filter_type filter_type;
7423 int ret = I40E_SUCCESS;
7425 /* Can't find it, return an error */
7426 f = i40e_find_mac_filter(vsi, addr);
7428 return I40E_ERR_PARAM;
7430 vlan_num = vsi->vlan_num;
7431 filter_type = f->mac_info.filter_type;
7432 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7433 filter_type == RTE_MACVLAN_HASH_MATCH) {
7434 if (vlan_num == 0) {
7435 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7436 return I40E_ERR_PARAM;
7438 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7439 filter_type == RTE_MAC_HASH_MATCH)
7442 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7444 PMD_DRV_LOG(ERR, "failed to allocate memory");
7445 return I40E_ERR_NO_MEMORY;
7448 for (i = 0; i < vlan_num; i++) {
7449 mv_f[i].filter_type = filter_type;
7450 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7453 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7454 filter_type == RTE_MACVLAN_HASH_MATCH) {
7455 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7456 if (ret != I40E_SUCCESS)
7460 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7461 if (ret != I40E_SUCCESS)
7464 /* Remove the mac addr into mac list */
7465 TAILQ_REMOVE(&vsi->mac_list, f, next);
7475 /* Configure hash enable flags for RSS */
7477 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7485 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7486 if (flags & (1ULL << i))
7487 hena |= adapter->pctypes_tbl[i];
7493 /* Parse the hash enable flags */
7495 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7497 uint64_t rss_hf = 0;
7503 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7504 if (flags & adapter->pctypes_tbl[i])
7505 rss_hf |= (1ULL << i);
7512 i40e_pf_disable_rss(struct i40e_pf *pf)
7514 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7516 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7517 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7518 I40E_WRITE_FLUSH(hw);
7522 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7524 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7525 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7526 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7527 I40E_VFQF_HKEY_MAX_INDEX :
7528 I40E_PFQF_HKEY_MAX_INDEX;
7531 if (!key || key_len == 0) {
7532 PMD_DRV_LOG(DEBUG, "No key to be configured");
7534 } else if (key_len != (key_idx + 1) *
7536 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7540 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7541 struct i40e_aqc_get_set_rss_key_data *key_dw =
7542 (struct i40e_aqc_get_set_rss_key_data *)key;
7544 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7546 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7548 uint32_t *hash_key = (uint32_t *)key;
7551 if (vsi->type == I40E_VSI_SRIOV) {
7552 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7555 I40E_VFQF_HKEY1(i, vsi->user_param),
7559 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7560 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7563 I40E_WRITE_FLUSH(hw);
7570 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7572 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7573 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7577 if (!key || !key_len)
7580 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7581 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7582 (struct i40e_aqc_get_set_rss_key_data *)key);
7584 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7588 uint32_t *key_dw = (uint32_t *)key;
7591 if (vsi->type == I40E_VSI_SRIOV) {
7592 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7593 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7594 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7596 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7599 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7600 reg = I40E_PFQF_HKEY(i);
7601 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7603 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7611 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7613 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7617 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7618 rss_conf->rss_key_len);
7622 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7623 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7624 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7625 I40E_WRITE_FLUSH(hw);
7631 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7632 struct rte_eth_rss_conf *rss_conf)
7634 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7636 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7639 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7640 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7642 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7643 if (rss_hf != 0) /* Enable RSS */
7645 return 0; /* Nothing to do */
7648 if (rss_hf == 0) /* Disable RSS */
7651 return i40e_hw_rss_hash_set(pf, rss_conf);
7655 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7656 struct rte_eth_rss_conf *rss_conf)
7658 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7666 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7667 &rss_conf->rss_key_len);
7671 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7672 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7673 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7679 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7681 switch (filter_type) {
7682 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7683 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7685 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7686 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7688 case RTE_TUNNEL_FILTER_IMAC_TENID:
7689 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7691 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7692 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7694 case ETH_TUNNEL_FILTER_IMAC:
7695 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7697 case ETH_TUNNEL_FILTER_OIP:
7698 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7700 case ETH_TUNNEL_FILTER_IIP:
7701 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7704 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7711 /* Convert tunnel filter structure */
7713 i40e_tunnel_filter_convert(
7714 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7715 struct i40e_tunnel_filter *tunnel_filter)
7717 rte_ether_addr_copy((struct rte_ether_addr *)
7718 &cld_filter->element.outer_mac,
7719 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7720 rte_ether_addr_copy((struct rte_ether_addr *)
7721 &cld_filter->element.inner_mac,
7722 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7723 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7724 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7725 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7726 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7727 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7729 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7730 tunnel_filter->input.flags = cld_filter->element.flags;
7731 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7732 tunnel_filter->queue = cld_filter->element.queue_number;
7733 rte_memcpy(tunnel_filter->input.general_fields,
7734 cld_filter->general_fields,
7735 sizeof(cld_filter->general_fields));
7740 /* Check if there exists the tunnel filter */
7741 struct i40e_tunnel_filter *
7742 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7743 const struct i40e_tunnel_filter_input *input)
7747 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7751 return tunnel_rule->hash_map[ret];
7754 /* Add a tunnel filter into the SW list */
7756 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7757 struct i40e_tunnel_filter *tunnel_filter)
7759 struct i40e_tunnel_rule *rule = &pf->tunnel;
7762 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7765 "Failed to insert tunnel filter to hash table %d!",
7769 rule->hash_map[ret] = tunnel_filter;
7771 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7776 /* Delete a tunnel filter from the SW list */
7778 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7779 struct i40e_tunnel_filter_input *input)
7781 struct i40e_tunnel_rule *rule = &pf->tunnel;
7782 struct i40e_tunnel_filter *tunnel_filter;
7785 ret = rte_hash_del_key(rule->hash_table, input);
7788 "Failed to delete tunnel filter to hash table %d!",
7792 tunnel_filter = rule->hash_map[ret];
7793 rule->hash_map[ret] = NULL;
7795 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7796 rte_free(tunnel_filter);
7802 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7803 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7807 uint32_t ipv4_addr, ipv4_addr_le;
7808 uint8_t i, tun_type = 0;
7809 /* internal varialbe to convert ipv6 byte order */
7810 uint32_t convert_ipv6[4];
7812 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7813 struct i40e_vsi *vsi = pf->main_vsi;
7814 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7815 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7816 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7817 struct i40e_tunnel_filter *tunnel, *node;
7818 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7820 cld_filter = rte_zmalloc("tunnel_filter",
7821 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7824 if (NULL == cld_filter) {
7825 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7828 pfilter = cld_filter;
7830 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7831 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7832 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7833 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7835 pfilter->element.inner_vlan =
7836 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7837 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7838 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7839 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7840 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7841 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7843 sizeof(pfilter->element.ipaddr.v4.data));
7845 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7846 for (i = 0; i < 4; i++) {
7848 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7850 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7852 sizeof(pfilter->element.ipaddr.v6.data));
7855 /* check tunneled type */
7856 switch (tunnel_filter->tunnel_type) {
7857 case RTE_TUNNEL_TYPE_VXLAN:
7858 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7860 case RTE_TUNNEL_TYPE_NVGRE:
7861 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7863 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7864 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7866 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7867 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7870 /* Other tunnel types is not supported. */
7871 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7872 rte_free(cld_filter);
7876 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7877 &pfilter->element.flags);
7879 rte_free(cld_filter);
7883 pfilter->element.flags |= rte_cpu_to_le_16(
7884 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7885 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7886 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7887 pfilter->element.queue_number =
7888 rte_cpu_to_le_16(tunnel_filter->queue_id);
7890 /* Check if there is the filter in SW list */
7891 memset(&check_filter, 0, sizeof(check_filter));
7892 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7893 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7895 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7896 rte_free(cld_filter);
7900 if (!add && !node) {
7901 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7902 rte_free(cld_filter);
7907 ret = i40e_aq_add_cloud_filters(hw,
7908 vsi->seid, &cld_filter->element, 1);
7910 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7911 rte_free(cld_filter);
7914 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7915 if (tunnel == NULL) {
7916 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7917 rte_free(cld_filter);
7921 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7922 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7926 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7927 &cld_filter->element, 1);
7929 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7930 rte_free(cld_filter);
7933 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7936 rte_free(cld_filter);
7940 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7941 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7942 #define I40E_TR_GENEVE_KEY_MASK 0x8
7943 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7944 #define I40E_TR_GRE_KEY_MASK 0x400
7945 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7946 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7949 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7951 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7952 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7953 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7954 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7955 enum i40e_status_code status = I40E_SUCCESS;
7957 if (pf->support_multi_driver) {
7958 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7959 return I40E_NOT_SUPPORTED;
7962 memset(&filter_replace, 0,
7963 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7964 memset(&filter_replace_buf, 0,
7965 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7967 /* create L1 filter */
7968 filter_replace.old_filter_type =
7969 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7970 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7971 filter_replace.tr_bit = 0;
7973 /* Prepare the buffer, 3 entries */
7974 filter_replace_buf.data[0] =
7975 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7976 filter_replace_buf.data[0] |=
7977 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7978 filter_replace_buf.data[2] = 0xFF;
7979 filter_replace_buf.data[3] = 0xFF;
7980 filter_replace_buf.data[4] =
7981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7982 filter_replace_buf.data[4] |=
7983 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7984 filter_replace_buf.data[7] = 0xF0;
7985 filter_replace_buf.data[8]
7986 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7987 filter_replace_buf.data[8] |=
7988 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7989 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7990 I40E_TR_GENEVE_KEY_MASK |
7991 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7992 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7993 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7994 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7996 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7997 &filter_replace_buf);
7998 if (!status && (filter_replace.old_filter_type !=
7999 filter_replace.new_filter_type))
8000 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8001 " original: 0x%x, new: 0x%x",
8003 filter_replace.old_filter_type,
8004 filter_replace.new_filter_type);
8010 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8012 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8013 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8014 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8015 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8016 enum i40e_status_code status = I40E_SUCCESS;
8018 if (pf->support_multi_driver) {
8019 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8020 return I40E_NOT_SUPPORTED;
8024 memset(&filter_replace, 0,
8025 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8026 memset(&filter_replace_buf, 0,
8027 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8028 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8029 I40E_AQC_MIRROR_CLOUD_FILTER;
8030 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8031 filter_replace.new_filter_type =
8032 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8033 /* Prepare the buffer, 2 entries */
8034 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8035 filter_replace_buf.data[0] |=
8036 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8037 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8038 filter_replace_buf.data[4] |=
8039 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8040 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8041 &filter_replace_buf);
8044 if (filter_replace.old_filter_type !=
8045 filter_replace.new_filter_type)
8046 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8047 " original: 0x%x, new: 0x%x",
8049 filter_replace.old_filter_type,
8050 filter_replace.new_filter_type);
8053 memset(&filter_replace, 0,
8054 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8055 memset(&filter_replace_buf, 0,
8056 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8058 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8059 I40E_AQC_MIRROR_CLOUD_FILTER;
8060 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8061 filter_replace.new_filter_type =
8062 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8063 /* Prepare the buffer, 2 entries */
8064 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8065 filter_replace_buf.data[0] |=
8066 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8067 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8068 filter_replace_buf.data[4] |=
8069 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8071 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8072 &filter_replace_buf);
8073 if (!status && (filter_replace.old_filter_type !=
8074 filter_replace.new_filter_type))
8075 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8076 " original: 0x%x, new: 0x%x",
8078 filter_replace.old_filter_type,
8079 filter_replace.new_filter_type);
8084 static enum i40e_status_code
8085 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8087 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8088 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8089 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8090 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8091 enum i40e_status_code status = I40E_SUCCESS;
8093 if (pf->support_multi_driver) {
8094 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8095 return I40E_NOT_SUPPORTED;
8099 memset(&filter_replace, 0,
8100 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8101 memset(&filter_replace_buf, 0,
8102 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8103 /* create L1 filter */
8104 filter_replace.old_filter_type =
8105 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8106 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8107 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8108 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8109 /* Prepare the buffer, 2 entries */
8110 filter_replace_buf.data[0] =
8111 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8112 filter_replace_buf.data[0] |=
8113 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8114 filter_replace_buf.data[2] = 0xFF;
8115 filter_replace_buf.data[3] = 0xFF;
8116 filter_replace_buf.data[4] =
8117 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8118 filter_replace_buf.data[4] |=
8119 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8120 filter_replace_buf.data[6] = 0xFF;
8121 filter_replace_buf.data[7] = 0xFF;
8122 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8123 &filter_replace_buf);
8126 if (filter_replace.old_filter_type !=
8127 filter_replace.new_filter_type)
8128 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8129 " original: 0x%x, new: 0x%x",
8131 filter_replace.old_filter_type,
8132 filter_replace.new_filter_type);
8135 memset(&filter_replace, 0,
8136 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8137 memset(&filter_replace_buf, 0,
8138 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8139 /* create L1 filter */
8140 filter_replace.old_filter_type =
8141 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8142 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8143 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8144 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8145 /* Prepare the buffer, 2 entries */
8146 filter_replace_buf.data[0] =
8147 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8148 filter_replace_buf.data[0] |=
8149 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8150 filter_replace_buf.data[2] = 0xFF;
8151 filter_replace_buf.data[3] = 0xFF;
8152 filter_replace_buf.data[4] =
8153 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8154 filter_replace_buf.data[4] |=
8155 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8156 filter_replace_buf.data[6] = 0xFF;
8157 filter_replace_buf.data[7] = 0xFF;
8159 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8160 &filter_replace_buf);
8161 if (!status && (filter_replace.old_filter_type !=
8162 filter_replace.new_filter_type))
8163 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8164 " original: 0x%x, new: 0x%x",
8166 filter_replace.old_filter_type,
8167 filter_replace.new_filter_type);
8173 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8175 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8176 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8177 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8178 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8179 enum i40e_status_code status = I40E_SUCCESS;
8181 if (pf->support_multi_driver) {
8182 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8183 return I40E_NOT_SUPPORTED;
8187 memset(&filter_replace, 0,
8188 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8189 memset(&filter_replace_buf, 0,
8190 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8191 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8192 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8193 filter_replace.new_filter_type =
8194 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8195 /* Prepare the buffer, 2 entries */
8196 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8197 filter_replace_buf.data[0] |=
8198 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8199 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8200 filter_replace_buf.data[4] |=
8201 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8202 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8203 &filter_replace_buf);
8206 if (filter_replace.old_filter_type !=
8207 filter_replace.new_filter_type)
8208 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8209 " original: 0x%x, new: 0x%x",
8211 filter_replace.old_filter_type,
8212 filter_replace.new_filter_type);
8215 memset(&filter_replace, 0,
8216 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8217 memset(&filter_replace_buf, 0,
8218 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8219 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8220 filter_replace.old_filter_type =
8221 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8222 filter_replace.new_filter_type =
8223 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8224 /* Prepare the buffer, 2 entries */
8225 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8226 filter_replace_buf.data[0] |=
8227 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8228 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8229 filter_replace_buf.data[4] |=
8230 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8232 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8233 &filter_replace_buf);
8234 if (!status && (filter_replace.old_filter_type !=
8235 filter_replace.new_filter_type))
8236 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8237 " original: 0x%x, new: 0x%x",
8239 filter_replace.old_filter_type,
8240 filter_replace.new_filter_type);
8246 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8247 struct i40e_tunnel_filter_conf *tunnel_filter,
8251 uint32_t ipv4_addr, ipv4_addr_le;
8252 uint8_t i, tun_type = 0;
8253 /* internal variable to convert ipv6 byte order */
8254 uint32_t convert_ipv6[4];
8256 struct i40e_pf_vf *vf = NULL;
8257 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8258 struct i40e_vsi *vsi;
8259 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8260 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8261 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8262 struct i40e_tunnel_filter *tunnel, *node;
8263 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8265 bool big_buffer = 0;
8267 cld_filter = rte_zmalloc("tunnel_filter",
8268 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8271 if (cld_filter == NULL) {
8272 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8275 pfilter = cld_filter;
8277 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8278 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8279 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8280 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8282 pfilter->element.inner_vlan =
8283 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8284 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8285 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8286 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8287 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8288 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8290 sizeof(pfilter->element.ipaddr.v4.data));
8292 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8293 for (i = 0; i < 4; i++) {
8295 rte_cpu_to_le_32(rte_be_to_cpu_32(
8296 tunnel_filter->ip_addr.ipv6_addr[i]));
8298 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8300 sizeof(pfilter->element.ipaddr.v6.data));
8303 /* check tunneled type */
8304 switch (tunnel_filter->tunnel_type) {
8305 case I40E_TUNNEL_TYPE_VXLAN:
8306 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8308 case I40E_TUNNEL_TYPE_NVGRE:
8309 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8311 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8312 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8314 case I40E_TUNNEL_TYPE_MPLSoUDP:
8315 if (!pf->mpls_replace_flag) {
8316 i40e_replace_mpls_l1_filter(pf);
8317 i40e_replace_mpls_cloud_filter(pf);
8318 pf->mpls_replace_flag = 1;
8320 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8321 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8323 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8324 (teid_le & 0xF) << 12;
8325 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8328 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8330 case I40E_TUNNEL_TYPE_MPLSoGRE:
8331 if (!pf->mpls_replace_flag) {
8332 i40e_replace_mpls_l1_filter(pf);
8333 i40e_replace_mpls_cloud_filter(pf);
8334 pf->mpls_replace_flag = 1;
8336 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8337 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8339 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8340 (teid_le & 0xF) << 12;
8341 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8344 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8346 case I40E_TUNNEL_TYPE_GTPC:
8347 if (!pf->gtp_replace_flag) {
8348 i40e_replace_gtp_l1_filter(pf);
8349 i40e_replace_gtp_cloud_filter(pf);
8350 pf->gtp_replace_flag = 1;
8352 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8353 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8354 (teid_le >> 16) & 0xFFFF;
8355 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8357 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8361 case I40E_TUNNEL_TYPE_GTPU:
8362 if (!pf->gtp_replace_flag) {
8363 i40e_replace_gtp_l1_filter(pf);
8364 i40e_replace_gtp_cloud_filter(pf);
8365 pf->gtp_replace_flag = 1;
8367 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8368 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8369 (teid_le >> 16) & 0xFFFF;
8370 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8372 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8376 case I40E_TUNNEL_TYPE_QINQ:
8377 if (!pf->qinq_replace_flag) {
8378 ret = i40e_cloud_filter_qinq_create(pf);
8381 "QinQ tunnel filter already created.");
8382 pf->qinq_replace_flag = 1;
8384 /* Add in the General fields the values of
8385 * the Outer and Inner VLAN
8386 * Big Buffer should be set, see changes in
8387 * i40e_aq_add_cloud_filters
8389 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8390 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8394 /* Other tunnel types is not supported. */
8395 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8396 rte_free(cld_filter);
8400 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8401 pfilter->element.flags =
8402 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8403 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8404 pfilter->element.flags =
8405 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8406 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8407 pfilter->element.flags =
8408 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8409 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8410 pfilter->element.flags =
8411 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8412 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8413 pfilter->element.flags |=
8414 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8416 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8417 &pfilter->element.flags);
8419 rte_free(cld_filter);
8424 pfilter->element.flags |= rte_cpu_to_le_16(
8425 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8426 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8427 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8428 pfilter->element.queue_number =
8429 rte_cpu_to_le_16(tunnel_filter->queue_id);
8431 if (!tunnel_filter->is_to_vf)
8434 if (tunnel_filter->vf_id >= pf->vf_num) {
8435 PMD_DRV_LOG(ERR, "Invalid argument.");
8436 rte_free(cld_filter);
8439 vf = &pf->vfs[tunnel_filter->vf_id];
8443 /* Check if there is the filter in SW list */
8444 memset(&check_filter, 0, sizeof(check_filter));
8445 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8446 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8447 check_filter.vf_id = tunnel_filter->vf_id;
8448 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8450 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8451 rte_free(cld_filter);
8455 if (!add && !node) {
8456 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8457 rte_free(cld_filter);
8463 ret = i40e_aq_add_cloud_filters_bb(hw,
8464 vsi->seid, cld_filter, 1);
8466 ret = i40e_aq_add_cloud_filters(hw,
8467 vsi->seid, &cld_filter->element, 1);
8469 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8470 rte_free(cld_filter);
8473 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8474 if (tunnel == NULL) {
8475 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8476 rte_free(cld_filter);
8480 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8481 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8486 ret = i40e_aq_rem_cloud_filters_bb(
8487 hw, vsi->seid, cld_filter, 1);
8489 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8490 &cld_filter->element, 1);
8492 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8493 rte_free(cld_filter);
8496 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8499 rte_free(cld_filter);
8504 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8508 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8509 if (pf->vxlan_ports[i] == port)
8517 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8520 uint8_t filter_idx = 0;
8521 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8523 idx = i40e_get_vxlan_port_idx(pf, port);
8525 /* Check if port already exists */
8527 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8531 /* Now check if there is space to add the new port */
8532 idx = i40e_get_vxlan_port_idx(pf, 0);
8535 "Maximum number of UDP ports reached, not adding port %d",
8540 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8543 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8547 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8550 /* New port: add it and mark its index in the bitmap */
8551 pf->vxlan_ports[idx] = port;
8552 pf->vxlan_bitmap |= (1 << idx);
8554 if (!(pf->flags & I40E_FLAG_VXLAN))
8555 pf->flags |= I40E_FLAG_VXLAN;
8561 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8564 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8566 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8567 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8571 idx = i40e_get_vxlan_port_idx(pf, port);
8574 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8578 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8579 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8583 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8586 pf->vxlan_ports[idx] = 0;
8587 pf->vxlan_bitmap &= ~(1 << idx);
8589 if (!pf->vxlan_bitmap)
8590 pf->flags &= ~I40E_FLAG_VXLAN;
8595 /* Add UDP tunneling port */
8597 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8598 struct rte_eth_udp_tunnel *udp_tunnel)
8601 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8603 if (udp_tunnel == NULL)
8606 switch (udp_tunnel->prot_type) {
8607 case RTE_TUNNEL_TYPE_VXLAN:
8608 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8609 I40E_AQC_TUNNEL_TYPE_VXLAN);
8611 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8612 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8613 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8615 case RTE_TUNNEL_TYPE_GENEVE:
8616 case RTE_TUNNEL_TYPE_TEREDO:
8617 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8622 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8630 /* Remove UDP tunneling port */
8632 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8633 struct rte_eth_udp_tunnel *udp_tunnel)
8636 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8638 if (udp_tunnel == NULL)
8641 switch (udp_tunnel->prot_type) {
8642 case RTE_TUNNEL_TYPE_VXLAN:
8643 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8644 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8646 case RTE_TUNNEL_TYPE_GENEVE:
8647 case RTE_TUNNEL_TYPE_TEREDO:
8648 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8652 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8660 /* Calculate the maximum number of contiguous PF queues that are configured */
8662 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8664 struct rte_eth_dev_data *data = pf->dev_data;
8666 struct i40e_rx_queue *rxq;
8669 for (i = 0; i < pf->lan_nb_qps; i++) {
8670 rxq = data->rx_queues[i];
8671 if (rxq && rxq->q_set)
8682 i40e_pf_config_rss(struct i40e_pf *pf)
8684 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8685 struct rte_eth_rss_conf rss_conf;
8686 uint32_t i, lut = 0;
8690 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8691 * It's necessary to calculate the actual PF queues that are configured.
8693 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8694 num = i40e_pf_calc_configured_queues_num(pf);
8696 num = pf->dev_data->nb_rx_queues;
8698 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8699 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8704 "No PF queues are configured to enable RSS for port %u",
8705 pf->dev_data->port_id);
8709 if (pf->adapter->rss_reta_updated == 0) {
8710 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8713 lut = (lut << 8) | (j & ((0x1 <<
8714 hw->func_caps.rss_table_entry_width) - 1));
8716 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8721 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8722 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8723 i40e_pf_disable_rss(pf);
8726 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8727 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8728 /* Random default keys */
8729 static uint32_t rss_key_default[] = {0x6b793944,
8730 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8731 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8732 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8734 rss_conf.rss_key = (uint8_t *)rss_key_default;
8735 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8739 return i40e_hw_rss_hash_set(pf, &rss_conf);
8743 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8744 struct rte_eth_tunnel_filter_conf *filter)
8746 if (pf == NULL || filter == NULL) {
8747 PMD_DRV_LOG(ERR, "Invalid parameter");
8751 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8752 PMD_DRV_LOG(ERR, "Invalid queue ID");
8756 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8757 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8761 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8762 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8763 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8767 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8768 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8769 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8776 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8777 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8779 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8781 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8785 if (pf->support_multi_driver) {
8786 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8790 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8791 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8794 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8795 } else if (len == 4) {
8796 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8798 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8803 ret = i40e_aq_debug_write_global_register(hw,
8804 I40E_GL_PRS_FVBM(2),
8808 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8809 "with value 0x%08x",
8810 I40E_GL_PRS_FVBM(2), reg);
8814 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8815 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8821 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8828 switch (cfg->cfg_type) {
8829 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8830 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8833 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8841 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8842 enum rte_filter_op filter_op,
8845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8846 int ret = I40E_ERR_PARAM;
8848 switch (filter_op) {
8849 case RTE_ETH_FILTER_SET:
8850 ret = i40e_dev_global_config_set(hw,
8851 (struct rte_eth_global_cfg *)arg);
8854 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8862 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8863 enum rte_filter_op filter_op,
8866 struct rte_eth_tunnel_filter_conf *filter;
8867 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8868 int ret = I40E_SUCCESS;
8870 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8872 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8873 return I40E_ERR_PARAM;
8875 switch (filter_op) {
8876 case RTE_ETH_FILTER_NOP:
8877 if (!(pf->flags & I40E_FLAG_VXLAN))
8878 ret = I40E_NOT_SUPPORTED;
8880 case RTE_ETH_FILTER_ADD:
8881 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8883 case RTE_ETH_FILTER_DELETE:
8884 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8887 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8888 ret = I40E_ERR_PARAM;
8896 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8899 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8902 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8903 ret = i40e_pf_config_rss(pf);
8905 i40e_pf_disable_rss(pf);
8910 /* Get the symmetric hash enable configurations per port */
8912 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8914 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8916 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8919 /* Set the symmetric hash enable configurations per port */
8921 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8923 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8926 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8928 "Symmetric hash has already been enabled");
8931 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8933 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8935 "Symmetric hash has already been disabled");
8938 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8940 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8941 I40E_WRITE_FLUSH(hw);
8945 * Get global configurations of hash function type and symmetric hash enable
8946 * per flow type (pctype). Note that global configuration means it affects all
8947 * the ports on the same NIC.
8950 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8951 struct rte_eth_hash_global_conf *g_cfg)
8953 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8957 memset(g_cfg, 0, sizeof(*g_cfg));
8958 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8959 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8960 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8962 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8963 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8964 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8967 * As i40e supports less than 64 flow types, only first 64 bits need to
8970 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8971 g_cfg->valid_bit_mask[i] = 0ULL;
8972 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8975 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8977 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8978 if (!adapter->pctypes_tbl[i])
8980 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8981 j < I40E_FILTER_PCTYPE_MAX; j++) {
8982 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8983 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8984 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8985 g_cfg->sym_hash_enable_mask[0] |=
8996 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8997 const struct rte_eth_hash_global_conf *g_cfg)
9000 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9002 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9003 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9004 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9005 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9011 * As i40e supports less than 64 flow types, only first 64 bits need to
9014 mask0 = g_cfg->valid_bit_mask[0];
9015 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9017 /* Check if any unsupported flow type configured */
9018 if ((mask0 | i40e_mask) ^ i40e_mask)
9021 if (g_cfg->valid_bit_mask[i])
9029 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9035 * Set global configurations of hash function type and symmetric hash enable
9036 * per flow type (pctype). Note any modifying global configuration will affect
9037 * all the ports on the same NIC.
9040 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9041 struct rte_eth_hash_global_conf *g_cfg)
9043 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9044 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9048 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9050 if (pf->support_multi_driver) {
9051 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9055 /* Check the input parameters */
9056 ret = i40e_hash_global_config_check(adapter, g_cfg);
9061 * As i40e supports less than 64 flow types, only first 64 bits need to
9064 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9065 if (mask0 & (1UL << i)) {
9066 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9067 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9069 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9070 j < I40E_FILTER_PCTYPE_MAX; j++) {
9071 if (adapter->pctypes_tbl[i] & (1ULL << j))
9072 i40e_write_global_rx_ctl(hw,
9079 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9080 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9082 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9084 "Hash function already set to Toeplitz");
9087 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9088 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9090 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9092 "Hash function already set to Simple XOR");
9095 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9097 /* Use the default, and keep it as it is */
9100 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9103 I40E_WRITE_FLUSH(hw);
9109 * Valid input sets for hash and flow director filters per PCTYPE
9112 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9113 enum rte_filter_type filter)
9117 static const uint64_t valid_hash_inset_table[] = {
9118 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9119 I40E_INSET_DMAC | I40E_INSET_SMAC |
9120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9121 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9122 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9123 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9124 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9125 I40E_INSET_FLEX_PAYLOAD,
9126 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9127 I40E_INSET_DMAC | I40E_INSET_SMAC |
9128 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9130 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9131 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9132 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9133 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9134 I40E_INSET_FLEX_PAYLOAD,
9135 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9136 I40E_INSET_DMAC | I40E_INSET_SMAC |
9137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9138 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9139 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9140 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9141 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9142 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9143 I40E_INSET_FLEX_PAYLOAD,
9144 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9145 I40E_INSET_DMAC | I40E_INSET_SMAC |
9146 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9148 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9149 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9150 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9151 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9152 I40E_INSET_FLEX_PAYLOAD,
9153 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9154 I40E_INSET_DMAC | I40E_INSET_SMAC |
9155 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9156 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9157 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9158 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9159 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9160 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9161 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9162 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9163 I40E_INSET_DMAC | I40E_INSET_SMAC |
9164 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9165 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9166 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9167 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9168 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9169 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9170 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9171 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9172 I40E_INSET_DMAC | I40E_INSET_SMAC |
9173 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9174 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9175 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9176 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9177 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9178 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9179 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9180 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9181 I40E_INSET_DMAC | I40E_INSET_SMAC |
9182 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9183 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9184 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9185 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9186 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9187 I40E_INSET_FLEX_PAYLOAD,
9188 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9189 I40E_INSET_DMAC | I40E_INSET_SMAC |
9190 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9191 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9192 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9193 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9194 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9195 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9196 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9197 I40E_INSET_DMAC | I40E_INSET_SMAC |
9198 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9199 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9200 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9201 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9202 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9203 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9204 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9205 I40E_INSET_DMAC | I40E_INSET_SMAC |
9206 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9207 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9208 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9209 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9210 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9211 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9212 I40E_INSET_FLEX_PAYLOAD,
9213 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9214 I40E_INSET_DMAC | I40E_INSET_SMAC |
9215 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9216 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9217 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9218 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9219 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9220 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9221 I40E_INSET_FLEX_PAYLOAD,
9222 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9223 I40E_INSET_DMAC | I40E_INSET_SMAC |
9224 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9225 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9226 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9227 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9228 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9229 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9230 I40E_INSET_FLEX_PAYLOAD,
9231 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9232 I40E_INSET_DMAC | I40E_INSET_SMAC |
9233 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9234 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9235 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9236 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9237 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9238 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9239 I40E_INSET_FLEX_PAYLOAD,
9240 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9241 I40E_INSET_DMAC | I40E_INSET_SMAC |
9242 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9243 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9244 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9245 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9246 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9247 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9248 I40E_INSET_FLEX_PAYLOAD,
9249 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9250 I40E_INSET_DMAC | I40E_INSET_SMAC |
9251 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9252 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9253 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9254 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9255 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9256 I40E_INSET_FLEX_PAYLOAD,
9257 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9258 I40E_INSET_DMAC | I40E_INSET_SMAC |
9259 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9260 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9261 I40E_INSET_FLEX_PAYLOAD,
9265 * Flow director supports only fields defined in
9266 * union rte_eth_fdir_flow.
9268 static const uint64_t valid_fdir_inset_table[] = {
9269 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9270 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9271 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9272 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9273 I40E_INSET_IPV4_TTL,
9274 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9275 I40E_INSET_DMAC | I40E_INSET_SMAC |
9276 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9277 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9278 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9279 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9280 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9281 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9282 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9283 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9284 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9285 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9286 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9287 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9288 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9289 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9290 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9291 I40E_INSET_DMAC | I40E_INSET_SMAC |
9292 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9293 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9294 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9297 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9298 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9299 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9301 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9302 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9303 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9304 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9305 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9307 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9308 I40E_INSET_DMAC | I40E_INSET_SMAC |
9309 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9310 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9311 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9312 I40E_INSET_IPV4_TTL,
9313 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9314 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9315 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9316 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9317 I40E_INSET_IPV6_HOP_LIMIT,
9318 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9319 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9320 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9321 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9322 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9323 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9324 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9325 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9326 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9327 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9328 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9329 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9330 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9331 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9332 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9333 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9334 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9335 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9336 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9337 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9338 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9339 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9340 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9341 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9342 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9343 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9344 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9345 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9346 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9347 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9349 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9350 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9351 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9352 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9353 I40E_INSET_IPV6_HOP_LIMIT,
9354 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9355 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9356 I40E_INSET_LAST_ETHER_TYPE,
9359 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9361 if (filter == RTE_ETH_FILTER_HASH)
9362 valid = valid_hash_inset_table[pctype];
9364 valid = valid_fdir_inset_table[pctype];
9370 * Validate if the input set is allowed for a specific PCTYPE
9373 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9374 enum rte_filter_type filter, uint64_t inset)
9378 valid = i40e_get_valid_input_set(pctype, filter);
9379 if (inset & (~valid))
9385 /* default input set fields combination per pctype */
9387 i40e_get_default_input_set(uint16_t pctype)
9389 static const uint64_t default_inset_table[] = {
9390 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9391 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9392 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9393 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9394 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9395 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9396 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9397 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9398 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9399 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9400 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9401 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9402 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9403 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9404 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9405 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9406 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9407 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9408 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9409 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9411 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9412 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9413 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9414 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9415 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9416 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9417 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9418 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9419 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9420 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9421 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9422 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9423 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9424 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9425 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9426 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9427 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9428 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9429 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9430 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9431 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9432 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9434 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9435 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9436 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9437 I40E_INSET_LAST_ETHER_TYPE,
9440 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9443 return default_inset_table[pctype];
9447 * Parse the input set from index to logical bit masks
9450 i40e_parse_input_set(uint64_t *inset,
9451 enum i40e_filter_pctype pctype,
9452 enum rte_eth_input_set_field *field,
9458 static const struct {
9459 enum rte_eth_input_set_field field;
9461 } inset_convert_table[] = {
9462 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9463 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9464 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9465 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9466 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9467 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9468 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9469 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9470 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9471 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9472 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9473 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9474 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9475 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9476 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9477 I40E_INSET_IPV6_NEXT_HDR},
9478 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9479 I40E_INSET_IPV6_HOP_LIMIT},
9480 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9481 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9482 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9483 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9484 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9485 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9486 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9487 I40E_INSET_SCTP_VT},
9488 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9489 I40E_INSET_TUNNEL_DMAC},
9490 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9491 I40E_INSET_VLAN_TUNNEL},
9492 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9493 I40E_INSET_TUNNEL_ID},
9494 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9495 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9496 I40E_INSET_FLEX_PAYLOAD_W1},
9497 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9498 I40E_INSET_FLEX_PAYLOAD_W2},
9499 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9500 I40E_INSET_FLEX_PAYLOAD_W3},
9501 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9502 I40E_INSET_FLEX_PAYLOAD_W4},
9503 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9504 I40E_INSET_FLEX_PAYLOAD_W5},
9505 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9506 I40E_INSET_FLEX_PAYLOAD_W6},
9507 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9508 I40E_INSET_FLEX_PAYLOAD_W7},
9509 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9510 I40E_INSET_FLEX_PAYLOAD_W8},
9513 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9516 /* Only one item allowed for default or all */
9518 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9519 *inset = i40e_get_default_input_set(pctype);
9521 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9522 *inset = I40E_INSET_NONE;
9527 for (i = 0, *inset = 0; i < size; i++) {
9528 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9529 if (field[i] == inset_convert_table[j].field) {
9530 *inset |= inset_convert_table[j].inset;
9535 /* It contains unsupported input set, return immediately */
9536 if (j == RTE_DIM(inset_convert_table))
9544 * Translate the input set from bit masks to register aware bit masks
9548 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9558 static const struct inset_map inset_map_common[] = {
9559 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9560 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9561 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9562 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9563 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9564 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9565 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9566 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9567 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9568 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9569 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9570 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9571 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9572 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9573 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9574 {I40E_INSET_TUNNEL_DMAC,
9575 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9576 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9577 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9578 {I40E_INSET_TUNNEL_SRC_PORT,
9579 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9580 {I40E_INSET_TUNNEL_DST_PORT,
9581 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9582 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9583 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9584 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9585 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9586 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9587 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9588 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9589 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9590 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9593 /* some different registers map in x722*/
9594 static const struct inset_map inset_map_diff_x722[] = {
9595 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9596 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9597 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9598 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9601 static const struct inset_map inset_map_diff_not_x722[] = {
9602 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9603 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9604 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9605 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9611 /* Translate input set to register aware inset */
9612 if (type == I40E_MAC_X722) {
9613 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9614 if (input & inset_map_diff_x722[i].inset)
9615 val |= inset_map_diff_x722[i].inset_reg;
9618 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9619 if (input & inset_map_diff_not_x722[i].inset)
9620 val |= inset_map_diff_not_x722[i].inset_reg;
9624 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9625 if (input & inset_map_common[i].inset)
9626 val |= inset_map_common[i].inset_reg;
9633 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9636 uint64_t inset_need_mask = inset;
9638 static const struct {
9641 } inset_mask_map[] = {
9642 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9643 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9644 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9645 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9646 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9647 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9648 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9649 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9652 if (!inset || !mask || !nb_elem)
9655 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9656 /* Clear the inset bit, if no MASK is required,
9657 * for example proto + ttl
9659 if ((inset & inset_mask_map[i].inset) ==
9660 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9661 inset_need_mask &= ~inset_mask_map[i].inset;
9662 if (!inset_need_mask)
9665 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9666 if ((inset_need_mask & inset_mask_map[i].inset) ==
9667 inset_mask_map[i].inset) {
9668 if (idx >= nb_elem) {
9669 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9672 mask[idx] = inset_mask_map[i].mask;
9681 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9683 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9685 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9687 i40e_write_rx_ctl(hw, addr, val);
9688 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9689 (uint32_t)i40e_read_rx_ctl(hw, addr));
9693 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9695 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9696 struct rte_eth_dev *dev;
9698 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9700 i40e_write_rx_ctl(hw, addr, val);
9701 PMD_DRV_LOG(WARNING,
9702 "i40e device %s changed global register [0x%08x]."
9703 " original: 0x%08x, new: 0x%08x",
9704 dev->device->name, addr, reg,
9705 (uint32_t)i40e_read_rx_ctl(hw, addr));
9710 i40e_filter_input_set_init(struct i40e_pf *pf)
9712 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9713 enum i40e_filter_pctype pctype;
9714 uint64_t input_set, inset_reg;
9715 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9719 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9720 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9721 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9723 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9726 input_set = i40e_get_default_input_set(pctype);
9728 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9729 I40E_INSET_MASK_NUM_REG);
9732 if (pf->support_multi_driver && num > 0) {
9733 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9736 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9739 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9740 (uint32_t)(inset_reg & UINT32_MAX));
9741 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9742 (uint32_t)((inset_reg >>
9743 I40E_32_BIT_WIDTH) & UINT32_MAX));
9744 if (!pf->support_multi_driver) {
9745 i40e_check_write_global_reg(hw,
9746 I40E_GLQF_HASH_INSET(0, pctype),
9747 (uint32_t)(inset_reg & UINT32_MAX));
9748 i40e_check_write_global_reg(hw,
9749 I40E_GLQF_HASH_INSET(1, pctype),
9750 (uint32_t)((inset_reg >>
9751 I40E_32_BIT_WIDTH) & UINT32_MAX));
9753 for (i = 0; i < num; i++) {
9754 i40e_check_write_global_reg(hw,
9755 I40E_GLQF_FD_MSK(i, pctype),
9757 i40e_check_write_global_reg(hw,
9758 I40E_GLQF_HASH_MSK(i, pctype),
9761 /*clear unused mask registers of the pctype */
9762 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9763 i40e_check_write_global_reg(hw,
9764 I40E_GLQF_FD_MSK(i, pctype),
9766 i40e_check_write_global_reg(hw,
9767 I40E_GLQF_HASH_MSK(i, pctype),
9771 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9773 I40E_WRITE_FLUSH(hw);
9775 /* store the default input set */
9776 if (!pf->support_multi_driver)
9777 pf->hash_input_set[pctype] = input_set;
9778 pf->fdir.input_set[pctype] = input_set;
9783 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9784 struct rte_eth_input_set_conf *conf)
9786 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9787 enum i40e_filter_pctype pctype;
9788 uint64_t input_set, inset_reg = 0;
9789 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9793 PMD_DRV_LOG(ERR, "Invalid pointer");
9796 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9797 conf->op != RTE_ETH_INPUT_SET_ADD) {
9798 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9802 if (pf->support_multi_driver) {
9803 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9807 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9808 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9809 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9813 if (hw->mac.type == I40E_MAC_X722) {
9814 /* get translated pctype value in fd pctype register */
9815 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9816 I40E_GLQF_FD_PCTYPES((int)pctype));
9819 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9822 PMD_DRV_LOG(ERR, "Failed to parse input set");
9826 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9827 /* get inset value in register */
9828 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9829 inset_reg <<= I40E_32_BIT_WIDTH;
9830 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9831 input_set |= pf->hash_input_set[pctype];
9833 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9834 I40E_INSET_MASK_NUM_REG);
9838 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9840 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9841 (uint32_t)(inset_reg & UINT32_MAX));
9842 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9843 (uint32_t)((inset_reg >>
9844 I40E_32_BIT_WIDTH) & UINT32_MAX));
9846 for (i = 0; i < num; i++)
9847 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9849 /*clear unused mask registers of the pctype */
9850 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9851 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9853 I40E_WRITE_FLUSH(hw);
9855 pf->hash_input_set[pctype] = input_set;
9860 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9861 struct rte_eth_input_set_conf *conf)
9863 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9864 enum i40e_filter_pctype pctype;
9865 uint64_t input_set, inset_reg = 0;
9866 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9870 PMD_DRV_LOG(ERR, "Invalid pointer");
9873 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9874 conf->op != RTE_ETH_INPUT_SET_ADD) {
9875 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9879 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9881 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9882 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9886 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9889 PMD_DRV_LOG(ERR, "Failed to parse input set");
9893 /* get inset value in register */
9894 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9895 inset_reg <<= I40E_32_BIT_WIDTH;
9896 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9898 /* Can not change the inset reg for flex payload for fdir,
9899 * it is done by writing I40E_PRTQF_FD_FLXINSET
9900 * in i40e_set_flex_mask_on_pctype.
9902 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9903 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9905 input_set |= pf->fdir.input_set[pctype];
9906 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9907 I40E_INSET_MASK_NUM_REG);
9910 if (pf->support_multi_driver && num > 0) {
9911 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9915 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9917 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9918 (uint32_t)(inset_reg & UINT32_MAX));
9919 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9920 (uint32_t)((inset_reg >>
9921 I40E_32_BIT_WIDTH) & UINT32_MAX));
9923 if (!pf->support_multi_driver) {
9924 for (i = 0; i < num; i++)
9925 i40e_check_write_global_reg(hw,
9926 I40E_GLQF_FD_MSK(i, pctype),
9928 /*clear unused mask registers of the pctype */
9929 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9930 i40e_check_write_global_reg(hw,
9931 I40E_GLQF_FD_MSK(i, pctype),
9934 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9936 I40E_WRITE_FLUSH(hw);
9938 pf->fdir.input_set[pctype] = input_set;
9943 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9948 PMD_DRV_LOG(ERR, "Invalid pointer");
9952 switch (info->info_type) {
9953 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9954 i40e_get_symmetric_hash_enable_per_port(hw,
9955 &(info->info.enable));
9957 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9958 ret = i40e_get_hash_filter_global_config(hw,
9959 &(info->info.global_conf));
9962 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9972 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9977 PMD_DRV_LOG(ERR, "Invalid pointer");
9981 switch (info->info_type) {
9982 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9983 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9985 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9986 ret = i40e_set_hash_filter_global_config(hw,
9987 &(info->info.global_conf));
9989 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9990 ret = i40e_hash_filter_inset_select(hw,
9991 &(info->info.input_set_conf));
9995 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10004 /* Operations for hash function */
10006 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10007 enum rte_filter_op filter_op,
10010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10013 switch (filter_op) {
10014 case RTE_ETH_FILTER_NOP:
10016 case RTE_ETH_FILTER_GET:
10017 ret = i40e_hash_filter_get(hw,
10018 (struct rte_eth_hash_filter_info *)arg);
10020 case RTE_ETH_FILTER_SET:
10021 ret = i40e_hash_filter_set(hw,
10022 (struct rte_eth_hash_filter_info *)arg);
10025 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10034 /* Convert ethertype filter structure */
10036 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10037 struct i40e_ethertype_filter *filter)
10039 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10040 RTE_ETHER_ADDR_LEN);
10041 filter->input.ether_type = input->ether_type;
10042 filter->flags = input->flags;
10043 filter->queue = input->queue;
10048 /* Check if there exists the ehtertype filter */
10049 struct i40e_ethertype_filter *
10050 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10051 const struct i40e_ethertype_filter_input *input)
10055 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10059 return ethertype_rule->hash_map[ret];
10062 /* Add ethertype filter in SW list */
10064 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10065 struct i40e_ethertype_filter *filter)
10067 struct i40e_ethertype_rule *rule = &pf->ethertype;
10070 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10073 "Failed to insert ethertype filter"
10074 " to hash table %d!",
10078 rule->hash_map[ret] = filter;
10080 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10085 /* Delete ethertype filter in SW list */
10087 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10088 struct i40e_ethertype_filter_input *input)
10090 struct i40e_ethertype_rule *rule = &pf->ethertype;
10091 struct i40e_ethertype_filter *filter;
10094 ret = rte_hash_del_key(rule->hash_table, input);
10097 "Failed to delete ethertype filter"
10098 " to hash table %d!",
10102 filter = rule->hash_map[ret];
10103 rule->hash_map[ret] = NULL;
10105 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10112 * Configure ethertype filter, which can director packet by filtering
10113 * with mac address and ether_type or only ether_type
10116 i40e_ethertype_filter_set(struct i40e_pf *pf,
10117 struct rte_eth_ethertype_filter *filter,
10120 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10121 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10122 struct i40e_ethertype_filter *ethertype_filter, *node;
10123 struct i40e_ethertype_filter check_filter;
10124 struct i40e_control_filter_stats stats;
10125 uint16_t flags = 0;
10128 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10129 PMD_DRV_LOG(ERR, "Invalid queue ID");
10132 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10133 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10135 "unsupported ether_type(0x%04x) in control packet filter.",
10136 filter->ether_type);
10139 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10140 PMD_DRV_LOG(WARNING,
10141 "filter vlan ether_type in first tag is not supported.");
10143 /* Check if there is the filter in SW list */
10144 memset(&check_filter, 0, sizeof(check_filter));
10145 i40e_ethertype_filter_convert(filter, &check_filter);
10146 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10147 &check_filter.input);
10149 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10153 if (!add && !node) {
10154 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10158 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10159 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10160 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10161 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10162 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10164 memset(&stats, 0, sizeof(stats));
10165 ret = i40e_aq_add_rem_control_packet_filter(hw,
10166 filter->mac_addr.addr_bytes,
10167 filter->ether_type, flags,
10168 pf->main_vsi->seid,
10169 filter->queue, add, &stats, NULL);
10172 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10173 ret, stats.mac_etype_used, stats.etype_used,
10174 stats.mac_etype_free, stats.etype_free);
10178 /* Add or delete a filter in SW list */
10180 ethertype_filter = rte_zmalloc("ethertype_filter",
10181 sizeof(*ethertype_filter), 0);
10182 if (ethertype_filter == NULL) {
10183 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10187 rte_memcpy(ethertype_filter, &check_filter,
10188 sizeof(check_filter));
10189 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10191 rte_free(ethertype_filter);
10193 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10200 * Handle operations for ethertype filter.
10203 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10204 enum rte_filter_op filter_op,
10207 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10210 if (filter_op == RTE_ETH_FILTER_NOP)
10214 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10219 switch (filter_op) {
10220 case RTE_ETH_FILTER_ADD:
10221 ret = i40e_ethertype_filter_set(pf,
10222 (struct rte_eth_ethertype_filter *)arg,
10225 case RTE_ETH_FILTER_DELETE:
10226 ret = i40e_ethertype_filter_set(pf,
10227 (struct rte_eth_ethertype_filter *)arg,
10231 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10239 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10240 enum rte_filter_type filter_type,
10241 enum rte_filter_op filter_op,
10249 switch (filter_type) {
10250 case RTE_ETH_FILTER_NONE:
10251 /* For global configuration */
10252 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10254 case RTE_ETH_FILTER_HASH:
10255 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10257 case RTE_ETH_FILTER_MACVLAN:
10258 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10260 case RTE_ETH_FILTER_ETHERTYPE:
10261 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10263 case RTE_ETH_FILTER_TUNNEL:
10264 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10266 case RTE_ETH_FILTER_FDIR:
10267 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10269 case RTE_ETH_FILTER_GENERIC:
10270 if (filter_op != RTE_ETH_FILTER_GET)
10272 *(const void **)arg = &i40e_flow_ops;
10275 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10285 * Check and enable Extended Tag.
10286 * Enabling Extended Tag is important for 40G performance.
10289 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10291 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10295 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10298 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10302 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10303 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10308 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10311 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10315 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10316 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10319 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10320 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10323 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10330 * As some registers wouldn't be reset unless a global hardware reset,
10331 * hardware initialization is needed to put those registers into an
10332 * expected initial state.
10335 i40e_hw_init(struct rte_eth_dev *dev)
10337 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10339 i40e_enable_extended_tag(dev);
10341 /* clear the PF Queue Filter control register */
10342 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10344 /* Disable symmetric hash per port */
10345 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10349 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10350 * however this function will return only one highest pctype index,
10351 * which is not quite correct. This is known problem of i40e driver
10352 * and needs to be fixed later.
10354 enum i40e_filter_pctype
10355 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10358 uint64_t pctype_mask;
10360 if (flow_type < I40E_FLOW_TYPE_MAX) {
10361 pctype_mask = adapter->pctypes_tbl[flow_type];
10362 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10363 if (pctype_mask & (1ULL << i))
10364 return (enum i40e_filter_pctype)i;
10367 return I40E_FILTER_PCTYPE_INVALID;
10371 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10372 enum i40e_filter_pctype pctype)
10375 uint64_t pctype_mask = 1ULL << pctype;
10377 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10379 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10383 return RTE_ETH_FLOW_UNKNOWN;
10387 * On X710, performance number is far from the expectation on recent firmware
10388 * versions; on XL710, performance number is also far from the expectation on
10389 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10390 * mode is enabled and port MAC address is equal to the packet destination MAC
10391 * address. The fix for this issue may not be integrated in the following
10392 * firmware version. So the workaround in software driver is needed. It needs
10393 * to modify the initial values of 3 internal only registers for both X710 and
10394 * XL710. Note that the values for X710 or XL710 could be different, and the
10395 * workaround can be removed when it is fixed in firmware in the future.
10398 /* For both X710 and XL710 */
10399 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10400 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10401 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10403 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10404 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10407 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10408 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10411 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10413 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10414 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10417 * GL_SWR_PM_UP_THR:
10418 * The value is not impacted from the link speed, its value is set according
10419 * to the total number of ports for a better pipe-monitor configuration.
10422 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10424 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10425 .device_id = (dev), \
10426 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10428 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10429 .device_id = (dev), \
10430 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10432 static const struct {
10433 uint16_t device_id;
10435 } swr_pm_table[] = {
10436 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10437 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10438 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10439 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10440 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10442 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10443 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10444 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10445 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10446 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10447 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10448 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10452 if (value == NULL) {
10453 PMD_DRV_LOG(ERR, "value is NULL");
10457 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10458 if (hw->device_id == swr_pm_table[i].device_id) {
10459 *value = swr_pm_table[i].val;
10461 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10463 hw->device_id, *value);
10472 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10474 enum i40e_status_code status;
10475 struct i40e_aq_get_phy_abilities_resp phy_ab;
10476 int ret = -ENOTSUP;
10479 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10483 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10486 rte_delay_us(100000);
10488 status = i40e_aq_get_phy_capabilities(hw, false,
10489 true, &phy_ab, NULL);
10497 i40e_configure_registers(struct i40e_hw *hw)
10503 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10504 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10505 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10511 for (i = 0; i < RTE_DIM(reg_table); i++) {
10512 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10513 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10515 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10516 else /* For X710/XL710/XXV710 */
10517 if (hw->aq.fw_maj_ver < 6)
10519 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10522 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10525 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10526 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10528 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10529 else /* For X710/XL710/XXV710 */
10531 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10534 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10537 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10538 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10539 "GL_SWR_PM_UP_THR value fixup",
10544 reg_table[i].val = cfg_val;
10547 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10550 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10551 reg_table[i].addr);
10554 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10555 reg_table[i].addr, reg);
10556 if (reg == reg_table[i].val)
10559 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10560 reg_table[i].val, NULL);
10563 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10564 reg_table[i].val, reg_table[i].addr);
10567 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10568 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10572 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10573 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10574 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10575 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10577 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10582 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10583 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10587 /* Configure for double VLAN RX stripping */
10588 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10589 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10590 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10591 ret = i40e_aq_debug_write_register(hw,
10592 I40E_VSI_TSR(vsi->vsi_id),
10595 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10597 return I40E_ERR_CONFIG;
10601 /* Configure for double VLAN TX insertion */
10602 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10603 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10604 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10605 ret = i40e_aq_debug_write_register(hw,
10606 I40E_VSI_L2TAGSTXVALID(
10607 vsi->vsi_id), reg, NULL);
10610 "Failed to update VSI_L2TAGSTXVALID[%d]",
10612 return I40E_ERR_CONFIG;
10620 * i40e_aq_add_mirror_rule
10621 * @hw: pointer to the hardware structure
10622 * @seid: VEB seid to add mirror rule to
10623 * @dst_id: destination vsi seid
10624 * @entries: Buffer which contains the entities to be mirrored
10625 * @count: number of entities contained in the buffer
10626 * @rule_id:the rule_id of the rule to be added
10628 * Add a mirror rule for a given veb.
10631 static enum i40e_status_code
10632 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10633 uint16_t seid, uint16_t dst_id,
10634 uint16_t rule_type, uint16_t *entries,
10635 uint16_t count, uint16_t *rule_id)
10637 struct i40e_aq_desc desc;
10638 struct i40e_aqc_add_delete_mirror_rule cmd;
10639 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10640 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10643 enum i40e_status_code status;
10645 i40e_fill_default_direct_cmd_desc(&desc,
10646 i40e_aqc_opc_add_mirror_rule);
10647 memset(&cmd, 0, sizeof(cmd));
10649 buff_len = sizeof(uint16_t) * count;
10650 desc.datalen = rte_cpu_to_le_16(buff_len);
10652 desc.flags |= rte_cpu_to_le_16(
10653 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10654 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10655 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10656 cmd.num_entries = rte_cpu_to_le_16(count);
10657 cmd.seid = rte_cpu_to_le_16(seid);
10658 cmd.destination = rte_cpu_to_le_16(dst_id);
10660 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10661 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10663 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10664 hw->aq.asq_last_status, resp->rule_id,
10665 resp->mirror_rules_used, resp->mirror_rules_free);
10666 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10672 * i40e_aq_del_mirror_rule
10673 * @hw: pointer to the hardware structure
10674 * @seid: VEB seid to add mirror rule to
10675 * @entries: Buffer which contains the entities to be mirrored
10676 * @count: number of entities contained in the buffer
10677 * @rule_id:the rule_id of the rule to be delete
10679 * Delete a mirror rule for a given veb.
10682 static enum i40e_status_code
10683 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10684 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10685 uint16_t count, uint16_t rule_id)
10687 struct i40e_aq_desc desc;
10688 struct i40e_aqc_add_delete_mirror_rule cmd;
10689 uint16_t buff_len = 0;
10690 enum i40e_status_code status;
10693 i40e_fill_default_direct_cmd_desc(&desc,
10694 i40e_aqc_opc_delete_mirror_rule);
10695 memset(&cmd, 0, sizeof(cmd));
10696 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10697 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10699 cmd.num_entries = count;
10700 buff_len = sizeof(uint16_t) * count;
10701 desc.datalen = rte_cpu_to_le_16(buff_len);
10702 buff = (void *)entries;
10704 /* rule id is filled in destination field for deleting mirror rule */
10705 cmd.destination = rte_cpu_to_le_16(rule_id);
10707 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10708 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10709 cmd.seid = rte_cpu_to_le_16(seid);
10711 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10712 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10718 * i40e_mirror_rule_set
10719 * @dev: pointer to the hardware structure
10720 * @mirror_conf: mirror rule info
10721 * @sw_id: mirror rule's sw_id
10722 * @on: enable/disable
10724 * set a mirror rule.
10728 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10729 struct rte_eth_mirror_conf *mirror_conf,
10730 uint8_t sw_id, uint8_t on)
10732 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10733 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10734 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10735 struct i40e_mirror_rule *parent = NULL;
10736 uint16_t seid, dst_seid, rule_id;
10740 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10742 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10744 "mirror rule can not be configured without veb or vfs.");
10747 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10748 PMD_DRV_LOG(ERR, "mirror table is full.");
10751 if (mirror_conf->dst_pool > pf->vf_num) {
10752 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10753 mirror_conf->dst_pool);
10757 seid = pf->main_vsi->veb->seid;
10759 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10760 if (sw_id <= it->index) {
10766 if (mirr_rule && sw_id == mirr_rule->index) {
10768 PMD_DRV_LOG(ERR, "mirror rule exists.");
10771 ret = i40e_aq_del_mirror_rule(hw, seid,
10772 mirr_rule->rule_type,
10773 mirr_rule->entries,
10774 mirr_rule->num_entries, mirr_rule->id);
10777 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10778 ret, hw->aq.asq_last_status);
10781 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10782 rte_free(mirr_rule);
10783 pf->nb_mirror_rule--;
10787 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10791 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10792 sizeof(struct i40e_mirror_rule) , 0);
10794 PMD_DRV_LOG(ERR, "failed to allocate memory");
10795 return I40E_ERR_NO_MEMORY;
10797 switch (mirror_conf->rule_type) {
10798 case ETH_MIRROR_VLAN:
10799 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10800 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10801 mirr_rule->entries[j] =
10802 mirror_conf->vlan.vlan_id[i];
10807 PMD_DRV_LOG(ERR, "vlan is not specified.");
10808 rte_free(mirr_rule);
10811 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10813 case ETH_MIRROR_VIRTUAL_POOL_UP:
10814 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10815 /* check if the specified pool bit is out of range */
10816 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10817 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10818 rte_free(mirr_rule);
10821 for (i = 0, j = 0; i < pf->vf_num; i++) {
10822 if (mirror_conf->pool_mask & (1ULL << i)) {
10823 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10827 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10828 /* add pf vsi to entries */
10829 mirr_rule->entries[j] = pf->main_vsi_seid;
10833 PMD_DRV_LOG(ERR, "pool is not specified.");
10834 rte_free(mirr_rule);
10837 /* egress and ingress in aq commands means from switch but not port */
10838 mirr_rule->rule_type =
10839 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10840 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10841 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10843 case ETH_MIRROR_UPLINK_PORT:
10844 /* egress and ingress in aq commands means from switch but not port*/
10845 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10847 case ETH_MIRROR_DOWNLINK_PORT:
10848 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10851 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10852 mirror_conf->rule_type);
10853 rte_free(mirr_rule);
10857 /* If the dst_pool is equal to vf_num, consider it as PF */
10858 if (mirror_conf->dst_pool == pf->vf_num)
10859 dst_seid = pf->main_vsi_seid;
10861 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10863 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10864 mirr_rule->rule_type, mirr_rule->entries,
10868 "failed to add mirror rule: ret = %d, aq_err = %d.",
10869 ret, hw->aq.asq_last_status);
10870 rte_free(mirr_rule);
10874 mirr_rule->index = sw_id;
10875 mirr_rule->num_entries = j;
10876 mirr_rule->id = rule_id;
10877 mirr_rule->dst_vsi_seid = dst_seid;
10880 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10882 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10884 pf->nb_mirror_rule++;
10889 * i40e_mirror_rule_reset
10890 * @dev: pointer to the device
10891 * @sw_id: mirror rule's sw_id
10893 * reset a mirror rule.
10897 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10899 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10900 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10901 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10905 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10907 seid = pf->main_vsi->veb->seid;
10909 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10910 if (sw_id == it->index) {
10916 ret = i40e_aq_del_mirror_rule(hw, seid,
10917 mirr_rule->rule_type,
10918 mirr_rule->entries,
10919 mirr_rule->num_entries, mirr_rule->id);
10922 "failed to remove mirror rule: status = %d, aq_err = %d.",
10923 ret, hw->aq.asq_last_status);
10926 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10927 rte_free(mirr_rule);
10928 pf->nb_mirror_rule--;
10930 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10937 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10940 uint64_t systim_cycles;
10942 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10943 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10946 return systim_cycles;
10950 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10952 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10953 uint64_t rx_tstamp;
10955 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10956 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10963 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10965 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10966 uint64_t tx_tstamp;
10968 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10969 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10976 i40e_start_timecounters(struct rte_eth_dev *dev)
10978 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10979 struct i40e_adapter *adapter = dev->data->dev_private;
10980 struct rte_eth_link link;
10981 uint32_t tsync_inc_l;
10982 uint32_t tsync_inc_h;
10984 /* Get current link speed. */
10985 i40e_dev_link_update(dev, 1);
10986 rte_eth_linkstatus_get(dev, &link);
10988 switch (link.link_speed) {
10989 case ETH_SPEED_NUM_40G:
10990 case ETH_SPEED_NUM_25G:
10991 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10992 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10994 case ETH_SPEED_NUM_10G:
10995 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10996 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10998 case ETH_SPEED_NUM_1G:
10999 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11000 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11007 /* Set the timesync increment value. */
11008 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11009 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11011 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11012 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11013 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11015 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11016 adapter->systime_tc.cc_shift = 0;
11017 adapter->systime_tc.nsec_mask = 0;
11019 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11020 adapter->rx_tstamp_tc.cc_shift = 0;
11021 adapter->rx_tstamp_tc.nsec_mask = 0;
11023 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11024 adapter->tx_tstamp_tc.cc_shift = 0;
11025 adapter->tx_tstamp_tc.nsec_mask = 0;
11029 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11031 struct i40e_adapter *adapter = dev->data->dev_private;
11033 adapter->systime_tc.nsec += delta;
11034 adapter->rx_tstamp_tc.nsec += delta;
11035 adapter->tx_tstamp_tc.nsec += delta;
11041 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11044 struct i40e_adapter *adapter = dev->data->dev_private;
11046 ns = rte_timespec_to_ns(ts);
11048 /* Set the timecounters to a new value. */
11049 adapter->systime_tc.nsec = ns;
11050 adapter->rx_tstamp_tc.nsec = ns;
11051 adapter->tx_tstamp_tc.nsec = ns;
11057 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11059 uint64_t ns, systime_cycles;
11060 struct i40e_adapter *adapter = dev->data->dev_private;
11062 systime_cycles = i40e_read_systime_cyclecounter(dev);
11063 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11064 *ts = rte_ns_to_timespec(ns);
11070 i40e_timesync_enable(struct rte_eth_dev *dev)
11072 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11073 uint32_t tsync_ctl_l;
11074 uint32_t tsync_ctl_h;
11076 /* Stop the timesync system time. */
11077 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11078 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11079 /* Reset the timesync system time value. */
11080 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11081 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11083 i40e_start_timecounters(dev);
11085 /* Clear timesync registers. */
11086 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11087 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11088 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11089 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11090 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11091 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11093 /* Enable timestamping of PTP packets. */
11094 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11095 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11097 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11098 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11099 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11101 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11102 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11108 i40e_timesync_disable(struct rte_eth_dev *dev)
11110 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11111 uint32_t tsync_ctl_l;
11112 uint32_t tsync_ctl_h;
11114 /* Disable timestamping of transmitted PTP packets. */
11115 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11116 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11118 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11119 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11121 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11122 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11124 /* Reset the timesync increment value. */
11125 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11126 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11132 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11133 struct timespec *timestamp, uint32_t flags)
11135 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11136 struct i40e_adapter *adapter = dev->data->dev_private;
11137 uint32_t sync_status;
11138 uint32_t index = flags & 0x03;
11139 uint64_t rx_tstamp_cycles;
11142 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11143 if ((sync_status & (1 << index)) == 0)
11146 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11147 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11148 *timestamp = rte_ns_to_timespec(ns);
11154 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11155 struct timespec *timestamp)
11157 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11158 struct i40e_adapter *adapter = dev->data->dev_private;
11159 uint32_t sync_status;
11160 uint64_t tx_tstamp_cycles;
11163 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11164 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11167 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11168 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11169 *timestamp = rte_ns_to_timespec(ns);
11175 * i40e_parse_dcb_configure - parse dcb configure from user
11176 * @dev: the device being configured
11177 * @dcb_cfg: pointer of the result of parse
11178 * @*tc_map: bit map of enabled traffic classes
11180 * Returns 0 on success, negative value on failure
11183 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11184 struct i40e_dcbx_config *dcb_cfg,
11187 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11188 uint8_t i, tc_bw, bw_lf;
11190 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11192 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11193 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11194 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11198 /* assume each tc has the same bw */
11199 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11200 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11201 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11202 /* to ensure the sum of tcbw is equal to 100 */
11203 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11204 for (i = 0; i < bw_lf; i++)
11205 dcb_cfg->etscfg.tcbwtable[i]++;
11207 /* assume each tc has the same Transmission Selection Algorithm */
11208 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11209 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11211 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11212 dcb_cfg->etscfg.prioritytable[i] =
11213 dcb_rx_conf->dcb_tc[i];
11215 /* FW needs one App to configure HW */
11216 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11217 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11218 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11219 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11221 if (dcb_rx_conf->nb_tcs == 0)
11222 *tc_map = 1; /* tc0 only */
11224 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11226 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11227 dcb_cfg->pfc.willing = 0;
11228 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11229 dcb_cfg->pfc.pfcenable = *tc_map;
11235 static enum i40e_status_code
11236 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11237 struct i40e_aqc_vsi_properties_data *info,
11238 uint8_t enabled_tcmap)
11240 enum i40e_status_code ret;
11241 int i, total_tc = 0;
11242 uint16_t qpnum_per_tc, bsf, qp_idx;
11243 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11244 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11245 uint16_t used_queues;
11247 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11248 if (ret != I40E_SUCCESS)
11251 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11252 if (enabled_tcmap & (1 << i))
11257 vsi->enabled_tc = enabled_tcmap;
11259 /* different VSI has different queues assigned */
11260 if (vsi->type == I40E_VSI_MAIN)
11261 used_queues = dev_data->nb_rx_queues -
11262 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11263 else if (vsi->type == I40E_VSI_VMDQ2)
11264 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11266 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11267 return I40E_ERR_NO_AVAILABLE_VSI;
11270 qpnum_per_tc = used_queues / total_tc;
11271 /* Number of queues per enabled TC */
11272 if (qpnum_per_tc == 0) {
11273 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11274 return I40E_ERR_INVALID_QP_ID;
11276 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11277 I40E_MAX_Q_PER_TC);
11278 bsf = rte_bsf32(qpnum_per_tc);
11281 * Configure TC and queue mapping parameters, for enabled TC,
11282 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11283 * default queue will serve it.
11286 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11287 if (vsi->enabled_tc & (1 << i)) {
11288 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11289 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11290 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11291 qp_idx += qpnum_per_tc;
11293 info->tc_mapping[i] = 0;
11296 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11297 if (vsi->type == I40E_VSI_SRIOV) {
11298 info->mapping_flags |=
11299 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11300 for (i = 0; i < vsi->nb_qps; i++)
11301 info->queue_mapping[i] =
11302 rte_cpu_to_le_16(vsi->base_queue + i);
11304 info->mapping_flags |=
11305 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11306 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11308 info->valid_sections |=
11309 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11311 return I40E_SUCCESS;
11315 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11316 * @veb: VEB to be configured
11317 * @tc_map: enabled TC bitmap
11319 * Returns 0 on success, negative value on failure
11321 static enum i40e_status_code
11322 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11324 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11325 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11326 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11327 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11328 enum i40e_status_code ret = I40E_SUCCESS;
11332 /* Check if enabled_tc is same as existing or new TCs */
11333 if (veb->enabled_tc == tc_map)
11336 /* configure tc bandwidth */
11337 memset(&veb_bw, 0, sizeof(veb_bw));
11338 veb_bw.tc_valid_bits = tc_map;
11339 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11340 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11341 if (tc_map & BIT_ULL(i))
11342 veb_bw.tc_bw_share_credits[i] = 1;
11344 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11348 "AQ command Config switch_comp BW allocation per TC failed = %d",
11349 hw->aq.asq_last_status);
11353 memset(&ets_query, 0, sizeof(ets_query));
11354 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11356 if (ret != I40E_SUCCESS) {
11358 "Failed to get switch_comp ETS configuration %u",
11359 hw->aq.asq_last_status);
11362 memset(&bw_query, 0, sizeof(bw_query));
11363 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11365 if (ret != I40E_SUCCESS) {
11367 "Failed to get switch_comp bandwidth configuration %u",
11368 hw->aq.asq_last_status);
11372 /* store and print out BW info */
11373 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11374 veb->bw_info.bw_max = ets_query.tc_bw_max;
11375 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11376 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11377 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11378 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11379 I40E_16_BIT_WIDTH);
11380 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11381 veb->bw_info.bw_ets_share_credits[i] =
11382 bw_query.tc_bw_share_credits[i];
11383 veb->bw_info.bw_ets_credits[i] =
11384 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11385 /* 4 bits per TC, 4th bit is reserved */
11386 veb->bw_info.bw_ets_max[i] =
11387 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11388 RTE_LEN2MASK(3, uint8_t));
11389 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11390 veb->bw_info.bw_ets_share_credits[i]);
11391 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11392 veb->bw_info.bw_ets_credits[i]);
11393 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11394 veb->bw_info.bw_ets_max[i]);
11397 veb->enabled_tc = tc_map;
11404 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11405 * @vsi: VSI to be configured
11406 * @tc_map: enabled TC bitmap
11408 * Returns 0 on success, negative value on failure
11410 static enum i40e_status_code
11411 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11413 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11414 struct i40e_vsi_context ctxt;
11415 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11416 enum i40e_status_code ret = I40E_SUCCESS;
11419 /* Check if enabled_tc is same as existing or new TCs */
11420 if (vsi->enabled_tc == tc_map)
11423 /* configure tc bandwidth */
11424 memset(&bw_data, 0, sizeof(bw_data));
11425 bw_data.tc_valid_bits = tc_map;
11426 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11427 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11428 if (tc_map & BIT_ULL(i))
11429 bw_data.tc_bw_credits[i] = 1;
11431 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11434 "AQ command Config VSI BW allocation per TC failed = %d",
11435 hw->aq.asq_last_status);
11438 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11439 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11441 /* Update Queue Pairs Mapping for currently enabled UPs */
11442 ctxt.seid = vsi->seid;
11443 ctxt.pf_num = hw->pf_id;
11445 ctxt.uplink_seid = vsi->uplink_seid;
11446 ctxt.info = vsi->info;
11448 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11452 /* Update the VSI after updating the VSI queue-mapping information */
11453 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11455 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11456 hw->aq.asq_last_status);
11459 /* update the local VSI info with updated queue map */
11460 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11461 sizeof(vsi->info.tc_mapping));
11462 rte_memcpy(&vsi->info.queue_mapping,
11463 &ctxt.info.queue_mapping,
11464 sizeof(vsi->info.queue_mapping));
11465 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11466 vsi->info.valid_sections = 0;
11468 /* query and update current VSI BW information */
11469 ret = i40e_vsi_get_bw_config(vsi);
11472 "Failed updating vsi bw info, err %s aq_err %s",
11473 i40e_stat_str(hw, ret),
11474 i40e_aq_str(hw, hw->aq.asq_last_status));
11478 vsi->enabled_tc = tc_map;
11485 * i40e_dcb_hw_configure - program the dcb setting to hw
11486 * @pf: pf the configuration is taken on
11487 * @new_cfg: new configuration
11488 * @tc_map: enabled TC bitmap
11490 * Returns 0 on success, negative value on failure
11492 static enum i40e_status_code
11493 i40e_dcb_hw_configure(struct i40e_pf *pf,
11494 struct i40e_dcbx_config *new_cfg,
11497 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11498 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11499 struct i40e_vsi *main_vsi = pf->main_vsi;
11500 struct i40e_vsi_list *vsi_list;
11501 enum i40e_status_code ret;
11505 /* Use the FW API if FW > v4.4*/
11506 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11507 (hw->aq.fw_maj_ver >= 5))) {
11509 "FW < v4.4, can not use FW LLDP API to configure DCB");
11510 return I40E_ERR_FIRMWARE_API_VERSION;
11513 /* Check if need reconfiguration */
11514 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11515 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11516 return I40E_SUCCESS;
11519 /* Copy the new config to the current config */
11520 *old_cfg = *new_cfg;
11521 old_cfg->etsrec = old_cfg->etscfg;
11522 ret = i40e_set_dcb_config(hw);
11524 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11525 i40e_stat_str(hw, ret),
11526 i40e_aq_str(hw, hw->aq.asq_last_status));
11529 /* set receive Arbiter to RR mode and ETS scheme by default */
11530 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11531 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11532 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11533 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11534 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11535 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11536 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11537 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11538 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11539 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11540 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11541 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11542 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11544 /* get local mib to check whether it is configured correctly */
11546 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11547 /* Get Local DCB Config */
11548 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11549 &hw->local_dcbx_config);
11551 /* if Veb is created, need to update TC of it at first */
11552 if (main_vsi->veb) {
11553 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11555 PMD_INIT_LOG(WARNING,
11556 "Failed configuring TC for VEB seid=%d",
11557 main_vsi->veb->seid);
11559 /* Update each VSI */
11560 i40e_vsi_config_tc(main_vsi, tc_map);
11561 if (main_vsi->veb) {
11562 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11563 /* Beside main VSI and VMDQ VSIs, only enable default
11564 * TC for other VSIs
11566 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11567 ret = i40e_vsi_config_tc(vsi_list->vsi,
11570 ret = i40e_vsi_config_tc(vsi_list->vsi,
11571 I40E_DEFAULT_TCMAP);
11573 PMD_INIT_LOG(WARNING,
11574 "Failed configuring TC for VSI seid=%d",
11575 vsi_list->vsi->seid);
11579 return I40E_SUCCESS;
11583 * i40e_dcb_init_configure - initial dcb config
11584 * @dev: device being configured
11585 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11587 * Returns 0 on success, negative value on failure
11590 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11592 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11593 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11596 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11597 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11601 /* DCB initialization:
11602 * Update DCB configuration from the Firmware and configure
11603 * LLDP MIB change event.
11605 if (sw_dcb == TRUE) {
11606 /* Stopping lldp is necessary for DPDK, but it will cause
11607 * DCB init failed. For i40e_init_dcb(), the prerequisite
11608 * for successful initialization of DCB is that LLDP is
11609 * enabled. So it is needed to start lldp before DCB init
11610 * and stop it after initialization.
11612 ret = i40e_aq_start_lldp(hw, true, NULL);
11613 if (ret != I40E_SUCCESS)
11614 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11616 ret = i40e_init_dcb(hw, true);
11617 /* If lldp agent is stopped, the return value from
11618 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11619 * adminq status. Otherwise, it should return success.
11621 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11622 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11623 memset(&hw->local_dcbx_config, 0,
11624 sizeof(struct i40e_dcbx_config));
11625 /* set dcb default configuration */
11626 hw->local_dcbx_config.etscfg.willing = 0;
11627 hw->local_dcbx_config.etscfg.maxtcs = 0;
11628 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11629 hw->local_dcbx_config.etscfg.tsatable[0] =
11631 /* all UPs mapping to TC0 */
11632 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11633 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11634 hw->local_dcbx_config.etsrec =
11635 hw->local_dcbx_config.etscfg;
11636 hw->local_dcbx_config.pfc.willing = 0;
11637 hw->local_dcbx_config.pfc.pfccap =
11638 I40E_MAX_TRAFFIC_CLASS;
11639 /* FW needs one App to configure HW */
11640 hw->local_dcbx_config.numapps = 1;
11641 hw->local_dcbx_config.app[0].selector =
11642 I40E_APP_SEL_ETHTYPE;
11643 hw->local_dcbx_config.app[0].priority = 3;
11644 hw->local_dcbx_config.app[0].protocolid =
11645 I40E_APP_PROTOID_FCOE;
11646 ret = i40e_set_dcb_config(hw);
11649 "default dcb config fails. err = %d, aq_err = %d.",
11650 ret, hw->aq.asq_last_status);
11655 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11656 ret, hw->aq.asq_last_status);
11660 if (i40e_need_stop_lldp(dev)) {
11661 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11662 if (ret != I40E_SUCCESS)
11663 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11666 ret = i40e_aq_start_lldp(hw, true, NULL);
11667 if (ret != I40E_SUCCESS)
11668 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11670 ret = i40e_init_dcb(hw, true);
11672 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11674 "HW doesn't support DCBX offload.");
11679 "DCBX configuration failed, err = %d, aq_err = %d.",
11680 ret, hw->aq.asq_last_status);
11688 * i40e_dcb_setup - setup dcb related config
11689 * @dev: device being configured
11691 * Returns 0 on success, negative value on failure
11694 i40e_dcb_setup(struct rte_eth_dev *dev)
11696 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11697 struct i40e_dcbx_config dcb_cfg;
11698 uint8_t tc_map = 0;
11701 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11702 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11706 if (pf->vf_num != 0)
11707 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11709 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11711 PMD_INIT_LOG(ERR, "invalid dcb config");
11714 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11716 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11724 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11725 struct rte_eth_dcb_info *dcb_info)
11727 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11728 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11729 struct i40e_vsi *vsi = pf->main_vsi;
11730 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11731 uint16_t bsf, tc_mapping;
11734 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11735 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11737 dcb_info->nb_tcs = 1;
11738 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11739 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11740 for (i = 0; i < dcb_info->nb_tcs; i++)
11741 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11743 /* get queue mapping if vmdq is disabled */
11744 if (!pf->nb_cfg_vmdq_vsi) {
11745 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11746 if (!(vsi->enabled_tc & (1 << i)))
11748 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11749 dcb_info->tc_queue.tc_rxq[j][i].base =
11750 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11751 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11752 dcb_info->tc_queue.tc_txq[j][i].base =
11753 dcb_info->tc_queue.tc_rxq[j][i].base;
11754 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11755 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11756 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11757 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11758 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11763 /* get queue mapping if vmdq is enabled */
11765 vsi = pf->vmdq[j].vsi;
11766 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11767 if (!(vsi->enabled_tc & (1 << i)))
11769 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11770 dcb_info->tc_queue.tc_rxq[j][i].base =
11771 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11772 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11773 dcb_info->tc_queue.tc_txq[j][i].base =
11774 dcb_info->tc_queue.tc_rxq[j][i].base;
11775 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11776 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11777 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11778 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11779 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11782 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11787 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11789 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11790 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11791 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11792 uint16_t msix_intr;
11794 msix_intr = intr_handle->intr_vec[queue_id];
11795 if (msix_intr == I40E_MISC_VEC_ID)
11796 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11797 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11798 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11799 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11802 I40E_PFINT_DYN_CTLN(msix_intr -
11803 I40E_RX_VEC_START),
11804 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11805 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11806 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11808 I40E_WRITE_FLUSH(hw);
11809 rte_intr_ack(&pci_dev->intr_handle);
11815 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11817 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11818 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11820 uint16_t msix_intr;
11822 msix_intr = intr_handle->intr_vec[queue_id];
11823 if (msix_intr == I40E_MISC_VEC_ID)
11824 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11825 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11828 I40E_PFINT_DYN_CTLN(msix_intr -
11829 I40E_RX_VEC_START),
11830 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11831 I40E_WRITE_FLUSH(hw);
11837 * This function is used to check if the register is valid.
11838 * Below is the valid registers list for X722 only:
11842 * 0x208e00--0x209000
11843 * 0x20be00--0x20c000
11844 * 0x263c00--0x264000
11845 * 0x265c00--0x266000
11847 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11849 if ((type != I40E_MAC_X722) &&
11850 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11851 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11852 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11853 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11854 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11855 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11856 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11862 static int i40e_get_regs(struct rte_eth_dev *dev,
11863 struct rte_dev_reg_info *regs)
11865 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11866 uint32_t *ptr_data = regs->data;
11867 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11868 const struct i40e_reg_info *reg_info;
11870 if (ptr_data == NULL) {
11871 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11872 regs->width = sizeof(uint32_t);
11876 /* The first few registers have to be read using AQ operations */
11878 while (i40e_regs_adminq[reg_idx].name) {
11879 reg_info = &i40e_regs_adminq[reg_idx++];
11880 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11882 arr_idx2 <= reg_info->count2;
11884 reg_offset = arr_idx * reg_info->stride1 +
11885 arr_idx2 * reg_info->stride2;
11886 reg_offset += reg_info->base_addr;
11887 ptr_data[reg_offset >> 2] =
11888 i40e_read_rx_ctl(hw, reg_offset);
11892 /* The remaining registers can be read using primitives */
11894 while (i40e_regs_others[reg_idx].name) {
11895 reg_info = &i40e_regs_others[reg_idx++];
11896 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11898 arr_idx2 <= reg_info->count2;
11900 reg_offset = arr_idx * reg_info->stride1 +
11901 arr_idx2 * reg_info->stride2;
11902 reg_offset += reg_info->base_addr;
11903 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11904 ptr_data[reg_offset >> 2] = 0;
11906 ptr_data[reg_offset >> 2] =
11907 I40E_READ_REG(hw, reg_offset);
11914 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11918 /* Convert word count to byte count */
11919 return hw->nvm.sr_size << 1;
11922 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11923 struct rte_dev_eeprom_info *eeprom)
11925 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11926 uint16_t *data = eeprom->data;
11927 uint16_t offset, length, cnt_words;
11930 offset = eeprom->offset >> 1;
11931 length = eeprom->length >> 1;
11932 cnt_words = length;
11934 if (offset > hw->nvm.sr_size ||
11935 offset + length > hw->nvm.sr_size) {
11936 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11940 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11942 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11943 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11944 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11951 static int i40e_get_module_info(struct rte_eth_dev *dev,
11952 struct rte_eth_dev_module_info *modinfo)
11954 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11955 uint32_t sff8472_comp = 0;
11956 uint32_t sff8472_swap = 0;
11957 uint32_t sff8636_rev = 0;
11958 i40e_status status;
11961 /* Check if firmware supports reading module EEPROM. */
11962 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11964 "Module EEPROM memory read not supported. "
11965 "Please update the NVM image.\n");
11969 status = i40e_update_link_info(hw);
11973 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11975 "Cannot read module EEPROM memory. "
11976 "No module connected.\n");
11980 type = hw->phy.link_info.module_type[0];
11983 case I40E_MODULE_TYPE_SFP:
11984 status = i40e_aq_get_phy_register(hw,
11985 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11986 I40E_I2C_EEPROM_DEV_ADDR, 1,
11987 I40E_MODULE_SFF_8472_COMP,
11988 &sff8472_comp, NULL);
11992 status = i40e_aq_get_phy_register(hw,
11993 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11994 I40E_I2C_EEPROM_DEV_ADDR, 1,
11995 I40E_MODULE_SFF_8472_SWAP,
11996 &sff8472_swap, NULL);
12000 /* Check if the module requires address swap to access
12001 * the other EEPROM memory page.
12003 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12004 PMD_DRV_LOG(WARNING,
12005 "Module address swap to access "
12006 "page 0xA2 is not supported.\n");
12007 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12008 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12009 } else if (sff8472_comp == 0x00) {
12010 /* Module is not SFF-8472 compliant */
12011 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12012 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12014 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12015 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12018 case I40E_MODULE_TYPE_QSFP_PLUS:
12019 /* Read from memory page 0. */
12020 status = i40e_aq_get_phy_register(hw,
12021 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12023 I40E_MODULE_REVISION_ADDR,
12024 &sff8636_rev, NULL);
12027 /* Determine revision compliance byte */
12028 if (sff8636_rev > 0x02) {
12029 /* Module is SFF-8636 compliant */
12030 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12031 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12033 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12034 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12037 case I40E_MODULE_TYPE_QSFP28:
12038 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12039 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12042 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12048 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12049 struct rte_dev_eeprom_info *info)
12051 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12052 bool is_sfp = false;
12053 i40e_status status;
12055 uint32_t value = 0;
12058 if (!info || !info->length || !info->data)
12061 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12065 for (i = 0; i < info->length; i++) {
12066 u32 offset = i + info->offset;
12067 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12069 /* Check if we need to access the other memory page */
12071 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12072 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12073 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12076 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12077 /* Compute memory page number and offset. */
12078 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12082 status = i40e_aq_get_phy_register(hw,
12083 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12084 addr, offset, 1, &value, NULL);
12087 data[i] = (uint8_t)value;
12092 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12093 struct rte_ether_addr *mac_addr)
12095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12096 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12097 struct i40e_vsi *vsi = pf->main_vsi;
12098 struct i40e_mac_filter_info mac_filter;
12099 struct i40e_mac_filter *f;
12102 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12103 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12107 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12108 if (rte_is_same_ether_addr(&pf->dev_addr,
12109 &f->mac_info.mac_addr))
12114 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12118 mac_filter = f->mac_info;
12119 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12120 if (ret != I40E_SUCCESS) {
12121 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12124 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12125 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12126 if (ret != I40E_SUCCESS) {
12127 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12130 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12132 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12133 mac_addr->addr_bytes, NULL);
12134 if (ret != I40E_SUCCESS) {
12135 PMD_DRV_LOG(ERR, "Failed to change mac");
12143 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12146 struct rte_eth_dev_data *dev_data = pf->dev_data;
12147 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12150 /* check if mtu is within the allowed range */
12151 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12154 /* mtu setting is forbidden if port is start */
12155 if (dev_data->dev_started) {
12156 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12157 dev_data->port_id);
12161 if (frame_size > RTE_ETHER_MAX_LEN)
12162 dev_data->dev_conf.rxmode.offloads |=
12163 DEV_RX_OFFLOAD_JUMBO_FRAME;
12165 dev_data->dev_conf.rxmode.offloads &=
12166 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12168 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12173 /* Restore ethertype filter */
12175 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12177 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12178 struct i40e_ethertype_filter_list
12179 *ethertype_list = &pf->ethertype.ethertype_list;
12180 struct i40e_ethertype_filter *f;
12181 struct i40e_control_filter_stats stats;
12184 TAILQ_FOREACH(f, ethertype_list, rules) {
12186 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12187 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12188 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12189 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12190 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12192 memset(&stats, 0, sizeof(stats));
12193 i40e_aq_add_rem_control_packet_filter(hw,
12194 f->input.mac_addr.addr_bytes,
12195 f->input.ether_type,
12196 flags, pf->main_vsi->seid,
12197 f->queue, 1, &stats, NULL);
12199 PMD_DRV_LOG(INFO, "Ethertype filter:"
12200 " mac_etype_used = %u, etype_used = %u,"
12201 " mac_etype_free = %u, etype_free = %u",
12202 stats.mac_etype_used, stats.etype_used,
12203 stats.mac_etype_free, stats.etype_free);
12206 /* Restore tunnel filter */
12208 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12210 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12211 struct i40e_vsi *vsi;
12212 struct i40e_pf_vf *vf;
12213 struct i40e_tunnel_filter_list
12214 *tunnel_list = &pf->tunnel.tunnel_list;
12215 struct i40e_tunnel_filter *f;
12216 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12217 bool big_buffer = 0;
12219 TAILQ_FOREACH(f, tunnel_list, rules) {
12221 vsi = pf->main_vsi;
12223 vf = &pf->vfs[f->vf_id];
12226 memset(&cld_filter, 0, sizeof(cld_filter));
12227 rte_ether_addr_copy((struct rte_ether_addr *)
12228 &f->input.outer_mac,
12229 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12230 rte_ether_addr_copy((struct rte_ether_addr *)
12231 &f->input.inner_mac,
12232 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12233 cld_filter.element.inner_vlan = f->input.inner_vlan;
12234 cld_filter.element.flags = f->input.flags;
12235 cld_filter.element.tenant_id = f->input.tenant_id;
12236 cld_filter.element.queue_number = f->queue;
12237 rte_memcpy(cld_filter.general_fields,
12238 f->input.general_fields,
12239 sizeof(f->input.general_fields));
12241 if (((f->input.flags &
12242 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12243 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12245 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12246 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12248 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12249 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12253 i40e_aq_add_cloud_filters_bb(hw,
12254 vsi->seid, &cld_filter, 1);
12256 i40e_aq_add_cloud_filters(hw, vsi->seid,
12257 &cld_filter.element, 1);
12261 /* Restore RSS filter */
12263 i40e_rss_filter_restore(struct i40e_pf *pf)
12265 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12266 struct i40e_rss_filter *filter;
12268 TAILQ_FOREACH(filter, list, next) {
12269 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12274 i40e_filter_restore(struct i40e_pf *pf)
12276 i40e_ethertype_filter_restore(pf);
12277 i40e_tunnel_filter_restore(pf);
12278 i40e_fdir_filter_restore(pf);
12279 i40e_rss_filter_restore(pf);
12283 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12285 if (strcmp(dev->device->driver->name, drv->driver.name))
12292 is_i40e_supported(struct rte_eth_dev *dev)
12294 return is_device_supported(dev, &rte_i40e_pmd);
12297 struct i40e_customized_pctype*
12298 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12302 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12303 if (pf->customized_pctype[i].index == index)
12304 return &pf->customized_pctype[i];
12310 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12311 uint32_t pkg_size, uint32_t proto_num,
12312 struct rte_pmd_i40e_proto_info *proto,
12313 enum rte_pmd_i40e_package_op op)
12315 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12316 uint32_t pctype_num;
12317 struct rte_pmd_i40e_ptype_info *pctype;
12318 uint32_t buff_size;
12319 struct i40e_customized_pctype *new_pctype = NULL;
12321 uint8_t pctype_value;
12326 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12327 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12328 PMD_DRV_LOG(ERR, "Unsupported operation.");
12332 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12333 (uint8_t *)&pctype_num, sizeof(pctype_num),
12334 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12336 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12340 PMD_DRV_LOG(INFO, "No new pctype added");
12344 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12345 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12347 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12350 /* get information about new pctype list */
12351 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12352 (uint8_t *)pctype, buff_size,
12353 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12355 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12360 /* Update customized pctype. */
12361 for (i = 0; i < pctype_num; i++) {
12362 pctype_value = pctype[i].ptype_id;
12363 memset(name, 0, sizeof(name));
12364 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12365 proto_id = pctype[i].protocols[j];
12366 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12368 for (n = 0; n < proto_num; n++) {
12369 if (proto[n].proto_id != proto_id)
12371 strlcat(name, proto[n].name, sizeof(name));
12372 strlcat(name, "_", sizeof(name));
12376 name[strlen(name) - 1] = '\0';
12377 PMD_DRV_LOG(INFO, "name = %s\n", name);
12378 if (!strcmp(name, "GTPC"))
12380 i40e_find_customized_pctype(pf,
12381 I40E_CUSTOMIZED_GTPC);
12382 else if (!strcmp(name, "GTPU_IPV4"))
12384 i40e_find_customized_pctype(pf,
12385 I40E_CUSTOMIZED_GTPU_IPV4);
12386 else if (!strcmp(name, "GTPU_IPV6"))
12388 i40e_find_customized_pctype(pf,
12389 I40E_CUSTOMIZED_GTPU_IPV6);
12390 else if (!strcmp(name, "GTPU"))
12392 i40e_find_customized_pctype(pf,
12393 I40E_CUSTOMIZED_GTPU);
12394 else if (!strcmp(name, "IPV4_L2TPV3"))
12396 i40e_find_customized_pctype(pf,
12397 I40E_CUSTOMIZED_IPV4_L2TPV3);
12398 else if (!strcmp(name, "IPV6_L2TPV3"))
12400 i40e_find_customized_pctype(pf,
12401 I40E_CUSTOMIZED_IPV6_L2TPV3);
12402 else if (!strcmp(name, "IPV4_ESP"))
12404 i40e_find_customized_pctype(pf,
12405 I40E_CUSTOMIZED_ESP_IPV4);
12406 else if (!strcmp(name, "IPV6_ESP"))
12408 i40e_find_customized_pctype(pf,
12409 I40E_CUSTOMIZED_ESP_IPV6);
12410 else if (!strcmp(name, "IPV4_UDP_ESP"))
12412 i40e_find_customized_pctype(pf,
12413 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12414 else if (!strcmp(name, "IPV6_UDP_ESP"))
12416 i40e_find_customized_pctype(pf,
12417 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12418 else if (!strcmp(name, "IPV4_AH"))
12420 i40e_find_customized_pctype(pf,
12421 I40E_CUSTOMIZED_AH_IPV4);
12422 else if (!strcmp(name, "IPV6_AH"))
12424 i40e_find_customized_pctype(pf,
12425 I40E_CUSTOMIZED_AH_IPV6);
12427 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12428 new_pctype->pctype = pctype_value;
12429 new_pctype->valid = true;
12431 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12432 new_pctype->valid = false;
12442 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12443 uint32_t pkg_size, uint32_t proto_num,
12444 struct rte_pmd_i40e_proto_info *proto,
12445 enum rte_pmd_i40e_package_op op)
12447 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12448 uint16_t port_id = dev->data->port_id;
12449 uint32_t ptype_num;
12450 struct rte_pmd_i40e_ptype_info *ptype;
12451 uint32_t buff_size;
12453 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12458 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12459 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12460 PMD_DRV_LOG(ERR, "Unsupported operation.");
12464 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12465 rte_pmd_i40e_ptype_mapping_reset(port_id);
12469 /* get information about new ptype num */
12470 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12471 (uint8_t *)&ptype_num, sizeof(ptype_num),
12472 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12474 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12478 PMD_DRV_LOG(INFO, "No new ptype added");
12482 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12483 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12485 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12489 /* get information about new ptype list */
12490 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12491 (uint8_t *)ptype, buff_size,
12492 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12494 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12499 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12500 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12501 if (!ptype_mapping) {
12502 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12507 /* Update ptype mapping table. */
12508 for (i = 0; i < ptype_num; i++) {
12509 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12510 ptype_mapping[i].sw_ptype = 0;
12512 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12513 proto_id = ptype[i].protocols[j];
12514 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12516 for (n = 0; n < proto_num; n++) {
12517 if (proto[n].proto_id != proto_id)
12519 memset(name, 0, sizeof(name));
12520 strcpy(name, proto[n].name);
12521 PMD_DRV_LOG(INFO, "name = %s\n", name);
12522 if (!strncasecmp(name, "PPPOE", 5))
12523 ptype_mapping[i].sw_ptype |=
12524 RTE_PTYPE_L2_ETHER_PPPOE;
12525 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12527 ptype_mapping[i].sw_ptype |=
12528 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12529 ptype_mapping[i].sw_ptype |=
12531 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12533 ptype_mapping[i].sw_ptype |=
12534 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12535 ptype_mapping[i].sw_ptype |=
12536 RTE_PTYPE_INNER_L4_FRAG;
12537 } else if (!strncasecmp(name, "OIPV4", 5)) {
12538 ptype_mapping[i].sw_ptype |=
12539 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12541 } else if (!strncasecmp(name, "IPV4", 4) &&
12543 ptype_mapping[i].sw_ptype |=
12544 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12545 else if (!strncasecmp(name, "IPV4", 4) &&
12547 ptype_mapping[i].sw_ptype |=
12548 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12549 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12551 ptype_mapping[i].sw_ptype |=
12552 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12553 ptype_mapping[i].sw_ptype |=
12555 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12557 ptype_mapping[i].sw_ptype |=
12558 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12559 ptype_mapping[i].sw_ptype |=
12560 RTE_PTYPE_INNER_L4_FRAG;
12561 } else if (!strncasecmp(name, "OIPV6", 5)) {
12562 ptype_mapping[i].sw_ptype |=
12563 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12565 } else if (!strncasecmp(name, "IPV6", 4) &&
12567 ptype_mapping[i].sw_ptype |=
12568 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12569 else if (!strncasecmp(name, "IPV6", 4) &&
12571 ptype_mapping[i].sw_ptype |=
12572 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12573 else if (!strncasecmp(name, "UDP", 3) &&
12575 ptype_mapping[i].sw_ptype |=
12577 else if (!strncasecmp(name, "UDP", 3) &&
12579 ptype_mapping[i].sw_ptype |=
12580 RTE_PTYPE_INNER_L4_UDP;
12581 else if (!strncasecmp(name, "TCP", 3) &&
12583 ptype_mapping[i].sw_ptype |=
12585 else if (!strncasecmp(name, "TCP", 3) &&
12587 ptype_mapping[i].sw_ptype |=
12588 RTE_PTYPE_INNER_L4_TCP;
12589 else if (!strncasecmp(name, "SCTP", 4) &&
12591 ptype_mapping[i].sw_ptype |=
12593 else if (!strncasecmp(name, "SCTP", 4) &&
12595 ptype_mapping[i].sw_ptype |=
12596 RTE_PTYPE_INNER_L4_SCTP;
12597 else if ((!strncasecmp(name, "ICMP", 4) ||
12598 !strncasecmp(name, "ICMPV6", 6)) &&
12600 ptype_mapping[i].sw_ptype |=
12602 else if ((!strncasecmp(name, "ICMP", 4) ||
12603 !strncasecmp(name, "ICMPV6", 6)) &&
12605 ptype_mapping[i].sw_ptype |=
12606 RTE_PTYPE_INNER_L4_ICMP;
12607 else if (!strncasecmp(name, "GTPC", 4)) {
12608 ptype_mapping[i].sw_ptype |=
12609 RTE_PTYPE_TUNNEL_GTPC;
12611 } else if (!strncasecmp(name, "GTPU", 4)) {
12612 ptype_mapping[i].sw_ptype |=
12613 RTE_PTYPE_TUNNEL_GTPU;
12615 } else if (!strncasecmp(name, "ESP", 3)) {
12616 ptype_mapping[i].sw_ptype |=
12617 RTE_PTYPE_TUNNEL_ESP;
12619 } else if (!strncasecmp(name, "GRENAT", 6)) {
12620 ptype_mapping[i].sw_ptype |=
12621 RTE_PTYPE_TUNNEL_GRENAT;
12623 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12624 !strncasecmp(name, "L2TPV2", 6) ||
12625 !strncasecmp(name, "L2TPV3", 6)) {
12626 ptype_mapping[i].sw_ptype |=
12627 RTE_PTYPE_TUNNEL_L2TP;
12636 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12639 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12641 rte_free(ptype_mapping);
12647 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12648 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12650 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12651 uint32_t proto_num;
12652 struct rte_pmd_i40e_proto_info *proto;
12653 uint32_t buff_size;
12657 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12658 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12659 PMD_DRV_LOG(ERR, "Unsupported operation.");
12663 /* get information about protocol number */
12664 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12665 (uint8_t *)&proto_num, sizeof(proto_num),
12666 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12668 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12672 PMD_DRV_LOG(INFO, "No new protocol added");
12676 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12677 proto = rte_zmalloc("new_proto", buff_size, 0);
12679 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12683 /* get information about protocol list */
12684 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12685 (uint8_t *)proto, buff_size,
12686 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12688 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12693 /* Check if GTP is supported. */
12694 for (i = 0; i < proto_num; i++) {
12695 if (!strncmp(proto[i].name, "GTP", 3)) {
12696 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12697 pf->gtp_support = true;
12699 pf->gtp_support = false;
12704 /* Check if ESP is supported. */
12705 for (i = 0; i < proto_num; i++) {
12706 if (!strncmp(proto[i].name, "ESP", 3)) {
12707 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12708 pf->esp_support = true;
12710 pf->esp_support = false;
12715 /* Update customized pctype info */
12716 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12717 proto_num, proto, op);
12719 PMD_DRV_LOG(INFO, "No pctype is updated.");
12721 /* Update customized ptype info */
12722 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12723 proto_num, proto, op);
12725 PMD_DRV_LOG(INFO, "No ptype is updated.");
12730 /* Create a QinQ cloud filter
12732 * The Fortville NIC has limited resources for tunnel filters,
12733 * so we can only reuse existing filters.
12735 * In step 1 we define which Field Vector fields can be used for
12737 * As we do not have the inner tag defined as a field,
12738 * we have to define it first, by reusing one of L1 entries.
12740 * In step 2 we are replacing one of existing filter types with
12741 * a new one for QinQ.
12742 * As we reusing L1 and replacing L2, some of the default filter
12743 * types will disappear,which depends on L1 and L2 entries we reuse.
12745 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12747 * 1. Create L1 filter of outer vlan (12b) which will be in use
12748 * later when we define the cloud filter.
12749 * a. Valid_flags.replace_cloud = 0
12750 * b. Old_filter = 10 (Stag_Inner_Vlan)
12751 * c. New_filter = 0x10
12752 * d. TR bit = 0xff (optional, not used here)
12753 * e. Buffer – 2 entries:
12754 * i. Byte 0 = 8 (outer vlan FV index).
12756 * Byte 2-3 = 0x0fff
12757 * ii. Byte 0 = 37 (inner vlan FV index).
12759 * Byte 2-3 = 0x0fff
12762 * 2. Create cloud filter using two L1 filters entries: stag and
12763 * new filter(outer vlan+ inner vlan)
12764 * a. Valid_flags.replace_cloud = 1
12765 * b. Old_filter = 1 (instead of outer IP)
12766 * c. New_filter = 0x10
12767 * d. Buffer – 2 entries:
12768 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12769 * Byte 1-3 = 0 (rsv)
12770 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12771 * Byte 9-11 = 0 (rsv)
12774 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12776 int ret = -ENOTSUP;
12777 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12778 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12780 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12782 if (pf->support_multi_driver) {
12783 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12788 memset(&filter_replace, 0,
12789 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12790 memset(&filter_replace_buf, 0,
12791 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12793 /* create L1 filter */
12794 filter_replace.old_filter_type =
12795 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12796 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12797 filter_replace.tr_bit = 0;
12799 /* Prepare the buffer, 2 entries */
12800 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12801 filter_replace_buf.data[0] |=
12802 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12803 /* Field Vector 12b mask */
12804 filter_replace_buf.data[2] = 0xff;
12805 filter_replace_buf.data[3] = 0x0f;
12806 filter_replace_buf.data[4] =
12807 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12808 filter_replace_buf.data[4] |=
12809 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12810 /* Field Vector 12b mask */
12811 filter_replace_buf.data[6] = 0xff;
12812 filter_replace_buf.data[7] = 0x0f;
12813 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12814 &filter_replace_buf);
12815 if (ret != I40E_SUCCESS)
12818 if (filter_replace.old_filter_type !=
12819 filter_replace.new_filter_type)
12820 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12821 " original: 0x%x, new: 0x%x",
12823 filter_replace.old_filter_type,
12824 filter_replace.new_filter_type);
12826 /* Apply the second L2 cloud filter */
12827 memset(&filter_replace, 0,
12828 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12829 memset(&filter_replace_buf, 0,
12830 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12832 /* create L2 filter, input for L2 filter will be L1 filter */
12833 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12834 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12835 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12837 /* Prepare the buffer, 2 entries */
12838 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12839 filter_replace_buf.data[0] |=
12840 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12841 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12842 filter_replace_buf.data[4] |=
12843 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12844 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12845 &filter_replace_buf);
12846 if (!ret && (filter_replace.old_filter_type !=
12847 filter_replace.new_filter_type))
12848 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12849 " original: 0x%x, new: 0x%x",
12851 filter_replace.old_filter_type,
12852 filter_replace.new_filter_type);
12858 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12859 const struct rte_flow_action_rss *in)
12861 if (in->key_len > RTE_DIM(out->key) ||
12862 in->queue_num > RTE_DIM(out->queue))
12864 if (!in->key && in->key_len)
12866 out->conf = (struct rte_flow_action_rss){
12868 .level = in->level,
12869 .types = in->types,
12870 .key_len = in->key_len,
12871 .queue_num = in->queue_num,
12872 .queue = memcpy(out->queue, in->queue,
12873 sizeof(*in->queue) * in->queue_num),
12876 out->conf.key = memcpy(out->key, in->key, in->key_len);
12880 /* Write HENA register to enable hash */
12882 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
12884 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12885 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
12889 ret = i40e_set_rss_key(pf->main_vsi, key,
12890 rss_conf->conf.key_len);
12894 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
12895 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
12896 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
12897 I40E_WRITE_FLUSH(hw);
12902 /* Configure hash input set */
12904 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
12906 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12907 struct rte_eth_input_set_conf conf;
12912 static const struct {
12914 enum rte_eth_input_set_field field;
12915 } inset_match_table[] = {
12916 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
12917 RTE_ETH_INPUT_SET_L3_SRC_IP4},
12918 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
12919 RTE_ETH_INPUT_SET_L3_DST_IP4},
12920 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
12921 RTE_ETH_INPUT_SET_UNKNOWN},
12922 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
12923 RTE_ETH_INPUT_SET_UNKNOWN},
12925 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
12926 RTE_ETH_INPUT_SET_L3_SRC_IP4},
12927 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
12928 RTE_ETH_INPUT_SET_L3_DST_IP4},
12929 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
12930 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
12931 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
12932 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
12934 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
12935 RTE_ETH_INPUT_SET_L3_SRC_IP4},
12936 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
12937 RTE_ETH_INPUT_SET_L3_DST_IP4},
12938 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
12939 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
12940 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
12941 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
12943 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
12944 RTE_ETH_INPUT_SET_L3_SRC_IP4},
12945 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
12946 RTE_ETH_INPUT_SET_L3_DST_IP4},
12947 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
12948 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
12949 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
12950 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
12952 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
12953 RTE_ETH_INPUT_SET_L3_SRC_IP4},
12954 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
12955 RTE_ETH_INPUT_SET_L3_DST_IP4},
12956 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
12957 RTE_ETH_INPUT_SET_UNKNOWN},
12958 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
12959 RTE_ETH_INPUT_SET_UNKNOWN},
12961 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
12962 RTE_ETH_INPUT_SET_L3_SRC_IP6},
12963 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
12964 RTE_ETH_INPUT_SET_L3_DST_IP6},
12965 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
12966 RTE_ETH_INPUT_SET_UNKNOWN},
12967 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
12968 RTE_ETH_INPUT_SET_UNKNOWN},
12970 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
12971 RTE_ETH_INPUT_SET_L3_SRC_IP6},
12972 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
12973 RTE_ETH_INPUT_SET_L3_DST_IP6},
12974 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
12975 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
12976 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
12977 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
12979 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
12980 RTE_ETH_INPUT_SET_L3_SRC_IP6},
12981 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
12982 RTE_ETH_INPUT_SET_L3_DST_IP6},
12983 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
12984 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
12985 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
12986 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
12988 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
12989 RTE_ETH_INPUT_SET_L3_SRC_IP6},
12990 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
12991 RTE_ETH_INPUT_SET_L3_DST_IP6},
12992 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
12993 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
12994 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
12995 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
12997 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
12998 RTE_ETH_INPUT_SET_L3_SRC_IP6},
12999 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13000 RTE_ETH_INPUT_SET_L3_DST_IP6},
13001 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13002 RTE_ETH_INPUT_SET_UNKNOWN},
13003 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13004 RTE_ETH_INPUT_SET_UNKNOWN},
13007 mask0 = types & pf->adapter->flow_types_mask;
13008 conf.op = RTE_ETH_INPUT_SET_SELECT;
13009 conf.inset_size = 0;
13010 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13011 if (mask0 & (1ULL << i)) {
13012 conf.flow_type = i;
13017 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13018 if ((types & inset_match_table[j].type) ==
13019 inset_match_table[j].type) {
13020 if (inset_match_table[j].field ==
13021 RTE_ETH_INPUT_SET_UNKNOWN)
13024 conf.field[conf.inset_size] =
13025 inset_match_table[j].field;
13030 if (conf.inset_size) {
13031 ret = i40e_hash_filter_inset_select(hw, &conf);
13039 /* Look up the conflicted rule then mark it as invalid */
13041 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13042 struct i40e_rte_flow_rss_conf *conf)
13044 struct i40e_rss_filter *rss_item;
13045 uint64_t rss_inset;
13047 /* Clear input set bits before comparing the pctype */
13048 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13049 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13051 /* Look up the conflicted rule then mark it as invalid */
13052 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13053 if (!rss_item->rss_filter_info.valid)
13056 if (conf->conf.queue_num &&
13057 rss_item->rss_filter_info.conf.queue_num)
13058 rss_item->rss_filter_info.valid = false;
13060 if (conf->conf.types &&
13061 (rss_item->rss_filter_info.conf.types &
13063 (conf->conf.types & rss_inset))
13064 rss_item->rss_filter_info.valid = false;
13066 if (conf->conf.func ==
13067 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13068 rss_item->rss_filter_info.conf.func ==
13069 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13070 rss_item->rss_filter_info.valid = false;
13074 /* Configure RSS hash function */
13076 i40e_rss_config_hash_function(struct i40e_pf *pf,
13077 struct i40e_rte_flow_rss_conf *conf)
13079 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13084 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13085 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13086 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13087 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13088 I40E_WRITE_FLUSH(hw);
13089 i40e_rss_mark_invalid_rule(pf, conf);
13093 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13095 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13096 I40E_WRITE_FLUSH(hw);
13097 i40e_rss_mark_invalid_rule(pf, conf);
13098 } else if (conf->conf.func ==
13099 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13100 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13102 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13103 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13104 if (mask0 & (1UL << i))
13108 if (i == UINT64_BIT)
13111 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13112 j < I40E_FILTER_PCTYPE_MAX; j++) {
13113 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13114 i40e_write_global_rx_ctl(hw,
13116 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13123 /* Enable RSS according to the configuration */
13125 i40e_rss_enable_hash(struct i40e_pf *pf,
13126 struct i40e_rte_flow_rss_conf *conf)
13128 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13129 struct i40e_rte_flow_rss_conf rss_conf;
13131 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13134 memset(&rss_conf, 0, sizeof(rss_conf));
13135 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13137 /* Configure hash input set */
13138 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13141 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13142 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13143 /* Random default keys */
13144 static uint32_t rss_key_default[] = {0x6b793944,
13145 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13146 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13147 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13149 rss_conf.conf.key = (uint8_t *)rss_key_default;
13150 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13153 "No valid RSS key config for i40e, using default\n");
13156 rss_conf.conf.types |= rss_info->conf.types;
13157 i40e_rss_hash_set(pf, &rss_conf);
13159 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13160 i40e_rss_config_hash_function(pf, conf);
13162 i40e_rss_mark_invalid_rule(pf, conf);
13167 /* Configure RSS queue region */
13169 i40e_rss_config_queue_region(struct i40e_pf *pf,
13170 struct i40e_rte_flow_rss_conf *conf)
13172 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13177 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13178 * It's necessary to calculate the actual PF queues that are configured.
13180 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13181 num = i40e_pf_calc_configured_queues_num(pf);
13183 num = pf->dev_data->nb_rx_queues;
13185 num = RTE_MIN(num, conf->conf.queue_num);
13186 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13191 "No PF queues are configured to enable RSS for port %u",
13192 pf->dev_data->port_id);
13196 /* Fill in redirection table */
13197 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13200 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13201 hw->func_caps.rss_table_entry_width) - 1));
13203 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13206 i40e_rss_mark_invalid_rule(pf, conf);
13211 /* Configure RSS hash function to default */
13213 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13214 struct i40e_rte_flow_rss_conf *conf)
13216 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13221 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13222 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13223 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13225 "Hash function already set to Toeplitz");
13226 I40E_WRITE_FLUSH(hw);
13230 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13232 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13233 I40E_WRITE_FLUSH(hw);
13234 } else if (conf->conf.func ==
13235 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13236 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13238 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13239 if (mask0 & (1UL << i))
13243 if (i == UINT64_BIT)
13246 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13247 j < I40E_FILTER_PCTYPE_MAX; j++) {
13248 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13249 i40e_write_global_rx_ctl(hw,
13258 /* Disable RSS hash and configure default input set */
13260 i40e_rss_disable_hash(struct i40e_pf *pf,
13261 struct i40e_rte_flow_rss_conf *conf)
13263 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13264 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13265 struct i40e_rte_flow_rss_conf rss_conf;
13268 memset(&rss_conf, 0, sizeof(rss_conf));
13269 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13271 /* Disable RSS hash */
13272 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13273 i40e_rss_hash_set(pf, &rss_conf);
13275 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13276 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13277 !(conf->conf.types & (1ULL << i)))
13280 /* Configure default input set */
13281 struct rte_eth_input_set_conf input_conf = {
13282 .op = RTE_ETH_INPUT_SET_SELECT,
13286 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13287 i40e_hash_filter_inset_select(hw, &input_conf);
13290 rss_info->conf.types = rss_conf.conf.types;
13292 i40e_rss_clear_hash_function(pf, conf);
13297 /* Configure RSS queue region to default */
13299 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13301 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13302 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13303 uint16_t queue[I40E_MAX_Q_PER_TC];
13304 uint32_t num_rxq, i;
13308 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13310 for (j = 0; j < num_rxq; j++)
13313 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13314 * It's necessary to calculate the actual PF queues that are configured.
13316 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13317 num = i40e_pf_calc_configured_queues_num(pf);
13319 num = pf->dev_data->nb_rx_queues;
13321 num = RTE_MIN(num, num_rxq);
13322 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13327 "No PF queues are configured to enable RSS for port %u",
13328 pf->dev_data->port_id);
13332 /* Fill in redirection table */
13333 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13336 lut = (lut << 8) | (queue[j] & ((0x1 <<
13337 hw->func_caps.rss_table_entry_width) - 1));
13339 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13342 rss_info->conf.queue_num = 0;
13343 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13349 i40e_config_rss_filter(struct i40e_pf *pf,
13350 struct i40e_rte_flow_rss_conf *conf, bool add)
13352 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13353 struct rte_flow_action_rss update_conf = rss_info->conf;
13357 if (conf->conf.queue_num) {
13358 /* Configure RSS queue region */
13359 ret = i40e_rss_config_queue_region(pf, conf);
13363 update_conf.queue_num = conf->conf.queue_num;
13364 update_conf.queue = conf->conf.queue;
13365 } else if (conf->conf.func ==
13366 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13367 /* Configure hash function */
13368 ret = i40e_rss_config_hash_function(pf, conf);
13372 update_conf.func = conf->conf.func;
13374 /* Configure hash enable and input set */
13375 ret = i40e_rss_enable_hash(pf, conf);
13379 update_conf.types |= conf->conf.types;
13380 update_conf.key = conf->conf.key;
13381 update_conf.key_len = conf->conf.key_len;
13384 /* Update RSS info in pf */
13385 if (i40e_rss_conf_init(rss_info, &update_conf))
13391 if (conf->conf.queue_num)
13392 i40e_rss_clear_queue_region(pf);
13393 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13394 i40e_rss_clear_hash_function(pf, conf);
13396 i40e_rss_disable_hash(pf, conf);
13402 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13403 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13404 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13405 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13407 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13408 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13410 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13411 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13414 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13415 ETH_I40E_FLOATING_VEB_ARG "=1"
13416 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13417 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13418 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13419 ETH_I40E_USE_LATEST_VEC "=0|1");