1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
246 char *fw_version, size_t fw_size);
247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
248 struct rte_eth_dev_info *dev_info);
249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
253 enum rte_vlan_type vlan_type,
255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
263 struct rte_eth_fc_conf *fc_conf);
264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
265 struct rte_eth_fc_conf *fc_conf);
266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
267 struct rte_eth_pfc_conf *pfc_conf);
268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr,
272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
277 struct rte_eth_rss_reta_entry64 *reta_conf,
280 static int i40e_get_cap(struct i40e_hw *hw);
281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
282 static int i40e_pf_setup(struct i40e_pf *pf);
283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
287 bool offset_loaded, uint64_t *offset, uint64_t *stat);
288 static void i40e_stat_update_48(struct i40e_hw *hw,
294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
295 static void i40e_dev_interrupt_handler(void *param);
296 static void i40e_dev_alarm_handler(void *param);
297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
298 uint32_t base, uint32_t num);
299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
305 static int i40e_veb_release(struct i40e_veb *veb);
306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
307 struct i40e_vsi *vsi);
308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
311 struct i40e_macvlan_filter *mv_f,
314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
318 struct rte_eth_rss_conf *rss_conf);
319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
322 struct rte_eth_udp_tunnel *udp_tunnel);
323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
334 static void i40e_configure_registers(struct i40e_hw *hw);
335 static void i40e_hw_init(struct rte_eth_dev *dev);
336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
344 struct rte_eth_mirror_conf *mirror_conf,
345 uint8_t sw_id, uint8_t on);
346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp,
353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp);
355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
369 static int i40e_get_regs(struct rte_eth_dev *dev,
370 struct rte_dev_reg_info *regs);
372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *eeprom);
377 static int i40e_get_module_info(struct rte_eth_dev *dev,
378 struct rte_eth_dev_module_info *modinfo);
379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
380 struct rte_dev_eeprom_info *info);
382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
383 struct ether_addr *mac_addr);
385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
387 static int i40e_ethertype_filter_convert(
388 const struct rte_eth_ethertype_filter *input,
389 struct i40e_ethertype_filter *filter);
390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
391 struct i40e_ethertype_filter *filter);
393 static int i40e_tunnel_filter_convert(
394 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
397 struct i40e_tunnel_filter *tunnel_filter);
398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
402 static void i40e_filter_restore(struct i40e_pf *pf);
403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
405 int i40e_logtype_init;
406 int i40e_logtype_driver;
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
413 ETH_I40E_USE_LATEST_VEC,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
632 struct rte_pci_device *pci_dev)
634 char name[RTE_ETH_NAME_MAX_LEN];
635 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
638 if (pci_dev->device.devargs) {
639 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
645 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
646 sizeof(struct i40e_adapter),
647 eth_dev_pci_specific_init, pci_dev,
648 eth_i40e_dev_init, NULL);
650 if (retval || eth_da.nb_representor_ports < 1)
653 /* probe VF representor ports */
654 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
655 pci_dev->device.name);
657 if (pf_ethdev == NULL)
660 for (i = 0; i < eth_da.nb_representor_ports; i++) {
661 struct i40e_vf_representor representor = {
662 .vf_id = eth_da.representor_ports[i],
663 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
664 pf_ethdev->data->dev_private)->switch_domain_id,
665 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
666 pf_ethdev->data->dev_private)
669 /* representor port net_bdf_port */
670 snprintf(name, sizeof(name), "net_%s_representor_%d",
671 pci_dev->device.name, eth_da.representor_ports[i]);
673 retval = rte_eth_dev_create(&pci_dev->device, name,
674 sizeof(struct i40e_vf_representor), NULL, NULL,
675 i40e_vf_representor_init, &representor);
678 PMD_DRV_LOG(ERR, "failed to create i40e vf "
679 "representor %s.", name);
685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
687 struct rte_eth_dev *ethdev;
689 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
697 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
700 static struct rte_pci_driver rte_i40e_pmd = {
701 .id_table = pci_id_i40e_map,
702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
703 RTE_PCI_DRV_IOVA_AS_VA,
704 .probe = eth_i40e_pci_probe,
705 .remove = eth_i40e_pci_remove,
709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
712 uint32_t ori_reg_val;
713 struct rte_eth_dev *dev;
715 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
716 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
717 i40e_write_rx_ctl(hw, reg_addr, reg_val);
718 if (ori_reg_val != reg_val)
720 "i40e device %s changed global register [0x%08x]."
721 " original: 0x%08x, new: 0x%08x",
722 dev->device->name, reg_addr, ori_reg_val, reg_val);
725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
729 #ifndef I40E_GLQF_ORT
730 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
732 #ifndef I40E_GLQF_PIT
733 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
735 #ifndef I40E_GLQF_L3_MAP
736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
742 * Initialize registers for parsing packet type of QinQ
743 * This should be removed from code once proper
744 * configuration API is added to avoid configuration conflicts
745 * between ports of the same device.
747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
751 static inline void i40e_config_automask(struct i40e_pf *pf)
753 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
756 /* INTENA flag is not auto-cleared for interrupt */
757 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
758 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
759 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
761 /* If support multi-driver, PF will use INT0. */
762 if (!pf->support_multi_driver)
763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
765 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
768 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
771 * Add a ethertype filter to drop all flow control frames transmitted
775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
783 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
784 I40E_FLOW_CONTROL_ETHERTYPE, flags,
785 pf->main_vsi_seid, 0,
789 "Failed to add filter to drop flow control frames from VSIs.");
793 floating_veb_list_handler(__rte_unused const char *key,
794 const char *floating_veb_value,
798 unsigned int count = 0;
801 bool *vf_floating_veb = opaque;
803 while (isblank(*floating_veb_value))
804 floating_veb_value++;
806 /* Reset floating VEB configuration for VFs */
807 for (idx = 0; idx < I40E_MAX_VF; idx++)
808 vf_floating_veb[idx] = false;
812 while (isblank(*floating_veb_value))
813 floating_veb_value++;
814 if (*floating_veb_value == '\0')
817 idx = strtoul(floating_veb_value, &end, 10);
818 if (errno || end == NULL)
820 while (isblank(*end))
824 } else if ((*end == ';') || (*end == '\0')) {
826 if (min == I40E_MAX_VF)
828 if (max >= I40E_MAX_VF)
829 max = I40E_MAX_VF - 1;
830 for (idx = min; idx <= max; idx++) {
831 vf_floating_veb[idx] = true;
838 floating_veb_value = end + 1;
839 } while (*end != '\0');
848 config_vf_floating_veb(struct rte_devargs *devargs,
849 uint16_t floating_veb,
850 bool *vf_floating_veb)
852 struct rte_kvargs *kvlist;
854 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
858 /* All the VFs attach to the floating VEB by default
859 * when the floating VEB is enabled.
861 for (i = 0; i < I40E_MAX_VF; i++)
862 vf_floating_veb[i] = true;
867 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
871 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
872 rte_kvargs_free(kvlist);
875 /* When the floating_veb_list parameter exists, all the VFs
876 * will attach to the legacy VEB firstly, then configure VFs
877 * to the floating VEB according to the floating_veb_list.
879 if (rte_kvargs_process(kvlist, floating_veb_list,
880 floating_veb_list_handler,
881 vf_floating_veb) < 0) {
882 rte_kvargs_free(kvlist);
885 rte_kvargs_free(kvlist);
889 i40e_check_floating_handler(__rte_unused const char *key,
891 __rte_unused void *opaque)
893 if (strcmp(value, "1"))
900 is_floating_veb_supported(struct rte_devargs *devargs)
902 struct rte_kvargs *kvlist;
903 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
908 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
912 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
913 rte_kvargs_free(kvlist);
916 /* Floating VEB is enabled when there's key-value:
917 * enable_floating_veb=1
919 if (rte_kvargs_process(kvlist, floating_veb_key,
920 i40e_check_floating_handler, NULL) < 0) {
921 rte_kvargs_free(kvlist);
924 rte_kvargs_free(kvlist);
930 config_floating_veb(struct rte_eth_dev *dev)
932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
938 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
940 is_floating_veb_supported(pci_dev->device.devargs);
941 config_vf_floating_veb(pci_dev->device.devargs,
943 pf->floating_veb_list);
945 pf->floating_veb = false;
949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
957 char ethertype_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters ethertype_hash_params = {
961 .name = ethertype_hash_name,
962 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
963 .key_len = sizeof(struct i40e_ethertype_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize ethertype filter rule list and hash */
970 TAILQ_INIT(ðertype_rule->ethertype_list);
971 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
972 "ethertype_%s", dev->device->name);
973 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
974 if (!ethertype_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
978 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
979 sizeof(struct i40e_ethertype_filter *) *
980 I40E_MAX_ETHERTYPE_FILTER_NUM,
982 if (!ethertype_rule->hash_map) {
984 "Failed to allocate memory for ethertype hash map!");
986 goto err_ethertype_hash_map_alloc;
991 err_ethertype_hash_map_alloc:
992 rte_hash_free(ethertype_rule->hash_table);
998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters tunnel_hash_params = {
1006 .name = tunnel_hash_name,
1007 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize tunnel filter rule list and hash */
1015 TAILQ_INIT(&tunnel_rule->tunnel_list);
1016 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017 "tunnel_%s", dev->device->name);
1018 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019 if (!tunnel_rule->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024 sizeof(struct i40e_tunnel_filter *) *
1025 I40E_MAX_TUNNEL_FILTER_NUM,
1027 if (!tunnel_rule->hash_map) {
1029 "Failed to allocate memory for tunnel hash map!");
1031 goto err_tunnel_hash_map_alloc;
1036 err_tunnel_hash_map_alloc:
1037 rte_hash_free(tunnel_rule->hash_table);
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046 struct i40e_fdir_info *fdir_info = &pf->fdir;
1047 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 struct rte_hash_parameters fdir_hash_params = {
1051 .name = fdir_hash_name,
1052 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053 .key_len = sizeof(struct i40e_fdir_input),
1054 .hash_func = rte_hash_crc,
1055 .hash_func_init_val = 0,
1056 .socket_id = rte_socket_id(),
1059 /* Initialize flow director filter rule list and hash */
1060 TAILQ_INIT(&fdir_info->fdir_list);
1061 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062 "fdir_%s", dev->device->name);
1063 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064 if (!fdir_info->hash_table) {
1065 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069 sizeof(struct i40e_fdir_filter *) *
1070 I40E_MAX_FDIR_FILTER_NUM,
1072 if (!fdir_info->hash_map) {
1074 "Failed to allocate memory for fdir hash map!");
1076 goto err_fdir_hash_map_alloc;
1080 err_fdir_hash_map_alloc:
1081 rte_hash_free(fdir_info->hash_table);
1087 i40e_init_customized_info(struct i40e_pf *pf)
1091 /* Initialize customized pctype */
1092 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093 pf->customized_pctype[i].index = i;
1094 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095 pf->customized_pctype[i].valid = false;
1098 pf->gtp_support = false;
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106 struct i40e_queue_regions *info = &pf->queue_region;
1109 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1112 memset(info, 0, sizeof(struct i40e_queue_regions));
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1121 unsigned long support_multi_driver;
1124 pf = (struct i40e_pf *)opaque;
1127 support_multi_driver = strtoul(value, &end, 10);
1128 if (errno != 0 || end == value || *end != 0) {
1129 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1133 if (support_multi_driver == 1 || support_multi_driver == 0)
1134 pf->support_multi_driver = (bool)support_multi_driver;
1136 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137 "enable global configuration by default."
1138 ETH_I40E_SUPPORT_MULTI_DRIVER);
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146 struct rte_kvargs *kvlist;
1149 /* Enable global configuration by default */
1150 pf->support_multi_driver = false;
1152 if (!dev->device->devargs)
1155 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1159 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160 if (!kvargs_count) {
1161 rte_kvargs_free(kvlist);
1165 if (kvargs_count > 1)
1166 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167 "the first invalid or last valid one is used !",
1168 ETH_I40E_SUPPORT_MULTI_DRIVER);
1170 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171 i40e_parse_multi_drv_handler, pf) < 0) {
1172 rte_kvargs_free(kvlist);
1176 rte_kvargs_free(kvlist);
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182 uint32_t reg_addr, uint64_t reg_val,
1183 struct i40e_asq_cmd_details *cmd_details)
1185 uint64_t ori_reg_val;
1186 struct rte_eth_dev *dev;
1189 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190 if (ret != I40E_SUCCESS) {
1192 "Fail to debug read from 0x%08x",
1196 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1198 if (ori_reg_val != reg_val)
1199 PMD_DRV_LOG(WARNING,
1200 "i40e device %s changed global register [0x%08x]."
1201 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202 dev->device->name, reg_addr, ori_reg_val, reg_val);
1204 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1212 struct i40e_adapter *ad;
1215 ad = (struct i40e_adapter *)opaque;
1217 use_latest_vec = atoi(value);
1219 if (use_latest_vec != 0 && use_latest_vec != 1)
1220 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1222 ad->use_latest_vec = (uint8_t)use_latest_vec;
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1230 struct i40e_adapter *ad =
1231 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232 struct rte_kvargs *kvlist;
1235 ad->use_latest_vec = false;
1237 if (!dev->device->devargs)
1240 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1244 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245 if (!kvargs_count) {
1246 rte_kvargs_free(kvlist);
1250 if (kvargs_count > 1)
1251 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252 "the first invalid or last valid one is used !",
1253 ETH_I40E_USE_LATEST_VEC);
1255 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256 i40e_parse_latest_vec_handler, ad) < 0) {
1257 rte_kvargs_free(kvlist);
1261 rte_kvargs_free(kvlist);
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1270 struct rte_pci_device *pci_dev;
1271 struct rte_intr_handle *intr_handle;
1272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 struct i40e_vsi *vsi;
1277 uint8_t aq_fail = 0;
1279 PMD_INIT_FUNC_TRACE();
1281 dev->dev_ops = &i40e_eth_dev_ops;
1282 dev->rx_pkt_burst = i40e_recv_pkts;
1283 dev->tx_pkt_burst = i40e_xmit_pkts;
1284 dev->tx_pkt_prepare = i40e_prep_pkts;
1286 /* for secondary processes, we don't initialise any further as primary
1287 * has already done this work. Only check we don't need a different
1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290 i40e_set_rx_function(dev);
1291 i40e_set_tx_function(dev);
1294 i40e_set_default_ptype_table(dev);
1295 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296 intr_handle = &pci_dev->intr_handle;
1298 rte_eth_copy_pci_info(dev, pci_dev);
1300 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301 pf->adapter->eth_dev = dev;
1302 pf->dev_data = dev->data;
1304 hw->back = I40E_PF_TO_ADAPTER(pf);
1305 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308 "Hardware is not available, as address is NULL");
1312 hw->vendor_id = pci_dev->id.vendor_id;
1313 hw->device_id = pci_dev->id.device_id;
1314 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316 hw->bus.device = pci_dev->addr.devid;
1317 hw->bus.func = pci_dev->addr.function;
1318 hw->adapter_stopped = 0;
1319 hw->adapter_closed = 0;
1322 * Switch Tag value should not be identical to either the First Tag
1323 * or Second Tag values. So set something other than common Ethertype
1324 * for internal switching.
1326 hw->switch_tag = 0xffff;
1328 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1329 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1330 PMD_INIT_LOG(ERR, "\nERROR: "
1331 "Firmware recovery mode detected. Limiting functionality.\n"
1332 "Refer to the Intel(R) Ethernet Adapters and Devices "
1333 "User Guide for details on firmware recovery mode.");
1337 /* Check if need to support multi-driver */
1338 i40e_support_multi_driver(dev);
1339 /* Check if users want the latest supported vec path */
1340 i40e_use_latest_vec(dev);
1342 /* Make sure all is clean before doing PF reset */
1345 /* Reset here to make sure all is clean for each PF */
1346 ret = i40e_pf_reset(hw);
1348 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1352 /* Initialize the shared code (base driver) */
1353 ret = i40e_init_shared_code(hw);
1355 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1359 /* Initialize the parameters for adminq */
1360 i40e_init_adminq_parameter(hw);
1361 ret = i40e_init_adminq(hw);
1362 if (ret != I40E_SUCCESS) {
1363 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1366 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1367 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1368 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1369 ((hw->nvm.version >> 12) & 0xf),
1370 ((hw->nvm.version >> 4) & 0xff),
1371 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1373 /* Initialize the hardware */
1376 i40e_config_automask(pf);
1378 i40e_set_default_pctype_table(dev);
1381 * To work around the NVM issue, initialize registers
1382 * for packet type of QinQ by software.
1383 * It should be removed once issues are fixed in NVM.
1385 if (!pf->support_multi_driver)
1386 i40e_GLQF_reg_init(hw);
1388 /* Initialize the input set for filters (hash and fd) to default value */
1389 i40e_filter_input_set_init(pf);
1391 /* initialise the L3_MAP register */
1392 if (!pf->support_multi_driver) {
1393 ret = i40e_aq_debug_write_global_register(hw,
1394 I40E_GLQF_L3_MAP(40),
1397 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1400 "Global register 0x%08x is changed with 0x28",
1401 I40E_GLQF_L3_MAP(40));
1404 /* Need the special FW version to support floating VEB */
1405 config_floating_veb(dev);
1406 /* Clear PXE mode */
1407 i40e_clear_pxe_mode(hw);
1408 i40e_dev_sync_phy_type(hw);
1411 * On X710, performance number is far from the expectation on recent
1412 * firmware versions. The fix for this issue may not be integrated in
1413 * the following firmware version. So the workaround in software driver
1414 * is needed. It needs to modify the initial values of 3 internal only
1415 * registers. Note that the workaround can be removed when it is fixed
1416 * in firmware in the future.
1418 i40e_configure_registers(hw);
1420 /* Get hw capabilities */
1421 ret = i40e_get_cap(hw);
1422 if (ret != I40E_SUCCESS) {
1423 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1424 goto err_get_capabilities;
1427 /* Initialize parameters for PF */
1428 ret = i40e_pf_parameter_init(dev);
1430 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1431 goto err_parameter_init;
1434 /* Initialize the queue management */
1435 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1437 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1438 goto err_qp_pool_init;
1440 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1441 hw->func_caps.num_msix_vectors - 1);
1443 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1444 goto err_msix_pool_init;
1447 /* Initialize lan hmc */
1448 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1449 hw->func_caps.num_rx_qp, 0, 0);
1450 if (ret != I40E_SUCCESS) {
1451 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1452 goto err_init_lan_hmc;
1455 /* Configure lan hmc */
1456 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1457 if (ret != I40E_SUCCESS) {
1458 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1459 goto err_configure_lan_hmc;
1462 /* Get and check the mac address */
1463 i40e_get_mac_addr(hw, hw->mac.addr);
1464 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1465 PMD_INIT_LOG(ERR, "mac address is not valid");
1467 goto err_get_mac_addr;
1469 /* Copy the permanent MAC address */
1470 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1471 (struct ether_addr *) hw->mac.perm_addr);
1473 /* Disable flow control */
1474 hw->fc.requested_mode = I40E_FC_NONE;
1475 i40e_set_fc(hw, &aq_fail, TRUE);
1477 /* Set the global registers with default ether type value */
1478 if (!pf->support_multi_driver) {
1479 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1481 if (ret != I40E_SUCCESS) {
1483 "Failed to set the default outer "
1485 goto err_setup_pf_switch;
1489 /* PF setup, which includes VSI setup */
1490 ret = i40e_pf_setup(pf);
1492 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1493 goto err_setup_pf_switch;
1496 /* reset all stats of the device, including pf and main vsi */
1497 i40e_dev_stats_reset(dev);
1501 /* Disable double vlan by default */
1502 i40e_vsi_config_double_vlan(vsi, FALSE);
1504 /* Disable S-TAG identification when floating_veb is disabled */
1505 if (!pf->floating_veb) {
1506 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1507 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1508 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1509 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1513 if (!vsi->max_macaddrs)
1514 len = ETHER_ADDR_LEN;
1516 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1518 /* Should be after VSI initialized */
1519 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1520 if (!dev->data->mac_addrs) {
1522 "Failed to allocated memory for storing mac address");
1525 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1526 &dev->data->mac_addrs[0]);
1528 /* Init dcb to sw mode by default */
1529 ret = i40e_dcb_init_configure(dev, TRUE);
1530 if (ret != I40E_SUCCESS) {
1531 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1532 pf->flags &= ~I40E_FLAG_DCB;
1534 /* Update HW struct after DCB configuration */
1537 /* initialize pf host driver to setup SRIOV resource if applicable */
1538 i40e_pf_host_init(dev);
1540 /* register callback func to eal lib */
1541 rte_intr_callback_register(intr_handle,
1542 i40e_dev_interrupt_handler, dev);
1544 /* configure and enable device interrupt */
1545 i40e_pf_config_irq0(hw, TRUE);
1546 i40e_pf_enable_irq0(hw);
1548 /* enable uio intr after callback register */
1549 rte_intr_enable(intr_handle);
1551 /* By default disable flexible payload in global configuration */
1552 if (!pf->support_multi_driver)
1553 i40e_flex_payload_reg_set_default(hw);
1556 * Add an ethertype filter to drop all flow control frames transmitted
1557 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1560 i40e_add_tx_flow_control_drop_filter(pf);
1562 /* Set the max frame size to 0x2600 by default,
1563 * in case other drivers changed the default value.
1565 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1567 /* initialize mirror rule list */
1568 TAILQ_INIT(&pf->mirror_list);
1570 /* initialize Traffic Manager configuration */
1571 i40e_tm_conf_init(dev);
1573 /* Initialize customized information */
1574 i40e_init_customized_info(pf);
1576 ret = i40e_init_ethtype_filter_list(dev);
1578 goto err_init_ethtype_filter_list;
1579 ret = i40e_init_tunnel_filter_list(dev);
1581 goto err_init_tunnel_filter_list;
1582 ret = i40e_init_fdir_filter_list(dev);
1584 goto err_init_fdir_filter_list;
1586 /* initialize queue region configuration */
1587 i40e_init_queue_region_conf(dev);
1589 /* initialize rss configuration from rte_flow */
1590 memset(&pf->rss_info, 0,
1591 sizeof(struct i40e_rte_flow_rss_conf));
1595 err_init_fdir_filter_list:
1596 rte_free(pf->tunnel.hash_table);
1597 rte_free(pf->tunnel.hash_map);
1598 err_init_tunnel_filter_list:
1599 rte_free(pf->ethertype.hash_table);
1600 rte_free(pf->ethertype.hash_map);
1601 err_init_ethtype_filter_list:
1602 rte_free(dev->data->mac_addrs);
1604 i40e_vsi_release(pf->main_vsi);
1605 err_setup_pf_switch:
1607 err_configure_lan_hmc:
1608 (void)i40e_shutdown_lan_hmc(hw);
1610 i40e_res_pool_destroy(&pf->msix_pool);
1612 i40e_res_pool_destroy(&pf->qp_pool);
1615 err_get_capabilities:
1616 (void)i40e_shutdown_adminq(hw);
1622 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1624 struct i40e_ethertype_filter *p_ethertype;
1625 struct i40e_ethertype_rule *ethertype_rule;
1627 ethertype_rule = &pf->ethertype;
1628 /* Remove all ethertype filter rules and hash */
1629 if (ethertype_rule->hash_map)
1630 rte_free(ethertype_rule->hash_map);
1631 if (ethertype_rule->hash_table)
1632 rte_hash_free(ethertype_rule->hash_table);
1634 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1635 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1636 p_ethertype, rules);
1637 rte_free(p_ethertype);
1642 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1644 struct i40e_tunnel_filter *p_tunnel;
1645 struct i40e_tunnel_rule *tunnel_rule;
1647 tunnel_rule = &pf->tunnel;
1648 /* Remove all tunnel director rules and hash */
1649 if (tunnel_rule->hash_map)
1650 rte_free(tunnel_rule->hash_map);
1651 if (tunnel_rule->hash_table)
1652 rte_hash_free(tunnel_rule->hash_table);
1654 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1655 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1661 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1663 struct i40e_fdir_filter *p_fdir;
1664 struct i40e_fdir_info *fdir_info;
1666 fdir_info = &pf->fdir;
1667 /* Remove all flow director rules and hash */
1668 if (fdir_info->hash_map)
1669 rte_free(fdir_info->hash_map);
1670 if (fdir_info->hash_table)
1671 rte_hash_free(fdir_info->hash_table);
1673 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1674 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1679 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1682 * Disable by default flexible payload
1683 * for corresponding L2/L3/L4 layers.
1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1687 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1691 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1694 struct rte_pci_device *pci_dev;
1695 struct rte_intr_handle *intr_handle;
1697 struct i40e_filter_control_settings settings;
1698 struct rte_flow *p_flow;
1700 uint8_t aq_fail = 0;
1703 PMD_INIT_FUNC_TRACE();
1705 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1708 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1709 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1711 intr_handle = &pci_dev->intr_handle;
1713 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1715 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1717 if (hw->adapter_closed == 0)
1718 i40e_dev_close(dev);
1720 dev->dev_ops = NULL;
1721 dev->rx_pkt_burst = NULL;
1722 dev->tx_pkt_burst = NULL;
1724 /* Clear PXE mode */
1725 i40e_clear_pxe_mode(hw);
1727 /* Unconfigure filter control */
1728 memset(&settings, 0, sizeof(settings));
1729 ret = i40e_set_filter_control(hw, &settings);
1731 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1734 /* Disable flow control */
1735 hw->fc.requested_mode = I40E_FC_NONE;
1736 i40e_set_fc(hw, &aq_fail, TRUE);
1738 /* uninitialize pf host driver */
1739 i40e_pf_host_uninit(dev);
1741 /* disable uio intr before callback unregister */
1742 rte_intr_disable(intr_handle);
1744 /* unregister callback func to eal lib */
1746 ret = rte_intr_callback_unregister(intr_handle,
1747 i40e_dev_interrupt_handler, dev);
1750 } else if (ret != -EAGAIN) {
1752 "intr callback unregister failed: %d",
1756 i40e_msec_delay(500);
1757 } while (retries++ < 5);
1759 i40e_rm_ethtype_filter_list(pf);
1760 i40e_rm_tunnel_filter_list(pf);
1761 i40e_rm_fdir_filter_list(pf);
1763 /* Remove all flows */
1764 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1765 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1769 /* Remove all Traffic Manager configuration */
1770 i40e_tm_conf_uninit(dev);
1776 i40e_dev_configure(struct rte_eth_dev *dev)
1778 struct i40e_adapter *ad =
1779 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1785 ret = i40e_dev_sync_phy_type(hw);
1789 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1790 * bulk allocation or vector Rx preconditions we will reset it.
1792 ad->rx_bulk_alloc_allowed = true;
1793 ad->rx_vec_allowed = true;
1794 ad->tx_simple_allowed = true;
1795 ad->tx_vec_allowed = true;
1797 /* Only legacy filter API needs the following fdir config. So when the
1798 * legacy filter API is deprecated, the following codes should also be
1801 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1802 ret = i40e_fdir_setup(pf);
1803 if (ret != I40E_SUCCESS) {
1804 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1807 ret = i40e_fdir_configure(dev);
1809 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1813 i40e_fdir_teardown(pf);
1815 ret = i40e_dev_init_vlan(dev);
1820 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1821 * RSS setting have different requirements.
1822 * General PMD driver call sequence are NIC init, configure,
1823 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1824 * will try to lookup the VSI that specific queue belongs to if VMDQ
1825 * applicable. So, VMDQ setting has to be done before
1826 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1827 * For RSS setting, it will try to calculate actual configured RX queue
1828 * number, which will be available after rx_queue_setup(). dev_start()
1829 * function is good to place RSS setup.
1831 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1832 ret = i40e_vmdq_setup(dev);
1837 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1838 ret = i40e_dcb_setup(dev);
1840 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1845 TAILQ_INIT(&pf->flow_list);
1850 /* need to release vmdq resource if exists */
1851 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1852 i40e_vsi_release(pf->vmdq[i].vsi);
1853 pf->vmdq[i].vsi = NULL;
1858 /* Need to release fdir resource if exists.
1859 * Only legacy filter API needs the following fdir config. So when the
1860 * legacy filter API is deprecated, the following code should also be
1863 i40e_fdir_teardown(pf);
1868 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1870 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1871 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1872 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1873 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1874 uint16_t msix_vect = vsi->msix_intr;
1877 for (i = 0; i < vsi->nb_qps; i++) {
1878 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1879 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1883 if (vsi->type != I40E_VSI_SRIOV) {
1884 if (!rte_intr_allow_others(intr_handle)) {
1885 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1886 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1888 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1891 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1892 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1894 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1899 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1900 vsi->user_param + (msix_vect - 1);
1902 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1903 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1905 I40E_WRITE_FLUSH(hw);
1909 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1910 int base_queue, int nb_queue,
1915 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1916 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1918 /* Bind all RX queues to allocated MSIX interrupt */
1919 for (i = 0; i < nb_queue; i++) {
1920 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1921 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1922 ((base_queue + i + 1) <<
1923 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1924 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1925 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1927 if (i == nb_queue - 1)
1928 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1929 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1932 /* Write first RX queue to Link list register as the head element */
1933 if (vsi->type != I40E_VSI_SRIOV) {
1935 i40e_calc_itr_interval(1, pf->support_multi_driver);
1937 if (msix_vect == I40E_MISC_VEC_ID) {
1938 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1940 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1942 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1944 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1947 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1949 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1951 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1953 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1960 if (msix_vect == I40E_MISC_VEC_ID) {
1962 I40E_VPINT_LNKLST0(vsi->user_param),
1964 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1966 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1968 /* num_msix_vectors_vf needs to minus irq0 */
1969 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1970 vsi->user_param + (msix_vect - 1);
1972 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1974 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1976 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1980 I40E_WRITE_FLUSH(hw);
1984 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1986 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1987 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1990 uint16_t msix_vect = vsi->msix_intr;
1991 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1992 uint16_t queue_idx = 0;
1996 for (i = 0; i < vsi->nb_qps; i++) {
1997 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1998 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2001 /* VF bind interrupt */
2002 if (vsi->type == I40E_VSI_SRIOV) {
2003 __vsi_queues_bind_intr(vsi, msix_vect,
2004 vsi->base_queue, vsi->nb_qps,
2009 /* PF & VMDq bind interrupt */
2010 if (rte_intr_dp_is_en(intr_handle)) {
2011 if (vsi->type == I40E_VSI_MAIN) {
2014 } else if (vsi->type == I40E_VSI_VMDQ2) {
2015 struct i40e_vsi *main_vsi =
2016 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2017 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2022 for (i = 0; i < vsi->nb_used_qps; i++) {
2024 if (!rte_intr_allow_others(intr_handle))
2025 /* allow to share MISC_VEC_ID */
2026 msix_vect = I40E_MISC_VEC_ID;
2028 /* no enough msix_vect, map all to one */
2029 __vsi_queues_bind_intr(vsi, msix_vect,
2030 vsi->base_queue + i,
2031 vsi->nb_used_qps - i,
2033 for (; !!record && i < vsi->nb_used_qps; i++)
2034 intr_handle->intr_vec[queue_idx + i] =
2038 /* 1:1 queue/msix_vect mapping */
2039 __vsi_queues_bind_intr(vsi, msix_vect,
2040 vsi->base_queue + i, 1,
2043 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2051 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2053 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2054 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2055 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2057 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2058 uint16_t msix_intr, i;
2060 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2061 for (i = 0; i < vsi->nb_msix; i++) {
2062 msix_intr = vsi->msix_intr + i;
2063 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2064 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2065 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2066 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2069 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2070 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2071 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2072 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2074 I40E_WRITE_FLUSH(hw);
2078 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2080 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2081 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2082 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2083 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2084 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2085 uint16_t msix_intr, i;
2087 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2088 for (i = 0; i < vsi->nb_msix; i++) {
2089 msix_intr = vsi->msix_intr + i;
2090 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2091 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2094 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2095 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2097 I40E_WRITE_FLUSH(hw);
2100 static inline uint8_t
2101 i40e_parse_link_speeds(uint16_t link_speeds)
2103 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2105 if (link_speeds & ETH_LINK_SPEED_40G)
2106 link_speed |= I40E_LINK_SPEED_40GB;
2107 if (link_speeds & ETH_LINK_SPEED_25G)
2108 link_speed |= I40E_LINK_SPEED_25GB;
2109 if (link_speeds & ETH_LINK_SPEED_20G)
2110 link_speed |= I40E_LINK_SPEED_20GB;
2111 if (link_speeds & ETH_LINK_SPEED_10G)
2112 link_speed |= I40E_LINK_SPEED_10GB;
2113 if (link_speeds & ETH_LINK_SPEED_1G)
2114 link_speed |= I40E_LINK_SPEED_1GB;
2115 if (link_speeds & ETH_LINK_SPEED_100M)
2116 link_speed |= I40E_LINK_SPEED_100MB;
2122 i40e_phy_conf_link(struct i40e_hw *hw,
2124 uint8_t force_speed,
2127 enum i40e_status_code status;
2128 struct i40e_aq_get_phy_abilities_resp phy_ab;
2129 struct i40e_aq_set_phy_config phy_conf;
2130 enum i40e_aq_phy_type cnt;
2131 uint8_t avail_speed;
2132 uint32_t phy_type_mask = 0;
2134 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2135 I40E_AQ_PHY_FLAG_PAUSE_RX |
2136 I40E_AQ_PHY_FLAG_PAUSE_RX |
2137 I40E_AQ_PHY_FLAG_LOW_POWER;
2140 /* To get phy capabilities of available speeds. */
2141 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2144 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2148 avail_speed = phy_ab.link_speed;
2150 /* To get the current phy config. */
2151 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2154 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2159 /* If link needs to go up and it is in autoneg mode the speed is OK,
2160 * no need to set up again.
2162 if (is_up && phy_ab.phy_type != 0 &&
2163 abilities & I40E_AQ_PHY_AN_ENABLED &&
2164 phy_ab.link_speed != 0)
2165 return I40E_SUCCESS;
2167 memset(&phy_conf, 0, sizeof(phy_conf));
2169 /* bits 0-2 use the values from get_phy_abilities_resp */
2171 abilities |= phy_ab.abilities & mask;
2173 phy_conf.abilities = abilities;
2175 /* If link needs to go up, but the force speed is not supported,
2176 * Warn users and config the default available speeds.
2178 if (is_up && !(force_speed & avail_speed)) {
2179 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2180 phy_conf.link_speed = avail_speed;
2182 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2185 /* PHY type mask needs to include each type except PHY type extension */
2186 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2187 phy_type_mask |= 1 << cnt;
2189 /* use get_phy_abilities_resp value for the rest */
2190 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2191 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2192 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2193 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2194 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2195 phy_conf.eee_capability = phy_ab.eee_capability;
2196 phy_conf.eeer = phy_ab.eeer_val;
2197 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2199 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2200 phy_ab.abilities, phy_ab.link_speed);
2201 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2202 phy_conf.abilities, phy_conf.link_speed);
2204 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2208 return I40E_SUCCESS;
2212 i40e_apply_link_speed(struct rte_eth_dev *dev)
2215 uint8_t abilities = 0;
2216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217 struct rte_eth_conf *conf = &dev->data->dev_conf;
2219 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2220 conf->link_speeds = ETH_LINK_SPEED_40G |
2221 ETH_LINK_SPEED_25G |
2222 ETH_LINK_SPEED_20G |
2223 ETH_LINK_SPEED_10G |
2225 ETH_LINK_SPEED_100M;
2227 speed = i40e_parse_link_speeds(conf->link_speeds);
2228 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2229 I40E_AQ_PHY_AN_ENABLED |
2230 I40E_AQ_PHY_LINK_ENABLED;
2232 return i40e_phy_conf_link(hw, abilities, speed, true);
2236 i40e_dev_start(struct rte_eth_dev *dev)
2238 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240 struct i40e_vsi *main_vsi = pf->main_vsi;
2242 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2243 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2244 uint32_t intr_vector = 0;
2245 struct i40e_vsi *vsi;
2247 hw->adapter_stopped = 0;
2249 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2251 "Invalid link_speeds for port %u, autonegotiation disabled",
2252 dev->data->port_id);
2256 rte_intr_disable(intr_handle);
2258 if ((rte_intr_cap_multiple(intr_handle) ||
2259 !RTE_ETH_DEV_SRIOV(dev).active) &&
2260 dev->data->dev_conf.intr_conf.rxq != 0) {
2261 intr_vector = dev->data->nb_rx_queues;
2262 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2267 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2268 intr_handle->intr_vec =
2269 rte_zmalloc("intr_vec",
2270 dev->data->nb_rx_queues * sizeof(int),
2272 if (!intr_handle->intr_vec) {
2274 "Failed to allocate %d rx_queues intr_vec",
2275 dev->data->nb_rx_queues);
2280 /* Initialize VSI */
2281 ret = i40e_dev_rxtx_init(pf);
2282 if (ret != I40E_SUCCESS) {
2283 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2287 /* Map queues with MSIX interrupt */
2288 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2289 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2290 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2291 i40e_vsi_enable_queues_intr(main_vsi);
2293 /* Map VMDQ VSI queues with MSIX interrupt */
2294 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2295 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2296 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2297 I40E_ITR_INDEX_DEFAULT);
2298 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2301 /* enable FDIR MSIX interrupt */
2302 if (pf->fdir.fdir_vsi) {
2303 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2304 I40E_ITR_INDEX_NONE);
2305 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2308 /* Enable all queues which have been configured */
2309 ret = i40e_dev_switch_queues(pf, TRUE);
2310 if (ret != I40E_SUCCESS) {
2311 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2315 /* Enable receiving broadcast packets */
2316 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2317 if (ret != I40E_SUCCESS)
2318 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2320 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2321 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2323 if (ret != I40E_SUCCESS)
2324 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2327 /* Enable the VLAN promiscuous mode. */
2329 for (i = 0; i < pf->vf_num; i++) {
2330 vsi = pf->vfs[i].vsi;
2331 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2336 /* Enable mac loopback mode */
2337 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2338 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2339 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2340 if (ret != I40E_SUCCESS) {
2341 PMD_DRV_LOG(ERR, "fail to set loopback link");
2346 /* Apply link configure */
2347 ret = i40e_apply_link_speed(dev);
2348 if (I40E_SUCCESS != ret) {
2349 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2353 if (!rte_intr_allow_others(intr_handle)) {
2354 rte_intr_callback_unregister(intr_handle,
2355 i40e_dev_interrupt_handler,
2357 /* configure and enable device interrupt */
2358 i40e_pf_config_irq0(hw, FALSE);
2359 i40e_pf_enable_irq0(hw);
2361 if (dev->data->dev_conf.intr_conf.lsc != 0)
2363 "lsc won't enable because of no intr multiplex");
2365 ret = i40e_aq_set_phy_int_mask(hw,
2366 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2367 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2368 I40E_AQ_EVENT_MEDIA_NA), NULL);
2369 if (ret != I40E_SUCCESS)
2370 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2372 /* Call get_link_info aq commond to enable/disable LSE */
2373 i40e_dev_link_update(dev, 0);
2376 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2377 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2378 i40e_dev_alarm_handler, dev);
2380 /* enable uio intr after callback register */
2381 rte_intr_enable(intr_handle);
2384 i40e_filter_restore(pf);
2386 if (pf->tm_conf.root && !pf->tm_conf.committed)
2387 PMD_DRV_LOG(WARNING,
2388 "please call hierarchy_commit() "
2389 "before starting the port");
2391 return I40E_SUCCESS;
2394 i40e_dev_switch_queues(pf, FALSE);
2395 i40e_dev_clear_queues(dev);
2401 i40e_dev_stop(struct rte_eth_dev *dev)
2403 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2404 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405 struct i40e_vsi *main_vsi = pf->main_vsi;
2406 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2407 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2410 if (hw->adapter_stopped == 1)
2413 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2414 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2415 rte_intr_enable(intr_handle);
2418 /* Disable all queues */
2419 i40e_dev_switch_queues(pf, FALSE);
2421 /* un-map queues with interrupt registers */
2422 i40e_vsi_disable_queues_intr(main_vsi);
2423 i40e_vsi_queues_unbind_intr(main_vsi);
2425 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2426 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2427 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2430 if (pf->fdir.fdir_vsi) {
2431 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2432 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2434 /* Clear all queues and release memory */
2435 i40e_dev_clear_queues(dev);
2438 i40e_dev_set_link_down(dev);
2440 if (!rte_intr_allow_others(intr_handle))
2441 /* resume to the default handler */
2442 rte_intr_callback_register(intr_handle,
2443 i40e_dev_interrupt_handler,
2446 /* Clean datapath event and queue/vec mapping */
2447 rte_intr_efd_disable(intr_handle);
2448 if (intr_handle->intr_vec) {
2449 rte_free(intr_handle->intr_vec);
2450 intr_handle->intr_vec = NULL;
2453 /* reset hierarchy commit */
2454 pf->tm_conf.committed = false;
2456 hw->adapter_stopped = 1;
2458 pf->adapter->rss_reta_updated = 0;
2462 i40e_dev_close(struct rte_eth_dev *dev)
2464 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2465 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2467 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2468 struct i40e_mirror_rule *p_mirror;
2473 PMD_INIT_FUNC_TRACE();
2477 /* Remove all mirror rules */
2478 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2479 ret = i40e_aq_del_mirror_rule(hw,
2480 pf->main_vsi->veb->seid,
2481 p_mirror->rule_type,
2483 p_mirror->num_entries,
2486 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2487 "status = %d, aq_err = %d.", ret,
2488 hw->aq.asq_last_status);
2490 /* remove mirror software resource anyway */
2491 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2493 pf->nb_mirror_rule--;
2496 i40e_dev_free_queues(dev);
2498 /* Disable interrupt */
2499 i40e_pf_disable_irq0(hw);
2500 rte_intr_disable(intr_handle);
2503 * Only legacy filter API needs the following fdir config. So when the
2504 * legacy filter API is deprecated, the following code should also be
2507 i40e_fdir_teardown(pf);
2509 /* shutdown and destroy the HMC */
2510 i40e_shutdown_lan_hmc(hw);
2512 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2513 i40e_vsi_release(pf->vmdq[i].vsi);
2514 pf->vmdq[i].vsi = NULL;
2519 /* release all the existing VSIs and VEBs */
2520 i40e_vsi_release(pf->main_vsi);
2522 /* shutdown the adminq */
2523 i40e_aq_queue_shutdown(hw, true);
2524 i40e_shutdown_adminq(hw);
2526 i40e_res_pool_destroy(&pf->qp_pool);
2527 i40e_res_pool_destroy(&pf->msix_pool);
2529 /* Disable flexible payload in global configuration */
2530 if (!pf->support_multi_driver)
2531 i40e_flex_payload_reg_set_default(hw);
2533 /* force a PF reset to clean anything leftover */
2534 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2535 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2536 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2537 I40E_WRITE_FLUSH(hw);
2539 hw->adapter_closed = 1;
2543 * Reset PF device only to re-initialize resources in PMD layer
2546 i40e_dev_reset(struct rte_eth_dev *dev)
2550 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2551 * its VF to make them align with it. The detailed notification
2552 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2553 * To avoid unexpected behavior in VF, currently reset of PF with
2554 * SR-IOV activation is not supported. It might be supported later.
2556 if (dev->data->sriov.active)
2559 ret = eth_i40e_dev_uninit(dev);
2563 ret = eth_i40e_dev_init(dev, NULL);
2569 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2571 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2572 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573 struct i40e_vsi *vsi = pf->main_vsi;
2576 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2578 if (status != I40E_SUCCESS)
2579 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2581 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2583 if (status != I40E_SUCCESS)
2584 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2589 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2591 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2592 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593 struct i40e_vsi *vsi = pf->main_vsi;
2596 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2598 if (status != I40E_SUCCESS)
2599 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2601 /* must remain in all_multicast mode */
2602 if (dev->data->all_multicast == 1)
2605 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2607 if (status != I40E_SUCCESS)
2608 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2612 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 struct i40e_vsi *vsi = pf->main_vsi;
2619 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2620 if (ret != I40E_SUCCESS)
2621 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2625 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2627 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2628 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629 struct i40e_vsi *vsi = pf->main_vsi;
2632 if (dev->data->promiscuous == 1)
2633 return; /* must remain in all_multicast mode */
2635 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2636 vsi->seid, FALSE, NULL);
2637 if (ret != I40E_SUCCESS)
2638 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2642 * Set device link up.
2645 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2647 /* re-apply link speed setting */
2648 return i40e_apply_link_speed(dev);
2652 * Set device link down.
2655 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2657 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2658 uint8_t abilities = 0;
2659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2662 return i40e_phy_conf_link(hw, abilities, speed, false);
2665 static __rte_always_inline void
2666 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2668 /* Link status registers and values*/
2669 #define I40E_PRTMAC_LINKSTA 0x001E2420
2670 #define I40E_REG_LINK_UP 0x40000080
2671 #define I40E_PRTMAC_MACC 0x001E24E0
2672 #define I40E_REG_MACC_25GB 0x00020000
2673 #define I40E_REG_SPEED_MASK 0x38000000
2674 #define I40E_REG_SPEED_100MB 0x00000000
2675 #define I40E_REG_SPEED_1GB 0x08000000
2676 #define I40E_REG_SPEED_10GB 0x10000000
2677 #define I40E_REG_SPEED_20GB 0x20000000
2678 #define I40E_REG_SPEED_25_40GB 0x18000000
2679 uint32_t link_speed;
2682 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2683 link_speed = reg_val & I40E_REG_SPEED_MASK;
2684 reg_val &= I40E_REG_LINK_UP;
2685 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2687 if (unlikely(link->link_status == 0))
2690 /* Parse the link status */
2691 switch (link_speed) {
2692 case I40E_REG_SPEED_100MB:
2693 link->link_speed = ETH_SPEED_NUM_100M;
2695 case I40E_REG_SPEED_1GB:
2696 link->link_speed = ETH_SPEED_NUM_1G;
2698 case I40E_REG_SPEED_10GB:
2699 link->link_speed = ETH_SPEED_NUM_10G;
2701 case I40E_REG_SPEED_20GB:
2702 link->link_speed = ETH_SPEED_NUM_20G;
2704 case I40E_REG_SPEED_25_40GB:
2705 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2707 if (reg_val & I40E_REG_MACC_25GB)
2708 link->link_speed = ETH_SPEED_NUM_25G;
2710 link->link_speed = ETH_SPEED_NUM_40G;
2714 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2719 static __rte_always_inline void
2720 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2721 bool enable_lse, int wait_to_complete)
2723 #define CHECK_INTERVAL 100 /* 100ms */
2724 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2725 uint32_t rep_cnt = MAX_REPEAT_TIME;
2726 struct i40e_link_status link_status;
2729 memset(&link_status, 0, sizeof(link_status));
2732 memset(&link_status, 0, sizeof(link_status));
2734 /* Get link status information from hardware */
2735 status = i40e_aq_get_link_info(hw, enable_lse,
2736 &link_status, NULL);
2737 if (unlikely(status != I40E_SUCCESS)) {
2738 link->link_speed = ETH_SPEED_NUM_100M;
2739 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2740 PMD_DRV_LOG(ERR, "Failed to get link info");
2744 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2745 if (!wait_to_complete || link->link_status)
2748 rte_delay_ms(CHECK_INTERVAL);
2749 } while (--rep_cnt);
2751 /* Parse the link status */
2752 switch (link_status.link_speed) {
2753 case I40E_LINK_SPEED_100MB:
2754 link->link_speed = ETH_SPEED_NUM_100M;
2756 case I40E_LINK_SPEED_1GB:
2757 link->link_speed = ETH_SPEED_NUM_1G;
2759 case I40E_LINK_SPEED_10GB:
2760 link->link_speed = ETH_SPEED_NUM_10G;
2762 case I40E_LINK_SPEED_20GB:
2763 link->link_speed = ETH_SPEED_NUM_20G;
2765 case I40E_LINK_SPEED_25GB:
2766 link->link_speed = ETH_SPEED_NUM_25G;
2768 case I40E_LINK_SPEED_40GB:
2769 link->link_speed = ETH_SPEED_NUM_40G;
2772 link->link_speed = ETH_SPEED_NUM_100M;
2778 i40e_dev_link_update(struct rte_eth_dev *dev,
2779 int wait_to_complete)
2781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782 struct rte_eth_link link;
2783 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2786 memset(&link, 0, sizeof(link));
2788 /* i40e uses full duplex only */
2789 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2790 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2791 ETH_LINK_SPEED_FIXED);
2793 if (!wait_to_complete && !enable_lse)
2794 update_link_reg(hw, &link);
2796 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2798 ret = rte_eth_linkstatus_set(dev, &link);
2799 i40e_notify_all_vfs_link_status(dev);
2804 /* Get all the statistics of a VSI */
2806 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2808 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2809 struct i40e_eth_stats *nes = &vsi->eth_stats;
2810 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2811 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2813 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2814 vsi->offset_loaded, &oes->rx_bytes,
2816 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2817 vsi->offset_loaded, &oes->rx_unicast,
2819 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2820 vsi->offset_loaded, &oes->rx_multicast,
2821 &nes->rx_multicast);
2822 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2823 vsi->offset_loaded, &oes->rx_broadcast,
2824 &nes->rx_broadcast);
2825 /* exclude CRC bytes */
2826 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2827 nes->rx_broadcast) * ETHER_CRC_LEN;
2829 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2830 &oes->rx_discards, &nes->rx_discards);
2831 /* GLV_REPC not supported */
2832 /* GLV_RMPC not supported */
2833 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2834 &oes->rx_unknown_protocol,
2835 &nes->rx_unknown_protocol);
2836 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2837 vsi->offset_loaded, &oes->tx_bytes,
2839 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2840 vsi->offset_loaded, &oes->tx_unicast,
2842 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2843 vsi->offset_loaded, &oes->tx_multicast,
2844 &nes->tx_multicast);
2845 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2846 vsi->offset_loaded, &oes->tx_broadcast,
2847 &nes->tx_broadcast);
2848 /* GLV_TDPC not supported */
2849 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2850 &oes->tx_errors, &nes->tx_errors);
2851 vsi->offset_loaded = true;
2853 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2855 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2856 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2857 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2858 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2859 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2860 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2861 nes->rx_unknown_protocol);
2862 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2863 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2864 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2865 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2866 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2867 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2868 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2873 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2876 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2877 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2879 /* Get rx/tx bytes of internal transfer packets */
2880 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2881 I40E_GLV_GORCL(hw->port),
2883 &pf->internal_stats_offset.rx_bytes,
2884 &pf->internal_stats.rx_bytes);
2886 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2887 I40E_GLV_GOTCL(hw->port),
2889 &pf->internal_stats_offset.tx_bytes,
2890 &pf->internal_stats.tx_bytes);
2891 /* Get total internal rx packet count */
2892 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2893 I40E_GLV_UPRCL(hw->port),
2895 &pf->internal_stats_offset.rx_unicast,
2896 &pf->internal_stats.rx_unicast);
2897 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2898 I40E_GLV_MPRCL(hw->port),
2900 &pf->internal_stats_offset.rx_multicast,
2901 &pf->internal_stats.rx_multicast);
2902 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2903 I40E_GLV_BPRCL(hw->port),
2905 &pf->internal_stats_offset.rx_broadcast,
2906 &pf->internal_stats.rx_broadcast);
2907 /* Get total internal tx packet count */
2908 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2909 I40E_GLV_UPTCL(hw->port),
2911 &pf->internal_stats_offset.tx_unicast,
2912 &pf->internal_stats.tx_unicast);
2913 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2914 I40E_GLV_MPTCL(hw->port),
2916 &pf->internal_stats_offset.tx_multicast,
2917 &pf->internal_stats.tx_multicast);
2918 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2919 I40E_GLV_BPTCL(hw->port),
2921 &pf->internal_stats_offset.tx_broadcast,
2922 &pf->internal_stats.tx_broadcast);
2924 /* exclude CRC size */
2925 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2926 pf->internal_stats.rx_multicast +
2927 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2929 /* Get statistics of struct i40e_eth_stats */
2930 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2931 I40E_GLPRT_GORCL(hw->port),
2932 pf->offset_loaded, &os->eth.rx_bytes,
2934 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2935 I40E_GLPRT_UPRCL(hw->port),
2936 pf->offset_loaded, &os->eth.rx_unicast,
2937 &ns->eth.rx_unicast);
2938 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2939 I40E_GLPRT_MPRCL(hw->port),
2940 pf->offset_loaded, &os->eth.rx_multicast,
2941 &ns->eth.rx_multicast);
2942 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2943 I40E_GLPRT_BPRCL(hw->port),
2944 pf->offset_loaded, &os->eth.rx_broadcast,
2945 &ns->eth.rx_broadcast);
2946 /* Workaround: CRC size should not be included in byte statistics,
2947 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2949 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2950 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2952 /* exclude internal rx bytes
2953 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2954 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2956 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2958 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2959 ns->eth.rx_bytes = 0;
2961 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2963 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2964 ns->eth.rx_unicast = 0;
2966 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2968 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2969 ns->eth.rx_multicast = 0;
2971 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2973 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2974 ns->eth.rx_broadcast = 0;
2976 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2978 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2979 pf->offset_loaded, &os->eth.rx_discards,
2980 &ns->eth.rx_discards);
2981 /* GLPRT_REPC not supported */
2982 /* GLPRT_RMPC not supported */
2983 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2985 &os->eth.rx_unknown_protocol,
2986 &ns->eth.rx_unknown_protocol);
2987 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2988 I40E_GLPRT_GOTCL(hw->port),
2989 pf->offset_loaded, &os->eth.tx_bytes,
2991 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2992 I40E_GLPRT_UPTCL(hw->port),
2993 pf->offset_loaded, &os->eth.tx_unicast,
2994 &ns->eth.tx_unicast);
2995 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2996 I40E_GLPRT_MPTCL(hw->port),
2997 pf->offset_loaded, &os->eth.tx_multicast,
2998 &ns->eth.tx_multicast);
2999 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3000 I40E_GLPRT_BPTCL(hw->port),
3001 pf->offset_loaded, &os->eth.tx_broadcast,
3002 &ns->eth.tx_broadcast);
3003 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3004 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3006 /* exclude internal tx bytes
3007 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3008 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3010 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3012 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3013 ns->eth.tx_bytes = 0;
3015 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3017 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3018 ns->eth.tx_unicast = 0;
3020 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3022 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3023 ns->eth.tx_multicast = 0;
3025 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3027 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3028 ns->eth.tx_broadcast = 0;
3030 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3032 /* GLPRT_TEPC not supported */
3034 /* additional port specific stats */
3035 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3036 pf->offset_loaded, &os->tx_dropped_link_down,
3037 &ns->tx_dropped_link_down);
3038 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3039 pf->offset_loaded, &os->crc_errors,
3041 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3042 pf->offset_loaded, &os->illegal_bytes,
3043 &ns->illegal_bytes);
3044 /* GLPRT_ERRBC not supported */
3045 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3046 pf->offset_loaded, &os->mac_local_faults,
3047 &ns->mac_local_faults);
3048 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3049 pf->offset_loaded, &os->mac_remote_faults,
3050 &ns->mac_remote_faults);
3051 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3052 pf->offset_loaded, &os->rx_length_errors,
3053 &ns->rx_length_errors);
3054 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3055 pf->offset_loaded, &os->link_xon_rx,
3057 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3058 pf->offset_loaded, &os->link_xoff_rx,
3060 for (i = 0; i < 8; i++) {
3061 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3063 &os->priority_xon_rx[i],
3064 &ns->priority_xon_rx[i]);
3065 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3067 &os->priority_xoff_rx[i],
3068 &ns->priority_xoff_rx[i]);
3070 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3071 pf->offset_loaded, &os->link_xon_tx,
3073 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3074 pf->offset_loaded, &os->link_xoff_tx,
3076 for (i = 0; i < 8; i++) {
3077 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3079 &os->priority_xon_tx[i],
3080 &ns->priority_xon_tx[i]);
3081 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3083 &os->priority_xoff_tx[i],
3084 &ns->priority_xoff_tx[i]);
3085 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3087 &os->priority_xon_2_xoff[i],
3088 &ns->priority_xon_2_xoff[i]);
3090 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3091 I40E_GLPRT_PRC64L(hw->port),
3092 pf->offset_loaded, &os->rx_size_64,
3094 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3095 I40E_GLPRT_PRC127L(hw->port),
3096 pf->offset_loaded, &os->rx_size_127,
3098 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3099 I40E_GLPRT_PRC255L(hw->port),
3100 pf->offset_loaded, &os->rx_size_255,
3102 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3103 I40E_GLPRT_PRC511L(hw->port),
3104 pf->offset_loaded, &os->rx_size_511,
3106 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3107 I40E_GLPRT_PRC1023L(hw->port),
3108 pf->offset_loaded, &os->rx_size_1023,
3110 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3111 I40E_GLPRT_PRC1522L(hw->port),
3112 pf->offset_loaded, &os->rx_size_1522,
3114 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3115 I40E_GLPRT_PRC9522L(hw->port),
3116 pf->offset_loaded, &os->rx_size_big,
3118 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3119 pf->offset_loaded, &os->rx_undersize,
3121 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3122 pf->offset_loaded, &os->rx_fragments,
3124 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3125 pf->offset_loaded, &os->rx_oversize,
3127 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3128 pf->offset_loaded, &os->rx_jabber,
3130 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3131 I40E_GLPRT_PTC64L(hw->port),
3132 pf->offset_loaded, &os->tx_size_64,
3134 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3135 I40E_GLPRT_PTC127L(hw->port),
3136 pf->offset_loaded, &os->tx_size_127,
3138 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3139 I40E_GLPRT_PTC255L(hw->port),
3140 pf->offset_loaded, &os->tx_size_255,
3142 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3143 I40E_GLPRT_PTC511L(hw->port),
3144 pf->offset_loaded, &os->tx_size_511,
3146 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3147 I40E_GLPRT_PTC1023L(hw->port),
3148 pf->offset_loaded, &os->tx_size_1023,
3150 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3151 I40E_GLPRT_PTC1522L(hw->port),
3152 pf->offset_loaded, &os->tx_size_1522,
3154 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3155 I40E_GLPRT_PTC9522L(hw->port),
3156 pf->offset_loaded, &os->tx_size_big,
3158 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3160 &os->fd_sb_match, &ns->fd_sb_match);
3161 /* GLPRT_MSPDC not supported */
3162 /* GLPRT_XEC not supported */
3164 pf->offset_loaded = true;
3167 i40e_update_vsi_stats(pf->main_vsi);
3170 /* Get all statistics of a port */
3172 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3174 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3175 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3179 /* call read registers - updates values, now write them to struct */
3180 i40e_read_stats_registers(pf, hw);
3182 stats->ipackets = ns->eth.rx_unicast +
3183 ns->eth.rx_multicast +
3184 ns->eth.rx_broadcast -
3185 ns->eth.rx_discards -
3186 pf->main_vsi->eth_stats.rx_discards;
3187 stats->opackets = ns->eth.tx_unicast +
3188 ns->eth.tx_multicast +
3189 ns->eth.tx_broadcast;
3190 stats->ibytes = ns->eth.rx_bytes;
3191 stats->obytes = ns->eth.tx_bytes;
3192 stats->oerrors = ns->eth.tx_errors +
3193 pf->main_vsi->eth_stats.tx_errors;
3196 stats->imissed = ns->eth.rx_discards +
3197 pf->main_vsi->eth_stats.rx_discards;
3198 stats->ierrors = ns->crc_errors +
3199 ns->rx_length_errors + ns->rx_undersize +
3200 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3202 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3203 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3204 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3205 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3206 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3207 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3208 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3209 ns->eth.rx_unknown_protocol);
3210 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3211 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3212 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3213 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3214 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3215 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3217 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3218 ns->tx_dropped_link_down);
3219 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3220 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3222 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3223 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3224 ns->mac_local_faults);
3225 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3226 ns->mac_remote_faults);
3227 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3228 ns->rx_length_errors);
3229 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3230 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3231 for (i = 0; i < 8; i++) {
3232 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3233 i, ns->priority_xon_rx[i]);
3234 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3235 i, ns->priority_xoff_rx[i]);
3237 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3238 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3239 for (i = 0; i < 8; i++) {
3240 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3241 i, ns->priority_xon_tx[i]);
3242 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3243 i, ns->priority_xoff_tx[i]);
3244 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3245 i, ns->priority_xon_2_xoff[i]);
3247 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3248 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3249 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3250 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3251 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3252 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3253 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3254 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3255 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3256 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3257 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3258 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3259 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3260 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3261 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3262 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3263 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3264 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3265 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3266 ns->mac_short_packet_dropped);
3267 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3268 ns->checksum_error);
3269 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3270 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3274 /* Reset the statistics */
3276 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281 /* Mark PF and VSI stats to update the offset, aka "reset" */
3282 pf->offset_loaded = false;
3284 pf->main_vsi->offset_loaded = false;
3286 /* read the stats, reading current register values into offset */
3287 i40e_read_stats_registers(pf, hw);
3291 i40e_xstats_calc_num(void)
3293 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3294 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3295 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3298 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3299 struct rte_eth_xstat_name *xstats_names,
3300 __rte_unused unsigned limit)
3305 if (xstats_names == NULL)
3306 return i40e_xstats_calc_num();
3308 /* Note: limit checked in rte_eth_xstats_names() */
3310 /* Get stats from i40e_eth_stats struct */
3311 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3312 snprintf(xstats_names[count].name,
3313 sizeof(xstats_names[count].name),
3314 "%s", rte_i40e_stats_strings[i].name);
3318 /* Get individiual stats from i40e_hw_port struct */
3319 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3320 snprintf(xstats_names[count].name,
3321 sizeof(xstats_names[count].name),
3322 "%s", rte_i40e_hw_port_strings[i].name);
3326 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3327 for (prio = 0; prio < 8; prio++) {
3328 snprintf(xstats_names[count].name,
3329 sizeof(xstats_names[count].name),
3330 "rx_priority%u_%s", prio,
3331 rte_i40e_rxq_prio_strings[i].name);
3336 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3337 for (prio = 0; prio < 8; prio++) {
3338 snprintf(xstats_names[count].name,
3339 sizeof(xstats_names[count].name),
3340 "tx_priority%u_%s", prio,
3341 rte_i40e_txq_prio_strings[i].name);
3349 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3354 unsigned i, count, prio;
3355 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3357 count = i40e_xstats_calc_num();
3361 i40e_read_stats_registers(pf, hw);
3368 /* Get stats from i40e_eth_stats struct */
3369 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3370 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3371 rte_i40e_stats_strings[i].offset);
3372 xstats[count].id = count;
3376 /* Get individiual stats from i40e_hw_port struct */
3377 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3378 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3379 rte_i40e_hw_port_strings[i].offset);
3380 xstats[count].id = count;
3384 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3385 for (prio = 0; prio < 8; prio++) {
3386 xstats[count].value =
3387 *(uint64_t *)(((char *)hw_stats) +
3388 rte_i40e_rxq_prio_strings[i].offset +
3389 (sizeof(uint64_t) * prio));
3390 xstats[count].id = count;
3395 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3396 for (prio = 0; prio < 8; prio++) {
3397 xstats[count].value =
3398 *(uint64_t *)(((char *)hw_stats) +
3399 rte_i40e_txq_prio_strings[i].offset +
3400 (sizeof(uint64_t) * prio));
3401 xstats[count].id = count;
3410 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3411 __rte_unused uint16_t queue_id,
3412 __rte_unused uint8_t stat_idx,
3413 __rte_unused uint8_t is_rx)
3415 PMD_INIT_FUNC_TRACE();
3421 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3423 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3429 full_ver = hw->nvm.oem_ver;
3430 ver = (u8)(full_ver >> 24);
3431 build = (u16)((full_ver >> 8) & 0xffff);
3432 patch = (u8)(full_ver & 0xff);
3434 ret = snprintf(fw_version, fw_size,
3435 "%d.%d%d 0x%08x %d.%d.%d",
3436 ((hw->nvm.version >> 12) & 0xf),
3437 ((hw->nvm.version >> 4) & 0xff),
3438 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3441 ret += 1; /* add the size of '\0' */
3442 if (fw_size < (u32)ret)
3449 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3451 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453 struct i40e_vsi *vsi = pf->main_vsi;
3454 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3456 dev_info->max_rx_queues = vsi->nb_qps;
3457 dev_info->max_tx_queues = vsi->nb_qps;
3458 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3459 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3460 dev_info->max_mac_addrs = vsi->max_macaddrs;
3461 dev_info->max_vfs = pci_dev->max_vfs;
3462 dev_info->rx_queue_offload_capa = 0;
3463 dev_info->rx_offload_capa =
3464 DEV_RX_OFFLOAD_VLAN_STRIP |
3465 DEV_RX_OFFLOAD_QINQ_STRIP |
3466 DEV_RX_OFFLOAD_IPV4_CKSUM |
3467 DEV_RX_OFFLOAD_UDP_CKSUM |
3468 DEV_RX_OFFLOAD_TCP_CKSUM |
3469 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3470 DEV_RX_OFFLOAD_KEEP_CRC |
3471 DEV_RX_OFFLOAD_SCATTER |
3472 DEV_RX_OFFLOAD_VLAN_EXTEND |
3473 DEV_RX_OFFLOAD_VLAN_FILTER |
3474 DEV_RX_OFFLOAD_JUMBO_FRAME;
3476 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3477 dev_info->tx_offload_capa =
3478 DEV_TX_OFFLOAD_VLAN_INSERT |
3479 DEV_TX_OFFLOAD_QINQ_INSERT |
3480 DEV_TX_OFFLOAD_IPV4_CKSUM |
3481 DEV_TX_OFFLOAD_UDP_CKSUM |
3482 DEV_TX_OFFLOAD_TCP_CKSUM |
3483 DEV_TX_OFFLOAD_SCTP_CKSUM |
3484 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3485 DEV_TX_OFFLOAD_TCP_TSO |
3486 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3487 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3488 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3489 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3490 DEV_TX_OFFLOAD_MULTI_SEGS |
3491 dev_info->tx_queue_offload_capa;
3492 dev_info->dev_capa =
3493 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3494 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3496 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3498 dev_info->reta_size = pf->hash_lut_size;
3499 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3501 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3503 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3504 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3505 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3507 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3512 dev_info->default_txconf = (struct rte_eth_txconf) {
3514 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3515 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3516 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3518 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3519 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3523 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3524 .nb_max = I40E_MAX_RING_DESC,
3525 .nb_min = I40E_MIN_RING_DESC,
3526 .nb_align = I40E_ALIGN_RING_DESC,
3529 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3530 .nb_max = I40E_MAX_RING_DESC,
3531 .nb_min = I40E_MIN_RING_DESC,
3532 .nb_align = I40E_ALIGN_RING_DESC,
3533 .nb_seg_max = I40E_TX_MAX_SEG,
3534 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3537 if (pf->flags & I40E_FLAG_VMDQ) {
3538 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3539 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3540 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3541 pf->max_nb_vmdq_vsi;
3542 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3543 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3544 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3547 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3549 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3550 dev_info->default_rxportconf.nb_queues = 2;
3551 dev_info->default_txportconf.nb_queues = 2;
3552 if (dev->data->nb_rx_queues == 1)
3553 dev_info->default_rxportconf.ring_size = 2048;
3555 dev_info->default_rxportconf.ring_size = 1024;
3556 if (dev->data->nb_tx_queues == 1)
3557 dev_info->default_txportconf.ring_size = 1024;
3559 dev_info->default_txportconf.ring_size = 512;
3561 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3563 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3564 dev_info->default_rxportconf.nb_queues = 1;
3565 dev_info->default_txportconf.nb_queues = 1;
3566 dev_info->default_rxportconf.ring_size = 256;
3567 dev_info->default_txportconf.ring_size = 256;
3570 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3571 dev_info->default_rxportconf.nb_queues = 1;
3572 dev_info->default_txportconf.nb_queues = 1;
3573 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3574 dev_info->default_rxportconf.ring_size = 512;
3575 dev_info->default_txportconf.ring_size = 256;
3577 dev_info->default_rxportconf.ring_size = 256;
3578 dev_info->default_txportconf.ring_size = 256;
3581 dev_info->default_rxportconf.burst_size = 32;
3582 dev_info->default_txportconf.burst_size = 32;
3586 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3588 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3589 struct i40e_vsi *vsi = pf->main_vsi;
3590 PMD_INIT_FUNC_TRACE();
3593 return i40e_vsi_add_vlan(vsi, vlan_id);
3595 return i40e_vsi_delete_vlan(vsi, vlan_id);
3599 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3600 enum rte_vlan_type vlan_type,
3601 uint16_t tpid, int qinq)
3603 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3606 uint16_t reg_id = 3;
3610 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3614 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3616 if (ret != I40E_SUCCESS) {
3618 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3623 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3626 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3627 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3628 if (reg_r == reg_w) {
3629 PMD_DRV_LOG(DEBUG, "No need to write");
3633 ret = i40e_aq_debug_write_global_register(hw,
3634 I40E_GL_SWT_L2TAGCTRL(reg_id),
3636 if (ret != I40E_SUCCESS) {
3638 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3643 "Global register 0x%08x is changed with value 0x%08x",
3644 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3650 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3651 enum rte_vlan_type vlan_type,
3654 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3655 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3656 int qinq = dev->data->dev_conf.rxmode.offloads &
3657 DEV_RX_OFFLOAD_VLAN_EXTEND;
3660 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3661 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3662 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3664 "Unsupported vlan type.");
3668 if (pf->support_multi_driver) {
3669 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3673 /* 802.1ad frames ability is added in NVM API 1.7*/
3674 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3676 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3677 hw->first_tag = rte_cpu_to_le_16(tpid);
3678 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3679 hw->second_tag = rte_cpu_to_le_16(tpid);
3681 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3682 hw->second_tag = rte_cpu_to_le_16(tpid);
3684 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3685 if (ret != I40E_SUCCESS) {
3687 "Set switch config failed aq_err: %d",
3688 hw->aq.asq_last_status);
3692 /* If NVM API < 1.7, keep the register setting */
3693 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3700 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3702 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3703 struct i40e_vsi *vsi = pf->main_vsi;
3704 struct rte_eth_rxmode *rxmode;
3706 rxmode = &dev->data->dev_conf.rxmode;
3707 if (mask & ETH_VLAN_FILTER_MASK) {
3708 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3709 i40e_vsi_config_vlan_filter(vsi, TRUE);
3711 i40e_vsi_config_vlan_filter(vsi, FALSE);
3714 if (mask & ETH_VLAN_STRIP_MASK) {
3715 /* Enable or disable VLAN stripping */
3716 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3717 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3719 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3722 if (mask & ETH_VLAN_EXTEND_MASK) {
3723 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3724 i40e_vsi_config_double_vlan(vsi, TRUE);
3725 /* Set global registers with default ethertype. */
3726 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3728 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3732 i40e_vsi_config_double_vlan(vsi, FALSE);
3739 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3740 __rte_unused uint16_t queue,
3741 __rte_unused int on)
3743 PMD_INIT_FUNC_TRACE();
3747 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3749 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3750 struct i40e_vsi *vsi = pf->main_vsi;
3751 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3752 struct i40e_vsi_vlan_pvid_info info;
3754 memset(&info, 0, sizeof(info));
3757 info.config.pvid = pvid;
3759 info.config.reject.tagged =
3760 data->dev_conf.txmode.hw_vlan_reject_tagged;
3761 info.config.reject.untagged =
3762 data->dev_conf.txmode.hw_vlan_reject_untagged;
3765 return i40e_vsi_vlan_pvid_set(vsi, &info);
3769 i40e_dev_led_on(struct rte_eth_dev *dev)
3771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3772 uint32_t mode = i40e_led_get(hw);
3775 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3781 i40e_dev_led_off(struct rte_eth_dev *dev)
3783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784 uint32_t mode = i40e_led_get(hw);
3787 i40e_led_set(hw, 0, false);
3793 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3795 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3798 fc_conf->pause_time = pf->fc_conf.pause_time;
3800 /* read out from register, in case they are modified by other port */
3801 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3802 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3803 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3804 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3806 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3807 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3809 /* Return current mode according to actual setting*/
3810 switch (hw->fc.current_mode) {
3812 fc_conf->mode = RTE_FC_FULL;
3814 case I40E_FC_TX_PAUSE:
3815 fc_conf->mode = RTE_FC_TX_PAUSE;
3817 case I40E_FC_RX_PAUSE:
3818 fc_conf->mode = RTE_FC_RX_PAUSE;
3822 fc_conf->mode = RTE_FC_NONE;
3829 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3831 uint32_t mflcn_reg, fctrl_reg, reg;
3832 uint32_t max_high_water;
3833 uint8_t i, aq_failure;
3837 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3838 [RTE_FC_NONE] = I40E_FC_NONE,
3839 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3840 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3841 [RTE_FC_FULL] = I40E_FC_FULL
3844 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3846 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3847 if ((fc_conf->high_water > max_high_water) ||
3848 (fc_conf->high_water < fc_conf->low_water)) {
3850 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3855 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3857 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3859 pf->fc_conf.pause_time = fc_conf->pause_time;
3860 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3861 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3863 PMD_INIT_FUNC_TRACE();
3865 /* All the link flow control related enable/disable register
3866 * configuration is handle by the F/W
3868 err = i40e_set_fc(hw, &aq_failure, true);
3872 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3873 /* Configure flow control refresh threshold,
3874 * the value for stat_tx_pause_refresh_timer[8]
3875 * is used for global pause operation.
3879 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3880 pf->fc_conf.pause_time);
3882 /* configure the timer value included in transmitted pause
3884 * the value for stat_tx_pause_quanta[8] is used for global
3887 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3888 pf->fc_conf.pause_time);
3890 fctrl_reg = I40E_READ_REG(hw,
3891 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3893 if (fc_conf->mac_ctrl_frame_fwd != 0)
3894 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3896 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3898 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3901 /* Configure pause time (2 TCs per register) */
3902 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3903 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3904 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3906 /* Configure flow control refresh threshold value */
3907 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3908 pf->fc_conf.pause_time / 2);
3910 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3912 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3913 *depending on configuration
3915 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3916 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3917 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3919 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3920 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3923 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3926 if (!pf->support_multi_driver) {
3927 /* config water marker both based on the packets and bytes */
3928 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3929 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3930 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3931 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3932 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3933 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3934 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3935 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3937 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3938 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3942 "Water marker configuration is not supported.");
3945 I40E_WRITE_FLUSH(hw);
3951 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3952 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3954 PMD_INIT_FUNC_TRACE();
3959 /* Add a MAC address, and update filters */
3961 i40e_macaddr_add(struct rte_eth_dev *dev,
3962 struct ether_addr *mac_addr,
3963 __rte_unused uint32_t index,
3966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3967 struct i40e_mac_filter_info mac_filter;
3968 struct i40e_vsi *vsi;
3969 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3972 /* If VMDQ not enabled or configured, return */
3973 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3974 !pf->nb_cfg_vmdq_vsi)) {
3975 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3976 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3981 if (pool > pf->nb_cfg_vmdq_vsi) {
3982 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3983 pool, pf->nb_cfg_vmdq_vsi);
3987 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3988 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3989 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3991 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3996 vsi = pf->vmdq[pool - 1].vsi;
3998 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3999 if (ret != I40E_SUCCESS) {
4000 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4006 /* Remove a MAC address, and update filters */
4008 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4010 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4011 struct i40e_vsi *vsi;
4012 struct rte_eth_dev_data *data = dev->data;
4013 struct ether_addr *macaddr;
4018 macaddr = &(data->mac_addrs[index]);
4020 pool_sel = dev->data->mac_pool_sel[index];
4022 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4023 if (pool_sel & (1ULL << i)) {
4027 /* No VMDQ pool enabled or configured */
4028 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4029 (i > pf->nb_cfg_vmdq_vsi)) {
4031 "No VMDQ pool enabled/configured");
4034 vsi = pf->vmdq[i - 1].vsi;
4036 ret = i40e_vsi_delete_mac(vsi, macaddr);
4039 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4046 /* Set perfect match or hash match of MAC and VLAN for a VF */
4048 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4049 struct rte_eth_mac_filter *filter,
4053 struct i40e_mac_filter_info mac_filter;
4054 struct ether_addr old_mac;
4055 struct ether_addr *new_mac;
4056 struct i40e_pf_vf *vf = NULL;
4061 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4064 hw = I40E_PF_TO_HW(pf);
4066 if (filter == NULL) {
4067 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4071 new_mac = &filter->mac_addr;
4073 if (is_zero_ether_addr(new_mac)) {
4074 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4078 vf_id = filter->dst_id;
4080 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4081 PMD_DRV_LOG(ERR, "Invalid argument.");
4084 vf = &pf->vfs[vf_id];
4086 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4087 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4092 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4093 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4095 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4098 mac_filter.filter_type = filter->filter_type;
4099 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4100 if (ret != I40E_SUCCESS) {
4101 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4104 ether_addr_copy(new_mac, &pf->dev_addr);
4106 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4108 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4109 if (ret != I40E_SUCCESS) {
4110 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4114 /* Clear device address as it has been removed */
4115 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4116 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4122 /* MAC filter handle */
4124 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4127 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4128 struct rte_eth_mac_filter *filter;
4129 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4130 int ret = I40E_NOT_SUPPORTED;
4132 filter = (struct rte_eth_mac_filter *)(arg);
4134 switch (filter_op) {
4135 case RTE_ETH_FILTER_NOP:
4138 case RTE_ETH_FILTER_ADD:
4139 i40e_pf_disable_irq0(hw);
4141 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4142 i40e_pf_enable_irq0(hw);
4144 case RTE_ETH_FILTER_DELETE:
4145 i40e_pf_disable_irq0(hw);
4147 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4148 i40e_pf_enable_irq0(hw);
4151 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4152 ret = I40E_ERR_PARAM;
4160 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4162 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4163 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4170 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4171 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4174 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4178 uint32_t *lut_dw = (uint32_t *)lut;
4179 uint16_t i, lut_size_dw = lut_size / 4;
4181 if (vsi->type == I40E_VSI_SRIOV) {
4182 for (i = 0; i <= lut_size_dw; i++) {
4183 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4184 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4187 for (i = 0; i < lut_size_dw; i++)
4188 lut_dw[i] = I40E_READ_REG(hw,
4197 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4206 pf = I40E_VSI_TO_PF(vsi);
4207 hw = I40E_VSI_TO_HW(vsi);
4209 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4210 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4213 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4217 uint32_t *lut_dw = (uint32_t *)lut;
4218 uint16_t i, lut_size_dw = lut_size / 4;
4220 if (vsi->type == I40E_VSI_SRIOV) {
4221 for (i = 0; i < lut_size_dw; i++)
4224 I40E_VFQF_HLUT1(i, vsi->user_param),
4227 for (i = 0; i < lut_size_dw; i++)
4228 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4231 I40E_WRITE_FLUSH(hw);
4238 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4239 struct rte_eth_rss_reta_entry64 *reta_conf,
4242 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4243 uint16_t i, lut_size = pf->hash_lut_size;
4244 uint16_t idx, shift;
4248 if (reta_size != lut_size ||
4249 reta_size > ETH_RSS_RETA_SIZE_512) {
4251 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4252 reta_size, lut_size);
4256 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4258 PMD_DRV_LOG(ERR, "No memory can be allocated");
4261 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4264 for (i = 0; i < reta_size; i++) {
4265 idx = i / RTE_RETA_GROUP_SIZE;
4266 shift = i % RTE_RETA_GROUP_SIZE;
4267 if (reta_conf[idx].mask & (1ULL << shift))
4268 lut[i] = reta_conf[idx].reta[shift];
4270 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4272 pf->adapter->rss_reta_updated = 1;
4281 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4282 struct rte_eth_rss_reta_entry64 *reta_conf,
4285 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4286 uint16_t i, lut_size = pf->hash_lut_size;
4287 uint16_t idx, shift;
4291 if (reta_size != lut_size ||
4292 reta_size > ETH_RSS_RETA_SIZE_512) {
4294 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4295 reta_size, lut_size);
4299 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4301 PMD_DRV_LOG(ERR, "No memory can be allocated");
4305 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4308 for (i = 0; i < reta_size; i++) {
4309 idx = i / RTE_RETA_GROUP_SIZE;
4310 shift = i % RTE_RETA_GROUP_SIZE;
4311 if (reta_conf[idx].mask & (1ULL << shift))
4312 reta_conf[idx].reta[shift] = lut[i];
4322 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4323 * @hw: pointer to the HW structure
4324 * @mem: pointer to mem struct to fill out
4325 * @size: size of memory requested
4326 * @alignment: what to align the allocation to
4328 enum i40e_status_code
4329 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4330 struct i40e_dma_mem *mem,
4334 const struct rte_memzone *mz = NULL;
4335 char z_name[RTE_MEMZONE_NAMESIZE];
4338 return I40E_ERR_PARAM;
4340 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4341 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4342 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4344 return I40E_ERR_NO_MEMORY;
4349 mem->zone = (const void *)mz;
4351 "memzone %s allocated with physical address: %"PRIu64,
4354 return I40E_SUCCESS;
4358 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4359 * @hw: pointer to the HW structure
4360 * @mem: ptr to mem struct to free
4362 enum i40e_status_code
4363 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4364 struct i40e_dma_mem *mem)
4367 return I40E_ERR_PARAM;
4370 "memzone %s to be freed with physical address: %"PRIu64,
4371 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4372 rte_memzone_free((const struct rte_memzone *)mem->zone);
4377 return I40E_SUCCESS;
4381 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4382 * @hw: pointer to the HW structure
4383 * @mem: pointer to mem struct to fill out
4384 * @size: size of memory requested
4386 enum i40e_status_code
4387 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4388 struct i40e_virt_mem *mem,
4392 return I40E_ERR_PARAM;
4395 mem->va = rte_zmalloc("i40e", size, 0);
4398 return I40E_SUCCESS;
4400 return I40E_ERR_NO_MEMORY;
4404 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4405 * @hw: pointer to the HW structure
4406 * @mem: pointer to mem struct to free
4408 enum i40e_status_code
4409 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4410 struct i40e_virt_mem *mem)
4413 return I40E_ERR_PARAM;
4418 return I40E_SUCCESS;
4422 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4424 rte_spinlock_init(&sp->spinlock);
4428 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4430 rte_spinlock_lock(&sp->spinlock);
4434 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4436 rte_spinlock_unlock(&sp->spinlock);
4440 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4446 * Get the hardware capabilities, which will be parsed
4447 * and saved into struct i40e_hw.
4450 i40e_get_cap(struct i40e_hw *hw)
4452 struct i40e_aqc_list_capabilities_element_resp *buf;
4453 uint16_t len, size = 0;
4456 /* Calculate a huge enough buff for saving response data temporarily */
4457 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4458 I40E_MAX_CAP_ELE_NUM;
4459 buf = rte_zmalloc("i40e", len, 0);
4461 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4462 return I40E_ERR_NO_MEMORY;
4465 /* Get, parse the capabilities and save it to hw */
4466 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4467 i40e_aqc_opc_list_func_capabilities, NULL);
4468 if (ret != I40E_SUCCESS)
4469 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4471 /* Free the temporary buffer after being used */
4477 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4479 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4487 pf = (struct i40e_pf *)opaque;
4491 num = strtoul(value, &end, 0);
4492 if (errno != 0 || end == value || *end != 0) {
4493 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4494 "kept the value = %hu", value, pf->vf_nb_qp_max);
4498 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4499 pf->vf_nb_qp_max = (uint16_t)num;
4501 /* here return 0 to make next valid same argument work */
4502 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4503 "power of 2 and equal or less than 16 !, Now it is "
4504 "kept the value = %hu", num, pf->vf_nb_qp_max);
4509 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4511 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4512 struct rte_kvargs *kvlist;
4515 /* set default queue number per VF as 4 */
4516 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4518 if (dev->device->devargs == NULL)
4521 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4525 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4526 if (!kvargs_count) {
4527 rte_kvargs_free(kvlist);
4531 if (kvargs_count > 1)
4532 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4533 "the first invalid or last valid one is used !",
4534 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4536 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4537 i40e_pf_parse_vf_queue_number_handler, pf);
4539 rte_kvargs_free(kvlist);
4545 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4548 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4549 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4550 uint16_t qp_count = 0, vsi_count = 0;
4552 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4553 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4557 i40e_pf_config_vf_rxq_number(dev);
4559 /* Add the parameter init for LFC */
4560 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4561 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4562 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4564 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4565 pf->max_num_vsi = hw->func_caps.num_vsis;
4566 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4567 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4569 /* FDir queue/VSI allocation */
4570 pf->fdir_qp_offset = 0;
4571 if (hw->func_caps.fd) {
4572 pf->flags |= I40E_FLAG_FDIR;
4573 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4575 pf->fdir_nb_qps = 0;
4577 qp_count += pf->fdir_nb_qps;
4580 /* LAN queue/VSI allocation */
4581 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4582 if (!hw->func_caps.rss) {
4585 pf->flags |= I40E_FLAG_RSS;
4586 if (hw->mac.type == I40E_MAC_X722)
4587 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4588 pf->lan_nb_qps = pf->lan_nb_qp_max;
4590 qp_count += pf->lan_nb_qps;
4593 /* VF queue/VSI allocation */
4594 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4595 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4596 pf->flags |= I40E_FLAG_SRIOV;
4597 pf->vf_nb_qps = pf->vf_nb_qp_max;
4598 pf->vf_num = pci_dev->max_vfs;
4600 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4601 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4606 qp_count += pf->vf_nb_qps * pf->vf_num;
4607 vsi_count += pf->vf_num;
4609 /* VMDq queue/VSI allocation */
4610 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4611 pf->vmdq_nb_qps = 0;
4612 pf->max_nb_vmdq_vsi = 0;
4613 if (hw->func_caps.vmdq) {
4614 if (qp_count < hw->func_caps.num_tx_qp &&
4615 vsi_count < hw->func_caps.num_vsis) {
4616 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4617 qp_count) / pf->vmdq_nb_qp_max;
4619 /* Limit the maximum number of VMDq vsi to the maximum
4620 * ethdev can support
4622 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4623 hw->func_caps.num_vsis - vsi_count);
4624 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4626 if (pf->max_nb_vmdq_vsi) {
4627 pf->flags |= I40E_FLAG_VMDQ;
4628 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4630 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4631 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4632 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4635 "No enough queues left for VMDq");
4638 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4641 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4642 vsi_count += pf->max_nb_vmdq_vsi;
4644 if (hw->func_caps.dcb)
4645 pf->flags |= I40E_FLAG_DCB;
4647 if (qp_count > hw->func_caps.num_tx_qp) {
4649 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4650 qp_count, hw->func_caps.num_tx_qp);
4653 if (vsi_count > hw->func_caps.num_vsis) {
4655 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4656 vsi_count, hw->func_caps.num_vsis);
4664 i40e_pf_get_switch_config(struct i40e_pf *pf)
4666 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4667 struct i40e_aqc_get_switch_config_resp *switch_config;
4668 struct i40e_aqc_switch_config_element_resp *element;
4669 uint16_t start_seid = 0, num_reported;
4672 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4673 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4674 if (!switch_config) {
4675 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4679 /* Get the switch configurations */
4680 ret = i40e_aq_get_switch_config(hw, switch_config,
4681 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4682 if (ret != I40E_SUCCESS) {
4683 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4686 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4687 if (num_reported != 1) { /* The number should be 1 */
4688 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4692 /* Parse the switch configuration elements */
4693 element = &(switch_config->element[0]);
4694 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4695 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4696 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4698 PMD_DRV_LOG(INFO, "Unknown element type");
4701 rte_free(switch_config);
4707 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4710 struct pool_entry *entry;
4712 if (pool == NULL || num == 0)
4715 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4716 if (entry == NULL) {
4717 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4721 /* queue heap initialize */
4722 pool->num_free = num;
4723 pool->num_alloc = 0;
4725 LIST_INIT(&pool->alloc_list);
4726 LIST_INIT(&pool->free_list);
4728 /* Initialize element */
4732 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4737 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4739 struct pool_entry *entry, *next_entry;
4744 for (entry = LIST_FIRST(&pool->alloc_list);
4745 entry && (next_entry = LIST_NEXT(entry, next), 1);
4746 entry = next_entry) {
4747 LIST_REMOVE(entry, next);
4751 for (entry = LIST_FIRST(&pool->free_list);
4752 entry && (next_entry = LIST_NEXT(entry, next), 1);
4753 entry = next_entry) {
4754 LIST_REMOVE(entry, next);
4759 pool->num_alloc = 0;
4761 LIST_INIT(&pool->alloc_list);
4762 LIST_INIT(&pool->free_list);
4766 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4769 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4770 uint32_t pool_offset;
4774 PMD_DRV_LOG(ERR, "Invalid parameter");
4778 pool_offset = base - pool->base;
4779 /* Lookup in alloc list */
4780 LIST_FOREACH(entry, &pool->alloc_list, next) {
4781 if (entry->base == pool_offset) {
4782 valid_entry = entry;
4783 LIST_REMOVE(entry, next);
4788 /* Not find, return */
4789 if (valid_entry == NULL) {
4790 PMD_DRV_LOG(ERR, "Failed to find entry");
4795 * Found it, move it to free list and try to merge.
4796 * In order to make merge easier, always sort it by qbase.
4797 * Find adjacent prev and last entries.
4800 LIST_FOREACH(entry, &pool->free_list, next) {
4801 if (entry->base > valid_entry->base) {
4809 /* Try to merge with next one*/
4811 /* Merge with next one */
4812 if (valid_entry->base + valid_entry->len == next->base) {
4813 next->base = valid_entry->base;
4814 next->len += valid_entry->len;
4815 rte_free(valid_entry);
4822 /* Merge with previous one */
4823 if (prev->base + prev->len == valid_entry->base) {
4824 prev->len += valid_entry->len;
4825 /* If it merge with next one, remove next node */
4827 LIST_REMOVE(valid_entry, next);
4828 rte_free(valid_entry);
4830 rte_free(valid_entry);
4836 /* Not find any entry to merge, insert */
4839 LIST_INSERT_AFTER(prev, valid_entry, next);
4840 else if (next != NULL)
4841 LIST_INSERT_BEFORE(next, valid_entry, next);
4842 else /* It's empty list, insert to head */
4843 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4846 pool->num_free += valid_entry->len;
4847 pool->num_alloc -= valid_entry->len;
4853 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4856 struct pool_entry *entry, *valid_entry;
4858 if (pool == NULL || num == 0) {
4859 PMD_DRV_LOG(ERR, "Invalid parameter");
4863 if (pool->num_free < num) {
4864 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4865 num, pool->num_free);
4870 /* Lookup in free list and find most fit one */
4871 LIST_FOREACH(entry, &pool->free_list, next) {
4872 if (entry->len >= num) {
4874 if (entry->len == num) {
4875 valid_entry = entry;
4878 if (valid_entry == NULL || valid_entry->len > entry->len)
4879 valid_entry = entry;
4883 /* Not find one to satisfy the request, return */
4884 if (valid_entry == NULL) {
4885 PMD_DRV_LOG(ERR, "No valid entry found");
4889 * The entry have equal queue number as requested,
4890 * remove it from alloc_list.
4892 if (valid_entry->len == num) {
4893 LIST_REMOVE(valid_entry, next);
4896 * The entry have more numbers than requested,
4897 * create a new entry for alloc_list and minus its
4898 * queue base and number in free_list.
4900 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4901 if (entry == NULL) {
4903 "Failed to allocate memory for resource pool");
4906 entry->base = valid_entry->base;
4908 valid_entry->base += num;
4909 valid_entry->len -= num;
4910 valid_entry = entry;
4913 /* Insert it into alloc list, not sorted */
4914 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4916 pool->num_free -= valid_entry->len;
4917 pool->num_alloc += valid_entry->len;
4919 return valid_entry->base + pool->base;
4923 * bitmap_is_subset - Check whether src2 is subset of src1
4926 bitmap_is_subset(uint8_t src1, uint8_t src2)
4928 return !((src1 ^ src2) & src2);
4931 static enum i40e_status_code
4932 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4934 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4936 /* If DCB is not supported, only default TC is supported */
4937 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4938 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4939 return I40E_NOT_SUPPORTED;
4942 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4944 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4945 hw->func_caps.enabled_tcmap, enabled_tcmap);
4946 return I40E_NOT_SUPPORTED;
4948 return I40E_SUCCESS;
4952 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4953 struct i40e_vsi_vlan_pvid_info *info)
4956 struct i40e_vsi_context ctxt;
4957 uint8_t vlan_flags = 0;
4960 if (vsi == NULL || info == NULL) {
4961 PMD_DRV_LOG(ERR, "invalid parameters");
4962 return I40E_ERR_PARAM;
4966 vsi->info.pvid = info->config.pvid;
4968 * If insert pvid is enabled, only tagged pkts are
4969 * allowed to be sent out.
4971 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4972 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4975 if (info->config.reject.tagged == 0)
4976 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4978 if (info->config.reject.untagged == 0)
4979 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4981 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4982 I40E_AQ_VSI_PVLAN_MODE_MASK);
4983 vsi->info.port_vlan_flags |= vlan_flags;
4984 vsi->info.valid_sections =
4985 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4986 memset(&ctxt, 0, sizeof(ctxt));
4987 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4988 ctxt.seid = vsi->seid;
4990 hw = I40E_VSI_TO_HW(vsi);
4991 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4992 if (ret != I40E_SUCCESS)
4993 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4999 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5001 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5003 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5005 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5006 if (ret != I40E_SUCCESS)
5010 PMD_DRV_LOG(ERR, "seid not valid");
5014 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5015 tc_bw_data.tc_valid_bits = enabled_tcmap;
5016 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5017 tc_bw_data.tc_bw_credits[i] =
5018 (enabled_tcmap & (1 << i)) ? 1 : 0;
5020 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5021 if (ret != I40E_SUCCESS) {
5022 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5026 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5027 sizeof(vsi->info.qs_handle));
5028 return I40E_SUCCESS;
5031 static enum i40e_status_code
5032 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5033 struct i40e_aqc_vsi_properties_data *info,
5034 uint8_t enabled_tcmap)
5036 enum i40e_status_code ret;
5037 int i, total_tc = 0;
5038 uint16_t qpnum_per_tc, bsf, qp_idx;
5040 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5041 if (ret != I40E_SUCCESS)
5044 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5045 if (enabled_tcmap & (1 << i))
5049 vsi->enabled_tc = enabled_tcmap;
5051 /* Number of queues per enabled TC */
5052 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5053 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5054 bsf = rte_bsf32(qpnum_per_tc);
5056 /* Adjust the queue number to actual queues that can be applied */
5057 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5058 vsi->nb_qps = qpnum_per_tc * total_tc;
5061 * Configure TC and queue mapping parameters, for enabled TC,
5062 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5063 * default queue will serve it.
5066 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5067 if (vsi->enabled_tc & (1 << i)) {
5068 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5069 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5070 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5071 qp_idx += qpnum_per_tc;
5073 info->tc_mapping[i] = 0;
5076 /* Associate queue number with VSI */
5077 if (vsi->type == I40E_VSI_SRIOV) {
5078 info->mapping_flags |=
5079 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5080 for (i = 0; i < vsi->nb_qps; i++)
5081 info->queue_mapping[i] =
5082 rte_cpu_to_le_16(vsi->base_queue + i);
5084 info->mapping_flags |=
5085 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5086 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5088 info->valid_sections |=
5089 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5091 return I40E_SUCCESS;
5095 i40e_veb_release(struct i40e_veb *veb)
5097 struct i40e_vsi *vsi;
5103 if (!TAILQ_EMPTY(&veb->head)) {
5104 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5107 /* associate_vsi field is NULL for floating VEB */
5108 if (veb->associate_vsi != NULL) {
5109 vsi = veb->associate_vsi;
5110 hw = I40E_VSI_TO_HW(vsi);
5112 vsi->uplink_seid = veb->uplink_seid;
5115 veb->associate_pf->main_vsi->floating_veb = NULL;
5116 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5119 i40e_aq_delete_element(hw, veb->seid, NULL);
5121 return I40E_SUCCESS;
5125 static struct i40e_veb *
5126 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5128 struct i40e_veb *veb;
5134 "veb setup failed, associated PF shouldn't null");
5137 hw = I40E_PF_TO_HW(pf);
5139 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5141 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5145 veb->associate_vsi = vsi;
5146 veb->associate_pf = pf;
5147 TAILQ_INIT(&veb->head);
5148 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5150 /* create floating veb if vsi is NULL */
5152 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5153 I40E_DEFAULT_TCMAP, false,
5154 &veb->seid, false, NULL);
5156 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5157 true, &veb->seid, false, NULL);
5160 if (ret != I40E_SUCCESS) {
5161 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5162 hw->aq.asq_last_status);
5165 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5167 /* get statistics index */
5168 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5169 &veb->stats_idx, NULL, NULL, NULL);
5170 if (ret != I40E_SUCCESS) {
5171 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5172 hw->aq.asq_last_status);
5175 /* Get VEB bandwidth, to be implemented */
5176 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5178 vsi->uplink_seid = veb->seid;
5187 i40e_vsi_release(struct i40e_vsi *vsi)
5191 struct i40e_vsi_list *vsi_list;
5194 struct i40e_mac_filter *f;
5195 uint16_t user_param;
5198 return I40E_SUCCESS;
5203 user_param = vsi->user_param;
5205 pf = I40E_VSI_TO_PF(vsi);
5206 hw = I40E_VSI_TO_HW(vsi);
5208 /* VSI has child to attach, release child first */
5210 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5211 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5214 i40e_veb_release(vsi->veb);
5217 if (vsi->floating_veb) {
5218 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5219 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5224 /* Remove all macvlan filters of the VSI */
5225 i40e_vsi_remove_all_macvlan_filter(vsi);
5226 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5229 if (vsi->type != I40E_VSI_MAIN &&
5230 ((vsi->type != I40E_VSI_SRIOV) ||
5231 !pf->floating_veb_list[user_param])) {
5232 /* Remove vsi from parent's sibling list */
5233 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5234 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5235 return I40E_ERR_PARAM;
5237 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5238 &vsi->sib_vsi_list, list);
5240 /* Remove all switch element of the VSI */
5241 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5242 if (ret != I40E_SUCCESS)
5243 PMD_DRV_LOG(ERR, "Failed to delete element");
5246 if ((vsi->type == I40E_VSI_SRIOV) &&
5247 pf->floating_veb_list[user_param]) {
5248 /* Remove vsi from parent's sibling list */
5249 if (vsi->parent_vsi == NULL ||
5250 vsi->parent_vsi->floating_veb == NULL) {
5251 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5252 return I40E_ERR_PARAM;
5254 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5255 &vsi->sib_vsi_list, list);
5257 /* Remove all switch element of the VSI */
5258 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5259 if (ret != I40E_SUCCESS)
5260 PMD_DRV_LOG(ERR, "Failed to delete element");
5263 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5265 if (vsi->type != I40E_VSI_SRIOV)
5266 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5269 return I40E_SUCCESS;
5273 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5275 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5276 struct i40e_aqc_remove_macvlan_element_data def_filter;
5277 struct i40e_mac_filter_info filter;
5280 if (vsi->type != I40E_VSI_MAIN)
5281 return I40E_ERR_CONFIG;
5282 memset(&def_filter, 0, sizeof(def_filter));
5283 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5285 def_filter.vlan_tag = 0;
5286 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5287 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5288 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5289 if (ret != I40E_SUCCESS) {
5290 struct i40e_mac_filter *f;
5291 struct ether_addr *mac;
5294 "Cannot remove the default macvlan filter");
5295 /* It needs to add the permanent mac into mac list */
5296 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5298 PMD_DRV_LOG(ERR, "failed to allocate memory");
5299 return I40E_ERR_NO_MEMORY;
5301 mac = &f->mac_info.mac_addr;
5302 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5304 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5305 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5310 rte_memcpy(&filter.mac_addr,
5311 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5312 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5313 return i40e_vsi_add_mac(vsi, &filter);
5317 * i40e_vsi_get_bw_config - Query VSI BW Information
5318 * @vsi: the VSI to be queried
5320 * Returns 0 on success, negative value on failure
5322 static enum i40e_status_code
5323 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5325 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5326 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5327 struct i40e_hw *hw = &vsi->adapter->hw;
5332 memset(&bw_config, 0, sizeof(bw_config));
5333 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5334 if (ret != I40E_SUCCESS) {
5335 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5336 hw->aq.asq_last_status);
5340 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5341 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5342 &ets_sla_config, NULL);
5343 if (ret != I40E_SUCCESS) {
5345 "VSI failed to get TC bandwdith configuration %u",
5346 hw->aq.asq_last_status);
5350 /* store and print out BW info */
5351 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5352 vsi->bw_info.bw_max = bw_config.max_bw;
5353 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5354 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5355 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5356 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5358 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5359 vsi->bw_info.bw_ets_share_credits[i] =
5360 ets_sla_config.share_credits[i];
5361 vsi->bw_info.bw_ets_credits[i] =
5362 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5363 /* 4 bits per TC, 4th bit is reserved */
5364 vsi->bw_info.bw_ets_max[i] =
5365 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5366 RTE_LEN2MASK(3, uint8_t));
5367 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5368 vsi->bw_info.bw_ets_share_credits[i]);
5369 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5370 vsi->bw_info.bw_ets_credits[i]);
5371 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5372 vsi->bw_info.bw_ets_max[i]);
5375 return I40E_SUCCESS;
5378 /* i40e_enable_pf_lb
5379 * @pf: pointer to the pf structure
5381 * allow loopback on pf
5384 i40e_enable_pf_lb(struct i40e_pf *pf)
5386 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5387 struct i40e_vsi_context ctxt;
5390 /* Use the FW API if FW >= v5.0 */
5391 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5392 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5396 memset(&ctxt, 0, sizeof(ctxt));
5397 ctxt.seid = pf->main_vsi_seid;
5398 ctxt.pf_num = hw->pf_id;
5399 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5401 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5402 ret, hw->aq.asq_last_status);
5405 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5406 ctxt.info.valid_sections =
5407 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5408 ctxt.info.switch_id |=
5409 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5411 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5413 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5414 hw->aq.asq_last_status);
5419 i40e_vsi_setup(struct i40e_pf *pf,
5420 enum i40e_vsi_type type,
5421 struct i40e_vsi *uplink_vsi,
5422 uint16_t user_param)
5424 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5425 struct i40e_vsi *vsi;
5426 struct i40e_mac_filter_info filter;
5428 struct i40e_vsi_context ctxt;
5429 struct ether_addr broadcast =
5430 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5432 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5433 uplink_vsi == NULL) {
5435 "VSI setup failed, VSI link shouldn't be NULL");
5439 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5441 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5446 * 1.type is not MAIN and uplink vsi is not NULL
5447 * If uplink vsi didn't setup VEB, create one first under veb field
5448 * 2.type is SRIOV and the uplink is NULL
5449 * If floating VEB is NULL, create one veb under floating veb field
5452 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5453 uplink_vsi->veb == NULL) {
5454 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5456 if (uplink_vsi->veb == NULL) {
5457 PMD_DRV_LOG(ERR, "VEB setup failed");
5460 /* set ALLOWLOOPBACk on pf, when veb is created */
5461 i40e_enable_pf_lb(pf);
5464 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5465 pf->main_vsi->floating_veb == NULL) {
5466 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5468 if (pf->main_vsi->floating_veb == NULL) {
5469 PMD_DRV_LOG(ERR, "VEB setup failed");
5474 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5476 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5479 TAILQ_INIT(&vsi->mac_list);
5481 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5482 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5483 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5484 vsi->user_param = user_param;
5485 vsi->vlan_anti_spoof_on = 0;
5486 vsi->vlan_filter_on = 0;
5487 /* Allocate queues */
5488 switch (vsi->type) {
5489 case I40E_VSI_MAIN :
5490 vsi->nb_qps = pf->lan_nb_qps;
5492 case I40E_VSI_SRIOV :
5493 vsi->nb_qps = pf->vf_nb_qps;
5495 case I40E_VSI_VMDQ2:
5496 vsi->nb_qps = pf->vmdq_nb_qps;
5499 vsi->nb_qps = pf->fdir_nb_qps;
5505 * The filter status descriptor is reported in rx queue 0,
5506 * while the tx queue for fdir filter programming has no
5507 * such constraints, can be non-zero queues.
5508 * To simplify it, choose FDIR vsi use queue 0 pair.
5509 * To make sure it will use queue 0 pair, queue allocation
5510 * need be done before this function is called
5512 if (type != I40E_VSI_FDIR) {
5513 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5515 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5519 vsi->base_queue = ret;
5521 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5523 /* VF has MSIX interrupt in VF range, don't allocate here */
5524 if (type == I40E_VSI_MAIN) {
5525 if (pf->support_multi_driver) {
5526 /* If support multi-driver, need to use INT0 instead of
5527 * allocating from msix pool. The Msix pool is init from
5528 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5529 * to 1 without calling i40e_res_pool_alloc.
5534 ret = i40e_res_pool_alloc(&pf->msix_pool,
5535 RTE_MIN(vsi->nb_qps,
5536 RTE_MAX_RXTX_INTR_VEC_ID));
5539 "VSI MAIN %d get heap failed %d",
5541 goto fail_queue_alloc;
5543 vsi->msix_intr = ret;
5544 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5545 RTE_MAX_RXTX_INTR_VEC_ID);
5547 } else if (type != I40E_VSI_SRIOV) {
5548 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5550 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5551 goto fail_queue_alloc;
5553 vsi->msix_intr = ret;
5561 if (type == I40E_VSI_MAIN) {
5562 /* For main VSI, no need to add since it's default one */
5563 vsi->uplink_seid = pf->mac_seid;
5564 vsi->seid = pf->main_vsi_seid;
5565 /* Bind queues with specific MSIX interrupt */
5567 * Needs 2 interrupt at least, one for misc cause which will
5568 * enabled from OS side, Another for queues binding the
5569 * interrupt from device side only.
5572 /* Get default VSI parameters from hardware */
5573 memset(&ctxt, 0, sizeof(ctxt));
5574 ctxt.seid = vsi->seid;
5575 ctxt.pf_num = hw->pf_id;
5576 ctxt.uplink_seid = vsi->uplink_seid;
5578 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5579 if (ret != I40E_SUCCESS) {
5580 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5581 goto fail_msix_alloc;
5583 rte_memcpy(&vsi->info, &ctxt.info,
5584 sizeof(struct i40e_aqc_vsi_properties_data));
5585 vsi->vsi_id = ctxt.vsi_number;
5586 vsi->info.valid_sections = 0;
5588 /* Configure tc, enabled TC0 only */
5589 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5591 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5592 goto fail_msix_alloc;
5595 /* TC, queue mapping */
5596 memset(&ctxt, 0, sizeof(ctxt));
5597 vsi->info.valid_sections |=
5598 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5599 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5600 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5601 rte_memcpy(&ctxt.info, &vsi->info,
5602 sizeof(struct i40e_aqc_vsi_properties_data));
5603 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5604 I40E_DEFAULT_TCMAP);
5605 if (ret != I40E_SUCCESS) {
5607 "Failed to configure TC queue mapping");
5608 goto fail_msix_alloc;
5610 ctxt.seid = vsi->seid;
5611 ctxt.pf_num = hw->pf_id;
5612 ctxt.uplink_seid = vsi->uplink_seid;
5615 /* Update VSI parameters */
5616 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5617 if (ret != I40E_SUCCESS) {
5618 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5619 goto fail_msix_alloc;
5622 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5623 sizeof(vsi->info.tc_mapping));
5624 rte_memcpy(&vsi->info.queue_mapping,
5625 &ctxt.info.queue_mapping,
5626 sizeof(vsi->info.queue_mapping));
5627 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5628 vsi->info.valid_sections = 0;
5630 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5634 * Updating default filter settings are necessary to prevent
5635 * reception of tagged packets.
5636 * Some old firmware configurations load a default macvlan
5637 * filter which accepts both tagged and untagged packets.
5638 * The updating is to use a normal filter instead if needed.
5639 * For NVM 4.2.2 or after, the updating is not needed anymore.
5640 * The firmware with correct configurations load the default
5641 * macvlan filter which is expected and cannot be removed.
5643 i40e_update_default_filter_setting(vsi);
5644 i40e_config_qinq(hw, vsi);
5645 } else if (type == I40E_VSI_SRIOV) {
5646 memset(&ctxt, 0, sizeof(ctxt));
5648 * For other VSI, the uplink_seid equals to uplink VSI's
5649 * uplink_seid since they share same VEB
5651 if (uplink_vsi == NULL)
5652 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5654 vsi->uplink_seid = uplink_vsi->uplink_seid;
5655 ctxt.pf_num = hw->pf_id;
5656 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5657 ctxt.uplink_seid = vsi->uplink_seid;
5658 ctxt.connection_type = 0x1;
5659 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5661 /* Use the VEB configuration if FW >= v5.0 */
5662 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5663 /* Configure switch ID */
5664 ctxt.info.valid_sections |=
5665 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5666 ctxt.info.switch_id =
5667 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5670 /* Configure port/vlan */
5671 ctxt.info.valid_sections |=
5672 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5673 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5674 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5675 hw->func_caps.enabled_tcmap);
5676 if (ret != I40E_SUCCESS) {
5678 "Failed to configure TC queue mapping");
5679 goto fail_msix_alloc;
5682 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5683 ctxt.info.valid_sections |=
5684 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5686 * Since VSI is not created yet, only configure parameter,
5687 * will add vsi below.
5690 i40e_config_qinq(hw, vsi);
5691 } else if (type == I40E_VSI_VMDQ2) {
5692 memset(&ctxt, 0, sizeof(ctxt));
5694 * For other VSI, the uplink_seid equals to uplink VSI's
5695 * uplink_seid since they share same VEB
5697 vsi->uplink_seid = uplink_vsi->uplink_seid;
5698 ctxt.pf_num = hw->pf_id;
5700 ctxt.uplink_seid = vsi->uplink_seid;
5701 ctxt.connection_type = 0x1;
5702 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5704 ctxt.info.valid_sections |=
5705 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5706 /* user_param carries flag to enable loop back */
5708 ctxt.info.switch_id =
5709 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5710 ctxt.info.switch_id |=
5711 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5714 /* Configure port/vlan */
5715 ctxt.info.valid_sections |=
5716 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5717 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5718 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5719 I40E_DEFAULT_TCMAP);
5720 if (ret != I40E_SUCCESS) {
5722 "Failed to configure TC queue mapping");
5723 goto fail_msix_alloc;
5725 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5726 ctxt.info.valid_sections |=
5727 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5728 } else if (type == I40E_VSI_FDIR) {
5729 memset(&ctxt, 0, sizeof(ctxt));
5730 vsi->uplink_seid = uplink_vsi->uplink_seid;
5731 ctxt.pf_num = hw->pf_id;
5733 ctxt.uplink_seid = vsi->uplink_seid;
5734 ctxt.connection_type = 0x1; /* regular data port */
5735 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5736 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5737 I40E_DEFAULT_TCMAP);
5738 if (ret != I40E_SUCCESS) {
5740 "Failed to configure TC queue mapping.");
5741 goto fail_msix_alloc;
5743 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5744 ctxt.info.valid_sections |=
5745 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5747 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5748 goto fail_msix_alloc;
5751 if (vsi->type != I40E_VSI_MAIN) {
5752 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5753 if (ret != I40E_SUCCESS) {
5754 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5755 hw->aq.asq_last_status);
5756 goto fail_msix_alloc;
5758 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5759 vsi->info.valid_sections = 0;
5760 vsi->seid = ctxt.seid;
5761 vsi->vsi_id = ctxt.vsi_number;
5762 vsi->sib_vsi_list.vsi = vsi;
5763 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5764 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5765 &vsi->sib_vsi_list, list);
5767 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5768 &vsi->sib_vsi_list, list);
5772 /* MAC/VLAN configuration */
5773 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5774 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5776 ret = i40e_vsi_add_mac(vsi, &filter);
5777 if (ret != I40E_SUCCESS) {
5778 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5779 goto fail_msix_alloc;
5782 /* Get VSI BW information */
5783 i40e_vsi_get_bw_config(vsi);
5786 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5788 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5794 /* Configure vlan filter on or off */
5796 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5799 struct i40e_mac_filter *f;
5801 struct i40e_mac_filter_info *mac_filter;
5802 enum rte_mac_filter_type desired_filter;
5803 int ret = I40E_SUCCESS;
5806 /* Filter to match MAC and VLAN */
5807 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5809 /* Filter to match only MAC */
5810 desired_filter = RTE_MAC_PERFECT_MATCH;
5815 mac_filter = rte_zmalloc("mac_filter_info_data",
5816 num * sizeof(*mac_filter), 0);
5817 if (mac_filter == NULL) {
5818 PMD_DRV_LOG(ERR, "failed to allocate memory");
5819 return I40E_ERR_NO_MEMORY;
5824 /* Remove all existing mac */
5825 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5826 mac_filter[i] = f->mac_info;
5827 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5829 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5830 on ? "enable" : "disable");
5836 /* Override with new filter */
5837 for (i = 0; i < num; i++) {
5838 mac_filter[i].filter_type = desired_filter;
5839 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5841 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5842 on ? "enable" : "disable");
5848 rte_free(mac_filter);
5852 /* Configure vlan stripping on or off */
5854 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5856 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5857 struct i40e_vsi_context ctxt;
5859 int ret = I40E_SUCCESS;
5861 /* Check if it has been already on or off */
5862 if (vsi->info.valid_sections &
5863 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5865 if ((vsi->info.port_vlan_flags &
5866 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5867 return 0; /* already on */
5869 if ((vsi->info.port_vlan_flags &
5870 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5871 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5872 return 0; /* already off */
5877 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5879 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5880 vsi->info.valid_sections =
5881 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5882 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5883 vsi->info.port_vlan_flags |= vlan_flags;
5884 ctxt.seid = vsi->seid;
5885 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5886 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5888 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5889 on ? "enable" : "disable");
5895 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5897 struct rte_eth_dev_data *data = dev->data;
5901 /* Apply vlan offload setting */
5902 mask = ETH_VLAN_STRIP_MASK |
5903 ETH_VLAN_FILTER_MASK |
5904 ETH_VLAN_EXTEND_MASK;
5905 ret = i40e_vlan_offload_set(dev, mask);
5907 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5911 /* Apply pvid setting */
5912 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5913 data->dev_conf.txmode.hw_vlan_insert_pvid);
5915 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5921 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5923 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5925 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5929 i40e_update_flow_control(struct i40e_hw *hw)
5931 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5932 struct i40e_link_status link_status;
5933 uint32_t rxfc = 0, txfc = 0, reg;
5937 memset(&link_status, 0, sizeof(link_status));
5938 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5939 if (ret != I40E_SUCCESS) {
5940 PMD_DRV_LOG(ERR, "Failed to get link status information");
5941 goto write_reg; /* Disable flow control */
5944 an_info = hw->phy.link_info.an_info;
5945 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5946 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5947 ret = I40E_ERR_NOT_READY;
5948 goto write_reg; /* Disable flow control */
5951 * If link auto negotiation is enabled, flow control needs to
5952 * be configured according to it
5954 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5955 case I40E_LINK_PAUSE_RXTX:
5958 hw->fc.current_mode = I40E_FC_FULL;
5960 case I40E_AQ_LINK_PAUSE_RX:
5962 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5964 case I40E_AQ_LINK_PAUSE_TX:
5966 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5969 hw->fc.current_mode = I40E_FC_NONE;
5974 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5975 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5976 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5977 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5978 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5979 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5986 i40e_pf_setup(struct i40e_pf *pf)
5988 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5989 struct i40e_filter_control_settings settings;
5990 struct i40e_vsi *vsi;
5993 /* Clear all stats counters */
5994 pf->offset_loaded = FALSE;
5995 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5996 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5997 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5998 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6000 ret = i40e_pf_get_switch_config(pf);
6001 if (ret != I40E_SUCCESS) {
6002 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6006 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6008 PMD_INIT_LOG(WARNING,
6009 "failed to allocate switch domain for device %d", ret);
6011 if (pf->flags & I40E_FLAG_FDIR) {
6012 /* make queue allocated first, let FDIR use queue pair 0*/
6013 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6014 if (ret != I40E_FDIR_QUEUE_ID) {
6016 "queue allocation fails for FDIR: ret =%d",
6018 pf->flags &= ~I40E_FLAG_FDIR;
6021 /* main VSI setup */
6022 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6024 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6025 return I40E_ERR_NOT_READY;
6029 /* Configure filter control */
6030 memset(&settings, 0, sizeof(settings));
6031 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6032 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6033 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6034 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6036 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6037 hw->func_caps.rss_table_size);
6038 return I40E_ERR_PARAM;
6040 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6041 hw->func_caps.rss_table_size);
6042 pf->hash_lut_size = hw->func_caps.rss_table_size;
6044 /* Enable ethtype and macvlan filters */
6045 settings.enable_ethtype = TRUE;
6046 settings.enable_macvlan = TRUE;
6047 ret = i40e_set_filter_control(hw, &settings);
6049 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6052 /* Update flow control according to the auto negotiation */
6053 i40e_update_flow_control(hw);
6055 return I40E_SUCCESS;
6059 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6065 * Set or clear TX Queue Disable flags,
6066 * which is required by hardware.
6068 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6069 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6071 /* Wait until the request is finished */
6072 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6073 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6074 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6075 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6076 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6082 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6083 return I40E_SUCCESS; /* already on, skip next steps */
6085 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6086 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6088 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6089 return I40E_SUCCESS; /* already off, skip next steps */
6090 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6092 /* Write the register */
6093 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6094 /* Check the result */
6095 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6096 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6097 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6099 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6100 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6103 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6104 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6108 /* Check if it is timeout */
6109 if (j >= I40E_CHK_Q_ENA_COUNT) {
6110 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6111 (on ? "enable" : "disable"), q_idx);
6112 return I40E_ERR_TIMEOUT;
6115 return I40E_SUCCESS;
6118 /* Swith on or off the tx queues */
6120 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6122 struct rte_eth_dev_data *dev_data = pf->dev_data;
6123 struct i40e_tx_queue *txq;
6124 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6128 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6129 txq = dev_data->tx_queues[i];
6130 /* Don't operate the queue if not configured or
6131 * if starting only per queue */
6132 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6135 ret = i40e_dev_tx_queue_start(dev, i);
6137 ret = i40e_dev_tx_queue_stop(dev, i);
6138 if ( ret != I40E_SUCCESS)
6142 return I40E_SUCCESS;
6146 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6151 /* Wait until the request is finished */
6152 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6153 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6154 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6155 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6156 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6161 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6162 return I40E_SUCCESS; /* Already on, skip next steps */
6163 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6165 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6166 return I40E_SUCCESS; /* Already off, skip next steps */
6167 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6170 /* Write the register */
6171 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6172 /* Check the result */
6173 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6174 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6175 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6177 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6178 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6181 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6182 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6187 /* Check if it is timeout */
6188 if (j >= I40E_CHK_Q_ENA_COUNT) {
6189 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6190 (on ? "enable" : "disable"), q_idx);
6191 return I40E_ERR_TIMEOUT;
6194 return I40E_SUCCESS;
6196 /* Switch on or off the rx queues */
6198 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6200 struct rte_eth_dev_data *dev_data = pf->dev_data;
6201 struct i40e_rx_queue *rxq;
6202 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6206 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6207 rxq = dev_data->rx_queues[i];
6208 /* Don't operate the queue if not configured or
6209 * if starting only per queue */
6210 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6213 ret = i40e_dev_rx_queue_start(dev, i);
6215 ret = i40e_dev_rx_queue_stop(dev, i);
6216 if (ret != I40E_SUCCESS)
6220 return I40E_SUCCESS;
6223 /* Switch on or off all the rx/tx queues */
6225 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6230 /* enable rx queues before enabling tx queues */
6231 ret = i40e_dev_switch_rx_queues(pf, on);
6233 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6236 ret = i40e_dev_switch_tx_queues(pf, on);
6238 /* Stop tx queues before stopping rx queues */
6239 ret = i40e_dev_switch_tx_queues(pf, on);
6241 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6244 ret = i40e_dev_switch_rx_queues(pf, on);
6250 /* Initialize VSI for TX */
6252 i40e_dev_tx_init(struct i40e_pf *pf)
6254 struct rte_eth_dev_data *data = pf->dev_data;
6256 uint32_t ret = I40E_SUCCESS;
6257 struct i40e_tx_queue *txq;
6259 for (i = 0; i < data->nb_tx_queues; i++) {
6260 txq = data->tx_queues[i];
6261 if (!txq || !txq->q_set)
6263 ret = i40e_tx_queue_init(txq);
6264 if (ret != I40E_SUCCESS)
6267 if (ret == I40E_SUCCESS)
6268 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6274 /* Initialize VSI for RX */
6276 i40e_dev_rx_init(struct i40e_pf *pf)
6278 struct rte_eth_dev_data *data = pf->dev_data;
6279 int ret = I40E_SUCCESS;
6281 struct i40e_rx_queue *rxq;
6283 i40e_pf_config_mq_rx(pf);
6284 for (i = 0; i < data->nb_rx_queues; i++) {
6285 rxq = data->rx_queues[i];
6286 if (!rxq || !rxq->q_set)
6289 ret = i40e_rx_queue_init(rxq);
6290 if (ret != I40E_SUCCESS) {
6292 "Failed to do RX queue initialization");
6296 if (ret == I40E_SUCCESS)
6297 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6304 i40e_dev_rxtx_init(struct i40e_pf *pf)
6308 err = i40e_dev_tx_init(pf);
6310 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6313 err = i40e_dev_rx_init(pf);
6315 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6323 i40e_vmdq_setup(struct rte_eth_dev *dev)
6325 struct rte_eth_conf *conf = &dev->data->dev_conf;
6326 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6327 int i, err, conf_vsis, j, loop;
6328 struct i40e_vsi *vsi;
6329 struct i40e_vmdq_info *vmdq_info;
6330 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6331 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6334 * Disable interrupt to avoid message from VF. Furthermore, it will
6335 * avoid race condition in VSI creation/destroy.
6337 i40e_pf_disable_irq0(hw);
6339 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6340 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6344 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6345 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6346 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6347 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6348 pf->max_nb_vmdq_vsi);
6352 if (pf->vmdq != NULL) {
6353 PMD_INIT_LOG(INFO, "VMDQ already configured");
6357 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6358 sizeof(*vmdq_info) * conf_vsis, 0);
6360 if (pf->vmdq == NULL) {
6361 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6365 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6367 /* Create VMDQ VSI */
6368 for (i = 0; i < conf_vsis; i++) {
6369 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6370 vmdq_conf->enable_loop_back);
6372 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6376 vmdq_info = &pf->vmdq[i];
6378 vmdq_info->vsi = vsi;
6380 pf->nb_cfg_vmdq_vsi = conf_vsis;
6382 /* Configure Vlan */
6383 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6384 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6385 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6386 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6387 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6388 vmdq_conf->pool_map[i].vlan_id, j);
6390 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6391 vmdq_conf->pool_map[i].vlan_id);
6393 PMD_INIT_LOG(ERR, "Failed to add vlan");
6401 i40e_pf_enable_irq0(hw);
6406 for (i = 0; i < conf_vsis; i++)
6407 if (pf->vmdq[i].vsi == NULL)
6410 i40e_vsi_release(pf->vmdq[i].vsi);
6414 i40e_pf_enable_irq0(hw);
6419 i40e_stat_update_32(struct i40e_hw *hw,
6427 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6431 if (new_data >= *offset)
6432 *stat = (uint64_t)(new_data - *offset);
6434 *stat = (uint64_t)((new_data +
6435 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6439 i40e_stat_update_48(struct i40e_hw *hw,
6448 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6449 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6450 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6455 if (new_data >= *offset)
6456 *stat = new_data - *offset;
6458 *stat = (uint64_t)((new_data +
6459 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6461 *stat &= I40E_48_BIT_MASK;
6466 i40e_pf_disable_irq0(struct i40e_hw *hw)
6468 /* Disable all interrupt types */
6469 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6470 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6471 I40E_WRITE_FLUSH(hw);
6476 i40e_pf_enable_irq0(struct i40e_hw *hw)
6478 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6479 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6480 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6481 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6482 I40E_WRITE_FLUSH(hw);
6486 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6488 /* read pending request and disable first */
6489 i40e_pf_disable_irq0(hw);
6490 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6491 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6492 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6495 /* Link no queues with irq0 */
6496 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6497 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6501 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6503 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6504 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6507 uint32_t index, offset, val;
6512 * Try to find which VF trigger a reset, use absolute VF id to access
6513 * since the reg is global register.
6515 for (i = 0; i < pf->vf_num; i++) {
6516 abs_vf_id = hw->func_caps.vf_base_id + i;
6517 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6518 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6519 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6520 /* VFR event occurred */
6521 if (val & (0x1 << offset)) {
6524 /* Clear the event first */
6525 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6527 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6529 * Only notify a VF reset event occurred,
6530 * don't trigger another SW reset
6532 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6533 if (ret != I40E_SUCCESS)
6534 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6540 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6542 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6545 for (i = 0; i < pf->vf_num; i++)
6546 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6550 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6552 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6553 struct i40e_arq_event_info info;
6554 uint16_t pending, opcode;
6557 info.buf_len = I40E_AQ_BUF_SZ;
6558 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6559 if (!info.msg_buf) {
6560 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6566 ret = i40e_clean_arq_element(hw, &info, &pending);
6568 if (ret != I40E_SUCCESS) {
6570 "Failed to read msg from AdminQ, aq_err: %u",
6571 hw->aq.asq_last_status);
6574 opcode = rte_le_to_cpu_16(info.desc.opcode);
6577 case i40e_aqc_opc_send_msg_to_pf:
6578 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6579 i40e_pf_host_handle_vf_msg(dev,
6580 rte_le_to_cpu_16(info.desc.retval),
6581 rte_le_to_cpu_32(info.desc.cookie_high),
6582 rte_le_to_cpu_32(info.desc.cookie_low),
6586 case i40e_aqc_opc_get_link_status:
6587 ret = i40e_dev_link_update(dev, 0);
6589 _rte_eth_dev_callback_process(dev,
6590 RTE_ETH_EVENT_INTR_LSC, NULL);
6593 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6598 rte_free(info.msg_buf);
6602 * Interrupt handler triggered by NIC for handling
6603 * specific interrupt.
6606 * Pointer to interrupt handle.
6608 * The address of parameter (struct rte_eth_dev *) regsitered before.
6614 i40e_dev_interrupt_handler(void *param)
6616 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6620 /* Disable interrupt */
6621 i40e_pf_disable_irq0(hw);
6623 /* read out interrupt causes */
6624 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6626 /* No interrupt event indicated */
6627 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6628 PMD_DRV_LOG(INFO, "No interrupt event");
6631 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6632 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6633 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6634 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6635 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6636 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6637 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6638 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6639 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6640 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6641 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6642 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6643 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6644 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6646 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6647 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6648 i40e_dev_handle_vfr_event(dev);
6650 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6651 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6652 i40e_dev_handle_aq_msg(dev);
6656 /* Enable interrupt */
6657 i40e_pf_enable_irq0(hw);
6661 i40e_dev_alarm_handler(void *param)
6663 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6667 /* Disable interrupt */
6668 i40e_pf_disable_irq0(hw);
6670 /* read out interrupt causes */
6671 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6673 /* No interrupt event indicated */
6674 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6676 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6677 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6678 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6679 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6680 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6681 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6682 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6683 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6684 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6685 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6686 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6687 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6688 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6689 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6691 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6692 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6693 i40e_dev_handle_vfr_event(dev);
6695 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6696 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6697 i40e_dev_handle_aq_msg(dev);
6701 /* Enable interrupt */
6702 i40e_pf_enable_irq0(hw);
6703 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6704 i40e_dev_alarm_handler, dev);
6708 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6709 struct i40e_macvlan_filter *filter,
6712 int ele_num, ele_buff_size;
6713 int num, actual_num, i;
6715 int ret = I40E_SUCCESS;
6716 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6717 struct i40e_aqc_add_macvlan_element_data *req_list;
6719 if (filter == NULL || total == 0)
6720 return I40E_ERR_PARAM;
6721 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6722 ele_buff_size = hw->aq.asq_buf_size;
6724 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6725 if (req_list == NULL) {
6726 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6727 return I40E_ERR_NO_MEMORY;
6732 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6733 memset(req_list, 0, ele_buff_size);
6735 for (i = 0; i < actual_num; i++) {
6736 rte_memcpy(req_list[i].mac_addr,
6737 &filter[num + i].macaddr, ETH_ADDR_LEN);
6738 req_list[i].vlan_tag =
6739 rte_cpu_to_le_16(filter[num + i].vlan_id);
6741 switch (filter[num + i].filter_type) {
6742 case RTE_MAC_PERFECT_MATCH:
6743 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6744 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6746 case RTE_MACVLAN_PERFECT_MATCH:
6747 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6749 case RTE_MAC_HASH_MATCH:
6750 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6751 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6753 case RTE_MACVLAN_HASH_MATCH:
6754 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6757 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6758 ret = I40E_ERR_PARAM;
6762 req_list[i].queue_number = 0;
6764 req_list[i].flags = rte_cpu_to_le_16(flags);
6767 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6769 if (ret != I40E_SUCCESS) {
6770 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6774 } while (num < total);
6782 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6783 struct i40e_macvlan_filter *filter,
6786 int ele_num, ele_buff_size;
6787 int num, actual_num, i;
6789 int ret = I40E_SUCCESS;
6790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6791 struct i40e_aqc_remove_macvlan_element_data *req_list;
6793 if (filter == NULL || total == 0)
6794 return I40E_ERR_PARAM;
6796 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6797 ele_buff_size = hw->aq.asq_buf_size;
6799 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6800 if (req_list == NULL) {
6801 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6802 return I40E_ERR_NO_MEMORY;
6807 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6808 memset(req_list, 0, ele_buff_size);
6810 for (i = 0; i < actual_num; i++) {
6811 rte_memcpy(req_list[i].mac_addr,
6812 &filter[num + i].macaddr, ETH_ADDR_LEN);
6813 req_list[i].vlan_tag =
6814 rte_cpu_to_le_16(filter[num + i].vlan_id);
6816 switch (filter[num + i].filter_type) {
6817 case RTE_MAC_PERFECT_MATCH:
6818 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6819 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6821 case RTE_MACVLAN_PERFECT_MATCH:
6822 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6824 case RTE_MAC_HASH_MATCH:
6825 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6826 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6828 case RTE_MACVLAN_HASH_MATCH:
6829 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6832 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6833 ret = I40E_ERR_PARAM;
6836 req_list[i].flags = rte_cpu_to_le_16(flags);
6839 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6841 if (ret != I40E_SUCCESS) {
6842 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6846 } while (num < total);
6853 /* Find out specific MAC filter */
6854 static struct i40e_mac_filter *
6855 i40e_find_mac_filter(struct i40e_vsi *vsi,
6856 struct ether_addr *macaddr)
6858 struct i40e_mac_filter *f;
6860 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6861 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6869 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6872 uint32_t vid_idx, vid_bit;
6874 if (vlan_id > ETH_VLAN_ID_MAX)
6877 vid_idx = I40E_VFTA_IDX(vlan_id);
6878 vid_bit = I40E_VFTA_BIT(vlan_id);
6880 if (vsi->vfta[vid_idx] & vid_bit)
6887 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6888 uint16_t vlan_id, bool on)
6890 uint32_t vid_idx, vid_bit;
6892 vid_idx = I40E_VFTA_IDX(vlan_id);
6893 vid_bit = I40E_VFTA_BIT(vlan_id);
6896 vsi->vfta[vid_idx] |= vid_bit;
6898 vsi->vfta[vid_idx] &= ~vid_bit;
6902 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6903 uint16_t vlan_id, bool on)
6905 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6906 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6909 if (vlan_id > ETH_VLAN_ID_MAX)
6912 i40e_store_vlan_filter(vsi, vlan_id, on);
6914 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6917 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6920 ret = i40e_aq_add_vlan(hw, vsi->seid,
6921 &vlan_data, 1, NULL);
6922 if (ret != I40E_SUCCESS)
6923 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6925 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6926 &vlan_data, 1, NULL);
6927 if (ret != I40E_SUCCESS)
6929 "Failed to remove vlan filter");
6934 * Find all vlan options for specific mac addr,
6935 * return with actual vlan found.
6938 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6939 struct i40e_macvlan_filter *mv_f,
6940 int num, struct ether_addr *addr)
6946 * Not to use i40e_find_vlan_filter to decrease the loop time,
6947 * although the code looks complex.
6949 if (num < vsi->vlan_num)
6950 return I40E_ERR_PARAM;
6953 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6955 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6956 if (vsi->vfta[j] & (1 << k)) {
6959 "vlan number doesn't match");
6960 return I40E_ERR_PARAM;
6962 rte_memcpy(&mv_f[i].macaddr,
6963 addr, ETH_ADDR_LEN);
6965 j * I40E_UINT32_BIT_SIZE + k;
6971 return I40E_SUCCESS;
6975 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6976 struct i40e_macvlan_filter *mv_f,
6981 struct i40e_mac_filter *f;
6983 if (num < vsi->mac_num)
6984 return I40E_ERR_PARAM;
6986 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6988 PMD_DRV_LOG(ERR, "buffer number not match");
6989 return I40E_ERR_PARAM;
6991 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6993 mv_f[i].vlan_id = vlan;
6994 mv_f[i].filter_type = f->mac_info.filter_type;
6998 return I40E_SUCCESS;
7002 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7005 struct i40e_mac_filter *f;
7006 struct i40e_macvlan_filter *mv_f;
7007 int ret = I40E_SUCCESS;
7009 if (vsi == NULL || vsi->mac_num == 0)
7010 return I40E_ERR_PARAM;
7012 /* Case that no vlan is set */
7013 if (vsi->vlan_num == 0)
7016 num = vsi->mac_num * vsi->vlan_num;
7018 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7020 PMD_DRV_LOG(ERR, "failed to allocate memory");
7021 return I40E_ERR_NO_MEMORY;
7025 if (vsi->vlan_num == 0) {
7026 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7027 rte_memcpy(&mv_f[i].macaddr,
7028 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7029 mv_f[i].filter_type = f->mac_info.filter_type;
7030 mv_f[i].vlan_id = 0;
7034 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7035 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7036 vsi->vlan_num, &f->mac_info.mac_addr);
7037 if (ret != I40E_SUCCESS)
7039 for (j = i; j < i + vsi->vlan_num; j++)
7040 mv_f[j].filter_type = f->mac_info.filter_type;
7045 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7053 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7055 struct i40e_macvlan_filter *mv_f;
7057 int ret = I40E_SUCCESS;
7059 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7060 return I40E_ERR_PARAM;
7062 /* If it's already set, just return */
7063 if (i40e_find_vlan_filter(vsi,vlan))
7064 return I40E_SUCCESS;
7066 mac_num = vsi->mac_num;
7069 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7070 return I40E_ERR_PARAM;
7073 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7076 PMD_DRV_LOG(ERR, "failed to allocate memory");
7077 return I40E_ERR_NO_MEMORY;
7080 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7082 if (ret != I40E_SUCCESS)
7085 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7087 if (ret != I40E_SUCCESS)
7090 i40e_set_vlan_filter(vsi, vlan, 1);
7100 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7102 struct i40e_macvlan_filter *mv_f;
7104 int ret = I40E_SUCCESS;
7107 * Vlan 0 is the generic filter for untagged packets
7108 * and can't be removed.
7110 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7111 return I40E_ERR_PARAM;
7113 /* If can't find it, just return */
7114 if (!i40e_find_vlan_filter(vsi, vlan))
7115 return I40E_ERR_PARAM;
7117 mac_num = vsi->mac_num;
7120 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7121 return I40E_ERR_PARAM;
7124 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7127 PMD_DRV_LOG(ERR, "failed to allocate memory");
7128 return I40E_ERR_NO_MEMORY;
7131 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7133 if (ret != I40E_SUCCESS)
7136 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7138 if (ret != I40E_SUCCESS)
7141 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7142 if (vsi->vlan_num == 1) {
7143 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7144 if (ret != I40E_SUCCESS)
7147 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7148 if (ret != I40E_SUCCESS)
7152 i40e_set_vlan_filter(vsi, vlan, 0);
7162 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7164 struct i40e_mac_filter *f;
7165 struct i40e_macvlan_filter *mv_f;
7166 int i, vlan_num = 0;
7167 int ret = I40E_SUCCESS;
7169 /* If it's add and we've config it, return */
7170 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7172 return I40E_SUCCESS;
7173 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7174 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7177 * If vlan_num is 0, that's the first time to add mac,
7178 * set mask for vlan_id 0.
7180 if (vsi->vlan_num == 0) {
7181 i40e_set_vlan_filter(vsi, 0, 1);
7184 vlan_num = vsi->vlan_num;
7185 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7186 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7189 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7191 PMD_DRV_LOG(ERR, "failed to allocate memory");
7192 return I40E_ERR_NO_MEMORY;
7195 for (i = 0; i < vlan_num; i++) {
7196 mv_f[i].filter_type = mac_filter->filter_type;
7197 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7201 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7202 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7203 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7204 &mac_filter->mac_addr);
7205 if (ret != I40E_SUCCESS)
7209 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7210 if (ret != I40E_SUCCESS)
7213 /* Add the mac addr into mac list */
7214 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7216 PMD_DRV_LOG(ERR, "failed to allocate memory");
7217 ret = I40E_ERR_NO_MEMORY;
7220 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7222 f->mac_info.filter_type = mac_filter->filter_type;
7223 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7234 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7236 struct i40e_mac_filter *f;
7237 struct i40e_macvlan_filter *mv_f;
7239 enum rte_mac_filter_type filter_type;
7240 int ret = I40E_SUCCESS;
7242 /* Can't find it, return an error */
7243 f = i40e_find_mac_filter(vsi, addr);
7245 return I40E_ERR_PARAM;
7247 vlan_num = vsi->vlan_num;
7248 filter_type = f->mac_info.filter_type;
7249 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7250 filter_type == RTE_MACVLAN_HASH_MATCH) {
7251 if (vlan_num == 0) {
7252 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7253 return I40E_ERR_PARAM;
7255 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7256 filter_type == RTE_MAC_HASH_MATCH)
7259 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7261 PMD_DRV_LOG(ERR, "failed to allocate memory");
7262 return I40E_ERR_NO_MEMORY;
7265 for (i = 0; i < vlan_num; i++) {
7266 mv_f[i].filter_type = filter_type;
7267 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7270 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7271 filter_type == RTE_MACVLAN_HASH_MATCH) {
7272 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7273 if (ret != I40E_SUCCESS)
7277 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7278 if (ret != I40E_SUCCESS)
7281 /* Remove the mac addr into mac list */
7282 TAILQ_REMOVE(&vsi->mac_list, f, next);
7292 /* Configure hash enable flags for RSS */
7294 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7302 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7303 if (flags & (1ULL << i))
7304 hena |= adapter->pctypes_tbl[i];
7310 /* Parse the hash enable flags */
7312 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7314 uint64_t rss_hf = 0;
7320 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7321 if (flags & adapter->pctypes_tbl[i])
7322 rss_hf |= (1ULL << i);
7329 i40e_pf_disable_rss(struct i40e_pf *pf)
7331 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7333 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7334 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7335 I40E_WRITE_FLUSH(hw);
7339 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7341 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7342 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7343 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7344 I40E_VFQF_HKEY_MAX_INDEX :
7345 I40E_PFQF_HKEY_MAX_INDEX;
7348 if (!key || key_len == 0) {
7349 PMD_DRV_LOG(DEBUG, "No key to be configured");
7351 } else if (key_len != (key_idx + 1) *
7353 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7357 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7358 struct i40e_aqc_get_set_rss_key_data *key_dw =
7359 (struct i40e_aqc_get_set_rss_key_data *)key;
7361 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7363 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7365 uint32_t *hash_key = (uint32_t *)key;
7368 if (vsi->type == I40E_VSI_SRIOV) {
7369 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7372 I40E_VFQF_HKEY1(i, vsi->user_param),
7376 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7377 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7380 I40E_WRITE_FLUSH(hw);
7387 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7389 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7390 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7394 if (!key || !key_len)
7397 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7398 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7399 (struct i40e_aqc_get_set_rss_key_data *)key);
7401 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7405 uint32_t *key_dw = (uint32_t *)key;
7408 if (vsi->type == I40E_VSI_SRIOV) {
7409 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7410 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7411 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7413 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7416 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7417 reg = I40E_PFQF_HKEY(i);
7418 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7420 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7428 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7430 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7434 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7435 rss_conf->rss_key_len);
7439 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7440 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7441 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7442 I40E_WRITE_FLUSH(hw);
7448 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7449 struct rte_eth_rss_conf *rss_conf)
7451 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7453 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7456 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7457 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7459 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7460 if (rss_hf != 0) /* Enable RSS */
7462 return 0; /* Nothing to do */
7465 if (rss_hf == 0) /* Disable RSS */
7468 return i40e_hw_rss_hash_set(pf, rss_conf);
7472 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7473 struct rte_eth_rss_conf *rss_conf)
7475 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7476 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7480 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7481 &rss_conf->rss_key_len);
7485 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7486 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7487 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7493 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7495 switch (filter_type) {
7496 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7497 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7499 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7500 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7502 case RTE_TUNNEL_FILTER_IMAC_TENID:
7503 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7505 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7506 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7508 case ETH_TUNNEL_FILTER_IMAC:
7509 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7511 case ETH_TUNNEL_FILTER_OIP:
7512 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7514 case ETH_TUNNEL_FILTER_IIP:
7515 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7518 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7525 /* Convert tunnel filter structure */
7527 i40e_tunnel_filter_convert(
7528 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7529 struct i40e_tunnel_filter *tunnel_filter)
7531 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7532 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7533 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7534 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7535 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7536 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7537 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7538 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7539 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7541 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7542 tunnel_filter->input.flags = cld_filter->element.flags;
7543 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7544 tunnel_filter->queue = cld_filter->element.queue_number;
7545 rte_memcpy(tunnel_filter->input.general_fields,
7546 cld_filter->general_fields,
7547 sizeof(cld_filter->general_fields));
7552 /* Check if there exists the tunnel filter */
7553 struct i40e_tunnel_filter *
7554 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7555 const struct i40e_tunnel_filter_input *input)
7559 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7563 return tunnel_rule->hash_map[ret];
7566 /* Add a tunnel filter into the SW list */
7568 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7569 struct i40e_tunnel_filter *tunnel_filter)
7571 struct i40e_tunnel_rule *rule = &pf->tunnel;
7574 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7577 "Failed to insert tunnel filter to hash table %d!",
7581 rule->hash_map[ret] = tunnel_filter;
7583 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7588 /* Delete a tunnel filter from the SW list */
7590 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7591 struct i40e_tunnel_filter_input *input)
7593 struct i40e_tunnel_rule *rule = &pf->tunnel;
7594 struct i40e_tunnel_filter *tunnel_filter;
7597 ret = rte_hash_del_key(rule->hash_table, input);
7600 "Failed to delete tunnel filter to hash table %d!",
7604 tunnel_filter = rule->hash_map[ret];
7605 rule->hash_map[ret] = NULL;
7607 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7608 rte_free(tunnel_filter);
7614 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7615 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7619 uint32_t ipv4_addr, ipv4_addr_le;
7620 uint8_t i, tun_type = 0;
7621 /* internal varialbe to convert ipv6 byte order */
7622 uint32_t convert_ipv6[4];
7624 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7625 struct i40e_vsi *vsi = pf->main_vsi;
7626 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7627 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7628 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7629 struct i40e_tunnel_filter *tunnel, *node;
7630 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7632 cld_filter = rte_zmalloc("tunnel_filter",
7633 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7636 if (NULL == cld_filter) {
7637 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7640 pfilter = cld_filter;
7642 ether_addr_copy(&tunnel_filter->outer_mac,
7643 (struct ether_addr *)&pfilter->element.outer_mac);
7644 ether_addr_copy(&tunnel_filter->inner_mac,
7645 (struct ether_addr *)&pfilter->element.inner_mac);
7647 pfilter->element.inner_vlan =
7648 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7649 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7650 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7651 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7652 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7653 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7655 sizeof(pfilter->element.ipaddr.v4.data));
7657 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7658 for (i = 0; i < 4; i++) {
7660 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7662 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7664 sizeof(pfilter->element.ipaddr.v6.data));
7667 /* check tunneled type */
7668 switch (tunnel_filter->tunnel_type) {
7669 case RTE_TUNNEL_TYPE_VXLAN:
7670 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7672 case RTE_TUNNEL_TYPE_NVGRE:
7673 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7675 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7676 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7679 /* Other tunnel types is not supported. */
7680 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7681 rte_free(cld_filter);
7685 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7686 &pfilter->element.flags);
7688 rte_free(cld_filter);
7692 pfilter->element.flags |= rte_cpu_to_le_16(
7693 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7694 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7695 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7696 pfilter->element.queue_number =
7697 rte_cpu_to_le_16(tunnel_filter->queue_id);
7699 /* Check if there is the filter in SW list */
7700 memset(&check_filter, 0, sizeof(check_filter));
7701 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7702 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7704 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7705 rte_free(cld_filter);
7709 if (!add && !node) {
7710 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7711 rte_free(cld_filter);
7716 ret = i40e_aq_add_cloud_filters(hw,
7717 vsi->seid, &cld_filter->element, 1);
7719 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7720 rte_free(cld_filter);
7723 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7724 if (tunnel == NULL) {
7725 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7726 rte_free(cld_filter);
7730 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7731 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7735 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7736 &cld_filter->element, 1);
7738 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7739 rte_free(cld_filter);
7742 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7745 rte_free(cld_filter);
7749 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7750 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7751 #define I40E_TR_GENEVE_KEY_MASK 0x8
7752 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7753 #define I40E_TR_GRE_KEY_MASK 0x400
7754 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7755 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7758 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7760 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7761 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7762 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7763 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7764 enum i40e_status_code status = I40E_SUCCESS;
7766 if (pf->support_multi_driver) {
7767 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7768 return I40E_NOT_SUPPORTED;
7771 memset(&filter_replace, 0,
7772 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7773 memset(&filter_replace_buf, 0,
7774 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7776 /* create L1 filter */
7777 filter_replace.old_filter_type =
7778 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7779 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7780 filter_replace.tr_bit = 0;
7782 /* Prepare the buffer, 3 entries */
7783 filter_replace_buf.data[0] =
7784 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7785 filter_replace_buf.data[0] |=
7786 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7787 filter_replace_buf.data[2] = 0xFF;
7788 filter_replace_buf.data[3] = 0xFF;
7789 filter_replace_buf.data[4] =
7790 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7791 filter_replace_buf.data[4] |=
7792 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7793 filter_replace_buf.data[7] = 0xF0;
7794 filter_replace_buf.data[8]
7795 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7796 filter_replace_buf.data[8] |=
7797 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7798 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7799 I40E_TR_GENEVE_KEY_MASK |
7800 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7801 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7802 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7803 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7805 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7806 &filter_replace_buf);
7807 if (!status && (filter_replace.old_filter_type !=
7808 filter_replace.new_filter_type))
7809 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7810 " original: 0x%x, new: 0x%x",
7812 filter_replace.old_filter_type,
7813 filter_replace.new_filter_type);
7819 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7821 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7822 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7823 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7824 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7825 enum i40e_status_code status = I40E_SUCCESS;
7827 if (pf->support_multi_driver) {
7828 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7829 return I40E_NOT_SUPPORTED;
7833 memset(&filter_replace, 0,
7834 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7835 memset(&filter_replace_buf, 0,
7836 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7837 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7838 I40E_AQC_MIRROR_CLOUD_FILTER;
7839 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7840 filter_replace.new_filter_type =
7841 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7842 /* Prepare the buffer, 2 entries */
7843 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7844 filter_replace_buf.data[0] |=
7845 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7846 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7847 filter_replace_buf.data[4] |=
7848 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7849 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7850 &filter_replace_buf);
7853 if (filter_replace.old_filter_type !=
7854 filter_replace.new_filter_type)
7855 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7856 " original: 0x%x, new: 0x%x",
7858 filter_replace.old_filter_type,
7859 filter_replace.new_filter_type);
7862 memset(&filter_replace, 0,
7863 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7864 memset(&filter_replace_buf, 0,
7865 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7867 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7868 I40E_AQC_MIRROR_CLOUD_FILTER;
7869 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7870 filter_replace.new_filter_type =
7871 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7872 /* Prepare the buffer, 2 entries */
7873 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7874 filter_replace_buf.data[0] |=
7875 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7876 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7877 filter_replace_buf.data[4] |=
7878 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7880 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7881 &filter_replace_buf);
7882 if (!status && (filter_replace.old_filter_type !=
7883 filter_replace.new_filter_type))
7884 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7885 " original: 0x%x, new: 0x%x",
7887 filter_replace.old_filter_type,
7888 filter_replace.new_filter_type);
7893 static enum i40e_status_code
7894 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7896 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7897 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7898 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7899 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7900 enum i40e_status_code status = I40E_SUCCESS;
7902 if (pf->support_multi_driver) {
7903 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7904 return I40E_NOT_SUPPORTED;
7908 memset(&filter_replace, 0,
7909 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7910 memset(&filter_replace_buf, 0,
7911 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7912 /* create L1 filter */
7913 filter_replace.old_filter_type =
7914 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7915 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7916 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7917 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7918 /* Prepare the buffer, 2 entries */
7919 filter_replace_buf.data[0] =
7920 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7921 filter_replace_buf.data[0] |=
7922 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7923 filter_replace_buf.data[2] = 0xFF;
7924 filter_replace_buf.data[3] = 0xFF;
7925 filter_replace_buf.data[4] =
7926 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7927 filter_replace_buf.data[4] |=
7928 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7929 filter_replace_buf.data[6] = 0xFF;
7930 filter_replace_buf.data[7] = 0xFF;
7931 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7932 &filter_replace_buf);
7935 if (filter_replace.old_filter_type !=
7936 filter_replace.new_filter_type)
7937 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7938 " original: 0x%x, new: 0x%x",
7940 filter_replace.old_filter_type,
7941 filter_replace.new_filter_type);
7944 memset(&filter_replace, 0,
7945 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7946 memset(&filter_replace_buf, 0,
7947 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7948 /* create L1 filter */
7949 filter_replace.old_filter_type =
7950 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7951 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7952 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7953 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7954 /* Prepare the buffer, 2 entries */
7955 filter_replace_buf.data[0] =
7956 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7957 filter_replace_buf.data[0] |=
7958 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7959 filter_replace_buf.data[2] = 0xFF;
7960 filter_replace_buf.data[3] = 0xFF;
7961 filter_replace_buf.data[4] =
7962 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7963 filter_replace_buf.data[4] |=
7964 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7965 filter_replace_buf.data[6] = 0xFF;
7966 filter_replace_buf.data[7] = 0xFF;
7968 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7969 &filter_replace_buf);
7970 if (!status && (filter_replace.old_filter_type !=
7971 filter_replace.new_filter_type))
7972 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7973 " original: 0x%x, new: 0x%x",
7975 filter_replace.old_filter_type,
7976 filter_replace.new_filter_type);
7982 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7984 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7985 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7986 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7987 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7988 enum i40e_status_code status = I40E_SUCCESS;
7990 if (pf->support_multi_driver) {
7991 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7992 return I40E_NOT_SUPPORTED;
7996 memset(&filter_replace, 0,
7997 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7998 memset(&filter_replace_buf, 0,
7999 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8000 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8001 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8002 filter_replace.new_filter_type =
8003 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8004 /* Prepare the buffer, 2 entries */
8005 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8006 filter_replace_buf.data[0] |=
8007 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8008 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8009 filter_replace_buf.data[4] |=
8010 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8011 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8012 &filter_replace_buf);
8015 if (filter_replace.old_filter_type !=
8016 filter_replace.new_filter_type)
8017 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8018 " original: 0x%x, new: 0x%x",
8020 filter_replace.old_filter_type,
8021 filter_replace.new_filter_type);
8024 memset(&filter_replace, 0,
8025 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8026 memset(&filter_replace_buf, 0,
8027 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8028 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8029 filter_replace.old_filter_type =
8030 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8031 filter_replace.new_filter_type =
8032 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8033 /* Prepare the buffer, 2 entries */
8034 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8035 filter_replace_buf.data[0] |=
8036 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8037 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8038 filter_replace_buf.data[4] |=
8039 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8041 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8042 &filter_replace_buf);
8043 if (!status && (filter_replace.old_filter_type !=
8044 filter_replace.new_filter_type))
8045 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8046 " original: 0x%x, new: 0x%x",
8048 filter_replace.old_filter_type,
8049 filter_replace.new_filter_type);
8055 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8056 struct i40e_tunnel_filter_conf *tunnel_filter,
8060 uint32_t ipv4_addr, ipv4_addr_le;
8061 uint8_t i, tun_type = 0;
8062 /* internal variable to convert ipv6 byte order */
8063 uint32_t convert_ipv6[4];
8065 struct i40e_pf_vf *vf = NULL;
8066 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8067 struct i40e_vsi *vsi;
8068 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8069 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8070 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8071 struct i40e_tunnel_filter *tunnel, *node;
8072 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8074 bool big_buffer = 0;
8076 cld_filter = rte_zmalloc("tunnel_filter",
8077 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8080 if (cld_filter == NULL) {
8081 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8084 pfilter = cld_filter;
8086 ether_addr_copy(&tunnel_filter->outer_mac,
8087 (struct ether_addr *)&pfilter->element.outer_mac);
8088 ether_addr_copy(&tunnel_filter->inner_mac,
8089 (struct ether_addr *)&pfilter->element.inner_mac);
8091 pfilter->element.inner_vlan =
8092 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8093 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8094 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8095 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8096 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8097 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8099 sizeof(pfilter->element.ipaddr.v4.data));
8101 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8102 for (i = 0; i < 4; i++) {
8104 rte_cpu_to_le_32(rte_be_to_cpu_32(
8105 tunnel_filter->ip_addr.ipv6_addr[i]));
8107 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8109 sizeof(pfilter->element.ipaddr.v6.data));
8112 /* check tunneled type */
8113 switch (tunnel_filter->tunnel_type) {
8114 case I40E_TUNNEL_TYPE_VXLAN:
8115 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8117 case I40E_TUNNEL_TYPE_NVGRE:
8118 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8120 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8121 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8123 case I40E_TUNNEL_TYPE_MPLSoUDP:
8124 if (!pf->mpls_replace_flag) {
8125 i40e_replace_mpls_l1_filter(pf);
8126 i40e_replace_mpls_cloud_filter(pf);
8127 pf->mpls_replace_flag = 1;
8129 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8130 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8132 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8133 (teid_le & 0xF) << 12;
8134 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8137 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8139 case I40E_TUNNEL_TYPE_MPLSoGRE:
8140 if (!pf->mpls_replace_flag) {
8141 i40e_replace_mpls_l1_filter(pf);
8142 i40e_replace_mpls_cloud_filter(pf);
8143 pf->mpls_replace_flag = 1;
8145 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8146 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8148 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8149 (teid_le & 0xF) << 12;
8150 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8153 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8155 case I40E_TUNNEL_TYPE_GTPC:
8156 if (!pf->gtp_replace_flag) {
8157 i40e_replace_gtp_l1_filter(pf);
8158 i40e_replace_gtp_cloud_filter(pf);
8159 pf->gtp_replace_flag = 1;
8161 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8162 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8163 (teid_le >> 16) & 0xFFFF;
8164 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8166 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8170 case I40E_TUNNEL_TYPE_GTPU:
8171 if (!pf->gtp_replace_flag) {
8172 i40e_replace_gtp_l1_filter(pf);
8173 i40e_replace_gtp_cloud_filter(pf);
8174 pf->gtp_replace_flag = 1;
8176 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8177 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8178 (teid_le >> 16) & 0xFFFF;
8179 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8181 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8185 case I40E_TUNNEL_TYPE_QINQ:
8186 if (!pf->qinq_replace_flag) {
8187 ret = i40e_cloud_filter_qinq_create(pf);
8190 "QinQ tunnel filter already created.");
8191 pf->qinq_replace_flag = 1;
8193 /* Add in the General fields the values of
8194 * the Outer and Inner VLAN
8195 * Big Buffer should be set, see changes in
8196 * i40e_aq_add_cloud_filters
8198 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8199 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8203 /* Other tunnel types is not supported. */
8204 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8205 rte_free(cld_filter);
8209 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8210 pfilter->element.flags =
8211 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8212 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8213 pfilter->element.flags =
8214 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8215 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8216 pfilter->element.flags =
8217 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8218 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8219 pfilter->element.flags =
8220 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8221 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8222 pfilter->element.flags |=
8223 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8225 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8226 &pfilter->element.flags);
8228 rte_free(cld_filter);
8233 pfilter->element.flags |= rte_cpu_to_le_16(
8234 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8235 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8236 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8237 pfilter->element.queue_number =
8238 rte_cpu_to_le_16(tunnel_filter->queue_id);
8240 if (!tunnel_filter->is_to_vf)
8243 if (tunnel_filter->vf_id >= pf->vf_num) {
8244 PMD_DRV_LOG(ERR, "Invalid argument.");
8245 rte_free(cld_filter);
8248 vf = &pf->vfs[tunnel_filter->vf_id];
8252 /* Check if there is the filter in SW list */
8253 memset(&check_filter, 0, sizeof(check_filter));
8254 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8255 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8256 check_filter.vf_id = tunnel_filter->vf_id;
8257 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8259 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8260 rte_free(cld_filter);
8264 if (!add && !node) {
8265 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8266 rte_free(cld_filter);
8272 ret = i40e_aq_add_cloud_filters_bb(hw,
8273 vsi->seid, cld_filter, 1);
8275 ret = i40e_aq_add_cloud_filters(hw,
8276 vsi->seid, &cld_filter->element, 1);
8278 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8279 rte_free(cld_filter);
8282 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8283 if (tunnel == NULL) {
8284 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8285 rte_free(cld_filter);
8289 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8290 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8295 ret = i40e_aq_rem_cloud_filters_bb(
8296 hw, vsi->seid, cld_filter, 1);
8298 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8299 &cld_filter->element, 1);
8301 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8302 rte_free(cld_filter);
8305 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8308 rte_free(cld_filter);
8313 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8317 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8318 if (pf->vxlan_ports[i] == port)
8326 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8330 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8332 idx = i40e_get_vxlan_port_idx(pf, port);
8334 /* Check if port already exists */
8336 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8340 /* Now check if there is space to add the new port */
8341 idx = i40e_get_vxlan_port_idx(pf, 0);
8344 "Maximum number of UDP ports reached, not adding port %d",
8349 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8352 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8356 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8359 /* New port: add it and mark its index in the bitmap */
8360 pf->vxlan_ports[idx] = port;
8361 pf->vxlan_bitmap |= (1 << idx);
8363 if (!(pf->flags & I40E_FLAG_VXLAN))
8364 pf->flags |= I40E_FLAG_VXLAN;
8370 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8373 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8375 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8376 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8380 idx = i40e_get_vxlan_port_idx(pf, port);
8383 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8387 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8388 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8392 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8395 pf->vxlan_ports[idx] = 0;
8396 pf->vxlan_bitmap &= ~(1 << idx);
8398 if (!pf->vxlan_bitmap)
8399 pf->flags &= ~I40E_FLAG_VXLAN;
8404 /* Add UDP tunneling port */
8406 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8407 struct rte_eth_udp_tunnel *udp_tunnel)
8410 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8412 if (udp_tunnel == NULL)
8415 switch (udp_tunnel->prot_type) {
8416 case RTE_TUNNEL_TYPE_VXLAN:
8417 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8420 case RTE_TUNNEL_TYPE_GENEVE:
8421 case RTE_TUNNEL_TYPE_TEREDO:
8422 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8427 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8435 /* Remove UDP tunneling port */
8437 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8438 struct rte_eth_udp_tunnel *udp_tunnel)
8441 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8443 if (udp_tunnel == NULL)
8446 switch (udp_tunnel->prot_type) {
8447 case RTE_TUNNEL_TYPE_VXLAN:
8448 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8450 case RTE_TUNNEL_TYPE_GENEVE:
8451 case RTE_TUNNEL_TYPE_TEREDO:
8452 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8456 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8464 /* Calculate the maximum number of contiguous PF queues that are configured */
8466 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8468 struct rte_eth_dev_data *data = pf->dev_data;
8470 struct i40e_rx_queue *rxq;
8473 for (i = 0; i < pf->lan_nb_qps; i++) {
8474 rxq = data->rx_queues[i];
8475 if (rxq && rxq->q_set)
8486 i40e_pf_config_rss(struct i40e_pf *pf)
8488 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8489 struct rte_eth_rss_conf rss_conf;
8490 uint32_t i, lut = 0;
8494 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8495 * It's necessary to calculate the actual PF queues that are configured.
8497 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8498 num = i40e_pf_calc_configured_queues_num(pf);
8500 num = pf->dev_data->nb_rx_queues;
8502 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8503 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8507 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8511 if (pf->adapter->rss_reta_updated == 0) {
8512 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8515 lut = (lut << 8) | (j & ((0x1 <<
8516 hw->func_caps.rss_table_entry_width) - 1));
8518 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8523 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8524 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8525 i40e_pf_disable_rss(pf);
8528 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8529 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8530 /* Random default keys */
8531 static uint32_t rss_key_default[] = {0x6b793944,
8532 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8533 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8534 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8536 rss_conf.rss_key = (uint8_t *)rss_key_default;
8537 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8541 return i40e_hw_rss_hash_set(pf, &rss_conf);
8545 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8546 struct rte_eth_tunnel_filter_conf *filter)
8548 if (pf == NULL || filter == NULL) {
8549 PMD_DRV_LOG(ERR, "Invalid parameter");
8553 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8554 PMD_DRV_LOG(ERR, "Invalid queue ID");
8558 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8559 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8563 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8564 (is_zero_ether_addr(&filter->outer_mac))) {
8565 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8569 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8570 (is_zero_ether_addr(&filter->inner_mac))) {
8571 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8578 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8579 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8581 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8583 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8587 if (pf->support_multi_driver) {
8588 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8592 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8593 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8596 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8597 } else if (len == 4) {
8598 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8600 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8605 ret = i40e_aq_debug_write_global_register(hw,
8606 I40E_GL_PRS_FVBM(2),
8610 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8611 "with value 0x%08x",
8612 I40E_GL_PRS_FVBM(2), reg);
8616 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8617 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8623 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8630 switch (cfg->cfg_type) {
8631 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8632 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8635 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8643 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8644 enum rte_filter_op filter_op,
8647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8648 int ret = I40E_ERR_PARAM;
8650 switch (filter_op) {
8651 case RTE_ETH_FILTER_SET:
8652 ret = i40e_dev_global_config_set(hw,
8653 (struct rte_eth_global_cfg *)arg);
8656 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8664 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8665 enum rte_filter_op filter_op,
8668 struct rte_eth_tunnel_filter_conf *filter;
8669 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8670 int ret = I40E_SUCCESS;
8672 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8674 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8675 return I40E_ERR_PARAM;
8677 switch (filter_op) {
8678 case RTE_ETH_FILTER_NOP:
8679 if (!(pf->flags & I40E_FLAG_VXLAN))
8680 ret = I40E_NOT_SUPPORTED;
8682 case RTE_ETH_FILTER_ADD:
8683 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8685 case RTE_ETH_FILTER_DELETE:
8686 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8689 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8690 ret = I40E_ERR_PARAM;
8698 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8701 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8704 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8705 ret = i40e_pf_config_rss(pf);
8707 i40e_pf_disable_rss(pf);
8712 /* Get the symmetric hash enable configurations per port */
8714 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8716 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8718 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8721 /* Set the symmetric hash enable configurations per port */
8723 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8725 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8728 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8730 "Symmetric hash has already been enabled");
8733 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8735 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8737 "Symmetric hash has already been disabled");
8740 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8742 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8743 I40E_WRITE_FLUSH(hw);
8747 * Get global configurations of hash function type and symmetric hash enable
8748 * per flow type (pctype). Note that global configuration means it affects all
8749 * the ports on the same NIC.
8752 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8753 struct rte_eth_hash_global_conf *g_cfg)
8755 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8759 memset(g_cfg, 0, sizeof(*g_cfg));
8760 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8761 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8762 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8764 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8765 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8766 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8769 * As i40e supports less than 64 flow types, only first 64 bits need to
8772 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8773 g_cfg->valid_bit_mask[i] = 0ULL;
8774 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8777 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8779 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8780 if (!adapter->pctypes_tbl[i])
8782 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8783 j < I40E_FILTER_PCTYPE_MAX; j++) {
8784 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8785 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8786 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8787 g_cfg->sym_hash_enable_mask[0] |=
8798 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8799 const struct rte_eth_hash_global_conf *g_cfg)
8802 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8804 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8805 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8806 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8807 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8813 * As i40e supports less than 64 flow types, only first 64 bits need to
8816 mask0 = g_cfg->valid_bit_mask[0];
8817 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8819 /* Check if any unsupported flow type configured */
8820 if ((mask0 | i40e_mask) ^ i40e_mask)
8823 if (g_cfg->valid_bit_mask[i])
8831 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8837 * Set global configurations of hash function type and symmetric hash enable
8838 * per flow type (pctype). Note any modifying global configuration will affect
8839 * all the ports on the same NIC.
8842 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8843 struct rte_eth_hash_global_conf *g_cfg)
8845 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8846 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8850 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8852 if (pf->support_multi_driver) {
8853 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8857 /* Check the input parameters */
8858 ret = i40e_hash_global_config_check(adapter, g_cfg);
8863 * As i40e supports less than 64 flow types, only first 64 bits need to
8866 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8867 if (mask0 & (1UL << i)) {
8868 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8869 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8871 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8872 j < I40E_FILTER_PCTYPE_MAX; j++) {
8873 if (adapter->pctypes_tbl[i] & (1ULL << j))
8874 i40e_write_global_rx_ctl(hw,
8881 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8882 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8884 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8886 "Hash function already set to Toeplitz");
8889 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8890 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8892 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8894 "Hash function already set to Simple XOR");
8897 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8899 /* Use the default, and keep it as it is */
8902 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8905 I40E_WRITE_FLUSH(hw);
8911 * Valid input sets for hash and flow director filters per PCTYPE
8914 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8915 enum rte_filter_type filter)
8919 static const uint64_t valid_hash_inset_table[] = {
8920 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8921 I40E_INSET_DMAC | I40E_INSET_SMAC |
8922 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8923 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8924 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8925 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8926 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8927 I40E_INSET_FLEX_PAYLOAD,
8928 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8929 I40E_INSET_DMAC | I40E_INSET_SMAC |
8930 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8931 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8932 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8933 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8934 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8935 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8936 I40E_INSET_FLEX_PAYLOAD,
8937 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8938 I40E_INSET_DMAC | I40E_INSET_SMAC |
8939 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8940 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8941 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8942 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8943 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8944 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8945 I40E_INSET_FLEX_PAYLOAD,
8946 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8947 I40E_INSET_DMAC | I40E_INSET_SMAC |
8948 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8949 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8950 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8951 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8952 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8953 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8954 I40E_INSET_FLEX_PAYLOAD,
8955 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8956 I40E_INSET_DMAC | I40E_INSET_SMAC |
8957 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8958 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8959 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8960 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8961 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8962 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8963 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8964 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8965 I40E_INSET_DMAC | I40E_INSET_SMAC |
8966 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8967 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8968 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8969 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8970 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8971 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8972 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8973 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8974 I40E_INSET_DMAC | I40E_INSET_SMAC |
8975 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8976 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8977 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8978 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8979 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8980 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8981 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8982 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8983 I40E_INSET_DMAC | I40E_INSET_SMAC |
8984 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8985 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8986 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8987 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8988 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8989 I40E_INSET_FLEX_PAYLOAD,
8990 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8991 I40E_INSET_DMAC | I40E_INSET_SMAC |
8992 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8993 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8994 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8995 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8996 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8997 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8998 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8999 I40E_INSET_DMAC | I40E_INSET_SMAC |
9000 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9001 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9002 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9003 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9004 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9005 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9006 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9007 I40E_INSET_DMAC | I40E_INSET_SMAC |
9008 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9009 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9010 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9011 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9012 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9013 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9014 I40E_INSET_FLEX_PAYLOAD,
9015 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9016 I40E_INSET_DMAC | I40E_INSET_SMAC |
9017 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9018 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9019 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9020 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9021 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9022 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9023 I40E_INSET_FLEX_PAYLOAD,
9024 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9025 I40E_INSET_DMAC | I40E_INSET_SMAC |
9026 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9027 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9028 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9029 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9030 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9031 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9032 I40E_INSET_FLEX_PAYLOAD,
9033 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9034 I40E_INSET_DMAC | I40E_INSET_SMAC |
9035 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9036 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9037 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9038 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9039 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9040 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9041 I40E_INSET_FLEX_PAYLOAD,
9042 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9043 I40E_INSET_DMAC | I40E_INSET_SMAC |
9044 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9045 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9046 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9047 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9048 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9049 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9050 I40E_INSET_FLEX_PAYLOAD,
9051 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9052 I40E_INSET_DMAC | I40E_INSET_SMAC |
9053 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9054 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9055 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9056 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9057 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9058 I40E_INSET_FLEX_PAYLOAD,
9059 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9060 I40E_INSET_DMAC | I40E_INSET_SMAC |
9061 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9062 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9063 I40E_INSET_FLEX_PAYLOAD,
9067 * Flow director supports only fields defined in
9068 * union rte_eth_fdir_flow.
9070 static const uint64_t valid_fdir_inset_table[] = {
9071 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9072 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9073 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9074 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9075 I40E_INSET_IPV4_TTL,
9076 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9077 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9078 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9079 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9080 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9081 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9082 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9083 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9084 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9085 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9086 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9088 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9089 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9090 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9091 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9094 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9095 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9096 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9097 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9098 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9099 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9100 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9101 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9102 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9103 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9104 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9105 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9107 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9108 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9109 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9110 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9111 I40E_INSET_IPV4_TTL,
9112 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9113 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9115 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9116 I40E_INSET_IPV6_HOP_LIMIT,
9117 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9118 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9119 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9120 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9121 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9122 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9123 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9124 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9125 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9126 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9127 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9128 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9130 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9131 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9132 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9133 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9134 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9135 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9136 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9137 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9138 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9139 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9140 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9141 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9142 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9143 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9145 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9146 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9148 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9149 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9150 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9151 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9152 I40E_INSET_IPV6_HOP_LIMIT,
9153 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9154 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9155 I40E_INSET_LAST_ETHER_TYPE,
9158 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9160 if (filter == RTE_ETH_FILTER_HASH)
9161 valid = valid_hash_inset_table[pctype];
9163 valid = valid_fdir_inset_table[pctype];
9169 * Validate if the input set is allowed for a specific PCTYPE
9172 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9173 enum rte_filter_type filter, uint64_t inset)
9177 valid = i40e_get_valid_input_set(pctype, filter);
9178 if (inset & (~valid))
9184 /* default input set fields combination per pctype */
9186 i40e_get_default_input_set(uint16_t pctype)
9188 static const uint64_t default_inset_table[] = {
9189 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9190 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9191 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9192 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9193 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9194 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9196 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9197 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9198 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9199 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9200 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9201 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9203 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9204 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9205 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9206 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9207 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9208 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9210 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9211 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9212 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9213 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9214 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9215 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9216 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9217 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9218 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9219 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9220 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9221 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9222 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9223 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9224 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9225 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9226 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9227 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9228 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9229 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9230 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9231 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9233 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9234 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9235 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9236 I40E_INSET_LAST_ETHER_TYPE,
9239 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9242 return default_inset_table[pctype];
9246 * Parse the input set from index to logical bit masks
9249 i40e_parse_input_set(uint64_t *inset,
9250 enum i40e_filter_pctype pctype,
9251 enum rte_eth_input_set_field *field,
9257 static const struct {
9258 enum rte_eth_input_set_field field;
9260 } inset_convert_table[] = {
9261 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9262 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9263 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9264 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9265 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9266 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9267 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9268 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9269 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9270 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9271 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9272 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9273 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9274 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9275 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9276 I40E_INSET_IPV6_NEXT_HDR},
9277 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9278 I40E_INSET_IPV6_HOP_LIMIT},
9279 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9280 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9281 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9282 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9283 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9284 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9285 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9286 I40E_INSET_SCTP_VT},
9287 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9288 I40E_INSET_TUNNEL_DMAC},
9289 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9290 I40E_INSET_VLAN_TUNNEL},
9291 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9292 I40E_INSET_TUNNEL_ID},
9293 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9294 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9295 I40E_INSET_FLEX_PAYLOAD_W1},
9296 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9297 I40E_INSET_FLEX_PAYLOAD_W2},
9298 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9299 I40E_INSET_FLEX_PAYLOAD_W3},
9300 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9301 I40E_INSET_FLEX_PAYLOAD_W4},
9302 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9303 I40E_INSET_FLEX_PAYLOAD_W5},
9304 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9305 I40E_INSET_FLEX_PAYLOAD_W6},
9306 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9307 I40E_INSET_FLEX_PAYLOAD_W7},
9308 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9309 I40E_INSET_FLEX_PAYLOAD_W8},
9312 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9315 /* Only one item allowed for default or all */
9317 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9318 *inset = i40e_get_default_input_set(pctype);
9320 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9321 *inset = I40E_INSET_NONE;
9326 for (i = 0, *inset = 0; i < size; i++) {
9327 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9328 if (field[i] == inset_convert_table[j].field) {
9329 *inset |= inset_convert_table[j].inset;
9334 /* It contains unsupported input set, return immediately */
9335 if (j == RTE_DIM(inset_convert_table))
9343 * Translate the input set from bit masks to register aware bit masks
9347 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9357 static const struct inset_map inset_map_common[] = {
9358 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9359 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9360 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9361 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9362 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9363 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9364 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9365 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9366 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9367 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9368 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9369 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9370 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9371 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9372 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9373 {I40E_INSET_TUNNEL_DMAC,
9374 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9375 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9376 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9377 {I40E_INSET_TUNNEL_SRC_PORT,
9378 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9379 {I40E_INSET_TUNNEL_DST_PORT,
9380 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9381 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9382 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9383 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9384 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9385 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9386 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9387 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9388 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9389 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9392 /* some different registers map in x722*/
9393 static const struct inset_map inset_map_diff_x722[] = {
9394 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9395 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9396 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9397 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9400 static const struct inset_map inset_map_diff_not_x722[] = {
9401 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9402 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9403 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9404 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9410 /* Translate input set to register aware inset */
9411 if (type == I40E_MAC_X722) {
9412 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9413 if (input & inset_map_diff_x722[i].inset)
9414 val |= inset_map_diff_x722[i].inset_reg;
9417 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9418 if (input & inset_map_diff_not_x722[i].inset)
9419 val |= inset_map_diff_not_x722[i].inset_reg;
9423 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9424 if (input & inset_map_common[i].inset)
9425 val |= inset_map_common[i].inset_reg;
9432 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9435 uint64_t inset_need_mask = inset;
9437 static const struct {
9440 } inset_mask_map[] = {
9441 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9442 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9443 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9444 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9445 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9446 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9447 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9448 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9451 if (!inset || !mask || !nb_elem)
9454 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9455 /* Clear the inset bit, if no MASK is required,
9456 * for example proto + ttl
9458 if ((inset & inset_mask_map[i].inset) ==
9459 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9460 inset_need_mask &= ~inset_mask_map[i].inset;
9461 if (!inset_need_mask)
9464 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9465 if ((inset_need_mask & inset_mask_map[i].inset) ==
9466 inset_mask_map[i].inset) {
9467 if (idx >= nb_elem) {
9468 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9471 mask[idx] = inset_mask_map[i].mask;
9480 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9482 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9484 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9486 i40e_write_rx_ctl(hw, addr, val);
9487 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9488 (uint32_t)i40e_read_rx_ctl(hw, addr));
9492 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9494 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9495 struct rte_eth_dev *dev;
9497 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9499 i40e_write_rx_ctl(hw, addr, val);
9500 PMD_DRV_LOG(WARNING,
9501 "i40e device %s changed global register [0x%08x]."
9502 " original: 0x%08x, new: 0x%08x",
9503 dev->device->name, addr, reg,
9504 (uint32_t)i40e_read_rx_ctl(hw, addr));
9509 i40e_filter_input_set_init(struct i40e_pf *pf)
9511 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9512 enum i40e_filter_pctype pctype;
9513 uint64_t input_set, inset_reg;
9514 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9518 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9519 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9520 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9522 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9525 input_set = i40e_get_default_input_set(pctype);
9527 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9528 I40E_INSET_MASK_NUM_REG);
9531 if (pf->support_multi_driver && num > 0) {
9532 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9535 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9538 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9539 (uint32_t)(inset_reg & UINT32_MAX));
9540 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9541 (uint32_t)((inset_reg >>
9542 I40E_32_BIT_WIDTH) & UINT32_MAX));
9543 if (!pf->support_multi_driver) {
9544 i40e_check_write_global_reg(hw,
9545 I40E_GLQF_HASH_INSET(0, pctype),
9546 (uint32_t)(inset_reg & UINT32_MAX));
9547 i40e_check_write_global_reg(hw,
9548 I40E_GLQF_HASH_INSET(1, pctype),
9549 (uint32_t)((inset_reg >>
9550 I40E_32_BIT_WIDTH) & UINT32_MAX));
9552 for (i = 0; i < num; i++) {
9553 i40e_check_write_global_reg(hw,
9554 I40E_GLQF_FD_MSK(i, pctype),
9556 i40e_check_write_global_reg(hw,
9557 I40E_GLQF_HASH_MSK(i, pctype),
9560 /*clear unused mask registers of the pctype */
9561 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9562 i40e_check_write_global_reg(hw,
9563 I40E_GLQF_FD_MSK(i, pctype),
9565 i40e_check_write_global_reg(hw,
9566 I40E_GLQF_HASH_MSK(i, pctype),
9570 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9572 I40E_WRITE_FLUSH(hw);
9574 /* store the default input set */
9575 if (!pf->support_multi_driver)
9576 pf->hash_input_set[pctype] = input_set;
9577 pf->fdir.input_set[pctype] = input_set;
9582 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9583 struct rte_eth_input_set_conf *conf)
9585 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9586 enum i40e_filter_pctype pctype;
9587 uint64_t input_set, inset_reg = 0;
9588 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9592 PMD_DRV_LOG(ERR, "Invalid pointer");
9595 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9596 conf->op != RTE_ETH_INPUT_SET_ADD) {
9597 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9601 if (pf->support_multi_driver) {
9602 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9606 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9607 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9608 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9612 if (hw->mac.type == I40E_MAC_X722) {
9613 /* get translated pctype value in fd pctype register */
9614 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9615 I40E_GLQF_FD_PCTYPES((int)pctype));
9618 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9621 PMD_DRV_LOG(ERR, "Failed to parse input set");
9625 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9626 /* get inset value in register */
9627 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9628 inset_reg <<= I40E_32_BIT_WIDTH;
9629 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9630 input_set |= pf->hash_input_set[pctype];
9632 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9633 I40E_INSET_MASK_NUM_REG);
9637 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9639 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9640 (uint32_t)(inset_reg & UINT32_MAX));
9641 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9642 (uint32_t)((inset_reg >>
9643 I40E_32_BIT_WIDTH) & UINT32_MAX));
9645 for (i = 0; i < num; i++)
9646 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9648 /*clear unused mask registers of the pctype */
9649 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9650 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9652 I40E_WRITE_FLUSH(hw);
9654 pf->hash_input_set[pctype] = input_set;
9659 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9660 struct rte_eth_input_set_conf *conf)
9662 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9663 enum i40e_filter_pctype pctype;
9664 uint64_t input_set, inset_reg = 0;
9665 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9669 PMD_DRV_LOG(ERR, "Invalid pointer");
9672 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9673 conf->op != RTE_ETH_INPUT_SET_ADD) {
9674 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9678 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9680 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9681 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9685 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9688 PMD_DRV_LOG(ERR, "Failed to parse input set");
9692 /* get inset value in register */
9693 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9694 inset_reg <<= I40E_32_BIT_WIDTH;
9695 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9697 /* Can not change the inset reg for flex payload for fdir,
9698 * it is done by writing I40E_PRTQF_FD_FLXINSET
9699 * in i40e_set_flex_mask_on_pctype.
9701 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9702 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9704 input_set |= pf->fdir.input_set[pctype];
9705 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9706 I40E_INSET_MASK_NUM_REG);
9709 if (pf->support_multi_driver && num > 0) {
9710 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9714 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9716 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9717 (uint32_t)(inset_reg & UINT32_MAX));
9718 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9719 (uint32_t)((inset_reg >>
9720 I40E_32_BIT_WIDTH) & UINT32_MAX));
9722 if (!pf->support_multi_driver) {
9723 for (i = 0; i < num; i++)
9724 i40e_check_write_global_reg(hw,
9725 I40E_GLQF_FD_MSK(i, pctype),
9727 /*clear unused mask registers of the pctype */
9728 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9729 i40e_check_write_global_reg(hw,
9730 I40E_GLQF_FD_MSK(i, pctype),
9733 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9735 I40E_WRITE_FLUSH(hw);
9737 pf->fdir.input_set[pctype] = input_set;
9742 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9747 PMD_DRV_LOG(ERR, "Invalid pointer");
9751 switch (info->info_type) {
9752 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9753 i40e_get_symmetric_hash_enable_per_port(hw,
9754 &(info->info.enable));
9756 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9757 ret = i40e_get_hash_filter_global_config(hw,
9758 &(info->info.global_conf));
9761 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9771 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9776 PMD_DRV_LOG(ERR, "Invalid pointer");
9780 switch (info->info_type) {
9781 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9782 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9784 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9785 ret = i40e_set_hash_filter_global_config(hw,
9786 &(info->info.global_conf));
9788 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9789 ret = i40e_hash_filter_inset_select(hw,
9790 &(info->info.input_set_conf));
9794 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9803 /* Operations for hash function */
9805 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9806 enum rte_filter_op filter_op,
9809 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9812 switch (filter_op) {
9813 case RTE_ETH_FILTER_NOP:
9815 case RTE_ETH_FILTER_GET:
9816 ret = i40e_hash_filter_get(hw,
9817 (struct rte_eth_hash_filter_info *)arg);
9819 case RTE_ETH_FILTER_SET:
9820 ret = i40e_hash_filter_set(hw,
9821 (struct rte_eth_hash_filter_info *)arg);
9824 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9833 /* Convert ethertype filter structure */
9835 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9836 struct i40e_ethertype_filter *filter)
9838 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9839 filter->input.ether_type = input->ether_type;
9840 filter->flags = input->flags;
9841 filter->queue = input->queue;
9846 /* Check if there exists the ehtertype filter */
9847 struct i40e_ethertype_filter *
9848 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9849 const struct i40e_ethertype_filter_input *input)
9853 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9857 return ethertype_rule->hash_map[ret];
9860 /* Add ethertype filter in SW list */
9862 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9863 struct i40e_ethertype_filter *filter)
9865 struct i40e_ethertype_rule *rule = &pf->ethertype;
9868 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9871 "Failed to insert ethertype filter"
9872 " to hash table %d!",
9876 rule->hash_map[ret] = filter;
9878 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9883 /* Delete ethertype filter in SW list */
9885 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9886 struct i40e_ethertype_filter_input *input)
9888 struct i40e_ethertype_rule *rule = &pf->ethertype;
9889 struct i40e_ethertype_filter *filter;
9892 ret = rte_hash_del_key(rule->hash_table, input);
9895 "Failed to delete ethertype filter"
9896 " to hash table %d!",
9900 filter = rule->hash_map[ret];
9901 rule->hash_map[ret] = NULL;
9903 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9910 * Configure ethertype filter, which can director packet by filtering
9911 * with mac address and ether_type or only ether_type
9914 i40e_ethertype_filter_set(struct i40e_pf *pf,
9915 struct rte_eth_ethertype_filter *filter,
9918 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9919 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9920 struct i40e_ethertype_filter *ethertype_filter, *node;
9921 struct i40e_ethertype_filter check_filter;
9922 struct i40e_control_filter_stats stats;
9926 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9927 PMD_DRV_LOG(ERR, "Invalid queue ID");
9930 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9931 filter->ether_type == ETHER_TYPE_IPv6) {
9933 "unsupported ether_type(0x%04x) in control packet filter.",
9934 filter->ether_type);
9937 if (filter->ether_type == ETHER_TYPE_VLAN)
9938 PMD_DRV_LOG(WARNING,
9939 "filter vlan ether_type in first tag is not supported.");
9941 /* Check if there is the filter in SW list */
9942 memset(&check_filter, 0, sizeof(check_filter));
9943 i40e_ethertype_filter_convert(filter, &check_filter);
9944 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9945 &check_filter.input);
9947 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9951 if (!add && !node) {
9952 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9956 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9957 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9958 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9959 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9960 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9962 memset(&stats, 0, sizeof(stats));
9963 ret = i40e_aq_add_rem_control_packet_filter(hw,
9964 filter->mac_addr.addr_bytes,
9965 filter->ether_type, flags,
9967 filter->queue, add, &stats, NULL);
9970 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9971 ret, stats.mac_etype_used, stats.etype_used,
9972 stats.mac_etype_free, stats.etype_free);
9976 /* Add or delete a filter in SW list */
9978 ethertype_filter = rte_zmalloc("ethertype_filter",
9979 sizeof(*ethertype_filter), 0);
9980 if (ethertype_filter == NULL) {
9981 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9985 rte_memcpy(ethertype_filter, &check_filter,
9986 sizeof(check_filter));
9987 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9989 rte_free(ethertype_filter);
9991 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9998 * Handle operations for ethertype filter.
10001 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10002 enum rte_filter_op filter_op,
10005 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10008 if (filter_op == RTE_ETH_FILTER_NOP)
10012 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10017 switch (filter_op) {
10018 case RTE_ETH_FILTER_ADD:
10019 ret = i40e_ethertype_filter_set(pf,
10020 (struct rte_eth_ethertype_filter *)arg,
10023 case RTE_ETH_FILTER_DELETE:
10024 ret = i40e_ethertype_filter_set(pf,
10025 (struct rte_eth_ethertype_filter *)arg,
10029 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10037 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10038 enum rte_filter_type filter_type,
10039 enum rte_filter_op filter_op,
10047 switch (filter_type) {
10048 case RTE_ETH_FILTER_NONE:
10049 /* For global configuration */
10050 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10052 case RTE_ETH_FILTER_HASH:
10053 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10055 case RTE_ETH_FILTER_MACVLAN:
10056 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10058 case RTE_ETH_FILTER_ETHERTYPE:
10059 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10061 case RTE_ETH_FILTER_TUNNEL:
10062 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10064 case RTE_ETH_FILTER_FDIR:
10065 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10067 case RTE_ETH_FILTER_GENERIC:
10068 if (filter_op != RTE_ETH_FILTER_GET)
10070 *(const void **)arg = &i40e_flow_ops;
10073 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10083 * Check and enable Extended Tag.
10084 * Enabling Extended Tag is important for 40G performance.
10087 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10089 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10093 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10096 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10100 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10101 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10106 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10109 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10113 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10114 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10117 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10118 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10121 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10128 * As some registers wouldn't be reset unless a global hardware reset,
10129 * hardware initialization is needed to put those registers into an
10130 * expected initial state.
10133 i40e_hw_init(struct rte_eth_dev *dev)
10135 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10137 i40e_enable_extended_tag(dev);
10139 /* clear the PF Queue Filter control register */
10140 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10142 /* Disable symmetric hash per port */
10143 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10147 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10148 * however this function will return only one highest pctype index,
10149 * which is not quite correct. This is known problem of i40e driver
10150 * and needs to be fixed later.
10152 enum i40e_filter_pctype
10153 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10156 uint64_t pctype_mask;
10158 if (flow_type < I40E_FLOW_TYPE_MAX) {
10159 pctype_mask = adapter->pctypes_tbl[flow_type];
10160 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10161 if (pctype_mask & (1ULL << i))
10162 return (enum i40e_filter_pctype)i;
10165 return I40E_FILTER_PCTYPE_INVALID;
10169 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10170 enum i40e_filter_pctype pctype)
10173 uint64_t pctype_mask = 1ULL << pctype;
10175 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10177 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10181 return RTE_ETH_FLOW_UNKNOWN;
10185 * On X710, performance number is far from the expectation on recent firmware
10186 * versions; on XL710, performance number is also far from the expectation on
10187 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10188 * mode is enabled and port MAC address is equal to the packet destination MAC
10189 * address. The fix for this issue may not be integrated in the following
10190 * firmware version. So the workaround in software driver is needed. It needs
10191 * to modify the initial values of 3 internal only registers for both X710 and
10192 * XL710. Note that the values for X710 or XL710 could be different, and the
10193 * workaround can be removed when it is fixed in firmware in the future.
10196 /* For both X710 and XL710 */
10197 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10198 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10199 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10201 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10202 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10205 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10206 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10209 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10211 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10212 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10215 * GL_SWR_PM_UP_THR:
10216 * The value is not impacted from the link speed, its value is set according
10217 * to the total number of ports for a better pipe-monitor configuration.
10220 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10222 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10223 .device_id = (dev), \
10224 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10226 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10227 .device_id = (dev), \
10228 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10230 static const struct {
10231 uint16_t device_id;
10233 } swr_pm_table[] = {
10234 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10235 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10236 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10237 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10239 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10240 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10241 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10242 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10243 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10244 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10245 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10249 if (value == NULL) {
10250 PMD_DRV_LOG(ERR, "value is NULL");
10254 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10255 if (hw->device_id == swr_pm_table[i].device_id) {
10256 *value = swr_pm_table[i].val;
10258 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10260 hw->device_id, *value);
10269 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10271 enum i40e_status_code status;
10272 struct i40e_aq_get_phy_abilities_resp phy_ab;
10273 int ret = -ENOTSUP;
10276 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10280 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10283 rte_delay_us(100000);
10285 status = i40e_aq_get_phy_capabilities(hw, false,
10286 true, &phy_ab, NULL);
10294 i40e_configure_registers(struct i40e_hw *hw)
10300 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10301 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10302 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10308 for (i = 0; i < RTE_DIM(reg_table); i++) {
10309 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10310 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10312 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10313 else /* For X710/XL710/XXV710 */
10314 if (hw->aq.fw_maj_ver < 6)
10316 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10319 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10322 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10323 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10325 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10326 else /* For X710/XL710/XXV710 */
10328 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10331 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10334 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10335 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10336 "GL_SWR_PM_UP_THR value fixup",
10341 reg_table[i].val = cfg_val;
10344 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10347 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10348 reg_table[i].addr);
10351 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10352 reg_table[i].addr, reg);
10353 if (reg == reg_table[i].val)
10356 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10357 reg_table[i].val, NULL);
10360 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10361 reg_table[i].val, reg_table[i].addr);
10364 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10365 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10369 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10370 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10371 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10372 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10374 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10379 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10380 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10384 /* Configure for double VLAN RX stripping */
10385 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10386 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10387 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10388 ret = i40e_aq_debug_write_register(hw,
10389 I40E_VSI_TSR(vsi->vsi_id),
10392 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10394 return I40E_ERR_CONFIG;
10398 /* Configure for double VLAN TX insertion */
10399 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10400 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10401 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10402 ret = i40e_aq_debug_write_register(hw,
10403 I40E_VSI_L2TAGSTXVALID(
10404 vsi->vsi_id), reg, NULL);
10407 "Failed to update VSI_L2TAGSTXVALID[%d]",
10409 return I40E_ERR_CONFIG;
10417 * i40e_aq_add_mirror_rule
10418 * @hw: pointer to the hardware structure
10419 * @seid: VEB seid to add mirror rule to
10420 * @dst_id: destination vsi seid
10421 * @entries: Buffer which contains the entities to be mirrored
10422 * @count: number of entities contained in the buffer
10423 * @rule_id:the rule_id of the rule to be added
10425 * Add a mirror rule for a given veb.
10428 static enum i40e_status_code
10429 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10430 uint16_t seid, uint16_t dst_id,
10431 uint16_t rule_type, uint16_t *entries,
10432 uint16_t count, uint16_t *rule_id)
10434 struct i40e_aq_desc desc;
10435 struct i40e_aqc_add_delete_mirror_rule cmd;
10436 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10437 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10440 enum i40e_status_code status;
10442 i40e_fill_default_direct_cmd_desc(&desc,
10443 i40e_aqc_opc_add_mirror_rule);
10444 memset(&cmd, 0, sizeof(cmd));
10446 buff_len = sizeof(uint16_t) * count;
10447 desc.datalen = rte_cpu_to_le_16(buff_len);
10449 desc.flags |= rte_cpu_to_le_16(
10450 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10451 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10452 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10453 cmd.num_entries = rte_cpu_to_le_16(count);
10454 cmd.seid = rte_cpu_to_le_16(seid);
10455 cmd.destination = rte_cpu_to_le_16(dst_id);
10457 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10458 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10460 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10461 hw->aq.asq_last_status, resp->rule_id,
10462 resp->mirror_rules_used, resp->mirror_rules_free);
10463 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10469 * i40e_aq_del_mirror_rule
10470 * @hw: pointer to the hardware structure
10471 * @seid: VEB seid to add mirror rule to
10472 * @entries: Buffer which contains the entities to be mirrored
10473 * @count: number of entities contained in the buffer
10474 * @rule_id:the rule_id of the rule to be delete
10476 * Delete a mirror rule for a given veb.
10479 static enum i40e_status_code
10480 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10481 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10482 uint16_t count, uint16_t rule_id)
10484 struct i40e_aq_desc desc;
10485 struct i40e_aqc_add_delete_mirror_rule cmd;
10486 uint16_t buff_len = 0;
10487 enum i40e_status_code status;
10490 i40e_fill_default_direct_cmd_desc(&desc,
10491 i40e_aqc_opc_delete_mirror_rule);
10492 memset(&cmd, 0, sizeof(cmd));
10493 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10494 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10496 cmd.num_entries = count;
10497 buff_len = sizeof(uint16_t) * count;
10498 desc.datalen = rte_cpu_to_le_16(buff_len);
10499 buff = (void *)entries;
10501 /* rule id is filled in destination field for deleting mirror rule */
10502 cmd.destination = rte_cpu_to_le_16(rule_id);
10504 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10505 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10506 cmd.seid = rte_cpu_to_le_16(seid);
10508 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10509 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10515 * i40e_mirror_rule_set
10516 * @dev: pointer to the hardware structure
10517 * @mirror_conf: mirror rule info
10518 * @sw_id: mirror rule's sw_id
10519 * @on: enable/disable
10521 * set a mirror rule.
10525 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10526 struct rte_eth_mirror_conf *mirror_conf,
10527 uint8_t sw_id, uint8_t on)
10529 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10530 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10531 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10532 struct i40e_mirror_rule *parent = NULL;
10533 uint16_t seid, dst_seid, rule_id;
10537 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10539 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10541 "mirror rule can not be configured without veb or vfs.");
10544 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10545 PMD_DRV_LOG(ERR, "mirror table is full.");
10548 if (mirror_conf->dst_pool > pf->vf_num) {
10549 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10550 mirror_conf->dst_pool);
10554 seid = pf->main_vsi->veb->seid;
10556 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10557 if (sw_id <= it->index) {
10563 if (mirr_rule && sw_id == mirr_rule->index) {
10565 PMD_DRV_LOG(ERR, "mirror rule exists.");
10568 ret = i40e_aq_del_mirror_rule(hw, seid,
10569 mirr_rule->rule_type,
10570 mirr_rule->entries,
10571 mirr_rule->num_entries, mirr_rule->id);
10574 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10575 ret, hw->aq.asq_last_status);
10578 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10579 rte_free(mirr_rule);
10580 pf->nb_mirror_rule--;
10584 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10588 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10589 sizeof(struct i40e_mirror_rule) , 0);
10591 PMD_DRV_LOG(ERR, "failed to allocate memory");
10592 return I40E_ERR_NO_MEMORY;
10594 switch (mirror_conf->rule_type) {
10595 case ETH_MIRROR_VLAN:
10596 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10597 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10598 mirr_rule->entries[j] =
10599 mirror_conf->vlan.vlan_id[i];
10604 PMD_DRV_LOG(ERR, "vlan is not specified.");
10605 rte_free(mirr_rule);
10608 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10610 case ETH_MIRROR_VIRTUAL_POOL_UP:
10611 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10612 /* check if the specified pool bit is out of range */
10613 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10614 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10615 rte_free(mirr_rule);
10618 for (i = 0, j = 0; i < pf->vf_num; i++) {
10619 if (mirror_conf->pool_mask & (1ULL << i)) {
10620 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10624 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10625 /* add pf vsi to entries */
10626 mirr_rule->entries[j] = pf->main_vsi_seid;
10630 PMD_DRV_LOG(ERR, "pool is not specified.");
10631 rte_free(mirr_rule);
10634 /* egress and ingress in aq commands means from switch but not port */
10635 mirr_rule->rule_type =
10636 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10637 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10638 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10640 case ETH_MIRROR_UPLINK_PORT:
10641 /* egress and ingress in aq commands means from switch but not port*/
10642 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10644 case ETH_MIRROR_DOWNLINK_PORT:
10645 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10648 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10649 mirror_conf->rule_type);
10650 rte_free(mirr_rule);
10654 /* If the dst_pool is equal to vf_num, consider it as PF */
10655 if (mirror_conf->dst_pool == pf->vf_num)
10656 dst_seid = pf->main_vsi_seid;
10658 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10660 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10661 mirr_rule->rule_type, mirr_rule->entries,
10665 "failed to add mirror rule: ret = %d, aq_err = %d.",
10666 ret, hw->aq.asq_last_status);
10667 rte_free(mirr_rule);
10671 mirr_rule->index = sw_id;
10672 mirr_rule->num_entries = j;
10673 mirr_rule->id = rule_id;
10674 mirr_rule->dst_vsi_seid = dst_seid;
10677 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10679 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10681 pf->nb_mirror_rule++;
10686 * i40e_mirror_rule_reset
10687 * @dev: pointer to the device
10688 * @sw_id: mirror rule's sw_id
10690 * reset a mirror rule.
10694 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10696 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10697 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10698 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10702 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10704 seid = pf->main_vsi->veb->seid;
10706 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10707 if (sw_id == it->index) {
10713 ret = i40e_aq_del_mirror_rule(hw, seid,
10714 mirr_rule->rule_type,
10715 mirr_rule->entries,
10716 mirr_rule->num_entries, mirr_rule->id);
10719 "failed to remove mirror rule: status = %d, aq_err = %d.",
10720 ret, hw->aq.asq_last_status);
10723 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10724 rte_free(mirr_rule);
10725 pf->nb_mirror_rule--;
10727 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10734 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10736 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10737 uint64_t systim_cycles;
10739 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10740 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10743 return systim_cycles;
10747 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10750 uint64_t rx_tstamp;
10752 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10753 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10760 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10762 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10763 uint64_t tx_tstamp;
10765 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10766 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10773 i40e_start_timecounters(struct rte_eth_dev *dev)
10775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10776 struct i40e_adapter *adapter =
10777 (struct i40e_adapter *)dev->data->dev_private;
10778 struct rte_eth_link link;
10779 uint32_t tsync_inc_l;
10780 uint32_t tsync_inc_h;
10782 /* Get current link speed. */
10783 i40e_dev_link_update(dev, 1);
10784 rte_eth_linkstatus_get(dev, &link);
10786 switch (link.link_speed) {
10787 case ETH_SPEED_NUM_40G:
10788 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10789 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10791 case ETH_SPEED_NUM_10G:
10792 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10793 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10795 case ETH_SPEED_NUM_1G:
10796 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10797 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10804 /* Set the timesync increment value. */
10805 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10806 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10808 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10809 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10810 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10812 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10813 adapter->systime_tc.cc_shift = 0;
10814 adapter->systime_tc.nsec_mask = 0;
10816 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10817 adapter->rx_tstamp_tc.cc_shift = 0;
10818 adapter->rx_tstamp_tc.nsec_mask = 0;
10820 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10821 adapter->tx_tstamp_tc.cc_shift = 0;
10822 adapter->tx_tstamp_tc.nsec_mask = 0;
10826 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10828 struct i40e_adapter *adapter =
10829 (struct i40e_adapter *)dev->data->dev_private;
10831 adapter->systime_tc.nsec += delta;
10832 adapter->rx_tstamp_tc.nsec += delta;
10833 adapter->tx_tstamp_tc.nsec += delta;
10839 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10842 struct i40e_adapter *adapter =
10843 (struct i40e_adapter *)dev->data->dev_private;
10845 ns = rte_timespec_to_ns(ts);
10847 /* Set the timecounters to a new value. */
10848 adapter->systime_tc.nsec = ns;
10849 adapter->rx_tstamp_tc.nsec = ns;
10850 adapter->tx_tstamp_tc.nsec = ns;
10856 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10858 uint64_t ns, systime_cycles;
10859 struct i40e_adapter *adapter =
10860 (struct i40e_adapter *)dev->data->dev_private;
10862 systime_cycles = i40e_read_systime_cyclecounter(dev);
10863 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10864 *ts = rte_ns_to_timespec(ns);
10870 i40e_timesync_enable(struct rte_eth_dev *dev)
10872 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10873 uint32_t tsync_ctl_l;
10874 uint32_t tsync_ctl_h;
10876 /* Stop the timesync system time. */
10877 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10878 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10879 /* Reset the timesync system time value. */
10880 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10881 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10883 i40e_start_timecounters(dev);
10885 /* Clear timesync registers. */
10886 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10887 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10888 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10889 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10890 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10891 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10893 /* Enable timestamping of PTP packets. */
10894 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10895 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10897 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10898 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10899 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10901 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10902 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10908 i40e_timesync_disable(struct rte_eth_dev *dev)
10910 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10911 uint32_t tsync_ctl_l;
10912 uint32_t tsync_ctl_h;
10914 /* Disable timestamping of transmitted PTP packets. */
10915 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10916 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10918 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10919 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10921 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10922 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10924 /* Reset the timesync increment value. */
10925 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10926 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10932 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10933 struct timespec *timestamp, uint32_t flags)
10935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10936 struct i40e_adapter *adapter =
10937 (struct i40e_adapter *)dev->data->dev_private;
10939 uint32_t sync_status;
10940 uint32_t index = flags & 0x03;
10941 uint64_t rx_tstamp_cycles;
10944 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10945 if ((sync_status & (1 << index)) == 0)
10948 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10949 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10950 *timestamp = rte_ns_to_timespec(ns);
10956 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10957 struct timespec *timestamp)
10959 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10960 struct i40e_adapter *adapter =
10961 (struct i40e_adapter *)dev->data->dev_private;
10963 uint32_t sync_status;
10964 uint64_t tx_tstamp_cycles;
10967 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10968 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10971 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10972 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10973 *timestamp = rte_ns_to_timespec(ns);
10979 * i40e_parse_dcb_configure - parse dcb configure from user
10980 * @dev: the device being configured
10981 * @dcb_cfg: pointer of the result of parse
10982 * @*tc_map: bit map of enabled traffic classes
10984 * Returns 0 on success, negative value on failure
10987 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10988 struct i40e_dcbx_config *dcb_cfg,
10991 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10992 uint8_t i, tc_bw, bw_lf;
10994 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10996 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10997 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10998 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11002 /* assume each tc has the same bw */
11003 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11004 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11005 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11006 /* to ensure the sum of tcbw is equal to 100 */
11007 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11008 for (i = 0; i < bw_lf; i++)
11009 dcb_cfg->etscfg.tcbwtable[i]++;
11011 /* assume each tc has the same Transmission Selection Algorithm */
11012 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11013 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11015 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11016 dcb_cfg->etscfg.prioritytable[i] =
11017 dcb_rx_conf->dcb_tc[i];
11019 /* FW needs one App to configure HW */
11020 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11021 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11022 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11023 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11025 if (dcb_rx_conf->nb_tcs == 0)
11026 *tc_map = 1; /* tc0 only */
11028 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11030 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11031 dcb_cfg->pfc.willing = 0;
11032 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11033 dcb_cfg->pfc.pfcenable = *tc_map;
11039 static enum i40e_status_code
11040 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11041 struct i40e_aqc_vsi_properties_data *info,
11042 uint8_t enabled_tcmap)
11044 enum i40e_status_code ret;
11045 int i, total_tc = 0;
11046 uint16_t qpnum_per_tc, bsf, qp_idx;
11047 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11048 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11049 uint16_t used_queues;
11051 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11052 if (ret != I40E_SUCCESS)
11055 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11056 if (enabled_tcmap & (1 << i))
11061 vsi->enabled_tc = enabled_tcmap;
11063 /* different VSI has different queues assigned */
11064 if (vsi->type == I40E_VSI_MAIN)
11065 used_queues = dev_data->nb_rx_queues -
11066 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11067 else if (vsi->type == I40E_VSI_VMDQ2)
11068 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11070 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11071 return I40E_ERR_NO_AVAILABLE_VSI;
11074 qpnum_per_tc = used_queues / total_tc;
11075 /* Number of queues per enabled TC */
11076 if (qpnum_per_tc == 0) {
11077 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11078 return I40E_ERR_INVALID_QP_ID;
11080 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11081 I40E_MAX_Q_PER_TC);
11082 bsf = rte_bsf32(qpnum_per_tc);
11085 * Configure TC and queue mapping parameters, for enabled TC,
11086 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11087 * default queue will serve it.
11090 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11091 if (vsi->enabled_tc & (1 << i)) {
11092 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11093 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11094 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11095 qp_idx += qpnum_per_tc;
11097 info->tc_mapping[i] = 0;
11100 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11101 if (vsi->type == I40E_VSI_SRIOV) {
11102 info->mapping_flags |=
11103 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11104 for (i = 0; i < vsi->nb_qps; i++)
11105 info->queue_mapping[i] =
11106 rte_cpu_to_le_16(vsi->base_queue + i);
11108 info->mapping_flags |=
11109 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11110 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11112 info->valid_sections |=
11113 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11115 return I40E_SUCCESS;
11119 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11120 * @veb: VEB to be configured
11121 * @tc_map: enabled TC bitmap
11123 * Returns 0 on success, negative value on failure
11125 static enum i40e_status_code
11126 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11128 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11129 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11130 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11131 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11132 enum i40e_status_code ret = I40E_SUCCESS;
11136 /* Check if enabled_tc is same as existing or new TCs */
11137 if (veb->enabled_tc == tc_map)
11140 /* configure tc bandwidth */
11141 memset(&veb_bw, 0, sizeof(veb_bw));
11142 veb_bw.tc_valid_bits = tc_map;
11143 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11144 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11145 if (tc_map & BIT_ULL(i))
11146 veb_bw.tc_bw_share_credits[i] = 1;
11148 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11152 "AQ command Config switch_comp BW allocation per TC failed = %d",
11153 hw->aq.asq_last_status);
11157 memset(&ets_query, 0, sizeof(ets_query));
11158 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11160 if (ret != I40E_SUCCESS) {
11162 "Failed to get switch_comp ETS configuration %u",
11163 hw->aq.asq_last_status);
11166 memset(&bw_query, 0, sizeof(bw_query));
11167 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11169 if (ret != I40E_SUCCESS) {
11171 "Failed to get switch_comp bandwidth configuration %u",
11172 hw->aq.asq_last_status);
11176 /* store and print out BW info */
11177 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11178 veb->bw_info.bw_max = ets_query.tc_bw_max;
11179 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11180 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11181 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11182 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11183 I40E_16_BIT_WIDTH);
11184 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11185 veb->bw_info.bw_ets_share_credits[i] =
11186 bw_query.tc_bw_share_credits[i];
11187 veb->bw_info.bw_ets_credits[i] =
11188 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11189 /* 4 bits per TC, 4th bit is reserved */
11190 veb->bw_info.bw_ets_max[i] =
11191 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11192 RTE_LEN2MASK(3, uint8_t));
11193 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11194 veb->bw_info.bw_ets_share_credits[i]);
11195 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11196 veb->bw_info.bw_ets_credits[i]);
11197 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11198 veb->bw_info.bw_ets_max[i]);
11201 veb->enabled_tc = tc_map;
11208 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11209 * @vsi: VSI to be configured
11210 * @tc_map: enabled TC bitmap
11212 * Returns 0 on success, negative value on failure
11214 static enum i40e_status_code
11215 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11217 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11218 struct i40e_vsi_context ctxt;
11219 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11220 enum i40e_status_code ret = I40E_SUCCESS;
11223 /* Check if enabled_tc is same as existing or new TCs */
11224 if (vsi->enabled_tc == tc_map)
11227 /* configure tc bandwidth */
11228 memset(&bw_data, 0, sizeof(bw_data));
11229 bw_data.tc_valid_bits = tc_map;
11230 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11231 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11232 if (tc_map & BIT_ULL(i))
11233 bw_data.tc_bw_credits[i] = 1;
11235 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11238 "AQ command Config VSI BW allocation per TC failed = %d",
11239 hw->aq.asq_last_status);
11242 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11243 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11245 /* Update Queue Pairs Mapping for currently enabled UPs */
11246 ctxt.seid = vsi->seid;
11247 ctxt.pf_num = hw->pf_id;
11249 ctxt.uplink_seid = vsi->uplink_seid;
11250 ctxt.info = vsi->info;
11252 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11256 /* Update the VSI after updating the VSI queue-mapping information */
11257 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11259 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11260 hw->aq.asq_last_status);
11263 /* update the local VSI info with updated queue map */
11264 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11265 sizeof(vsi->info.tc_mapping));
11266 rte_memcpy(&vsi->info.queue_mapping,
11267 &ctxt.info.queue_mapping,
11268 sizeof(vsi->info.queue_mapping));
11269 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11270 vsi->info.valid_sections = 0;
11272 /* query and update current VSI BW information */
11273 ret = i40e_vsi_get_bw_config(vsi);
11276 "Failed updating vsi bw info, err %s aq_err %s",
11277 i40e_stat_str(hw, ret),
11278 i40e_aq_str(hw, hw->aq.asq_last_status));
11282 vsi->enabled_tc = tc_map;
11289 * i40e_dcb_hw_configure - program the dcb setting to hw
11290 * @pf: pf the configuration is taken on
11291 * @new_cfg: new configuration
11292 * @tc_map: enabled TC bitmap
11294 * Returns 0 on success, negative value on failure
11296 static enum i40e_status_code
11297 i40e_dcb_hw_configure(struct i40e_pf *pf,
11298 struct i40e_dcbx_config *new_cfg,
11301 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11302 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11303 struct i40e_vsi *main_vsi = pf->main_vsi;
11304 struct i40e_vsi_list *vsi_list;
11305 enum i40e_status_code ret;
11309 /* Use the FW API if FW > v4.4*/
11310 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11311 (hw->aq.fw_maj_ver >= 5))) {
11313 "FW < v4.4, can not use FW LLDP API to configure DCB");
11314 return I40E_ERR_FIRMWARE_API_VERSION;
11317 /* Check if need reconfiguration */
11318 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11319 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11320 return I40E_SUCCESS;
11323 /* Copy the new config to the current config */
11324 *old_cfg = *new_cfg;
11325 old_cfg->etsrec = old_cfg->etscfg;
11326 ret = i40e_set_dcb_config(hw);
11328 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11329 i40e_stat_str(hw, ret),
11330 i40e_aq_str(hw, hw->aq.asq_last_status));
11333 /* set receive Arbiter to RR mode and ETS scheme by default */
11334 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11335 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11336 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11337 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11338 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11339 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11340 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11341 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11342 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11343 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11344 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11345 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11346 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11348 /* get local mib to check whether it is configured correctly */
11350 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11351 /* Get Local DCB Config */
11352 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11353 &hw->local_dcbx_config);
11355 /* if Veb is created, need to update TC of it at first */
11356 if (main_vsi->veb) {
11357 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11359 PMD_INIT_LOG(WARNING,
11360 "Failed configuring TC for VEB seid=%d",
11361 main_vsi->veb->seid);
11363 /* Update each VSI */
11364 i40e_vsi_config_tc(main_vsi, tc_map);
11365 if (main_vsi->veb) {
11366 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11367 /* Beside main VSI and VMDQ VSIs, only enable default
11368 * TC for other VSIs
11370 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11371 ret = i40e_vsi_config_tc(vsi_list->vsi,
11374 ret = i40e_vsi_config_tc(vsi_list->vsi,
11375 I40E_DEFAULT_TCMAP);
11377 PMD_INIT_LOG(WARNING,
11378 "Failed configuring TC for VSI seid=%d",
11379 vsi_list->vsi->seid);
11383 return I40E_SUCCESS;
11387 * i40e_dcb_init_configure - initial dcb config
11388 * @dev: device being configured
11389 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11391 * Returns 0 on success, negative value on failure
11394 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11400 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11401 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11405 /* DCB initialization:
11406 * Update DCB configuration from the Firmware and configure
11407 * LLDP MIB change event.
11409 if (sw_dcb == TRUE) {
11410 /* When using NVM 6.01 or later, the RX data path does
11411 * not hang if the FW LLDP is stopped.
11413 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11414 ((hw->nvm.version >> 4) & 0xff) >= 1) {
11415 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11416 if (ret != I40E_SUCCESS)
11417 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11420 ret = i40e_init_dcb(hw);
11421 /* If lldp agent is stopped, the return value from
11422 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11423 * adminq status. Otherwise, it should return success.
11425 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11426 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11427 memset(&hw->local_dcbx_config, 0,
11428 sizeof(struct i40e_dcbx_config));
11429 /* set dcb default configuration */
11430 hw->local_dcbx_config.etscfg.willing = 0;
11431 hw->local_dcbx_config.etscfg.maxtcs = 0;
11432 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11433 hw->local_dcbx_config.etscfg.tsatable[0] =
11435 /* all UPs mapping to TC0 */
11436 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11437 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11438 hw->local_dcbx_config.etsrec =
11439 hw->local_dcbx_config.etscfg;
11440 hw->local_dcbx_config.pfc.willing = 0;
11441 hw->local_dcbx_config.pfc.pfccap =
11442 I40E_MAX_TRAFFIC_CLASS;
11443 /* FW needs one App to configure HW */
11444 hw->local_dcbx_config.numapps = 1;
11445 hw->local_dcbx_config.app[0].selector =
11446 I40E_APP_SEL_ETHTYPE;
11447 hw->local_dcbx_config.app[0].priority = 3;
11448 hw->local_dcbx_config.app[0].protocolid =
11449 I40E_APP_PROTOID_FCOE;
11450 ret = i40e_set_dcb_config(hw);
11453 "default dcb config fails. err = %d, aq_err = %d.",
11454 ret, hw->aq.asq_last_status);
11459 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11460 ret, hw->aq.asq_last_status);
11464 ret = i40e_aq_start_lldp(hw, NULL);
11465 if (ret != I40E_SUCCESS)
11466 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11468 ret = i40e_init_dcb(hw);
11470 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11472 "HW doesn't support DCBX offload.");
11477 "DCBX configuration failed, err = %d, aq_err = %d.",
11478 ret, hw->aq.asq_last_status);
11486 * i40e_dcb_setup - setup dcb related config
11487 * @dev: device being configured
11489 * Returns 0 on success, negative value on failure
11492 i40e_dcb_setup(struct rte_eth_dev *dev)
11494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11495 struct i40e_dcbx_config dcb_cfg;
11496 uint8_t tc_map = 0;
11499 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11500 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11504 if (pf->vf_num != 0)
11505 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11507 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11509 PMD_INIT_LOG(ERR, "invalid dcb config");
11512 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11514 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11522 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11523 struct rte_eth_dcb_info *dcb_info)
11525 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11526 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11527 struct i40e_vsi *vsi = pf->main_vsi;
11528 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11529 uint16_t bsf, tc_mapping;
11532 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11533 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11535 dcb_info->nb_tcs = 1;
11536 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11537 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11538 for (i = 0; i < dcb_info->nb_tcs; i++)
11539 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11541 /* get queue mapping if vmdq is disabled */
11542 if (!pf->nb_cfg_vmdq_vsi) {
11543 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11544 if (!(vsi->enabled_tc & (1 << i)))
11546 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11547 dcb_info->tc_queue.tc_rxq[j][i].base =
11548 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11549 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11550 dcb_info->tc_queue.tc_txq[j][i].base =
11551 dcb_info->tc_queue.tc_rxq[j][i].base;
11552 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11553 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11554 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11555 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11556 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11561 /* get queue mapping if vmdq is enabled */
11563 vsi = pf->vmdq[j].vsi;
11564 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11565 if (!(vsi->enabled_tc & (1 << i)))
11567 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11568 dcb_info->tc_queue.tc_rxq[j][i].base =
11569 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11570 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11571 dcb_info->tc_queue.tc_txq[j][i].base =
11572 dcb_info->tc_queue.tc_rxq[j][i].base;
11573 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11574 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11575 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11576 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11577 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11580 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11585 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11587 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11588 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11589 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11590 uint16_t msix_intr;
11592 msix_intr = intr_handle->intr_vec[queue_id];
11593 if (msix_intr == I40E_MISC_VEC_ID)
11594 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11595 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11596 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11597 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11600 I40E_PFINT_DYN_CTLN(msix_intr -
11601 I40E_RX_VEC_START),
11602 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11603 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11604 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11606 I40E_WRITE_FLUSH(hw);
11607 rte_intr_enable(&pci_dev->intr_handle);
11613 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11615 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11616 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11618 uint16_t msix_intr;
11620 msix_intr = intr_handle->intr_vec[queue_id];
11621 if (msix_intr == I40E_MISC_VEC_ID)
11622 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11623 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11626 I40E_PFINT_DYN_CTLN(msix_intr -
11627 I40E_RX_VEC_START),
11628 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11629 I40E_WRITE_FLUSH(hw);
11635 * This function is used to check if the register is valid.
11636 * Below is the valid registers list for X722 only:
11640 * 0x208e00--0x209000
11641 * 0x20be00--0x20c000
11642 * 0x263c00--0x264000
11643 * 0x265c00--0x266000
11645 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11647 if ((type != I40E_MAC_X722) &&
11648 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11649 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11650 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11651 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11652 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11653 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11654 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11660 static int i40e_get_regs(struct rte_eth_dev *dev,
11661 struct rte_dev_reg_info *regs)
11663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11664 uint32_t *ptr_data = regs->data;
11665 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11666 const struct i40e_reg_info *reg_info;
11668 if (ptr_data == NULL) {
11669 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11670 regs->width = sizeof(uint32_t);
11674 /* The first few registers have to be read using AQ operations */
11676 while (i40e_regs_adminq[reg_idx].name) {
11677 reg_info = &i40e_regs_adminq[reg_idx++];
11678 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11680 arr_idx2 <= reg_info->count2;
11682 reg_offset = arr_idx * reg_info->stride1 +
11683 arr_idx2 * reg_info->stride2;
11684 reg_offset += reg_info->base_addr;
11685 ptr_data[reg_offset >> 2] =
11686 i40e_read_rx_ctl(hw, reg_offset);
11690 /* The remaining registers can be read using primitives */
11692 while (i40e_regs_others[reg_idx].name) {
11693 reg_info = &i40e_regs_others[reg_idx++];
11694 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11696 arr_idx2 <= reg_info->count2;
11698 reg_offset = arr_idx * reg_info->stride1 +
11699 arr_idx2 * reg_info->stride2;
11700 reg_offset += reg_info->base_addr;
11701 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11702 ptr_data[reg_offset >> 2] = 0;
11704 ptr_data[reg_offset >> 2] =
11705 I40E_READ_REG(hw, reg_offset);
11712 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11716 /* Convert word count to byte count */
11717 return hw->nvm.sr_size << 1;
11720 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11721 struct rte_dev_eeprom_info *eeprom)
11723 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11724 uint16_t *data = eeprom->data;
11725 uint16_t offset, length, cnt_words;
11728 offset = eeprom->offset >> 1;
11729 length = eeprom->length >> 1;
11730 cnt_words = length;
11732 if (offset > hw->nvm.sr_size ||
11733 offset + length > hw->nvm.sr_size) {
11734 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11738 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11740 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11741 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11742 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11749 static int i40e_get_module_info(struct rte_eth_dev *dev,
11750 struct rte_eth_dev_module_info *modinfo)
11752 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11753 uint32_t sff8472_comp = 0;
11754 uint32_t sff8472_swap = 0;
11755 uint32_t sff8636_rev = 0;
11756 i40e_status status;
11759 /* Check if firmware supports reading module EEPROM. */
11760 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11762 "Module EEPROM memory read not supported. "
11763 "Please update the NVM image.\n");
11767 status = i40e_update_link_info(hw);
11771 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11773 "Cannot read module EEPROM memory. "
11774 "No module connected.\n");
11778 type = hw->phy.link_info.module_type[0];
11781 case I40E_MODULE_TYPE_SFP:
11782 status = i40e_aq_get_phy_register(hw,
11783 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11784 I40E_I2C_EEPROM_DEV_ADDR, 1,
11785 I40E_MODULE_SFF_8472_COMP,
11786 &sff8472_comp, NULL);
11790 status = i40e_aq_get_phy_register(hw,
11791 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11792 I40E_I2C_EEPROM_DEV_ADDR, 1,
11793 I40E_MODULE_SFF_8472_SWAP,
11794 &sff8472_swap, NULL);
11798 /* Check if the module requires address swap to access
11799 * the other EEPROM memory page.
11801 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11802 PMD_DRV_LOG(WARNING,
11803 "Module address swap to access "
11804 "page 0xA2 is not supported.\n");
11805 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11806 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11807 } else if (sff8472_comp == 0x00) {
11808 /* Module is not SFF-8472 compliant */
11809 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11810 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11812 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11813 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11816 case I40E_MODULE_TYPE_QSFP_PLUS:
11817 /* Read from memory page 0. */
11818 status = i40e_aq_get_phy_register(hw,
11819 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11821 I40E_MODULE_REVISION_ADDR,
11822 &sff8636_rev, NULL);
11825 /* Determine revision compliance byte */
11826 if (sff8636_rev > 0x02) {
11827 /* Module is SFF-8636 compliant */
11828 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11829 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11831 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11832 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11835 case I40E_MODULE_TYPE_QSFP28:
11836 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11837 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11840 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11846 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11847 struct rte_dev_eeprom_info *info)
11849 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11850 bool is_sfp = false;
11851 i40e_status status;
11852 uint8_t *data = info->data;
11853 uint32_t value = 0;
11856 if (!info || !info->length || !data)
11859 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11862 for (i = 0; i < info->length; i++) {
11863 u32 offset = i + info->offset;
11864 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11866 /* Check if we need to access the other memory page */
11868 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11869 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11870 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11873 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11874 /* Compute memory page number and offset. */
11875 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11879 status = i40e_aq_get_phy_register(hw,
11880 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11881 addr, offset, 1, &value, NULL);
11884 data[i] = (uint8_t)value;
11889 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11890 struct ether_addr *mac_addr)
11892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11893 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11894 struct i40e_vsi *vsi = pf->main_vsi;
11895 struct i40e_mac_filter_info mac_filter;
11896 struct i40e_mac_filter *f;
11899 if (!is_valid_assigned_ether_addr(mac_addr)) {
11900 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11904 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11905 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11910 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11914 mac_filter = f->mac_info;
11915 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11916 if (ret != I40E_SUCCESS) {
11917 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11920 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11921 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11922 if (ret != I40E_SUCCESS) {
11923 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11926 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11928 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11929 mac_addr->addr_bytes, NULL);
11930 if (ret != I40E_SUCCESS) {
11931 PMD_DRV_LOG(ERR, "Failed to change mac");
11939 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11942 struct rte_eth_dev_data *dev_data = pf->dev_data;
11943 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11946 /* check if mtu is within the allowed range */
11947 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11950 /* mtu setting is forbidden if port is start */
11951 if (dev_data->dev_started) {
11952 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11953 dev_data->port_id);
11957 if (frame_size > ETHER_MAX_LEN)
11958 dev_data->dev_conf.rxmode.offloads |=
11959 DEV_RX_OFFLOAD_JUMBO_FRAME;
11961 dev_data->dev_conf.rxmode.offloads &=
11962 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11964 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11969 /* Restore ethertype filter */
11971 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11973 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11974 struct i40e_ethertype_filter_list
11975 *ethertype_list = &pf->ethertype.ethertype_list;
11976 struct i40e_ethertype_filter *f;
11977 struct i40e_control_filter_stats stats;
11980 TAILQ_FOREACH(f, ethertype_list, rules) {
11982 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11983 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11984 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11985 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11986 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11988 memset(&stats, 0, sizeof(stats));
11989 i40e_aq_add_rem_control_packet_filter(hw,
11990 f->input.mac_addr.addr_bytes,
11991 f->input.ether_type,
11992 flags, pf->main_vsi->seid,
11993 f->queue, 1, &stats, NULL);
11995 PMD_DRV_LOG(INFO, "Ethertype filter:"
11996 " mac_etype_used = %u, etype_used = %u,"
11997 " mac_etype_free = %u, etype_free = %u",
11998 stats.mac_etype_used, stats.etype_used,
11999 stats.mac_etype_free, stats.etype_free);
12002 /* Restore tunnel filter */
12004 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12006 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12007 struct i40e_vsi *vsi;
12008 struct i40e_pf_vf *vf;
12009 struct i40e_tunnel_filter_list
12010 *tunnel_list = &pf->tunnel.tunnel_list;
12011 struct i40e_tunnel_filter *f;
12012 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12013 bool big_buffer = 0;
12015 TAILQ_FOREACH(f, tunnel_list, rules) {
12017 vsi = pf->main_vsi;
12019 vf = &pf->vfs[f->vf_id];
12022 memset(&cld_filter, 0, sizeof(cld_filter));
12023 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
12024 (struct ether_addr *)&cld_filter.element.outer_mac);
12025 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
12026 (struct ether_addr *)&cld_filter.element.inner_mac);
12027 cld_filter.element.inner_vlan = f->input.inner_vlan;
12028 cld_filter.element.flags = f->input.flags;
12029 cld_filter.element.tenant_id = f->input.tenant_id;
12030 cld_filter.element.queue_number = f->queue;
12031 rte_memcpy(cld_filter.general_fields,
12032 f->input.general_fields,
12033 sizeof(f->input.general_fields));
12035 if (((f->input.flags &
12036 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12037 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12039 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12040 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12042 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12043 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12047 i40e_aq_add_cloud_filters_bb(hw,
12048 vsi->seid, &cld_filter, 1);
12050 i40e_aq_add_cloud_filters(hw, vsi->seid,
12051 &cld_filter.element, 1);
12055 /* Restore rss filter */
12057 i40e_rss_filter_restore(struct i40e_pf *pf)
12059 struct i40e_rte_flow_rss_conf *conf =
12061 if (conf->conf.queue_num)
12062 i40e_config_rss_filter(pf, conf, TRUE);
12066 i40e_filter_restore(struct i40e_pf *pf)
12068 i40e_ethertype_filter_restore(pf);
12069 i40e_tunnel_filter_restore(pf);
12070 i40e_fdir_filter_restore(pf);
12071 i40e_rss_filter_restore(pf);
12075 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12077 if (strcmp(dev->device->driver->name, drv->driver.name))
12084 is_i40e_supported(struct rte_eth_dev *dev)
12086 return is_device_supported(dev, &rte_i40e_pmd);
12089 struct i40e_customized_pctype*
12090 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12094 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12095 if (pf->customized_pctype[i].index == index)
12096 return &pf->customized_pctype[i];
12102 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12103 uint32_t pkg_size, uint32_t proto_num,
12104 struct rte_pmd_i40e_proto_info *proto,
12105 enum rte_pmd_i40e_package_op op)
12107 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12108 uint32_t pctype_num;
12109 struct rte_pmd_i40e_ptype_info *pctype;
12110 uint32_t buff_size;
12111 struct i40e_customized_pctype *new_pctype = NULL;
12113 uint8_t pctype_value;
12118 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12119 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12120 PMD_DRV_LOG(ERR, "Unsupported operation.");
12124 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12125 (uint8_t *)&pctype_num, sizeof(pctype_num),
12126 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12128 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12132 PMD_DRV_LOG(INFO, "No new pctype added");
12136 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12137 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12139 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12142 /* get information about new pctype list */
12143 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12144 (uint8_t *)pctype, buff_size,
12145 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12147 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12152 /* Update customized pctype. */
12153 for (i = 0; i < pctype_num; i++) {
12154 pctype_value = pctype[i].ptype_id;
12155 memset(name, 0, sizeof(name));
12156 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12157 proto_id = pctype[i].protocols[j];
12158 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12160 for (n = 0; n < proto_num; n++) {
12161 if (proto[n].proto_id != proto_id)
12163 strcat(name, proto[n].name);
12168 name[strlen(name) - 1] = '\0';
12169 if (!strcmp(name, "GTPC"))
12171 i40e_find_customized_pctype(pf,
12172 I40E_CUSTOMIZED_GTPC);
12173 else if (!strcmp(name, "GTPU_IPV4"))
12175 i40e_find_customized_pctype(pf,
12176 I40E_CUSTOMIZED_GTPU_IPV4);
12177 else if (!strcmp(name, "GTPU_IPV6"))
12179 i40e_find_customized_pctype(pf,
12180 I40E_CUSTOMIZED_GTPU_IPV6);
12181 else if (!strcmp(name, "GTPU"))
12183 i40e_find_customized_pctype(pf,
12184 I40E_CUSTOMIZED_GTPU);
12186 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12187 new_pctype->pctype = pctype_value;
12188 new_pctype->valid = true;
12190 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12191 new_pctype->valid = false;
12201 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12202 uint32_t pkg_size, uint32_t proto_num,
12203 struct rte_pmd_i40e_proto_info *proto,
12204 enum rte_pmd_i40e_package_op op)
12206 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12207 uint16_t port_id = dev->data->port_id;
12208 uint32_t ptype_num;
12209 struct rte_pmd_i40e_ptype_info *ptype;
12210 uint32_t buff_size;
12212 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12217 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12218 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12219 PMD_DRV_LOG(ERR, "Unsupported operation.");
12223 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12224 rte_pmd_i40e_ptype_mapping_reset(port_id);
12228 /* get information about new ptype num */
12229 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12230 (uint8_t *)&ptype_num, sizeof(ptype_num),
12231 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12233 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12237 PMD_DRV_LOG(INFO, "No new ptype added");
12241 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12242 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12244 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12248 /* get information about new ptype list */
12249 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12250 (uint8_t *)ptype, buff_size,
12251 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12253 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12258 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12259 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12260 if (!ptype_mapping) {
12261 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12266 /* Update ptype mapping table. */
12267 for (i = 0; i < ptype_num; i++) {
12268 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12269 ptype_mapping[i].sw_ptype = 0;
12271 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12272 proto_id = ptype[i].protocols[j];
12273 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12275 for (n = 0; n < proto_num; n++) {
12276 if (proto[n].proto_id != proto_id)
12278 memset(name, 0, sizeof(name));
12279 strcpy(name, proto[n].name);
12280 if (!strncasecmp(name, "PPPOE", 5))
12281 ptype_mapping[i].sw_ptype |=
12282 RTE_PTYPE_L2_ETHER_PPPOE;
12283 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12285 ptype_mapping[i].sw_ptype |=
12286 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12287 ptype_mapping[i].sw_ptype |=
12289 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12291 ptype_mapping[i].sw_ptype |=
12292 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12293 ptype_mapping[i].sw_ptype |=
12294 RTE_PTYPE_INNER_L4_FRAG;
12295 } else if (!strncasecmp(name, "OIPV4", 5)) {
12296 ptype_mapping[i].sw_ptype |=
12297 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12299 } else if (!strncasecmp(name, "IPV4", 4) &&
12301 ptype_mapping[i].sw_ptype |=
12302 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12303 else if (!strncasecmp(name, "IPV4", 4) &&
12305 ptype_mapping[i].sw_ptype |=
12306 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12307 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12309 ptype_mapping[i].sw_ptype |=
12310 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12311 ptype_mapping[i].sw_ptype |=
12313 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12315 ptype_mapping[i].sw_ptype |=
12316 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12317 ptype_mapping[i].sw_ptype |=
12318 RTE_PTYPE_INNER_L4_FRAG;
12319 } else if (!strncasecmp(name, "OIPV6", 5)) {
12320 ptype_mapping[i].sw_ptype |=
12321 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12323 } else if (!strncasecmp(name, "IPV6", 4) &&
12325 ptype_mapping[i].sw_ptype |=
12326 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12327 else if (!strncasecmp(name, "IPV6", 4) &&
12329 ptype_mapping[i].sw_ptype |=
12330 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12331 else if (!strncasecmp(name, "UDP", 3) &&
12333 ptype_mapping[i].sw_ptype |=
12335 else if (!strncasecmp(name, "UDP", 3) &&
12337 ptype_mapping[i].sw_ptype |=
12338 RTE_PTYPE_INNER_L4_UDP;
12339 else if (!strncasecmp(name, "TCP", 3) &&
12341 ptype_mapping[i].sw_ptype |=
12343 else if (!strncasecmp(name, "TCP", 3) &&
12345 ptype_mapping[i].sw_ptype |=
12346 RTE_PTYPE_INNER_L4_TCP;
12347 else if (!strncasecmp(name, "SCTP", 4) &&
12349 ptype_mapping[i].sw_ptype |=
12351 else if (!strncasecmp(name, "SCTP", 4) &&
12353 ptype_mapping[i].sw_ptype |=
12354 RTE_PTYPE_INNER_L4_SCTP;
12355 else if ((!strncasecmp(name, "ICMP", 4) ||
12356 !strncasecmp(name, "ICMPV6", 6)) &&
12358 ptype_mapping[i].sw_ptype |=
12360 else if ((!strncasecmp(name, "ICMP", 4) ||
12361 !strncasecmp(name, "ICMPV6", 6)) &&
12363 ptype_mapping[i].sw_ptype |=
12364 RTE_PTYPE_INNER_L4_ICMP;
12365 else if (!strncasecmp(name, "GTPC", 4)) {
12366 ptype_mapping[i].sw_ptype |=
12367 RTE_PTYPE_TUNNEL_GTPC;
12369 } else if (!strncasecmp(name, "GTPU", 4)) {
12370 ptype_mapping[i].sw_ptype |=
12371 RTE_PTYPE_TUNNEL_GTPU;
12373 } else if (!strncasecmp(name, "GRENAT", 6)) {
12374 ptype_mapping[i].sw_ptype |=
12375 RTE_PTYPE_TUNNEL_GRENAT;
12377 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12378 !strncasecmp(name, "L2TPV2", 6)) {
12379 ptype_mapping[i].sw_ptype |=
12380 RTE_PTYPE_TUNNEL_L2TP;
12389 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12392 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12394 rte_free(ptype_mapping);
12400 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12401 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12403 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12404 uint32_t proto_num;
12405 struct rte_pmd_i40e_proto_info *proto;
12406 uint32_t buff_size;
12410 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12411 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12412 PMD_DRV_LOG(ERR, "Unsupported operation.");
12416 /* get information about protocol number */
12417 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12418 (uint8_t *)&proto_num, sizeof(proto_num),
12419 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12421 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12425 PMD_DRV_LOG(INFO, "No new protocol added");
12429 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12430 proto = rte_zmalloc("new_proto", buff_size, 0);
12432 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12436 /* get information about protocol list */
12437 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12438 (uint8_t *)proto, buff_size,
12439 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12441 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12446 /* Check if GTP is supported. */
12447 for (i = 0; i < proto_num; i++) {
12448 if (!strncmp(proto[i].name, "GTP", 3)) {
12449 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12450 pf->gtp_support = true;
12452 pf->gtp_support = false;
12457 /* Update customized pctype info */
12458 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12459 proto_num, proto, op);
12461 PMD_DRV_LOG(INFO, "No pctype is updated.");
12463 /* Update customized ptype info */
12464 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12465 proto_num, proto, op);
12467 PMD_DRV_LOG(INFO, "No ptype is updated.");
12472 /* Create a QinQ cloud filter
12474 * The Fortville NIC has limited resources for tunnel filters,
12475 * so we can only reuse existing filters.
12477 * In step 1 we define which Field Vector fields can be used for
12479 * As we do not have the inner tag defined as a field,
12480 * we have to define it first, by reusing one of L1 entries.
12482 * In step 2 we are replacing one of existing filter types with
12483 * a new one for QinQ.
12484 * As we reusing L1 and replacing L2, some of the default filter
12485 * types will disappear,which depends on L1 and L2 entries we reuse.
12487 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12489 * 1. Create L1 filter of outer vlan (12b) which will be in use
12490 * later when we define the cloud filter.
12491 * a. Valid_flags.replace_cloud = 0
12492 * b. Old_filter = 10 (Stag_Inner_Vlan)
12493 * c. New_filter = 0x10
12494 * d. TR bit = 0xff (optional, not used here)
12495 * e. Buffer – 2 entries:
12496 * i. Byte 0 = 8 (outer vlan FV index).
12498 * Byte 2-3 = 0x0fff
12499 * ii. Byte 0 = 37 (inner vlan FV index).
12501 * Byte 2-3 = 0x0fff
12504 * 2. Create cloud filter using two L1 filters entries: stag and
12505 * new filter(outer vlan+ inner vlan)
12506 * a. Valid_flags.replace_cloud = 1
12507 * b. Old_filter = 1 (instead of outer IP)
12508 * c. New_filter = 0x10
12509 * d. Buffer – 2 entries:
12510 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12511 * Byte 1-3 = 0 (rsv)
12512 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12513 * Byte 9-11 = 0 (rsv)
12516 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12518 int ret = -ENOTSUP;
12519 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12520 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12521 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12522 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12524 if (pf->support_multi_driver) {
12525 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12530 memset(&filter_replace, 0,
12531 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12532 memset(&filter_replace_buf, 0,
12533 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12535 /* create L1 filter */
12536 filter_replace.old_filter_type =
12537 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12538 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12539 filter_replace.tr_bit = 0;
12541 /* Prepare the buffer, 2 entries */
12542 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12543 filter_replace_buf.data[0] |=
12544 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12545 /* Field Vector 12b mask */
12546 filter_replace_buf.data[2] = 0xff;
12547 filter_replace_buf.data[3] = 0x0f;
12548 filter_replace_buf.data[4] =
12549 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12550 filter_replace_buf.data[4] |=
12551 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12552 /* Field Vector 12b mask */
12553 filter_replace_buf.data[6] = 0xff;
12554 filter_replace_buf.data[7] = 0x0f;
12555 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12556 &filter_replace_buf);
12557 if (ret != I40E_SUCCESS)
12560 if (filter_replace.old_filter_type !=
12561 filter_replace.new_filter_type)
12562 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12563 " original: 0x%x, new: 0x%x",
12565 filter_replace.old_filter_type,
12566 filter_replace.new_filter_type);
12568 /* Apply the second L2 cloud filter */
12569 memset(&filter_replace, 0,
12570 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12571 memset(&filter_replace_buf, 0,
12572 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12574 /* create L2 filter, input for L2 filter will be L1 filter */
12575 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12576 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12577 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12579 /* Prepare the buffer, 2 entries */
12580 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12581 filter_replace_buf.data[0] |=
12582 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12583 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12584 filter_replace_buf.data[4] |=
12585 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12586 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12587 &filter_replace_buf);
12588 if (!ret && (filter_replace.old_filter_type !=
12589 filter_replace.new_filter_type))
12590 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12591 " original: 0x%x, new: 0x%x",
12593 filter_replace.old_filter_type,
12594 filter_replace.new_filter_type);
12600 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12601 const struct rte_flow_action_rss *in)
12603 if (in->key_len > RTE_DIM(out->key) ||
12604 in->queue_num > RTE_DIM(out->queue))
12606 if (!in->key && in->key_len)
12608 out->conf = (struct rte_flow_action_rss){
12610 .level = in->level,
12611 .types = in->types,
12612 .key_len = in->key_len,
12613 .queue_num = in->queue_num,
12614 .queue = memcpy(out->queue, in->queue,
12615 sizeof(*in->queue) * in->queue_num),
12618 out->conf.key = memcpy(out->key, in->key, in->key_len);
12623 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12624 const struct rte_flow_action_rss *with)
12626 return (comp->func == with->func &&
12627 comp->level == with->level &&
12628 comp->types == with->types &&
12629 comp->key_len == with->key_len &&
12630 comp->queue_num == with->queue_num &&
12631 !memcmp(comp->key, with->key, with->key_len) &&
12632 !memcmp(comp->queue, with->queue,
12633 sizeof(*with->queue) * with->queue_num));
12637 i40e_config_rss_filter(struct i40e_pf *pf,
12638 struct i40e_rte_flow_rss_conf *conf, bool add)
12640 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12641 uint32_t i, lut = 0;
12643 struct rte_eth_rss_conf rss_conf = {
12644 .rss_key = conf->conf.key_len ?
12645 (void *)(uintptr_t)conf->conf.key : NULL,
12646 .rss_key_len = conf->conf.key_len,
12647 .rss_hf = conf->conf.types,
12649 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12652 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12653 i40e_pf_disable_rss(pf);
12654 memset(rss_info, 0,
12655 sizeof(struct i40e_rte_flow_rss_conf));
12661 if (rss_info->conf.queue_num)
12664 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12665 * It's necessary to calculate the actual PF queues that are configured.
12667 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12668 num = i40e_pf_calc_configured_queues_num(pf);
12670 num = pf->dev_data->nb_rx_queues;
12672 num = RTE_MIN(num, conf->conf.queue_num);
12673 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12677 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12681 /* Fill in redirection table */
12682 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12685 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12686 hw->func_caps.rss_table_entry_width) - 1));
12688 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12691 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12692 i40e_pf_disable_rss(pf);
12695 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12696 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12697 /* Random default keys */
12698 static uint32_t rss_key_default[] = {0x6b793944,
12699 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12700 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12701 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12703 rss_conf.rss_key = (uint8_t *)rss_key_default;
12704 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12708 i40e_hw_rss_hash_set(pf, &rss_conf);
12710 if (i40e_rss_conf_init(rss_info, &conf->conf))
12716 RTE_INIT(i40e_init_log)
12718 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12719 if (i40e_logtype_init >= 0)
12720 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12721 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12722 if (i40e_logtype_driver >= 0)
12723 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12726 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12727 ETH_I40E_FLOATING_VEB_ARG "=1"
12728 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12729 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12730 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12731 ETH_I40E_USE_LATEST_VEC "=0|1");