4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
68 #include "rte_pmd_i40e.h"
70 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
71 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
73 #define I40E_CLEAR_PXE_WAIT_MS 200
75 /* Maximun number of capability elements */
76 #define I40E_MAX_CAP_ELE_NUM 128
78 /* Wait count and inteval */
79 #define I40E_CHK_Q_ENA_COUNT 1000
80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
82 /* Maximun number of VSI */
83 #define I40E_MAX_NUM_VSIS (384UL)
85 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
87 /* Flow control default timer */
88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
90 /* Flow control default high water */
91 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
93 /* Flow control default low water */
94 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
96 /* Flow control enable fwd bit */
97 #define I40E_PRTMAC_FWD_CTRL 0x00000001
99 /* Receive Packet Buffer size */
100 #define I40E_RXPBSIZE (968 * 1024)
102 /* Kilobytes shift */
103 #define I40E_KILOSHIFT 10
105 /* Receive Average Packet Size in Byte*/
106 #define I40E_PACKET_AVERAGE_SIZE 128
108 /* Mask of PF interrupt causes */
109 #define I40E_PFINT_ICR0_ENA_MASK ( \
110 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
112 I40E_PFINT_ICR0_ENA_GRST_MASK | \
113 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
114 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
115 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
116 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
117 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
118 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
120 #define I40E_FLOW_TYPES ( \
121 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
126 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
130 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
131 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
133 /* Additional timesync values. */
134 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
135 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
136 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
137 #define I40E_PRTTSYN_TSYNENA 0x80000000
138 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
139 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define I40E_MAX_PERCENT 100
142 #define I40E_DEFAULT_DCB_APP_NUM 1
143 #define I40E_DEFAULT_DCB_APP_PRIO 3
146 * Below are values for writing un-exposed registers suggested
149 /* Destination MAC address */
150 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
151 /* Source MAC address */
152 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
153 /* Outer (S-Tag) VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
155 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
156 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
157 /* Single VLAN tag in the inner L2 header */
158 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
159 /* Source IPv4 address */
160 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
161 /* Destination IPv4 address */
162 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
163 /* Source IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
165 /* Destination IPv4 address for X722 */
166 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
167 /* IPv4 Protocol for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
169 /* IPv4 Time to Live for X722 */
170 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
171 /* IPv4 Type of Service (TOS) */
172 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
174 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
175 /* IPv4 Time to Live */
176 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
177 /* Source IPv6 address */
178 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
179 /* Destination IPv6 address */
180 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
181 /* IPv6 Traffic Class (TC) */
182 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
183 /* IPv6 Next Header */
184 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
186 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
188 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
189 /* Destination L4 port */
190 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
191 /* SCTP verification tag */
192 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
193 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
194 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
195 /* Source port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
197 /* Destination port of tunneling UDP */
198 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
199 /* UDP Tunneling ID, NVGRE/GRE key */
200 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
201 /* Last ether type */
202 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
203 /* Tunneling outer destination IPv4 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
205 /* Tunneling outer destination IPv6 address */
206 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
207 /* 1st word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
209 /* 2nd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
211 /* 3rd word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
213 /* 4th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
215 /* 5th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
217 /* 6th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
219 /* 7th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
221 /* 8th word of flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
223 /* all 8 words flex payload */
224 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
225 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
227 #define I40E_TRANSLATE_INSET 0
228 #define I40E_TRANSLATE_REG 1
230 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
231 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
232 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
233 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
234 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
235 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
237 /* PCI offset for querying capability */
238 #define PCI_DEV_CAP_REG 0xA4
239 /* PCI offset for enabling/disabling Extended Tag */
240 #define PCI_DEV_CTRL_REG 0xA8
241 /* Bit mask of Extended Tag capability */
242 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
243 /* Bit shift of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
245 /* Bit mask of Extended Tag enable/disable */
246 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
248 /* The max bandwidth of i40e is 40Gbps. */
249 #define I40E_QOS_BW_MAX 40000
250 /* The bandwidth should be the multiple of 50Mbps. */
251 #define I40E_QOS_BW_GRANULARITY 50
252 /* The min bandwidth weight is 1. */
253 #define I40E_QOS_BW_WEIGHT_MIN 1
254 /* The max bandwidth weight is 127. */
255 #define I40E_QOS_BW_WEIGHT_MAX 127
257 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
258 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
259 static int i40e_dev_configure(struct rte_eth_dev *dev);
260 static int i40e_dev_start(struct rte_eth_dev *dev);
261 static void i40e_dev_stop(struct rte_eth_dev *dev);
262 static void i40e_dev_close(struct rte_eth_dev *dev);
263 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
264 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
265 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
266 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
267 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
268 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
269 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
270 struct rte_eth_stats *stats);
271 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
272 struct rte_eth_xstat *xstats, unsigned n);
273 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
274 struct rte_eth_xstat_name *xstats_names,
276 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
277 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
281 static int i40e_fw_version_get(struct rte_eth_dev *dev,
282 char *fw_version, size_t fw_size);
283 static void i40e_dev_info_get(struct rte_eth_dev *dev,
284 struct rte_eth_dev_info *dev_info);
285 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
288 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
289 enum rte_vlan_type vlan_type,
291 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
292 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
295 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
296 static int i40e_dev_led_on(struct rte_eth_dev *dev);
297 static int i40e_dev_led_off(struct rte_eth_dev *dev);
298 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
299 struct rte_eth_fc_conf *fc_conf);
300 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
301 struct rte_eth_fc_conf *fc_conf);
302 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
303 struct rte_eth_pfc_conf *pfc_conf);
304 static void i40e_macaddr_add(struct rte_eth_dev *dev,
305 struct ether_addr *mac_addr,
308 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
309 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
310 struct rte_eth_rss_reta_entry64 *reta_conf,
312 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
313 struct rte_eth_rss_reta_entry64 *reta_conf,
316 static int i40e_get_cap(struct i40e_hw *hw);
317 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
318 static int i40e_pf_setup(struct i40e_pf *pf);
319 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
320 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
321 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
322 static int i40e_dcb_setup(struct rte_eth_dev *dev);
323 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
324 bool offset_loaded, uint64_t *offset, uint64_t *stat);
325 static void i40e_stat_update_48(struct i40e_hw *hw,
331 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
332 static void i40e_dev_interrupt_handler(void *param);
333 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
334 uint32_t base, uint32_t num);
335 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
336 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
338 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
340 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
341 static int i40e_veb_release(struct i40e_veb *veb);
342 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
343 struct i40e_vsi *vsi);
344 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
345 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
346 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
347 struct i40e_macvlan_filter *mv_f,
349 struct ether_addr *addr);
350 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
351 struct i40e_macvlan_filter *mv_f,
354 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
355 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
356 struct rte_eth_rss_conf *rss_conf);
357 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
358 struct rte_eth_rss_conf *rss_conf);
359 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
360 struct rte_eth_udp_tunnel *udp_tunnel);
361 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
362 struct rte_eth_udp_tunnel *udp_tunnel);
363 static void i40e_filter_input_set_init(struct i40e_pf *pf);
364 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
365 enum rte_filter_op filter_op,
367 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
368 enum rte_filter_type filter_type,
369 enum rte_filter_op filter_op,
371 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
372 struct rte_eth_dcb_info *dcb_info);
373 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
374 static void i40e_configure_registers(struct i40e_hw *hw);
375 static void i40e_hw_init(struct rte_eth_dev *dev);
376 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
377 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
378 struct rte_eth_mirror_conf *mirror_conf,
379 uint8_t sw_id, uint8_t on);
380 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
382 static int i40e_timesync_enable(struct rte_eth_dev *dev);
383 static int i40e_timesync_disable(struct rte_eth_dev *dev);
384 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
385 struct timespec *timestamp,
387 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
388 struct timespec *timestamp);
389 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
391 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
393 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
394 struct timespec *timestamp);
395 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
396 const struct timespec *timestamp);
398 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
400 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
403 static int i40e_get_regs(struct rte_eth_dev *dev,
404 struct rte_dev_reg_info *regs);
406 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
408 static int i40e_get_eeprom(struct rte_eth_dev *dev,
409 struct rte_dev_eeprom_info *eeprom);
411 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
412 struct ether_addr *mac_addr);
414 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
416 static int i40e_ethertype_filter_convert(
417 const struct rte_eth_ethertype_filter *input,
418 struct i40e_ethertype_filter *filter);
419 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
420 struct i40e_ethertype_filter *filter);
422 static int i40e_tunnel_filter_convert(
423 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
424 struct i40e_tunnel_filter *tunnel_filter);
425 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
426 struct i40e_tunnel_filter *tunnel_filter);
427 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
429 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
430 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
431 static void i40e_filter_restore(struct i40e_pf *pf);
433 int i40e_logtype_init;
434 int i40e_logtype_driver;
436 static const struct rte_pci_id pci_id_i40e_map[] = {
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
452 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
453 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
454 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
455 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
456 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
457 { .vendor_id = 0, /* sentinel */ },
460 static const struct eth_dev_ops i40e_eth_dev_ops = {
461 .dev_configure = i40e_dev_configure,
462 .dev_start = i40e_dev_start,
463 .dev_stop = i40e_dev_stop,
464 .dev_close = i40e_dev_close,
465 .promiscuous_enable = i40e_dev_promiscuous_enable,
466 .promiscuous_disable = i40e_dev_promiscuous_disable,
467 .allmulticast_enable = i40e_dev_allmulticast_enable,
468 .allmulticast_disable = i40e_dev_allmulticast_disable,
469 .dev_set_link_up = i40e_dev_set_link_up,
470 .dev_set_link_down = i40e_dev_set_link_down,
471 .link_update = i40e_dev_link_update,
472 .stats_get = i40e_dev_stats_get,
473 .xstats_get = i40e_dev_xstats_get,
474 .xstats_get_names = i40e_dev_xstats_get_names,
475 .stats_reset = i40e_dev_stats_reset,
476 .xstats_reset = i40e_dev_stats_reset,
477 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
478 .fw_version_get = i40e_fw_version_get,
479 .dev_infos_get = i40e_dev_info_get,
480 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
481 .vlan_filter_set = i40e_vlan_filter_set,
482 .vlan_tpid_set = i40e_vlan_tpid_set,
483 .vlan_offload_set = i40e_vlan_offload_set,
484 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
485 .vlan_pvid_set = i40e_vlan_pvid_set,
486 .rx_queue_start = i40e_dev_rx_queue_start,
487 .rx_queue_stop = i40e_dev_rx_queue_stop,
488 .tx_queue_start = i40e_dev_tx_queue_start,
489 .tx_queue_stop = i40e_dev_tx_queue_stop,
490 .rx_queue_setup = i40e_dev_rx_queue_setup,
491 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
492 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
493 .rx_queue_release = i40e_dev_rx_queue_release,
494 .rx_queue_count = i40e_dev_rx_queue_count,
495 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
496 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
497 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
498 .tx_queue_setup = i40e_dev_tx_queue_setup,
499 .tx_queue_release = i40e_dev_tx_queue_release,
500 .dev_led_on = i40e_dev_led_on,
501 .dev_led_off = i40e_dev_led_off,
502 .flow_ctrl_get = i40e_flow_ctrl_get,
503 .flow_ctrl_set = i40e_flow_ctrl_set,
504 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
505 .mac_addr_add = i40e_macaddr_add,
506 .mac_addr_remove = i40e_macaddr_remove,
507 .reta_update = i40e_dev_rss_reta_update,
508 .reta_query = i40e_dev_rss_reta_query,
509 .rss_hash_update = i40e_dev_rss_hash_update,
510 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
511 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
512 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
513 .filter_ctrl = i40e_dev_filter_ctrl,
514 .rxq_info_get = i40e_rxq_info_get,
515 .txq_info_get = i40e_txq_info_get,
516 .mirror_rule_set = i40e_mirror_rule_set,
517 .mirror_rule_reset = i40e_mirror_rule_reset,
518 .timesync_enable = i40e_timesync_enable,
519 .timesync_disable = i40e_timesync_disable,
520 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
521 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
522 .get_dcb_info = i40e_dev_get_dcb_info,
523 .timesync_adjust_time = i40e_timesync_adjust_time,
524 .timesync_read_time = i40e_timesync_read_time,
525 .timesync_write_time = i40e_timesync_write_time,
526 .get_reg = i40e_get_regs,
527 .get_eeprom_length = i40e_get_eeprom_length,
528 .get_eeprom = i40e_get_eeprom,
529 .mac_addr_set = i40e_set_default_mac_addr,
530 .mtu_set = i40e_dev_mtu_set,
533 /* store statistics names and its offset in stats structure */
534 struct rte_i40e_xstats_name_off {
535 char name[RTE_ETH_XSTATS_NAME_SIZE];
539 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
540 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
541 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
542 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
543 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
544 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
545 rx_unknown_protocol)},
546 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
547 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
548 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
549 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
552 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
553 sizeof(rte_i40e_stats_strings[0]))
555 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
556 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
557 tx_dropped_link_down)},
558 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
559 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
562 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
564 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
566 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
568 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
569 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
570 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
571 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
572 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
573 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
583 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
585 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
587 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
590 mac_short_packet_dropped)},
591 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
593 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
594 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
595 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
603 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
605 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
607 {"rx_flow_director_atr_match_packets",
608 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
609 {"rx_flow_director_sb_match_packets",
610 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
611 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
613 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
615 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
617 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
621 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
622 sizeof(rte_i40e_hw_port_strings[0]))
624 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
625 {"xon_packets", offsetof(struct i40e_hw_port_stats,
627 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
631 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
632 sizeof(rte_i40e_rxq_prio_strings[0]))
634 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
635 {"xon_packets", offsetof(struct i40e_hw_port_stats,
637 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
639 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
640 priority_xon_2_xoff)},
643 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
644 sizeof(rte_i40e_txq_prio_strings[0]))
646 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
647 struct rte_pci_device *pci_dev)
649 return rte_eth_dev_pci_generic_probe(pci_dev,
650 sizeof(struct i40e_adapter), eth_i40e_dev_init);
653 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
655 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
658 static struct rte_pci_driver rte_i40e_pmd = {
659 .id_table = pci_id_i40e_map,
660 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
661 .probe = eth_i40e_pci_probe,
662 .remove = eth_i40e_pci_remove,
666 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
667 struct rte_eth_link *link)
669 struct rte_eth_link *dst = link;
670 struct rte_eth_link *src = &(dev->data->dev_link);
672 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
673 *(uint64_t *)src) == 0)
680 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
681 struct rte_eth_link *link)
683 struct rte_eth_link *dst = &(dev->data->dev_link);
684 struct rte_eth_link *src = link;
686 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
687 *(uint64_t *)src) == 0)
693 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
694 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
695 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
697 #ifndef I40E_GLQF_ORT
698 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
700 #ifndef I40E_GLQF_PIT
701 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
703 #ifndef I40E_GLQF_L3_MAP
704 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
707 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
710 * Initialize registers for flexible payload, which should be set by NVM.
711 * This should be removed from code once it is fixed in NVM.
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
723 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
724 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
726 /* Initialize registers for parsing packet type of QinQ */
727 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
728 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
731 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
734 * Add a ethertype filter to drop all flow control frames transmitted
738 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
740 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
741 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
742 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
743 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
746 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
747 I40E_FLOW_CONTROL_ETHERTYPE, flags,
748 pf->main_vsi_seid, 0,
752 "Failed to add filter to drop flow control frames from VSIs.");
756 floating_veb_list_handler(__rte_unused const char *key,
757 const char *floating_veb_value,
761 unsigned int count = 0;
764 bool *vf_floating_veb = opaque;
766 while (isblank(*floating_veb_value))
767 floating_veb_value++;
769 /* Reset floating VEB configuration for VFs */
770 for (idx = 0; idx < I40E_MAX_VF; idx++)
771 vf_floating_veb[idx] = false;
775 while (isblank(*floating_veb_value))
776 floating_veb_value++;
777 if (*floating_veb_value == '\0')
780 idx = strtoul(floating_veb_value, &end, 10);
781 if (errno || end == NULL)
783 while (isblank(*end))
787 } else if ((*end == ';') || (*end == '\0')) {
789 if (min == I40E_MAX_VF)
791 if (max >= I40E_MAX_VF)
792 max = I40E_MAX_VF - 1;
793 for (idx = min; idx <= max; idx++) {
794 vf_floating_veb[idx] = true;
801 floating_veb_value = end + 1;
802 } while (*end != '\0');
811 config_vf_floating_veb(struct rte_devargs *devargs,
812 uint16_t floating_veb,
813 bool *vf_floating_veb)
815 struct rte_kvargs *kvlist;
817 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
821 /* All the VFs attach to the floating VEB by default
822 * when the floating VEB is enabled.
824 for (i = 0; i < I40E_MAX_VF; i++)
825 vf_floating_veb[i] = true;
830 kvlist = rte_kvargs_parse(devargs->args, NULL);
834 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
835 rte_kvargs_free(kvlist);
838 /* When the floating_veb_list parameter exists, all the VFs
839 * will attach to the legacy VEB firstly, then configure VFs
840 * to the floating VEB according to the floating_veb_list.
842 if (rte_kvargs_process(kvlist, floating_veb_list,
843 floating_veb_list_handler,
844 vf_floating_veb) < 0) {
845 rte_kvargs_free(kvlist);
848 rte_kvargs_free(kvlist);
852 i40e_check_floating_handler(__rte_unused const char *key,
854 __rte_unused void *opaque)
856 if (strcmp(value, "1"))
863 is_floating_veb_supported(struct rte_devargs *devargs)
865 struct rte_kvargs *kvlist;
866 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
871 kvlist = rte_kvargs_parse(devargs->args, NULL);
875 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
876 rte_kvargs_free(kvlist);
879 /* Floating VEB is enabled when there's key-value:
880 * enable_floating_veb=1
882 if (rte_kvargs_process(kvlist, floating_veb_key,
883 i40e_check_floating_handler, NULL) < 0) {
884 rte_kvargs_free(kvlist);
887 rte_kvargs_free(kvlist);
893 config_floating_veb(struct rte_eth_dev *dev)
895 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
896 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
897 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
899 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
901 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
903 is_floating_veb_supported(pci_dev->device.devargs);
904 config_vf_floating_veb(pci_dev->device.devargs,
906 pf->floating_veb_list);
908 pf->floating_veb = false;
912 #define I40E_L2_TAGS_S_TAG_SHIFT 1
913 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
916 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
919 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
920 char ethertype_hash_name[RTE_HASH_NAMESIZE];
923 struct rte_hash_parameters ethertype_hash_params = {
924 .name = ethertype_hash_name,
925 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
926 .key_len = sizeof(struct i40e_ethertype_filter_input),
927 .hash_func = rte_hash_crc,
928 .hash_func_init_val = 0,
929 .socket_id = rte_socket_id(),
932 /* Initialize ethertype filter rule list and hash */
933 TAILQ_INIT(ðertype_rule->ethertype_list);
934 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
935 "ethertype_%s", dev->data->name);
936 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
937 if (!ethertype_rule->hash_table) {
938 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
941 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
942 sizeof(struct i40e_ethertype_filter *) *
943 I40E_MAX_ETHERTYPE_FILTER_NUM,
945 if (!ethertype_rule->hash_map) {
947 "Failed to allocate memory for ethertype hash map!");
949 goto err_ethertype_hash_map_alloc;
954 err_ethertype_hash_map_alloc:
955 rte_hash_free(ethertype_rule->hash_table);
961 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
963 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
964 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
965 char tunnel_hash_name[RTE_HASH_NAMESIZE];
968 struct rte_hash_parameters tunnel_hash_params = {
969 .name = tunnel_hash_name,
970 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
971 .key_len = sizeof(struct i40e_tunnel_filter_input),
972 .hash_func = rte_hash_crc,
973 .hash_func_init_val = 0,
974 .socket_id = rte_socket_id(),
977 /* Initialize tunnel filter rule list and hash */
978 TAILQ_INIT(&tunnel_rule->tunnel_list);
979 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
980 "tunnel_%s", dev->data->name);
981 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
982 if (!tunnel_rule->hash_table) {
983 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
986 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
987 sizeof(struct i40e_tunnel_filter *) *
988 I40E_MAX_TUNNEL_FILTER_NUM,
990 if (!tunnel_rule->hash_map) {
992 "Failed to allocate memory for tunnel hash map!");
994 goto err_tunnel_hash_map_alloc;
999 err_tunnel_hash_map_alloc:
1000 rte_hash_free(tunnel_rule->hash_table);
1006 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1009 struct i40e_fdir_info *fdir_info = &pf->fdir;
1010 char fdir_hash_name[RTE_HASH_NAMESIZE];
1013 struct rte_hash_parameters fdir_hash_params = {
1014 .name = fdir_hash_name,
1015 .entries = I40E_MAX_FDIR_FILTER_NUM,
1016 .key_len = sizeof(struct rte_eth_fdir_input),
1017 .hash_func = rte_hash_crc,
1018 .hash_func_init_val = 0,
1019 .socket_id = rte_socket_id(),
1022 /* Initialize flow director filter rule list and hash */
1023 TAILQ_INIT(&fdir_info->fdir_list);
1024 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1025 "fdir_%s", dev->data->name);
1026 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1027 if (!fdir_info->hash_table) {
1028 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1031 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1032 sizeof(struct i40e_fdir_filter *) *
1033 I40E_MAX_FDIR_FILTER_NUM,
1035 if (!fdir_info->hash_map) {
1037 "Failed to allocate memory for fdir hash map!");
1039 goto err_fdir_hash_map_alloc;
1043 err_fdir_hash_map_alloc:
1044 rte_hash_free(fdir_info->hash_table);
1050 eth_i40e_dev_init(struct rte_eth_dev *dev)
1052 struct rte_pci_device *pci_dev;
1053 struct rte_intr_handle *intr_handle;
1054 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056 struct i40e_vsi *vsi;
1059 uint8_t aq_fail = 0;
1061 PMD_INIT_FUNC_TRACE();
1063 dev->dev_ops = &i40e_eth_dev_ops;
1064 dev->rx_pkt_burst = i40e_recv_pkts;
1065 dev->tx_pkt_burst = i40e_xmit_pkts;
1066 dev->tx_pkt_prepare = i40e_prep_pkts;
1068 /* for secondary processes, we don't initialise any further as primary
1069 * has already done this work. Only check we don't need a different
1071 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1072 i40e_set_rx_function(dev);
1073 i40e_set_tx_function(dev);
1076 pci_dev = I40E_DEV_TO_PCI(dev);
1077 intr_handle = &pci_dev->intr_handle;
1079 rte_eth_copy_pci_info(dev, pci_dev);
1080 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1082 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1083 pf->adapter->eth_dev = dev;
1084 pf->dev_data = dev->data;
1086 hw->back = I40E_PF_TO_ADAPTER(pf);
1087 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1090 "Hardware is not available, as address is NULL");
1094 hw->vendor_id = pci_dev->id.vendor_id;
1095 hw->device_id = pci_dev->id.device_id;
1096 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1097 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1098 hw->bus.device = pci_dev->addr.devid;
1099 hw->bus.func = pci_dev->addr.function;
1100 hw->adapter_stopped = 0;
1102 /* Make sure all is clean before doing PF reset */
1105 /* Initialize the hardware */
1108 /* Reset here to make sure all is clean for each PF */
1109 ret = i40e_pf_reset(hw);
1111 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1115 /* Initialize the shared code (base driver) */
1116 ret = i40e_init_shared_code(hw);
1118 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1123 * To work around the NVM issue, initialize registers
1124 * for flexible payload and packet type of QinQ by
1125 * software. It should be removed once issues are fixed
1128 i40e_GLQF_reg_init(hw);
1130 /* Initialize the input set for filters (hash and fd) to default value */
1131 i40e_filter_input_set_init(pf);
1133 /* Initialize the parameters for adminq */
1134 i40e_init_adminq_parameter(hw);
1135 ret = i40e_init_adminq(hw);
1136 if (ret != I40E_SUCCESS) {
1137 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1140 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1141 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1142 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1143 ((hw->nvm.version >> 12) & 0xf),
1144 ((hw->nvm.version >> 4) & 0xff),
1145 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1147 /* initialise the L3_MAP register */
1148 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1151 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1153 /* Need the special FW version to support floating VEB */
1154 config_floating_veb(dev);
1155 /* Clear PXE mode */
1156 i40e_clear_pxe_mode(hw);
1157 ret = i40e_dev_sync_phy_type(hw);
1159 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1160 goto err_sync_phy_type;
1163 * On X710, performance number is far from the expectation on recent
1164 * firmware versions. The fix for this issue may not be integrated in
1165 * the following firmware version. So the workaround in software driver
1166 * is needed. It needs to modify the initial values of 3 internal only
1167 * registers. Note that the workaround can be removed when it is fixed
1168 * in firmware in the future.
1170 i40e_configure_registers(hw);
1172 /* Get hw capabilities */
1173 ret = i40e_get_cap(hw);
1174 if (ret != I40E_SUCCESS) {
1175 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1176 goto err_get_capabilities;
1179 /* Initialize parameters for PF */
1180 ret = i40e_pf_parameter_init(dev);
1182 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1183 goto err_parameter_init;
1186 /* Initialize the queue management */
1187 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1189 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1190 goto err_qp_pool_init;
1192 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1193 hw->func_caps.num_msix_vectors - 1);
1195 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1196 goto err_msix_pool_init;
1199 /* Initialize lan hmc */
1200 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1201 hw->func_caps.num_rx_qp, 0, 0);
1202 if (ret != I40E_SUCCESS) {
1203 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1204 goto err_init_lan_hmc;
1207 /* Configure lan hmc */
1208 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1209 if (ret != I40E_SUCCESS) {
1210 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1211 goto err_configure_lan_hmc;
1214 /* Get and check the mac address */
1215 i40e_get_mac_addr(hw, hw->mac.addr);
1216 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1217 PMD_INIT_LOG(ERR, "mac address is not valid");
1219 goto err_get_mac_addr;
1221 /* Copy the permanent MAC address */
1222 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1223 (struct ether_addr *) hw->mac.perm_addr);
1225 /* Disable flow control */
1226 hw->fc.requested_mode = I40E_FC_NONE;
1227 i40e_set_fc(hw, &aq_fail, TRUE);
1229 /* Set the global registers with default ether type value */
1230 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1231 if (ret != I40E_SUCCESS) {
1233 "Failed to set the default outer VLAN ether type");
1234 goto err_setup_pf_switch;
1237 /* PF setup, which includes VSI setup */
1238 ret = i40e_pf_setup(pf);
1240 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1241 goto err_setup_pf_switch;
1244 /* reset all stats of the device, including pf and main vsi */
1245 i40e_dev_stats_reset(dev);
1249 /* Disable double vlan by default */
1250 i40e_vsi_config_double_vlan(vsi, FALSE);
1252 /* Disable S-TAG identification when floating_veb is disabled */
1253 if (!pf->floating_veb) {
1254 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1255 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1256 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1257 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1261 if (!vsi->max_macaddrs)
1262 len = ETHER_ADDR_LEN;
1264 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1266 /* Should be after VSI initialized */
1267 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1268 if (!dev->data->mac_addrs) {
1270 "Failed to allocated memory for storing mac address");
1273 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1274 &dev->data->mac_addrs[0]);
1276 /* Init dcb to sw mode by default */
1277 ret = i40e_dcb_init_configure(dev, TRUE);
1278 if (ret != I40E_SUCCESS) {
1279 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1280 pf->flags &= ~I40E_FLAG_DCB;
1282 /* Update HW struct after DCB configuration */
1285 /* initialize pf host driver to setup SRIOV resource if applicable */
1286 i40e_pf_host_init(dev);
1288 /* register callback func to eal lib */
1289 rte_intr_callback_register(intr_handle,
1290 i40e_dev_interrupt_handler, dev);
1292 /* configure and enable device interrupt */
1293 i40e_pf_config_irq0(hw, TRUE);
1294 i40e_pf_enable_irq0(hw);
1296 /* enable uio intr after callback register */
1297 rte_intr_enable(intr_handle);
1299 * Add an ethertype filter to drop all flow control frames transmitted
1300 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1303 i40e_add_tx_flow_control_drop_filter(pf);
1305 /* Set the max frame size to 0x2600 by default,
1306 * in case other drivers changed the default value.
1308 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1310 /* initialize mirror rule list */
1311 TAILQ_INIT(&pf->mirror_list);
1313 ret = i40e_init_ethtype_filter_list(dev);
1315 goto err_init_ethtype_filter_list;
1316 ret = i40e_init_tunnel_filter_list(dev);
1318 goto err_init_tunnel_filter_list;
1319 ret = i40e_init_fdir_filter_list(dev);
1321 goto err_init_fdir_filter_list;
1325 err_init_fdir_filter_list:
1326 rte_free(pf->tunnel.hash_table);
1327 rte_free(pf->tunnel.hash_map);
1328 err_init_tunnel_filter_list:
1329 rte_free(pf->ethertype.hash_table);
1330 rte_free(pf->ethertype.hash_map);
1331 err_init_ethtype_filter_list:
1332 rte_free(dev->data->mac_addrs);
1334 i40e_vsi_release(pf->main_vsi);
1335 err_setup_pf_switch:
1337 err_configure_lan_hmc:
1338 (void)i40e_shutdown_lan_hmc(hw);
1340 i40e_res_pool_destroy(&pf->msix_pool);
1342 i40e_res_pool_destroy(&pf->qp_pool);
1345 err_get_capabilities:
1347 (void)i40e_shutdown_adminq(hw);
1353 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1355 struct i40e_ethertype_filter *p_ethertype;
1356 struct i40e_ethertype_rule *ethertype_rule;
1358 ethertype_rule = &pf->ethertype;
1359 /* Remove all ethertype filter rules and hash */
1360 if (ethertype_rule->hash_map)
1361 rte_free(ethertype_rule->hash_map);
1362 if (ethertype_rule->hash_table)
1363 rte_hash_free(ethertype_rule->hash_table);
1365 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1366 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1367 p_ethertype, rules);
1368 rte_free(p_ethertype);
1373 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1375 struct i40e_tunnel_filter *p_tunnel;
1376 struct i40e_tunnel_rule *tunnel_rule;
1378 tunnel_rule = &pf->tunnel;
1379 /* Remove all tunnel director rules and hash */
1380 if (tunnel_rule->hash_map)
1381 rte_free(tunnel_rule->hash_map);
1382 if (tunnel_rule->hash_table)
1383 rte_hash_free(tunnel_rule->hash_table);
1385 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1386 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1392 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1394 struct i40e_fdir_filter *p_fdir;
1395 struct i40e_fdir_info *fdir_info;
1397 fdir_info = &pf->fdir;
1398 /* Remove all flow director rules and hash */
1399 if (fdir_info->hash_map)
1400 rte_free(fdir_info->hash_map);
1401 if (fdir_info->hash_table)
1402 rte_hash_free(fdir_info->hash_table);
1404 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1405 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1411 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1414 struct rte_pci_device *pci_dev;
1415 struct rte_intr_handle *intr_handle;
1417 struct i40e_filter_control_settings settings;
1418 struct rte_flow *p_flow;
1420 uint8_t aq_fail = 0;
1422 PMD_INIT_FUNC_TRACE();
1424 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1427 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1428 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429 pci_dev = I40E_DEV_TO_PCI(dev);
1430 intr_handle = &pci_dev->intr_handle;
1432 if (hw->adapter_stopped == 0)
1433 i40e_dev_close(dev);
1435 dev->dev_ops = NULL;
1436 dev->rx_pkt_burst = NULL;
1437 dev->tx_pkt_burst = NULL;
1439 /* Clear PXE mode */
1440 i40e_clear_pxe_mode(hw);
1442 /* Unconfigure filter control */
1443 memset(&settings, 0, sizeof(settings));
1444 ret = i40e_set_filter_control(hw, &settings);
1446 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1449 /* Disable flow control */
1450 hw->fc.requested_mode = I40E_FC_NONE;
1451 i40e_set_fc(hw, &aq_fail, TRUE);
1453 /* uninitialize pf host driver */
1454 i40e_pf_host_uninit(dev);
1456 rte_free(dev->data->mac_addrs);
1457 dev->data->mac_addrs = NULL;
1459 /* disable uio intr before callback unregister */
1460 rte_intr_disable(intr_handle);
1462 /* register callback func to eal lib */
1463 rte_intr_callback_unregister(intr_handle,
1464 i40e_dev_interrupt_handler, dev);
1466 i40e_rm_ethtype_filter_list(pf);
1467 i40e_rm_tunnel_filter_list(pf);
1468 i40e_rm_fdir_filter_list(pf);
1470 /* Remove all flows */
1471 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1472 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1480 i40e_dev_configure(struct rte_eth_dev *dev)
1482 struct i40e_adapter *ad =
1483 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1484 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1485 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1488 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1489 * bulk allocation or vector Rx preconditions we will reset it.
1491 ad->rx_bulk_alloc_allowed = true;
1492 ad->rx_vec_allowed = true;
1493 ad->tx_simple_allowed = true;
1494 ad->tx_vec_allowed = true;
1496 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1497 ret = i40e_fdir_setup(pf);
1498 if (ret != I40E_SUCCESS) {
1499 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1502 ret = i40e_fdir_configure(dev);
1504 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1508 i40e_fdir_teardown(pf);
1510 ret = i40e_dev_init_vlan(dev);
1515 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1516 * RSS setting have different requirements.
1517 * General PMD driver call sequence are NIC init, configure,
1518 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1519 * will try to lookup the VSI that specific queue belongs to if VMDQ
1520 * applicable. So, VMDQ setting has to be done before
1521 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1522 * For RSS setting, it will try to calculate actual configured RX queue
1523 * number, which will be available after rx_queue_setup(). dev_start()
1524 * function is good to place RSS setup.
1526 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1527 ret = i40e_vmdq_setup(dev);
1532 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1533 ret = i40e_dcb_setup(dev);
1535 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1540 TAILQ_INIT(&pf->flow_list);
1545 /* need to release vmdq resource if exists */
1546 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1547 i40e_vsi_release(pf->vmdq[i].vsi);
1548 pf->vmdq[i].vsi = NULL;
1553 /* need to release fdir resource if exists */
1554 i40e_fdir_teardown(pf);
1559 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1561 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1562 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1565 uint16_t msix_vect = vsi->msix_intr;
1568 for (i = 0; i < vsi->nb_qps; i++) {
1569 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1570 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1574 if (vsi->type != I40E_VSI_SRIOV) {
1575 if (!rte_intr_allow_others(intr_handle)) {
1576 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1577 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1579 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1582 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1583 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1585 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1590 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1591 vsi->user_param + (msix_vect - 1);
1593 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1594 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1596 I40E_WRITE_FLUSH(hw);
1600 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1601 int base_queue, int nb_queue)
1605 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1607 /* Bind all RX queues to allocated MSIX interrupt */
1608 for (i = 0; i < nb_queue; i++) {
1609 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1610 I40E_QINT_RQCTL_ITR_INDX_MASK |
1611 ((base_queue + i + 1) <<
1612 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1613 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1614 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1616 if (i == nb_queue - 1)
1617 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1618 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1621 /* Write first RX queue to Link list register as the head element */
1622 if (vsi->type != I40E_VSI_SRIOV) {
1624 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1626 if (msix_vect == I40E_MISC_VEC_ID) {
1627 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1629 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1631 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1633 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1636 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1638 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1640 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1642 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1649 if (msix_vect == I40E_MISC_VEC_ID) {
1651 I40E_VPINT_LNKLST0(vsi->user_param),
1653 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1655 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1657 /* num_msix_vectors_vf needs to minus irq0 */
1658 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1659 vsi->user_param + (msix_vect - 1);
1661 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1663 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1665 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1669 I40E_WRITE_FLUSH(hw);
1673 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1675 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1676 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1677 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1678 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1679 uint16_t msix_vect = vsi->msix_intr;
1680 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1681 uint16_t queue_idx = 0;
1686 for (i = 0; i < vsi->nb_qps; i++) {
1687 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1688 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1691 /* INTENA flag is not auto-cleared for interrupt */
1692 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1693 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1694 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1695 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1696 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1698 /* VF bind interrupt */
1699 if (vsi->type == I40E_VSI_SRIOV) {
1700 __vsi_queues_bind_intr(vsi, msix_vect,
1701 vsi->base_queue, vsi->nb_qps);
1705 /* PF & VMDq bind interrupt */
1706 if (rte_intr_dp_is_en(intr_handle)) {
1707 if (vsi->type == I40E_VSI_MAIN) {
1710 } else if (vsi->type == I40E_VSI_VMDQ2) {
1711 struct i40e_vsi *main_vsi =
1712 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1713 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1718 for (i = 0; i < vsi->nb_used_qps; i++) {
1720 if (!rte_intr_allow_others(intr_handle))
1721 /* allow to share MISC_VEC_ID */
1722 msix_vect = I40E_MISC_VEC_ID;
1724 /* no enough msix_vect, map all to one */
1725 __vsi_queues_bind_intr(vsi, msix_vect,
1726 vsi->base_queue + i,
1727 vsi->nb_used_qps - i);
1728 for (; !!record && i < vsi->nb_used_qps; i++)
1729 intr_handle->intr_vec[queue_idx + i] =
1733 /* 1:1 queue/msix_vect mapping */
1734 __vsi_queues_bind_intr(vsi, msix_vect,
1735 vsi->base_queue + i, 1);
1737 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1745 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1747 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1748 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1749 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1750 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1751 uint16_t interval = i40e_calc_itr_interval(\
1752 RTE_LIBRTE_I40E_ITR_INTERVAL);
1753 uint16_t msix_intr, i;
1755 if (rte_intr_allow_others(intr_handle))
1756 for (i = 0; i < vsi->nb_msix; i++) {
1757 msix_intr = vsi->msix_intr + i;
1758 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1759 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1760 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1761 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1763 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1766 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1767 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1768 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1769 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1771 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1773 I40E_WRITE_FLUSH(hw);
1777 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1779 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1780 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1781 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1782 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1783 uint16_t msix_intr, i;
1785 if (rte_intr_allow_others(intr_handle))
1786 for (i = 0; i < vsi->nb_msix; i++) {
1787 msix_intr = vsi->msix_intr + i;
1788 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1792 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1794 I40E_WRITE_FLUSH(hw);
1797 static inline uint8_t
1798 i40e_parse_link_speeds(uint16_t link_speeds)
1800 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1802 if (link_speeds & ETH_LINK_SPEED_40G)
1803 link_speed |= I40E_LINK_SPEED_40GB;
1804 if (link_speeds & ETH_LINK_SPEED_25G)
1805 link_speed |= I40E_LINK_SPEED_25GB;
1806 if (link_speeds & ETH_LINK_SPEED_20G)
1807 link_speed |= I40E_LINK_SPEED_20GB;
1808 if (link_speeds & ETH_LINK_SPEED_10G)
1809 link_speed |= I40E_LINK_SPEED_10GB;
1810 if (link_speeds & ETH_LINK_SPEED_1G)
1811 link_speed |= I40E_LINK_SPEED_1GB;
1812 if (link_speeds & ETH_LINK_SPEED_100M)
1813 link_speed |= I40E_LINK_SPEED_100MB;
1819 i40e_phy_conf_link(struct i40e_hw *hw,
1821 uint8_t force_speed)
1823 enum i40e_status_code status;
1824 struct i40e_aq_get_phy_abilities_resp phy_ab;
1825 struct i40e_aq_set_phy_config phy_conf;
1826 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1827 I40E_AQ_PHY_FLAG_PAUSE_RX |
1828 I40E_AQ_PHY_FLAG_PAUSE_RX |
1829 I40E_AQ_PHY_FLAG_LOW_POWER;
1830 const uint8_t advt = I40E_LINK_SPEED_40GB |
1831 I40E_LINK_SPEED_25GB |
1832 I40E_LINK_SPEED_10GB |
1833 I40E_LINK_SPEED_1GB |
1834 I40E_LINK_SPEED_100MB;
1838 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1843 memset(&phy_conf, 0, sizeof(phy_conf));
1845 /* bits 0-2 use the values from get_phy_abilities_resp */
1847 abilities |= phy_ab.abilities & mask;
1849 /* update ablities and speed */
1850 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1851 phy_conf.link_speed = advt;
1853 phy_conf.link_speed = force_speed;
1855 phy_conf.abilities = abilities;
1857 /* use get_phy_abilities_resp value for the rest */
1858 phy_conf.phy_type = phy_ab.phy_type;
1859 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1860 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1861 phy_conf.eee_capability = phy_ab.eee_capability;
1862 phy_conf.eeer = phy_ab.eeer_val;
1863 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1865 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1866 phy_ab.abilities, phy_ab.link_speed);
1867 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1868 phy_conf.abilities, phy_conf.link_speed);
1870 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1874 return I40E_SUCCESS;
1878 i40e_apply_link_speed(struct rte_eth_dev *dev)
1881 uint8_t abilities = 0;
1882 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883 struct rte_eth_conf *conf = &dev->data->dev_conf;
1885 speed = i40e_parse_link_speeds(conf->link_speeds);
1886 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1887 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1888 abilities |= I40E_AQ_PHY_AN_ENABLED;
1889 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1891 /* Skip changing speed on 40G interfaces, FW does not support */
1892 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1893 speed = I40E_LINK_SPEED_UNKNOWN;
1894 abilities |= I40E_AQ_PHY_AN_ENABLED;
1897 return i40e_phy_conf_link(hw, abilities, speed);
1901 i40e_dev_start(struct rte_eth_dev *dev)
1903 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1904 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905 struct i40e_vsi *main_vsi = pf->main_vsi;
1907 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1908 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1909 uint32_t intr_vector = 0;
1910 struct i40e_vsi *vsi;
1912 hw->adapter_stopped = 0;
1914 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1915 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1916 dev->data->port_id);
1920 rte_intr_disable(intr_handle);
1922 if ((rte_intr_cap_multiple(intr_handle) ||
1923 !RTE_ETH_DEV_SRIOV(dev).active) &&
1924 dev->data->dev_conf.intr_conf.rxq != 0) {
1925 intr_vector = dev->data->nb_rx_queues;
1926 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1931 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1932 intr_handle->intr_vec =
1933 rte_zmalloc("intr_vec",
1934 dev->data->nb_rx_queues * sizeof(int),
1936 if (!intr_handle->intr_vec) {
1938 "Failed to allocate %d rx_queues intr_vec",
1939 dev->data->nb_rx_queues);
1944 /* Initialize VSI */
1945 ret = i40e_dev_rxtx_init(pf);
1946 if (ret != I40E_SUCCESS) {
1947 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1951 /* Map queues with MSIX interrupt */
1952 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1953 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1954 i40e_vsi_queues_bind_intr(main_vsi);
1955 i40e_vsi_enable_queues_intr(main_vsi);
1957 /* Map VMDQ VSI queues with MSIX interrupt */
1958 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1959 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1960 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1961 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1964 /* enable FDIR MSIX interrupt */
1965 if (pf->fdir.fdir_vsi) {
1966 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1967 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1970 /* Enable all queues which have been configured */
1971 ret = i40e_dev_switch_queues(pf, TRUE);
1972 if (ret != I40E_SUCCESS) {
1973 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1977 /* Enable receiving broadcast packets */
1978 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1979 if (ret != I40E_SUCCESS)
1980 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1982 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1983 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1985 if (ret != I40E_SUCCESS)
1986 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1989 /* Enable the VLAN promiscuous mode. */
1991 for (i = 0; i < pf->vf_num; i++) {
1992 vsi = pf->vfs[i].vsi;
1993 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1998 /* Apply link configure */
1999 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2000 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2001 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2002 ETH_LINK_SPEED_40G)) {
2003 PMD_DRV_LOG(ERR, "Invalid link setting");
2006 ret = i40e_apply_link_speed(dev);
2007 if (I40E_SUCCESS != ret) {
2008 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2012 if (!rte_intr_allow_others(intr_handle)) {
2013 rte_intr_callback_unregister(intr_handle,
2014 i40e_dev_interrupt_handler,
2016 /* configure and enable device interrupt */
2017 i40e_pf_config_irq0(hw, FALSE);
2018 i40e_pf_enable_irq0(hw);
2020 if (dev->data->dev_conf.intr_conf.lsc != 0)
2022 "lsc won't enable because of no intr multiplex");
2023 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2024 ret = i40e_aq_set_phy_int_mask(hw,
2025 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2026 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2027 I40E_AQ_EVENT_MEDIA_NA), NULL);
2028 if (ret != I40E_SUCCESS)
2029 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2031 /* Call get_link_info aq commond to enable LSE */
2032 i40e_dev_link_update(dev, 0);
2035 /* enable uio intr after callback register */
2036 rte_intr_enable(intr_handle);
2038 i40e_filter_restore(pf);
2040 return I40E_SUCCESS;
2043 i40e_dev_switch_queues(pf, FALSE);
2044 i40e_dev_clear_queues(dev);
2050 i40e_dev_stop(struct rte_eth_dev *dev)
2052 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2053 struct i40e_vsi *main_vsi = pf->main_vsi;
2054 struct i40e_mirror_rule *p_mirror;
2055 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2056 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2059 /* Disable all queues */
2060 i40e_dev_switch_queues(pf, FALSE);
2062 /* un-map queues with interrupt registers */
2063 i40e_vsi_disable_queues_intr(main_vsi);
2064 i40e_vsi_queues_unbind_intr(main_vsi);
2066 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2067 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2068 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2071 if (pf->fdir.fdir_vsi) {
2072 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2073 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2075 /* Clear all queues and release memory */
2076 i40e_dev_clear_queues(dev);
2079 i40e_dev_set_link_down(dev);
2081 /* Remove all mirror rules */
2082 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2083 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2086 pf->nb_mirror_rule = 0;
2088 if (!rte_intr_allow_others(intr_handle))
2089 /* resume to the default handler */
2090 rte_intr_callback_register(intr_handle,
2091 i40e_dev_interrupt_handler,
2094 /* Clean datapath event and queue/vec mapping */
2095 rte_intr_efd_disable(intr_handle);
2096 if (intr_handle->intr_vec) {
2097 rte_free(intr_handle->intr_vec);
2098 intr_handle->intr_vec = NULL;
2103 i40e_dev_close(struct rte_eth_dev *dev)
2105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2108 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2112 PMD_INIT_FUNC_TRACE();
2115 hw->adapter_stopped = 1;
2116 i40e_dev_free_queues(dev);
2118 /* Disable interrupt */
2119 i40e_pf_disable_irq0(hw);
2120 rte_intr_disable(intr_handle);
2122 /* shutdown and destroy the HMC */
2123 i40e_shutdown_lan_hmc(hw);
2125 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2126 i40e_vsi_release(pf->vmdq[i].vsi);
2127 pf->vmdq[i].vsi = NULL;
2132 /* release all the existing VSIs and VEBs */
2133 i40e_fdir_teardown(pf);
2134 i40e_vsi_release(pf->main_vsi);
2136 /* shutdown the adminq */
2137 i40e_aq_queue_shutdown(hw, true);
2138 i40e_shutdown_adminq(hw);
2140 i40e_res_pool_destroy(&pf->qp_pool);
2141 i40e_res_pool_destroy(&pf->msix_pool);
2143 /* force a PF reset to clean anything leftover */
2144 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2145 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2146 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2147 I40E_WRITE_FLUSH(hw);
2151 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2153 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2154 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155 struct i40e_vsi *vsi = pf->main_vsi;
2158 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2160 if (status != I40E_SUCCESS)
2161 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2163 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2165 if (status != I40E_SUCCESS)
2166 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2171 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2173 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175 struct i40e_vsi *vsi = pf->main_vsi;
2178 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2180 if (status != I40E_SUCCESS)
2181 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2183 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2185 if (status != I40E_SUCCESS)
2186 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2190 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2192 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194 struct i40e_vsi *vsi = pf->main_vsi;
2197 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2198 if (ret != I40E_SUCCESS)
2199 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2203 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2205 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2206 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207 struct i40e_vsi *vsi = pf->main_vsi;
2210 if (dev->data->promiscuous == 1)
2211 return; /* must remain in all_multicast mode */
2213 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2214 vsi->seid, FALSE, NULL);
2215 if (ret != I40E_SUCCESS)
2216 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2220 * Set device link up.
2223 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2225 /* re-apply link speed setting */
2226 return i40e_apply_link_speed(dev);
2230 * Set device link down.
2233 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2235 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2236 uint8_t abilities = 0;
2237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2240 return i40e_phy_conf_link(hw, abilities, speed);
2244 i40e_dev_link_update(struct rte_eth_dev *dev,
2245 int wait_to_complete)
2247 #define CHECK_INTERVAL 100 /* 100ms */
2248 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2249 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250 struct i40e_link_status link_status;
2251 struct rte_eth_link link, old;
2253 unsigned rep_cnt = MAX_REPEAT_TIME;
2254 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2256 memset(&link, 0, sizeof(link));
2257 memset(&old, 0, sizeof(old));
2258 memset(&link_status, 0, sizeof(link_status));
2259 rte_i40e_dev_atomic_read_link_status(dev, &old);
2262 /* Get link status information from hardware */
2263 status = i40e_aq_get_link_info(hw, enable_lse,
2264 &link_status, NULL);
2265 if (status != I40E_SUCCESS) {
2266 link.link_speed = ETH_SPEED_NUM_100M;
2267 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2268 PMD_DRV_LOG(ERR, "Failed to get link info");
2272 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2273 if (!wait_to_complete || link.link_status)
2276 rte_delay_ms(CHECK_INTERVAL);
2277 } while (--rep_cnt);
2279 if (!link.link_status)
2282 /* i40e uses full duplex only */
2283 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2285 /* Parse the link status */
2286 switch (link_status.link_speed) {
2287 case I40E_LINK_SPEED_100MB:
2288 link.link_speed = ETH_SPEED_NUM_100M;
2290 case I40E_LINK_SPEED_1GB:
2291 link.link_speed = ETH_SPEED_NUM_1G;
2293 case I40E_LINK_SPEED_10GB:
2294 link.link_speed = ETH_SPEED_NUM_10G;
2296 case I40E_LINK_SPEED_20GB:
2297 link.link_speed = ETH_SPEED_NUM_20G;
2299 case I40E_LINK_SPEED_25GB:
2300 link.link_speed = ETH_SPEED_NUM_25G;
2302 case I40E_LINK_SPEED_40GB:
2303 link.link_speed = ETH_SPEED_NUM_40G;
2306 link.link_speed = ETH_SPEED_NUM_100M;
2310 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2311 ETH_LINK_SPEED_FIXED);
2314 rte_i40e_dev_atomic_write_link_status(dev, &link);
2315 if (link.link_status == old.link_status)
2321 /* Get all the statistics of a VSI */
2323 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2325 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2326 struct i40e_eth_stats *nes = &vsi->eth_stats;
2327 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2328 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2330 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2331 vsi->offset_loaded, &oes->rx_bytes,
2333 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2334 vsi->offset_loaded, &oes->rx_unicast,
2336 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2337 vsi->offset_loaded, &oes->rx_multicast,
2338 &nes->rx_multicast);
2339 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2340 vsi->offset_loaded, &oes->rx_broadcast,
2341 &nes->rx_broadcast);
2342 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2343 &oes->rx_discards, &nes->rx_discards);
2344 /* GLV_REPC not supported */
2345 /* GLV_RMPC not supported */
2346 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2347 &oes->rx_unknown_protocol,
2348 &nes->rx_unknown_protocol);
2349 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2350 vsi->offset_loaded, &oes->tx_bytes,
2352 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2353 vsi->offset_loaded, &oes->tx_unicast,
2355 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2356 vsi->offset_loaded, &oes->tx_multicast,
2357 &nes->tx_multicast);
2358 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2359 vsi->offset_loaded, &oes->tx_broadcast,
2360 &nes->tx_broadcast);
2361 /* GLV_TDPC not supported */
2362 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2363 &oes->tx_errors, &nes->tx_errors);
2364 vsi->offset_loaded = true;
2366 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2368 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2369 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2370 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2371 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2372 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2373 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2374 nes->rx_unknown_protocol);
2375 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2376 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2377 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2378 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2379 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2380 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2381 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2386 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2389 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2390 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2392 /* Get statistics of struct i40e_eth_stats */
2393 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2394 I40E_GLPRT_GORCL(hw->port),
2395 pf->offset_loaded, &os->eth.rx_bytes,
2397 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2398 I40E_GLPRT_UPRCL(hw->port),
2399 pf->offset_loaded, &os->eth.rx_unicast,
2400 &ns->eth.rx_unicast);
2401 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2402 I40E_GLPRT_MPRCL(hw->port),
2403 pf->offset_loaded, &os->eth.rx_multicast,
2404 &ns->eth.rx_multicast);
2405 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2406 I40E_GLPRT_BPRCL(hw->port),
2407 pf->offset_loaded, &os->eth.rx_broadcast,
2408 &ns->eth.rx_broadcast);
2409 /* Workaround: CRC size should not be included in byte statistics,
2410 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2412 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2413 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2415 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2416 pf->offset_loaded, &os->eth.rx_discards,
2417 &ns->eth.rx_discards);
2418 /* GLPRT_REPC not supported */
2419 /* GLPRT_RMPC not supported */
2420 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2422 &os->eth.rx_unknown_protocol,
2423 &ns->eth.rx_unknown_protocol);
2424 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2425 I40E_GLPRT_GOTCL(hw->port),
2426 pf->offset_loaded, &os->eth.tx_bytes,
2428 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2429 I40E_GLPRT_UPTCL(hw->port),
2430 pf->offset_loaded, &os->eth.tx_unicast,
2431 &ns->eth.tx_unicast);
2432 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2433 I40E_GLPRT_MPTCL(hw->port),
2434 pf->offset_loaded, &os->eth.tx_multicast,
2435 &ns->eth.tx_multicast);
2436 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2437 I40E_GLPRT_BPTCL(hw->port),
2438 pf->offset_loaded, &os->eth.tx_broadcast,
2439 &ns->eth.tx_broadcast);
2440 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2441 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2442 /* GLPRT_TEPC not supported */
2444 /* additional port specific stats */
2445 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2446 pf->offset_loaded, &os->tx_dropped_link_down,
2447 &ns->tx_dropped_link_down);
2448 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2449 pf->offset_loaded, &os->crc_errors,
2451 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2452 pf->offset_loaded, &os->illegal_bytes,
2453 &ns->illegal_bytes);
2454 /* GLPRT_ERRBC not supported */
2455 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2456 pf->offset_loaded, &os->mac_local_faults,
2457 &ns->mac_local_faults);
2458 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2459 pf->offset_loaded, &os->mac_remote_faults,
2460 &ns->mac_remote_faults);
2461 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2462 pf->offset_loaded, &os->rx_length_errors,
2463 &ns->rx_length_errors);
2464 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2465 pf->offset_loaded, &os->link_xon_rx,
2467 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2468 pf->offset_loaded, &os->link_xoff_rx,
2470 for (i = 0; i < 8; i++) {
2471 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2473 &os->priority_xon_rx[i],
2474 &ns->priority_xon_rx[i]);
2475 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2477 &os->priority_xoff_rx[i],
2478 &ns->priority_xoff_rx[i]);
2480 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2481 pf->offset_loaded, &os->link_xon_tx,
2483 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2484 pf->offset_loaded, &os->link_xoff_tx,
2486 for (i = 0; i < 8; i++) {
2487 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2489 &os->priority_xon_tx[i],
2490 &ns->priority_xon_tx[i]);
2491 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2493 &os->priority_xoff_tx[i],
2494 &ns->priority_xoff_tx[i]);
2495 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2497 &os->priority_xon_2_xoff[i],
2498 &ns->priority_xon_2_xoff[i]);
2500 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2501 I40E_GLPRT_PRC64L(hw->port),
2502 pf->offset_loaded, &os->rx_size_64,
2504 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2505 I40E_GLPRT_PRC127L(hw->port),
2506 pf->offset_loaded, &os->rx_size_127,
2508 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2509 I40E_GLPRT_PRC255L(hw->port),
2510 pf->offset_loaded, &os->rx_size_255,
2512 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2513 I40E_GLPRT_PRC511L(hw->port),
2514 pf->offset_loaded, &os->rx_size_511,
2516 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2517 I40E_GLPRT_PRC1023L(hw->port),
2518 pf->offset_loaded, &os->rx_size_1023,
2520 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2521 I40E_GLPRT_PRC1522L(hw->port),
2522 pf->offset_loaded, &os->rx_size_1522,
2524 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2525 I40E_GLPRT_PRC9522L(hw->port),
2526 pf->offset_loaded, &os->rx_size_big,
2528 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2529 pf->offset_loaded, &os->rx_undersize,
2531 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2532 pf->offset_loaded, &os->rx_fragments,
2534 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2535 pf->offset_loaded, &os->rx_oversize,
2537 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2538 pf->offset_loaded, &os->rx_jabber,
2540 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2541 I40E_GLPRT_PTC64L(hw->port),
2542 pf->offset_loaded, &os->tx_size_64,
2544 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2545 I40E_GLPRT_PTC127L(hw->port),
2546 pf->offset_loaded, &os->tx_size_127,
2548 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2549 I40E_GLPRT_PTC255L(hw->port),
2550 pf->offset_loaded, &os->tx_size_255,
2552 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2553 I40E_GLPRT_PTC511L(hw->port),
2554 pf->offset_loaded, &os->tx_size_511,
2556 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2557 I40E_GLPRT_PTC1023L(hw->port),
2558 pf->offset_loaded, &os->tx_size_1023,
2560 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2561 I40E_GLPRT_PTC1522L(hw->port),
2562 pf->offset_loaded, &os->tx_size_1522,
2564 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2565 I40E_GLPRT_PTC9522L(hw->port),
2566 pf->offset_loaded, &os->tx_size_big,
2568 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2570 &os->fd_sb_match, &ns->fd_sb_match);
2571 /* GLPRT_MSPDC not supported */
2572 /* GLPRT_XEC not supported */
2574 pf->offset_loaded = true;
2577 i40e_update_vsi_stats(pf->main_vsi);
2580 /* Get all statistics of a port */
2582 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2584 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2585 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2589 /* call read registers - updates values, now write them to struct */
2590 i40e_read_stats_registers(pf, hw);
2592 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2593 pf->main_vsi->eth_stats.rx_multicast +
2594 pf->main_vsi->eth_stats.rx_broadcast -
2595 pf->main_vsi->eth_stats.rx_discards;
2596 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2597 pf->main_vsi->eth_stats.tx_multicast +
2598 pf->main_vsi->eth_stats.tx_broadcast;
2599 stats->ibytes = ns->eth.rx_bytes;
2600 stats->obytes = ns->eth.tx_bytes;
2601 stats->oerrors = ns->eth.tx_errors +
2602 pf->main_vsi->eth_stats.tx_errors;
2605 stats->imissed = ns->eth.rx_discards +
2606 pf->main_vsi->eth_stats.rx_discards;
2607 stats->ierrors = ns->crc_errors +
2608 ns->rx_length_errors + ns->rx_undersize +
2609 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2611 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2612 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2613 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2614 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2615 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2616 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2617 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2618 ns->eth.rx_unknown_protocol);
2619 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2620 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2621 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2622 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2623 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2624 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2626 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2627 ns->tx_dropped_link_down);
2628 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2629 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2631 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2632 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2633 ns->mac_local_faults);
2634 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2635 ns->mac_remote_faults);
2636 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2637 ns->rx_length_errors);
2638 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2639 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2640 for (i = 0; i < 8; i++) {
2641 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2642 i, ns->priority_xon_rx[i]);
2643 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2644 i, ns->priority_xoff_rx[i]);
2646 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2647 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2648 for (i = 0; i < 8; i++) {
2649 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2650 i, ns->priority_xon_tx[i]);
2651 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2652 i, ns->priority_xoff_tx[i]);
2653 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2654 i, ns->priority_xon_2_xoff[i]);
2656 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2657 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2658 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2659 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2660 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2661 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2662 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2663 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2664 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2665 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2666 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2667 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2668 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2669 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2670 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2671 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2672 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2673 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2674 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2675 ns->mac_short_packet_dropped);
2676 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2677 ns->checksum_error);
2678 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2679 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2682 /* Reset the statistics */
2684 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2686 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2687 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689 /* Mark PF and VSI stats to update the offset, aka "reset" */
2690 pf->offset_loaded = false;
2692 pf->main_vsi->offset_loaded = false;
2694 /* read the stats, reading current register values into offset */
2695 i40e_read_stats_registers(pf, hw);
2699 i40e_xstats_calc_num(void)
2701 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2702 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2703 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2706 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2707 struct rte_eth_xstat_name *xstats_names,
2708 __rte_unused unsigned limit)
2713 if (xstats_names == NULL)
2714 return i40e_xstats_calc_num();
2716 /* Note: limit checked in rte_eth_xstats_names() */
2718 /* Get stats from i40e_eth_stats struct */
2719 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2720 snprintf(xstats_names[count].name,
2721 sizeof(xstats_names[count].name),
2722 "%s", rte_i40e_stats_strings[i].name);
2726 /* Get individiual stats from i40e_hw_port struct */
2727 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2728 snprintf(xstats_names[count].name,
2729 sizeof(xstats_names[count].name),
2730 "%s", rte_i40e_hw_port_strings[i].name);
2734 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2735 for (prio = 0; prio < 8; prio++) {
2736 snprintf(xstats_names[count].name,
2737 sizeof(xstats_names[count].name),
2738 "rx_priority%u_%s", prio,
2739 rte_i40e_rxq_prio_strings[i].name);
2744 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2745 for (prio = 0; prio < 8; prio++) {
2746 snprintf(xstats_names[count].name,
2747 sizeof(xstats_names[count].name),
2748 "tx_priority%u_%s", prio,
2749 rte_i40e_txq_prio_strings[i].name);
2757 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2760 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2761 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762 unsigned i, count, prio;
2763 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2765 count = i40e_xstats_calc_num();
2769 i40e_read_stats_registers(pf, hw);
2776 /* Get stats from i40e_eth_stats struct */
2777 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2778 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2779 rte_i40e_stats_strings[i].offset);
2780 xstats[count].id = count;
2784 /* Get individiual stats from i40e_hw_port struct */
2785 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2786 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2787 rte_i40e_hw_port_strings[i].offset);
2788 xstats[count].id = count;
2792 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2793 for (prio = 0; prio < 8; prio++) {
2794 xstats[count].value =
2795 *(uint64_t *)(((char *)hw_stats) +
2796 rte_i40e_rxq_prio_strings[i].offset +
2797 (sizeof(uint64_t) * prio));
2798 xstats[count].id = count;
2803 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2804 for (prio = 0; prio < 8; prio++) {
2805 xstats[count].value =
2806 *(uint64_t *)(((char *)hw_stats) +
2807 rte_i40e_txq_prio_strings[i].offset +
2808 (sizeof(uint64_t) * prio));
2809 xstats[count].id = count;
2818 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2819 __rte_unused uint16_t queue_id,
2820 __rte_unused uint8_t stat_idx,
2821 __rte_unused uint8_t is_rx)
2823 PMD_INIT_FUNC_TRACE();
2829 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837 full_ver = hw->nvm.oem_ver;
2838 ver = (u8)(full_ver >> 24);
2839 build = (u16)((full_ver >> 8) & 0xffff);
2840 patch = (u8)(full_ver & 0xff);
2842 ret = snprintf(fw_version, fw_size,
2843 "%d.%d%d 0x%08x %d.%d.%d",
2844 ((hw->nvm.version >> 12) & 0xf),
2845 ((hw->nvm.version >> 4) & 0xff),
2846 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2849 ret += 1; /* add the size of '\0' */
2850 if (fw_size < (u32)ret)
2857 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2859 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 struct i40e_vsi *vsi = pf->main_vsi;
2862 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2864 dev_info->pci_dev = pci_dev;
2865 dev_info->max_rx_queues = vsi->nb_qps;
2866 dev_info->max_tx_queues = vsi->nb_qps;
2867 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2868 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2869 dev_info->max_mac_addrs = vsi->max_macaddrs;
2870 dev_info->max_vfs = pci_dev->max_vfs;
2871 dev_info->rx_offload_capa =
2872 DEV_RX_OFFLOAD_VLAN_STRIP |
2873 DEV_RX_OFFLOAD_QINQ_STRIP |
2874 DEV_RX_OFFLOAD_IPV4_CKSUM |
2875 DEV_RX_OFFLOAD_UDP_CKSUM |
2876 DEV_RX_OFFLOAD_TCP_CKSUM;
2877 dev_info->tx_offload_capa =
2878 DEV_TX_OFFLOAD_VLAN_INSERT |
2879 DEV_TX_OFFLOAD_QINQ_INSERT |
2880 DEV_TX_OFFLOAD_IPV4_CKSUM |
2881 DEV_TX_OFFLOAD_UDP_CKSUM |
2882 DEV_TX_OFFLOAD_TCP_CKSUM |
2883 DEV_TX_OFFLOAD_SCTP_CKSUM |
2884 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2885 DEV_TX_OFFLOAD_TCP_TSO |
2886 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2887 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2888 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2889 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2890 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2892 dev_info->reta_size = pf->hash_lut_size;
2893 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2895 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2897 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2898 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2899 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2901 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2905 dev_info->default_txconf = (struct rte_eth_txconf) {
2907 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2908 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2909 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2911 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2912 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2913 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2914 ETH_TXQ_FLAGS_NOOFFLOADS,
2917 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2918 .nb_max = I40E_MAX_RING_DESC,
2919 .nb_min = I40E_MIN_RING_DESC,
2920 .nb_align = I40E_ALIGN_RING_DESC,
2923 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2924 .nb_max = I40E_MAX_RING_DESC,
2925 .nb_min = I40E_MIN_RING_DESC,
2926 .nb_align = I40E_ALIGN_RING_DESC,
2927 .nb_seg_max = I40E_TX_MAX_SEG,
2928 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2931 if (pf->flags & I40E_FLAG_VMDQ) {
2932 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2933 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2934 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2935 pf->max_nb_vmdq_vsi;
2936 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2937 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2938 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2941 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2943 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2944 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2946 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2949 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2953 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2956 struct i40e_vsi *vsi = pf->main_vsi;
2957 PMD_INIT_FUNC_TRACE();
2960 return i40e_vsi_add_vlan(vsi, vlan_id);
2962 return i40e_vsi_delete_vlan(vsi, vlan_id);
2966 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2967 enum rte_vlan_type vlan_type,
2970 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 uint64_t reg_r = 0, reg_w = 0;
2972 uint16_t reg_id = 0;
2974 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2976 switch (vlan_type) {
2977 case ETH_VLAN_TYPE_OUTER:
2983 case ETH_VLAN_TYPE_INNER:
2989 "Unsupported vlan type in single vlan.");
2995 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2998 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3000 if (ret != I40E_SUCCESS) {
3002 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3008 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3011 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3012 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3013 if (reg_r == reg_w) {
3015 PMD_DRV_LOG(DEBUG, "No need to write");
3019 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3021 if (ret != I40E_SUCCESS) {
3024 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3029 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3036 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3038 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3039 struct i40e_vsi *vsi = pf->main_vsi;
3041 if (mask & ETH_VLAN_FILTER_MASK) {
3042 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3043 i40e_vsi_config_vlan_filter(vsi, TRUE);
3045 i40e_vsi_config_vlan_filter(vsi, FALSE);
3048 if (mask & ETH_VLAN_STRIP_MASK) {
3049 /* Enable or disable VLAN stripping */
3050 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3051 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3053 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3056 if (mask & ETH_VLAN_EXTEND_MASK) {
3057 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3058 i40e_vsi_config_double_vlan(vsi, TRUE);
3059 /* Set global registers with default ether type value */
3060 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3062 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3066 i40e_vsi_config_double_vlan(vsi, FALSE);
3071 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3072 __rte_unused uint16_t queue,
3073 __rte_unused int on)
3075 PMD_INIT_FUNC_TRACE();
3079 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3081 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3082 struct i40e_vsi *vsi = pf->main_vsi;
3083 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3084 struct i40e_vsi_vlan_pvid_info info;
3086 memset(&info, 0, sizeof(info));
3089 info.config.pvid = pvid;
3091 info.config.reject.tagged =
3092 data->dev_conf.txmode.hw_vlan_reject_tagged;
3093 info.config.reject.untagged =
3094 data->dev_conf.txmode.hw_vlan_reject_untagged;
3097 return i40e_vsi_vlan_pvid_set(vsi, &info);
3101 i40e_dev_led_on(struct rte_eth_dev *dev)
3103 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104 uint32_t mode = i40e_led_get(hw);
3107 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3113 i40e_dev_led_off(struct rte_eth_dev *dev)
3115 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116 uint32_t mode = i40e_led_get(hw);
3119 i40e_led_set(hw, 0, false);
3125 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3127 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3128 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3130 fc_conf->pause_time = pf->fc_conf.pause_time;
3131 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3132 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3134 /* Return current mode according to actual setting*/
3135 switch (hw->fc.current_mode) {
3137 fc_conf->mode = RTE_FC_FULL;
3139 case I40E_FC_TX_PAUSE:
3140 fc_conf->mode = RTE_FC_TX_PAUSE;
3142 case I40E_FC_RX_PAUSE:
3143 fc_conf->mode = RTE_FC_RX_PAUSE;
3147 fc_conf->mode = RTE_FC_NONE;
3154 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3156 uint32_t mflcn_reg, fctrl_reg, reg;
3157 uint32_t max_high_water;
3158 uint8_t i, aq_failure;
3162 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3163 [RTE_FC_NONE] = I40E_FC_NONE,
3164 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3165 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3166 [RTE_FC_FULL] = I40E_FC_FULL
3169 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3171 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3172 if ((fc_conf->high_water > max_high_water) ||
3173 (fc_conf->high_water < fc_conf->low_water)) {
3175 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3180 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3182 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3184 pf->fc_conf.pause_time = fc_conf->pause_time;
3185 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3186 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3188 PMD_INIT_FUNC_TRACE();
3190 /* All the link flow control related enable/disable register
3191 * configuration is handle by the F/W
3193 err = i40e_set_fc(hw, &aq_failure, true);
3197 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3198 /* Configure flow control refresh threshold,
3199 * the value for stat_tx_pause_refresh_timer[8]
3200 * is used for global pause operation.
3204 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3205 pf->fc_conf.pause_time);
3207 /* configure the timer value included in transmitted pause
3209 * the value for stat_tx_pause_quanta[8] is used for global
3212 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3213 pf->fc_conf.pause_time);
3215 fctrl_reg = I40E_READ_REG(hw,
3216 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3218 if (fc_conf->mac_ctrl_frame_fwd != 0)
3219 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3221 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3223 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3226 /* Configure pause time (2 TCs per register) */
3227 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3228 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3229 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3231 /* Configure flow control refresh threshold value */
3232 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3233 pf->fc_conf.pause_time / 2);
3235 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3237 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3238 *depending on configuration
3240 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3241 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3242 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3244 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3245 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3248 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3251 /* config the water marker both based on the packets and bytes */
3252 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3253 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3254 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3255 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3256 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3257 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3258 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3259 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3261 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3262 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3265 I40E_WRITE_FLUSH(hw);
3271 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3272 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3274 PMD_INIT_FUNC_TRACE();
3279 /* Add a MAC address, and update filters */
3281 i40e_macaddr_add(struct rte_eth_dev *dev,
3282 struct ether_addr *mac_addr,
3283 __rte_unused uint32_t index,
3286 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3287 struct i40e_mac_filter_info mac_filter;
3288 struct i40e_vsi *vsi;
3291 /* If VMDQ not enabled or configured, return */
3292 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3293 !pf->nb_cfg_vmdq_vsi)) {
3294 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3295 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3300 if (pool > pf->nb_cfg_vmdq_vsi) {
3301 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3302 pool, pf->nb_cfg_vmdq_vsi);
3306 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3307 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3308 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3310 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3315 vsi = pf->vmdq[pool - 1].vsi;
3317 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3318 if (ret != I40E_SUCCESS) {
3319 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3324 /* Remove a MAC address, and update filters */
3326 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3328 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3329 struct i40e_vsi *vsi;
3330 struct rte_eth_dev_data *data = dev->data;
3331 struct ether_addr *macaddr;
3336 macaddr = &(data->mac_addrs[index]);
3338 pool_sel = dev->data->mac_pool_sel[index];
3340 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3341 if (pool_sel & (1ULL << i)) {
3345 /* No VMDQ pool enabled or configured */
3346 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3347 (i > pf->nb_cfg_vmdq_vsi)) {
3349 "No VMDQ pool enabled/configured");
3352 vsi = pf->vmdq[i - 1].vsi;
3354 ret = i40e_vsi_delete_mac(vsi, macaddr);
3357 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3364 /* Set perfect match or hash match of MAC and VLAN for a VF */
3366 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3367 struct rte_eth_mac_filter *filter,
3371 struct i40e_mac_filter_info mac_filter;
3372 struct ether_addr old_mac;
3373 struct ether_addr *new_mac;
3374 struct i40e_pf_vf *vf = NULL;
3379 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3382 hw = I40E_PF_TO_HW(pf);
3384 if (filter == NULL) {
3385 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3389 new_mac = &filter->mac_addr;
3391 if (is_zero_ether_addr(new_mac)) {
3392 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3396 vf_id = filter->dst_id;
3398 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3399 PMD_DRV_LOG(ERR, "Invalid argument.");
3402 vf = &pf->vfs[vf_id];
3404 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3405 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3410 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3411 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3413 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3416 mac_filter.filter_type = filter->filter_type;
3417 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3418 if (ret != I40E_SUCCESS) {
3419 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3422 ether_addr_copy(new_mac, &pf->dev_addr);
3424 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3426 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3427 if (ret != I40E_SUCCESS) {
3428 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3432 /* Clear device address as it has been removed */
3433 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3434 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3440 /* MAC filter handle */
3442 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3445 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446 struct rte_eth_mac_filter *filter;
3447 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3448 int ret = I40E_NOT_SUPPORTED;
3450 filter = (struct rte_eth_mac_filter *)(arg);
3452 switch (filter_op) {
3453 case RTE_ETH_FILTER_NOP:
3456 case RTE_ETH_FILTER_ADD:
3457 i40e_pf_disable_irq0(hw);
3459 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3460 i40e_pf_enable_irq0(hw);
3462 case RTE_ETH_FILTER_DELETE:
3463 i40e_pf_disable_irq0(hw);
3465 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3466 i40e_pf_enable_irq0(hw);
3469 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3470 ret = I40E_ERR_PARAM;
3478 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3480 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3481 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3487 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3488 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3491 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3495 uint32_t *lut_dw = (uint32_t *)lut;
3496 uint16_t i, lut_size_dw = lut_size / 4;
3498 for (i = 0; i < lut_size_dw; i++)
3499 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3506 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3515 pf = I40E_VSI_TO_PF(vsi);
3516 hw = I40E_VSI_TO_HW(vsi);
3518 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3519 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3522 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3526 uint32_t *lut_dw = (uint32_t *)lut;
3527 uint16_t i, lut_size_dw = lut_size / 4;
3529 for (i = 0; i < lut_size_dw; i++)
3530 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3531 I40E_WRITE_FLUSH(hw);
3538 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3539 struct rte_eth_rss_reta_entry64 *reta_conf,
3542 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3543 uint16_t i, lut_size = pf->hash_lut_size;
3544 uint16_t idx, shift;
3548 if (reta_size != lut_size ||
3549 reta_size > ETH_RSS_RETA_SIZE_512) {
3551 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3552 reta_size, lut_size);
3556 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3558 PMD_DRV_LOG(ERR, "No memory can be allocated");
3561 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3564 for (i = 0; i < reta_size; i++) {
3565 idx = i / RTE_RETA_GROUP_SIZE;
3566 shift = i % RTE_RETA_GROUP_SIZE;
3567 if (reta_conf[idx].mask & (1ULL << shift))
3568 lut[i] = reta_conf[idx].reta[shift];
3570 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3579 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3580 struct rte_eth_rss_reta_entry64 *reta_conf,
3583 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3584 uint16_t i, lut_size = pf->hash_lut_size;
3585 uint16_t idx, shift;
3589 if (reta_size != lut_size ||
3590 reta_size > ETH_RSS_RETA_SIZE_512) {
3592 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3593 reta_size, lut_size);
3597 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3599 PMD_DRV_LOG(ERR, "No memory can be allocated");
3603 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3606 for (i = 0; i < reta_size; i++) {
3607 idx = i / RTE_RETA_GROUP_SIZE;
3608 shift = i % RTE_RETA_GROUP_SIZE;
3609 if (reta_conf[idx].mask & (1ULL << shift))
3610 reta_conf[idx].reta[shift] = lut[i];
3620 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3621 * @hw: pointer to the HW structure
3622 * @mem: pointer to mem struct to fill out
3623 * @size: size of memory requested
3624 * @alignment: what to align the allocation to
3626 enum i40e_status_code
3627 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3628 struct i40e_dma_mem *mem,
3632 const struct rte_memzone *mz = NULL;
3633 char z_name[RTE_MEMZONE_NAMESIZE];
3636 return I40E_ERR_PARAM;
3638 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3639 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3640 alignment, RTE_PGSIZE_2M);
3642 return I40E_ERR_NO_MEMORY;
3646 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3647 mem->zone = (const void *)mz;
3649 "memzone %s allocated with physical address: %"PRIu64,
3652 return I40E_SUCCESS;
3656 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3657 * @hw: pointer to the HW structure
3658 * @mem: ptr to mem struct to free
3660 enum i40e_status_code
3661 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3662 struct i40e_dma_mem *mem)
3665 return I40E_ERR_PARAM;
3668 "memzone %s to be freed with physical address: %"PRIu64,
3669 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3670 rte_memzone_free((const struct rte_memzone *)mem->zone);
3675 return I40E_SUCCESS;
3679 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3680 * @hw: pointer to the HW structure
3681 * @mem: pointer to mem struct to fill out
3682 * @size: size of memory requested
3684 enum i40e_status_code
3685 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3686 struct i40e_virt_mem *mem,
3690 return I40E_ERR_PARAM;
3693 mem->va = rte_zmalloc("i40e", size, 0);
3696 return I40E_SUCCESS;
3698 return I40E_ERR_NO_MEMORY;
3702 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3703 * @hw: pointer to the HW structure
3704 * @mem: pointer to mem struct to free
3706 enum i40e_status_code
3707 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3708 struct i40e_virt_mem *mem)
3711 return I40E_ERR_PARAM;
3716 return I40E_SUCCESS;
3720 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3722 rte_spinlock_init(&sp->spinlock);
3726 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3728 rte_spinlock_lock(&sp->spinlock);
3732 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3734 rte_spinlock_unlock(&sp->spinlock);
3738 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3744 * Get the hardware capabilities, which will be parsed
3745 * and saved into struct i40e_hw.
3748 i40e_get_cap(struct i40e_hw *hw)
3750 struct i40e_aqc_list_capabilities_element_resp *buf;
3751 uint16_t len, size = 0;
3754 /* Calculate a huge enough buff for saving response data temporarily */
3755 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3756 I40E_MAX_CAP_ELE_NUM;
3757 buf = rte_zmalloc("i40e", len, 0);
3759 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3760 return I40E_ERR_NO_MEMORY;
3763 /* Get, parse the capabilities and save it to hw */
3764 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3765 i40e_aqc_opc_list_func_capabilities, NULL);
3766 if (ret != I40E_SUCCESS)
3767 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3769 /* Free the temporary buffer after being used */
3776 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3778 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3780 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3781 uint16_t qp_count = 0, vsi_count = 0;
3783 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3784 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3787 /* Add the parameter init for LFC */
3788 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3789 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3790 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3792 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3793 pf->max_num_vsi = hw->func_caps.num_vsis;
3794 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3795 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3796 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3798 /* FDir queue/VSI allocation */
3799 pf->fdir_qp_offset = 0;
3800 if (hw->func_caps.fd) {
3801 pf->flags |= I40E_FLAG_FDIR;
3802 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3804 pf->fdir_nb_qps = 0;
3806 qp_count += pf->fdir_nb_qps;
3809 /* LAN queue/VSI allocation */
3810 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3811 if (!hw->func_caps.rss) {
3814 pf->flags |= I40E_FLAG_RSS;
3815 if (hw->mac.type == I40E_MAC_X722)
3816 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3817 pf->lan_nb_qps = pf->lan_nb_qp_max;
3819 qp_count += pf->lan_nb_qps;
3822 /* VF queue/VSI allocation */
3823 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3824 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3825 pf->flags |= I40E_FLAG_SRIOV;
3826 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3827 pf->vf_num = pci_dev->max_vfs;
3829 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3830 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3835 qp_count += pf->vf_nb_qps * pf->vf_num;
3836 vsi_count += pf->vf_num;
3838 /* VMDq queue/VSI allocation */
3839 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3840 pf->vmdq_nb_qps = 0;
3841 pf->max_nb_vmdq_vsi = 0;
3842 if (hw->func_caps.vmdq) {
3843 if (qp_count < hw->func_caps.num_tx_qp &&
3844 vsi_count < hw->func_caps.num_vsis) {
3845 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3846 qp_count) / pf->vmdq_nb_qp_max;
3848 /* Limit the maximum number of VMDq vsi to the maximum
3849 * ethdev can support
3851 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3852 hw->func_caps.num_vsis - vsi_count);
3853 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3855 if (pf->max_nb_vmdq_vsi) {
3856 pf->flags |= I40E_FLAG_VMDQ;
3857 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3859 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3860 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3861 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3864 "No enough queues left for VMDq");
3867 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3870 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3871 vsi_count += pf->max_nb_vmdq_vsi;
3873 if (hw->func_caps.dcb)
3874 pf->flags |= I40E_FLAG_DCB;
3876 if (qp_count > hw->func_caps.num_tx_qp) {
3878 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3879 qp_count, hw->func_caps.num_tx_qp);
3882 if (vsi_count > hw->func_caps.num_vsis) {
3884 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3885 vsi_count, hw->func_caps.num_vsis);
3893 i40e_pf_get_switch_config(struct i40e_pf *pf)
3895 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3896 struct i40e_aqc_get_switch_config_resp *switch_config;
3897 struct i40e_aqc_switch_config_element_resp *element;
3898 uint16_t start_seid = 0, num_reported;
3901 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3902 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3903 if (!switch_config) {
3904 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3908 /* Get the switch configurations */
3909 ret = i40e_aq_get_switch_config(hw, switch_config,
3910 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3911 if (ret != I40E_SUCCESS) {
3912 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3915 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3916 if (num_reported != 1) { /* The number should be 1 */
3917 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3921 /* Parse the switch configuration elements */
3922 element = &(switch_config->element[0]);
3923 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3924 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3925 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3927 PMD_DRV_LOG(INFO, "Unknown element type");
3930 rte_free(switch_config);
3936 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3939 struct pool_entry *entry;
3941 if (pool == NULL || num == 0)
3944 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3945 if (entry == NULL) {
3946 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3950 /* queue heap initialize */
3951 pool->num_free = num;
3952 pool->num_alloc = 0;
3954 LIST_INIT(&pool->alloc_list);
3955 LIST_INIT(&pool->free_list);
3957 /* Initialize element */
3961 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3966 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3968 struct pool_entry *entry, *next_entry;
3973 for (entry = LIST_FIRST(&pool->alloc_list);
3974 entry && (next_entry = LIST_NEXT(entry, next), 1);
3975 entry = next_entry) {
3976 LIST_REMOVE(entry, next);
3980 for (entry = LIST_FIRST(&pool->free_list);
3981 entry && (next_entry = LIST_NEXT(entry, next), 1);
3982 entry = next_entry) {
3983 LIST_REMOVE(entry, next);
3988 pool->num_alloc = 0;
3990 LIST_INIT(&pool->alloc_list);
3991 LIST_INIT(&pool->free_list);
3995 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3998 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3999 uint32_t pool_offset;
4003 PMD_DRV_LOG(ERR, "Invalid parameter");
4007 pool_offset = base - pool->base;
4008 /* Lookup in alloc list */
4009 LIST_FOREACH(entry, &pool->alloc_list, next) {
4010 if (entry->base == pool_offset) {
4011 valid_entry = entry;
4012 LIST_REMOVE(entry, next);
4017 /* Not find, return */
4018 if (valid_entry == NULL) {
4019 PMD_DRV_LOG(ERR, "Failed to find entry");
4024 * Found it, move it to free list and try to merge.
4025 * In order to make merge easier, always sort it by qbase.
4026 * Find adjacent prev and last entries.
4029 LIST_FOREACH(entry, &pool->free_list, next) {
4030 if (entry->base > valid_entry->base) {
4038 /* Try to merge with next one*/
4040 /* Merge with next one */
4041 if (valid_entry->base + valid_entry->len == next->base) {
4042 next->base = valid_entry->base;
4043 next->len += valid_entry->len;
4044 rte_free(valid_entry);
4051 /* Merge with previous one */
4052 if (prev->base + prev->len == valid_entry->base) {
4053 prev->len += valid_entry->len;
4054 /* If it merge with next one, remove next node */
4056 LIST_REMOVE(valid_entry, next);
4057 rte_free(valid_entry);
4059 rte_free(valid_entry);
4065 /* Not find any entry to merge, insert */
4068 LIST_INSERT_AFTER(prev, valid_entry, next);
4069 else if (next != NULL)
4070 LIST_INSERT_BEFORE(next, valid_entry, next);
4071 else /* It's empty list, insert to head */
4072 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4075 pool->num_free += valid_entry->len;
4076 pool->num_alloc -= valid_entry->len;
4082 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4085 struct pool_entry *entry, *valid_entry;
4087 if (pool == NULL || num == 0) {
4088 PMD_DRV_LOG(ERR, "Invalid parameter");
4092 if (pool->num_free < num) {
4093 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4094 num, pool->num_free);
4099 /* Lookup in free list and find most fit one */
4100 LIST_FOREACH(entry, &pool->free_list, next) {
4101 if (entry->len >= num) {
4103 if (entry->len == num) {
4104 valid_entry = entry;
4107 if (valid_entry == NULL || valid_entry->len > entry->len)
4108 valid_entry = entry;
4112 /* Not find one to satisfy the request, return */
4113 if (valid_entry == NULL) {
4114 PMD_DRV_LOG(ERR, "No valid entry found");
4118 * The entry have equal queue number as requested,
4119 * remove it from alloc_list.
4121 if (valid_entry->len == num) {
4122 LIST_REMOVE(valid_entry, next);
4125 * The entry have more numbers than requested,
4126 * create a new entry for alloc_list and minus its
4127 * queue base and number in free_list.
4129 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4130 if (entry == NULL) {
4132 "Failed to allocate memory for resource pool");
4135 entry->base = valid_entry->base;
4137 valid_entry->base += num;
4138 valid_entry->len -= num;
4139 valid_entry = entry;
4142 /* Insert it into alloc list, not sorted */
4143 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4145 pool->num_free -= valid_entry->len;
4146 pool->num_alloc += valid_entry->len;
4148 return valid_entry->base + pool->base;
4152 * bitmap_is_subset - Check whether src2 is subset of src1
4155 bitmap_is_subset(uint8_t src1, uint8_t src2)
4157 return !((src1 ^ src2) & src2);
4160 static enum i40e_status_code
4161 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4163 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4165 /* If DCB is not supported, only default TC is supported */
4166 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4167 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4168 return I40E_NOT_SUPPORTED;
4171 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4173 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4174 hw->func_caps.enabled_tcmap, enabled_tcmap);
4175 return I40E_NOT_SUPPORTED;
4177 return I40E_SUCCESS;
4181 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4182 struct i40e_vsi_vlan_pvid_info *info)
4185 struct i40e_vsi_context ctxt;
4186 uint8_t vlan_flags = 0;
4189 if (vsi == NULL || info == NULL) {
4190 PMD_DRV_LOG(ERR, "invalid parameters");
4191 return I40E_ERR_PARAM;
4195 vsi->info.pvid = info->config.pvid;
4197 * If insert pvid is enabled, only tagged pkts are
4198 * allowed to be sent out.
4200 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4201 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4204 if (info->config.reject.tagged == 0)
4205 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4207 if (info->config.reject.untagged == 0)
4208 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4210 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4211 I40E_AQ_VSI_PVLAN_MODE_MASK);
4212 vsi->info.port_vlan_flags |= vlan_flags;
4213 vsi->info.valid_sections =
4214 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4215 memset(&ctxt, 0, sizeof(ctxt));
4216 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4217 ctxt.seid = vsi->seid;
4219 hw = I40E_VSI_TO_HW(vsi);
4220 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4221 if (ret != I40E_SUCCESS)
4222 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4228 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4230 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4232 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4234 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4235 if (ret != I40E_SUCCESS)
4239 PMD_DRV_LOG(ERR, "seid not valid");
4243 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4244 tc_bw_data.tc_valid_bits = enabled_tcmap;
4245 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4246 tc_bw_data.tc_bw_credits[i] =
4247 (enabled_tcmap & (1 << i)) ? 1 : 0;
4249 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4250 if (ret != I40E_SUCCESS) {
4251 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4255 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4256 sizeof(vsi->info.qs_handle));
4257 return I40E_SUCCESS;
4260 static enum i40e_status_code
4261 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4262 struct i40e_aqc_vsi_properties_data *info,
4263 uint8_t enabled_tcmap)
4265 enum i40e_status_code ret;
4266 int i, total_tc = 0;
4267 uint16_t qpnum_per_tc, bsf, qp_idx;
4269 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4270 if (ret != I40E_SUCCESS)
4273 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4274 if (enabled_tcmap & (1 << i))
4276 vsi->enabled_tc = enabled_tcmap;
4278 /* Number of queues per enabled TC */
4279 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4280 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4281 bsf = rte_bsf32(qpnum_per_tc);
4283 /* Adjust the queue number to actual queues that can be applied */
4284 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4285 vsi->nb_qps = qpnum_per_tc * total_tc;
4288 * Configure TC and queue mapping parameters, for enabled TC,
4289 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4290 * default queue will serve it.
4293 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4294 if (vsi->enabled_tc & (1 << i)) {
4295 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4296 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4297 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4298 qp_idx += qpnum_per_tc;
4300 info->tc_mapping[i] = 0;
4303 /* Associate queue number with VSI */
4304 if (vsi->type == I40E_VSI_SRIOV) {
4305 info->mapping_flags |=
4306 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4307 for (i = 0; i < vsi->nb_qps; i++)
4308 info->queue_mapping[i] =
4309 rte_cpu_to_le_16(vsi->base_queue + i);
4311 info->mapping_flags |=
4312 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4313 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4315 info->valid_sections |=
4316 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4318 return I40E_SUCCESS;
4322 i40e_veb_release(struct i40e_veb *veb)
4324 struct i40e_vsi *vsi;
4330 if (!TAILQ_EMPTY(&veb->head)) {
4331 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4334 /* associate_vsi field is NULL for floating VEB */
4335 if (veb->associate_vsi != NULL) {
4336 vsi = veb->associate_vsi;
4337 hw = I40E_VSI_TO_HW(vsi);
4339 vsi->uplink_seid = veb->uplink_seid;
4342 veb->associate_pf->main_vsi->floating_veb = NULL;
4343 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4346 i40e_aq_delete_element(hw, veb->seid, NULL);
4348 return I40E_SUCCESS;
4352 static struct i40e_veb *
4353 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4355 struct i40e_veb *veb;
4361 "veb setup failed, associated PF shouldn't null");
4364 hw = I40E_PF_TO_HW(pf);
4366 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4368 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4372 veb->associate_vsi = vsi;
4373 veb->associate_pf = pf;
4374 TAILQ_INIT(&veb->head);
4375 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4377 /* create floating veb if vsi is NULL */
4379 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4380 I40E_DEFAULT_TCMAP, false,
4381 &veb->seid, false, NULL);
4383 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4384 true, &veb->seid, false, NULL);
4387 if (ret != I40E_SUCCESS) {
4388 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4389 hw->aq.asq_last_status);
4392 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4394 /* get statistics index */
4395 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4396 &veb->stats_idx, NULL, NULL, NULL);
4397 if (ret != I40E_SUCCESS) {
4398 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4399 hw->aq.asq_last_status);
4402 /* Get VEB bandwidth, to be implemented */
4403 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4405 vsi->uplink_seid = veb->seid;
4414 i40e_vsi_release(struct i40e_vsi *vsi)
4418 struct i40e_vsi_list *vsi_list;
4421 struct i40e_mac_filter *f;
4422 uint16_t user_param;
4425 return I40E_SUCCESS;
4430 user_param = vsi->user_param;
4432 pf = I40E_VSI_TO_PF(vsi);
4433 hw = I40E_VSI_TO_HW(vsi);
4435 /* VSI has child to attach, release child first */
4437 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4438 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4441 i40e_veb_release(vsi->veb);
4444 if (vsi->floating_veb) {
4445 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4446 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4451 /* Remove all macvlan filters of the VSI */
4452 i40e_vsi_remove_all_macvlan_filter(vsi);
4453 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4456 if (vsi->type != I40E_VSI_MAIN &&
4457 ((vsi->type != I40E_VSI_SRIOV) ||
4458 !pf->floating_veb_list[user_param])) {
4459 /* Remove vsi from parent's sibling list */
4460 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4461 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4462 return I40E_ERR_PARAM;
4464 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4465 &vsi->sib_vsi_list, list);
4467 /* Remove all switch element of the VSI */
4468 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4469 if (ret != I40E_SUCCESS)
4470 PMD_DRV_LOG(ERR, "Failed to delete element");
4473 if ((vsi->type == I40E_VSI_SRIOV) &&
4474 pf->floating_veb_list[user_param]) {
4475 /* Remove vsi from parent's sibling list */
4476 if (vsi->parent_vsi == NULL ||
4477 vsi->parent_vsi->floating_veb == NULL) {
4478 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4479 return I40E_ERR_PARAM;
4481 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4482 &vsi->sib_vsi_list, list);
4484 /* Remove all switch element of the VSI */
4485 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4486 if (ret != I40E_SUCCESS)
4487 PMD_DRV_LOG(ERR, "Failed to delete element");
4490 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4492 if (vsi->type != I40E_VSI_SRIOV)
4493 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4496 return I40E_SUCCESS;
4500 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4502 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4503 struct i40e_aqc_remove_macvlan_element_data def_filter;
4504 struct i40e_mac_filter_info filter;
4507 if (vsi->type != I40E_VSI_MAIN)
4508 return I40E_ERR_CONFIG;
4509 memset(&def_filter, 0, sizeof(def_filter));
4510 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4512 def_filter.vlan_tag = 0;
4513 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4514 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4515 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4516 if (ret != I40E_SUCCESS) {
4517 struct i40e_mac_filter *f;
4518 struct ether_addr *mac;
4520 PMD_DRV_LOG(WARNING,
4521 "Cannot remove the default macvlan filter");
4522 /* It needs to add the permanent mac into mac list */
4523 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4525 PMD_DRV_LOG(ERR, "failed to allocate memory");
4526 return I40E_ERR_NO_MEMORY;
4528 mac = &f->mac_info.mac_addr;
4529 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4531 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4532 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4537 (void)rte_memcpy(&filter.mac_addr,
4538 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4539 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4540 return i40e_vsi_add_mac(vsi, &filter);
4544 * i40e_vsi_get_bw_config - Query VSI BW Information
4545 * @vsi: the VSI to be queried
4547 * Returns 0 on success, negative value on failure
4549 static enum i40e_status_code
4550 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4552 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4553 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4554 struct i40e_hw *hw = &vsi->adapter->hw;
4559 memset(&bw_config, 0, sizeof(bw_config));
4560 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4561 if (ret != I40E_SUCCESS) {
4562 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4563 hw->aq.asq_last_status);
4567 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4568 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4569 &ets_sla_config, NULL);
4570 if (ret != I40E_SUCCESS) {
4572 "VSI failed to get TC bandwdith configuration %u",
4573 hw->aq.asq_last_status);
4577 /* store and print out BW info */
4578 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4579 vsi->bw_info.bw_max = bw_config.max_bw;
4580 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4581 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4582 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4583 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4585 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4586 vsi->bw_info.bw_ets_share_credits[i] =
4587 ets_sla_config.share_credits[i];
4588 vsi->bw_info.bw_ets_credits[i] =
4589 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4590 /* 4 bits per TC, 4th bit is reserved */
4591 vsi->bw_info.bw_ets_max[i] =
4592 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4593 RTE_LEN2MASK(3, uint8_t));
4594 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4595 vsi->bw_info.bw_ets_share_credits[i]);
4596 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4597 vsi->bw_info.bw_ets_credits[i]);
4598 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4599 vsi->bw_info.bw_ets_max[i]);
4602 return I40E_SUCCESS;
4605 /* i40e_enable_pf_lb
4606 * @pf: pointer to the pf structure
4608 * allow loopback on pf
4611 i40e_enable_pf_lb(struct i40e_pf *pf)
4613 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4614 struct i40e_vsi_context ctxt;
4617 /* Use the FW API if FW >= v5.0 */
4618 if (hw->aq.fw_maj_ver < 5) {
4619 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4623 memset(&ctxt, 0, sizeof(ctxt));
4624 ctxt.seid = pf->main_vsi_seid;
4625 ctxt.pf_num = hw->pf_id;
4626 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4628 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4629 ret, hw->aq.asq_last_status);
4632 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4633 ctxt.info.valid_sections =
4634 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4635 ctxt.info.switch_id |=
4636 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4638 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4640 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4641 hw->aq.asq_last_status);
4646 i40e_vsi_setup(struct i40e_pf *pf,
4647 enum i40e_vsi_type type,
4648 struct i40e_vsi *uplink_vsi,
4649 uint16_t user_param)
4651 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4652 struct i40e_vsi *vsi;
4653 struct i40e_mac_filter_info filter;
4655 struct i40e_vsi_context ctxt;
4656 struct ether_addr broadcast =
4657 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4659 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4660 uplink_vsi == NULL) {
4662 "VSI setup failed, VSI link shouldn't be NULL");
4666 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4668 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4673 * 1.type is not MAIN and uplink vsi is not NULL
4674 * If uplink vsi didn't setup VEB, create one first under veb field
4675 * 2.type is SRIOV and the uplink is NULL
4676 * If floating VEB is NULL, create one veb under floating veb field
4679 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4680 uplink_vsi->veb == NULL) {
4681 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4683 if (uplink_vsi->veb == NULL) {
4684 PMD_DRV_LOG(ERR, "VEB setup failed");
4687 /* set ALLOWLOOPBACk on pf, when veb is created */
4688 i40e_enable_pf_lb(pf);
4691 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4692 pf->main_vsi->floating_veb == NULL) {
4693 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4695 if (pf->main_vsi->floating_veb == NULL) {
4696 PMD_DRV_LOG(ERR, "VEB setup failed");
4701 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4703 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4706 TAILQ_INIT(&vsi->mac_list);
4708 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4709 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4710 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4711 vsi->user_param = user_param;
4712 vsi->vlan_anti_spoof_on = 0;
4713 vsi->vlan_filter_on = 0;
4714 /* Allocate queues */
4715 switch (vsi->type) {
4716 case I40E_VSI_MAIN :
4717 vsi->nb_qps = pf->lan_nb_qps;
4719 case I40E_VSI_SRIOV :
4720 vsi->nb_qps = pf->vf_nb_qps;
4722 case I40E_VSI_VMDQ2:
4723 vsi->nb_qps = pf->vmdq_nb_qps;
4726 vsi->nb_qps = pf->fdir_nb_qps;
4732 * The filter status descriptor is reported in rx queue 0,
4733 * while the tx queue for fdir filter programming has no
4734 * such constraints, can be non-zero queues.
4735 * To simplify it, choose FDIR vsi use queue 0 pair.
4736 * To make sure it will use queue 0 pair, queue allocation
4737 * need be done before this function is called
4739 if (type != I40E_VSI_FDIR) {
4740 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4742 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4746 vsi->base_queue = ret;
4748 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4750 /* VF has MSIX interrupt in VF range, don't allocate here */
4751 if (type == I40E_VSI_MAIN) {
4752 ret = i40e_res_pool_alloc(&pf->msix_pool,
4753 RTE_MIN(vsi->nb_qps,
4754 RTE_MAX_RXTX_INTR_VEC_ID));
4756 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4758 goto fail_queue_alloc;
4760 vsi->msix_intr = ret;
4761 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4762 } else if (type != I40E_VSI_SRIOV) {
4763 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4765 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4766 goto fail_queue_alloc;
4768 vsi->msix_intr = ret;
4776 if (type == I40E_VSI_MAIN) {
4777 /* For main VSI, no need to add since it's default one */
4778 vsi->uplink_seid = pf->mac_seid;
4779 vsi->seid = pf->main_vsi_seid;
4780 /* Bind queues with specific MSIX interrupt */
4782 * Needs 2 interrupt at least, one for misc cause which will
4783 * enabled from OS side, Another for queues binding the
4784 * interrupt from device side only.
4787 /* Get default VSI parameters from hardware */
4788 memset(&ctxt, 0, sizeof(ctxt));
4789 ctxt.seid = vsi->seid;
4790 ctxt.pf_num = hw->pf_id;
4791 ctxt.uplink_seid = vsi->uplink_seid;
4793 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4794 if (ret != I40E_SUCCESS) {
4795 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4796 goto fail_msix_alloc;
4798 (void)rte_memcpy(&vsi->info, &ctxt.info,
4799 sizeof(struct i40e_aqc_vsi_properties_data));
4800 vsi->vsi_id = ctxt.vsi_number;
4801 vsi->info.valid_sections = 0;
4803 /* Configure tc, enabled TC0 only */
4804 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4806 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4807 goto fail_msix_alloc;
4810 /* TC, queue mapping */
4811 memset(&ctxt, 0, sizeof(ctxt));
4812 vsi->info.valid_sections |=
4813 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4814 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4815 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4816 (void)rte_memcpy(&ctxt.info, &vsi->info,
4817 sizeof(struct i40e_aqc_vsi_properties_data));
4818 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4819 I40E_DEFAULT_TCMAP);
4820 if (ret != I40E_SUCCESS) {
4822 "Failed to configure TC queue mapping");
4823 goto fail_msix_alloc;
4825 ctxt.seid = vsi->seid;
4826 ctxt.pf_num = hw->pf_id;
4827 ctxt.uplink_seid = vsi->uplink_seid;
4830 /* Update VSI parameters */
4831 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4832 if (ret != I40E_SUCCESS) {
4833 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4834 goto fail_msix_alloc;
4837 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4838 sizeof(vsi->info.tc_mapping));
4839 (void)rte_memcpy(&vsi->info.queue_mapping,
4840 &ctxt.info.queue_mapping,
4841 sizeof(vsi->info.queue_mapping));
4842 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4843 vsi->info.valid_sections = 0;
4845 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4849 * Updating default filter settings are necessary to prevent
4850 * reception of tagged packets.
4851 * Some old firmware configurations load a default macvlan
4852 * filter which accepts both tagged and untagged packets.
4853 * The updating is to use a normal filter instead if needed.
4854 * For NVM 4.2.2 or after, the updating is not needed anymore.
4855 * The firmware with correct configurations load the default
4856 * macvlan filter which is expected and cannot be removed.
4858 i40e_update_default_filter_setting(vsi);
4859 i40e_config_qinq(hw, vsi);
4860 } else if (type == I40E_VSI_SRIOV) {
4861 memset(&ctxt, 0, sizeof(ctxt));
4863 * For other VSI, the uplink_seid equals to uplink VSI's
4864 * uplink_seid since they share same VEB
4866 if (uplink_vsi == NULL)
4867 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4869 vsi->uplink_seid = uplink_vsi->uplink_seid;
4870 ctxt.pf_num = hw->pf_id;
4871 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4872 ctxt.uplink_seid = vsi->uplink_seid;
4873 ctxt.connection_type = 0x1;
4874 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4876 /* Use the VEB configuration if FW >= v5.0 */
4877 if (hw->aq.fw_maj_ver >= 5) {
4878 /* Configure switch ID */
4879 ctxt.info.valid_sections |=
4880 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4881 ctxt.info.switch_id =
4882 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4885 /* Configure port/vlan */
4886 ctxt.info.valid_sections |=
4887 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4888 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4889 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4890 hw->func_caps.enabled_tcmap);
4891 if (ret != I40E_SUCCESS) {
4893 "Failed to configure TC queue mapping");
4894 goto fail_msix_alloc;
4897 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4898 ctxt.info.valid_sections |=
4899 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4901 * Since VSI is not created yet, only configure parameter,
4902 * will add vsi below.
4905 i40e_config_qinq(hw, vsi);
4906 } else if (type == I40E_VSI_VMDQ2) {
4907 memset(&ctxt, 0, sizeof(ctxt));
4909 * For other VSI, the uplink_seid equals to uplink VSI's
4910 * uplink_seid since they share same VEB
4912 vsi->uplink_seid = uplink_vsi->uplink_seid;
4913 ctxt.pf_num = hw->pf_id;
4915 ctxt.uplink_seid = vsi->uplink_seid;
4916 ctxt.connection_type = 0x1;
4917 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4919 ctxt.info.valid_sections |=
4920 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4921 /* user_param carries flag to enable loop back */
4923 ctxt.info.switch_id =
4924 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4925 ctxt.info.switch_id |=
4926 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4929 /* Configure port/vlan */
4930 ctxt.info.valid_sections |=
4931 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4932 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4933 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4934 I40E_DEFAULT_TCMAP);
4935 if (ret != I40E_SUCCESS) {
4937 "Failed to configure TC queue mapping");
4938 goto fail_msix_alloc;
4940 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4941 ctxt.info.valid_sections |=
4942 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4943 } else if (type == I40E_VSI_FDIR) {
4944 memset(&ctxt, 0, sizeof(ctxt));
4945 vsi->uplink_seid = uplink_vsi->uplink_seid;
4946 ctxt.pf_num = hw->pf_id;
4948 ctxt.uplink_seid = vsi->uplink_seid;
4949 ctxt.connection_type = 0x1; /* regular data port */
4950 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4951 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4952 I40E_DEFAULT_TCMAP);
4953 if (ret != I40E_SUCCESS) {
4955 "Failed to configure TC queue mapping.");
4956 goto fail_msix_alloc;
4958 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4959 ctxt.info.valid_sections |=
4960 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4962 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4963 goto fail_msix_alloc;
4966 if (vsi->type != I40E_VSI_MAIN) {
4967 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4968 if (ret != I40E_SUCCESS) {
4969 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4970 hw->aq.asq_last_status);
4971 goto fail_msix_alloc;
4973 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4974 vsi->info.valid_sections = 0;
4975 vsi->seid = ctxt.seid;
4976 vsi->vsi_id = ctxt.vsi_number;
4977 vsi->sib_vsi_list.vsi = vsi;
4978 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4979 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4980 &vsi->sib_vsi_list, list);
4982 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4983 &vsi->sib_vsi_list, list);
4987 /* MAC/VLAN configuration */
4988 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4989 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4991 ret = i40e_vsi_add_mac(vsi, &filter);
4992 if (ret != I40E_SUCCESS) {
4993 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4994 goto fail_msix_alloc;
4997 /* Get VSI BW information */
4998 i40e_vsi_get_bw_config(vsi);
5001 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5003 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5009 /* Configure vlan filter on or off */
5011 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5014 struct i40e_mac_filter *f;
5016 struct i40e_mac_filter_info *mac_filter;
5017 enum rte_mac_filter_type desired_filter;
5018 int ret = I40E_SUCCESS;
5021 /* Filter to match MAC and VLAN */
5022 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5024 /* Filter to match only MAC */
5025 desired_filter = RTE_MAC_PERFECT_MATCH;
5030 mac_filter = rte_zmalloc("mac_filter_info_data",
5031 num * sizeof(*mac_filter), 0);
5032 if (mac_filter == NULL) {
5033 PMD_DRV_LOG(ERR, "failed to allocate memory");
5034 return I40E_ERR_NO_MEMORY;
5039 /* Remove all existing mac */
5040 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5041 mac_filter[i] = f->mac_info;
5042 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5044 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5045 on ? "enable" : "disable");
5051 /* Override with new filter */
5052 for (i = 0; i < num; i++) {
5053 mac_filter[i].filter_type = desired_filter;
5054 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5056 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5057 on ? "enable" : "disable");
5063 rte_free(mac_filter);
5067 /* Configure vlan stripping on or off */
5069 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5071 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5072 struct i40e_vsi_context ctxt;
5074 int ret = I40E_SUCCESS;
5076 /* Check if it has been already on or off */
5077 if (vsi->info.valid_sections &
5078 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5080 if ((vsi->info.port_vlan_flags &
5081 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5082 return 0; /* already on */
5084 if ((vsi->info.port_vlan_flags &
5085 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5086 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5087 return 0; /* already off */
5092 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5094 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5095 vsi->info.valid_sections =
5096 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5097 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5098 vsi->info.port_vlan_flags |= vlan_flags;
5099 ctxt.seid = vsi->seid;
5100 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5101 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5103 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5104 on ? "enable" : "disable");
5110 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5112 struct rte_eth_dev_data *data = dev->data;
5116 /* Apply vlan offload setting */
5117 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5118 i40e_vlan_offload_set(dev, mask);
5120 /* Apply double-vlan setting, not implemented yet */
5122 /* Apply pvid setting */
5123 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5124 data->dev_conf.txmode.hw_vlan_insert_pvid);
5126 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5132 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5134 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5136 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5140 i40e_update_flow_control(struct i40e_hw *hw)
5142 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5143 struct i40e_link_status link_status;
5144 uint32_t rxfc = 0, txfc = 0, reg;
5148 memset(&link_status, 0, sizeof(link_status));
5149 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5150 if (ret != I40E_SUCCESS) {
5151 PMD_DRV_LOG(ERR, "Failed to get link status information");
5152 goto write_reg; /* Disable flow control */
5155 an_info = hw->phy.link_info.an_info;
5156 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5157 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5158 ret = I40E_ERR_NOT_READY;
5159 goto write_reg; /* Disable flow control */
5162 * If link auto negotiation is enabled, flow control needs to
5163 * be configured according to it
5165 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5166 case I40E_LINK_PAUSE_RXTX:
5169 hw->fc.current_mode = I40E_FC_FULL;
5171 case I40E_AQ_LINK_PAUSE_RX:
5173 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5175 case I40E_AQ_LINK_PAUSE_TX:
5177 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5180 hw->fc.current_mode = I40E_FC_NONE;
5185 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5186 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5187 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5188 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5189 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5190 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5197 i40e_pf_setup(struct i40e_pf *pf)
5199 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5200 struct i40e_filter_control_settings settings;
5201 struct i40e_vsi *vsi;
5204 /* Clear all stats counters */
5205 pf->offset_loaded = FALSE;
5206 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5207 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5209 ret = i40e_pf_get_switch_config(pf);
5210 if (ret != I40E_SUCCESS) {
5211 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5214 if (pf->flags & I40E_FLAG_FDIR) {
5215 /* make queue allocated first, let FDIR use queue pair 0*/
5216 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5217 if (ret != I40E_FDIR_QUEUE_ID) {
5219 "queue allocation fails for FDIR: ret =%d",
5221 pf->flags &= ~I40E_FLAG_FDIR;
5224 /* main VSI setup */
5225 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5227 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5228 return I40E_ERR_NOT_READY;
5232 /* Configure filter control */
5233 memset(&settings, 0, sizeof(settings));
5234 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5235 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5236 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5237 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5239 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5240 hw->func_caps.rss_table_size);
5241 return I40E_ERR_PARAM;
5243 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5244 hw->func_caps.rss_table_size);
5245 pf->hash_lut_size = hw->func_caps.rss_table_size;
5247 /* Enable ethtype and macvlan filters */
5248 settings.enable_ethtype = TRUE;
5249 settings.enable_macvlan = TRUE;
5250 ret = i40e_set_filter_control(hw, &settings);
5252 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5255 /* Update flow control according to the auto negotiation */
5256 i40e_update_flow_control(hw);
5258 return I40E_SUCCESS;
5262 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5268 * Set or clear TX Queue Disable flags,
5269 * which is required by hardware.
5271 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5272 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5274 /* Wait until the request is finished */
5275 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5276 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5277 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5278 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5279 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5285 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5286 return I40E_SUCCESS; /* already on, skip next steps */
5288 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5289 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5291 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5292 return I40E_SUCCESS; /* already off, skip next steps */
5293 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5295 /* Write the register */
5296 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5297 /* Check the result */
5298 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5299 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5300 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5302 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5303 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5306 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5307 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5311 /* Check if it is timeout */
5312 if (j >= I40E_CHK_Q_ENA_COUNT) {
5313 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5314 (on ? "enable" : "disable"), q_idx);
5315 return I40E_ERR_TIMEOUT;
5318 return I40E_SUCCESS;
5321 /* Swith on or off the tx queues */
5323 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5325 struct rte_eth_dev_data *dev_data = pf->dev_data;
5326 struct i40e_tx_queue *txq;
5327 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5331 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5332 txq = dev_data->tx_queues[i];
5333 /* Don't operate the queue if not configured or
5334 * if starting only per queue */
5335 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5338 ret = i40e_dev_tx_queue_start(dev, i);
5340 ret = i40e_dev_tx_queue_stop(dev, i);
5341 if ( ret != I40E_SUCCESS)
5345 return I40E_SUCCESS;
5349 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5354 /* Wait until the request is finished */
5355 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5356 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5357 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5358 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5359 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5364 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5365 return I40E_SUCCESS; /* Already on, skip next steps */
5366 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5368 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5369 return I40E_SUCCESS; /* Already off, skip next steps */
5370 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5373 /* Write the register */
5374 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5375 /* Check the result */
5376 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5377 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5378 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5380 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5381 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5384 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5385 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5390 /* Check if it is timeout */
5391 if (j >= I40E_CHK_Q_ENA_COUNT) {
5392 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5393 (on ? "enable" : "disable"), q_idx);
5394 return I40E_ERR_TIMEOUT;
5397 return I40E_SUCCESS;
5399 /* Switch on or off the rx queues */
5401 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5403 struct rte_eth_dev_data *dev_data = pf->dev_data;
5404 struct i40e_rx_queue *rxq;
5405 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5409 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5410 rxq = dev_data->rx_queues[i];
5411 /* Don't operate the queue if not configured or
5412 * if starting only per queue */
5413 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5416 ret = i40e_dev_rx_queue_start(dev, i);
5418 ret = i40e_dev_rx_queue_stop(dev, i);
5419 if (ret != I40E_SUCCESS)
5423 return I40E_SUCCESS;
5426 /* Switch on or off all the rx/tx queues */
5428 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5433 /* enable rx queues before enabling tx queues */
5434 ret = i40e_dev_switch_rx_queues(pf, on);
5436 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5439 ret = i40e_dev_switch_tx_queues(pf, on);
5441 /* Stop tx queues before stopping rx queues */
5442 ret = i40e_dev_switch_tx_queues(pf, on);
5444 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5447 ret = i40e_dev_switch_rx_queues(pf, on);
5453 /* Initialize VSI for TX */
5455 i40e_dev_tx_init(struct i40e_pf *pf)
5457 struct rte_eth_dev_data *data = pf->dev_data;
5459 uint32_t ret = I40E_SUCCESS;
5460 struct i40e_tx_queue *txq;
5462 for (i = 0; i < data->nb_tx_queues; i++) {
5463 txq = data->tx_queues[i];
5464 if (!txq || !txq->q_set)
5466 ret = i40e_tx_queue_init(txq);
5467 if (ret != I40E_SUCCESS)
5470 if (ret == I40E_SUCCESS)
5471 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5477 /* Initialize VSI for RX */
5479 i40e_dev_rx_init(struct i40e_pf *pf)
5481 struct rte_eth_dev_data *data = pf->dev_data;
5482 int ret = I40E_SUCCESS;
5484 struct i40e_rx_queue *rxq;
5486 i40e_pf_config_mq_rx(pf);
5487 for (i = 0; i < data->nb_rx_queues; i++) {
5488 rxq = data->rx_queues[i];
5489 if (!rxq || !rxq->q_set)
5492 ret = i40e_rx_queue_init(rxq);
5493 if (ret != I40E_SUCCESS) {
5495 "Failed to do RX queue initialization");
5499 if (ret == I40E_SUCCESS)
5500 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5507 i40e_dev_rxtx_init(struct i40e_pf *pf)
5511 err = i40e_dev_tx_init(pf);
5513 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5516 err = i40e_dev_rx_init(pf);
5518 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5526 i40e_vmdq_setup(struct rte_eth_dev *dev)
5528 struct rte_eth_conf *conf = &dev->data->dev_conf;
5529 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5530 int i, err, conf_vsis, j, loop;
5531 struct i40e_vsi *vsi;
5532 struct i40e_vmdq_info *vmdq_info;
5533 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5534 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5537 * Disable interrupt to avoid message from VF. Furthermore, it will
5538 * avoid race condition in VSI creation/destroy.
5540 i40e_pf_disable_irq0(hw);
5542 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5543 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5547 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5548 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5549 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5550 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5551 pf->max_nb_vmdq_vsi);
5555 if (pf->vmdq != NULL) {
5556 PMD_INIT_LOG(INFO, "VMDQ already configured");
5560 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5561 sizeof(*vmdq_info) * conf_vsis, 0);
5563 if (pf->vmdq == NULL) {
5564 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5568 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5570 /* Create VMDQ VSI */
5571 for (i = 0; i < conf_vsis; i++) {
5572 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5573 vmdq_conf->enable_loop_back);
5575 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5579 vmdq_info = &pf->vmdq[i];
5581 vmdq_info->vsi = vsi;
5583 pf->nb_cfg_vmdq_vsi = conf_vsis;
5585 /* Configure Vlan */
5586 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5587 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5588 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5589 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5590 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5591 vmdq_conf->pool_map[i].vlan_id, j);
5593 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5594 vmdq_conf->pool_map[i].vlan_id);
5596 PMD_INIT_LOG(ERR, "Failed to add vlan");
5604 i40e_pf_enable_irq0(hw);
5609 for (i = 0; i < conf_vsis; i++)
5610 if (pf->vmdq[i].vsi == NULL)
5613 i40e_vsi_release(pf->vmdq[i].vsi);
5617 i40e_pf_enable_irq0(hw);
5622 i40e_stat_update_32(struct i40e_hw *hw,
5630 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5634 if (new_data >= *offset)
5635 *stat = (uint64_t)(new_data - *offset);
5637 *stat = (uint64_t)((new_data +
5638 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5642 i40e_stat_update_48(struct i40e_hw *hw,
5651 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5652 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5653 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5658 if (new_data >= *offset)
5659 *stat = new_data - *offset;
5661 *stat = (uint64_t)((new_data +
5662 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5664 *stat &= I40E_48_BIT_MASK;
5669 i40e_pf_disable_irq0(struct i40e_hw *hw)
5671 /* Disable all interrupt types */
5672 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5673 I40E_WRITE_FLUSH(hw);
5678 i40e_pf_enable_irq0(struct i40e_hw *hw)
5680 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5681 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5682 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5683 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5684 I40E_WRITE_FLUSH(hw);
5688 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5690 /* read pending request and disable first */
5691 i40e_pf_disable_irq0(hw);
5692 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5693 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5694 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5697 /* Link no queues with irq0 */
5698 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5699 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5703 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5705 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5706 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5709 uint32_t index, offset, val;
5714 * Try to find which VF trigger a reset, use absolute VF id to access
5715 * since the reg is global register.
5717 for (i = 0; i < pf->vf_num; i++) {
5718 abs_vf_id = hw->func_caps.vf_base_id + i;
5719 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5720 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5721 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5722 /* VFR event occured */
5723 if (val & (0x1 << offset)) {
5726 /* Clear the event first */
5727 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5729 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5731 * Only notify a VF reset event occured,
5732 * don't trigger another SW reset
5734 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5735 if (ret != I40E_SUCCESS)
5736 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5742 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5747 for (i = 0; i < pf->vf_num; i++)
5748 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5752 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5754 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5755 struct i40e_arq_event_info info;
5756 uint16_t pending, opcode;
5759 info.buf_len = I40E_AQ_BUF_SZ;
5760 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5761 if (!info.msg_buf) {
5762 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5768 ret = i40e_clean_arq_element(hw, &info, &pending);
5770 if (ret != I40E_SUCCESS) {
5772 "Failed to read msg from AdminQ, aq_err: %u",
5773 hw->aq.asq_last_status);
5776 opcode = rte_le_to_cpu_16(info.desc.opcode);
5779 case i40e_aqc_opc_send_msg_to_pf:
5780 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5781 i40e_pf_host_handle_vf_msg(dev,
5782 rte_le_to_cpu_16(info.desc.retval),
5783 rte_le_to_cpu_32(info.desc.cookie_high),
5784 rte_le_to_cpu_32(info.desc.cookie_low),
5788 case i40e_aqc_opc_get_link_status:
5789 ret = i40e_dev_link_update(dev, 0);
5791 i40e_notify_all_vfs_link_status(dev);
5792 _rte_eth_dev_callback_process(dev,
5793 RTE_ETH_EVENT_INTR_LSC, NULL);
5797 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5802 rte_free(info.msg_buf);
5806 * Interrupt handler triggered by NIC for handling
5807 * specific interrupt.
5810 * Pointer to interrupt handle.
5812 * The address of parameter (struct rte_eth_dev *) regsitered before.
5818 i40e_dev_interrupt_handler(void *param)
5820 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5824 /* Disable interrupt */
5825 i40e_pf_disable_irq0(hw);
5827 /* read out interrupt causes */
5828 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5830 /* No interrupt event indicated */
5831 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5832 PMD_DRV_LOG(INFO, "No interrupt event");
5835 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5836 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5837 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5838 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5839 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5840 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5841 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5842 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5843 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5844 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5845 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5846 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5847 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5848 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5850 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5851 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5852 i40e_dev_handle_vfr_event(dev);
5854 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5855 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5856 i40e_dev_handle_aq_msg(dev);
5860 /* Enable interrupt */
5861 i40e_pf_enable_irq0(hw);
5862 rte_intr_enable(dev->intr_handle);
5866 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5867 struct i40e_macvlan_filter *filter,
5870 int ele_num, ele_buff_size;
5871 int num, actual_num, i;
5873 int ret = I40E_SUCCESS;
5874 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5875 struct i40e_aqc_add_macvlan_element_data *req_list;
5877 if (filter == NULL || total == 0)
5878 return I40E_ERR_PARAM;
5879 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5880 ele_buff_size = hw->aq.asq_buf_size;
5882 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5883 if (req_list == NULL) {
5884 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5885 return I40E_ERR_NO_MEMORY;
5890 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5891 memset(req_list, 0, ele_buff_size);
5893 for (i = 0; i < actual_num; i++) {
5894 (void)rte_memcpy(req_list[i].mac_addr,
5895 &filter[num + i].macaddr, ETH_ADDR_LEN);
5896 req_list[i].vlan_tag =
5897 rte_cpu_to_le_16(filter[num + i].vlan_id);
5899 switch (filter[num + i].filter_type) {
5900 case RTE_MAC_PERFECT_MATCH:
5901 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5902 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5904 case RTE_MACVLAN_PERFECT_MATCH:
5905 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5907 case RTE_MAC_HASH_MATCH:
5908 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5909 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5911 case RTE_MACVLAN_HASH_MATCH:
5912 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5915 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5916 ret = I40E_ERR_PARAM;
5920 req_list[i].queue_number = 0;
5922 req_list[i].flags = rte_cpu_to_le_16(flags);
5925 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5927 if (ret != I40E_SUCCESS) {
5928 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5932 } while (num < total);
5940 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5941 struct i40e_macvlan_filter *filter,
5944 int ele_num, ele_buff_size;
5945 int num, actual_num, i;
5947 int ret = I40E_SUCCESS;
5948 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5949 struct i40e_aqc_remove_macvlan_element_data *req_list;
5951 if (filter == NULL || total == 0)
5952 return I40E_ERR_PARAM;
5954 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5955 ele_buff_size = hw->aq.asq_buf_size;
5957 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5958 if (req_list == NULL) {
5959 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5960 return I40E_ERR_NO_MEMORY;
5965 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5966 memset(req_list, 0, ele_buff_size);
5968 for (i = 0; i < actual_num; i++) {
5969 (void)rte_memcpy(req_list[i].mac_addr,
5970 &filter[num + i].macaddr, ETH_ADDR_LEN);
5971 req_list[i].vlan_tag =
5972 rte_cpu_to_le_16(filter[num + i].vlan_id);
5974 switch (filter[num + i].filter_type) {
5975 case RTE_MAC_PERFECT_MATCH:
5976 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5977 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5979 case RTE_MACVLAN_PERFECT_MATCH:
5980 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5982 case RTE_MAC_HASH_MATCH:
5983 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5984 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5986 case RTE_MACVLAN_HASH_MATCH:
5987 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5990 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5991 ret = I40E_ERR_PARAM;
5994 req_list[i].flags = rte_cpu_to_le_16(flags);
5997 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5999 if (ret != I40E_SUCCESS) {
6000 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6004 } while (num < total);
6011 /* Find out specific MAC filter */
6012 static struct i40e_mac_filter *
6013 i40e_find_mac_filter(struct i40e_vsi *vsi,
6014 struct ether_addr *macaddr)
6016 struct i40e_mac_filter *f;
6018 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6019 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6027 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6030 uint32_t vid_idx, vid_bit;
6032 if (vlan_id > ETH_VLAN_ID_MAX)
6035 vid_idx = I40E_VFTA_IDX(vlan_id);
6036 vid_bit = I40E_VFTA_BIT(vlan_id);
6038 if (vsi->vfta[vid_idx] & vid_bit)
6045 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6046 uint16_t vlan_id, bool on)
6048 uint32_t vid_idx, vid_bit;
6050 vid_idx = I40E_VFTA_IDX(vlan_id);
6051 vid_bit = I40E_VFTA_BIT(vlan_id);
6054 vsi->vfta[vid_idx] |= vid_bit;
6056 vsi->vfta[vid_idx] &= ~vid_bit;
6060 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6061 uint16_t vlan_id, bool on)
6063 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6064 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6067 if (vlan_id > ETH_VLAN_ID_MAX)
6070 i40e_store_vlan_filter(vsi, vlan_id, on);
6072 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6075 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6078 ret = i40e_aq_add_vlan(hw, vsi->seid,
6079 &vlan_data, 1, NULL);
6080 if (ret != I40E_SUCCESS)
6081 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6083 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6084 &vlan_data, 1, NULL);
6085 if (ret != I40E_SUCCESS)
6087 "Failed to remove vlan filter");
6092 * Find all vlan options for specific mac addr,
6093 * return with actual vlan found.
6096 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6097 struct i40e_macvlan_filter *mv_f,
6098 int num, struct ether_addr *addr)
6104 * Not to use i40e_find_vlan_filter to decrease the loop time,
6105 * although the code looks complex.
6107 if (num < vsi->vlan_num)
6108 return I40E_ERR_PARAM;
6111 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6113 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6114 if (vsi->vfta[j] & (1 << k)) {
6117 "vlan number doesn't match");
6118 return I40E_ERR_PARAM;
6120 (void)rte_memcpy(&mv_f[i].macaddr,
6121 addr, ETH_ADDR_LEN);
6123 j * I40E_UINT32_BIT_SIZE + k;
6129 return I40E_SUCCESS;
6133 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6134 struct i40e_macvlan_filter *mv_f,
6139 struct i40e_mac_filter *f;
6141 if (num < vsi->mac_num)
6142 return I40E_ERR_PARAM;
6144 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6146 PMD_DRV_LOG(ERR, "buffer number not match");
6147 return I40E_ERR_PARAM;
6149 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6151 mv_f[i].vlan_id = vlan;
6152 mv_f[i].filter_type = f->mac_info.filter_type;
6156 return I40E_SUCCESS;
6160 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6163 struct i40e_mac_filter *f;
6164 struct i40e_macvlan_filter *mv_f;
6165 int ret = I40E_SUCCESS;
6167 if (vsi == NULL || vsi->mac_num == 0)
6168 return I40E_ERR_PARAM;
6170 /* Case that no vlan is set */
6171 if (vsi->vlan_num == 0)
6174 num = vsi->mac_num * vsi->vlan_num;
6176 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6178 PMD_DRV_LOG(ERR, "failed to allocate memory");
6179 return I40E_ERR_NO_MEMORY;
6183 if (vsi->vlan_num == 0) {
6184 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6185 (void)rte_memcpy(&mv_f[i].macaddr,
6186 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6187 mv_f[i].filter_type = f->mac_info.filter_type;
6188 mv_f[i].vlan_id = 0;
6192 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6193 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6194 vsi->vlan_num, &f->mac_info.mac_addr);
6195 if (ret != I40E_SUCCESS)
6197 for (j = i; j < i + vsi->vlan_num; j++)
6198 mv_f[j].filter_type = f->mac_info.filter_type;
6203 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6211 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6213 struct i40e_macvlan_filter *mv_f;
6215 int ret = I40E_SUCCESS;
6217 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6218 return I40E_ERR_PARAM;
6220 /* If it's already set, just return */
6221 if (i40e_find_vlan_filter(vsi,vlan))
6222 return I40E_SUCCESS;
6224 mac_num = vsi->mac_num;
6227 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6228 return I40E_ERR_PARAM;
6231 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6234 PMD_DRV_LOG(ERR, "failed to allocate memory");
6235 return I40E_ERR_NO_MEMORY;
6238 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6240 if (ret != I40E_SUCCESS)
6243 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6245 if (ret != I40E_SUCCESS)
6248 i40e_set_vlan_filter(vsi, vlan, 1);
6258 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6260 struct i40e_macvlan_filter *mv_f;
6262 int ret = I40E_SUCCESS;
6265 * Vlan 0 is the generic filter for untagged packets
6266 * and can't be removed.
6268 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6269 return I40E_ERR_PARAM;
6271 /* If can't find it, just return */
6272 if (!i40e_find_vlan_filter(vsi, vlan))
6273 return I40E_ERR_PARAM;
6275 mac_num = vsi->mac_num;
6278 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6279 return I40E_ERR_PARAM;
6282 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6285 PMD_DRV_LOG(ERR, "failed to allocate memory");
6286 return I40E_ERR_NO_MEMORY;
6289 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6291 if (ret != I40E_SUCCESS)
6294 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6296 if (ret != I40E_SUCCESS)
6299 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6300 if (vsi->vlan_num == 1) {
6301 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6302 if (ret != I40E_SUCCESS)
6305 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6306 if (ret != I40E_SUCCESS)
6310 i40e_set_vlan_filter(vsi, vlan, 0);
6320 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6322 struct i40e_mac_filter *f;
6323 struct i40e_macvlan_filter *mv_f;
6324 int i, vlan_num = 0;
6325 int ret = I40E_SUCCESS;
6327 /* If it's add and we've config it, return */
6328 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6330 return I40E_SUCCESS;
6331 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6332 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6335 * If vlan_num is 0, that's the first time to add mac,
6336 * set mask for vlan_id 0.
6338 if (vsi->vlan_num == 0) {
6339 i40e_set_vlan_filter(vsi, 0, 1);
6342 vlan_num = vsi->vlan_num;
6343 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6344 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6347 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6349 PMD_DRV_LOG(ERR, "failed to allocate memory");
6350 return I40E_ERR_NO_MEMORY;
6353 for (i = 0; i < vlan_num; i++) {
6354 mv_f[i].filter_type = mac_filter->filter_type;
6355 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6359 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6360 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6361 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6362 &mac_filter->mac_addr);
6363 if (ret != I40E_SUCCESS)
6367 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6368 if (ret != I40E_SUCCESS)
6371 /* Add the mac addr into mac list */
6372 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6374 PMD_DRV_LOG(ERR, "failed to allocate memory");
6375 ret = I40E_ERR_NO_MEMORY;
6378 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6380 f->mac_info.filter_type = mac_filter->filter_type;
6381 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6392 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6394 struct i40e_mac_filter *f;
6395 struct i40e_macvlan_filter *mv_f;
6397 enum rte_mac_filter_type filter_type;
6398 int ret = I40E_SUCCESS;
6400 /* Can't find it, return an error */
6401 f = i40e_find_mac_filter(vsi, addr);
6403 return I40E_ERR_PARAM;
6405 vlan_num = vsi->vlan_num;
6406 filter_type = f->mac_info.filter_type;
6407 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6408 filter_type == RTE_MACVLAN_HASH_MATCH) {
6409 if (vlan_num == 0) {
6410 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6411 return I40E_ERR_PARAM;
6413 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6414 filter_type == RTE_MAC_HASH_MATCH)
6417 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6419 PMD_DRV_LOG(ERR, "failed to allocate memory");
6420 return I40E_ERR_NO_MEMORY;
6423 for (i = 0; i < vlan_num; i++) {
6424 mv_f[i].filter_type = filter_type;
6425 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6428 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6429 filter_type == RTE_MACVLAN_HASH_MATCH) {
6430 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6431 if (ret != I40E_SUCCESS)
6435 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6436 if (ret != I40E_SUCCESS)
6439 /* Remove the mac addr into mac list */
6440 TAILQ_REMOVE(&vsi->mac_list, f, next);
6450 /* Configure hash enable flags for RSS */
6452 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6459 if (flags & ETH_RSS_FRAG_IPV4)
6460 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6461 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6462 if (type == I40E_MAC_X722) {
6463 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6464 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6466 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6468 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6469 if (type == I40E_MAC_X722) {
6470 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6471 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6472 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6474 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6476 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6477 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6478 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6479 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6480 if (flags & ETH_RSS_FRAG_IPV6)
6481 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6482 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6483 if (type == I40E_MAC_X722) {
6484 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6485 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6487 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6489 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6490 if (type == I40E_MAC_X722) {
6491 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6492 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6493 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6495 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6497 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6498 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6499 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6500 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6501 if (flags & ETH_RSS_L2_PAYLOAD)
6502 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6507 /* Parse the hash enable flags */
6509 i40e_parse_hena(uint64_t flags)
6511 uint64_t rss_hf = 0;
6515 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6516 rss_hf |= ETH_RSS_FRAG_IPV4;
6517 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6518 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6519 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6520 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6521 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6522 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6523 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6524 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6525 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6526 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6527 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6528 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6529 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6530 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6531 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6532 rss_hf |= ETH_RSS_FRAG_IPV6;
6533 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6534 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6535 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6536 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6537 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6538 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6539 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6540 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6541 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6542 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6543 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6544 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6545 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6546 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6547 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6548 rss_hf |= ETH_RSS_L2_PAYLOAD;
6555 i40e_pf_disable_rss(struct i40e_pf *pf)
6557 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6560 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6561 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6562 if (hw->mac.type == I40E_MAC_X722)
6563 hena &= ~I40E_RSS_HENA_ALL_X722;
6565 hena &= ~I40E_RSS_HENA_ALL;
6566 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6567 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6568 I40E_WRITE_FLUSH(hw);
6572 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6574 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6575 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6578 if (!key || key_len == 0) {
6579 PMD_DRV_LOG(DEBUG, "No key to be configured");
6581 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6583 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6587 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6588 struct i40e_aqc_get_set_rss_key_data *key_dw =
6589 (struct i40e_aqc_get_set_rss_key_data *)key;
6591 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6593 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6595 uint32_t *hash_key = (uint32_t *)key;
6598 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6599 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6600 I40E_WRITE_FLUSH(hw);
6607 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6609 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6610 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6613 if (!key || !key_len)
6616 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6617 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6618 (struct i40e_aqc_get_set_rss_key_data *)key);
6620 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6624 uint32_t *key_dw = (uint32_t *)key;
6627 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6628 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6630 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6636 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6638 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6643 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6644 rss_conf->rss_key_len);
6648 rss_hf = rss_conf->rss_hf;
6649 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6650 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6651 if (hw->mac.type == I40E_MAC_X722)
6652 hena &= ~I40E_RSS_HENA_ALL_X722;
6654 hena &= ~I40E_RSS_HENA_ALL;
6655 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6656 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6657 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6658 I40E_WRITE_FLUSH(hw);
6664 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6665 struct rte_eth_rss_conf *rss_conf)
6667 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6669 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6672 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6673 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6674 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6675 ? I40E_RSS_HENA_ALL_X722
6676 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6677 if (rss_hf != 0) /* Enable RSS */
6679 return 0; /* Nothing to do */
6682 if (rss_hf == 0) /* Disable RSS */
6685 return i40e_hw_rss_hash_set(pf, rss_conf);
6689 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6690 struct rte_eth_rss_conf *rss_conf)
6692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6696 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6697 &rss_conf->rss_key_len);
6699 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6700 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6701 rss_conf->rss_hf = i40e_parse_hena(hena);
6707 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6709 switch (filter_type) {
6710 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6711 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6713 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6714 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6716 case RTE_TUNNEL_FILTER_IMAC_TENID:
6717 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6719 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6720 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6722 case ETH_TUNNEL_FILTER_IMAC:
6723 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6725 case ETH_TUNNEL_FILTER_OIP:
6726 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6728 case ETH_TUNNEL_FILTER_IIP:
6729 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6732 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6739 /* Convert tunnel filter structure */
6741 i40e_tunnel_filter_convert(
6742 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6743 struct i40e_tunnel_filter *tunnel_filter)
6745 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6746 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6747 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6748 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6749 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6750 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6751 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6752 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6753 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6755 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6756 tunnel_filter->input.flags = cld_filter->element.flags;
6757 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6758 tunnel_filter->queue = cld_filter->element.queue_number;
6759 rte_memcpy(tunnel_filter->input.general_fields,
6760 cld_filter->general_fields,
6761 sizeof(cld_filter->general_fields));
6766 /* Check if there exists the tunnel filter */
6767 struct i40e_tunnel_filter *
6768 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6769 const struct i40e_tunnel_filter_input *input)
6773 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6777 return tunnel_rule->hash_map[ret];
6780 /* Add a tunnel filter into the SW list */
6782 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6783 struct i40e_tunnel_filter *tunnel_filter)
6785 struct i40e_tunnel_rule *rule = &pf->tunnel;
6788 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6791 "Failed to insert tunnel filter to hash table %d!",
6795 rule->hash_map[ret] = tunnel_filter;
6797 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6802 /* Delete a tunnel filter from the SW list */
6804 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6805 struct i40e_tunnel_filter_input *input)
6807 struct i40e_tunnel_rule *rule = &pf->tunnel;
6808 struct i40e_tunnel_filter *tunnel_filter;
6811 ret = rte_hash_del_key(rule->hash_table, input);
6814 "Failed to delete tunnel filter to hash table %d!",
6818 tunnel_filter = rule->hash_map[ret];
6819 rule->hash_map[ret] = NULL;
6821 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6822 rte_free(tunnel_filter);
6828 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6829 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6834 uint8_t i, tun_type = 0;
6835 /* internal varialbe to convert ipv6 byte order */
6836 uint32_t convert_ipv6[4];
6838 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6839 struct i40e_vsi *vsi = pf->main_vsi;
6840 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6841 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6842 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6843 struct i40e_tunnel_filter *tunnel, *node;
6844 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6846 cld_filter = rte_zmalloc("tunnel_filter",
6847 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6850 if (NULL == cld_filter) {
6851 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6854 pfilter = cld_filter;
6856 ether_addr_copy(&tunnel_filter->outer_mac,
6857 (struct ether_addr *)&pfilter->element.outer_mac);
6858 ether_addr_copy(&tunnel_filter->inner_mac,
6859 (struct ether_addr *)&pfilter->element.inner_mac);
6861 pfilter->element.inner_vlan =
6862 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6863 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6864 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6865 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6866 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6867 &rte_cpu_to_le_32(ipv4_addr),
6868 sizeof(pfilter->element.ipaddr.v4.data));
6870 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6871 for (i = 0; i < 4; i++) {
6873 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6875 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6877 sizeof(pfilter->element.ipaddr.v6.data));
6880 /* check tunneled type */
6881 switch (tunnel_filter->tunnel_type) {
6882 case RTE_TUNNEL_TYPE_VXLAN:
6883 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6885 case RTE_TUNNEL_TYPE_NVGRE:
6886 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6888 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6889 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6892 /* Other tunnel types is not supported. */
6893 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6894 rte_free(cld_filter);
6898 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6899 &pfilter->element.flags);
6901 rte_free(cld_filter);
6905 pfilter->element.flags |= rte_cpu_to_le_16(
6906 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6907 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6908 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6909 pfilter->element.queue_number =
6910 rte_cpu_to_le_16(tunnel_filter->queue_id);
6912 /* Check if there is the filter in SW list */
6913 memset(&check_filter, 0, sizeof(check_filter));
6914 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6915 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6917 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6921 if (!add && !node) {
6922 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6927 ret = i40e_aq_add_cloud_filters(hw,
6928 vsi->seid, &cld_filter->element, 1);
6930 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6933 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6934 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6935 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6937 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6938 &cld_filter->element, 1);
6940 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6943 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6946 rte_free(cld_filter);
6950 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6951 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6952 #define I40E_TR_GENEVE_KEY_MASK 0x8
6953 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6954 #define I40E_TR_GRE_KEY_MASK 0x400
6955 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6956 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6959 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6961 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6962 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6963 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6964 enum i40e_status_code status = I40E_SUCCESS;
6966 memset(&filter_replace, 0,
6967 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6968 memset(&filter_replace_buf, 0,
6969 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6971 /* create L1 filter */
6972 filter_replace.old_filter_type =
6973 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6974 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6975 filter_replace.tr_bit = 0;
6977 /* Prepare the buffer, 3 entries */
6978 filter_replace_buf.data[0] =
6979 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6980 filter_replace_buf.data[0] |=
6981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6982 filter_replace_buf.data[2] = 0xFF;
6983 filter_replace_buf.data[3] = 0xFF;
6984 filter_replace_buf.data[4] =
6985 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6986 filter_replace_buf.data[4] |=
6987 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6988 filter_replace_buf.data[7] = 0xF0;
6989 filter_replace_buf.data[8]
6990 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6991 filter_replace_buf.data[8] |=
6992 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6993 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6994 I40E_TR_GENEVE_KEY_MASK |
6995 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6996 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6997 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6998 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7000 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7001 &filter_replace_buf);
7006 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7008 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7009 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7010 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7011 enum i40e_status_code status = I40E_SUCCESS;
7014 memset(&filter_replace, 0,
7015 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7016 memset(&filter_replace_buf, 0,
7017 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7018 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7019 I40E_AQC_MIRROR_CLOUD_FILTER;
7020 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7021 filter_replace.new_filter_type =
7022 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7023 /* Prepare the buffer, 2 entries */
7024 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7025 filter_replace_buf.data[0] |=
7026 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7027 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7028 filter_replace_buf.data[4] |=
7029 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7030 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7031 &filter_replace_buf);
7036 memset(&filter_replace, 0,
7037 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7038 memset(&filter_replace_buf, 0,
7039 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7041 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7042 I40E_AQC_MIRROR_CLOUD_FILTER;
7043 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7044 filter_replace.new_filter_type =
7045 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7046 /* Prepare the buffer, 2 entries */
7047 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7048 filter_replace_buf.data[0] |=
7049 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7050 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7051 filter_replace_buf.data[4] |=
7052 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7054 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7055 &filter_replace_buf);
7060 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7061 struct i40e_tunnel_filter_conf *tunnel_filter,
7066 uint8_t i, tun_type = 0;
7067 /* internal variable to convert ipv6 byte order */
7068 uint32_t convert_ipv6[4];
7070 struct i40e_pf_vf *vf = NULL;
7071 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7072 struct i40e_vsi *vsi;
7073 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7074 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7075 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7076 struct i40e_tunnel_filter *tunnel, *node;
7077 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7079 bool big_buffer = 0;
7081 cld_filter = rte_zmalloc("tunnel_filter",
7082 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7085 if (cld_filter == NULL) {
7086 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7089 pfilter = cld_filter;
7091 ether_addr_copy(&tunnel_filter->outer_mac,
7092 (struct ether_addr *)&pfilter->element.outer_mac);
7093 ether_addr_copy(&tunnel_filter->inner_mac,
7094 (struct ether_addr *)&pfilter->element.inner_mac);
7096 pfilter->element.inner_vlan =
7097 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7098 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7099 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7100 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7101 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7102 &rte_cpu_to_le_32(ipv4_addr),
7103 sizeof(pfilter->element.ipaddr.v4.data));
7105 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7106 for (i = 0; i < 4; i++) {
7108 rte_cpu_to_le_32(rte_be_to_cpu_32(
7109 tunnel_filter->ip_addr.ipv6_addr[i]));
7111 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7113 sizeof(pfilter->element.ipaddr.v6.data));
7116 /* check tunneled type */
7117 switch (tunnel_filter->tunnel_type) {
7118 case I40E_TUNNEL_TYPE_VXLAN:
7119 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7121 case I40E_TUNNEL_TYPE_NVGRE:
7122 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7124 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7125 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7127 case I40E_TUNNEL_TYPE_MPLSoUDP:
7128 if (!pf->mpls_replace_flag) {
7129 i40e_replace_mpls_l1_filter(pf);
7130 i40e_replace_mpls_cloud_filter(pf);
7131 pf->mpls_replace_flag = 1;
7133 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7134 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7136 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7137 (teid_le & 0xF) << 12;
7138 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7141 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7143 case I40E_TUNNEL_TYPE_MPLSoGRE:
7144 if (!pf->mpls_replace_flag) {
7145 i40e_replace_mpls_l1_filter(pf);
7146 i40e_replace_mpls_cloud_filter(pf);
7147 pf->mpls_replace_flag = 1;
7149 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7150 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7152 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7153 (teid_le & 0xF) << 12;
7154 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7157 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7159 case I40E_TUNNEL_TYPE_QINQ:
7160 if (!pf->qinq_replace_flag) {
7161 ret = i40e_cloud_filter_qinq_create(pf);
7164 "Failed to create a qinq tunnel filter.");
7165 pf->qinq_replace_flag = 1;
7167 /* Add in the General fields the values of
7168 * the Outer and Inner VLAN
7169 * Big Buffer should be set, see changes in
7170 * i40e_aq_add_cloud_filters
7172 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7173 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7177 /* Other tunnel types is not supported. */
7178 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7179 rte_free(cld_filter);
7183 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7184 pfilter->element.flags =
7185 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7186 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7187 pfilter->element.flags =
7188 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7189 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7190 pfilter->element.flags |=
7191 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7193 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7194 &pfilter->element.flags);
7196 rte_free(cld_filter);
7201 pfilter->element.flags |= rte_cpu_to_le_16(
7202 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7203 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7204 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7205 pfilter->element.queue_number =
7206 rte_cpu_to_le_16(tunnel_filter->queue_id);
7208 if (!tunnel_filter->is_to_vf)
7211 if (tunnel_filter->vf_id >= pf->vf_num) {
7212 PMD_DRV_LOG(ERR, "Invalid argument.");
7215 vf = &pf->vfs[tunnel_filter->vf_id];
7219 /* Check if there is the filter in SW list */
7220 memset(&check_filter, 0, sizeof(check_filter));
7221 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7222 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7223 check_filter.vf_id = tunnel_filter->vf_id;
7224 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7226 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7230 if (!add && !node) {
7231 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7237 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7238 vsi->seid, cld_filter, 1);
7240 ret = i40e_aq_add_cloud_filters(hw,
7241 vsi->seid, &cld_filter->element, 1);
7243 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7246 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7247 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7248 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7251 ret = i40e_aq_remove_cloud_filters_big_buffer(
7252 hw, vsi->seid, cld_filter, 1);
7254 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7255 &cld_filter->element, 1);
7257 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7260 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7263 rte_free(cld_filter);
7268 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7272 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7273 if (pf->vxlan_ports[i] == port)
7281 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7285 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7287 idx = i40e_get_vxlan_port_idx(pf, port);
7289 /* Check if port already exists */
7291 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7295 /* Now check if there is space to add the new port */
7296 idx = i40e_get_vxlan_port_idx(pf, 0);
7299 "Maximum number of UDP ports reached, not adding port %d",
7304 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7307 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7311 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7314 /* New port: add it and mark its index in the bitmap */
7315 pf->vxlan_ports[idx] = port;
7316 pf->vxlan_bitmap |= (1 << idx);
7318 if (!(pf->flags & I40E_FLAG_VXLAN))
7319 pf->flags |= I40E_FLAG_VXLAN;
7325 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7328 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7330 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7331 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7335 idx = i40e_get_vxlan_port_idx(pf, port);
7338 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7342 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7343 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7347 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7350 pf->vxlan_ports[idx] = 0;
7351 pf->vxlan_bitmap &= ~(1 << idx);
7353 if (!pf->vxlan_bitmap)
7354 pf->flags &= ~I40E_FLAG_VXLAN;
7359 /* Add UDP tunneling port */
7361 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7362 struct rte_eth_udp_tunnel *udp_tunnel)
7365 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7367 if (udp_tunnel == NULL)
7370 switch (udp_tunnel->prot_type) {
7371 case RTE_TUNNEL_TYPE_VXLAN:
7372 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7375 case RTE_TUNNEL_TYPE_GENEVE:
7376 case RTE_TUNNEL_TYPE_TEREDO:
7377 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7382 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7390 /* Remove UDP tunneling port */
7392 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7393 struct rte_eth_udp_tunnel *udp_tunnel)
7396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7398 if (udp_tunnel == NULL)
7401 switch (udp_tunnel->prot_type) {
7402 case RTE_TUNNEL_TYPE_VXLAN:
7403 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7405 case RTE_TUNNEL_TYPE_GENEVE:
7406 case RTE_TUNNEL_TYPE_TEREDO:
7407 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7411 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7419 /* Calculate the maximum number of contiguous PF queues that are configured */
7421 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7423 struct rte_eth_dev_data *data = pf->dev_data;
7425 struct i40e_rx_queue *rxq;
7428 for (i = 0; i < pf->lan_nb_qps; i++) {
7429 rxq = data->rx_queues[i];
7430 if (rxq && rxq->q_set)
7441 i40e_pf_config_rss(struct i40e_pf *pf)
7443 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7444 struct rte_eth_rss_conf rss_conf;
7445 uint32_t i, lut = 0;
7449 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7450 * It's necessary to calulate the actual PF queues that are configured.
7452 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7453 num = i40e_pf_calc_configured_queues_num(pf);
7455 num = pf->dev_data->nb_rx_queues;
7457 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7458 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7462 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7466 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7469 lut = (lut << 8) | (j & ((0x1 <<
7470 hw->func_caps.rss_table_entry_width) - 1));
7472 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7475 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7476 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7477 i40e_pf_disable_rss(pf);
7480 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7481 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7482 /* Random default keys */
7483 static uint32_t rss_key_default[] = {0x6b793944,
7484 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7485 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7486 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7488 rss_conf.rss_key = (uint8_t *)rss_key_default;
7489 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7493 return i40e_hw_rss_hash_set(pf, &rss_conf);
7497 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7498 struct rte_eth_tunnel_filter_conf *filter)
7500 if (pf == NULL || filter == NULL) {
7501 PMD_DRV_LOG(ERR, "Invalid parameter");
7505 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7506 PMD_DRV_LOG(ERR, "Invalid queue ID");
7510 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7511 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7515 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7516 (is_zero_ether_addr(&filter->outer_mac))) {
7517 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7521 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7522 (is_zero_ether_addr(&filter->inner_mac))) {
7523 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7530 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7531 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7533 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7538 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7539 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7542 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7543 } else if (len == 4) {
7544 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7546 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7551 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7558 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7559 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7565 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7572 switch (cfg->cfg_type) {
7573 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7574 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7577 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7585 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7586 enum rte_filter_op filter_op,
7589 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7590 int ret = I40E_ERR_PARAM;
7592 switch (filter_op) {
7593 case RTE_ETH_FILTER_SET:
7594 ret = i40e_dev_global_config_set(hw,
7595 (struct rte_eth_global_cfg *)arg);
7598 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7606 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7607 enum rte_filter_op filter_op,
7610 struct rte_eth_tunnel_filter_conf *filter;
7611 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7612 int ret = I40E_SUCCESS;
7614 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7616 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7617 return I40E_ERR_PARAM;
7619 switch (filter_op) {
7620 case RTE_ETH_FILTER_NOP:
7621 if (!(pf->flags & I40E_FLAG_VXLAN))
7622 ret = I40E_NOT_SUPPORTED;
7624 case RTE_ETH_FILTER_ADD:
7625 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7627 case RTE_ETH_FILTER_DELETE:
7628 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7631 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7632 ret = I40E_ERR_PARAM;
7640 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7643 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7646 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7647 ret = i40e_pf_config_rss(pf);
7649 i40e_pf_disable_rss(pf);
7654 /* Get the symmetric hash enable configurations per port */
7656 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7658 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7660 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7663 /* Set the symmetric hash enable configurations per port */
7665 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7667 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7670 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7672 "Symmetric hash has already been enabled");
7675 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7677 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7679 "Symmetric hash has already been disabled");
7682 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7684 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7685 I40E_WRITE_FLUSH(hw);
7689 * Get global configurations of hash function type and symmetric hash enable
7690 * per flow type (pctype). Note that global configuration means it affects all
7691 * the ports on the same NIC.
7694 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7695 struct rte_eth_hash_global_conf *g_cfg)
7697 uint32_t reg, mask = I40E_FLOW_TYPES;
7699 enum i40e_filter_pctype pctype;
7701 memset(g_cfg, 0, sizeof(*g_cfg));
7702 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7703 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7704 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7706 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7707 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7708 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7710 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7711 if (!(mask & (1UL << i)))
7713 mask &= ~(1UL << i);
7714 /* Bit set indicats the coresponding flow type is supported */
7715 g_cfg->valid_bit_mask[0] |= (1UL << i);
7716 /* if flowtype is invalid, continue */
7717 if (!I40E_VALID_FLOW(i))
7719 pctype = i40e_flowtype_to_pctype(i);
7720 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7721 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7722 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7729 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7732 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7734 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7735 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7736 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7737 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7743 * As i40e supports less than 32 flow types, only first 32 bits need to
7746 mask0 = g_cfg->valid_bit_mask[0];
7747 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7749 /* Check if any unsupported flow type configured */
7750 if ((mask0 | i40e_mask) ^ i40e_mask)
7753 if (g_cfg->valid_bit_mask[i])
7761 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7767 * Set global configurations of hash function type and symmetric hash enable
7768 * per flow type (pctype). Note any modifying global configuration will affect
7769 * all the ports on the same NIC.
7772 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7773 struct rte_eth_hash_global_conf *g_cfg)
7778 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7779 enum i40e_filter_pctype pctype;
7781 /* Check the input parameters */
7782 ret = i40e_hash_global_config_check(g_cfg);
7786 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7787 if (!(mask0 & (1UL << i)))
7789 mask0 &= ~(1UL << i);
7790 /* if flowtype is invalid, continue */
7791 if (!I40E_VALID_FLOW(i))
7793 pctype = i40e_flowtype_to_pctype(i);
7794 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7795 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7796 if (hw->mac.type == I40E_MAC_X722) {
7797 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7798 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7799 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7800 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7801 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7803 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7804 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7806 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7807 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7808 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7809 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7810 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7812 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7813 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7814 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7815 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7816 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7818 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7819 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7821 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7822 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7823 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7824 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7825 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7828 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7832 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7836 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7837 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7839 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7841 "Hash function already set to Toeplitz");
7844 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7845 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7847 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7849 "Hash function already set to Simple XOR");
7852 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7854 /* Use the default, and keep it as it is */
7857 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7860 I40E_WRITE_FLUSH(hw);
7866 * Valid input sets for hash and flow director filters per PCTYPE
7869 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7870 enum rte_filter_type filter)
7874 static const uint64_t valid_hash_inset_table[] = {
7875 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7876 I40E_INSET_DMAC | I40E_INSET_SMAC |
7877 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7878 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7879 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7880 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7881 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7882 I40E_INSET_FLEX_PAYLOAD,
7883 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7884 I40E_INSET_DMAC | I40E_INSET_SMAC |
7885 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7886 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7887 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7888 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7889 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7890 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7891 I40E_INSET_FLEX_PAYLOAD,
7892 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7893 I40E_INSET_DMAC | I40E_INSET_SMAC |
7894 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7895 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7896 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7897 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7898 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7899 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7900 I40E_INSET_FLEX_PAYLOAD,
7901 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7902 I40E_INSET_DMAC | I40E_INSET_SMAC |
7903 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7904 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7905 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7906 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7907 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7908 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7909 I40E_INSET_FLEX_PAYLOAD,
7910 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7911 I40E_INSET_DMAC | I40E_INSET_SMAC |
7912 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7913 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7914 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7915 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7916 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7917 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7918 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7919 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7920 I40E_INSET_DMAC | I40E_INSET_SMAC |
7921 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7922 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7923 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7924 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7925 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7926 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7927 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7928 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7929 I40E_INSET_DMAC | I40E_INSET_SMAC |
7930 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7931 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7932 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7933 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7934 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7935 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7936 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7937 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7938 I40E_INSET_DMAC | I40E_INSET_SMAC |
7939 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7940 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7941 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7942 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7943 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7944 I40E_INSET_FLEX_PAYLOAD,
7945 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7946 I40E_INSET_DMAC | I40E_INSET_SMAC |
7947 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7948 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7949 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7950 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7951 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7952 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7953 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7954 I40E_INSET_DMAC | I40E_INSET_SMAC |
7955 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7956 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7957 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7958 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7959 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7960 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7961 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7962 I40E_INSET_DMAC | I40E_INSET_SMAC |
7963 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7964 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7965 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7966 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7967 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7968 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7969 I40E_INSET_FLEX_PAYLOAD,
7970 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7971 I40E_INSET_DMAC | I40E_INSET_SMAC |
7972 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7973 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7974 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7975 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7976 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7977 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7978 I40E_INSET_FLEX_PAYLOAD,
7979 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7980 I40E_INSET_DMAC | I40E_INSET_SMAC |
7981 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7982 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7983 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7984 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7985 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7986 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7987 I40E_INSET_FLEX_PAYLOAD,
7988 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7989 I40E_INSET_DMAC | I40E_INSET_SMAC |
7990 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7991 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7992 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7993 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7994 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7995 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7996 I40E_INSET_FLEX_PAYLOAD,
7997 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7998 I40E_INSET_DMAC | I40E_INSET_SMAC |
7999 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8000 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8001 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8002 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8003 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8004 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8005 I40E_INSET_FLEX_PAYLOAD,
8006 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8007 I40E_INSET_DMAC | I40E_INSET_SMAC |
8008 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8009 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8010 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8011 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8012 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8013 I40E_INSET_FLEX_PAYLOAD,
8014 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8015 I40E_INSET_DMAC | I40E_INSET_SMAC |
8016 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8017 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8018 I40E_INSET_FLEX_PAYLOAD,
8022 * Flow director supports only fields defined in
8023 * union rte_eth_fdir_flow.
8025 static const uint64_t valid_fdir_inset_table[] = {
8026 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8027 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8028 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8029 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8030 I40E_INSET_IPV4_TTL,
8031 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8032 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8033 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8034 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8035 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8036 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8037 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8038 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8039 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8040 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8041 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8042 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8043 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8044 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8045 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8046 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8047 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8048 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8049 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8050 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8051 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8052 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8053 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8054 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8055 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8056 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8057 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8058 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8059 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8060 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8062 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8064 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8065 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8066 I40E_INSET_IPV4_TTL,
8067 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8069 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8070 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8071 I40E_INSET_IPV6_HOP_LIMIT,
8072 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8073 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8074 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8075 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8076 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8077 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8078 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8079 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8080 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8081 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8082 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8083 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8084 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8085 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8086 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8087 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8088 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8089 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8090 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8091 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8092 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8093 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8094 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8095 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8096 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8097 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8098 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8099 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8100 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8101 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8103 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8104 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8105 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8106 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8107 I40E_INSET_IPV6_HOP_LIMIT,
8108 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8109 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8110 I40E_INSET_LAST_ETHER_TYPE,
8113 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8115 if (filter == RTE_ETH_FILTER_HASH)
8116 valid = valid_hash_inset_table[pctype];
8118 valid = valid_fdir_inset_table[pctype];
8124 * Validate if the input set is allowed for a specific PCTYPE
8127 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8128 enum rte_filter_type filter, uint64_t inset)
8132 valid = i40e_get_valid_input_set(pctype, filter);
8133 if (inset & (~valid))
8139 /* default input set fields combination per pctype */
8141 i40e_get_default_input_set(uint16_t pctype)
8143 static const uint64_t default_inset_table[] = {
8144 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8145 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8146 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8147 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8148 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8149 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8150 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8151 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8152 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8153 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8154 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8155 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8156 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8157 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8158 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8159 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8160 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8162 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8163 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8165 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8166 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8167 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8168 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8169 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8170 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8171 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8172 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8173 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8175 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8176 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8177 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8178 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8179 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8180 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8181 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8182 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8183 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8184 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8185 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8188 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8189 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8190 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8191 I40E_INSET_LAST_ETHER_TYPE,
8194 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8197 return default_inset_table[pctype];
8201 * Parse the input set from index to logical bit masks
8204 i40e_parse_input_set(uint64_t *inset,
8205 enum i40e_filter_pctype pctype,
8206 enum rte_eth_input_set_field *field,
8212 static const struct {
8213 enum rte_eth_input_set_field field;
8215 } inset_convert_table[] = {
8216 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8217 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8218 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8219 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8220 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8221 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8222 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8223 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8224 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8225 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8226 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8227 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8228 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8229 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8230 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8231 I40E_INSET_IPV6_NEXT_HDR},
8232 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8233 I40E_INSET_IPV6_HOP_LIMIT},
8234 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8235 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8236 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8237 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8238 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8239 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8240 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8241 I40E_INSET_SCTP_VT},
8242 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8243 I40E_INSET_TUNNEL_DMAC},
8244 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8245 I40E_INSET_VLAN_TUNNEL},
8246 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8247 I40E_INSET_TUNNEL_ID},
8248 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8249 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8250 I40E_INSET_FLEX_PAYLOAD_W1},
8251 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8252 I40E_INSET_FLEX_PAYLOAD_W2},
8253 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8254 I40E_INSET_FLEX_PAYLOAD_W3},
8255 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8256 I40E_INSET_FLEX_PAYLOAD_W4},
8257 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8258 I40E_INSET_FLEX_PAYLOAD_W5},
8259 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8260 I40E_INSET_FLEX_PAYLOAD_W6},
8261 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8262 I40E_INSET_FLEX_PAYLOAD_W7},
8263 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8264 I40E_INSET_FLEX_PAYLOAD_W8},
8267 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8270 /* Only one item allowed for default or all */
8272 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8273 *inset = i40e_get_default_input_set(pctype);
8275 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8276 *inset = I40E_INSET_NONE;
8281 for (i = 0, *inset = 0; i < size; i++) {
8282 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8283 if (field[i] == inset_convert_table[j].field) {
8284 *inset |= inset_convert_table[j].inset;
8289 /* It contains unsupported input set, return immediately */
8290 if (j == RTE_DIM(inset_convert_table))
8298 * Translate the input set from bit masks to register aware bit masks
8302 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8312 static const struct inset_map inset_map_common[] = {
8313 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8314 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8315 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8316 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8317 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8318 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8319 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8320 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8321 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8322 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8323 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8324 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8325 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8326 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8327 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8328 {I40E_INSET_TUNNEL_DMAC,
8329 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8330 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8331 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8332 {I40E_INSET_TUNNEL_SRC_PORT,
8333 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8334 {I40E_INSET_TUNNEL_DST_PORT,
8335 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8336 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8337 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8338 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8339 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8340 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8341 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8342 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8343 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8344 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8347 /* some different registers map in x722*/
8348 static const struct inset_map inset_map_diff_x722[] = {
8349 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8350 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8351 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8352 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8355 static const struct inset_map inset_map_diff_not_x722[] = {
8356 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8357 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8358 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8359 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8365 /* Translate input set to register aware inset */
8366 if (type == I40E_MAC_X722) {
8367 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8368 if (input & inset_map_diff_x722[i].inset)
8369 val |= inset_map_diff_x722[i].inset_reg;
8372 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8373 if (input & inset_map_diff_not_x722[i].inset)
8374 val |= inset_map_diff_not_x722[i].inset_reg;
8378 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8379 if (input & inset_map_common[i].inset)
8380 val |= inset_map_common[i].inset_reg;
8387 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8390 uint64_t inset_need_mask = inset;
8392 static const struct {
8395 } inset_mask_map[] = {
8396 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8397 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8398 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8399 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8400 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8401 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8402 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8403 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8406 if (!inset || !mask || !nb_elem)
8409 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8410 /* Clear the inset bit, if no MASK is required,
8411 * for example proto + ttl
8413 if ((inset & inset_mask_map[i].inset) ==
8414 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8415 inset_need_mask &= ~inset_mask_map[i].inset;
8416 if (!inset_need_mask)
8419 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8420 if ((inset_need_mask & inset_mask_map[i].inset) ==
8421 inset_mask_map[i].inset) {
8422 if (idx >= nb_elem) {
8423 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8426 mask[idx] = inset_mask_map[i].mask;
8435 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8437 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8439 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8441 i40e_write_rx_ctl(hw, addr, val);
8442 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8443 (uint32_t)i40e_read_rx_ctl(hw, addr));
8447 i40e_filter_input_set_init(struct i40e_pf *pf)
8449 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8450 enum i40e_filter_pctype pctype;
8451 uint64_t input_set, inset_reg;
8452 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8455 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8456 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8457 if (hw->mac.type == I40E_MAC_X722) {
8458 if (!I40E_VALID_PCTYPE_X722(pctype))
8461 if (!I40E_VALID_PCTYPE(pctype))
8465 input_set = i40e_get_default_input_set(pctype);
8467 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8468 I40E_INSET_MASK_NUM_REG);
8471 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8474 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8475 (uint32_t)(inset_reg & UINT32_MAX));
8476 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8477 (uint32_t)((inset_reg >>
8478 I40E_32_BIT_WIDTH) & UINT32_MAX));
8479 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8480 (uint32_t)(inset_reg & UINT32_MAX));
8481 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8482 (uint32_t)((inset_reg >>
8483 I40E_32_BIT_WIDTH) & UINT32_MAX));
8485 for (i = 0; i < num; i++) {
8486 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8488 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8491 /*clear unused mask registers of the pctype */
8492 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8493 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8495 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8498 I40E_WRITE_FLUSH(hw);
8500 /* store the default input set */
8501 pf->hash_input_set[pctype] = input_set;
8502 pf->fdir.input_set[pctype] = input_set;
8507 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8508 struct rte_eth_input_set_conf *conf)
8510 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8511 enum i40e_filter_pctype pctype;
8512 uint64_t input_set, inset_reg = 0;
8513 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8517 PMD_DRV_LOG(ERR, "Invalid pointer");
8520 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8521 conf->op != RTE_ETH_INPUT_SET_ADD) {
8522 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8526 if (!I40E_VALID_FLOW(conf->flow_type)) {
8527 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8531 if (hw->mac.type == I40E_MAC_X722) {
8532 /* get translated pctype value in fd pctype register */
8533 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8534 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8537 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8539 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8542 PMD_DRV_LOG(ERR, "Failed to parse input set");
8545 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8547 PMD_DRV_LOG(ERR, "Invalid input set");
8550 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8551 /* get inset value in register */
8552 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8553 inset_reg <<= I40E_32_BIT_WIDTH;
8554 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8555 input_set |= pf->hash_input_set[pctype];
8557 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8558 I40E_INSET_MASK_NUM_REG);
8562 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8564 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8565 (uint32_t)(inset_reg & UINT32_MAX));
8566 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8567 (uint32_t)((inset_reg >>
8568 I40E_32_BIT_WIDTH) & UINT32_MAX));
8570 for (i = 0; i < num; i++)
8571 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8573 /*clear unused mask registers of the pctype */
8574 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8575 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8577 I40E_WRITE_FLUSH(hw);
8579 pf->hash_input_set[pctype] = input_set;
8584 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8585 struct rte_eth_input_set_conf *conf)
8587 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8588 enum i40e_filter_pctype pctype;
8589 uint64_t input_set, inset_reg = 0;
8590 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8594 PMD_DRV_LOG(ERR, "Invalid pointer");
8597 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8598 conf->op != RTE_ETH_INPUT_SET_ADD) {
8599 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8603 if (!I40E_VALID_FLOW(conf->flow_type)) {
8604 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8608 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8610 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8613 PMD_DRV_LOG(ERR, "Failed to parse input set");
8616 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8618 PMD_DRV_LOG(ERR, "Invalid input set");
8622 /* get inset value in register */
8623 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8624 inset_reg <<= I40E_32_BIT_WIDTH;
8625 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8627 /* Can not change the inset reg for flex payload for fdir,
8628 * it is done by writing I40E_PRTQF_FD_FLXINSET
8629 * in i40e_set_flex_mask_on_pctype.
8631 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8632 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8634 input_set |= pf->fdir.input_set[pctype];
8635 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8636 I40E_INSET_MASK_NUM_REG);
8640 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8642 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8643 (uint32_t)(inset_reg & UINT32_MAX));
8644 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8645 (uint32_t)((inset_reg >>
8646 I40E_32_BIT_WIDTH) & UINT32_MAX));
8648 for (i = 0; i < num; i++)
8649 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8651 /*clear unused mask registers of the pctype */
8652 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8653 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8655 I40E_WRITE_FLUSH(hw);
8657 pf->fdir.input_set[pctype] = input_set;
8662 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8667 PMD_DRV_LOG(ERR, "Invalid pointer");
8671 switch (info->info_type) {
8672 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8673 i40e_get_symmetric_hash_enable_per_port(hw,
8674 &(info->info.enable));
8676 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8677 ret = i40e_get_hash_filter_global_config(hw,
8678 &(info->info.global_conf));
8681 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8691 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8696 PMD_DRV_LOG(ERR, "Invalid pointer");
8700 switch (info->info_type) {
8701 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8702 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8704 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8705 ret = i40e_set_hash_filter_global_config(hw,
8706 &(info->info.global_conf));
8708 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8709 ret = i40e_hash_filter_inset_select(hw,
8710 &(info->info.input_set_conf));
8714 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8723 /* Operations for hash function */
8725 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8726 enum rte_filter_op filter_op,
8729 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8732 switch (filter_op) {
8733 case RTE_ETH_FILTER_NOP:
8735 case RTE_ETH_FILTER_GET:
8736 ret = i40e_hash_filter_get(hw,
8737 (struct rte_eth_hash_filter_info *)arg);
8739 case RTE_ETH_FILTER_SET:
8740 ret = i40e_hash_filter_set(hw,
8741 (struct rte_eth_hash_filter_info *)arg);
8744 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8753 /* Convert ethertype filter structure */
8755 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8756 struct i40e_ethertype_filter *filter)
8758 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8759 filter->input.ether_type = input->ether_type;
8760 filter->flags = input->flags;
8761 filter->queue = input->queue;
8766 /* Check if there exists the ehtertype filter */
8767 struct i40e_ethertype_filter *
8768 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8769 const struct i40e_ethertype_filter_input *input)
8773 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8777 return ethertype_rule->hash_map[ret];
8780 /* Add ethertype filter in SW list */
8782 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8783 struct i40e_ethertype_filter *filter)
8785 struct i40e_ethertype_rule *rule = &pf->ethertype;
8788 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8791 "Failed to insert ethertype filter"
8792 " to hash table %d!",
8796 rule->hash_map[ret] = filter;
8798 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8803 /* Delete ethertype filter in SW list */
8805 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8806 struct i40e_ethertype_filter_input *input)
8808 struct i40e_ethertype_rule *rule = &pf->ethertype;
8809 struct i40e_ethertype_filter *filter;
8812 ret = rte_hash_del_key(rule->hash_table, input);
8815 "Failed to delete ethertype filter"
8816 " to hash table %d!",
8820 filter = rule->hash_map[ret];
8821 rule->hash_map[ret] = NULL;
8823 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8830 * Configure ethertype filter, which can director packet by filtering
8831 * with mac address and ether_type or only ether_type
8834 i40e_ethertype_filter_set(struct i40e_pf *pf,
8835 struct rte_eth_ethertype_filter *filter,
8838 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8839 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8840 struct i40e_ethertype_filter *ethertype_filter, *node;
8841 struct i40e_ethertype_filter check_filter;
8842 struct i40e_control_filter_stats stats;
8846 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8847 PMD_DRV_LOG(ERR, "Invalid queue ID");
8850 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8851 filter->ether_type == ETHER_TYPE_IPv6) {
8853 "unsupported ether_type(0x%04x) in control packet filter.",
8854 filter->ether_type);
8857 if (filter->ether_type == ETHER_TYPE_VLAN)
8858 PMD_DRV_LOG(WARNING,
8859 "filter vlan ether_type in first tag is not supported.");
8861 /* Check if there is the filter in SW list */
8862 memset(&check_filter, 0, sizeof(check_filter));
8863 i40e_ethertype_filter_convert(filter, &check_filter);
8864 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8865 &check_filter.input);
8867 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8871 if (!add && !node) {
8872 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8876 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8877 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8878 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8879 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8880 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8882 memset(&stats, 0, sizeof(stats));
8883 ret = i40e_aq_add_rem_control_packet_filter(hw,
8884 filter->mac_addr.addr_bytes,
8885 filter->ether_type, flags,
8887 filter->queue, add, &stats, NULL);
8890 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8891 ret, stats.mac_etype_used, stats.etype_used,
8892 stats.mac_etype_free, stats.etype_free);
8896 /* Add or delete a filter in SW list */
8898 ethertype_filter = rte_zmalloc("ethertype_filter",
8899 sizeof(*ethertype_filter), 0);
8900 rte_memcpy(ethertype_filter, &check_filter,
8901 sizeof(check_filter));
8902 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8904 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8911 * Handle operations for ethertype filter.
8914 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8915 enum rte_filter_op filter_op,
8918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8921 if (filter_op == RTE_ETH_FILTER_NOP)
8925 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8930 switch (filter_op) {
8931 case RTE_ETH_FILTER_ADD:
8932 ret = i40e_ethertype_filter_set(pf,
8933 (struct rte_eth_ethertype_filter *)arg,
8936 case RTE_ETH_FILTER_DELETE:
8937 ret = i40e_ethertype_filter_set(pf,
8938 (struct rte_eth_ethertype_filter *)arg,
8942 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8950 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8951 enum rte_filter_type filter_type,
8952 enum rte_filter_op filter_op,
8960 switch (filter_type) {
8961 case RTE_ETH_FILTER_NONE:
8962 /* For global configuration */
8963 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8965 case RTE_ETH_FILTER_HASH:
8966 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8968 case RTE_ETH_FILTER_MACVLAN:
8969 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8971 case RTE_ETH_FILTER_ETHERTYPE:
8972 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8974 case RTE_ETH_FILTER_TUNNEL:
8975 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8977 case RTE_ETH_FILTER_FDIR:
8978 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8980 case RTE_ETH_FILTER_GENERIC:
8981 if (filter_op != RTE_ETH_FILTER_GET)
8983 *(const void **)arg = &i40e_flow_ops;
8986 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8996 * Check and enable Extended Tag.
8997 * Enabling Extended Tag is important for 40G performance.
9000 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9002 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9006 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
9009 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9013 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9014 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9019 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
9022 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9026 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9027 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9030 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9031 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
9034 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9041 * As some registers wouldn't be reset unless a global hardware reset,
9042 * hardware initialization is needed to put those registers into an
9043 * expected initial state.
9046 i40e_hw_init(struct rte_eth_dev *dev)
9048 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9050 i40e_enable_extended_tag(dev);
9052 /* clear the PF Queue Filter control register */
9053 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9055 /* Disable symmetric hash per port */
9056 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9059 enum i40e_filter_pctype
9060 i40e_flowtype_to_pctype(uint16_t flow_type)
9062 static const enum i40e_filter_pctype pctype_table[] = {
9063 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9064 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9065 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9066 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9067 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9068 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9069 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9070 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9071 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9072 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9073 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9074 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9075 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9076 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9077 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9078 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9079 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9080 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9081 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9084 return pctype_table[flow_type];
9088 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9090 static const uint16_t flowtype_table[] = {
9091 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9092 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9093 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9094 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9095 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9096 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9097 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9098 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9099 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9100 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9101 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9102 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9103 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9104 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9105 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9106 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9107 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9108 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9109 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9110 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9111 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9112 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9113 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9114 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9115 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9116 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9117 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9118 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9119 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9120 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9121 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9124 return flowtype_table[pctype];
9128 * On X710, performance number is far from the expectation on recent firmware
9129 * versions; on XL710, performance number is also far from the expectation on
9130 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9131 * mode is enabled and port MAC address is equal to the packet destination MAC
9132 * address. The fix for this issue may not be integrated in the following
9133 * firmware version. So the workaround in software driver is needed. It needs
9134 * to modify the initial values of 3 internal only registers for both X710 and
9135 * XL710. Note that the values for X710 or XL710 could be different, and the
9136 * workaround can be removed when it is fixed in firmware in the future.
9139 /* For both X710 and XL710 */
9140 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9141 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9143 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9144 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9147 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9148 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9151 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9153 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9154 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9157 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9159 enum i40e_status_code status;
9160 struct i40e_aq_get_phy_abilities_resp phy_ab;
9163 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9173 i40e_configure_registers(struct i40e_hw *hw)
9179 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9180 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9181 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9187 for (i = 0; i < RTE_DIM(reg_table); i++) {
9188 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9189 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9191 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9192 else /* For X710/XL710/XXV710 */
9194 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9197 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9198 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9200 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9201 else /* For X710/XL710/XXV710 */
9203 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9206 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9207 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9208 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9210 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9213 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9216 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9219 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9223 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9224 reg_table[i].addr, reg);
9225 if (reg == reg_table[i].val)
9228 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9229 reg_table[i].val, NULL);
9232 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9233 reg_table[i].val, reg_table[i].addr);
9236 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9237 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9241 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9242 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9243 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9244 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9246 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9251 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9252 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9256 /* Configure for double VLAN RX stripping */
9257 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9258 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9259 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9260 ret = i40e_aq_debug_write_register(hw,
9261 I40E_VSI_TSR(vsi->vsi_id),
9264 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9266 return I40E_ERR_CONFIG;
9270 /* Configure for double VLAN TX insertion */
9271 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9272 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9273 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9274 ret = i40e_aq_debug_write_register(hw,
9275 I40E_VSI_L2TAGSTXVALID(
9276 vsi->vsi_id), reg, NULL);
9279 "Failed to update VSI_L2TAGSTXVALID[%d]",
9281 return I40E_ERR_CONFIG;
9289 * i40e_aq_add_mirror_rule
9290 * @hw: pointer to the hardware structure
9291 * @seid: VEB seid to add mirror rule to
9292 * @dst_id: destination vsi seid
9293 * @entries: Buffer which contains the entities to be mirrored
9294 * @count: number of entities contained in the buffer
9295 * @rule_id:the rule_id of the rule to be added
9297 * Add a mirror rule for a given veb.
9300 static enum i40e_status_code
9301 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9302 uint16_t seid, uint16_t dst_id,
9303 uint16_t rule_type, uint16_t *entries,
9304 uint16_t count, uint16_t *rule_id)
9306 struct i40e_aq_desc desc;
9307 struct i40e_aqc_add_delete_mirror_rule cmd;
9308 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9309 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9312 enum i40e_status_code status;
9314 i40e_fill_default_direct_cmd_desc(&desc,
9315 i40e_aqc_opc_add_mirror_rule);
9316 memset(&cmd, 0, sizeof(cmd));
9318 buff_len = sizeof(uint16_t) * count;
9319 desc.datalen = rte_cpu_to_le_16(buff_len);
9321 desc.flags |= rte_cpu_to_le_16(
9322 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9323 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9324 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9325 cmd.num_entries = rte_cpu_to_le_16(count);
9326 cmd.seid = rte_cpu_to_le_16(seid);
9327 cmd.destination = rte_cpu_to_le_16(dst_id);
9329 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9330 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9332 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9333 hw->aq.asq_last_status, resp->rule_id,
9334 resp->mirror_rules_used, resp->mirror_rules_free);
9335 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9341 * i40e_aq_del_mirror_rule
9342 * @hw: pointer to the hardware structure
9343 * @seid: VEB seid to add mirror rule to
9344 * @entries: Buffer which contains the entities to be mirrored
9345 * @count: number of entities contained in the buffer
9346 * @rule_id:the rule_id of the rule to be delete
9348 * Delete a mirror rule for a given veb.
9351 static enum i40e_status_code
9352 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9353 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9354 uint16_t count, uint16_t rule_id)
9356 struct i40e_aq_desc desc;
9357 struct i40e_aqc_add_delete_mirror_rule cmd;
9358 uint16_t buff_len = 0;
9359 enum i40e_status_code status;
9362 i40e_fill_default_direct_cmd_desc(&desc,
9363 i40e_aqc_opc_delete_mirror_rule);
9364 memset(&cmd, 0, sizeof(cmd));
9365 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9366 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9368 cmd.num_entries = count;
9369 buff_len = sizeof(uint16_t) * count;
9370 desc.datalen = rte_cpu_to_le_16(buff_len);
9371 buff = (void *)entries;
9373 /* rule id is filled in destination field for deleting mirror rule */
9374 cmd.destination = rte_cpu_to_le_16(rule_id);
9376 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9377 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9378 cmd.seid = rte_cpu_to_le_16(seid);
9380 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9381 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9387 * i40e_mirror_rule_set
9388 * @dev: pointer to the hardware structure
9389 * @mirror_conf: mirror rule info
9390 * @sw_id: mirror rule's sw_id
9391 * @on: enable/disable
9393 * set a mirror rule.
9397 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9398 struct rte_eth_mirror_conf *mirror_conf,
9399 uint8_t sw_id, uint8_t on)
9401 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9402 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9403 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9404 struct i40e_mirror_rule *parent = NULL;
9405 uint16_t seid, dst_seid, rule_id;
9409 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9411 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9413 "mirror rule can not be configured without veb or vfs.");
9416 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9417 PMD_DRV_LOG(ERR, "mirror table is full.");
9420 if (mirror_conf->dst_pool > pf->vf_num) {
9421 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9422 mirror_conf->dst_pool);
9426 seid = pf->main_vsi->veb->seid;
9428 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9429 if (sw_id <= it->index) {
9435 if (mirr_rule && sw_id == mirr_rule->index) {
9437 PMD_DRV_LOG(ERR, "mirror rule exists.");
9440 ret = i40e_aq_del_mirror_rule(hw, seid,
9441 mirr_rule->rule_type,
9443 mirr_rule->num_entries, mirr_rule->id);
9446 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9447 ret, hw->aq.asq_last_status);
9450 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9451 rte_free(mirr_rule);
9452 pf->nb_mirror_rule--;
9456 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9460 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9461 sizeof(struct i40e_mirror_rule) , 0);
9463 PMD_DRV_LOG(ERR, "failed to allocate memory");
9464 return I40E_ERR_NO_MEMORY;
9466 switch (mirror_conf->rule_type) {
9467 case ETH_MIRROR_VLAN:
9468 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9469 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9470 mirr_rule->entries[j] =
9471 mirror_conf->vlan.vlan_id[i];
9476 PMD_DRV_LOG(ERR, "vlan is not specified.");
9477 rte_free(mirr_rule);
9480 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9482 case ETH_MIRROR_VIRTUAL_POOL_UP:
9483 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9484 /* check if the specified pool bit is out of range */
9485 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9486 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9487 rte_free(mirr_rule);
9490 for (i = 0, j = 0; i < pf->vf_num; i++) {
9491 if (mirror_conf->pool_mask & (1ULL << i)) {
9492 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9496 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9497 /* add pf vsi to entries */
9498 mirr_rule->entries[j] = pf->main_vsi_seid;
9502 PMD_DRV_LOG(ERR, "pool is not specified.");
9503 rte_free(mirr_rule);
9506 /* egress and ingress in aq commands means from switch but not port */
9507 mirr_rule->rule_type =
9508 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9509 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9510 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9512 case ETH_MIRROR_UPLINK_PORT:
9513 /* egress and ingress in aq commands means from switch but not port*/
9514 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9516 case ETH_MIRROR_DOWNLINK_PORT:
9517 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9520 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9521 mirror_conf->rule_type);
9522 rte_free(mirr_rule);
9526 /* If the dst_pool is equal to vf_num, consider it as PF */
9527 if (mirror_conf->dst_pool == pf->vf_num)
9528 dst_seid = pf->main_vsi_seid;
9530 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9532 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9533 mirr_rule->rule_type, mirr_rule->entries,
9537 "failed to add mirror rule: ret = %d, aq_err = %d.",
9538 ret, hw->aq.asq_last_status);
9539 rte_free(mirr_rule);
9543 mirr_rule->index = sw_id;
9544 mirr_rule->num_entries = j;
9545 mirr_rule->id = rule_id;
9546 mirr_rule->dst_vsi_seid = dst_seid;
9549 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9551 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9553 pf->nb_mirror_rule++;
9558 * i40e_mirror_rule_reset
9559 * @dev: pointer to the device
9560 * @sw_id: mirror rule's sw_id
9562 * reset a mirror rule.
9566 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9568 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9570 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9574 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9576 seid = pf->main_vsi->veb->seid;
9578 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9579 if (sw_id == it->index) {
9585 ret = i40e_aq_del_mirror_rule(hw, seid,
9586 mirr_rule->rule_type,
9588 mirr_rule->num_entries, mirr_rule->id);
9591 "failed to remove mirror rule: status = %d, aq_err = %d.",
9592 ret, hw->aq.asq_last_status);
9595 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9596 rte_free(mirr_rule);
9597 pf->nb_mirror_rule--;
9599 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9606 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9608 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9609 uint64_t systim_cycles;
9611 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9612 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9615 return systim_cycles;
9619 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9621 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9624 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9625 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9632 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9637 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9638 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9645 i40e_start_timecounters(struct rte_eth_dev *dev)
9647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9648 struct i40e_adapter *adapter =
9649 (struct i40e_adapter *)dev->data->dev_private;
9650 struct rte_eth_link link;
9651 uint32_t tsync_inc_l;
9652 uint32_t tsync_inc_h;
9654 /* Get current link speed. */
9655 memset(&link, 0, sizeof(link));
9656 i40e_dev_link_update(dev, 1);
9657 rte_i40e_dev_atomic_read_link_status(dev, &link);
9659 switch (link.link_speed) {
9660 case ETH_SPEED_NUM_40G:
9661 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9662 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9664 case ETH_SPEED_NUM_10G:
9665 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9666 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9668 case ETH_SPEED_NUM_1G:
9669 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9670 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9677 /* Set the timesync increment value. */
9678 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9679 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9681 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9682 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9683 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9685 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9686 adapter->systime_tc.cc_shift = 0;
9687 adapter->systime_tc.nsec_mask = 0;
9689 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9690 adapter->rx_tstamp_tc.cc_shift = 0;
9691 adapter->rx_tstamp_tc.nsec_mask = 0;
9693 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9694 adapter->tx_tstamp_tc.cc_shift = 0;
9695 adapter->tx_tstamp_tc.nsec_mask = 0;
9699 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9701 struct i40e_adapter *adapter =
9702 (struct i40e_adapter *)dev->data->dev_private;
9704 adapter->systime_tc.nsec += delta;
9705 adapter->rx_tstamp_tc.nsec += delta;
9706 adapter->tx_tstamp_tc.nsec += delta;
9712 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9715 struct i40e_adapter *adapter =
9716 (struct i40e_adapter *)dev->data->dev_private;
9718 ns = rte_timespec_to_ns(ts);
9720 /* Set the timecounters to a new value. */
9721 adapter->systime_tc.nsec = ns;
9722 adapter->rx_tstamp_tc.nsec = ns;
9723 adapter->tx_tstamp_tc.nsec = ns;
9729 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9731 uint64_t ns, systime_cycles;
9732 struct i40e_adapter *adapter =
9733 (struct i40e_adapter *)dev->data->dev_private;
9735 systime_cycles = i40e_read_systime_cyclecounter(dev);
9736 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9737 *ts = rte_ns_to_timespec(ns);
9743 i40e_timesync_enable(struct rte_eth_dev *dev)
9745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9746 uint32_t tsync_ctl_l;
9747 uint32_t tsync_ctl_h;
9749 /* Stop the timesync system time. */
9750 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9751 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9752 /* Reset the timesync system time value. */
9753 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9754 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9756 i40e_start_timecounters(dev);
9758 /* Clear timesync registers. */
9759 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9760 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9761 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9762 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9763 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9764 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9766 /* Enable timestamping of PTP packets. */
9767 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9768 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9770 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9771 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9772 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9774 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9775 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9781 i40e_timesync_disable(struct rte_eth_dev *dev)
9783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9784 uint32_t tsync_ctl_l;
9785 uint32_t tsync_ctl_h;
9787 /* Disable timestamping of transmitted PTP packets. */
9788 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9789 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9791 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9792 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9794 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9795 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9797 /* Reset the timesync increment value. */
9798 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9799 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9805 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9806 struct timespec *timestamp, uint32_t flags)
9808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9809 struct i40e_adapter *adapter =
9810 (struct i40e_adapter *)dev->data->dev_private;
9812 uint32_t sync_status;
9813 uint32_t index = flags & 0x03;
9814 uint64_t rx_tstamp_cycles;
9817 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9818 if ((sync_status & (1 << index)) == 0)
9821 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9822 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9823 *timestamp = rte_ns_to_timespec(ns);
9829 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9830 struct timespec *timestamp)
9832 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9833 struct i40e_adapter *adapter =
9834 (struct i40e_adapter *)dev->data->dev_private;
9836 uint32_t sync_status;
9837 uint64_t tx_tstamp_cycles;
9840 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9841 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9844 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9845 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9846 *timestamp = rte_ns_to_timespec(ns);
9852 * i40e_parse_dcb_configure - parse dcb configure from user
9853 * @dev: the device being configured
9854 * @dcb_cfg: pointer of the result of parse
9855 * @*tc_map: bit map of enabled traffic classes
9857 * Returns 0 on success, negative value on failure
9860 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9861 struct i40e_dcbx_config *dcb_cfg,
9864 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9865 uint8_t i, tc_bw, bw_lf;
9867 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9869 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9870 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9871 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9875 /* assume each tc has the same bw */
9876 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9877 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9878 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9879 /* to ensure the sum of tcbw is equal to 100 */
9880 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9881 for (i = 0; i < bw_lf; i++)
9882 dcb_cfg->etscfg.tcbwtable[i]++;
9884 /* assume each tc has the same Transmission Selection Algorithm */
9885 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9886 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9888 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9889 dcb_cfg->etscfg.prioritytable[i] =
9890 dcb_rx_conf->dcb_tc[i];
9892 /* FW needs one App to configure HW */
9893 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9894 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9895 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9896 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9898 if (dcb_rx_conf->nb_tcs == 0)
9899 *tc_map = 1; /* tc0 only */
9901 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9903 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9904 dcb_cfg->pfc.willing = 0;
9905 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9906 dcb_cfg->pfc.pfcenable = *tc_map;
9912 static enum i40e_status_code
9913 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9914 struct i40e_aqc_vsi_properties_data *info,
9915 uint8_t enabled_tcmap)
9917 enum i40e_status_code ret;
9918 int i, total_tc = 0;
9919 uint16_t qpnum_per_tc, bsf, qp_idx;
9920 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9921 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9922 uint16_t used_queues;
9924 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9925 if (ret != I40E_SUCCESS)
9928 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9929 if (enabled_tcmap & (1 << i))
9934 vsi->enabled_tc = enabled_tcmap;
9936 /* different VSI has different queues assigned */
9937 if (vsi->type == I40E_VSI_MAIN)
9938 used_queues = dev_data->nb_rx_queues -
9939 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9940 else if (vsi->type == I40E_VSI_VMDQ2)
9941 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9943 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9944 return I40E_ERR_NO_AVAILABLE_VSI;
9947 qpnum_per_tc = used_queues / total_tc;
9948 /* Number of queues per enabled TC */
9949 if (qpnum_per_tc == 0) {
9950 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9951 return I40E_ERR_INVALID_QP_ID;
9953 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9955 bsf = rte_bsf32(qpnum_per_tc);
9958 * Configure TC and queue mapping parameters, for enabled TC,
9959 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9960 * default queue will serve it.
9963 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9964 if (vsi->enabled_tc & (1 << i)) {
9965 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9966 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9967 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9968 qp_idx += qpnum_per_tc;
9970 info->tc_mapping[i] = 0;
9973 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9974 if (vsi->type == I40E_VSI_SRIOV) {
9975 info->mapping_flags |=
9976 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9977 for (i = 0; i < vsi->nb_qps; i++)
9978 info->queue_mapping[i] =
9979 rte_cpu_to_le_16(vsi->base_queue + i);
9981 info->mapping_flags |=
9982 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9983 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9985 info->valid_sections |=
9986 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9988 return I40E_SUCCESS;
9992 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9993 * @veb: VEB to be configured
9994 * @tc_map: enabled TC bitmap
9996 * Returns 0 on success, negative value on failure
9998 static enum i40e_status_code
9999 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10001 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10002 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10003 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10004 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10005 enum i40e_status_code ret = I40E_SUCCESS;
10009 /* Check if enabled_tc is same as existing or new TCs */
10010 if (veb->enabled_tc == tc_map)
10013 /* configure tc bandwidth */
10014 memset(&veb_bw, 0, sizeof(veb_bw));
10015 veb_bw.tc_valid_bits = tc_map;
10016 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10017 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10018 if (tc_map & BIT_ULL(i))
10019 veb_bw.tc_bw_share_credits[i] = 1;
10021 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10025 "AQ command Config switch_comp BW allocation per TC failed = %d",
10026 hw->aq.asq_last_status);
10030 memset(&ets_query, 0, sizeof(ets_query));
10031 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10033 if (ret != I40E_SUCCESS) {
10035 "Failed to get switch_comp ETS configuration %u",
10036 hw->aq.asq_last_status);
10039 memset(&bw_query, 0, sizeof(bw_query));
10040 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10042 if (ret != I40E_SUCCESS) {
10044 "Failed to get switch_comp bandwidth configuration %u",
10045 hw->aq.asq_last_status);
10049 /* store and print out BW info */
10050 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10051 veb->bw_info.bw_max = ets_query.tc_bw_max;
10052 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10053 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10054 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10055 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10056 I40E_16_BIT_WIDTH);
10057 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10058 veb->bw_info.bw_ets_share_credits[i] =
10059 bw_query.tc_bw_share_credits[i];
10060 veb->bw_info.bw_ets_credits[i] =
10061 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10062 /* 4 bits per TC, 4th bit is reserved */
10063 veb->bw_info.bw_ets_max[i] =
10064 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10065 RTE_LEN2MASK(3, uint8_t));
10066 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10067 veb->bw_info.bw_ets_share_credits[i]);
10068 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10069 veb->bw_info.bw_ets_credits[i]);
10070 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10071 veb->bw_info.bw_ets_max[i]);
10074 veb->enabled_tc = tc_map;
10081 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10082 * @vsi: VSI to be configured
10083 * @tc_map: enabled TC bitmap
10085 * Returns 0 on success, negative value on failure
10087 static enum i40e_status_code
10088 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10090 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10091 struct i40e_vsi_context ctxt;
10092 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10093 enum i40e_status_code ret = I40E_SUCCESS;
10096 /* Check if enabled_tc is same as existing or new TCs */
10097 if (vsi->enabled_tc == tc_map)
10100 /* configure tc bandwidth */
10101 memset(&bw_data, 0, sizeof(bw_data));
10102 bw_data.tc_valid_bits = tc_map;
10103 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10104 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10105 if (tc_map & BIT_ULL(i))
10106 bw_data.tc_bw_credits[i] = 1;
10108 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10111 "AQ command Config VSI BW allocation per TC failed = %d",
10112 hw->aq.asq_last_status);
10115 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10116 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10118 /* Update Queue Pairs Mapping for currently enabled UPs */
10119 ctxt.seid = vsi->seid;
10120 ctxt.pf_num = hw->pf_id;
10122 ctxt.uplink_seid = vsi->uplink_seid;
10123 ctxt.info = vsi->info;
10125 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10129 /* Update the VSI after updating the VSI queue-mapping information */
10130 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10132 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10133 hw->aq.asq_last_status);
10136 /* update the local VSI info with updated queue map */
10137 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10138 sizeof(vsi->info.tc_mapping));
10139 (void)rte_memcpy(&vsi->info.queue_mapping,
10140 &ctxt.info.queue_mapping,
10141 sizeof(vsi->info.queue_mapping));
10142 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10143 vsi->info.valid_sections = 0;
10145 /* query and update current VSI BW information */
10146 ret = i40e_vsi_get_bw_config(vsi);
10149 "Failed updating vsi bw info, err %s aq_err %s",
10150 i40e_stat_str(hw, ret),
10151 i40e_aq_str(hw, hw->aq.asq_last_status));
10155 vsi->enabled_tc = tc_map;
10162 * i40e_dcb_hw_configure - program the dcb setting to hw
10163 * @pf: pf the configuration is taken on
10164 * @new_cfg: new configuration
10165 * @tc_map: enabled TC bitmap
10167 * Returns 0 on success, negative value on failure
10169 static enum i40e_status_code
10170 i40e_dcb_hw_configure(struct i40e_pf *pf,
10171 struct i40e_dcbx_config *new_cfg,
10174 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10175 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10176 struct i40e_vsi *main_vsi = pf->main_vsi;
10177 struct i40e_vsi_list *vsi_list;
10178 enum i40e_status_code ret;
10182 /* Use the FW API if FW > v4.4*/
10183 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10184 (hw->aq.fw_maj_ver >= 5))) {
10186 "FW < v4.4, can not use FW LLDP API to configure DCB");
10187 return I40E_ERR_FIRMWARE_API_VERSION;
10190 /* Check if need reconfiguration */
10191 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10192 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10193 return I40E_SUCCESS;
10196 /* Copy the new config to the current config */
10197 *old_cfg = *new_cfg;
10198 old_cfg->etsrec = old_cfg->etscfg;
10199 ret = i40e_set_dcb_config(hw);
10201 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10202 i40e_stat_str(hw, ret),
10203 i40e_aq_str(hw, hw->aq.asq_last_status));
10206 /* set receive Arbiter to RR mode and ETS scheme by default */
10207 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10208 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10209 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10210 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10211 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10212 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10213 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10214 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10215 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10216 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10217 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10218 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10219 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10221 /* get local mib to check whether it is configured correctly */
10223 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10224 /* Get Local DCB Config */
10225 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10226 &hw->local_dcbx_config);
10228 /* if Veb is created, need to update TC of it at first */
10229 if (main_vsi->veb) {
10230 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10232 PMD_INIT_LOG(WARNING,
10233 "Failed configuring TC for VEB seid=%d",
10234 main_vsi->veb->seid);
10236 /* Update each VSI */
10237 i40e_vsi_config_tc(main_vsi, tc_map);
10238 if (main_vsi->veb) {
10239 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10240 /* Beside main VSI and VMDQ VSIs, only enable default
10241 * TC for other VSIs
10243 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10244 ret = i40e_vsi_config_tc(vsi_list->vsi,
10247 ret = i40e_vsi_config_tc(vsi_list->vsi,
10248 I40E_DEFAULT_TCMAP);
10250 PMD_INIT_LOG(WARNING,
10251 "Failed configuring TC for VSI seid=%d",
10252 vsi_list->vsi->seid);
10256 return I40E_SUCCESS;
10260 * i40e_dcb_init_configure - initial dcb config
10261 * @dev: device being configured
10262 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10264 * Returns 0 on success, negative value on failure
10267 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10269 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10270 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10273 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10274 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10278 /* DCB initialization:
10279 * Update DCB configuration from the Firmware and configure
10280 * LLDP MIB change event.
10282 if (sw_dcb == TRUE) {
10283 ret = i40e_init_dcb(hw);
10284 /* If lldp agent is stopped, the return value from
10285 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10286 * adminq status. Otherwise, it should return success.
10288 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10289 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10290 memset(&hw->local_dcbx_config, 0,
10291 sizeof(struct i40e_dcbx_config));
10292 /* set dcb default configuration */
10293 hw->local_dcbx_config.etscfg.willing = 0;
10294 hw->local_dcbx_config.etscfg.maxtcs = 0;
10295 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10296 hw->local_dcbx_config.etscfg.tsatable[0] =
10298 /* all UPs mapping to TC0 */
10299 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10300 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10301 hw->local_dcbx_config.etsrec =
10302 hw->local_dcbx_config.etscfg;
10303 hw->local_dcbx_config.pfc.willing = 0;
10304 hw->local_dcbx_config.pfc.pfccap =
10305 I40E_MAX_TRAFFIC_CLASS;
10306 /* FW needs one App to configure HW */
10307 hw->local_dcbx_config.numapps = 1;
10308 hw->local_dcbx_config.app[0].selector =
10309 I40E_APP_SEL_ETHTYPE;
10310 hw->local_dcbx_config.app[0].priority = 3;
10311 hw->local_dcbx_config.app[0].protocolid =
10312 I40E_APP_PROTOID_FCOE;
10313 ret = i40e_set_dcb_config(hw);
10316 "default dcb config fails. err = %d, aq_err = %d.",
10317 ret, hw->aq.asq_last_status);
10322 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10323 ret, hw->aq.asq_last_status);
10327 ret = i40e_aq_start_lldp(hw, NULL);
10328 if (ret != I40E_SUCCESS)
10329 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10331 ret = i40e_init_dcb(hw);
10333 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10335 "HW doesn't support DCBX offload.");
10340 "DCBX configuration failed, err = %d, aq_err = %d.",
10341 ret, hw->aq.asq_last_status);
10349 * i40e_dcb_setup - setup dcb related config
10350 * @dev: device being configured
10352 * Returns 0 on success, negative value on failure
10355 i40e_dcb_setup(struct rte_eth_dev *dev)
10357 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10358 struct i40e_dcbx_config dcb_cfg;
10359 uint8_t tc_map = 0;
10362 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10363 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10367 if (pf->vf_num != 0)
10368 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10370 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10372 PMD_INIT_LOG(ERR, "invalid dcb config");
10375 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10377 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10385 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10386 struct rte_eth_dcb_info *dcb_info)
10388 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10389 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10390 struct i40e_vsi *vsi = pf->main_vsi;
10391 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10392 uint16_t bsf, tc_mapping;
10395 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10396 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10398 dcb_info->nb_tcs = 1;
10399 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10400 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10401 for (i = 0; i < dcb_info->nb_tcs; i++)
10402 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10404 /* get queue mapping if vmdq is disabled */
10405 if (!pf->nb_cfg_vmdq_vsi) {
10406 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10407 if (!(vsi->enabled_tc & (1 << i)))
10409 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10410 dcb_info->tc_queue.tc_rxq[j][i].base =
10411 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10412 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10413 dcb_info->tc_queue.tc_txq[j][i].base =
10414 dcb_info->tc_queue.tc_rxq[j][i].base;
10415 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10416 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10417 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10418 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10419 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10424 /* get queue mapping if vmdq is enabled */
10426 vsi = pf->vmdq[j].vsi;
10427 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10428 if (!(vsi->enabled_tc & (1 << i)))
10430 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10431 dcb_info->tc_queue.tc_rxq[j][i].base =
10432 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10433 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10434 dcb_info->tc_queue.tc_txq[j][i].base =
10435 dcb_info->tc_queue.tc_rxq[j][i].base;
10436 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10437 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10438 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10439 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10440 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10443 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10448 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10450 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10451 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10453 uint16_t interval =
10454 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10455 uint16_t msix_intr;
10457 msix_intr = intr_handle->intr_vec[queue_id];
10458 if (msix_intr == I40E_MISC_VEC_ID)
10459 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10460 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10461 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10462 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10464 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10467 I40E_PFINT_DYN_CTLN(msix_intr -
10468 I40E_RX_VEC_START),
10469 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10470 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10471 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10473 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10475 I40E_WRITE_FLUSH(hw);
10476 rte_intr_enable(&pci_dev->intr_handle);
10482 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10484 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10485 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10486 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10487 uint16_t msix_intr;
10489 msix_intr = intr_handle->intr_vec[queue_id];
10490 if (msix_intr == I40E_MISC_VEC_ID)
10491 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10494 I40E_PFINT_DYN_CTLN(msix_intr -
10495 I40E_RX_VEC_START),
10497 I40E_WRITE_FLUSH(hw);
10502 static int i40e_get_regs(struct rte_eth_dev *dev,
10503 struct rte_dev_reg_info *regs)
10505 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10506 uint32_t *ptr_data = regs->data;
10507 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10508 const struct i40e_reg_info *reg_info;
10510 if (ptr_data == NULL) {
10511 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10512 regs->width = sizeof(uint32_t);
10516 /* The first few registers have to be read using AQ operations */
10518 while (i40e_regs_adminq[reg_idx].name) {
10519 reg_info = &i40e_regs_adminq[reg_idx++];
10520 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10522 arr_idx2 <= reg_info->count2;
10524 reg_offset = arr_idx * reg_info->stride1 +
10525 arr_idx2 * reg_info->stride2;
10526 reg_offset += reg_info->base_addr;
10527 ptr_data[reg_offset >> 2] =
10528 i40e_read_rx_ctl(hw, reg_offset);
10532 /* The remaining registers can be read using primitives */
10534 while (i40e_regs_others[reg_idx].name) {
10535 reg_info = &i40e_regs_others[reg_idx++];
10536 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10538 arr_idx2 <= reg_info->count2;
10540 reg_offset = arr_idx * reg_info->stride1 +
10541 arr_idx2 * reg_info->stride2;
10542 reg_offset += reg_info->base_addr;
10543 ptr_data[reg_offset >> 2] =
10544 I40E_READ_REG(hw, reg_offset);
10551 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10553 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10555 /* Convert word count to byte count */
10556 return hw->nvm.sr_size << 1;
10559 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10560 struct rte_dev_eeprom_info *eeprom)
10562 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10563 uint16_t *data = eeprom->data;
10564 uint16_t offset, length, cnt_words;
10567 offset = eeprom->offset >> 1;
10568 length = eeprom->length >> 1;
10569 cnt_words = length;
10571 if (offset > hw->nvm.sr_size ||
10572 offset + length > hw->nvm.sr_size) {
10573 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10577 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10579 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10580 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10581 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10588 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10589 struct ether_addr *mac_addr)
10591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10593 if (!is_valid_assigned_ether_addr(mac_addr)) {
10594 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10598 /* Flags: 0x3 updates port address */
10599 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10603 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10605 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10606 struct rte_eth_dev_data *dev_data = pf->dev_data;
10607 uint32_t frame_size = mtu + ETHER_HDR_LEN
10608 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10611 /* check if mtu is within the allowed range */
10612 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10615 /* mtu setting is forbidden if port is start */
10616 if (dev_data->dev_started) {
10617 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10618 dev_data->port_id);
10622 if (frame_size > ETHER_MAX_LEN)
10623 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10625 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10627 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10632 /* Restore ethertype filter */
10634 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10636 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10637 struct i40e_ethertype_filter_list
10638 *ethertype_list = &pf->ethertype.ethertype_list;
10639 struct i40e_ethertype_filter *f;
10640 struct i40e_control_filter_stats stats;
10643 TAILQ_FOREACH(f, ethertype_list, rules) {
10645 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10646 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10647 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10648 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10649 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10651 memset(&stats, 0, sizeof(stats));
10652 i40e_aq_add_rem_control_packet_filter(hw,
10653 f->input.mac_addr.addr_bytes,
10654 f->input.ether_type,
10655 flags, pf->main_vsi->seid,
10656 f->queue, 1, &stats, NULL);
10658 PMD_DRV_LOG(INFO, "Ethertype filter:"
10659 " mac_etype_used = %u, etype_used = %u,"
10660 " mac_etype_free = %u, etype_free = %u",
10661 stats.mac_etype_used, stats.etype_used,
10662 stats.mac_etype_free, stats.etype_free);
10665 /* Restore tunnel filter */
10667 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10669 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10670 struct i40e_vsi *vsi;
10671 struct i40e_pf_vf *vf;
10672 struct i40e_tunnel_filter_list
10673 *tunnel_list = &pf->tunnel.tunnel_list;
10674 struct i40e_tunnel_filter *f;
10675 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10676 bool big_buffer = 0;
10678 TAILQ_FOREACH(f, tunnel_list, rules) {
10680 vsi = pf->main_vsi;
10682 vf = &pf->vfs[f->vf_id];
10685 memset(&cld_filter, 0, sizeof(cld_filter));
10686 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10687 (struct ether_addr *)&cld_filter.element.outer_mac);
10688 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10689 (struct ether_addr *)&cld_filter.element.inner_mac);
10690 cld_filter.element.inner_vlan = f->input.inner_vlan;
10691 cld_filter.element.flags = f->input.flags;
10692 cld_filter.element.tenant_id = f->input.tenant_id;
10693 cld_filter.element.queue_number = f->queue;
10694 rte_memcpy(cld_filter.general_fields,
10695 f->input.general_fields,
10696 sizeof(f->input.general_fields));
10698 if (((f->input.flags &
10699 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10700 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10702 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10703 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10705 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10706 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10710 i40e_aq_add_cloud_filters_big_buffer(hw,
10711 vsi->seid, &cld_filter, 1);
10713 i40e_aq_add_cloud_filters(hw, vsi->seid,
10714 &cld_filter.element, 1);
10719 i40e_filter_restore(struct i40e_pf *pf)
10721 i40e_ethertype_filter_restore(pf);
10722 i40e_tunnel_filter_restore(pf);
10723 i40e_fdir_filter_restore(pf);
10727 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10729 if (strcmp(dev->data->drv_name,
10737 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10739 struct rte_eth_dev *dev;
10740 struct i40e_pf *pf;
10742 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10744 dev = &rte_eth_devices[port];
10746 if (!is_device_supported(dev, &rte_i40e_pmd))
10749 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10751 if (vf >= pf->vf_num || !pf->vfs) {
10752 PMD_DRV_LOG(ERR, "Invalid argument.");
10756 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10762 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10764 struct rte_eth_dev *dev;
10765 struct i40e_pf *pf;
10766 struct i40e_vsi *vsi;
10767 struct i40e_hw *hw;
10768 struct i40e_vsi_context ctxt;
10771 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10773 dev = &rte_eth_devices[port];
10775 if (!is_device_supported(dev, &rte_i40e_pmd))
10778 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10780 if (vf_id >= pf->vf_num || !pf->vfs) {
10781 PMD_DRV_LOG(ERR, "Invalid argument.");
10785 vsi = pf->vfs[vf_id].vsi;
10787 PMD_DRV_LOG(ERR, "Invalid VSI.");
10791 /* Check if it has been already on or off */
10792 if (vsi->info.valid_sections &
10793 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10795 if ((vsi->info.sec_flags &
10796 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10797 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10798 return 0; /* already on */
10800 if ((vsi->info.sec_flags &
10801 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10802 return 0; /* already off */
10806 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10808 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10810 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10812 memset(&ctxt, 0, sizeof(ctxt));
10813 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10814 ctxt.seid = vsi->seid;
10816 hw = I40E_VSI_TO_HW(vsi);
10817 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10818 if (ret != I40E_SUCCESS) {
10820 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10827 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10831 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10832 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10835 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10839 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10840 if (!(vsi->vfta[j] & (1 << k)))
10843 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10847 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10849 ret = i40e_aq_add_vlan(hw, vsi->seid,
10850 &vlan_data, 1, NULL);
10852 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10853 &vlan_data, 1, NULL);
10854 if (ret != I40E_SUCCESS) {
10856 "Failed to add/rm vlan filter");
10862 return I40E_SUCCESS;
10866 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10868 struct rte_eth_dev *dev;
10869 struct i40e_pf *pf;
10870 struct i40e_vsi *vsi;
10871 struct i40e_hw *hw;
10872 struct i40e_vsi_context ctxt;
10875 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10877 dev = &rte_eth_devices[port];
10879 if (!is_device_supported(dev, &rte_i40e_pmd))
10882 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10884 if (vf_id >= pf->vf_num || !pf->vfs) {
10885 PMD_DRV_LOG(ERR, "Invalid argument.");
10889 vsi = pf->vfs[vf_id].vsi;
10891 PMD_DRV_LOG(ERR, "Invalid VSI.");
10895 /* Check if it has been already on or off */
10896 if (vsi->vlan_anti_spoof_on == on)
10897 return 0; /* already on or off */
10899 vsi->vlan_anti_spoof_on = on;
10900 if (!vsi->vlan_filter_on) {
10901 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10903 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10908 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10910 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10912 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10914 memset(&ctxt, 0, sizeof(ctxt));
10915 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10916 ctxt.seid = vsi->seid;
10918 hw = I40E_VSI_TO_HW(vsi);
10919 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10920 if (ret != I40E_SUCCESS) {
10922 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10929 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10931 struct i40e_mac_filter *f;
10932 struct i40e_macvlan_filter *mv_f;
10934 enum rte_mac_filter_type filter_type;
10935 int ret = I40E_SUCCESS;
10938 /* remove all the MACs */
10939 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10940 vlan_num = vsi->vlan_num;
10941 filter_type = f->mac_info.filter_type;
10942 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10943 filter_type == RTE_MACVLAN_HASH_MATCH) {
10944 if (vlan_num == 0) {
10945 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10946 return I40E_ERR_PARAM;
10948 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10949 filter_type == RTE_MAC_HASH_MATCH)
10952 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10954 PMD_DRV_LOG(ERR, "failed to allocate memory");
10955 return I40E_ERR_NO_MEMORY;
10958 for (i = 0; i < vlan_num; i++) {
10959 mv_f[i].filter_type = filter_type;
10960 (void)rte_memcpy(&mv_f[i].macaddr,
10961 &f->mac_info.mac_addr,
10964 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10965 filter_type == RTE_MACVLAN_HASH_MATCH) {
10966 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10967 &f->mac_info.mac_addr);
10968 if (ret != I40E_SUCCESS) {
10974 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10975 if (ret != I40E_SUCCESS) {
10981 ret = I40E_SUCCESS;
10988 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10990 struct i40e_mac_filter *f;
10991 struct i40e_macvlan_filter *mv_f;
10992 int i, vlan_num = 0;
10993 int ret = I40E_SUCCESS;
10996 /* restore all the MACs */
10997 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10998 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10999 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
11001 * If vlan_num is 0, that's the first time to add mac,
11002 * set mask for vlan_id 0.
11004 if (vsi->vlan_num == 0) {
11005 i40e_set_vlan_filter(vsi, 0, 1);
11008 vlan_num = vsi->vlan_num;
11009 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
11010 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
11013 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
11015 PMD_DRV_LOG(ERR, "failed to allocate memory");
11016 return I40E_ERR_NO_MEMORY;
11019 for (i = 0; i < vlan_num; i++) {
11020 mv_f[i].filter_type = f->mac_info.filter_type;
11021 (void)rte_memcpy(&mv_f[i].macaddr,
11022 &f->mac_info.mac_addr,
11026 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
11027 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
11028 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
11029 &f->mac_info.mac_addr);
11030 if (ret != I40E_SUCCESS) {
11036 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
11037 if (ret != I40E_SUCCESS) {
11043 ret = I40E_SUCCESS;
11050 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
11052 struct i40e_vsi_context ctxt;
11053 struct i40e_hw *hw;
11059 hw = I40E_VSI_TO_HW(vsi);
11061 /* Use the FW API if FW >= v5.0 */
11062 if (hw->aq.fw_maj_ver < 5) {
11063 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
11067 /* Check if it has been already on or off */
11068 if (vsi->info.valid_sections &
11069 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
11071 if ((vsi->info.switch_id &
11072 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
11073 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
11074 return 0; /* already on */
11076 if ((vsi->info.switch_id &
11077 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11078 return 0; /* already off */
11082 /* remove all the MAC and VLAN first */
11083 ret = i40e_vsi_rm_mac_filter(vsi);
11085 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11088 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11089 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11091 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11096 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11098 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11100 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11102 memset(&ctxt, 0, sizeof(ctxt));
11103 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11104 ctxt.seid = vsi->seid;
11106 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11107 if (ret != I40E_SUCCESS) {
11108 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11112 /* add all the MAC and VLAN back */
11113 ret = i40e_vsi_restore_mac_filter(vsi);
11116 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11117 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11126 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11128 struct rte_eth_dev *dev;
11129 struct i40e_pf *pf;
11130 struct i40e_pf_vf *vf;
11131 struct i40e_vsi *vsi;
11135 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11137 dev = &rte_eth_devices[port];
11139 if (!is_device_supported(dev, &rte_i40e_pmd))
11142 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11144 /* setup PF TX loopback */
11145 vsi = pf->main_vsi;
11146 ret = i40e_vsi_set_tx_loopback(vsi, on);
11150 /* setup TX loopback for all the VFs */
11152 /* if no VF, do nothing. */
11156 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11157 vf = &pf->vfs[vf_id];
11160 ret = i40e_vsi_set_tx_loopback(vsi, on);
11169 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11171 struct rte_eth_dev *dev;
11172 struct i40e_pf *pf;
11173 struct i40e_vsi *vsi;
11174 struct i40e_hw *hw;
11177 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11179 dev = &rte_eth_devices[port];
11181 if (!is_device_supported(dev, &rte_i40e_pmd))
11184 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11186 if (vf_id >= pf->vf_num || !pf->vfs) {
11187 PMD_DRV_LOG(ERR, "Invalid argument.");
11191 vsi = pf->vfs[vf_id].vsi;
11193 PMD_DRV_LOG(ERR, "Invalid VSI.");
11197 hw = I40E_VSI_TO_HW(vsi);
11199 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11201 if (ret != I40E_SUCCESS) {
11203 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11210 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11212 struct rte_eth_dev *dev;
11213 struct i40e_pf *pf;
11214 struct i40e_vsi *vsi;
11215 struct i40e_hw *hw;
11218 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11220 dev = &rte_eth_devices[port];
11222 if (!is_device_supported(dev, &rte_i40e_pmd))
11225 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11227 if (vf_id >= pf->vf_num || !pf->vfs) {
11228 PMD_DRV_LOG(ERR, "Invalid argument.");
11232 vsi = pf->vfs[vf_id].vsi;
11234 PMD_DRV_LOG(ERR, "Invalid VSI.");
11238 hw = I40E_VSI_TO_HW(vsi);
11240 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11242 if (ret != I40E_SUCCESS) {
11244 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11251 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11252 struct ether_addr *mac_addr)
11254 struct i40e_mac_filter *f;
11255 struct rte_eth_dev *dev;
11256 struct i40e_pf_vf *vf;
11257 struct i40e_vsi *vsi;
11258 struct i40e_pf *pf;
11261 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11264 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11266 dev = &rte_eth_devices[port];
11268 if (!is_device_supported(dev, &rte_i40e_pmd))
11271 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11273 if (vf_id >= pf->vf_num || !pf->vfs)
11276 vf = &pf->vfs[vf_id];
11279 PMD_DRV_LOG(ERR, "Invalid VSI.");
11283 ether_addr_copy(mac_addr, &vf->mac_addr);
11285 /* Remove all existing mac */
11286 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11287 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11292 /* Set vlan strip on/off for specific VF from host */
11294 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11296 struct rte_eth_dev *dev;
11297 struct i40e_pf *pf;
11298 struct i40e_vsi *vsi;
11301 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11303 dev = &rte_eth_devices[port];
11305 if (!is_device_supported(dev, &rte_i40e_pmd))
11308 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11310 if (vf_id >= pf->vf_num || !pf->vfs) {
11311 PMD_DRV_LOG(ERR, "Invalid argument.");
11315 vsi = pf->vfs[vf_id].vsi;
11320 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11321 if (ret != I40E_SUCCESS) {
11323 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11329 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11332 struct rte_eth_dev *dev;
11333 struct i40e_pf *pf;
11334 struct i40e_hw *hw;
11335 struct i40e_vsi *vsi;
11336 struct i40e_vsi_context ctxt;
11339 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11341 if (vlan_id > ETHER_MAX_VLAN_ID) {
11342 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11346 dev = &rte_eth_devices[port];
11348 if (!is_device_supported(dev, &rte_i40e_pmd))
11351 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11352 hw = I40E_PF_TO_HW(pf);
11355 * return -ENODEV if SRIOV not enabled, VF number not configured
11356 * or no queue assigned.
11358 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11359 pf->vf_nb_qps == 0)
11362 if (vf_id >= pf->vf_num || !pf->vfs) {
11363 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11367 vsi = pf->vfs[vf_id].vsi;
11369 PMD_DRV_LOG(ERR, "Invalid VSI.");
11373 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11374 vsi->info.pvid = vlan_id;
11376 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11378 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11380 memset(&ctxt, 0, sizeof(ctxt));
11381 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11382 ctxt.seid = vsi->seid;
11384 hw = I40E_VSI_TO_HW(vsi);
11385 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11386 if (ret != I40E_SUCCESS) {
11388 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11394 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11397 struct rte_eth_dev *dev;
11398 struct i40e_pf *pf;
11399 struct i40e_vsi *vsi;
11400 struct i40e_hw *hw;
11401 struct i40e_mac_filter_info filter;
11402 struct ether_addr broadcast = {
11403 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11406 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11409 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11413 dev = &rte_eth_devices[port];
11415 if (!is_device_supported(dev, &rte_i40e_pmd))
11418 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11419 hw = I40E_PF_TO_HW(pf);
11421 if (vf_id >= pf->vf_num || !pf->vfs) {
11422 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11427 * return -ENODEV if SRIOV not enabled, VF number not configured
11428 * or no queue assigned.
11430 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11431 pf->vf_nb_qps == 0) {
11432 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11436 vsi = pf->vfs[vf_id].vsi;
11438 PMD_DRV_LOG(ERR, "Invalid VSI.");
11443 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11444 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11445 ret = i40e_vsi_add_mac(vsi, &filter);
11447 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11450 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11452 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11460 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11462 struct rte_eth_dev *dev;
11463 struct i40e_pf *pf;
11464 struct i40e_hw *hw;
11465 struct i40e_vsi *vsi;
11466 struct i40e_vsi_context ctxt;
11469 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11472 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11476 dev = &rte_eth_devices[port];
11478 if (!is_device_supported(dev, &rte_i40e_pmd))
11481 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11482 hw = I40E_PF_TO_HW(pf);
11485 * return -ENODEV if SRIOV not enabled, VF number not configured
11486 * or no queue assigned.
11488 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11489 pf->vf_nb_qps == 0) {
11490 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11494 if (vf_id >= pf->vf_num || !pf->vfs) {
11495 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11499 vsi = pf->vfs[vf_id].vsi;
11501 PMD_DRV_LOG(ERR, "Invalid VSI.");
11505 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11507 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11508 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11510 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11511 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11514 memset(&ctxt, 0, sizeof(ctxt));
11515 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11516 ctxt.seid = vsi->seid;
11518 hw = I40E_VSI_TO_HW(vsi);
11519 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11520 if (ret != I40E_SUCCESS) {
11522 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11529 i40e_vlan_filter_count(struct i40e_vsi *vsi)
11535 for (j = 0; j < I40E_VFTA_SIZE; j++) {
11539 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
11540 if (!(vsi->vfta[j] & (1 << k)))
11543 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
11554 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11555 uint64_t vf_mask, uint8_t on)
11557 struct rte_eth_dev *dev;
11558 struct i40e_pf *pf;
11559 struct i40e_hw *hw;
11560 struct i40e_vsi *vsi;
11562 int ret = I40E_SUCCESS;
11564 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11566 dev = &rte_eth_devices[port];
11568 if (!is_device_supported(dev, &rte_i40e_pmd))
11571 if (vlan_id > ETHER_MAX_VLAN_ID || !vlan_id) {
11572 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11576 if (vf_mask == 0) {
11577 PMD_DRV_LOG(ERR, "No VF.");
11582 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11586 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11587 hw = I40E_PF_TO_HW(pf);
11590 * return -ENODEV if SRIOV not enabled, VF number not configured
11591 * or no queue assigned.
11593 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11594 pf->vf_nb_qps == 0) {
11595 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11599 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11600 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11601 vsi = pf->vfs[vf_idx].vsi;
11603 if (!vsi->vlan_filter_on) {
11604 vsi->vlan_filter_on = true;
11605 i40e_aq_set_vsi_vlan_promisc(hw,
11609 if (!vsi->vlan_anti_spoof_on)
11610 i40e_add_rm_all_vlan_filter(
11613 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11615 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11617 if (!i40e_vlan_filter_count(vsi)) {
11618 vsi->vlan_filter_on = false;
11619 i40e_aq_set_vsi_vlan_promisc(hw,
11628 if (ret != I40E_SUCCESS) {
11630 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11637 rte_pmd_i40e_get_vf_stats(uint8_t port,
11639 struct rte_eth_stats *stats)
11641 struct rte_eth_dev *dev;
11642 struct i40e_pf *pf;
11643 struct i40e_vsi *vsi;
11645 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11647 dev = &rte_eth_devices[port];
11649 if (!is_device_supported(dev, &rte_i40e_pmd))
11652 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11654 if (vf_id >= pf->vf_num || !pf->vfs) {
11655 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11659 vsi = pf->vfs[vf_id].vsi;
11661 PMD_DRV_LOG(ERR, "Invalid VSI.");
11665 i40e_update_vsi_stats(vsi);
11667 stats->ipackets = vsi->eth_stats.rx_unicast +
11668 vsi->eth_stats.rx_multicast +
11669 vsi->eth_stats.rx_broadcast;
11670 stats->opackets = vsi->eth_stats.tx_unicast +
11671 vsi->eth_stats.tx_multicast +
11672 vsi->eth_stats.tx_broadcast;
11673 stats->ibytes = vsi->eth_stats.rx_bytes;
11674 stats->obytes = vsi->eth_stats.tx_bytes;
11675 stats->ierrors = vsi->eth_stats.rx_discards;
11676 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11682 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11685 struct rte_eth_dev *dev;
11686 struct i40e_pf *pf;
11687 struct i40e_vsi *vsi;
11689 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11691 dev = &rte_eth_devices[port];
11693 if (!is_device_supported(dev, &rte_i40e_pmd))
11696 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11698 if (vf_id >= pf->vf_num || !pf->vfs) {
11699 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11703 vsi = pf->vfs[vf_id].vsi;
11705 PMD_DRV_LOG(ERR, "Invalid VSI.");
11709 vsi->offset_loaded = false;
11710 i40e_update_vsi_stats(vsi);
11716 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11718 struct rte_eth_dev *dev;
11719 struct i40e_pf *pf;
11720 struct i40e_vsi *vsi;
11721 struct i40e_hw *hw;
11725 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11727 dev = &rte_eth_devices[port];
11729 if (!is_device_supported(dev, &rte_i40e_pmd))
11732 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11734 if (vf_id >= pf->vf_num || !pf->vfs) {
11735 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11739 vsi = pf->vfs[vf_id].vsi;
11741 PMD_DRV_LOG(ERR, "Invalid VSI.");
11745 if (bw > I40E_QOS_BW_MAX) {
11746 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11751 if (bw % I40E_QOS_BW_GRANULARITY) {
11752 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11753 I40E_QOS_BW_GRANULARITY);
11757 bw /= I40E_QOS_BW_GRANULARITY;
11759 hw = I40E_VSI_TO_HW(vsi);
11762 if (bw == vsi->bw_info.bw_limit) {
11764 "No change for VF max bandwidth. Nothing to do.");
11769 * VF bandwidth limitation and TC bandwidth limitation cannot be
11770 * enabled in parallel, quit if TC bandwidth limitation is enabled.
11772 * If bw is 0, means disable bandwidth limitation. Then no need to
11773 * check TC bandwidth limitation.
11776 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11777 if ((vsi->enabled_tc & BIT_ULL(i)) &&
11778 vsi->bw_info.bw_ets_credits[i])
11781 if (i != I40E_MAX_TRAFFIC_CLASS) {
11783 "TC max bandwidth has been set on this VF,"
11784 " please disable it first.");
11789 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11792 "Failed to set VF %d bandwidth, err(%d).",
11797 /* Store the configuration. */
11798 vsi->bw_info.bw_limit = (uint16_t)bw;
11799 vsi->bw_info.bw_max = 0;
11805 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11806 uint8_t tc_num, uint8_t *bw_weight)
11808 struct rte_eth_dev *dev;
11809 struct i40e_pf *pf;
11810 struct i40e_vsi *vsi;
11811 struct i40e_hw *hw;
11812 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11816 bool b_change = false;
11818 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11820 dev = &rte_eth_devices[port];
11822 if (!is_device_supported(dev, &rte_i40e_pmd))
11825 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11827 if (vf_id >= pf->vf_num || !pf->vfs) {
11828 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11832 vsi = pf->vfs[vf_id].vsi;
11834 PMD_DRV_LOG(ERR, "Invalid VSI.");
11838 if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11839 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11840 I40E_MAX_TRAFFIC_CLASS);
11845 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11846 if (vsi->enabled_tc & BIT_ULL(i))
11849 if (sum != tc_num) {
11851 "Weight should be set for all %d enabled TCs.",
11857 for (i = 0; i < tc_num; i++) {
11858 if (!bw_weight[i]) {
11860 "The weight should be 1 at least.");
11863 sum += bw_weight[i];
11867 "The summary of the TC weight should be 100.");
11872 * Create the configuration for all the TCs.
11874 memset(&tc_bw, 0, sizeof(tc_bw));
11875 tc_bw.tc_valid_bits = vsi->enabled_tc;
11877 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11878 if (vsi->enabled_tc & BIT_ULL(i)) {
11879 if (bw_weight[j] !=
11880 vsi->bw_info.bw_ets_share_credits[i])
11883 tc_bw.tc_bw_credits[i] = bw_weight[j];
11891 "No change for TC allocated bandwidth."
11892 " Nothing to do.");
11896 hw = I40E_VSI_TO_HW(vsi);
11898 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11901 "Failed to set VF %d TC bandwidth weight, err(%d).",
11906 /* Store the configuration. */
11908 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11909 if (vsi->enabled_tc & BIT_ULL(i)) {
11910 vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11919 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11920 uint8_t tc_no, uint32_t bw)
11922 struct rte_eth_dev *dev;
11923 struct i40e_pf *pf;
11924 struct i40e_vsi *vsi;
11925 struct i40e_hw *hw;
11926 struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11930 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11932 dev = &rte_eth_devices[port];
11934 if (!is_device_supported(dev, &rte_i40e_pmd))
11937 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11939 if (vf_id >= pf->vf_num || !pf->vfs) {
11940 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11944 vsi = pf->vfs[vf_id].vsi;
11946 PMD_DRV_LOG(ERR, "Invalid VSI.");
11950 if (bw > I40E_QOS_BW_MAX) {
11951 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11956 if (bw % I40E_QOS_BW_GRANULARITY) {
11957 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11958 I40E_QOS_BW_GRANULARITY);
11962 bw /= I40E_QOS_BW_GRANULARITY;
11964 if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11965 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11966 I40E_MAX_TRAFFIC_CLASS);
11970 hw = I40E_VSI_TO_HW(vsi);
11972 if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11973 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11979 if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11981 "No change for TC max bandwidth. Nothing to do.");
11986 * VF bandwidth limitation and TC bandwidth limitation cannot be
11987 * enabled in parallel, disable VF bandwidth limitation if it's
11989 * If bw is 0, means disable bandwidth limitation. Then no need to
11990 * care about VF bandwidth limitation configuration.
11992 if (bw && vsi->bw_info.bw_limit) {
11993 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11996 "Failed to disable VF(%d)"
11997 " bandwidth limitation, err(%d).",
12003 "VF max bandwidth is disabled according"
12004 " to TC max bandwidth setting.");
12008 * Get all the TCs' info to create a whole picture.
12009 * Because the incremental change isn't permitted.
12011 memset(&tc_bw, 0, sizeof(tc_bw));
12012 tc_bw.tc_valid_bits = vsi->enabled_tc;
12013 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12014 if (vsi->enabled_tc & BIT_ULL(i)) {
12015 tc_bw.tc_bw_credits[i] =
12017 vsi->bw_info.bw_ets_credits[i]);
12020 tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
12022 ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
12025 "Failed to set VF %d TC %d max bandwidth, err(%d).",
12026 vf_id, tc_no, ret);
12030 /* Store the configuration. */
12031 vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
12037 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
12039 struct rte_eth_dev *dev;
12040 struct i40e_pf *pf;
12041 struct i40e_vsi *vsi;
12042 struct i40e_veb *veb;
12043 struct i40e_hw *hw;
12044 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
12048 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12050 dev = &rte_eth_devices[port];
12052 if (!is_device_supported(dev, &rte_i40e_pmd))
12055 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12057 vsi = pf->main_vsi;
12059 PMD_DRV_LOG(ERR, "Invalid VSI.");
12065 PMD_DRV_LOG(ERR, "Invalid VEB.");
12069 if ((tc_map & veb->enabled_tc) != tc_map) {
12071 "TC bitmap isn't the subset of enabled TCs 0x%x.",
12076 if (tc_map == veb->strict_prio_tc) {
12077 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
12081 hw = I40E_VSI_TO_HW(vsi);
12083 /* Disable DCBx if it's the first time to set strict priority. */
12084 if (!veb->strict_prio_tc) {
12085 ret = i40e_aq_stop_lldp(hw, true, NULL);
12088 "Failed to disable DCBx as it's already"
12092 "DCBx is disabled according to strict"
12093 " priority setting.");
12096 memset(&ets_data, 0, sizeof(ets_data));
12097 ets_data.tc_valid_bits = veb->enabled_tc;
12098 ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
12099 ets_data.tc_strict_priority_flags = tc_map;
12100 /* Get all TCs' bandwidth. */
12101 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12102 if (veb->enabled_tc & BIT_ULL(i)) {
12103 /* For rubust, if bandwidth is 0, use 1 instead. */
12104 if (veb->bw_info.bw_ets_share_credits[i])
12105 ets_data.tc_bw_share_credits[i] =
12106 veb->bw_info.bw_ets_share_credits[i];
12108 ets_data.tc_bw_share_credits[i] =
12109 I40E_QOS_BW_WEIGHT_MIN;
12113 if (!veb->strict_prio_tc)
12114 ret = i40e_aq_config_switch_comp_ets(
12115 hw, veb->uplink_seid,
12116 &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12119 ret = i40e_aq_config_switch_comp_ets(
12120 hw, veb->uplink_seid,
12121 &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12124 ret = i40e_aq_config_switch_comp_ets(
12125 hw, veb->uplink_seid,
12126 &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12131 "Failed to set TCs' strict priority mode."
12136 veb->strict_prio_tc = tc_map;
12138 /* Enable DCBx again, if all the TCs' strict priority disabled. */
12140 ret = i40e_aq_start_lldp(hw, NULL);
12143 "Failed to enable DCBx, err(%d).", ret);
12148 "DCBx is enabled again according to strict"
12149 " priority setting.");
12155 #define I40E_PROFILE_INFO_SIZE 48
12156 #define I40E_MAX_PROFILE_NUM 16
12159 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12160 uint32_t track_id, uint8_t *profile_info_sec,
12163 struct i40e_profile_section_header *sec = NULL;
12164 struct i40e_profile_info *pinfo;
12166 sec = (struct i40e_profile_section_header *)profile_info_sec;
12168 sec->data_end = sizeof(struct i40e_profile_section_header) +
12169 sizeof(struct i40e_profile_info);
12170 sec->section.type = SECTION_TYPE_INFO;
12171 sec->section.offset = sizeof(struct i40e_profile_section_header);
12172 sec->section.size = sizeof(struct i40e_profile_info);
12173 pinfo = (struct i40e_profile_info *)(profile_info_sec +
12174 sec->section.offset);
12175 pinfo->track_id = track_id;
12176 memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12177 memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12179 pinfo->op = I40E_DDP_ADD_TRACKID;
12181 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12184 static enum i40e_status_code
12185 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12187 enum i40e_status_code status = I40E_SUCCESS;
12188 struct i40e_profile_section_header *sec;
12190 uint32_t offset = 0;
12193 sec = (struct i40e_profile_section_header *)profile_info_sec;
12194 track_id = ((struct i40e_profile_info *)(profile_info_sec +
12195 sec->section.offset))->track_id;
12197 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12198 track_id, &offset, &info, NULL);
12200 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12201 "offset %d, info %d",
12207 #define I40E_PROFILE_INFO_SIZE 48
12208 #define I40E_MAX_PROFILE_NUM 16
12210 /* Check if the profile info exists */
12212 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12214 struct rte_eth_dev *dev = &rte_eth_devices[port];
12215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12217 struct rte_pmd_i40e_profile_list *p_list;
12218 struct rte_pmd_i40e_profile_info *pinfo, *p;
12222 buff = rte_zmalloc("pinfo_list",
12223 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12226 PMD_DRV_LOG(ERR, "failed to allocate memory");
12230 ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12231 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12234 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12238 p_list = (struct rte_pmd_i40e_profile_list *)buff;
12239 pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12240 sizeof(struct i40e_profile_section_header));
12241 for (i = 0; i < p_list->p_count; i++) {
12242 p = &p_list->p_info[i];
12243 if ((pinfo->track_id == p->track_id) &&
12244 !memcmp(&pinfo->version, &p->version,
12245 sizeof(struct i40e_ddp_version)) &&
12246 !memcmp(&pinfo->name, &p->name,
12247 I40E_DDP_NAME_SIZE)) {
12248 PMD_DRV_LOG(INFO, "Profile exists.");
12259 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12261 enum rte_pmd_i40e_package_op op)
12263 struct rte_eth_dev *dev;
12264 struct i40e_hw *hw;
12265 struct i40e_package_header *pkg_hdr;
12266 struct i40e_generic_seg_header *profile_seg_hdr;
12267 struct i40e_generic_seg_header *metadata_seg_hdr;
12269 uint8_t *profile_info_sec;
12271 enum i40e_status_code status = I40E_SUCCESS;
12273 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12275 dev = &rte_eth_devices[port];
12277 if (!is_device_supported(dev, &rte_i40e_pmd))
12280 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12282 if (size < (sizeof(struct i40e_package_header) +
12283 sizeof(struct i40e_metadata_segment) +
12284 sizeof(uint32_t) * 2)) {
12285 PMD_DRV_LOG(ERR, "Buff is invalid.");
12289 pkg_hdr = (struct i40e_package_header *)buff;
12292 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12296 if (pkg_hdr->segment_count < 2) {
12297 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12301 /* Find metadata segment */
12302 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12304 if (!metadata_seg_hdr) {
12305 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12308 track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12310 /* Find profile segment */
12311 profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12313 if (!profile_seg_hdr) {
12314 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12318 profile_info_sec = rte_zmalloc("i40e_profile_info",
12319 sizeof(struct i40e_profile_section_header) +
12320 sizeof(struct i40e_profile_info),
12322 if (!profile_info_sec) {
12323 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12327 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12328 /* Check if the profile exists */
12329 i40e_generate_profile_info_sec(
12330 ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12331 &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12332 track_id, profile_info_sec, 1);
12333 is_exist = i40e_check_profile_info(port, profile_info_sec);
12334 if (is_exist > 0) {
12335 PMD_DRV_LOG(ERR, "Profile already exists.");
12336 rte_free(profile_info_sec);
12338 } else if (is_exist < 0) {
12339 PMD_DRV_LOG(ERR, "Failed to check profile.");
12340 rte_free(profile_info_sec);
12344 /* Write profile to HW */
12345 status = i40e_write_profile(hw,
12346 (struct i40e_profile_segment *)profile_seg_hdr,
12349 PMD_DRV_LOG(ERR, "Failed to write profile.");
12350 rte_free(profile_info_sec);
12354 /* Add profile info to info list */
12355 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12357 PMD_DRV_LOG(ERR, "Failed to add profile info.");
12359 PMD_DRV_LOG(ERR, "Operation not supported.");
12361 rte_free(profile_info_sec);
12366 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12368 struct rte_eth_dev *dev;
12369 struct i40e_hw *hw;
12370 enum i40e_status_code status = I40E_SUCCESS;
12372 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12374 dev = &rte_eth_devices[port];
12376 if (!is_device_supported(dev, &rte_i40e_pmd))
12379 if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12382 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12384 status = i40e_aq_get_ddp_list(hw, (void *)buff,
12390 /* Create a QinQ cloud filter
12392 * The Fortville NIC has limited resources for tunnel filters,
12393 * so we can only reuse existing filters.
12395 * In step 1 we define which Field Vector fields can be used for
12397 * As we do not have the inner tag defined as a field,
12398 * we have to define it first, by reusing one of L1 entries.
12400 * In step 2 we are replacing one of existing filter types with
12401 * a new one for QinQ.
12402 * As we reusing L1 and replacing L2, some of the default filter
12403 * types will disappear,which depends on L1 and L2 entries we reuse.
12405 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12407 * 1. Create L1 filter of outer vlan (12b) which will be in use
12408 * later when we define the cloud filter.
12409 * a. Valid_flags.replace_cloud = 0
12410 * b. Old_filter = 10 (Stag_Inner_Vlan)
12411 * c. New_filter = 0x10
12412 * d. TR bit = 0xff (optional, not used here)
12413 * e. Buffer – 2 entries:
12414 * i. Byte 0 = 8 (outer vlan FV index).
12416 * Byte 2-3 = 0x0fff
12417 * ii. Byte 0 = 37 (inner vlan FV index).
12419 * Byte 2-3 = 0x0fff
12422 * 2. Create cloud filter using two L1 filters entries: stag and
12423 * new filter(outer vlan+ inner vlan)
12424 * a. Valid_flags.replace_cloud = 1
12425 * b. Old_filter = 1 (instead of outer IP)
12426 * c. New_filter = 0x10
12427 * d. Buffer – 2 entries:
12428 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12429 * Byte 1-3 = 0 (rsv)
12430 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12431 * Byte 9-11 = 0 (rsv)
12434 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12436 int ret = -ENOTSUP;
12437 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12438 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12439 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12442 memset(&filter_replace, 0,
12443 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12444 memset(&filter_replace_buf, 0,
12445 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12447 /* create L1 filter */
12448 filter_replace.old_filter_type =
12449 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12450 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12451 filter_replace.tr_bit = 0;
12453 /* Prepare the buffer, 2 entries */
12454 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12455 filter_replace_buf.data[0] |=
12456 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12457 /* Field Vector 12b mask */
12458 filter_replace_buf.data[2] = 0xff;
12459 filter_replace_buf.data[3] = 0x0f;
12460 filter_replace_buf.data[4] =
12461 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12462 filter_replace_buf.data[4] |=
12463 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12464 /* Field Vector 12b mask */
12465 filter_replace_buf.data[6] = 0xff;
12466 filter_replace_buf.data[7] = 0x0f;
12467 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12468 &filter_replace_buf);
12469 if (ret != I40E_SUCCESS)
12472 /* Apply the second L2 cloud filter */
12473 memset(&filter_replace, 0,
12474 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12475 memset(&filter_replace_buf, 0,
12476 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12478 /* create L2 filter, input for L2 filter will be L1 filter */
12479 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12480 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12481 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12483 /* Prepare the buffer, 2 entries */
12484 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12485 filter_replace_buf.data[0] |=
12486 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12487 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12488 filter_replace_buf.data[4] |=
12489 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12490 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12491 &filter_replace_buf);
12495 RTE_INIT(i40e_init_log);
12497 i40e_init_log(void)
12499 i40e_logtype_init = rte_log_register("pmd.i40e.init");
12500 if (i40e_logtype_init >= 0)
12501 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12502 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
12503 if (i40e_logtype_driver >= 0)
12504 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);