1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
246 char *fw_version, size_t fw_size);
247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
248 struct rte_eth_dev_info *dev_info);
249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
253 enum rte_vlan_type vlan_type,
255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
263 struct rte_eth_fc_conf *fc_conf);
264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
265 struct rte_eth_fc_conf *fc_conf);
266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
267 struct rte_eth_pfc_conf *pfc_conf);
268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr,
272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
277 struct rte_eth_rss_reta_entry64 *reta_conf,
280 static int i40e_get_cap(struct i40e_hw *hw);
281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
282 static int i40e_pf_setup(struct i40e_pf *pf);
283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
287 bool offset_loaded, uint64_t *offset, uint64_t *stat);
288 static void i40e_stat_update_48(struct i40e_hw *hw,
294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
295 static void i40e_dev_interrupt_handler(void *param);
296 static void i40e_dev_alarm_handler(void *param);
297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
298 uint32_t base, uint32_t num);
299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
305 static int i40e_veb_release(struct i40e_veb *veb);
306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
307 struct i40e_vsi *vsi);
308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
311 struct i40e_macvlan_filter *mv_f,
314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
318 struct rte_eth_rss_conf *rss_conf);
319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
322 struct rte_eth_udp_tunnel *udp_tunnel);
323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
334 static void i40e_configure_registers(struct i40e_hw *hw);
335 static void i40e_hw_init(struct rte_eth_dev *dev);
336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
344 struct rte_eth_mirror_conf *mirror_conf,
345 uint8_t sw_id, uint8_t on);
346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp,
353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp);
355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
369 static int i40e_get_regs(struct rte_eth_dev *dev,
370 struct rte_dev_reg_info *regs);
372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *eeprom);
377 static int i40e_get_module_info(struct rte_eth_dev *dev,
378 struct rte_eth_dev_module_info *modinfo);
379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
380 struct rte_dev_eeprom_info *info);
382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
383 struct ether_addr *mac_addr);
385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
387 static int i40e_ethertype_filter_convert(
388 const struct rte_eth_ethertype_filter *input,
389 struct i40e_ethertype_filter *filter);
390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
391 struct i40e_ethertype_filter *filter);
393 static int i40e_tunnel_filter_convert(
394 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
397 struct i40e_tunnel_filter *tunnel_filter);
398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
402 static void i40e_filter_restore(struct i40e_pf *pf);
403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
405 int i40e_logtype_init;
406 int i40e_logtype_driver;
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
413 ETH_I40E_USE_LATEST_VEC,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
632 struct rte_pci_device *pci_dev)
634 char name[RTE_ETH_NAME_MAX_LEN];
635 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
638 if (pci_dev->device.devargs) {
639 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
645 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
646 sizeof(struct i40e_adapter),
647 eth_dev_pci_specific_init, pci_dev,
648 eth_i40e_dev_init, NULL);
650 if (retval || eth_da.nb_representor_ports < 1)
653 /* probe VF representor ports */
654 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
655 pci_dev->device.name);
657 if (pf_ethdev == NULL)
660 for (i = 0; i < eth_da.nb_representor_ports; i++) {
661 struct i40e_vf_representor representor = {
662 .vf_id = eth_da.representor_ports[i],
663 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
664 pf_ethdev->data->dev_private)->switch_domain_id,
665 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
666 pf_ethdev->data->dev_private)
669 /* representor port net_bdf_port */
670 snprintf(name, sizeof(name), "net_%s_representor_%d",
671 pci_dev->device.name, eth_da.representor_ports[i]);
673 retval = rte_eth_dev_create(&pci_dev->device, name,
674 sizeof(struct i40e_vf_representor), NULL, NULL,
675 i40e_vf_representor_init, &representor);
678 PMD_DRV_LOG(ERR, "failed to create i40e vf "
679 "representor %s.", name);
685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
687 struct rte_eth_dev *ethdev;
689 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
697 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
700 static struct rte_pci_driver rte_i40e_pmd = {
701 .id_table = pci_id_i40e_map,
702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
703 RTE_PCI_DRV_IOVA_AS_VA,
704 .probe = eth_i40e_pci_probe,
705 .remove = eth_i40e_pci_remove,
709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
712 uint32_t ori_reg_val;
713 struct rte_eth_dev *dev;
715 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
716 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
717 i40e_write_rx_ctl(hw, reg_addr, reg_val);
718 if (ori_reg_val != reg_val)
720 "i40e device %s changed global register [0x%08x]."
721 " original: 0x%08x, new: 0x%08x",
722 dev->device->name, reg_addr, ori_reg_val, reg_val);
725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
729 #ifndef I40E_GLQF_ORT
730 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
732 #ifndef I40E_GLQF_PIT
733 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
735 #ifndef I40E_GLQF_L3_MAP
736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
742 * Initialize registers for parsing packet type of QinQ
743 * This should be removed from code once proper
744 * configuration API is added to avoid configuration conflicts
745 * between ports of the same device.
747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
751 static inline void i40e_config_automask(struct i40e_pf *pf)
753 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
756 /* INTENA flag is not auto-cleared for interrupt */
757 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
758 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
759 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
761 /* If support multi-driver, PF will use INT0. */
762 if (!pf->support_multi_driver)
763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
765 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
768 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
771 * Add a ethertype filter to drop all flow control frames transmitted
775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
783 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
784 I40E_FLOW_CONTROL_ETHERTYPE, flags,
785 pf->main_vsi_seid, 0,
789 "Failed to add filter to drop flow control frames from VSIs.");
793 floating_veb_list_handler(__rte_unused const char *key,
794 const char *floating_veb_value,
798 unsigned int count = 0;
801 bool *vf_floating_veb = opaque;
803 while (isblank(*floating_veb_value))
804 floating_veb_value++;
806 /* Reset floating VEB configuration for VFs */
807 for (idx = 0; idx < I40E_MAX_VF; idx++)
808 vf_floating_veb[idx] = false;
812 while (isblank(*floating_veb_value))
813 floating_veb_value++;
814 if (*floating_veb_value == '\0')
817 idx = strtoul(floating_veb_value, &end, 10);
818 if (errno || end == NULL)
820 while (isblank(*end))
824 } else if ((*end == ';') || (*end == '\0')) {
826 if (min == I40E_MAX_VF)
828 if (max >= I40E_MAX_VF)
829 max = I40E_MAX_VF - 1;
830 for (idx = min; idx <= max; idx++) {
831 vf_floating_veb[idx] = true;
838 floating_veb_value = end + 1;
839 } while (*end != '\0');
848 config_vf_floating_veb(struct rte_devargs *devargs,
849 uint16_t floating_veb,
850 bool *vf_floating_veb)
852 struct rte_kvargs *kvlist;
854 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
858 /* All the VFs attach to the floating VEB by default
859 * when the floating VEB is enabled.
861 for (i = 0; i < I40E_MAX_VF; i++)
862 vf_floating_veb[i] = true;
867 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
871 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
872 rte_kvargs_free(kvlist);
875 /* When the floating_veb_list parameter exists, all the VFs
876 * will attach to the legacy VEB firstly, then configure VFs
877 * to the floating VEB according to the floating_veb_list.
879 if (rte_kvargs_process(kvlist, floating_veb_list,
880 floating_veb_list_handler,
881 vf_floating_veb) < 0) {
882 rte_kvargs_free(kvlist);
885 rte_kvargs_free(kvlist);
889 i40e_check_floating_handler(__rte_unused const char *key,
891 __rte_unused void *opaque)
893 if (strcmp(value, "1"))
900 is_floating_veb_supported(struct rte_devargs *devargs)
902 struct rte_kvargs *kvlist;
903 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
908 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
912 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
913 rte_kvargs_free(kvlist);
916 /* Floating VEB is enabled when there's key-value:
917 * enable_floating_veb=1
919 if (rte_kvargs_process(kvlist, floating_veb_key,
920 i40e_check_floating_handler, NULL) < 0) {
921 rte_kvargs_free(kvlist);
924 rte_kvargs_free(kvlist);
930 config_floating_veb(struct rte_eth_dev *dev)
932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
938 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
940 is_floating_veb_supported(pci_dev->device.devargs);
941 config_vf_floating_veb(pci_dev->device.devargs,
943 pf->floating_veb_list);
945 pf->floating_veb = false;
949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
957 char ethertype_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters ethertype_hash_params = {
961 .name = ethertype_hash_name,
962 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
963 .key_len = sizeof(struct i40e_ethertype_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize ethertype filter rule list and hash */
970 TAILQ_INIT(ðertype_rule->ethertype_list);
971 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
972 "ethertype_%s", dev->device->name);
973 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
974 if (!ethertype_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
978 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
979 sizeof(struct i40e_ethertype_filter *) *
980 I40E_MAX_ETHERTYPE_FILTER_NUM,
982 if (!ethertype_rule->hash_map) {
984 "Failed to allocate memory for ethertype hash map!");
986 goto err_ethertype_hash_map_alloc;
991 err_ethertype_hash_map_alloc:
992 rte_hash_free(ethertype_rule->hash_table);
998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters tunnel_hash_params = {
1006 .name = tunnel_hash_name,
1007 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize tunnel filter rule list and hash */
1015 TAILQ_INIT(&tunnel_rule->tunnel_list);
1016 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017 "tunnel_%s", dev->device->name);
1018 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019 if (!tunnel_rule->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024 sizeof(struct i40e_tunnel_filter *) *
1025 I40E_MAX_TUNNEL_FILTER_NUM,
1027 if (!tunnel_rule->hash_map) {
1029 "Failed to allocate memory for tunnel hash map!");
1031 goto err_tunnel_hash_map_alloc;
1036 err_tunnel_hash_map_alloc:
1037 rte_hash_free(tunnel_rule->hash_table);
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046 struct i40e_fdir_info *fdir_info = &pf->fdir;
1047 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 struct rte_hash_parameters fdir_hash_params = {
1051 .name = fdir_hash_name,
1052 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053 .key_len = sizeof(struct i40e_fdir_input),
1054 .hash_func = rte_hash_crc,
1055 .hash_func_init_val = 0,
1056 .socket_id = rte_socket_id(),
1059 /* Initialize flow director filter rule list and hash */
1060 TAILQ_INIT(&fdir_info->fdir_list);
1061 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062 "fdir_%s", dev->device->name);
1063 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064 if (!fdir_info->hash_table) {
1065 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069 sizeof(struct i40e_fdir_filter *) *
1070 I40E_MAX_FDIR_FILTER_NUM,
1072 if (!fdir_info->hash_map) {
1074 "Failed to allocate memory for fdir hash map!");
1076 goto err_fdir_hash_map_alloc;
1080 err_fdir_hash_map_alloc:
1081 rte_hash_free(fdir_info->hash_table);
1087 i40e_init_customized_info(struct i40e_pf *pf)
1091 /* Initialize customized pctype */
1092 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093 pf->customized_pctype[i].index = i;
1094 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095 pf->customized_pctype[i].valid = false;
1098 pf->gtp_support = false;
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106 struct i40e_queue_regions *info = &pf->queue_region;
1109 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1112 memset(info, 0, sizeof(struct i40e_queue_regions));
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1121 unsigned long support_multi_driver;
1124 pf = (struct i40e_pf *)opaque;
1127 support_multi_driver = strtoul(value, &end, 10);
1128 if (errno != 0 || end == value || *end != 0) {
1129 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1133 if (support_multi_driver == 1 || support_multi_driver == 0)
1134 pf->support_multi_driver = (bool)support_multi_driver;
1136 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137 "enable global configuration by default."
1138 ETH_I40E_SUPPORT_MULTI_DRIVER);
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146 struct rte_kvargs *kvlist;
1149 /* Enable global configuration by default */
1150 pf->support_multi_driver = false;
1152 if (!dev->device->devargs)
1155 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1159 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160 if (!kvargs_count) {
1161 rte_kvargs_free(kvlist);
1165 if (kvargs_count > 1)
1166 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167 "the first invalid or last valid one is used !",
1168 ETH_I40E_SUPPORT_MULTI_DRIVER);
1170 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171 i40e_parse_multi_drv_handler, pf) < 0) {
1172 rte_kvargs_free(kvlist);
1176 rte_kvargs_free(kvlist);
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182 uint32_t reg_addr, uint64_t reg_val,
1183 struct i40e_asq_cmd_details *cmd_details)
1185 uint64_t ori_reg_val;
1186 struct rte_eth_dev *dev;
1189 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190 if (ret != I40E_SUCCESS) {
1192 "Fail to debug read from 0x%08x",
1196 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1198 if (ori_reg_val != reg_val)
1199 PMD_DRV_LOG(WARNING,
1200 "i40e device %s changed global register [0x%08x]."
1201 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202 dev->device->name, reg_addr, ori_reg_val, reg_val);
1204 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1212 struct i40e_adapter *ad;
1215 ad = (struct i40e_adapter *)opaque;
1217 use_latest_vec = atoi(value);
1219 if (use_latest_vec != 0 && use_latest_vec != 1)
1220 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1222 ad->use_latest_vec = (uint8_t)use_latest_vec;
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1230 struct i40e_adapter *ad =
1231 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232 struct rte_kvargs *kvlist;
1235 ad->use_latest_vec = false;
1237 if (!dev->device->devargs)
1240 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1244 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245 if (!kvargs_count) {
1246 rte_kvargs_free(kvlist);
1250 if (kvargs_count > 1)
1251 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252 "the first invalid or last valid one is used !",
1253 ETH_I40E_USE_LATEST_VEC);
1255 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256 i40e_parse_latest_vec_handler, ad) < 0) {
1257 rte_kvargs_free(kvlist);
1261 rte_kvargs_free(kvlist);
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1270 struct rte_pci_device *pci_dev;
1271 struct rte_intr_handle *intr_handle;
1272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 struct i40e_vsi *vsi;
1277 uint8_t aq_fail = 0;
1279 PMD_INIT_FUNC_TRACE();
1281 dev->dev_ops = &i40e_eth_dev_ops;
1282 dev->rx_pkt_burst = i40e_recv_pkts;
1283 dev->tx_pkt_burst = i40e_xmit_pkts;
1284 dev->tx_pkt_prepare = i40e_prep_pkts;
1286 /* for secondary processes, we don't initialise any further as primary
1287 * has already done this work. Only check we don't need a different
1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290 i40e_set_rx_function(dev);
1291 i40e_set_tx_function(dev);
1294 i40e_set_default_ptype_table(dev);
1295 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296 intr_handle = &pci_dev->intr_handle;
1298 rte_eth_copy_pci_info(dev, pci_dev);
1300 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301 pf->adapter->eth_dev = dev;
1302 pf->dev_data = dev->data;
1304 hw->back = I40E_PF_TO_ADAPTER(pf);
1305 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308 "Hardware is not available, as address is NULL");
1312 hw->vendor_id = pci_dev->id.vendor_id;
1313 hw->device_id = pci_dev->id.device_id;
1314 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316 hw->bus.device = pci_dev->addr.devid;
1317 hw->bus.func = pci_dev->addr.function;
1318 hw->adapter_stopped = 0;
1321 * Switch Tag value should not be identical to either the First Tag
1322 * or Second Tag values. So set something other than common Ethertype
1323 * for internal switching.
1325 hw->switch_tag = 0xffff;
1327 /* Check if need to support multi-driver */
1328 i40e_support_multi_driver(dev);
1329 /* Check if users want the latest supported vec path */
1330 i40e_use_latest_vec(dev);
1332 /* Make sure all is clean before doing PF reset */
1335 /* Initialize the hardware */
1338 /* Reset here to make sure all is clean for each PF */
1339 ret = i40e_pf_reset(hw);
1341 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1345 /* Initialize the shared code (base driver) */
1346 ret = i40e_init_shared_code(hw);
1348 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1352 i40e_config_automask(pf);
1354 i40e_set_default_pctype_table(dev);
1357 * To work around the NVM issue, initialize registers
1358 * for packet type of QinQ by software.
1359 * It should be removed once issues are fixed in NVM.
1361 if (!pf->support_multi_driver)
1362 i40e_GLQF_reg_init(hw);
1364 /* Initialize the input set for filters (hash and fd) to default value */
1365 i40e_filter_input_set_init(pf);
1367 /* Initialize the parameters for adminq */
1368 i40e_init_adminq_parameter(hw);
1369 ret = i40e_init_adminq(hw);
1370 if (ret != I40E_SUCCESS) {
1371 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1374 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1375 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1376 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1377 ((hw->nvm.version >> 12) & 0xf),
1378 ((hw->nvm.version >> 4) & 0xff),
1379 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1381 /* initialise the L3_MAP register */
1382 if (!pf->support_multi_driver) {
1383 ret = i40e_aq_debug_write_global_register(hw,
1384 I40E_GLQF_L3_MAP(40),
1387 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1390 "Global register 0x%08x is changed with 0x28",
1391 I40E_GLQF_L3_MAP(40));
1394 /* Need the special FW version to support floating VEB */
1395 config_floating_veb(dev);
1396 /* Clear PXE mode */
1397 i40e_clear_pxe_mode(hw);
1398 i40e_dev_sync_phy_type(hw);
1401 * On X710, performance number is far from the expectation on recent
1402 * firmware versions. The fix for this issue may not be integrated in
1403 * the following firmware version. So the workaround in software driver
1404 * is needed. It needs to modify the initial values of 3 internal only
1405 * registers. Note that the workaround can be removed when it is fixed
1406 * in firmware in the future.
1408 i40e_configure_registers(hw);
1410 /* Get hw capabilities */
1411 ret = i40e_get_cap(hw);
1412 if (ret != I40E_SUCCESS) {
1413 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1414 goto err_get_capabilities;
1417 /* Initialize parameters for PF */
1418 ret = i40e_pf_parameter_init(dev);
1420 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1421 goto err_parameter_init;
1424 /* Initialize the queue management */
1425 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1427 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1428 goto err_qp_pool_init;
1430 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1431 hw->func_caps.num_msix_vectors - 1);
1433 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1434 goto err_msix_pool_init;
1437 /* Initialize lan hmc */
1438 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1439 hw->func_caps.num_rx_qp, 0, 0);
1440 if (ret != I40E_SUCCESS) {
1441 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1442 goto err_init_lan_hmc;
1445 /* Configure lan hmc */
1446 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1447 if (ret != I40E_SUCCESS) {
1448 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1449 goto err_configure_lan_hmc;
1452 /* Get and check the mac address */
1453 i40e_get_mac_addr(hw, hw->mac.addr);
1454 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1455 PMD_INIT_LOG(ERR, "mac address is not valid");
1457 goto err_get_mac_addr;
1459 /* Copy the permanent MAC address */
1460 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1461 (struct ether_addr *) hw->mac.perm_addr);
1463 /* Disable flow control */
1464 hw->fc.requested_mode = I40E_FC_NONE;
1465 i40e_set_fc(hw, &aq_fail, TRUE);
1467 /* Set the global registers with default ether type value */
1468 if (!pf->support_multi_driver) {
1469 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1471 if (ret != I40E_SUCCESS) {
1473 "Failed to set the default outer "
1475 goto err_setup_pf_switch;
1479 /* PF setup, which includes VSI setup */
1480 ret = i40e_pf_setup(pf);
1482 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1483 goto err_setup_pf_switch;
1486 /* reset all stats of the device, including pf and main vsi */
1487 i40e_dev_stats_reset(dev);
1491 /* Disable double vlan by default */
1492 i40e_vsi_config_double_vlan(vsi, FALSE);
1494 /* Disable S-TAG identification when floating_veb is disabled */
1495 if (!pf->floating_veb) {
1496 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1497 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1498 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1499 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1503 if (!vsi->max_macaddrs)
1504 len = ETHER_ADDR_LEN;
1506 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1508 /* Should be after VSI initialized */
1509 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1510 if (!dev->data->mac_addrs) {
1512 "Failed to allocated memory for storing mac address");
1515 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1516 &dev->data->mac_addrs[0]);
1518 /* Init dcb to sw mode by default */
1519 ret = i40e_dcb_init_configure(dev, TRUE);
1520 if (ret != I40E_SUCCESS) {
1521 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1522 pf->flags &= ~I40E_FLAG_DCB;
1524 /* Update HW struct after DCB configuration */
1527 /* initialize pf host driver to setup SRIOV resource if applicable */
1528 i40e_pf_host_init(dev);
1530 /* register callback func to eal lib */
1531 rte_intr_callback_register(intr_handle,
1532 i40e_dev_interrupt_handler, dev);
1534 /* configure and enable device interrupt */
1535 i40e_pf_config_irq0(hw, TRUE);
1536 i40e_pf_enable_irq0(hw);
1538 /* enable uio intr after callback register */
1539 rte_intr_enable(intr_handle);
1541 /* By default disable flexible payload in global configuration */
1542 if (!pf->support_multi_driver)
1543 i40e_flex_payload_reg_set_default(hw);
1546 * Add an ethertype filter to drop all flow control frames transmitted
1547 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1550 i40e_add_tx_flow_control_drop_filter(pf);
1552 /* Set the max frame size to 0x2600 by default,
1553 * in case other drivers changed the default value.
1555 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1557 /* initialize mirror rule list */
1558 TAILQ_INIT(&pf->mirror_list);
1560 /* initialize Traffic Manager configuration */
1561 i40e_tm_conf_init(dev);
1563 /* Initialize customized information */
1564 i40e_init_customized_info(pf);
1566 ret = i40e_init_ethtype_filter_list(dev);
1568 goto err_init_ethtype_filter_list;
1569 ret = i40e_init_tunnel_filter_list(dev);
1571 goto err_init_tunnel_filter_list;
1572 ret = i40e_init_fdir_filter_list(dev);
1574 goto err_init_fdir_filter_list;
1576 /* initialize queue region configuration */
1577 i40e_init_queue_region_conf(dev);
1579 /* initialize rss configuration from rte_flow */
1580 memset(&pf->rss_info, 0,
1581 sizeof(struct i40e_rte_flow_rss_conf));
1585 err_init_fdir_filter_list:
1586 rte_free(pf->tunnel.hash_table);
1587 rte_free(pf->tunnel.hash_map);
1588 err_init_tunnel_filter_list:
1589 rte_free(pf->ethertype.hash_table);
1590 rte_free(pf->ethertype.hash_map);
1591 err_init_ethtype_filter_list:
1592 rte_free(dev->data->mac_addrs);
1594 i40e_vsi_release(pf->main_vsi);
1595 err_setup_pf_switch:
1597 err_configure_lan_hmc:
1598 (void)i40e_shutdown_lan_hmc(hw);
1600 i40e_res_pool_destroy(&pf->msix_pool);
1602 i40e_res_pool_destroy(&pf->qp_pool);
1605 err_get_capabilities:
1606 (void)i40e_shutdown_adminq(hw);
1612 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1614 struct i40e_ethertype_filter *p_ethertype;
1615 struct i40e_ethertype_rule *ethertype_rule;
1617 ethertype_rule = &pf->ethertype;
1618 /* Remove all ethertype filter rules and hash */
1619 if (ethertype_rule->hash_map)
1620 rte_free(ethertype_rule->hash_map);
1621 if (ethertype_rule->hash_table)
1622 rte_hash_free(ethertype_rule->hash_table);
1624 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1625 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1626 p_ethertype, rules);
1627 rte_free(p_ethertype);
1632 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1634 struct i40e_tunnel_filter *p_tunnel;
1635 struct i40e_tunnel_rule *tunnel_rule;
1637 tunnel_rule = &pf->tunnel;
1638 /* Remove all tunnel director rules and hash */
1639 if (tunnel_rule->hash_map)
1640 rte_free(tunnel_rule->hash_map);
1641 if (tunnel_rule->hash_table)
1642 rte_hash_free(tunnel_rule->hash_table);
1644 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1645 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1651 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1653 struct i40e_fdir_filter *p_fdir;
1654 struct i40e_fdir_info *fdir_info;
1656 fdir_info = &pf->fdir;
1657 /* Remove all flow director rules and hash */
1658 if (fdir_info->hash_map)
1659 rte_free(fdir_info->hash_map);
1660 if (fdir_info->hash_table)
1661 rte_hash_free(fdir_info->hash_table);
1663 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1664 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1669 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1672 * Disable by default flexible payload
1673 * for corresponding L2/L3/L4 layers.
1675 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1676 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1677 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1681 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1684 struct rte_pci_device *pci_dev;
1685 struct rte_intr_handle *intr_handle;
1687 struct i40e_filter_control_settings settings;
1688 struct rte_flow *p_flow;
1690 uint8_t aq_fail = 0;
1693 PMD_INIT_FUNC_TRACE();
1695 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1698 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1701 intr_handle = &pci_dev->intr_handle;
1703 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1705 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1707 if (hw->adapter_stopped == 0)
1708 i40e_dev_close(dev);
1710 dev->dev_ops = NULL;
1711 dev->rx_pkt_burst = NULL;
1712 dev->tx_pkt_burst = NULL;
1714 /* Clear PXE mode */
1715 i40e_clear_pxe_mode(hw);
1717 /* Unconfigure filter control */
1718 memset(&settings, 0, sizeof(settings));
1719 ret = i40e_set_filter_control(hw, &settings);
1721 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1724 /* Disable flow control */
1725 hw->fc.requested_mode = I40E_FC_NONE;
1726 i40e_set_fc(hw, &aq_fail, TRUE);
1728 /* uninitialize pf host driver */
1729 i40e_pf_host_uninit(dev);
1731 rte_free(dev->data->mac_addrs);
1732 dev->data->mac_addrs = NULL;
1734 /* disable uio intr before callback unregister */
1735 rte_intr_disable(intr_handle);
1737 /* unregister callback func to eal lib */
1739 ret = rte_intr_callback_unregister(intr_handle,
1740 i40e_dev_interrupt_handler, dev);
1743 } else if (ret != -EAGAIN) {
1745 "intr callback unregister failed: %d",
1749 i40e_msec_delay(500);
1750 } while (retries++ < 5);
1752 i40e_rm_ethtype_filter_list(pf);
1753 i40e_rm_tunnel_filter_list(pf);
1754 i40e_rm_fdir_filter_list(pf);
1756 /* Remove all flows */
1757 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1758 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1762 /* Remove all Traffic Manager configuration */
1763 i40e_tm_conf_uninit(dev);
1769 i40e_dev_configure(struct rte_eth_dev *dev)
1771 struct i40e_adapter *ad =
1772 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1773 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1778 ret = i40e_dev_sync_phy_type(hw);
1782 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1783 * bulk allocation or vector Rx preconditions we will reset it.
1785 ad->rx_bulk_alloc_allowed = true;
1786 ad->rx_vec_allowed = true;
1787 ad->tx_simple_allowed = true;
1788 ad->tx_vec_allowed = true;
1790 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1791 ret = i40e_fdir_setup(pf);
1792 if (ret != I40E_SUCCESS) {
1793 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1796 ret = i40e_fdir_configure(dev);
1798 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1802 i40e_fdir_teardown(pf);
1804 ret = i40e_dev_init_vlan(dev);
1809 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1810 * RSS setting have different requirements.
1811 * General PMD driver call sequence are NIC init, configure,
1812 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1813 * will try to lookup the VSI that specific queue belongs to if VMDQ
1814 * applicable. So, VMDQ setting has to be done before
1815 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1816 * For RSS setting, it will try to calculate actual configured RX queue
1817 * number, which will be available after rx_queue_setup(). dev_start()
1818 * function is good to place RSS setup.
1820 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1821 ret = i40e_vmdq_setup(dev);
1826 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1827 ret = i40e_dcb_setup(dev);
1829 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1834 TAILQ_INIT(&pf->flow_list);
1839 /* need to release vmdq resource if exists */
1840 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1841 i40e_vsi_release(pf->vmdq[i].vsi);
1842 pf->vmdq[i].vsi = NULL;
1847 /* need to release fdir resource if exists */
1848 i40e_fdir_teardown(pf);
1853 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1855 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1856 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1857 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1858 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1859 uint16_t msix_vect = vsi->msix_intr;
1862 for (i = 0; i < vsi->nb_qps; i++) {
1863 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1864 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1868 if (vsi->type != I40E_VSI_SRIOV) {
1869 if (!rte_intr_allow_others(intr_handle)) {
1870 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1871 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1873 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1876 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1877 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1879 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1884 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1885 vsi->user_param + (msix_vect - 1);
1887 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1888 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1890 I40E_WRITE_FLUSH(hw);
1894 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1895 int base_queue, int nb_queue,
1900 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1901 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1903 /* Bind all RX queues to allocated MSIX interrupt */
1904 for (i = 0; i < nb_queue; i++) {
1905 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1906 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1907 ((base_queue + i + 1) <<
1908 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1909 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1910 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1912 if (i == nb_queue - 1)
1913 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1914 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1917 /* Write first RX queue to Link list register as the head element */
1918 if (vsi->type != I40E_VSI_SRIOV) {
1920 i40e_calc_itr_interval(1, pf->support_multi_driver);
1922 if (msix_vect == I40E_MISC_VEC_ID) {
1923 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1925 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1927 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1929 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1932 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1934 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1936 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1938 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1945 if (msix_vect == I40E_MISC_VEC_ID) {
1947 I40E_VPINT_LNKLST0(vsi->user_param),
1949 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1951 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1953 /* num_msix_vectors_vf needs to minus irq0 */
1954 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1955 vsi->user_param + (msix_vect - 1);
1957 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1959 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1961 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1965 I40E_WRITE_FLUSH(hw);
1969 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1971 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1972 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1973 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1974 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1975 uint16_t msix_vect = vsi->msix_intr;
1976 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1977 uint16_t queue_idx = 0;
1981 for (i = 0; i < vsi->nb_qps; i++) {
1982 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1983 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1986 /* VF bind interrupt */
1987 if (vsi->type == I40E_VSI_SRIOV) {
1988 __vsi_queues_bind_intr(vsi, msix_vect,
1989 vsi->base_queue, vsi->nb_qps,
1994 /* PF & VMDq bind interrupt */
1995 if (rte_intr_dp_is_en(intr_handle)) {
1996 if (vsi->type == I40E_VSI_MAIN) {
1999 } else if (vsi->type == I40E_VSI_VMDQ2) {
2000 struct i40e_vsi *main_vsi =
2001 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2002 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2007 for (i = 0; i < vsi->nb_used_qps; i++) {
2009 if (!rte_intr_allow_others(intr_handle))
2010 /* allow to share MISC_VEC_ID */
2011 msix_vect = I40E_MISC_VEC_ID;
2013 /* no enough msix_vect, map all to one */
2014 __vsi_queues_bind_intr(vsi, msix_vect,
2015 vsi->base_queue + i,
2016 vsi->nb_used_qps - i,
2018 for (; !!record && i < vsi->nb_used_qps; i++)
2019 intr_handle->intr_vec[queue_idx + i] =
2023 /* 1:1 queue/msix_vect mapping */
2024 __vsi_queues_bind_intr(vsi, msix_vect,
2025 vsi->base_queue + i, 1,
2028 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2036 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2038 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2039 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2040 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2041 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2042 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2043 uint16_t msix_intr, i;
2045 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2046 for (i = 0; i < vsi->nb_msix; i++) {
2047 msix_intr = vsi->msix_intr + i;
2048 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2049 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2050 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2051 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2054 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2055 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2056 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2057 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2059 I40E_WRITE_FLUSH(hw);
2063 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2065 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2066 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2067 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2068 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2069 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2070 uint16_t msix_intr, i;
2072 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2073 for (i = 0; i < vsi->nb_msix; i++) {
2074 msix_intr = vsi->msix_intr + i;
2075 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2076 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2079 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2080 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2082 I40E_WRITE_FLUSH(hw);
2085 static inline uint8_t
2086 i40e_parse_link_speeds(uint16_t link_speeds)
2088 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2090 if (link_speeds & ETH_LINK_SPEED_40G)
2091 link_speed |= I40E_LINK_SPEED_40GB;
2092 if (link_speeds & ETH_LINK_SPEED_25G)
2093 link_speed |= I40E_LINK_SPEED_25GB;
2094 if (link_speeds & ETH_LINK_SPEED_20G)
2095 link_speed |= I40E_LINK_SPEED_20GB;
2096 if (link_speeds & ETH_LINK_SPEED_10G)
2097 link_speed |= I40E_LINK_SPEED_10GB;
2098 if (link_speeds & ETH_LINK_SPEED_1G)
2099 link_speed |= I40E_LINK_SPEED_1GB;
2100 if (link_speeds & ETH_LINK_SPEED_100M)
2101 link_speed |= I40E_LINK_SPEED_100MB;
2107 i40e_phy_conf_link(struct i40e_hw *hw,
2109 uint8_t force_speed,
2112 enum i40e_status_code status;
2113 struct i40e_aq_get_phy_abilities_resp phy_ab;
2114 struct i40e_aq_set_phy_config phy_conf;
2115 enum i40e_aq_phy_type cnt;
2116 uint8_t avail_speed;
2117 uint32_t phy_type_mask = 0;
2119 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2120 I40E_AQ_PHY_FLAG_PAUSE_RX |
2121 I40E_AQ_PHY_FLAG_PAUSE_RX |
2122 I40E_AQ_PHY_FLAG_LOW_POWER;
2125 /* To get phy capabilities of available speeds. */
2126 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2129 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2133 avail_speed = phy_ab.link_speed;
2135 /* To get the current phy config. */
2136 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2139 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2144 /* If link needs to go up and it is in autoneg mode the speed is OK,
2145 * no need to set up again.
2147 if (is_up && phy_ab.phy_type != 0 &&
2148 abilities & I40E_AQ_PHY_AN_ENABLED &&
2149 phy_ab.link_speed != 0)
2150 return I40E_SUCCESS;
2152 memset(&phy_conf, 0, sizeof(phy_conf));
2154 /* bits 0-2 use the values from get_phy_abilities_resp */
2156 abilities |= phy_ab.abilities & mask;
2158 phy_conf.abilities = abilities;
2160 /* If link needs to go up, but the force speed is not supported,
2161 * Warn users and config the default available speeds.
2163 if (is_up && !(force_speed & avail_speed)) {
2164 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2165 phy_conf.link_speed = avail_speed;
2167 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2170 /* PHY type mask needs to include each type except PHY type extension */
2171 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2172 phy_type_mask |= 1 << cnt;
2174 /* use get_phy_abilities_resp value for the rest */
2175 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2176 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2177 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2178 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2179 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2180 phy_conf.eee_capability = phy_ab.eee_capability;
2181 phy_conf.eeer = phy_ab.eeer_val;
2182 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2184 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2185 phy_ab.abilities, phy_ab.link_speed);
2186 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2187 phy_conf.abilities, phy_conf.link_speed);
2189 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2193 return I40E_SUCCESS;
2197 i40e_apply_link_speed(struct rte_eth_dev *dev)
2200 uint8_t abilities = 0;
2201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 struct rte_eth_conf *conf = &dev->data->dev_conf;
2204 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2205 conf->link_speeds = ETH_LINK_SPEED_40G |
2206 ETH_LINK_SPEED_25G |
2207 ETH_LINK_SPEED_20G |
2208 ETH_LINK_SPEED_10G |
2210 ETH_LINK_SPEED_100M;
2212 speed = i40e_parse_link_speeds(conf->link_speeds);
2213 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2214 I40E_AQ_PHY_AN_ENABLED |
2215 I40E_AQ_PHY_LINK_ENABLED;
2217 return i40e_phy_conf_link(hw, abilities, speed, true);
2221 i40e_dev_start(struct rte_eth_dev *dev)
2223 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2224 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225 struct i40e_vsi *main_vsi = pf->main_vsi;
2227 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2229 uint32_t intr_vector = 0;
2230 struct i40e_vsi *vsi;
2232 hw->adapter_stopped = 0;
2234 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2236 "Invalid link_speeds for port %u, autonegotiation disabled",
2237 dev->data->port_id);
2241 rte_intr_disable(intr_handle);
2243 if ((rte_intr_cap_multiple(intr_handle) ||
2244 !RTE_ETH_DEV_SRIOV(dev).active) &&
2245 dev->data->dev_conf.intr_conf.rxq != 0) {
2246 intr_vector = dev->data->nb_rx_queues;
2247 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2252 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2253 intr_handle->intr_vec =
2254 rte_zmalloc("intr_vec",
2255 dev->data->nb_rx_queues * sizeof(int),
2257 if (!intr_handle->intr_vec) {
2259 "Failed to allocate %d rx_queues intr_vec",
2260 dev->data->nb_rx_queues);
2265 /* Initialize VSI */
2266 ret = i40e_dev_rxtx_init(pf);
2267 if (ret != I40E_SUCCESS) {
2268 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2272 /* Map queues with MSIX interrupt */
2273 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2274 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2275 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2276 i40e_vsi_enable_queues_intr(main_vsi);
2278 /* Map VMDQ VSI queues with MSIX interrupt */
2279 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2280 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2281 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2282 I40E_ITR_INDEX_DEFAULT);
2283 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2286 /* enable FDIR MSIX interrupt */
2287 if (pf->fdir.fdir_vsi) {
2288 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2289 I40E_ITR_INDEX_NONE);
2290 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2293 /* Enable all queues which have been configured */
2294 ret = i40e_dev_switch_queues(pf, TRUE);
2295 if (ret != I40E_SUCCESS) {
2296 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2300 /* Enable receiving broadcast packets */
2301 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2302 if (ret != I40E_SUCCESS)
2303 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2305 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2306 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2308 if (ret != I40E_SUCCESS)
2309 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2312 /* Enable the VLAN promiscuous mode. */
2314 for (i = 0; i < pf->vf_num; i++) {
2315 vsi = pf->vfs[i].vsi;
2316 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2321 /* Enable mac loopback mode */
2322 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2323 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2324 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2325 if (ret != I40E_SUCCESS) {
2326 PMD_DRV_LOG(ERR, "fail to set loopback link");
2331 /* Apply link configure */
2332 ret = i40e_apply_link_speed(dev);
2333 if (I40E_SUCCESS != ret) {
2334 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2338 if (!rte_intr_allow_others(intr_handle)) {
2339 rte_intr_callback_unregister(intr_handle,
2340 i40e_dev_interrupt_handler,
2342 /* configure and enable device interrupt */
2343 i40e_pf_config_irq0(hw, FALSE);
2344 i40e_pf_enable_irq0(hw);
2346 if (dev->data->dev_conf.intr_conf.lsc != 0)
2348 "lsc won't enable because of no intr multiplex");
2350 ret = i40e_aq_set_phy_int_mask(hw,
2351 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2352 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2353 I40E_AQ_EVENT_MEDIA_NA), NULL);
2354 if (ret != I40E_SUCCESS)
2355 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2357 /* Call get_link_info aq commond to enable/disable LSE */
2358 i40e_dev_link_update(dev, 0);
2361 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2362 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2363 i40e_dev_alarm_handler, dev);
2365 /* enable uio intr after callback register */
2366 rte_intr_enable(intr_handle);
2369 i40e_filter_restore(pf);
2371 if (pf->tm_conf.root && !pf->tm_conf.committed)
2372 PMD_DRV_LOG(WARNING,
2373 "please call hierarchy_commit() "
2374 "before starting the port");
2376 return I40E_SUCCESS;
2379 i40e_dev_switch_queues(pf, FALSE);
2380 i40e_dev_clear_queues(dev);
2386 i40e_dev_stop(struct rte_eth_dev *dev)
2388 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390 struct i40e_vsi *main_vsi = pf->main_vsi;
2391 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2392 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2395 if (hw->adapter_stopped == 1)
2398 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2399 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2400 rte_intr_enable(intr_handle);
2403 /* Disable all queues */
2404 i40e_dev_switch_queues(pf, FALSE);
2406 /* un-map queues with interrupt registers */
2407 i40e_vsi_disable_queues_intr(main_vsi);
2408 i40e_vsi_queues_unbind_intr(main_vsi);
2410 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2411 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2412 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2415 if (pf->fdir.fdir_vsi) {
2416 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2417 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2419 /* Clear all queues and release memory */
2420 i40e_dev_clear_queues(dev);
2423 i40e_dev_set_link_down(dev);
2425 if (!rte_intr_allow_others(intr_handle))
2426 /* resume to the default handler */
2427 rte_intr_callback_register(intr_handle,
2428 i40e_dev_interrupt_handler,
2431 /* Clean datapath event and queue/vec mapping */
2432 rte_intr_efd_disable(intr_handle);
2433 if (intr_handle->intr_vec) {
2434 rte_free(intr_handle->intr_vec);
2435 intr_handle->intr_vec = NULL;
2438 /* reset hierarchy commit */
2439 pf->tm_conf.committed = false;
2441 hw->adapter_stopped = 1;
2445 i40e_dev_close(struct rte_eth_dev *dev)
2447 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2448 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2450 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2451 struct i40e_mirror_rule *p_mirror;
2456 PMD_INIT_FUNC_TRACE();
2460 /* Remove all mirror rules */
2461 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2462 ret = i40e_aq_del_mirror_rule(hw,
2463 pf->main_vsi->veb->seid,
2464 p_mirror->rule_type,
2466 p_mirror->num_entries,
2469 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2470 "status = %d, aq_err = %d.", ret,
2471 hw->aq.asq_last_status);
2473 /* remove mirror software resource anyway */
2474 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2476 pf->nb_mirror_rule--;
2479 i40e_dev_free_queues(dev);
2481 /* Disable interrupt */
2482 i40e_pf_disable_irq0(hw);
2483 rte_intr_disable(intr_handle);
2485 i40e_fdir_teardown(pf);
2487 /* shutdown and destroy the HMC */
2488 i40e_shutdown_lan_hmc(hw);
2490 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2491 i40e_vsi_release(pf->vmdq[i].vsi);
2492 pf->vmdq[i].vsi = NULL;
2497 /* release all the existing VSIs and VEBs */
2498 i40e_vsi_release(pf->main_vsi);
2500 /* shutdown the adminq */
2501 i40e_aq_queue_shutdown(hw, true);
2502 i40e_shutdown_adminq(hw);
2504 i40e_res_pool_destroy(&pf->qp_pool);
2505 i40e_res_pool_destroy(&pf->msix_pool);
2507 /* Disable flexible payload in global configuration */
2508 if (!pf->support_multi_driver)
2509 i40e_flex_payload_reg_set_default(hw);
2511 /* force a PF reset to clean anything leftover */
2512 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2513 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2514 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2515 I40E_WRITE_FLUSH(hw);
2519 * Reset PF device only to re-initialize resources in PMD layer
2522 i40e_dev_reset(struct rte_eth_dev *dev)
2526 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2527 * its VF to make them align with it. The detailed notification
2528 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2529 * To avoid unexpected behavior in VF, currently reset of PF with
2530 * SR-IOV activation is not supported. It might be supported later.
2532 if (dev->data->sriov.active)
2535 ret = eth_i40e_dev_uninit(dev);
2539 ret = eth_i40e_dev_init(dev, NULL);
2545 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 struct i40e_vsi *vsi = pf->main_vsi;
2552 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2554 if (status != I40E_SUCCESS)
2555 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2557 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2559 if (status != I40E_SUCCESS)
2560 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2565 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2567 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2568 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569 struct i40e_vsi *vsi = pf->main_vsi;
2572 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2574 if (status != I40E_SUCCESS)
2575 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2577 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2579 if (status != I40E_SUCCESS)
2580 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2584 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2586 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2587 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2588 struct i40e_vsi *vsi = pf->main_vsi;
2591 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2592 if (ret != I40E_SUCCESS)
2593 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2597 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601 struct i40e_vsi *vsi = pf->main_vsi;
2604 if (dev->data->promiscuous == 1)
2605 return; /* must remain in all_multicast mode */
2607 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2608 vsi->seid, FALSE, NULL);
2609 if (ret != I40E_SUCCESS)
2610 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2614 * Set device link up.
2617 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2619 /* re-apply link speed setting */
2620 return i40e_apply_link_speed(dev);
2624 * Set device link down.
2627 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2629 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2630 uint8_t abilities = 0;
2631 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2634 return i40e_phy_conf_link(hw, abilities, speed, false);
2637 static __rte_always_inline void
2638 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2640 /* Link status registers and values*/
2641 #define I40E_PRTMAC_LINKSTA 0x001E2420
2642 #define I40E_REG_LINK_UP 0x40000080
2643 #define I40E_PRTMAC_MACC 0x001E24E0
2644 #define I40E_REG_MACC_25GB 0x00020000
2645 #define I40E_REG_SPEED_MASK 0x38000000
2646 #define I40E_REG_SPEED_100MB 0x00000000
2647 #define I40E_REG_SPEED_1GB 0x08000000
2648 #define I40E_REG_SPEED_10GB 0x10000000
2649 #define I40E_REG_SPEED_20GB 0x20000000
2650 #define I40E_REG_SPEED_25_40GB 0x18000000
2651 uint32_t link_speed;
2654 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2655 link_speed = reg_val & I40E_REG_SPEED_MASK;
2656 reg_val &= I40E_REG_LINK_UP;
2657 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2659 if (unlikely(link->link_status == 0))
2662 /* Parse the link status */
2663 switch (link_speed) {
2664 case I40E_REG_SPEED_100MB:
2665 link->link_speed = ETH_SPEED_NUM_100M;
2667 case I40E_REG_SPEED_1GB:
2668 link->link_speed = ETH_SPEED_NUM_1G;
2670 case I40E_REG_SPEED_10GB:
2671 link->link_speed = ETH_SPEED_NUM_10G;
2673 case I40E_REG_SPEED_20GB:
2674 link->link_speed = ETH_SPEED_NUM_20G;
2676 case I40E_REG_SPEED_25_40GB:
2677 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2679 if (reg_val & I40E_REG_MACC_25GB)
2680 link->link_speed = ETH_SPEED_NUM_25G;
2682 link->link_speed = ETH_SPEED_NUM_40G;
2686 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2691 static __rte_always_inline void
2692 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2693 bool enable_lse, int wait_to_complete)
2695 #define CHECK_INTERVAL 100 /* 100ms */
2696 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2697 uint32_t rep_cnt = MAX_REPEAT_TIME;
2698 struct i40e_link_status link_status;
2701 memset(&link_status, 0, sizeof(link_status));
2704 memset(&link_status, 0, sizeof(link_status));
2706 /* Get link status information from hardware */
2707 status = i40e_aq_get_link_info(hw, enable_lse,
2708 &link_status, NULL);
2709 if (unlikely(status != I40E_SUCCESS)) {
2710 link->link_speed = ETH_SPEED_NUM_100M;
2711 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2712 PMD_DRV_LOG(ERR, "Failed to get link info");
2716 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2717 if (!wait_to_complete || link->link_status)
2720 rte_delay_ms(CHECK_INTERVAL);
2721 } while (--rep_cnt);
2723 /* Parse the link status */
2724 switch (link_status.link_speed) {
2725 case I40E_LINK_SPEED_100MB:
2726 link->link_speed = ETH_SPEED_NUM_100M;
2728 case I40E_LINK_SPEED_1GB:
2729 link->link_speed = ETH_SPEED_NUM_1G;
2731 case I40E_LINK_SPEED_10GB:
2732 link->link_speed = ETH_SPEED_NUM_10G;
2734 case I40E_LINK_SPEED_20GB:
2735 link->link_speed = ETH_SPEED_NUM_20G;
2737 case I40E_LINK_SPEED_25GB:
2738 link->link_speed = ETH_SPEED_NUM_25G;
2740 case I40E_LINK_SPEED_40GB:
2741 link->link_speed = ETH_SPEED_NUM_40G;
2744 link->link_speed = ETH_SPEED_NUM_100M;
2750 i40e_dev_link_update(struct rte_eth_dev *dev,
2751 int wait_to_complete)
2753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2754 struct rte_eth_link link;
2755 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2758 memset(&link, 0, sizeof(link));
2760 /* i40e uses full duplex only */
2761 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2762 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2763 ETH_LINK_SPEED_FIXED);
2765 if (!wait_to_complete && !enable_lse)
2766 update_link_reg(hw, &link);
2768 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2770 ret = rte_eth_linkstatus_set(dev, &link);
2771 i40e_notify_all_vfs_link_status(dev);
2776 /* Get all the statistics of a VSI */
2778 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2780 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2781 struct i40e_eth_stats *nes = &vsi->eth_stats;
2782 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2783 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2785 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2786 vsi->offset_loaded, &oes->rx_bytes,
2788 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2789 vsi->offset_loaded, &oes->rx_unicast,
2791 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2792 vsi->offset_loaded, &oes->rx_multicast,
2793 &nes->rx_multicast);
2794 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2795 vsi->offset_loaded, &oes->rx_broadcast,
2796 &nes->rx_broadcast);
2797 /* exclude CRC bytes */
2798 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2799 nes->rx_broadcast) * ETHER_CRC_LEN;
2801 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2802 &oes->rx_discards, &nes->rx_discards);
2803 /* GLV_REPC not supported */
2804 /* GLV_RMPC not supported */
2805 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2806 &oes->rx_unknown_protocol,
2807 &nes->rx_unknown_protocol);
2808 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2809 vsi->offset_loaded, &oes->tx_bytes,
2811 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2812 vsi->offset_loaded, &oes->tx_unicast,
2814 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2815 vsi->offset_loaded, &oes->tx_multicast,
2816 &nes->tx_multicast);
2817 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2818 vsi->offset_loaded, &oes->tx_broadcast,
2819 &nes->tx_broadcast);
2820 /* GLV_TDPC not supported */
2821 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2822 &oes->tx_errors, &nes->tx_errors);
2823 vsi->offset_loaded = true;
2825 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2827 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2828 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2829 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2830 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2831 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2832 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2833 nes->rx_unknown_protocol);
2834 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2835 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2836 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2837 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2838 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2839 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2840 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2845 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2848 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2849 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2851 /* Get rx/tx bytes of internal transfer packets */
2852 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2853 I40E_GLV_GORCL(hw->port),
2855 &pf->internal_stats_offset.rx_bytes,
2856 &pf->internal_stats.rx_bytes);
2858 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2859 I40E_GLV_GOTCL(hw->port),
2861 &pf->internal_stats_offset.tx_bytes,
2862 &pf->internal_stats.tx_bytes);
2863 /* Get total internal rx packet count */
2864 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2865 I40E_GLV_UPRCL(hw->port),
2867 &pf->internal_stats_offset.rx_unicast,
2868 &pf->internal_stats.rx_unicast);
2869 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2870 I40E_GLV_MPRCL(hw->port),
2872 &pf->internal_stats_offset.rx_multicast,
2873 &pf->internal_stats.rx_multicast);
2874 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2875 I40E_GLV_BPRCL(hw->port),
2877 &pf->internal_stats_offset.rx_broadcast,
2878 &pf->internal_stats.rx_broadcast);
2879 /* Get total internal tx packet count */
2880 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2881 I40E_GLV_UPTCL(hw->port),
2883 &pf->internal_stats_offset.tx_unicast,
2884 &pf->internal_stats.tx_unicast);
2885 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2886 I40E_GLV_MPTCL(hw->port),
2888 &pf->internal_stats_offset.tx_multicast,
2889 &pf->internal_stats.tx_multicast);
2890 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2891 I40E_GLV_BPTCL(hw->port),
2893 &pf->internal_stats_offset.tx_broadcast,
2894 &pf->internal_stats.tx_broadcast);
2896 /* exclude CRC size */
2897 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2898 pf->internal_stats.rx_multicast +
2899 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2901 /* Get statistics of struct i40e_eth_stats */
2902 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2903 I40E_GLPRT_GORCL(hw->port),
2904 pf->offset_loaded, &os->eth.rx_bytes,
2906 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2907 I40E_GLPRT_UPRCL(hw->port),
2908 pf->offset_loaded, &os->eth.rx_unicast,
2909 &ns->eth.rx_unicast);
2910 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2911 I40E_GLPRT_MPRCL(hw->port),
2912 pf->offset_loaded, &os->eth.rx_multicast,
2913 &ns->eth.rx_multicast);
2914 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2915 I40E_GLPRT_BPRCL(hw->port),
2916 pf->offset_loaded, &os->eth.rx_broadcast,
2917 &ns->eth.rx_broadcast);
2918 /* Workaround: CRC size should not be included in byte statistics,
2919 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2921 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2922 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2924 /* exclude internal rx bytes
2925 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2926 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2928 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2930 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2931 ns->eth.rx_bytes = 0;
2933 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2935 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2936 ns->eth.rx_unicast = 0;
2938 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2940 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2941 ns->eth.rx_multicast = 0;
2943 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2945 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2946 ns->eth.rx_broadcast = 0;
2948 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2950 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2951 pf->offset_loaded, &os->eth.rx_discards,
2952 &ns->eth.rx_discards);
2953 /* GLPRT_REPC not supported */
2954 /* GLPRT_RMPC not supported */
2955 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2957 &os->eth.rx_unknown_protocol,
2958 &ns->eth.rx_unknown_protocol);
2959 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2960 I40E_GLPRT_GOTCL(hw->port),
2961 pf->offset_loaded, &os->eth.tx_bytes,
2963 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2964 I40E_GLPRT_UPTCL(hw->port),
2965 pf->offset_loaded, &os->eth.tx_unicast,
2966 &ns->eth.tx_unicast);
2967 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2968 I40E_GLPRT_MPTCL(hw->port),
2969 pf->offset_loaded, &os->eth.tx_multicast,
2970 &ns->eth.tx_multicast);
2971 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2972 I40E_GLPRT_BPTCL(hw->port),
2973 pf->offset_loaded, &os->eth.tx_broadcast,
2974 &ns->eth.tx_broadcast);
2975 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2976 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2978 /* exclude internal tx bytes
2979 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2980 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2982 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2984 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2985 ns->eth.tx_bytes = 0;
2987 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2989 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2990 ns->eth.tx_unicast = 0;
2992 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2994 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2995 ns->eth.tx_multicast = 0;
2997 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2999 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3000 ns->eth.tx_broadcast = 0;
3002 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3004 /* GLPRT_TEPC not supported */
3006 /* additional port specific stats */
3007 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3008 pf->offset_loaded, &os->tx_dropped_link_down,
3009 &ns->tx_dropped_link_down);
3010 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3011 pf->offset_loaded, &os->crc_errors,
3013 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3014 pf->offset_loaded, &os->illegal_bytes,
3015 &ns->illegal_bytes);
3016 /* GLPRT_ERRBC not supported */
3017 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3018 pf->offset_loaded, &os->mac_local_faults,
3019 &ns->mac_local_faults);
3020 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3021 pf->offset_loaded, &os->mac_remote_faults,
3022 &ns->mac_remote_faults);
3023 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3024 pf->offset_loaded, &os->rx_length_errors,
3025 &ns->rx_length_errors);
3026 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3027 pf->offset_loaded, &os->link_xon_rx,
3029 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3030 pf->offset_loaded, &os->link_xoff_rx,
3032 for (i = 0; i < 8; i++) {
3033 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3035 &os->priority_xon_rx[i],
3036 &ns->priority_xon_rx[i]);
3037 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3039 &os->priority_xoff_rx[i],
3040 &ns->priority_xoff_rx[i]);
3042 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3043 pf->offset_loaded, &os->link_xon_tx,
3045 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3046 pf->offset_loaded, &os->link_xoff_tx,
3048 for (i = 0; i < 8; i++) {
3049 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3051 &os->priority_xon_tx[i],
3052 &ns->priority_xon_tx[i]);
3053 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3055 &os->priority_xoff_tx[i],
3056 &ns->priority_xoff_tx[i]);
3057 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3059 &os->priority_xon_2_xoff[i],
3060 &ns->priority_xon_2_xoff[i]);
3062 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3063 I40E_GLPRT_PRC64L(hw->port),
3064 pf->offset_loaded, &os->rx_size_64,
3066 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3067 I40E_GLPRT_PRC127L(hw->port),
3068 pf->offset_loaded, &os->rx_size_127,
3070 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3071 I40E_GLPRT_PRC255L(hw->port),
3072 pf->offset_loaded, &os->rx_size_255,
3074 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3075 I40E_GLPRT_PRC511L(hw->port),
3076 pf->offset_loaded, &os->rx_size_511,
3078 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3079 I40E_GLPRT_PRC1023L(hw->port),
3080 pf->offset_loaded, &os->rx_size_1023,
3082 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3083 I40E_GLPRT_PRC1522L(hw->port),
3084 pf->offset_loaded, &os->rx_size_1522,
3086 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3087 I40E_GLPRT_PRC9522L(hw->port),
3088 pf->offset_loaded, &os->rx_size_big,
3090 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3091 pf->offset_loaded, &os->rx_undersize,
3093 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3094 pf->offset_loaded, &os->rx_fragments,
3096 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3097 pf->offset_loaded, &os->rx_oversize,
3099 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3100 pf->offset_loaded, &os->rx_jabber,
3102 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3103 I40E_GLPRT_PTC64L(hw->port),
3104 pf->offset_loaded, &os->tx_size_64,
3106 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3107 I40E_GLPRT_PTC127L(hw->port),
3108 pf->offset_loaded, &os->tx_size_127,
3110 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3111 I40E_GLPRT_PTC255L(hw->port),
3112 pf->offset_loaded, &os->tx_size_255,
3114 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3115 I40E_GLPRT_PTC511L(hw->port),
3116 pf->offset_loaded, &os->tx_size_511,
3118 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3119 I40E_GLPRT_PTC1023L(hw->port),
3120 pf->offset_loaded, &os->tx_size_1023,
3122 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3123 I40E_GLPRT_PTC1522L(hw->port),
3124 pf->offset_loaded, &os->tx_size_1522,
3126 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3127 I40E_GLPRT_PTC9522L(hw->port),
3128 pf->offset_loaded, &os->tx_size_big,
3130 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3132 &os->fd_sb_match, &ns->fd_sb_match);
3133 /* GLPRT_MSPDC not supported */
3134 /* GLPRT_XEC not supported */
3136 pf->offset_loaded = true;
3139 i40e_update_vsi_stats(pf->main_vsi);
3142 /* Get all statistics of a port */
3144 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3146 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3147 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3151 /* call read registers - updates values, now write them to struct */
3152 i40e_read_stats_registers(pf, hw);
3154 stats->ipackets = ns->eth.rx_unicast +
3155 ns->eth.rx_multicast +
3156 ns->eth.rx_broadcast -
3157 ns->eth.rx_discards -
3158 pf->main_vsi->eth_stats.rx_discards;
3159 stats->opackets = ns->eth.tx_unicast +
3160 ns->eth.tx_multicast +
3161 ns->eth.tx_broadcast;
3162 stats->ibytes = ns->eth.rx_bytes;
3163 stats->obytes = ns->eth.tx_bytes;
3164 stats->oerrors = ns->eth.tx_errors +
3165 pf->main_vsi->eth_stats.tx_errors;
3168 stats->imissed = ns->eth.rx_discards +
3169 pf->main_vsi->eth_stats.rx_discards;
3170 stats->ierrors = ns->crc_errors +
3171 ns->rx_length_errors + ns->rx_undersize +
3172 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3174 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3175 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3176 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3177 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3178 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3179 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3180 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3181 ns->eth.rx_unknown_protocol);
3182 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3183 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3184 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3185 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3186 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3187 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3189 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3190 ns->tx_dropped_link_down);
3191 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3192 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3194 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3195 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3196 ns->mac_local_faults);
3197 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3198 ns->mac_remote_faults);
3199 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3200 ns->rx_length_errors);
3201 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3202 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3203 for (i = 0; i < 8; i++) {
3204 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3205 i, ns->priority_xon_rx[i]);
3206 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3207 i, ns->priority_xoff_rx[i]);
3209 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3210 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3211 for (i = 0; i < 8; i++) {
3212 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3213 i, ns->priority_xon_tx[i]);
3214 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3215 i, ns->priority_xoff_tx[i]);
3216 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3217 i, ns->priority_xon_2_xoff[i]);
3219 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3220 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3221 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3222 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3223 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3224 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3225 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3226 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3227 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3228 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3229 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3230 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3231 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3232 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3233 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3234 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3235 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3236 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3237 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3238 ns->mac_short_packet_dropped);
3239 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3240 ns->checksum_error);
3241 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3242 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3246 /* Reset the statistics */
3248 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3250 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3251 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253 /* Mark PF and VSI stats to update the offset, aka "reset" */
3254 pf->offset_loaded = false;
3256 pf->main_vsi->offset_loaded = false;
3258 /* read the stats, reading current register values into offset */
3259 i40e_read_stats_registers(pf, hw);
3263 i40e_xstats_calc_num(void)
3265 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3266 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3267 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3270 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3271 struct rte_eth_xstat_name *xstats_names,
3272 __rte_unused unsigned limit)
3277 if (xstats_names == NULL)
3278 return i40e_xstats_calc_num();
3280 /* Note: limit checked in rte_eth_xstats_names() */
3282 /* Get stats from i40e_eth_stats struct */
3283 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3284 snprintf(xstats_names[count].name,
3285 sizeof(xstats_names[count].name),
3286 "%s", rte_i40e_stats_strings[i].name);
3290 /* Get individiual stats from i40e_hw_port struct */
3291 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3292 snprintf(xstats_names[count].name,
3293 sizeof(xstats_names[count].name),
3294 "%s", rte_i40e_hw_port_strings[i].name);
3298 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3299 for (prio = 0; prio < 8; prio++) {
3300 snprintf(xstats_names[count].name,
3301 sizeof(xstats_names[count].name),
3302 "rx_priority%u_%s", prio,
3303 rte_i40e_rxq_prio_strings[i].name);
3308 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3309 for (prio = 0; prio < 8; prio++) {
3310 snprintf(xstats_names[count].name,
3311 sizeof(xstats_names[count].name),
3312 "tx_priority%u_%s", prio,
3313 rte_i40e_txq_prio_strings[i].name);
3321 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3324 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3325 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3326 unsigned i, count, prio;
3327 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3329 count = i40e_xstats_calc_num();
3333 i40e_read_stats_registers(pf, hw);
3340 /* Get stats from i40e_eth_stats struct */
3341 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3342 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3343 rte_i40e_stats_strings[i].offset);
3344 xstats[count].id = count;
3348 /* Get individiual stats from i40e_hw_port struct */
3349 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3350 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3351 rte_i40e_hw_port_strings[i].offset);
3352 xstats[count].id = count;
3356 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3357 for (prio = 0; prio < 8; prio++) {
3358 xstats[count].value =
3359 *(uint64_t *)(((char *)hw_stats) +
3360 rte_i40e_rxq_prio_strings[i].offset +
3361 (sizeof(uint64_t) * prio));
3362 xstats[count].id = count;
3367 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3368 for (prio = 0; prio < 8; prio++) {
3369 xstats[count].value =
3370 *(uint64_t *)(((char *)hw_stats) +
3371 rte_i40e_txq_prio_strings[i].offset +
3372 (sizeof(uint64_t) * prio));
3373 xstats[count].id = count;
3382 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3383 __rte_unused uint16_t queue_id,
3384 __rte_unused uint8_t stat_idx,
3385 __rte_unused uint8_t is_rx)
3387 PMD_INIT_FUNC_TRACE();
3393 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3395 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401 full_ver = hw->nvm.oem_ver;
3402 ver = (u8)(full_ver >> 24);
3403 build = (u16)((full_ver >> 8) & 0xffff);
3404 patch = (u8)(full_ver & 0xff);
3406 ret = snprintf(fw_version, fw_size,
3407 "%d.%d%d 0x%08x %d.%d.%d",
3408 ((hw->nvm.version >> 12) & 0xf),
3409 ((hw->nvm.version >> 4) & 0xff),
3410 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3413 ret += 1; /* add the size of '\0' */
3414 if (fw_size < (u32)ret)
3421 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3423 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3424 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425 struct i40e_vsi *vsi = pf->main_vsi;
3426 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3428 dev_info->max_rx_queues = vsi->nb_qps;
3429 dev_info->max_tx_queues = vsi->nb_qps;
3430 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3431 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3432 dev_info->max_mac_addrs = vsi->max_macaddrs;
3433 dev_info->max_vfs = pci_dev->max_vfs;
3434 dev_info->rx_queue_offload_capa = 0;
3435 dev_info->rx_offload_capa =
3436 DEV_RX_OFFLOAD_VLAN_STRIP |
3437 DEV_RX_OFFLOAD_QINQ_STRIP |
3438 DEV_RX_OFFLOAD_IPV4_CKSUM |
3439 DEV_RX_OFFLOAD_UDP_CKSUM |
3440 DEV_RX_OFFLOAD_TCP_CKSUM |
3441 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3442 DEV_RX_OFFLOAD_KEEP_CRC |
3443 DEV_RX_OFFLOAD_VLAN_EXTEND |
3444 DEV_RX_OFFLOAD_VLAN_FILTER |
3445 DEV_RX_OFFLOAD_JUMBO_FRAME;
3447 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3448 dev_info->tx_offload_capa =
3449 DEV_TX_OFFLOAD_VLAN_INSERT |
3450 DEV_TX_OFFLOAD_QINQ_INSERT |
3451 DEV_TX_OFFLOAD_IPV4_CKSUM |
3452 DEV_TX_OFFLOAD_UDP_CKSUM |
3453 DEV_TX_OFFLOAD_TCP_CKSUM |
3454 DEV_TX_OFFLOAD_SCTP_CKSUM |
3455 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3456 DEV_TX_OFFLOAD_TCP_TSO |
3457 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3458 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3459 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3460 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3461 DEV_TX_OFFLOAD_MULTI_SEGS |
3462 dev_info->tx_queue_offload_capa;
3463 dev_info->dev_capa =
3464 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3465 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3467 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3469 dev_info->reta_size = pf->hash_lut_size;
3470 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3472 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3474 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3475 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3476 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3478 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3483 dev_info->default_txconf = (struct rte_eth_txconf) {
3485 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3486 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3487 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3489 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3490 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3494 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3495 .nb_max = I40E_MAX_RING_DESC,
3496 .nb_min = I40E_MIN_RING_DESC,
3497 .nb_align = I40E_ALIGN_RING_DESC,
3500 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3501 .nb_max = I40E_MAX_RING_DESC,
3502 .nb_min = I40E_MIN_RING_DESC,
3503 .nb_align = I40E_ALIGN_RING_DESC,
3504 .nb_seg_max = I40E_TX_MAX_SEG,
3505 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3508 if (pf->flags & I40E_FLAG_VMDQ) {
3509 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3510 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3511 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3512 pf->max_nb_vmdq_vsi;
3513 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3514 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3515 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3518 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3520 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3521 dev_info->default_rxportconf.nb_queues = 2;
3522 dev_info->default_txportconf.nb_queues = 2;
3523 if (dev->data->nb_rx_queues == 1)
3524 dev_info->default_rxportconf.ring_size = 2048;
3526 dev_info->default_rxportconf.ring_size = 1024;
3527 if (dev->data->nb_tx_queues == 1)
3528 dev_info->default_txportconf.ring_size = 1024;
3530 dev_info->default_txportconf.ring_size = 512;
3532 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3534 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3535 dev_info->default_rxportconf.nb_queues = 1;
3536 dev_info->default_txportconf.nb_queues = 1;
3537 dev_info->default_rxportconf.ring_size = 256;
3538 dev_info->default_txportconf.ring_size = 256;
3541 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3542 dev_info->default_rxportconf.nb_queues = 1;
3543 dev_info->default_txportconf.nb_queues = 1;
3544 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3545 dev_info->default_rxportconf.ring_size = 512;
3546 dev_info->default_txportconf.ring_size = 256;
3548 dev_info->default_rxportconf.ring_size = 256;
3549 dev_info->default_txportconf.ring_size = 256;
3552 dev_info->default_rxportconf.burst_size = 32;
3553 dev_info->default_txportconf.burst_size = 32;
3557 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3559 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3560 struct i40e_vsi *vsi = pf->main_vsi;
3561 PMD_INIT_FUNC_TRACE();
3564 return i40e_vsi_add_vlan(vsi, vlan_id);
3566 return i40e_vsi_delete_vlan(vsi, vlan_id);
3570 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3571 enum rte_vlan_type vlan_type,
3572 uint16_t tpid, int qinq)
3574 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3577 uint16_t reg_id = 3;
3581 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3585 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3587 if (ret != I40E_SUCCESS) {
3589 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3594 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3597 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3598 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3599 if (reg_r == reg_w) {
3600 PMD_DRV_LOG(DEBUG, "No need to write");
3604 ret = i40e_aq_debug_write_global_register(hw,
3605 I40E_GL_SWT_L2TAGCTRL(reg_id),
3607 if (ret != I40E_SUCCESS) {
3609 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3614 "Global register 0x%08x is changed with value 0x%08x",
3615 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3621 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3622 enum rte_vlan_type vlan_type,
3625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3627 int qinq = dev->data->dev_conf.rxmode.offloads &
3628 DEV_RX_OFFLOAD_VLAN_EXTEND;
3631 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3632 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3633 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3635 "Unsupported vlan type.");
3639 if (pf->support_multi_driver) {
3640 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3644 /* 802.1ad frames ability is added in NVM API 1.7*/
3645 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3647 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3648 hw->first_tag = rte_cpu_to_le_16(tpid);
3649 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3650 hw->second_tag = rte_cpu_to_le_16(tpid);
3652 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3653 hw->second_tag = rte_cpu_to_le_16(tpid);
3655 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3656 if (ret != I40E_SUCCESS) {
3658 "Set switch config failed aq_err: %d",
3659 hw->aq.asq_last_status);
3663 /* If NVM API < 1.7, keep the register setting */
3664 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3671 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3674 struct i40e_vsi *vsi = pf->main_vsi;
3675 struct rte_eth_rxmode *rxmode;
3677 rxmode = &dev->data->dev_conf.rxmode;
3678 if (mask & ETH_VLAN_FILTER_MASK) {
3679 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3680 i40e_vsi_config_vlan_filter(vsi, TRUE);
3682 i40e_vsi_config_vlan_filter(vsi, FALSE);
3685 if (mask & ETH_VLAN_STRIP_MASK) {
3686 /* Enable or disable VLAN stripping */
3687 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3688 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3690 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3693 if (mask & ETH_VLAN_EXTEND_MASK) {
3694 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3695 i40e_vsi_config_double_vlan(vsi, TRUE);
3696 /* Set global registers with default ethertype. */
3697 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3699 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3703 i40e_vsi_config_double_vlan(vsi, FALSE);
3710 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3711 __rte_unused uint16_t queue,
3712 __rte_unused int on)
3714 PMD_INIT_FUNC_TRACE();
3718 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3720 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3721 struct i40e_vsi *vsi = pf->main_vsi;
3722 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3723 struct i40e_vsi_vlan_pvid_info info;
3725 memset(&info, 0, sizeof(info));
3728 info.config.pvid = pvid;
3730 info.config.reject.tagged =
3731 data->dev_conf.txmode.hw_vlan_reject_tagged;
3732 info.config.reject.untagged =
3733 data->dev_conf.txmode.hw_vlan_reject_untagged;
3736 return i40e_vsi_vlan_pvid_set(vsi, &info);
3740 i40e_dev_led_on(struct rte_eth_dev *dev)
3742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3743 uint32_t mode = i40e_led_get(hw);
3746 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3752 i40e_dev_led_off(struct rte_eth_dev *dev)
3754 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3755 uint32_t mode = i40e_led_get(hw);
3758 i40e_led_set(hw, 0, false);
3764 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3766 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3767 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3769 fc_conf->pause_time = pf->fc_conf.pause_time;
3771 /* read out from register, in case they are modified by other port */
3772 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3773 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3774 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3775 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3777 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3778 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3780 /* Return current mode according to actual setting*/
3781 switch (hw->fc.current_mode) {
3783 fc_conf->mode = RTE_FC_FULL;
3785 case I40E_FC_TX_PAUSE:
3786 fc_conf->mode = RTE_FC_TX_PAUSE;
3788 case I40E_FC_RX_PAUSE:
3789 fc_conf->mode = RTE_FC_RX_PAUSE;
3793 fc_conf->mode = RTE_FC_NONE;
3800 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3802 uint32_t mflcn_reg, fctrl_reg, reg;
3803 uint32_t max_high_water;
3804 uint8_t i, aq_failure;
3808 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3809 [RTE_FC_NONE] = I40E_FC_NONE,
3810 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3811 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3812 [RTE_FC_FULL] = I40E_FC_FULL
3815 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3817 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3818 if ((fc_conf->high_water > max_high_water) ||
3819 (fc_conf->high_water < fc_conf->low_water)) {
3821 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3826 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3828 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3830 pf->fc_conf.pause_time = fc_conf->pause_time;
3831 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3832 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3834 PMD_INIT_FUNC_TRACE();
3836 /* All the link flow control related enable/disable register
3837 * configuration is handle by the F/W
3839 err = i40e_set_fc(hw, &aq_failure, true);
3843 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3844 /* Configure flow control refresh threshold,
3845 * the value for stat_tx_pause_refresh_timer[8]
3846 * is used for global pause operation.
3850 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3851 pf->fc_conf.pause_time);
3853 /* configure the timer value included in transmitted pause
3855 * the value for stat_tx_pause_quanta[8] is used for global
3858 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3859 pf->fc_conf.pause_time);
3861 fctrl_reg = I40E_READ_REG(hw,
3862 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3864 if (fc_conf->mac_ctrl_frame_fwd != 0)
3865 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3867 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3869 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3872 /* Configure pause time (2 TCs per register) */
3873 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3874 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3875 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3877 /* Configure flow control refresh threshold value */
3878 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3879 pf->fc_conf.pause_time / 2);
3881 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3883 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3884 *depending on configuration
3886 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3887 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3888 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3890 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3891 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3894 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3897 if (!pf->support_multi_driver) {
3898 /* config water marker both based on the packets and bytes */
3899 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3900 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3901 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3902 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3903 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3904 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3905 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3906 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3908 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3909 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3913 "Water marker configuration is not supported.");
3916 I40E_WRITE_FLUSH(hw);
3922 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3923 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3925 PMD_INIT_FUNC_TRACE();
3930 /* Add a MAC address, and update filters */
3932 i40e_macaddr_add(struct rte_eth_dev *dev,
3933 struct ether_addr *mac_addr,
3934 __rte_unused uint32_t index,
3937 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3938 struct i40e_mac_filter_info mac_filter;
3939 struct i40e_vsi *vsi;
3940 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3943 /* If VMDQ not enabled or configured, return */
3944 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3945 !pf->nb_cfg_vmdq_vsi)) {
3946 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3947 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3952 if (pool > pf->nb_cfg_vmdq_vsi) {
3953 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3954 pool, pf->nb_cfg_vmdq_vsi);
3958 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3959 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3960 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3962 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3967 vsi = pf->vmdq[pool - 1].vsi;
3969 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3970 if (ret != I40E_SUCCESS) {
3971 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3977 /* Remove a MAC address, and update filters */
3979 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3981 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3982 struct i40e_vsi *vsi;
3983 struct rte_eth_dev_data *data = dev->data;
3984 struct ether_addr *macaddr;
3989 macaddr = &(data->mac_addrs[index]);
3991 pool_sel = dev->data->mac_pool_sel[index];
3993 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3994 if (pool_sel & (1ULL << i)) {
3998 /* No VMDQ pool enabled or configured */
3999 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4000 (i > pf->nb_cfg_vmdq_vsi)) {
4002 "No VMDQ pool enabled/configured");
4005 vsi = pf->vmdq[i - 1].vsi;
4007 ret = i40e_vsi_delete_mac(vsi, macaddr);
4010 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4017 /* Set perfect match or hash match of MAC and VLAN for a VF */
4019 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4020 struct rte_eth_mac_filter *filter,
4024 struct i40e_mac_filter_info mac_filter;
4025 struct ether_addr old_mac;
4026 struct ether_addr *new_mac;
4027 struct i40e_pf_vf *vf = NULL;
4032 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4035 hw = I40E_PF_TO_HW(pf);
4037 if (filter == NULL) {
4038 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4042 new_mac = &filter->mac_addr;
4044 if (is_zero_ether_addr(new_mac)) {
4045 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4049 vf_id = filter->dst_id;
4051 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4052 PMD_DRV_LOG(ERR, "Invalid argument.");
4055 vf = &pf->vfs[vf_id];
4057 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4058 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4063 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4064 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4066 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4069 mac_filter.filter_type = filter->filter_type;
4070 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4071 if (ret != I40E_SUCCESS) {
4072 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4075 ether_addr_copy(new_mac, &pf->dev_addr);
4077 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4079 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4080 if (ret != I40E_SUCCESS) {
4081 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4085 /* Clear device address as it has been removed */
4086 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4087 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4093 /* MAC filter handle */
4095 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4099 struct rte_eth_mac_filter *filter;
4100 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4101 int ret = I40E_NOT_SUPPORTED;
4103 filter = (struct rte_eth_mac_filter *)(arg);
4105 switch (filter_op) {
4106 case RTE_ETH_FILTER_NOP:
4109 case RTE_ETH_FILTER_ADD:
4110 i40e_pf_disable_irq0(hw);
4112 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4113 i40e_pf_enable_irq0(hw);
4115 case RTE_ETH_FILTER_DELETE:
4116 i40e_pf_disable_irq0(hw);
4118 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4119 i40e_pf_enable_irq0(hw);
4122 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4123 ret = I40E_ERR_PARAM;
4131 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4133 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4134 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4141 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4142 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4145 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4149 uint32_t *lut_dw = (uint32_t *)lut;
4150 uint16_t i, lut_size_dw = lut_size / 4;
4152 if (vsi->type == I40E_VSI_SRIOV) {
4153 for (i = 0; i <= lut_size_dw; i++) {
4154 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4155 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4158 for (i = 0; i < lut_size_dw; i++)
4159 lut_dw[i] = I40E_READ_REG(hw,
4168 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4177 pf = I40E_VSI_TO_PF(vsi);
4178 hw = I40E_VSI_TO_HW(vsi);
4180 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4181 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4184 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4188 uint32_t *lut_dw = (uint32_t *)lut;
4189 uint16_t i, lut_size_dw = lut_size / 4;
4191 if (vsi->type == I40E_VSI_SRIOV) {
4192 for (i = 0; i < lut_size_dw; i++)
4195 I40E_VFQF_HLUT1(i, vsi->user_param),
4198 for (i = 0; i < lut_size_dw; i++)
4199 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4202 I40E_WRITE_FLUSH(hw);
4209 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4210 struct rte_eth_rss_reta_entry64 *reta_conf,
4213 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4214 uint16_t i, lut_size = pf->hash_lut_size;
4215 uint16_t idx, shift;
4219 if (reta_size != lut_size ||
4220 reta_size > ETH_RSS_RETA_SIZE_512) {
4222 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4223 reta_size, lut_size);
4227 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4229 PMD_DRV_LOG(ERR, "No memory can be allocated");
4232 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4235 for (i = 0; i < reta_size; i++) {
4236 idx = i / RTE_RETA_GROUP_SIZE;
4237 shift = i % RTE_RETA_GROUP_SIZE;
4238 if (reta_conf[idx].mask & (1ULL << shift))
4239 lut[i] = reta_conf[idx].reta[shift];
4241 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4250 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4251 struct rte_eth_rss_reta_entry64 *reta_conf,
4254 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4255 uint16_t i, lut_size = pf->hash_lut_size;
4256 uint16_t idx, shift;
4260 if (reta_size != lut_size ||
4261 reta_size > ETH_RSS_RETA_SIZE_512) {
4263 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4264 reta_size, lut_size);
4268 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4270 PMD_DRV_LOG(ERR, "No memory can be allocated");
4274 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4277 for (i = 0; i < reta_size; i++) {
4278 idx = i / RTE_RETA_GROUP_SIZE;
4279 shift = i % RTE_RETA_GROUP_SIZE;
4280 if (reta_conf[idx].mask & (1ULL << shift))
4281 reta_conf[idx].reta[shift] = lut[i];
4291 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4292 * @hw: pointer to the HW structure
4293 * @mem: pointer to mem struct to fill out
4294 * @size: size of memory requested
4295 * @alignment: what to align the allocation to
4297 enum i40e_status_code
4298 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4299 struct i40e_dma_mem *mem,
4303 const struct rte_memzone *mz = NULL;
4304 char z_name[RTE_MEMZONE_NAMESIZE];
4307 return I40E_ERR_PARAM;
4309 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4310 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4311 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4313 return I40E_ERR_NO_MEMORY;
4318 mem->zone = (const void *)mz;
4320 "memzone %s allocated with physical address: %"PRIu64,
4323 return I40E_SUCCESS;
4327 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4328 * @hw: pointer to the HW structure
4329 * @mem: ptr to mem struct to free
4331 enum i40e_status_code
4332 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4333 struct i40e_dma_mem *mem)
4336 return I40E_ERR_PARAM;
4339 "memzone %s to be freed with physical address: %"PRIu64,
4340 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4341 rte_memzone_free((const struct rte_memzone *)mem->zone);
4346 return I40E_SUCCESS;
4350 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4351 * @hw: pointer to the HW structure
4352 * @mem: pointer to mem struct to fill out
4353 * @size: size of memory requested
4355 enum i40e_status_code
4356 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4357 struct i40e_virt_mem *mem,
4361 return I40E_ERR_PARAM;
4364 mem->va = rte_zmalloc("i40e", size, 0);
4367 return I40E_SUCCESS;
4369 return I40E_ERR_NO_MEMORY;
4373 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4374 * @hw: pointer to the HW structure
4375 * @mem: pointer to mem struct to free
4377 enum i40e_status_code
4378 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4379 struct i40e_virt_mem *mem)
4382 return I40E_ERR_PARAM;
4387 return I40E_SUCCESS;
4391 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4393 rte_spinlock_init(&sp->spinlock);
4397 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4399 rte_spinlock_lock(&sp->spinlock);
4403 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4405 rte_spinlock_unlock(&sp->spinlock);
4409 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4415 * Get the hardware capabilities, which will be parsed
4416 * and saved into struct i40e_hw.
4419 i40e_get_cap(struct i40e_hw *hw)
4421 struct i40e_aqc_list_capabilities_element_resp *buf;
4422 uint16_t len, size = 0;
4425 /* Calculate a huge enough buff for saving response data temporarily */
4426 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4427 I40E_MAX_CAP_ELE_NUM;
4428 buf = rte_zmalloc("i40e", len, 0);
4430 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4431 return I40E_ERR_NO_MEMORY;
4434 /* Get, parse the capabilities and save it to hw */
4435 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4436 i40e_aqc_opc_list_func_capabilities, NULL);
4437 if (ret != I40E_SUCCESS)
4438 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4440 /* Free the temporary buffer after being used */
4446 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4448 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4456 pf = (struct i40e_pf *)opaque;
4460 num = strtoul(value, &end, 0);
4461 if (errno != 0 || end == value || *end != 0) {
4462 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4463 "kept the value = %hu", value, pf->vf_nb_qp_max);
4467 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4468 pf->vf_nb_qp_max = (uint16_t)num;
4470 /* here return 0 to make next valid same argument work */
4471 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4472 "power of 2 and equal or less than 16 !, Now it is "
4473 "kept the value = %hu", num, pf->vf_nb_qp_max);
4478 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4481 struct rte_kvargs *kvlist;
4484 /* set default queue number per VF as 4 */
4485 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4487 if (dev->device->devargs == NULL)
4490 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4494 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4495 if (!kvargs_count) {
4496 rte_kvargs_free(kvlist);
4500 if (kvargs_count > 1)
4501 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4502 "the first invalid or last valid one is used !",
4503 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4505 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4506 i40e_pf_parse_vf_queue_number_handler, pf);
4508 rte_kvargs_free(kvlist);
4514 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4516 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4517 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4518 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4519 uint16_t qp_count = 0, vsi_count = 0;
4521 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4522 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4526 i40e_pf_config_vf_rxq_number(dev);
4528 /* Add the parameter init for LFC */
4529 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4530 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4531 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4533 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4534 pf->max_num_vsi = hw->func_caps.num_vsis;
4535 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4536 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4538 /* FDir queue/VSI allocation */
4539 pf->fdir_qp_offset = 0;
4540 if (hw->func_caps.fd) {
4541 pf->flags |= I40E_FLAG_FDIR;
4542 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4544 pf->fdir_nb_qps = 0;
4546 qp_count += pf->fdir_nb_qps;
4549 /* LAN queue/VSI allocation */
4550 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4551 if (!hw->func_caps.rss) {
4554 pf->flags |= I40E_FLAG_RSS;
4555 if (hw->mac.type == I40E_MAC_X722)
4556 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4557 pf->lan_nb_qps = pf->lan_nb_qp_max;
4559 qp_count += pf->lan_nb_qps;
4562 /* VF queue/VSI allocation */
4563 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4564 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4565 pf->flags |= I40E_FLAG_SRIOV;
4566 pf->vf_nb_qps = pf->vf_nb_qp_max;
4567 pf->vf_num = pci_dev->max_vfs;
4569 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4570 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4575 qp_count += pf->vf_nb_qps * pf->vf_num;
4576 vsi_count += pf->vf_num;
4578 /* VMDq queue/VSI allocation */
4579 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4580 pf->vmdq_nb_qps = 0;
4581 pf->max_nb_vmdq_vsi = 0;
4582 if (hw->func_caps.vmdq) {
4583 if (qp_count < hw->func_caps.num_tx_qp &&
4584 vsi_count < hw->func_caps.num_vsis) {
4585 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4586 qp_count) / pf->vmdq_nb_qp_max;
4588 /* Limit the maximum number of VMDq vsi to the maximum
4589 * ethdev can support
4591 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4592 hw->func_caps.num_vsis - vsi_count);
4593 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4595 if (pf->max_nb_vmdq_vsi) {
4596 pf->flags |= I40E_FLAG_VMDQ;
4597 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4599 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4600 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4601 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4604 "No enough queues left for VMDq");
4607 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4610 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4611 vsi_count += pf->max_nb_vmdq_vsi;
4613 if (hw->func_caps.dcb)
4614 pf->flags |= I40E_FLAG_DCB;
4616 if (qp_count > hw->func_caps.num_tx_qp) {
4618 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4619 qp_count, hw->func_caps.num_tx_qp);
4622 if (vsi_count > hw->func_caps.num_vsis) {
4624 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4625 vsi_count, hw->func_caps.num_vsis);
4633 i40e_pf_get_switch_config(struct i40e_pf *pf)
4635 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4636 struct i40e_aqc_get_switch_config_resp *switch_config;
4637 struct i40e_aqc_switch_config_element_resp *element;
4638 uint16_t start_seid = 0, num_reported;
4641 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4642 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4643 if (!switch_config) {
4644 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4648 /* Get the switch configurations */
4649 ret = i40e_aq_get_switch_config(hw, switch_config,
4650 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4651 if (ret != I40E_SUCCESS) {
4652 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4655 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4656 if (num_reported != 1) { /* The number should be 1 */
4657 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4661 /* Parse the switch configuration elements */
4662 element = &(switch_config->element[0]);
4663 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4664 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4665 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4667 PMD_DRV_LOG(INFO, "Unknown element type");
4670 rte_free(switch_config);
4676 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4679 struct pool_entry *entry;
4681 if (pool == NULL || num == 0)
4684 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4685 if (entry == NULL) {
4686 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4690 /* queue heap initialize */
4691 pool->num_free = num;
4692 pool->num_alloc = 0;
4694 LIST_INIT(&pool->alloc_list);
4695 LIST_INIT(&pool->free_list);
4697 /* Initialize element */
4701 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4706 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4708 struct pool_entry *entry, *next_entry;
4713 for (entry = LIST_FIRST(&pool->alloc_list);
4714 entry && (next_entry = LIST_NEXT(entry, next), 1);
4715 entry = next_entry) {
4716 LIST_REMOVE(entry, next);
4720 for (entry = LIST_FIRST(&pool->free_list);
4721 entry && (next_entry = LIST_NEXT(entry, next), 1);
4722 entry = next_entry) {
4723 LIST_REMOVE(entry, next);
4728 pool->num_alloc = 0;
4730 LIST_INIT(&pool->alloc_list);
4731 LIST_INIT(&pool->free_list);
4735 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4738 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4739 uint32_t pool_offset;
4743 PMD_DRV_LOG(ERR, "Invalid parameter");
4747 pool_offset = base - pool->base;
4748 /* Lookup in alloc list */
4749 LIST_FOREACH(entry, &pool->alloc_list, next) {
4750 if (entry->base == pool_offset) {
4751 valid_entry = entry;
4752 LIST_REMOVE(entry, next);
4757 /* Not find, return */
4758 if (valid_entry == NULL) {
4759 PMD_DRV_LOG(ERR, "Failed to find entry");
4764 * Found it, move it to free list and try to merge.
4765 * In order to make merge easier, always sort it by qbase.
4766 * Find adjacent prev and last entries.
4769 LIST_FOREACH(entry, &pool->free_list, next) {
4770 if (entry->base > valid_entry->base) {
4778 /* Try to merge with next one*/
4780 /* Merge with next one */
4781 if (valid_entry->base + valid_entry->len == next->base) {
4782 next->base = valid_entry->base;
4783 next->len += valid_entry->len;
4784 rte_free(valid_entry);
4791 /* Merge with previous one */
4792 if (prev->base + prev->len == valid_entry->base) {
4793 prev->len += valid_entry->len;
4794 /* If it merge with next one, remove next node */
4796 LIST_REMOVE(valid_entry, next);
4797 rte_free(valid_entry);
4799 rte_free(valid_entry);
4805 /* Not find any entry to merge, insert */
4808 LIST_INSERT_AFTER(prev, valid_entry, next);
4809 else if (next != NULL)
4810 LIST_INSERT_BEFORE(next, valid_entry, next);
4811 else /* It's empty list, insert to head */
4812 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4815 pool->num_free += valid_entry->len;
4816 pool->num_alloc -= valid_entry->len;
4822 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4825 struct pool_entry *entry, *valid_entry;
4827 if (pool == NULL || num == 0) {
4828 PMD_DRV_LOG(ERR, "Invalid parameter");
4832 if (pool->num_free < num) {
4833 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4834 num, pool->num_free);
4839 /* Lookup in free list and find most fit one */
4840 LIST_FOREACH(entry, &pool->free_list, next) {
4841 if (entry->len >= num) {
4843 if (entry->len == num) {
4844 valid_entry = entry;
4847 if (valid_entry == NULL || valid_entry->len > entry->len)
4848 valid_entry = entry;
4852 /* Not find one to satisfy the request, return */
4853 if (valid_entry == NULL) {
4854 PMD_DRV_LOG(ERR, "No valid entry found");
4858 * The entry have equal queue number as requested,
4859 * remove it from alloc_list.
4861 if (valid_entry->len == num) {
4862 LIST_REMOVE(valid_entry, next);
4865 * The entry have more numbers than requested,
4866 * create a new entry for alloc_list and minus its
4867 * queue base and number in free_list.
4869 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4870 if (entry == NULL) {
4872 "Failed to allocate memory for resource pool");
4875 entry->base = valid_entry->base;
4877 valid_entry->base += num;
4878 valid_entry->len -= num;
4879 valid_entry = entry;
4882 /* Insert it into alloc list, not sorted */
4883 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4885 pool->num_free -= valid_entry->len;
4886 pool->num_alloc += valid_entry->len;
4888 return valid_entry->base + pool->base;
4892 * bitmap_is_subset - Check whether src2 is subset of src1
4895 bitmap_is_subset(uint8_t src1, uint8_t src2)
4897 return !((src1 ^ src2) & src2);
4900 static enum i40e_status_code
4901 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4903 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4905 /* If DCB is not supported, only default TC is supported */
4906 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4907 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4908 return I40E_NOT_SUPPORTED;
4911 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4913 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4914 hw->func_caps.enabled_tcmap, enabled_tcmap);
4915 return I40E_NOT_SUPPORTED;
4917 return I40E_SUCCESS;
4921 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4922 struct i40e_vsi_vlan_pvid_info *info)
4925 struct i40e_vsi_context ctxt;
4926 uint8_t vlan_flags = 0;
4929 if (vsi == NULL || info == NULL) {
4930 PMD_DRV_LOG(ERR, "invalid parameters");
4931 return I40E_ERR_PARAM;
4935 vsi->info.pvid = info->config.pvid;
4937 * If insert pvid is enabled, only tagged pkts are
4938 * allowed to be sent out.
4940 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4941 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4944 if (info->config.reject.tagged == 0)
4945 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4947 if (info->config.reject.untagged == 0)
4948 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4950 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4951 I40E_AQ_VSI_PVLAN_MODE_MASK);
4952 vsi->info.port_vlan_flags |= vlan_flags;
4953 vsi->info.valid_sections =
4954 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4955 memset(&ctxt, 0, sizeof(ctxt));
4956 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4957 ctxt.seid = vsi->seid;
4959 hw = I40E_VSI_TO_HW(vsi);
4960 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4961 if (ret != I40E_SUCCESS)
4962 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4968 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4970 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4972 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4974 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4975 if (ret != I40E_SUCCESS)
4979 PMD_DRV_LOG(ERR, "seid not valid");
4983 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4984 tc_bw_data.tc_valid_bits = enabled_tcmap;
4985 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4986 tc_bw_data.tc_bw_credits[i] =
4987 (enabled_tcmap & (1 << i)) ? 1 : 0;
4989 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4990 if (ret != I40E_SUCCESS) {
4991 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4995 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4996 sizeof(vsi->info.qs_handle));
4997 return I40E_SUCCESS;
5000 static enum i40e_status_code
5001 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5002 struct i40e_aqc_vsi_properties_data *info,
5003 uint8_t enabled_tcmap)
5005 enum i40e_status_code ret;
5006 int i, total_tc = 0;
5007 uint16_t qpnum_per_tc, bsf, qp_idx;
5009 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5010 if (ret != I40E_SUCCESS)
5013 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5014 if (enabled_tcmap & (1 << i))
5018 vsi->enabled_tc = enabled_tcmap;
5020 /* Number of queues per enabled TC */
5021 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5022 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5023 bsf = rte_bsf32(qpnum_per_tc);
5025 /* Adjust the queue number to actual queues that can be applied */
5026 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5027 vsi->nb_qps = qpnum_per_tc * total_tc;
5030 * Configure TC and queue mapping parameters, for enabled TC,
5031 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5032 * default queue will serve it.
5035 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5036 if (vsi->enabled_tc & (1 << i)) {
5037 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5038 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5039 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5040 qp_idx += qpnum_per_tc;
5042 info->tc_mapping[i] = 0;
5045 /* Associate queue number with VSI */
5046 if (vsi->type == I40E_VSI_SRIOV) {
5047 info->mapping_flags |=
5048 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5049 for (i = 0; i < vsi->nb_qps; i++)
5050 info->queue_mapping[i] =
5051 rte_cpu_to_le_16(vsi->base_queue + i);
5053 info->mapping_flags |=
5054 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5055 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5057 info->valid_sections |=
5058 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5060 return I40E_SUCCESS;
5064 i40e_veb_release(struct i40e_veb *veb)
5066 struct i40e_vsi *vsi;
5072 if (!TAILQ_EMPTY(&veb->head)) {
5073 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5076 /* associate_vsi field is NULL for floating VEB */
5077 if (veb->associate_vsi != NULL) {
5078 vsi = veb->associate_vsi;
5079 hw = I40E_VSI_TO_HW(vsi);
5081 vsi->uplink_seid = veb->uplink_seid;
5084 veb->associate_pf->main_vsi->floating_veb = NULL;
5085 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5088 i40e_aq_delete_element(hw, veb->seid, NULL);
5090 return I40E_SUCCESS;
5094 static struct i40e_veb *
5095 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5097 struct i40e_veb *veb;
5103 "veb setup failed, associated PF shouldn't null");
5106 hw = I40E_PF_TO_HW(pf);
5108 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5110 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5114 veb->associate_vsi = vsi;
5115 veb->associate_pf = pf;
5116 TAILQ_INIT(&veb->head);
5117 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5119 /* create floating veb if vsi is NULL */
5121 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5122 I40E_DEFAULT_TCMAP, false,
5123 &veb->seid, false, NULL);
5125 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5126 true, &veb->seid, false, NULL);
5129 if (ret != I40E_SUCCESS) {
5130 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5131 hw->aq.asq_last_status);
5134 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5136 /* get statistics index */
5137 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5138 &veb->stats_idx, NULL, NULL, NULL);
5139 if (ret != I40E_SUCCESS) {
5140 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5141 hw->aq.asq_last_status);
5144 /* Get VEB bandwidth, to be implemented */
5145 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5147 vsi->uplink_seid = veb->seid;
5156 i40e_vsi_release(struct i40e_vsi *vsi)
5160 struct i40e_vsi_list *vsi_list;
5163 struct i40e_mac_filter *f;
5164 uint16_t user_param;
5167 return I40E_SUCCESS;
5172 user_param = vsi->user_param;
5174 pf = I40E_VSI_TO_PF(vsi);
5175 hw = I40E_VSI_TO_HW(vsi);
5177 /* VSI has child to attach, release child first */
5179 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5180 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5183 i40e_veb_release(vsi->veb);
5186 if (vsi->floating_veb) {
5187 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5188 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5193 /* Remove all macvlan filters of the VSI */
5194 i40e_vsi_remove_all_macvlan_filter(vsi);
5195 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5198 if (vsi->type != I40E_VSI_MAIN &&
5199 ((vsi->type != I40E_VSI_SRIOV) ||
5200 !pf->floating_veb_list[user_param])) {
5201 /* Remove vsi from parent's sibling list */
5202 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5203 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5204 return I40E_ERR_PARAM;
5206 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5207 &vsi->sib_vsi_list, list);
5209 /* Remove all switch element of the VSI */
5210 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5211 if (ret != I40E_SUCCESS)
5212 PMD_DRV_LOG(ERR, "Failed to delete element");
5215 if ((vsi->type == I40E_VSI_SRIOV) &&
5216 pf->floating_veb_list[user_param]) {
5217 /* Remove vsi from parent's sibling list */
5218 if (vsi->parent_vsi == NULL ||
5219 vsi->parent_vsi->floating_veb == NULL) {
5220 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5221 return I40E_ERR_PARAM;
5223 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5224 &vsi->sib_vsi_list, list);
5226 /* Remove all switch element of the VSI */
5227 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5228 if (ret != I40E_SUCCESS)
5229 PMD_DRV_LOG(ERR, "Failed to delete element");
5232 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5234 if (vsi->type != I40E_VSI_SRIOV)
5235 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5238 return I40E_SUCCESS;
5242 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5244 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5245 struct i40e_aqc_remove_macvlan_element_data def_filter;
5246 struct i40e_mac_filter_info filter;
5249 if (vsi->type != I40E_VSI_MAIN)
5250 return I40E_ERR_CONFIG;
5251 memset(&def_filter, 0, sizeof(def_filter));
5252 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5254 def_filter.vlan_tag = 0;
5255 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5256 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5257 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5258 if (ret != I40E_SUCCESS) {
5259 struct i40e_mac_filter *f;
5260 struct ether_addr *mac;
5263 "Cannot remove the default macvlan filter");
5264 /* It needs to add the permanent mac into mac list */
5265 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5267 PMD_DRV_LOG(ERR, "failed to allocate memory");
5268 return I40E_ERR_NO_MEMORY;
5270 mac = &f->mac_info.mac_addr;
5271 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5273 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5274 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5279 rte_memcpy(&filter.mac_addr,
5280 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5281 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5282 return i40e_vsi_add_mac(vsi, &filter);
5286 * i40e_vsi_get_bw_config - Query VSI BW Information
5287 * @vsi: the VSI to be queried
5289 * Returns 0 on success, negative value on failure
5291 static enum i40e_status_code
5292 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5294 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5295 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5296 struct i40e_hw *hw = &vsi->adapter->hw;
5301 memset(&bw_config, 0, sizeof(bw_config));
5302 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5303 if (ret != I40E_SUCCESS) {
5304 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5305 hw->aq.asq_last_status);
5309 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5310 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5311 &ets_sla_config, NULL);
5312 if (ret != I40E_SUCCESS) {
5314 "VSI failed to get TC bandwdith configuration %u",
5315 hw->aq.asq_last_status);
5319 /* store and print out BW info */
5320 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5321 vsi->bw_info.bw_max = bw_config.max_bw;
5322 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5323 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5324 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5325 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5327 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5328 vsi->bw_info.bw_ets_share_credits[i] =
5329 ets_sla_config.share_credits[i];
5330 vsi->bw_info.bw_ets_credits[i] =
5331 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5332 /* 4 bits per TC, 4th bit is reserved */
5333 vsi->bw_info.bw_ets_max[i] =
5334 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5335 RTE_LEN2MASK(3, uint8_t));
5336 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5337 vsi->bw_info.bw_ets_share_credits[i]);
5338 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5339 vsi->bw_info.bw_ets_credits[i]);
5340 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5341 vsi->bw_info.bw_ets_max[i]);
5344 return I40E_SUCCESS;
5347 /* i40e_enable_pf_lb
5348 * @pf: pointer to the pf structure
5350 * allow loopback on pf
5353 i40e_enable_pf_lb(struct i40e_pf *pf)
5355 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5356 struct i40e_vsi_context ctxt;
5359 /* Use the FW API if FW >= v5.0 */
5360 if (hw->aq.fw_maj_ver < 5) {
5361 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5365 memset(&ctxt, 0, sizeof(ctxt));
5366 ctxt.seid = pf->main_vsi_seid;
5367 ctxt.pf_num = hw->pf_id;
5368 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5370 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5371 ret, hw->aq.asq_last_status);
5374 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5375 ctxt.info.valid_sections =
5376 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5377 ctxt.info.switch_id |=
5378 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5380 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5382 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5383 hw->aq.asq_last_status);
5388 i40e_vsi_setup(struct i40e_pf *pf,
5389 enum i40e_vsi_type type,
5390 struct i40e_vsi *uplink_vsi,
5391 uint16_t user_param)
5393 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5394 struct i40e_vsi *vsi;
5395 struct i40e_mac_filter_info filter;
5397 struct i40e_vsi_context ctxt;
5398 struct ether_addr broadcast =
5399 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5401 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5402 uplink_vsi == NULL) {
5404 "VSI setup failed, VSI link shouldn't be NULL");
5408 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5410 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5415 * 1.type is not MAIN and uplink vsi is not NULL
5416 * If uplink vsi didn't setup VEB, create one first under veb field
5417 * 2.type is SRIOV and the uplink is NULL
5418 * If floating VEB is NULL, create one veb under floating veb field
5421 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5422 uplink_vsi->veb == NULL) {
5423 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5425 if (uplink_vsi->veb == NULL) {
5426 PMD_DRV_LOG(ERR, "VEB setup failed");
5429 /* set ALLOWLOOPBACk on pf, when veb is created */
5430 i40e_enable_pf_lb(pf);
5433 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5434 pf->main_vsi->floating_veb == NULL) {
5435 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5437 if (pf->main_vsi->floating_veb == NULL) {
5438 PMD_DRV_LOG(ERR, "VEB setup failed");
5443 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5445 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5448 TAILQ_INIT(&vsi->mac_list);
5450 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5451 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5452 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5453 vsi->user_param = user_param;
5454 vsi->vlan_anti_spoof_on = 0;
5455 vsi->vlan_filter_on = 0;
5456 /* Allocate queues */
5457 switch (vsi->type) {
5458 case I40E_VSI_MAIN :
5459 vsi->nb_qps = pf->lan_nb_qps;
5461 case I40E_VSI_SRIOV :
5462 vsi->nb_qps = pf->vf_nb_qps;
5464 case I40E_VSI_VMDQ2:
5465 vsi->nb_qps = pf->vmdq_nb_qps;
5468 vsi->nb_qps = pf->fdir_nb_qps;
5474 * The filter status descriptor is reported in rx queue 0,
5475 * while the tx queue for fdir filter programming has no
5476 * such constraints, can be non-zero queues.
5477 * To simplify it, choose FDIR vsi use queue 0 pair.
5478 * To make sure it will use queue 0 pair, queue allocation
5479 * need be done before this function is called
5481 if (type != I40E_VSI_FDIR) {
5482 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5484 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5488 vsi->base_queue = ret;
5490 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5492 /* VF has MSIX interrupt in VF range, don't allocate here */
5493 if (type == I40E_VSI_MAIN) {
5494 if (pf->support_multi_driver) {
5495 /* If support multi-driver, need to use INT0 instead of
5496 * allocating from msix pool. The Msix pool is init from
5497 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5498 * to 1 without calling i40e_res_pool_alloc.
5503 ret = i40e_res_pool_alloc(&pf->msix_pool,
5504 RTE_MIN(vsi->nb_qps,
5505 RTE_MAX_RXTX_INTR_VEC_ID));
5508 "VSI MAIN %d get heap failed %d",
5510 goto fail_queue_alloc;
5512 vsi->msix_intr = ret;
5513 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5514 RTE_MAX_RXTX_INTR_VEC_ID);
5516 } else if (type != I40E_VSI_SRIOV) {
5517 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5519 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5520 goto fail_queue_alloc;
5522 vsi->msix_intr = ret;
5530 if (type == I40E_VSI_MAIN) {
5531 /* For main VSI, no need to add since it's default one */
5532 vsi->uplink_seid = pf->mac_seid;
5533 vsi->seid = pf->main_vsi_seid;
5534 /* Bind queues with specific MSIX interrupt */
5536 * Needs 2 interrupt at least, one for misc cause which will
5537 * enabled from OS side, Another for queues binding the
5538 * interrupt from device side only.
5541 /* Get default VSI parameters from hardware */
5542 memset(&ctxt, 0, sizeof(ctxt));
5543 ctxt.seid = vsi->seid;
5544 ctxt.pf_num = hw->pf_id;
5545 ctxt.uplink_seid = vsi->uplink_seid;
5547 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5548 if (ret != I40E_SUCCESS) {
5549 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5550 goto fail_msix_alloc;
5552 rte_memcpy(&vsi->info, &ctxt.info,
5553 sizeof(struct i40e_aqc_vsi_properties_data));
5554 vsi->vsi_id = ctxt.vsi_number;
5555 vsi->info.valid_sections = 0;
5557 /* Configure tc, enabled TC0 only */
5558 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5560 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5561 goto fail_msix_alloc;
5564 /* TC, queue mapping */
5565 memset(&ctxt, 0, sizeof(ctxt));
5566 vsi->info.valid_sections |=
5567 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5568 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5569 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5570 rte_memcpy(&ctxt.info, &vsi->info,
5571 sizeof(struct i40e_aqc_vsi_properties_data));
5572 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5573 I40E_DEFAULT_TCMAP);
5574 if (ret != I40E_SUCCESS) {
5576 "Failed to configure TC queue mapping");
5577 goto fail_msix_alloc;
5579 ctxt.seid = vsi->seid;
5580 ctxt.pf_num = hw->pf_id;
5581 ctxt.uplink_seid = vsi->uplink_seid;
5584 /* Update VSI parameters */
5585 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5586 if (ret != I40E_SUCCESS) {
5587 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5588 goto fail_msix_alloc;
5591 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5592 sizeof(vsi->info.tc_mapping));
5593 rte_memcpy(&vsi->info.queue_mapping,
5594 &ctxt.info.queue_mapping,
5595 sizeof(vsi->info.queue_mapping));
5596 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5597 vsi->info.valid_sections = 0;
5599 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5603 * Updating default filter settings are necessary to prevent
5604 * reception of tagged packets.
5605 * Some old firmware configurations load a default macvlan
5606 * filter which accepts both tagged and untagged packets.
5607 * The updating is to use a normal filter instead if needed.
5608 * For NVM 4.2.2 or after, the updating is not needed anymore.
5609 * The firmware with correct configurations load the default
5610 * macvlan filter which is expected and cannot be removed.
5612 i40e_update_default_filter_setting(vsi);
5613 i40e_config_qinq(hw, vsi);
5614 } else if (type == I40E_VSI_SRIOV) {
5615 memset(&ctxt, 0, sizeof(ctxt));
5617 * For other VSI, the uplink_seid equals to uplink VSI's
5618 * uplink_seid since they share same VEB
5620 if (uplink_vsi == NULL)
5621 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5623 vsi->uplink_seid = uplink_vsi->uplink_seid;
5624 ctxt.pf_num = hw->pf_id;
5625 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5626 ctxt.uplink_seid = vsi->uplink_seid;
5627 ctxt.connection_type = 0x1;
5628 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5630 /* Use the VEB configuration if FW >= v5.0 */
5631 if (hw->aq.fw_maj_ver >= 5) {
5632 /* Configure switch ID */
5633 ctxt.info.valid_sections |=
5634 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5635 ctxt.info.switch_id =
5636 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5639 /* Configure port/vlan */
5640 ctxt.info.valid_sections |=
5641 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5642 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5643 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5644 hw->func_caps.enabled_tcmap);
5645 if (ret != I40E_SUCCESS) {
5647 "Failed to configure TC queue mapping");
5648 goto fail_msix_alloc;
5651 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5652 ctxt.info.valid_sections |=
5653 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5655 * Since VSI is not created yet, only configure parameter,
5656 * will add vsi below.
5659 i40e_config_qinq(hw, vsi);
5660 } else if (type == I40E_VSI_VMDQ2) {
5661 memset(&ctxt, 0, sizeof(ctxt));
5663 * For other VSI, the uplink_seid equals to uplink VSI's
5664 * uplink_seid since they share same VEB
5666 vsi->uplink_seid = uplink_vsi->uplink_seid;
5667 ctxt.pf_num = hw->pf_id;
5669 ctxt.uplink_seid = vsi->uplink_seid;
5670 ctxt.connection_type = 0x1;
5671 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5673 ctxt.info.valid_sections |=
5674 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5675 /* user_param carries flag to enable loop back */
5677 ctxt.info.switch_id =
5678 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5679 ctxt.info.switch_id |=
5680 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5683 /* Configure port/vlan */
5684 ctxt.info.valid_sections |=
5685 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5686 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5687 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5688 I40E_DEFAULT_TCMAP);
5689 if (ret != I40E_SUCCESS) {
5691 "Failed to configure TC queue mapping");
5692 goto fail_msix_alloc;
5694 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5695 ctxt.info.valid_sections |=
5696 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5697 } else if (type == I40E_VSI_FDIR) {
5698 memset(&ctxt, 0, sizeof(ctxt));
5699 vsi->uplink_seid = uplink_vsi->uplink_seid;
5700 ctxt.pf_num = hw->pf_id;
5702 ctxt.uplink_seid = vsi->uplink_seid;
5703 ctxt.connection_type = 0x1; /* regular data port */
5704 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5705 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5706 I40E_DEFAULT_TCMAP);
5707 if (ret != I40E_SUCCESS) {
5709 "Failed to configure TC queue mapping.");
5710 goto fail_msix_alloc;
5712 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5713 ctxt.info.valid_sections |=
5714 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5716 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5717 goto fail_msix_alloc;
5720 if (vsi->type != I40E_VSI_MAIN) {
5721 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5722 if (ret != I40E_SUCCESS) {
5723 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5724 hw->aq.asq_last_status);
5725 goto fail_msix_alloc;
5727 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5728 vsi->info.valid_sections = 0;
5729 vsi->seid = ctxt.seid;
5730 vsi->vsi_id = ctxt.vsi_number;
5731 vsi->sib_vsi_list.vsi = vsi;
5732 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5733 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5734 &vsi->sib_vsi_list, list);
5736 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5737 &vsi->sib_vsi_list, list);
5741 /* MAC/VLAN configuration */
5742 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5743 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5745 ret = i40e_vsi_add_mac(vsi, &filter);
5746 if (ret != I40E_SUCCESS) {
5747 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5748 goto fail_msix_alloc;
5751 /* Get VSI BW information */
5752 i40e_vsi_get_bw_config(vsi);
5755 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5757 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5763 /* Configure vlan filter on or off */
5765 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5768 struct i40e_mac_filter *f;
5770 struct i40e_mac_filter_info *mac_filter;
5771 enum rte_mac_filter_type desired_filter;
5772 int ret = I40E_SUCCESS;
5775 /* Filter to match MAC and VLAN */
5776 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5778 /* Filter to match only MAC */
5779 desired_filter = RTE_MAC_PERFECT_MATCH;
5784 mac_filter = rte_zmalloc("mac_filter_info_data",
5785 num * sizeof(*mac_filter), 0);
5786 if (mac_filter == NULL) {
5787 PMD_DRV_LOG(ERR, "failed to allocate memory");
5788 return I40E_ERR_NO_MEMORY;
5793 /* Remove all existing mac */
5794 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5795 mac_filter[i] = f->mac_info;
5796 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5798 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5799 on ? "enable" : "disable");
5805 /* Override with new filter */
5806 for (i = 0; i < num; i++) {
5807 mac_filter[i].filter_type = desired_filter;
5808 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5810 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5811 on ? "enable" : "disable");
5817 rte_free(mac_filter);
5821 /* Configure vlan stripping on or off */
5823 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5825 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5826 struct i40e_vsi_context ctxt;
5828 int ret = I40E_SUCCESS;
5830 /* Check if it has been already on or off */
5831 if (vsi->info.valid_sections &
5832 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5834 if ((vsi->info.port_vlan_flags &
5835 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5836 return 0; /* already on */
5838 if ((vsi->info.port_vlan_flags &
5839 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5840 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5841 return 0; /* already off */
5846 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5848 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5849 vsi->info.valid_sections =
5850 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5851 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5852 vsi->info.port_vlan_flags |= vlan_flags;
5853 ctxt.seid = vsi->seid;
5854 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5855 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5857 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5858 on ? "enable" : "disable");
5864 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5866 struct rte_eth_dev_data *data = dev->data;
5870 /* Apply vlan offload setting */
5871 mask = ETH_VLAN_STRIP_MASK |
5872 ETH_VLAN_FILTER_MASK |
5873 ETH_VLAN_EXTEND_MASK;
5874 ret = i40e_vlan_offload_set(dev, mask);
5876 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5880 /* Apply pvid setting */
5881 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5882 data->dev_conf.txmode.hw_vlan_insert_pvid);
5884 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5890 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5892 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5894 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5898 i40e_update_flow_control(struct i40e_hw *hw)
5900 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5901 struct i40e_link_status link_status;
5902 uint32_t rxfc = 0, txfc = 0, reg;
5906 memset(&link_status, 0, sizeof(link_status));
5907 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5908 if (ret != I40E_SUCCESS) {
5909 PMD_DRV_LOG(ERR, "Failed to get link status information");
5910 goto write_reg; /* Disable flow control */
5913 an_info = hw->phy.link_info.an_info;
5914 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5915 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5916 ret = I40E_ERR_NOT_READY;
5917 goto write_reg; /* Disable flow control */
5920 * If link auto negotiation is enabled, flow control needs to
5921 * be configured according to it
5923 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5924 case I40E_LINK_PAUSE_RXTX:
5927 hw->fc.current_mode = I40E_FC_FULL;
5929 case I40E_AQ_LINK_PAUSE_RX:
5931 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5933 case I40E_AQ_LINK_PAUSE_TX:
5935 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5938 hw->fc.current_mode = I40E_FC_NONE;
5943 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5944 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5945 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5946 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5947 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5948 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5955 i40e_pf_setup(struct i40e_pf *pf)
5957 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5958 struct i40e_filter_control_settings settings;
5959 struct i40e_vsi *vsi;
5962 /* Clear all stats counters */
5963 pf->offset_loaded = FALSE;
5964 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5965 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5966 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5967 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5969 ret = i40e_pf_get_switch_config(pf);
5970 if (ret != I40E_SUCCESS) {
5971 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5975 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5977 PMD_INIT_LOG(WARNING,
5978 "failed to allocate switch domain for device %d", ret);
5980 if (pf->flags & I40E_FLAG_FDIR) {
5981 /* make queue allocated first, let FDIR use queue pair 0*/
5982 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5983 if (ret != I40E_FDIR_QUEUE_ID) {
5985 "queue allocation fails for FDIR: ret =%d",
5987 pf->flags &= ~I40E_FLAG_FDIR;
5990 /* main VSI setup */
5991 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5993 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5994 return I40E_ERR_NOT_READY;
5998 /* Configure filter control */
5999 memset(&settings, 0, sizeof(settings));
6000 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6001 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6002 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6003 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6005 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6006 hw->func_caps.rss_table_size);
6007 return I40E_ERR_PARAM;
6009 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6010 hw->func_caps.rss_table_size);
6011 pf->hash_lut_size = hw->func_caps.rss_table_size;
6013 /* Enable ethtype and macvlan filters */
6014 settings.enable_ethtype = TRUE;
6015 settings.enable_macvlan = TRUE;
6016 ret = i40e_set_filter_control(hw, &settings);
6018 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6021 /* Update flow control according to the auto negotiation */
6022 i40e_update_flow_control(hw);
6024 return I40E_SUCCESS;
6028 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6034 * Set or clear TX Queue Disable flags,
6035 * which is required by hardware.
6037 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6038 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6040 /* Wait until the request is finished */
6041 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6042 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6043 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6044 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6045 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6051 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6052 return I40E_SUCCESS; /* already on, skip next steps */
6054 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6055 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6057 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6058 return I40E_SUCCESS; /* already off, skip next steps */
6059 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6061 /* Write the register */
6062 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6063 /* Check the result */
6064 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6065 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6066 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6068 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6069 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6072 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6073 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6077 /* Check if it is timeout */
6078 if (j >= I40E_CHK_Q_ENA_COUNT) {
6079 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6080 (on ? "enable" : "disable"), q_idx);
6081 return I40E_ERR_TIMEOUT;
6084 return I40E_SUCCESS;
6087 /* Swith on or off the tx queues */
6089 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6091 struct rte_eth_dev_data *dev_data = pf->dev_data;
6092 struct i40e_tx_queue *txq;
6093 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6097 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6098 txq = dev_data->tx_queues[i];
6099 /* Don't operate the queue if not configured or
6100 * if starting only per queue */
6101 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6104 ret = i40e_dev_tx_queue_start(dev, i);
6106 ret = i40e_dev_tx_queue_stop(dev, i);
6107 if ( ret != I40E_SUCCESS)
6111 return I40E_SUCCESS;
6115 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6120 /* Wait until the request is finished */
6121 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6122 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6123 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6124 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6125 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6130 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6131 return I40E_SUCCESS; /* Already on, skip next steps */
6132 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6134 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6135 return I40E_SUCCESS; /* Already off, skip next steps */
6136 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6139 /* Write the register */
6140 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6141 /* Check the result */
6142 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6143 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6144 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6146 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6147 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6150 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6151 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6156 /* Check if it is timeout */
6157 if (j >= I40E_CHK_Q_ENA_COUNT) {
6158 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6159 (on ? "enable" : "disable"), q_idx);
6160 return I40E_ERR_TIMEOUT;
6163 return I40E_SUCCESS;
6165 /* Switch on or off the rx queues */
6167 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6169 struct rte_eth_dev_data *dev_data = pf->dev_data;
6170 struct i40e_rx_queue *rxq;
6171 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6175 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6176 rxq = dev_data->rx_queues[i];
6177 /* Don't operate the queue if not configured or
6178 * if starting only per queue */
6179 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6182 ret = i40e_dev_rx_queue_start(dev, i);
6184 ret = i40e_dev_rx_queue_stop(dev, i);
6185 if (ret != I40E_SUCCESS)
6189 return I40E_SUCCESS;
6192 /* Switch on or off all the rx/tx queues */
6194 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6199 /* enable rx queues before enabling tx queues */
6200 ret = i40e_dev_switch_rx_queues(pf, on);
6202 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6205 ret = i40e_dev_switch_tx_queues(pf, on);
6207 /* Stop tx queues before stopping rx queues */
6208 ret = i40e_dev_switch_tx_queues(pf, on);
6210 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6213 ret = i40e_dev_switch_rx_queues(pf, on);
6219 /* Initialize VSI for TX */
6221 i40e_dev_tx_init(struct i40e_pf *pf)
6223 struct rte_eth_dev_data *data = pf->dev_data;
6225 uint32_t ret = I40E_SUCCESS;
6226 struct i40e_tx_queue *txq;
6228 for (i = 0; i < data->nb_tx_queues; i++) {
6229 txq = data->tx_queues[i];
6230 if (!txq || !txq->q_set)
6232 ret = i40e_tx_queue_init(txq);
6233 if (ret != I40E_SUCCESS)
6236 if (ret == I40E_SUCCESS)
6237 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6243 /* Initialize VSI for RX */
6245 i40e_dev_rx_init(struct i40e_pf *pf)
6247 struct rte_eth_dev_data *data = pf->dev_data;
6248 int ret = I40E_SUCCESS;
6250 struct i40e_rx_queue *rxq;
6252 i40e_pf_config_mq_rx(pf);
6253 for (i = 0; i < data->nb_rx_queues; i++) {
6254 rxq = data->rx_queues[i];
6255 if (!rxq || !rxq->q_set)
6258 ret = i40e_rx_queue_init(rxq);
6259 if (ret != I40E_SUCCESS) {
6261 "Failed to do RX queue initialization");
6265 if (ret == I40E_SUCCESS)
6266 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6273 i40e_dev_rxtx_init(struct i40e_pf *pf)
6277 err = i40e_dev_tx_init(pf);
6279 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6282 err = i40e_dev_rx_init(pf);
6284 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6292 i40e_vmdq_setup(struct rte_eth_dev *dev)
6294 struct rte_eth_conf *conf = &dev->data->dev_conf;
6295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6296 int i, err, conf_vsis, j, loop;
6297 struct i40e_vsi *vsi;
6298 struct i40e_vmdq_info *vmdq_info;
6299 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6300 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6303 * Disable interrupt to avoid message from VF. Furthermore, it will
6304 * avoid race condition in VSI creation/destroy.
6306 i40e_pf_disable_irq0(hw);
6308 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6309 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6313 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6314 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6315 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6316 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6317 pf->max_nb_vmdq_vsi);
6321 if (pf->vmdq != NULL) {
6322 PMD_INIT_LOG(INFO, "VMDQ already configured");
6326 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6327 sizeof(*vmdq_info) * conf_vsis, 0);
6329 if (pf->vmdq == NULL) {
6330 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6334 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6336 /* Create VMDQ VSI */
6337 for (i = 0; i < conf_vsis; i++) {
6338 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6339 vmdq_conf->enable_loop_back);
6341 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6345 vmdq_info = &pf->vmdq[i];
6347 vmdq_info->vsi = vsi;
6349 pf->nb_cfg_vmdq_vsi = conf_vsis;
6351 /* Configure Vlan */
6352 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6353 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6354 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6355 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6356 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6357 vmdq_conf->pool_map[i].vlan_id, j);
6359 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6360 vmdq_conf->pool_map[i].vlan_id);
6362 PMD_INIT_LOG(ERR, "Failed to add vlan");
6370 i40e_pf_enable_irq0(hw);
6375 for (i = 0; i < conf_vsis; i++)
6376 if (pf->vmdq[i].vsi == NULL)
6379 i40e_vsi_release(pf->vmdq[i].vsi);
6383 i40e_pf_enable_irq0(hw);
6388 i40e_stat_update_32(struct i40e_hw *hw,
6396 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6400 if (new_data >= *offset)
6401 *stat = (uint64_t)(new_data - *offset);
6403 *stat = (uint64_t)((new_data +
6404 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6408 i40e_stat_update_48(struct i40e_hw *hw,
6417 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6418 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6419 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6424 if (new_data >= *offset)
6425 *stat = new_data - *offset;
6427 *stat = (uint64_t)((new_data +
6428 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6430 *stat &= I40E_48_BIT_MASK;
6435 i40e_pf_disable_irq0(struct i40e_hw *hw)
6437 /* Disable all interrupt types */
6438 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6439 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6440 I40E_WRITE_FLUSH(hw);
6445 i40e_pf_enable_irq0(struct i40e_hw *hw)
6447 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6448 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6449 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6450 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6451 I40E_WRITE_FLUSH(hw);
6455 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6457 /* read pending request and disable first */
6458 i40e_pf_disable_irq0(hw);
6459 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6460 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6461 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6464 /* Link no queues with irq0 */
6465 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6466 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6470 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6472 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6476 uint32_t index, offset, val;
6481 * Try to find which VF trigger a reset, use absolute VF id to access
6482 * since the reg is global register.
6484 for (i = 0; i < pf->vf_num; i++) {
6485 abs_vf_id = hw->func_caps.vf_base_id + i;
6486 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6487 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6488 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6489 /* VFR event occurred */
6490 if (val & (0x1 << offset)) {
6493 /* Clear the event first */
6494 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6496 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6498 * Only notify a VF reset event occurred,
6499 * don't trigger another SW reset
6501 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6502 if (ret != I40E_SUCCESS)
6503 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6509 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6511 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6514 for (i = 0; i < pf->vf_num; i++)
6515 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6519 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6521 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6522 struct i40e_arq_event_info info;
6523 uint16_t pending, opcode;
6526 info.buf_len = I40E_AQ_BUF_SZ;
6527 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6528 if (!info.msg_buf) {
6529 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6535 ret = i40e_clean_arq_element(hw, &info, &pending);
6537 if (ret != I40E_SUCCESS) {
6539 "Failed to read msg from AdminQ, aq_err: %u",
6540 hw->aq.asq_last_status);
6543 opcode = rte_le_to_cpu_16(info.desc.opcode);
6546 case i40e_aqc_opc_send_msg_to_pf:
6547 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6548 i40e_pf_host_handle_vf_msg(dev,
6549 rte_le_to_cpu_16(info.desc.retval),
6550 rte_le_to_cpu_32(info.desc.cookie_high),
6551 rte_le_to_cpu_32(info.desc.cookie_low),
6555 case i40e_aqc_opc_get_link_status:
6556 ret = i40e_dev_link_update(dev, 0);
6558 _rte_eth_dev_callback_process(dev,
6559 RTE_ETH_EVENT_INTR_LSC, NULL);
6562 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6567 rte_free(info.msg_buf);
6571 * Interrupt handler triggered by NIC for handling
6572 * specific interrupt.
6575 * Pointer to interrupt handle.
6577 * The address of parameter (struct rte_eth_dev *) regsitered before.
6583 i40e_dev_interrupt_handler(void *param)
6585 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6589 /* Disable interrupt */
6590 i40e_pf_disable_irq0(hw);
6592 /* read out interrupt causes */
6593 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6595 /* No interrupt event indicated */
6596 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6597 PMD_DRV_LOG(INFO, "No interrupt event");
6600 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6601 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6602 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6603 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6604 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6605 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6606 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6607 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6608 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6609 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6610 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6611 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6612 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6613 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6615 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6616 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6617 i40e_dev_handle_vfr_event(dev);
6619 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6620 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6621 i40e_dev_handle_aq_msg(dev);
6625 /* Enable interrupt */
6626 i40e_pf_enable_irq0(hw);
6627 rte_intr_enable(dev->intr_handle);
6631 i40e_dev_alarm_handler(void *param)
6633 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6637 /* Disable interrupt */
6638 i40e_pf_disable_irq0(hw);
6640 /* read out interrupt causes */
6641 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6643 /* No interrupt event indicated */
6644 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6645 PMD_DRV_LOG(INFO, "No interrupt event");
6648 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6649 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6650 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6651 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6652 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6653 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6654 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6655 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6656 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6657 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6658 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6659 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6660 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6661 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6663 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6664 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6665 i40e_dev_handle_vfr_event(dev);
6667 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6668 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6669 i40e_dev_handle_aq_msg(dev);
6673 /* Enable interrupt */
6674 i40e_pf_enable_irq0(hw);
6675 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6676 i40e_dev_alarm_handler, dev);
6680 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6681 struct i40e_macvlan_filter *filter,
6684 int ele_num, ele_buff_size;
6685 int num, actual_num, i;
6687 int ret = I40E_SUCCESS;
6688 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6689 struct i40e_aqc_add_macvlan_element_data *req_list;
6691 if (filter == NULL || total == 0)
6692 return I40E_ERR_PARAM;
6693 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6694 ele_buff_size = hw->aq.asq_buf_size;
6696 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6697 if (req_list == NULL) {
6698 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6699 return I40E_ERR_NO_MEMORY;
6704 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6705 memset(req_list, 0, ele_buff_size);
6707 for (i = 0; i < actual_num; i++) {
6708 rte_memcpy(req_list[i].mac_addr,
6709 &filter[num + i].macaddr, ETH_ADDR_LEN);
6710 req_list[i].vlan_tag =
6711 rte_cpu_to_le_16(filter[num + i].vlan_id);
6713 switch (filter[num + i].filter_type) {
6714 case RTE_MAC_PERFECT_MATCH:
6715 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6716 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6718 case RTE_MACVLAN_PERFECT_MATCH:
6719 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6721 case RTE_MAC_HASH_MATCH:
6722 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6723 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6725 case RTE_MACVLAN_HASH_MATCH:
6726 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6729 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6730 ret = I40E_ERR_PARAM;
6734 req_list[i].queue_number = 0;
6736 req_list[i].flags = rte_cpu_to_le_16(flags);
6739 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6741 if (ret != I40E_SUCCESS) {
6742 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6746 } while (num < total);
6754 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6755 struct i40e_macvlan_filter *filter,
6758 int ele_num, ele_buff_size;
6759 int num, actual_num, i;
6761 int ret = I40E_SUCCESS;
6762 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6763 struct i40e_aqc_remove_macvlan_element_data *req_list;
6765 if (filter == NULL || total == 0)
6766 return I40E_ERR_PARAM;
6768 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6769 ele_buff_size = hw->aq.asq_buf_size;
6771 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6772 if (req_list == NULL) {
6773 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6774 return I40E_ERR_NO_MEMORY;
6779 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6780 memset(req_list, 0, ele_buff_size);
6782 for (i = 0; i < actual_num; i++) {
6783 rte_memcpy(req_list[i].mac_addr,
6784 &filter[num + i].macaddr, ETH_ADDR_LEN);
6785 req_list[i].vlan_tag =
6786 rte_cpu_to_le_16(filter[num + i].vlan_id);
6788 switch (filter[num + i].filter_type) {
6789 case RTE_MAC_PERFECT_MATCH:
6790 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6791 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6793 case RTE_MACVLAN_PERFECT_MATCH:
6794 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6796 case RTE_MAC_HASH_MATCH:
6797 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6798 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6800 case RTE_MACVLAN_HASH_MATCH:
6801 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6804 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6805 ret = I40E_ERR_PARAM;
6808 req_list[i].flags = rte_cpu_to_le_16(flags);
6811 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6813 if (ret != I40E_SUCCESS) {
6814 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6818 } while (num < total);
6825 /* Find out specific MAC filter */
6826 static struct i40e_mac_filter *
6827 i40e_find_mac_filter(struct i40e_vsi *vsi,
6828 struct ether_addr *macaddr)
6830 struct i40e_mac_filter *f;
6832 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6833 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6841 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6844 uint32_t vid_idx, vid_bit;
6846 if (vlan_id > ETH_VLAN_ID_MAX)
6849 vid_idx = I40E_VFTA_IDX(vlan_id);
6850 vid_bit = I40E_VFTA_BIT(vlan_id);
6852 if (vsi->vfta[vid_idx] & vid_bit)
6859 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6860 uint16_t vlan_id, bool on)
6862 uint32_t vid_idx, vid_bit;
6864 vid_idx = I40E_VFTA_IDX(vlan_id);
6865 vid_bit = I40E_VFTA_BIT(vlan_id);
6868 vsi->vfta[vid_idx] |= vid_bit;
6870 vsi->vfta[vid_idx] &= ~vid_bit;
6874 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6875 uint16_t vlan_id, bool on)
6877 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6878 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6881 if (vlan_id > ETH_VLAN_ID_MAX)
6884 i40e_store_vlan_filter(vsi, vlan_id, on);
6886 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6889 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6892 ret = i40e_aq_add_vlan(hw, vsi->seid,
6893 &vlan_data, 1, NULL);
6894 if (ret != I40E_SUCCESS)
6895 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6897 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6898 &vlan_data, 1, NULL);
6899 if (ret != I40E_SUCCESS)
6901 "Failed to remove vlan filter");
6906 * Find all vlan options for specific mac addr,
6907 * return with actual vlan found.
6910 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6911 struct i40e_macvlan_filter *mv_f,
6912 int num, struct ether_addr *addr)
6918 * Not to use i40e_find_vlan_filter to decrease the loop time,
6919 * although the code looks complex.
6921 if (num < vsi->vlan_num)
6922 return I40E_ERR_PARAM;
6925 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6927 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6928 if (vsi->vfta[j] & (1 << k)) {
6931 "vlan number doesn't match");
6932 return I40E_ERR_PARAM;
6934 rte_memcpy(&mv_f[i].macaddr,
6935 addr, ETH_ADDR_LEN);
6937 j * I40E_UINT32_BIT_SIZE + k;
6943 return I40E_SUCCESS;
6947 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6948 struct i40e_macvlan_filter *mv_f,
6953 struct i40e_mac_filter *f;
6955 if (num < vsi->mac_num)
6956 return I40E_ERR_PARAM;
6958 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6960 PMD_DRV_LOG(ERR, "buffer number not match");
6961 return I40E_ERR_PARAM;
6963 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6965 mv_f[i].vlan_id = vlan;
6966 mv_f[i].filter_type = f->mac_info.filter_type;
6970 return I40E_SUCCESS;
6974 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6977 struct i40e_mac_filter *f;
6978 struct i40e_macvlan_filter *mv_f;
6979 int ret = I40E_SUCCESS;
6981 if (vsi == NULL || vsi->mac_num == 0)
6982 return I40E_ERR_PARAM;
6984 /* Case that no vlan is set */
6985 if (vsi->vlan_num == 0)
6988 num = vsi->mac_num * vsi->vlan_num;
6990 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6992 PMD_DRV_LOG(ERR, "failed to allocate memory");
6993 return I40E_ERR_NO_MEMORY;
6997 if (vsi->vlan_num == 0) {
6998 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6999 rte_memcpy(&mv_f[i].macaddr,
7000 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7001 mv_f[i].filter_type = f->mac_info.filter_type;
7002 mv_f[i].vlan_id = 0;
7006 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7007 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7008 vsi->vlan_num, &f->mac_info.mac_addr);
7009 if (ret != I40E_SUCCESS)
7011 for (j = i; j < i + vsi->vlan_num; j++)
7012 mv_f[j].filter_type = f->mac_info.filter_type;
7017 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7025 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7027 struct i40e_macvlan_filter *mv_f;
7029 int ret = I40E_SUCCESS;
7031 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7032 return I40E_ERR_PARAM;
7034 /* If it's already set, just return */
7035 if (i40e_find_vlan_filter(vsi,vlan))
7036 return I40E_SUCCESS;
7038 mac_num = vsi->mac_num;
7041 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7042 return I40E_ERR_PARAM;
7045 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7048 PMD_DRV_LOG(ERR, "failed to allocate memory");
7049 return I40E_ERR_NO_MEMORY;
7052 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7054 if (ret != I40E_SUCCESS)
7057 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7059 if (ret != I40E_SUCCESS)
7062 i40e_set_vlan_filter(vsi, vlan, 1);
7072 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7074 struct i40e_macvlan_filter *mv_f;
7076 int ret = I40E_SUCCESS;
7079 * Vlan 0 is the generic filter for untagged packets
7080 * and can't be removed.
7082 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7083 return I40E_ERR_PARAM;
7085 /* If can't find it, just return */
7086 if (!i40e_find_vlan_filter(vsi, vlan))
7087 return I40E_ERR_PARAM;
7089 mac_num = vsi->mac_num;
7092 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7093 return I40E_ERR_PARAM;
7096 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7099 PMD_DRV_LOG(ERR, "failed to allocate memory");
7100 return I40E_ERR_NO_MEMORY;
7103 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7105 if (ret != I40E_SUCCESS)
7108 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7110 if (ret != I40E_SUCCESS)
7113 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7114 if (vsi->vlan_num == 1) {
7115 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7116 if (ret != I40E_SUCCESS)
7119 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7120 if (ret != I40E_SUCCESS)
7124 i40e_set_vlan_filter(vsi, vlan, 0);
7134 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7136 struct i40e_mac_filter *f;
7137 struct i40e_macvlan_filter *mv_f;
7138 int i, vlan_num = 0;
7139 int ret = I40E_SUCCESS;
7141 /* If it's add and we've config it, return */
7142 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7144 return I40E_SUCCESS;
7145 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7146 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7149 * If vlan_num is 0, that's the first time to add mac,
7150 * set mask for vlan_id 0.
7152 if (vsi->vlan_num == 0) {
7153 i40e_set_vlan_filter(vsi, 0, 1);
7156 vlan_num = vsi->vlan_num;
7157 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7158 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7161 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7163 PMD_DRV_LOG(ERR, "failed to allocate memory");
7164 return I40E_ERR_NO_MEMORY;
7167 for (i = 0; i < vlan_num; i++) {
7168 mv_f[i].filter_type = mac_filter->filter_type;
7169 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7173 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7174 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7175 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7176 &mac_filter->mac_addr);
7177 if (ret != I40E_SUCCESS)
7181 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7182 if (ret != I40E_SUCCESS)
7185 /* Add the mac addr into mac list */
7186 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7188 PMD_DRV_LOG(ERR, "failed to allocate memory");
7189 ret = I40E_ERR_NO_MEMORY;
7192 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7194 f->mac_info.filter_type = mac_filter->filter_type;
7195 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7206 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7208 struct i40e_mac_filter *f;
7209 struct i40e_macvlan_filter *mv_f;
7211 enum rte_mac_filter_type filter_type;
7212 int ret = I40E_SUCCESS;
7214 /* Can't find it, return an error */
7215 f = i40e_find_mac_filter(vsi, addr);
7217 return I40E_ERR_PARAM;
7219 vlan_num = vsi->vlan_num;
7220 filter_type = f->mac_info.filter_type;
7221 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7222 filter_type == RTE_MACVLAN_HASH_MATCH) {
7223 if (vlan_num == 0) {
7224 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7225 return I40E_ERR_PARAM;
7227 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7228 filter_type == RTE_MAC_HASH_MATCH)
7231 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7233 PMD_DRV_LOG(ERR, "failed to allocate memory");
7234 return I40E_ERR_NO_MEMORY;
7237 for (i = 0; i < vlan_num; i++) {
7238 mv_f[i].filter_type = filter_type;
7239 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7242 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7243 filter_type == RTE_MACVLAN_HASH_MATCH) {
7244 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7245 if (ret != I40E_SUCCESS)
7249 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7250 if (ret != I40E_SUCCESS)
7253 /* Remove the mac addr into mac list */
7254 TAILQ_REMOVE(&vsi->mac_list, f, next);
7264 /* Configure hash enable flags for RSS */
7266 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7274 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7275 if (flags & (1ULL << i))
7276 hena |= adapter->pctypes_tbl[i];
7282 /* Parse the hash enable flags */
7284 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7286 uint64_t rss_hf = 0;
7292 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7293 if (flags & adapter->pctypes_tbl[i])
7294 rss_hf |= (1ULL << i);
7301 i40e_pf_disable_rss(struct i40e_pf *pf)
7303 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7305 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7306 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7307 I40E_WRITE_FLUSH(hw);
7311 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7313 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7314 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7315 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7316 I40E_VFQF_HKEY_MAX_INDEX :
7317 I40E_PFQF_HKEY_MAX_INDEX;
7320 if (!key || key_len == 0) {
7321 PMD_DRV_LOG(DEBUG, "No key to be configured");
7323 } else if (key_len != (key_idx + 1) *
7325 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7329 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7330 struct i40e_aqc_get_set_rss_key_data *key_dw =
7331 (struct i40e_aqc_get_set_rss_key_data *)key;
7333 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7335 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7337 uint32_t *hash_key = (uint32_t *)key;
7340 if (vsi->type == I40E_VSI_SRIOV) {
7341 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7344 I40E_VFQF_HKEY1(i, vsi->user_param),
7348 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7349 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7352 I40E_WRITE_FLUSH(hw);
7359 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7361 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7362 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7366 if (!key || !key_len)
7369 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7370 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7371 (struct i40e_aqc_get_set_rss_key_data *)key);
7373 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7377 uint32_t *key_dw = (uint32_t *)key;
7380 if (vsi->type == I40E_VSI_SRIOV) {
7381 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7382 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7383 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7385 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7388 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7389 reg = I40E_PFQF_HKEY(i);
7390 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7392 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7400 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7402 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7406 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7407 rss_conf->rss_key_len);
7411 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7412 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7413 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7414 I40E_WRITE_FLUSH(hw);
7420 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7421 struct rte_eth_rss_conf *rss_conf)
7423 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7424 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7425 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7428 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7429 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7431 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7432 if (rss_hf != 0) /* Enable RSS */
7434 return 0; /* Nothing to do */
7437 if (rss_hf == 0) /* Disable RSS */
7440 return i40e_hw_rss_hash_set(pf, rss_conf);
7444 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7445 struct rte_eth_rss_conf *rss_conf)
7447 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7448 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7451 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7452 &rss_conf->rss_key_len);
7454 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7455 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7456 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7462 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7464 switch (filter_type) {
7465 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7466 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7468 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7469 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7471 case RTE_TUNNEL_FILTER_IMAC_TENID:
7472 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7474 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7475 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7477 case ETH_TUNNEL_FILTER_IMAC:
7478 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7480 case ETH_TUNNEL_FILTER_OIP:
7481 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7483 case ETH_TUNNEL_FILTER_IIP:
7484 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7487 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7494 /* Convert tunnel filter structure */
7496 i40e_tunnel_filter_convert(
7497 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7498 struct i40e_tunnel_filter *tunnel_filter)
7500 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7501 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7502 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7503 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7504 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7505 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7506 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7507 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7508 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7510 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7511 tunnel_filter->input.flags = cld_filter->element.flags;
7512 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7513 tunnel_filter->queue = cld_filter->element.queue_number;
7514 rte_memcpy(tunnel_filter->input.general_fields,
7515 cld_filter->general_fields,
7516 sizeof(cld_filter->general_fields));
7521 /* Check if there exists the tunnel filter */
7522 struct i40e_tunnel_filter *
7523 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7524 const struct i40e_tunnel_filter_input *input)
7528 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7532 return tunnel_rule->hash_map[ret];
7535 /* Add a tunnel filter into the SW list */
7537 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7538 struct i40e_tunnel_filter *tunnel_filter)
7540 struct i40e_tunnel_rule *rule = &pf->tunnel;
7543 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7546 "Failed to insert tunnel filter to hash table %d!",
7550 rule->hash_map[ret] = tunnel_filter;
7552 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7557 /* Delete a tunnel filter from the SW list */
7559 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7560 struct i40e_tunnel_filter_input *input)
7562 struct i40e_tunnel_rule *rule = &pf->tunnel;
7563 struct i40e_tunnel_filter *tunnel_filter;
7566 ret = rte_hash_del_key(rule->hash_table, input);
7569 "Failed to delete tunnel filter to hash table %d!",
7573 tunnel_filter = rule->hash_map[ret];
7574 rule->hash_map[ret] = NULL;
7576 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7577 rte_free(tunnel_filter);
7583 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7584 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7588 uint32_t ipv4_addr, ipv4_addr_le;
7589 uint8_t i, tun_type = 0;
7590 /* internal varialbe to convert ipv6 byte order */
7591 uint32_t convert_ipv6[4];
7593 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7594 struct i40e_vsi *vsi = pf->main_vsi;
7595 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7596 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7597 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7598 struct i40e_tunnel_filter *tunnel, *node;
7599 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7601 cld_filter = rte_zmalloc("tunnel_filter",
7602 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7605 if (NULL == cld_filter) {
7606 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7609 pfilter = cld_filter;
7611 ether_addr_copy(&tunnel_filter->outer_mac,
7612 (struct ether_addr *)&pfilter->element.outer_mac);
7613 ether_addr_copy(&tunnel_filter->inner_mac,
7614 (struct ether_addr *)&pfilter->element.inner_mac);
7616 pfilter->element.inner_vlan =
7617 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7618 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7619 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7620 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7621 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7622 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7624 sizeof(pfilter->element.ipaddr.v4.data));
7626 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7627 for (i = 0; i < 4; i++) {
7629 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7631 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7633 sizeof(pfilter->element.ipaddr.v6.data));
7636 /* check tunneled type */
7637 switch (tunnel_filter->tunnel_type) {
7638 case RTE_TUNNEL_TYPE_VXLAN:
7639 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7641 case RTE_TUNNEL_TYPE_NVGRE:
7642 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7644 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7645 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7648 /* Other tunnel types is not supported. */
7649 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7650 rte_free(cld_filter);
7654 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7655 &pfilter->element.flags);
7657 rte_free(cld_filter);
7661 pfilter->element.flags |= rte_cpu_to_le_16(
7662 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7663 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7664 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7665 pfilter->element.queue_number =
7666 rte_cpu_to_le_16(tunnel_filter->queue_id);
7668 /* Check if there is the filter in SW list */
7669 memset(&check_filter, 0, sizeof(check_filter));
7670 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7671 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7673 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7674 rte_free(cld_filter);
7678 if (!add && !node) {
7679 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7680 rte_free(cld_filter);
7685 ret = i40e_aq_add_cloud_filters(hw,
7686 vsi->seid, &cld_filter->element, 1);
7688 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7689 rte_free(cld_filter);
7692 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7693 if (tunnel == NULL) {
7694 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7695 rte_free(cld_filter);
7699 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7700 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7704 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7705 &cld_filter->element, 1);
7707 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7708 rte_free(cld_filter);
7711 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7714 rte_free(cld_filter);
7718 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7719 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7720 #define I40E_TR_GENEVE_KEY_MASK 0x8
7721 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7722 #define I40E_TR_GRE_KEY_MASK 0x400
7723 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7724 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7727 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7729 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7730 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7731 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7732 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7733 enum i40e_status_code status = I40E_SUCCESS;
7735 if (pf->support_multi_driver) {
7736 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7737 return I40E_NOT_SUPPORTED;
7740 memset(&filter_replace, 0,
7741 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7742 memset(&filter_replace_buf, 0,
7743 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7745 /* create L1 filter */
7746 filter_replace.old_filter_type =
7747 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7748 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7749 filter_replace.tr_bit = 0;
7751 /* Prepare the buffer, 3 entries */
7752 filter_replace_buf.data[0] =
7753 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7754 filter_replace_buf.data[0] |=
7755 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7756 filter_replace_buf.data[2] = 0xFF;
7757 filter_replace_buf.data[3] = 0xFF;
7758 filter_replace_buf.data[4] =
7759 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7760 filter_replace_buf.data[4] |=
7761 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7762 filter_replace_buf.data[7] = 0xF0;
7763 filter_replace_buf.data[8]
7764 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7765 filter_replace_buf.data[8] |=
7766 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7767 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7768 I40E_TR_GENEVE_KEY_MASK |
7769 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7770 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7771 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7772 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7774 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7775 &filter_replace_buf);
7776 if (!status && (filter_replace.old_filter_type !=
7777 filter_replace.new_filter_type))
7778 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7779 " original: 0x%x, new: 0x%x",
7781 filter_replace.old_filter_type,
7782 filter_replace.new_filter_type);
7788 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7790 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7791 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7792 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7793 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7794 enum i40e_status_code status = I40E_SUCCESS;
7796 if (pf->support_multi_driver) {
7797 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7798 return I40E_NOT_SUPPORTED;
7802 memset(&filter_replace, 0,
7803 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7804 memset(&filter_replace_buf, 0,
7805 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7806 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7807 I40E_AQC_MIRROR_CLOUD_FILTER;
7808 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7809 filter_replace.new_filter_type =
7810 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7811 /* Prepare the buffer, 2 entries */
7812 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7813 filter_replace_buf.data[0] |=
7814 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7815 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7816 filter_replace_buf.data[4] |=
7817 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7818 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7819 &filter_replace_buf);
7822 if (filter_replace.old_filter_type !=
7823 filter_replace.new_filter_type)
7824 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7825 " original: 0x%x, new: 0x%x",
7827 filter_replace.old_filter_type,
7828 filter_replace.new_filter_type);
7831 memset(&filter_replace, 0,
7832 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7833 memset(&filter_replace_buf, 0,
7834 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7836 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7837 I40E_AQC_MIRROR_CLOUD_FILTER;
7838 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7839 filter_replace.new_filter_type =
7840 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7841 /* Prepare the buffer, 2 entries */
7842 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7843 filter_replace_buf.data[0] |=
7844 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7845 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7846 filter_replace_buf.data[4] |=
7847 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7849 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7850 &filter_replace_buf);
7851 if (!status && (filter_replace.old_filter_type !=
7852 filter_replace.new_filter_type))
7853 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7854 " original: 0x%x, new: 0x%x",
7856 filter_replace.old_filter_type,
7857 filter_replace.new_filter_type);
7862 static enum i40e_status_code
7863 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7865 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7866 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7867 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7868 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7869 enum i40e_status_code status = I40E_SUCCESS;
7871 if (pf->support_multi_driver) {
7872 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7873 return I40E_NOT_SUPPORTED;
7877 memset(&filter_replace, 0,
7878 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7879 memset(&filter_replace_buf, 0,
7880 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7881 /* create L1 filter */
7882 filter_replace.old_filter_type =
7883 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7884 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7885 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7886 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7887 /* Prepare the buffer, 2 entries */
7888 filter_replace_buf.data[0] =
7889 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7890 filter_replace_buf.data[0] |=
7891 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7892 filter_replace_buf.data[2] = 0xFF;
7893 filter_replace_buf.data[3] = 0xFF;
7894 filter_replace_buf.data[4] =
7895 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7896 filter_replace_buf.data[4] |=
7897 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7898 filter_replace_buf.data[6] = 0xFF;
7899 filter_replace_buf.data[7] = 0xFF;
7900 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7901 &filter_replace_buf);
7904 if (filter_replace.old_filter_type !=
7905 filter_replace.new_filter_type)
7906 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7907 " original: 0x%x, new: 0x%x",
7909 filter_replace.old_filter_type,
7910 filter_replace.new_filter_type);
7913 memset(&filter_replace, 0,
7914 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7915 memset(&filter_replace_buf, 0,
7916 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7917 /* create L1 filter */
7918 filter_replace.old_filter_type =
7919 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7920 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7921 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7922 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7923 /* Prepare the buffer, 2 entries */
7924 filter_replace_buf.data[0] =
7925 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7926 filter_replace_buf.data[0] |=
7927 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7928 filter_replace_buf.data[2] = 0xFF;
7929 filter_replace_buf.data[3] = 0xFF;
7930 filter_replace_buf.data[4] =
7931 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7932 filter_replace_buf.data[4] |=
7933 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7934 filter_replace_buf.data[6] = 0xFF;
7935 filter_replace_buf.data[7] = 0xFF;
7937 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7938 &filter_replace_buf);
7939 if (!status && (filter_replace.old_filter_type !=
7940 filter_replace.new_filter_type))
7941 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7942 " original: 0x%x, new: 0x%x",
7944 filter_replace.old_filter_type,
7945 filter_replace.new_filter_type);
7951 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7953 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7954 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7955 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7956 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7957 enum i40e_status_code status = I40E_SUCCESS;
7959 if (pf->support_multi_driver) {
7960 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7961 return I40E_NOT_SUPPORTED;
7965 memset(&filter_replace, 0,
7966 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7967 memset(&filter_replace_buf, 0,
7968 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7969 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7970 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7971 filter_replace.new_filter_type =
7972 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7973 /* Prepare the buffer, 2 entries */
7974 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7975 filter_replace_buf.data[0] |=
7976 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7977 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7978 filter_replace_buf.data[4] |=
7979 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7980 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7981 &filter_replace_buf);
7984 if (filter_replace.old_filter_type !=
7985 filter_replace.new_filter_type)
7986 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7987 " original: 0x%x, new: 0x%x",
7989 filter_replace.old_filter_type,
7990 filter_replace.new_filter_type);
7993 memset(&filter_replace, 0,
7994 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7995 memset(&filter_replace_buf, 0,
7996 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7997 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7998 filter_replace.old_filter_type =
7999 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8000 filter_replace.new_filter_type =
8001 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8002 /* Prepare the buffer, 2 entries */
8003 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8004 filter_replace_buf.data[0] |=
8005 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8006 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8007 filter_replace_buf.data[4] |=
8008 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8010 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8011 &filter_replace_buf);
8012 if (!status && (filter_replace.old_filter_type !=
8013 filter_replace.new_filter_type))
8014 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8015 " original: 0x%x, new: 0x%x",
8017 filter_replace.old_filter_type,
8018 filter_replace.new_filter_type);
8024 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8025 struct i40e_tunnel_filter_conf *tunnel_filter,
8029 uint32_t ipv4_addr, ipv4_addr_le;
8030 uint8_t i, tun_type = 0;
8031 /* internal variable to convert ipv6 byte order */
8032 uint32_t convert_ipv6[4];
8034 struct i40e_pf_vf *vf = NULL;
8035 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8036 struct i40e_vsi *vsi;
8037 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
8038 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
8039 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8040 struct i40e_tunnel_filter *tunnel, *node;
8041 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8043 bool big_buffer = 0;
8045 cld_filter = rte_zmalloc("tunnel_filter",
8046 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8049 if (cld_filter == NULL) {
8050 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8053 pfilter = cld_filter;
8055 ether_addr_copy(&tunnel_filter->outer_mac,
8056 (struct ether_addr *)&pfilter->element.outer_mac);
8057 ether_addr_copy(&tunnel_filter->inner_mac,
8058 (struct ether_addr *)&pfilter->element.inner_mac);
8060 pfilter->element.inner_vlan =
8061 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8062 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8063 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8064 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8065 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8066 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8068 sizeof(pfilter->element.ipaddr.v4.data));
8070 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8071 for (i = 0; i < 4; i++) {
8073 rte_cpu_to_le_32(rte_be_to_cpu_32(
8074 tunnel_filter->ip_addr.ipv6_addr[i]));
8076 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8078 sizeof(pfilter->element.ipaddr.v6.data));
8081 /* check tunneled type */
8082 switch (tunnel_filter->tunnel_type) {
8083 case I40E_TUNNEL_TYPE_VXLAN:
8084 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8086 case I40E_TUNNEL_TYPE_NVGRE:
8087 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8089 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8090 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8092 case I40E_TUNNEL_TYPE_MPLSoUDP:
8093 if (!pf->mpls_replace_flag) {
8094 i40e_replace_mpls_l1_filter(pf);
8095 i40e_replace_mpls_cloud_filter(pf);
8096 pf->mpls_replace_flag = 1;
8098 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8099 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8101 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8102 (teid_le & 0xF) << 12;
8103 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8106 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8108 case I40E_TUNNEL_TYPE_MPLSoGRE:
8109 if (!pf->mpls_replace_flag) {
8110 i40e_replace_mpls_l1_filter(pf);
8111 i40e_replace_mpls_cloud_filter(pf);
8112 pf->mpls_replace_flag = 1;
8114 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8115 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8117 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8118 (teid_le & 0xF) << 12;
8119 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8122 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8124 case I40E_TUNNEL_TYPE_GTPC:
8125 if (!pf->gtp_replace_flag) {
8126 i40e_replace_gtp_l1_filter(pf);
8127 i40e_replace_gtp_cloud_filter(pf);
8128 pf->gtp_replace_flag = 1;
8130 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8131 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8132 (teid_le >> 16) & 0xFFFF;
8133 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8135 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8139 case I40E_TUNNEL_TYPE_GTPU:
8140 if (!pf->gtp_replace_flag) {
8141 i40e_replace_gtp_l1_filter(pf);
8142 i40e_replace_gtp_cloud_filter(pf);
8143 pf->gtp_replace_flag = 1;
8145 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8146 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8147 (teid_le >> 16) & 0xFFFF;
8148 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8150 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8154 case I40E_TUNNEL_TYPE_QINQ:
8155 if (!pf->qinq_replace_flag) {
8156 ret = i40e_cloud_filter_qinq_create(pf);
8159 "QinQ tunnel filter already created.");
8160 pf->qinq_replace_flag = 1;
8162 /* Add in the General fields the values of
8163 * the Outer and Inner VLAN
8164 * Big Buffer should be set, see changes in
8165 * i40e_aq_add_cloud_filters
8167 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8168 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8172 /* Other tunnel types is not supported. */
8173 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8174 rte_free(cld_filter);
8178 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8179 pfilter->element.flags =
8180 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8181 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8182 pfilter->element.flags =
8183 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8184 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8185 pfilter->element.flags =
8186 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8187 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8188 pfilter->element.flags =
8189 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8190 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8191 pfilter->element.flags |=
8192 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8194 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8195 &pfilter->element.flags);
8197 rte_free(cld_filter);
8202 pfilter->element.flags |= rte_cpu_to_le_16(
8203 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8204 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8205 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8206 pfilter->element.queue_number =
8207 rte_cpu_to_le_16(tunnel_filter->queue_id);
8209 if (!tunnel_filter->is_to_vf)
8212 if (tunnel_filter->vf_id >= pf->vf_num) {
8213 PMD_DRV_LOG(ERR, "Invalid argument.");
8214 rte_free(cld_filter);
8217 vf = &pf->vfs[tunnel_filter->vf_id];
8221 /* Check if there is the filter in SW list */
8222 memset(&check_filter, 0, sizeof(check_filter));
8223 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8224 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8225 check_filter.vf_id = tunnel_filter->vf_id;
8226 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8228 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8229 rte_free(cld_filter);
8233 if (!add && !node) {
8234 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8235 rte_free(cld_filter);
8241 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8242 vsi->seid, cld_filter, 1);
8244 ret = i40e_aq_add_cloud_filters(hw,
8245 vsi->seid, &cld_filter->element, 1);
8247 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8248 rte_free(cld_filter);
8251 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8252 if (tunnel == NULL) {
8253 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8254 rte_free(cld_filter);
8258 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8259 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8264 ret = i40e_aq_remove_cloud_filters_big_buffer(
8265 hw, vsi->seid, cld_filter, 1);
8267 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8268 &cld_filter->element, 1);
8270 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8271 rte_free(cld_filter);
8274 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8277 rte_free(cld_filter);
8282 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8286 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8287 if (pf->vxlan_ports[i] == port)
8295 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8299 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8301 idx = i40e_get_vxlan_port_idx(pf, port);
8303 /* Check if port already exists */
8305 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8309 /* Now check if there is space to add the new port */
8310 idx = i40e_get_vxlan_port_idx(pf, 0);
8313 "Maximum number of UDP ports reached, not adding port %d",
8318 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8321 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8325 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8328 /* New port: add it and mark its index in the bitmap */
8329 pf->vxlan_ports[idx] = port;
8330 pf->vxlan_bitmap |= (1 << idx);
8332 if (!(pf->flags & I40E_FLAG_VXLAN))
8333 pf->flags |= I40E_FLAG_VXLAN;
8339 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8342 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8344 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8345 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8349 idx = i40e_get_vxlan_port_idx(pf, port);
8352 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8356 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8357 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8361 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8364 pf->vxlan_ports[idx] = 0;
8365 pf->vxlan_bitmap &= ~(1 << idx);
8367 if (!pf->vxlan_bitmap)
8368 pf->flags &= ~I40E_FLAG_VXLAN;
8373 /* Add UDP tunneling port */
8375 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8376 struct rte_eth_udp_tunnel *udp_tunnel)
8379 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8381 if (udp_tunnel == NULL)
8384 switch (udp_tunnel->prot_type) {
8385 case RTE_TUNNEL_TYPE_VXLAN:
8386 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8389 case RTE_TUNNEL_TYPE_GENEVE:
8390 case RTE_TUNNEL_TYPE_TEREDO:
8391 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8396 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8404 /* Remove UDP tunneling port */
8406 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8407 struct rte_eth_udp_tunnel *udp_tunnel)
8410 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8412 if (udp_tunnel == NULL)
8415 switch (udp_tunnel->prot_type) {
8416 case RTE_TUNNEL_TYPE_VXLAN:
8417 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8419 case RTE_TUNNEL_TYPE_GENEVE:
8420 case RTE_TUNNEL_TYPE_TEREDO:
8421 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8425 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8433 /* Calculate the maximum number of contiguous PF queues that are configured */
8435 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8437 struct rte_eth_dev_data *data = pf->dev_data;
8439 struct i40e_rx_queue *rxq;
8442 for (i = 0; i < pf->lan_nb_qps; i++) {
8443 rxq = data->rx_queues[i];
8444 if (rxq && rxq->q_set)
8455 i40e_pf_config_rss(struct i40e_pf *pf)
8457 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8458 struct rte_eth_rss_conf rss_conf;
8459 uint32_t i, lut = 0;
8463 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8464 * It's necessary to calculate the actual PF queues that are configured.
8466 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8467 num = i40e_pf_calc_configured_queues_num(pf);
8469 num = pf->dev_data->nb_rx_queues;
8471 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8472 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8476 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8480 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8483 lut = (lut << 8) | (j & ((0x1 <<
8484 hw->func_caps.rss_table_entry_width) - 1));
8486 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8489 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8490 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8491 i40e_pf_disable_rss(pf);
8494 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8495 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8496 /* Random default keys */
8497 static uint32_t rss_key_default[] = {0x6b793944,
8498 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8499 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8500 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8502 rss_conf.rss_key = (uint8_t *)rss_key_default;
8503 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8507 return i40e_hw_rss_hash_set(pf, &rss_conf);
8511 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8512 struct rte_eth_tunnel_filter_conf *filter)
8514 if (pf == NULL || filter == NULL) {
8515 PMD_DRV_LOG(ERR, "Invalid parameter");
8519 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8520 PMD_DRV_LOG(ERR, "Invalid queue ID");
8524 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8525 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8529 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8530 (is_zero_ether_addr(&filter->outer_mac))) {
8531 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8535 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8536 (is_zero_ether_addr(&filter->inner_mac))) {
8537 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8544 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8545 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8547 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8549 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8553 if (pf->support_multi_driver) {
8554 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8558 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8559 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8562 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8563 } else if (len == 4) {
8564 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8566 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8571 ret = i40e_aq_debug_write_global_register(hw,
8572 I40E_GL_PRS_FVBM(2),
8576 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8577 "with value 0x%08x",
8578 I40E_GL_PRS_FVBM(2), reg);
8582 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8583 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8589 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8596 switch (cfg->cfg_type) {
8597 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8598 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8601 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8609 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8610 enum rte_filter_op filter_op,
8613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8614 int ret = I40E_ERR_PARAM;
8616 switch (filter_op) {
8617 case RTE_ETH_FILTER_SET:
8618 ret = i40e_dev_global_config_set(hw,
8619 (struct rte_eth_global_cfg *)arg);
8622 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8630 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8631 enum rte_filter_op filter_op,
8634 struct rte_eth_tunnel_filter_conf *filter;
8635 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8636 int ret = I40E_SUCCESS;
8638 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8640 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8641 return I40E_ERR_PARAM;
8643 switch (filter_op) {
8644 case RTE_ETH_FILTER_NOP:
8645 if (!(pf->flags & I40E_FLAG_VXLAN))
8646 ret = I40E_NOT_SUPPORTED;
8648 case RTE_ETH_FILTER_ADD:
8649 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8651 case RTE_ETH_FILTER_DELETE:
8652 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8655 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8656 ret = I40E_ERR_PARAM;
8664 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8667 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8670 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8671 ret = i40e_pf_config_rss(pf);
8673 i40e_pf_disable_rss(pf);
8678 /* Get the symmetric hash enable configurations per port */
8680 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8682 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8684 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8687 /* Set the symmetric hash enable configurations per port */
8689 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8691 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8694 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8696 "Symmetric hash has already been enabled");
8699 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8701 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8703 "Symmetric hash has already been disabled");
8706 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8708 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8709 I40E_WRITE_FLUSH(hw);
8713 * Get global configurations of hash function type and symmetric hash enable
8714 * per flow type (pctype). Note that global configuration means it affects all
8715 * the ports on the same NIC.
8718 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8719 struct rte_eth_hash_global_conf *g_cfg)
8721 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8725 memset(g_cfg, 0, sizeof(*g_cfg));
8726 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8727 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8728 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8730 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8731 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8732 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8735 * As i40e supports less than 64 flow types, only first 64 bits need to
8738 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8739 g_cfg->valid_bit_mask[i] = 0ULL;
8740 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8743 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8745 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8746 if (!adapter->pctypes_tbl[i])
8748 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8749 j < I40E_FILTER_PCTYPE_MAX; j++) {
8750 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8751 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8752 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8753 g_cfg->sym_hash_enable_mask[0] |=
8764 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8765 const struct rte_eth_hash_global_conf *g_cfg)
8768 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8770 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8771 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8772 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8773 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8779 * As i40e supports less than 64 flow types, only first 64 bits need to
8782 mask0 = g_cfg->valid_bit_mask[0];
8783 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8785 /* Check if any unsupported flow type configured */
8786 if ((mask0 | i40e_mask) ^ i40e_mask)
8789 if (g_cfg->valid_bit_mask[i])
8797 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8803 * Set global configurations of hash function type and symmetric hash enable
8804 * per flow type (pctype). Note any modifying global configuration will affect
8805 * all the ports on the same NIC.
8808 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8809 struct rte_eth_hash_global_conf *g_cfg)
8811 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8812 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8816 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8818 if (pf->support_multi_driver) {
8819 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8823 /* Check the input parameters */
8824 ret = i40e_hash_global_config_check(adapter, g_cfg);
8829 * As i40e supports less than 64 flow types, only first 64 bits need to
8832 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8833 if (mask0 & (1UL << i)) {
8834 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8835 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8837 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8838 j < I40E_FILTER_PCTYPE_MAX; j++) {
8839 if (adapter->pctypes_tbl[i] & (1ULL << j))
8840 i40e_write_global_rx_ctl(hw,
8847 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8848 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8850 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8852 "Hash function already set to Toeplitz");
8855 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8856 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8858 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8860 "Hash function already set to Simple XOR");
8863 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8865 /* Use the default, and keep it as it is */
8868 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8871 I40E_WRITE_FLUSH(hw);
8877 * Valid input sets for hash and flow director filters per PCTYPE
8880 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8881 enum rte_filter_type filter)
8885 static const uint64_t valid_hash_inset_table[] = {
8886 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8887 I40E_INSET_DMAC | I40E_INSET_SMAC |
8888 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8889 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8890 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8891 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8892 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8893 I40E_INSET_FLEX_PAYLOAD,
8894 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8895 I40E_INSET_DMAC | I40E_INSET_SMAC |
8896 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8897 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8898 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8899 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8900 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8901 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8902 I40E_INSET_FLEX_PAYLOAD,
8903 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8904 I40E_INSET_DMAC | I40E_INSET_SMAC |
8905 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8906 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8907 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8908 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8909 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8910 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8911 I40E_INSET_FLEX_PAYLOAD,
8912 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8913 I40E_INSET_DMAC | I40E_INSET_SMAC |
8914 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8915 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8916 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8917 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8918 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8919 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8920 I40E_INSET_FLEX_PAYLOAD,
8921 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8922 I40E_INSET_DMAC | I40E_INSET_SMAC |
8923 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8924 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8925 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8926 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8927 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8928 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8929 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8930 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8931 I40E_INSET_DMAC | I40E_INSET_SMAC |
8932 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8933 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8934 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8935 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8936 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8937 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8938 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8939 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8940 I40E_INSET_DMAC | I40E_INSET_SMAC |
8941 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8942 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8943 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8944 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8945 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8946 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8947 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8948 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8949 I40E_INSET_DMAC | I40E_INSET_SMAC |
8950 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8951 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8952 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8953 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8954 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8955 I40E_INSET_FLEX_PAYLOAD,
8956 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8957 I40E_INSET_DMAC | I40E_INSET_SMAC |
8958 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8959 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8960 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8961 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8962 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8963 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8964 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8965 I40E_INSET_DMAC | I40E_INSET_SMAC |
8966 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8967 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8968 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8969 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8970 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8971 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8972 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8973 I40E_INSET_DMAC | I40E_INSET_SMAC |
8974 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8975 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8976 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8977 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8978 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8979 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8980 I40E_INSET_FLEX_PAYLOAD,
8981 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8982 I40E_INSET_DMAC | I40E_INSET_SMAC |
8983 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8984 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8985 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8986 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8987 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8988 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8989 I40E_INSET_FLEX_PAYLOAD,
8990 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8991 I40E_INSET_DMAC | I40E_INSET_SMAC |
8992 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8993 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8994 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8995 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8996 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8997 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8998 I40E_INSET_FLEX_PAYLOAD,
8999 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9000 I40E_INSET_DMAC | I40E_INSET_SMAC |
9001 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9002 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9003 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9004 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9005 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9006 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9007 I40E_INSET_FLEX_PAYLOAD,
9008 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9009 I40E_INSET_DMAC | I40E_INSET_SMAC |
9010 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9011 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9012 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9013 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9014 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9015 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9016 I40E_INSET_FLEX_PAYLOAD,
9017 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9018 I40E_INSET_DMAC | I40E_INSET_SMAC |
9019 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9020 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9021 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9022 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9023 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9024 I40E_INSET_FLEX_PAYLOAD,
9025 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9026 I40E_INSET_DMAC | I40E_INSET_SMAC |
9027 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9028 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9029 I40E_INSET_FLEX_PAYLOAD,
9033 * Flow director supports only fields defined in
9034 * union rte_eth_fdir_flow.
9036 static const uint64_t valid_fdir_inset_table[] = {
9037 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9038 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9039 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9040 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9041 I40E_INSET_IPV4_TTL,
9042 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9043 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9044 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9045 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9046 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9047 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9048 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9049 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9050 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9051 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9052 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9053 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9054 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9055 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9056 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9057 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9058 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9059 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9060 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9061 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9062 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9064 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9065 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9066 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9067 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9069 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9070 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9071 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9073 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9074 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9076 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9077 I40E_INSET_IPV4_TTL,
9078 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9079 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9080 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9081 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9082 I40E_INSET_IPV6_HOP_LIMIT,
9083 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9084 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9086 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9087 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9088 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9089 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9090 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9091 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9092 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9093 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9094 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9095 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9096 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9097 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9098 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9099 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9100 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9101 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9102 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9103 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9104 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9105 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9106 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9107 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9108 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9109 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9110 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9111 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9112 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9114 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9115 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9116 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9117 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9118 I40E_INSET_IPV6_HOP_LIMIT,
9119 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9121 I40E_INSET_LAST_ETHER_TYPE,
9124 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9126 if (filter == RTE_ETH_FILTER_HASH)
9127 valid = valid_hash_inset_table[pctype];
9129 valid = valid_fdir_inset_table[pctype];
9135 * Validate if the input set is allowed for a specific PCTYPE
9138 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9139 enum rte_filter_type filter, uint64_t inset)
9143 valid = i40e_get_valid_input_set(pctype, filter);
9144 if (inset & (~valid))
9150 /* default input set fields combination per pctype */
9152 i40e_get_default_input_set(uint16_t pctype)
9154 static const uint64_t default_inset_table[] = {
9155 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9156 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9157 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9158 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9159 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9160 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9161 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9162 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9163 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9164 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9165 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9166 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9167 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9168 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9169 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9170 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9171 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9172 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9173 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9176 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9177 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9178 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9179 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9180 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9181 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9182 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9183 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9184 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9185 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9186 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9187 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9188 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9189 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9190 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9191 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9192 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9193 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9194 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9195 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9196 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9199 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9200 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9201 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9202 I40E_INSET_LAST_ETHER_TYPE,
9205 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9208 return default_inset_table[pctype];
9212 * Parse the input set from index to logical bit masks
9215 i40e_parse_input_set(uint64_t *inset,
9216 enum i40e_filter_pctype pctype,
9217 enum rte_eth_input_set_field *field,
9223 static const struct {
9224 enum rte_eth_input_set_field field;
9226 } inset_convert_table[] = {
9227 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9228 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9229 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9230 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9231 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9232 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9233 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9234 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9235 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9236 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9237 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9238 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9239 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9240 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9241 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9242 I40E_INSET_IPV6_NEXT_HDR},
9243 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9244 I40E_INSET_IPV6_HOP_LIMIT},
9245 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9246 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9247 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9248 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9249 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9250 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9251 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9252 I40E_INSET_SCTP_VT},
9253 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9254 I40E_INSET_TUNNEL_DMAC},
9255 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9256 I40E_INSET_VLAN_TUNNEL},
9257 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9258 I40E_INSET_TUNNEL_ID},
9259 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9260 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9261 I40E_INSET_FLEX_PAYLOAD_W1},
9262 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9263 I40E_INSET_FLEX_PAYLOAD_W2},
9264 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9265 I40E_INSET_FLEX_PAYLOAD_W3},
9266 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9267 I40E_INSET_FLEX_PAYLOAD_W4},
9268 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9269 I40E_INSET_FLEX_PAYLOAD_W5},
9270 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9271 I40E_INSET_FLEX_PAYLOAD_W6},
9272 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9273 I40E_INSET_FLEX_PAYLOAD_W7},
9274 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9275 I40E_INSET_FLEX_PAYLOAD_W8},
9278 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9281 /* Only one item allowed for default or all */
9283 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9284 *inset = i40e_get_default_input_set(pctype);
9286 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9287 *inset = I40E_INSET_NONE;
9292 for (i = 0, *inset = 0; i < size; i++) {
9293 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9294 if (field[i] == inset_convert_table[j].field) {
9295 *inset |= inset_convert_table[j].inset;
9300 /* It contains unsupported input set, return immediately */
9301 if (j == RTE_DIM(inset_convert_table))
9309 * Translate the input set from bit masks to register aware bit masks
9313 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9323 static const struct inset_map inset_map_common[] = {
9324 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9325 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9326 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9327 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9328 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9329 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9330 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9331 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9332 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9333 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9334 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9335 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9336 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9337 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9338 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9339 {I40E_INSET_TUNNEL_DMAC,
9340 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9341 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9342 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9343 {I40E_INSET_TUNNEL_SRC_PORT,
9344 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9345 {I40E_INSET_TUNNEL_DST_PORT,
9346 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9347 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9348 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9349 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9350 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9351 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9352 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9353 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9354 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9355 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9358 /* some different registers map in x722*/
9359 static const struct inset_map inset_map_diff_x722[] = {
9360 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9361 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9362 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9363 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9366 static const struct inset_map inset_map_diff_not_x722[] = {
9367 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9368 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9369 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9370 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9376 /* Translate input set to register aware inset */
9377 if (type == I40E_MAC_X722) {
9378 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9379 if (input & inset_map_diff_x722[i].inset)
9380 val |= inset_map_diff_x722[i].inset_reg;
9383 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9384 if (input & inset_map_diff_not_x722[i].inset)
9385 val |= inset_map_diff_not_x722[i].inset_reg;
9389 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9390 if (input & inset_map_common[i].inset)
9391 val |= inset_map_common[i].inset_reg;
9398 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9401 uint64_t inset_need_mask = inset;
9403 static const struct {
9406 } inset_mask_map[] = {
9407 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9408 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9409 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9410 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9411 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9412 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9413 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9414 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9417 if (!inset || !mask || !nb_elem)
9420 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9421 /* Clear the inset bit, if no MASK is required,
9422 * for example proto + ttl
9424 if ((inset & inset_mask_map[i].inset) ==
9425 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9426 inset_need_mask &= ~inset_mask_map[i].inset;
9427 if (!inset_need_mask)
9430 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9431 if ((inset_need_mask & inset_mask_map[i].inset) ==
9432 inset_mask_map[i].inset) {
9433 if (idx >= nb_elem) {
9434 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9437 mask[idx] = inset_mask_map[i].mask;
9446 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9448 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9450 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9452 i40e_write_rx_ctl(hw, addr, val);
9453 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9454 (uint32_t)i40e_read_rx_ctl(hw, addr));
9458 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9460 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9461 struct rte_eth_dev *dev;
9463 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9465 i40e_write_rx_ctl(hw, addr, val);
9466 PMD_DRV_LOG(WARNING,
9467 "i40e device %s changed global register [0x%08x]."
9468 " original: 0x%08x, new: 0x%08x",
9469 dev->device->name, addr, reg,
9470 (uint32_t)i40e_read_rx_ctl(hw, addr));
9475 i40e_filter_input_set_init(struct i40e_pf *pf)
9477 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9478 enum i40e_filter_pctype pctype;
9479 uint64_t input_set, inset_reg;
9480 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9484 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9485 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9486 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9488 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9491 input_set = i40e_get_default_input_set(pctype);
9493 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9494 I40E_INSET_MASK_NUM_REG);
9497 if (pf->support_multi_driver && num > 0) {
9498 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9501 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9504 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9505 (uint32_t)(inset_reg & UINT32_MAX));
9506 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9507 (uint32_t)((inset_reg >>
9508 I40E_32_BIT_WIDTH) & UINT32_MAX));
9509 if (!pf->support_multi_driver) {
9510 i40e_check_write_global_reg(hw,
9511 I40E_GLQF_HASH_INSET(0, pctype),
9512 (uint32_t)(inset_reg & UINT32_MAX));
9513 i40e_check_write_global_reg(hw,
9514 I40E_GLQF_HASH_INSET(1, pctype),
9515 (uint32_t)((inset_reg >>
9516 I40E_32_BIT_WIDTH) & UINT32_MAX));
9518 for (i = 0; i < num; i++) {
9519 i40e_check_write_global_reg(hw,
9520 I40E_GLQF_FD_MSK(i, pctype),
9522 i40e_check_write_global_reg(hw,
9523 I40E_GLQF_HASH_MSK(i, pctype),
9526 /*clear unused mask registers of the pctype */
9527 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9528 i40e_check_write_global_reg(hw,
9529 I40E_GLQF_FD_MSK(i, pctype),
9531 i40e_check_write_global_reg(hw,
9532 I40E_GLQF_HASH_MSK(i, pctype),
9536 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9538 I40E_WRITE_FLUSH(hw);
9540 /* store the default input set */
9541 if (!pf->support_multi_driver)
9542 pf->hash_input_set[pctype] = input_set;
9543 pf->fdir.input_set[pctype] = input_set;
9548 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9549 struct rte_eth_input_set_conf *conf)
9551 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9552 enum i40e_filter_pctype pctype;
9553 uint64_t input_set, inset_reg = 0;
9554 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9558 PMD_DRV_LOG(ERR, "Invalid pointer");
9561 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9562 conf->op != RTE_ETH_INPUT_SET_ADD) {
9563 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9567 if (pf->support_multi_driver) {
9568 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9572 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9573 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9574 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9578 if (hw->mac.type == I40E_MAC_X722) {
9579 /* get translated pctype value in fd pctype register */
9580 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9581 I40E_GLQF_FD_PCTYPES((int)pctype));
9584 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9587 PMD_DRV_LOG(ERR, "Failed to parse input set");
9591 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9592 /* get inset value in register */
9593 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9594 inset_reg <<= I40E_32_BIT_WIDTH;
9595 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9596 input_set |= pf->hash_input_set[pctype];
9598 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9599 I40E_INSET_MASK_NUM_REG);
9603 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9605 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9606 (uint32_t)(inset_reg & UINT32_MAX));
9607 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9608 (uint32_t)((inset_reg >>
9609 I40E_32_BIT_WIDTH) & UINT32_MAX));
9611 for (i = 0; i < num; i++)
9612 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9614 /*clear unused mask registers of the pctype */
9615 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9616 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9618 I40E_WRITE_FLUSH(hw);
9620 pf->hash_input_set[pctype] = input_set;
9625 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9626 struct rte_eth_input_set_conf *conf)
9628 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9629 enum i40e_filter_pctype pctype;
9630 uint64_t input_set, inset_reg = 0;
9631 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9635 PMD_DRV_LOG(ERR, "Invalid pointer");
9638 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9639 conf->op != RTE_ETH_INPUT_SET_ADD) {
9640 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9644 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9646 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9647 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9651 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9654 PMD_DRV_LOG(ERR, "Failed to parse input set");
9658 /* get inset value in register */
9659 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9660 inset_reg <<= I40E_32_BIT_WIDTH;
9661 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9663 /* Can not change the inset reg for flex payload for fdir,
9664 * it is done by writing I40E_PRTQF_FD_FLXINSET
9665 * in i40e_set_flex_mask_on_pctype.
9667 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9668 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9670 input_set |= pf->fdir.input_set[pctype];
9671 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9672 I40E_INSET_MASK_NUM_REG);
9675 if (pf->support_multi_driver && num > 0) {
9676 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9680 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9682 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9683 (uint32_t)(inset_reg & UINT32_MAX));
9684 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9685 (uint32_t)((inset_reg >>
9686 I40E_32_BIT_WIDTH) & UINT32_MAX));
9688 if (!pf->support_multi_driver) {
9689 for (i = 0; i < num; i++)
9690 i40e_check_write_global_reg(hw,
9691 I40E_GLQF_FD_MSK(i, pctype),
9693 /*clear unused mask registers of the pctype */
9694 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9695 i40e_check_write_global_reg(hw,
9696 I40E_GLQF_FD_MSK(i, pctype),
9699 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9701 I40E_WRITE_FLUSH(hw);
9703 pf->fdir.input_set[pctype] = input_set;
9708 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9713 PMD_DRV_LOG(ERR, "Invalid pointer");
9717 switch (info->info_type) {
9718 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9719 i40e_get_symmetric_hash_enable_per_port(hw,
9720 &(info->info.enable));
9722 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9723 ret = i40e_get_hash_filter_global_config(hw,
9724 &(info->info.global_conf));
9727 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9737 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9742 PMD_DRV_LOG(ERR, "Invalid pointer");
9746 switch (info->info_type) {
9747 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9748 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9750 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9751 ret = i40e_set_hash_filter_global_config(hw,
9752 &(info->info.global_conf));
9754 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9755 ret = i40e_hash_filter_inset_select(hw,
9756 &(info->info.input_set_conf));
9760 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9769 /* Operations for hash function */
9771 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9772 enum rte_filter_op filter_op,
9775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9778 switch (filter_op) {
9779 case RTE_ETH_FILTER_NOP:
9781 case RTE_ETH_FILTER_GET:
9782 ret = i40e_hash_filter_get(hw,
9783 (struct rte_eth_hash_filter_info *)arg);
9785 case RTE_ETH_FILTER_SET:
9786 ret = i40e_hash_filter_set(hw,
9787 (struct rte_eth_hash_filter_info *)arg);
9790 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9799 /* Convert ethertype filter structure */
9801 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9802 struct i40e_ethertype_filter *filter)
9804 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9805 filter->input.ether_type = input->ether_type;
9806 filter->flags = input->flags;
9807 filter->queue = input->queue;
9812 /* Check if there exists the ehtertype filter */
9813 struct i40e_ethertype_filter *
9814 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9815 const struct i40e_ethertype_filter_input *input)
9819 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9823 return ethertype_rule->hash_map[ret];
9826 /* Add ethertype filter in SW list */
9828 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9829 struct i40e_ethertype_filter *filter)
9831 struct i40e_ethertype_rule *rule = &pf->ethertype;
9834 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9837 "Failed to insert ethertype filter"
9838 " to hash table %d!",
9842 rule->hash_map[ret] = filter;
9844 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9849 /* Delete ethertype filter in SW list */
9851 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9852 struct i40e_ethertype_filter_input *input)
9854 struct i40e_ethertype_rule *rule = &pf->ethertype;
9855 struct i40e_ethertype_filter *filter;
9858 ret = rte_hash_del_key(rule->hash_table, input);
9861 "Failed to delete ethertype filter"
9862 " to hash table %d!",
9866 filter = rule->hash_map[ret];
9867 rule->hash_map[ret] = NULL;
9869 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9876 * Configure ethertype filter, which can director packet by filtering
9877 * with mac address and ether_type or only ether_type
9880 i40e_ethertype_filter_set(struct i40e_pf *pf,
9881 struct rte_eth_ethertype_filter *filter,
9884 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9885 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9886 struct i40e_ethertype_filter *ethertype_filter, *node;
9887 struct i40e_ethertype_filter check_filter;
9888 struct i40e_control_filter_stats stats;
9892 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9893 PMD_DRV_LOG(ERR, "Invalid queue ID");
9896 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9897 filter->ether_type == ETHER_TYPE_IPv6) {
9899 "unsupported ether_type(0x%04x) in control packet filter.",
9900 filter->ether_type);
9903 if (filter->ether_type == ETHER_TYPE_VLAN)
9904 PMD_DRV_LOG(WARNING,
9905 "filter vlan ether_type in first tag is not supported.");
9907 /* Check if there is the filter in SW list */
9908 memset(&check_filter, 0, sizeof(check_filter));
9909 i40e_ethertype_filter_convert(filter, &check_filter);
9910 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9911 &check_filter.input);
9913 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9917 if (!add && !node) {
9918 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9922 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9923 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9924 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9925 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9926 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9928 memset(&stats, 0, sizeof(stats));
9929 ret = i40e_aq_add_rem_control_packet_filter(hw,
9930 filter->mac_addr.addr_bytes,
9931 filter->ether_type, flags,
9933 filter->queue, add, &stats, NULL);
9936 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9937 ret, stats.mac_etype_used, stats.etype_used,
9938 stats.mac_etype_free, stats.etype_free);
9942 /* Add or delete a filter in SW list */
9944 ethertype_filter = rte_zmalloc("ethertype_filter",
9945 sizeof(*ethertype_filter), 0);
9946 if (ethertype_filter == NULL) {
9947 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9951 rte_memcpy(ethertype_filter, &check_filter,
9952 sizeof(check_filter));
9953 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9955 rte_free(ethertype_filter);
9957 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9964 * Handle operations for ethertype filter.
9967 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9968 enum rte_filter_op filter_op,
9971 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9974 if (filter_op == RTE_ETH_FILTER_NOP)
9978 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9983 switch (filter_op) {
9984 case RTE_ETH_FILTER_ADD:
9985 ret = i40e_ethertype_filter_set(pf,
9986 (struct rte_eth_ethertype_filter *)arg,
9989 case RTE_ETH_FILTER_DELETE:
9990 ret = i40e_ethertype_filter_set(pf,
9991 (struct rte_eth_ethertype_filter *)arg,
9995 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10003 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10004 enum rte_filter_type filter_type,
10005 enum rte_filter_op filter_op,
10013 switch (filter_type) {
10014 case RTE_ETH_FILTER_NONE:
10015 /* For global configuration */
10016 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10018 case RTE_ETH_FILTER_HASH:
10019 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10021 case RTE_ETH_FILTER_MACVLAN:
10022 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10024 case RTE_ETH_FILTER_ETHERTYPE:
10025 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10027 case RTE_ETH_FILTER_TUNNEL:
10028 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10030 case RTE_ETH_FILTER_FDIR:
10031 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10033 case RTE_ETH_FILTER_GENERIC:
10034 if (filter_op != RTE_ETH_FILTER_GET)
10036 *(const void **)arg = &i40e_flow_ops;
10039 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10049 * Check and enable Extended Tag.
10050 * Enabling Extended Tag is important for 40G performance.
10053 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10055 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10059 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10062 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10066 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10067 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10072 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10075 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10079 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10080 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10083 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10084 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10087 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10094 * As some registers wouldn't be reset unless a global hardware reset,
10095 * hardware initialization is needed to put those registers into an
10096 * expected initial state.
10099 i40e_hw_init(struct rte_eth_dev *dev)
10101 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10103 i40e_enable_extended_tag(dev);
10105 /* clear the PF Queue Filter control register */
10106 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10108 /* Disable symmetric hash per port */
10109 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10113 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10114 * however this function will return only one highest pctype index,
10115 * which is not quite correct. This is known problem of i40e driver
10116 * and needs to be fixed later.
10118 enum i40e_filter_pctype
10119 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10122 uint64_t pctype_mask;
10124 if (flow_type < I40E_FLOW_TYPE_MAX) {
10125 pctype_mask = adapter->pctypes_tbl[flow_type];
10126 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10127 if (pctype_mask & (1ULL << i))
10128 return (enum i40e_filter_pctype)i;
10131 return I40E_FILTER_PCTYPE_INVALID;
10135 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10136 enum i40e_filter_pctype pctype)
10139 uint64_t pctype_mask = 1ULL << pctype;
10141 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10143 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10147 return RTE_ETH_FLOW_UNKNOWN;
10151 * On X710, performance number is far from the expectation on recent firmware
10152 * versions; on XL710, performance number is also far from the expectation on
10153 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10154 * mode is enabled and port MAC address is equal to the packet destination MAC
10155 * address. The fix for this issue may not be integrated in the following
10156 * firmware version. So the workaround in software driver is needed. It needs
10157 * to modify the initial values of 3 internal only registers for both X710 and
10158 * XL710. Note that the values for X710 or XL710 could be different, and the
10159 * workaround can be removed when it is fixed in firmware in the future.
10162 /* For both X710 and XL710 */
10163 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10164 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10165 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10167 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10168 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10171 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10172 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10175 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10177 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10178 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10181 * GL_SWR_PM_UP_THR:
10182 * The value is not impacted from the link speed, its value is set according
10183 * to the total number of ports for a better pipe-monitor configuration.
10186 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10188 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10189 .device_id = (dev), \
10190 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10192 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10193 .device_id = (dev), \
10194 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10196 static const struct {
10197 uint16_t device_id;
10199 } swr_pm_table[] = {
10200 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10201 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10202 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10203 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10205 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10206 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10207 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10208 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10209 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10210 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10211 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10215 if (value == NULL) {
10216 PMD_DRV_LOG(ERR, "value is NULL");
10220 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10221 if (hw->device_id == swr_pm_table[i].device_id) {
10222 *value = swr_pm_table[i].val;
10224 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10226 hw->device_id, *value);
10235 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10237 enum i40e_status_code status;
10238 struct i40e_aq_get_phy_abilities_resp phy_ab;
10239 int ret = -ENOTSUP;
10242 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10246 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10249 rte_delay_us(100000);
10251 status = i40e_aq_get_phy_capabilities(hw, false,
10252 true, &phy_ab, NULL);
10260 i40e_configure_registers(struct i40e_hw *hw)
10266 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10267 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10268 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10274 for (i = 0; i < RTE_DIM(reg_table); i++) {
10275 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10276 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10278 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10279 else /* For X710/XL710/XXV710 */
10280 if (hw->aq.fw_maj_ver < 6)
10282 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10285 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10288 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10289 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10291 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10292 else /* For X710/XL710/XXV710 */
10294 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10297 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10300 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10301 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10302 "GL_SWR_PM_UP_THR value fixup",
10307 reg_table[i].val = cfg_val;
10310 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10313 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10314 reg_table[i].addr);
10317 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10318 reg_table[i].addr, reg);
10319 if (reg == reg_table[i].val)
10322 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10323 reg_table[i].val, NULL);
10326 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10327 reg_table[i].val, reg_table[i].addr);
10330 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10331 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10335 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10336 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10337 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10338 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10340 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10345 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10346 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10350 /* Configure for double VLAN RX stripping */
10351 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10352 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10353 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10354 ret = i40e_aq_debug_write_register(hw,
10355 I40E_VSI_TSR(vsi->vsi_id),
10358 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10360 return I40E_ERR_CONFIG;
10364 /* Configure for double VLAN TX insertion */
10365 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10366 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10367 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10368 ret = i40e_aq_debug_write_register(hw,
10369 I40E_VSI_L2TAGSTXVALID(
10370 vsi->vsi_id), reg, NULL);
10373 "Failed to update VSI_L2TAGSTXVALID[%d]",
10375 return I40E_ERR_CONFIG;
10383 * i40e_aq_add_mirror_rule
10384 * @hw: pointer to the hardware structure
10385 * @seid: VEB seid to add mirror rule to
10386 * @dst_id: destination vsi seid
10387 * @entries: Buffer which contains the entities to be mirrored
10388 * @count: number of entities contained in the buffer
10389 * @rule_id:the rule_id of the rule to be added
10391 * Add a mirror rule for a given veb.
10394 static enum i40e_status_code
10395 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10396 uint16_t seid, uint16_t dst_id,
10397 uint16_t rule_type, uint16_t *entries,
10398 uint16_t count, uint16_t *rule_id)
10400 struct i40e_aq_desc desc;
10401 struct i40e_aqc_add_delete_mirror_rule cmd;
10402 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10403 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10406 enum i40e_status_code status;
10408 i40e_fill_default_direct_cmd_desc(&desc,
10409 i40e_aqc_opc_add_mirror_rule);
10410 memset(&cmd, 0, sizeof(cmd));
10412 buff_len = sizeof(uint16_t) * count;
10413 desc.datalen = rte_cpu_to_le_16(buff_len);
10415 desc.flags |= rte_cpu_to_le_16(
10416 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10417 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10418 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10419 cmd.num_entries = rte_cpu_to_le_16(count);
10420 cmd.seid = rte_cpu_to_le_16(seid);
10421 cmd.destination = rte_cpu_to_le_16(dst_id);
10423 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10424 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10426 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10427 hw->aq.asq_last_status, resp->rule_id,
10428 resp->mirror_rules_used, resp->mirror_rules_free);
10429 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10435 * i40e_aq_del_mirror_rule
10436 * @hw: pointer to the hardware structure
10437 * @seid: VEB seid to add mirror rule to
10438 * @entries: Buffer which contains the entities to be mirrored
10439 * @count: number of entities contained in the buffer
10440 * @rule_id:the rule_id of the rule to be delete
10442 * Delete a mirror rule for a given veb.
10445 static enum i40e_status_code
10446 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10447 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10448 uint16_t count, uint16_t rule_id)
10450 struct i40e_aq_desc desc;
10451 struct i40e_aqc_add_delete_mirror_rule cmd;
10452 uint16_t buff_len = 0;
10453 enum i40e_status_code status;
10456 i40e_fill_default_direct_cmd_desc(&desc,
10457 i40e_aqc_opc_delete_mirror_rule);
10458 memset(&cmd, 0, sizeof(cmd));
10459 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10460 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10462 cmd.num_entries = count;
10463 buff_len = sizeof(uint16_t) * count;
10464 desc.datalen = rte_cpu_to_le_16(buff_len);
10465 buff = (void *)entries;
10467 /* rule id is filled in destination field for deleting mirror rule */
10468 cmd.destination = rte_cpu_to_le_16(rule_id);
10470 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10471 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10472 cmd.seid = rte_cpu_to_le_16(seid);
10474 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10475 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10481 * i40e_mirror_rule_set
10482 * @dev: pointer to the hardware structure
10483 * @mirror_conf: mirror rule info
10484 * @sw_id: mirror rule's sw_id
10485 * @on: enable/disable
10487 * set a mirror rule.
10491 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10492 struct rte_eth_mirror_conf *mirror_conf,
10493 uint8_t sw_id, uint8_t on)
10495 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10496 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10497 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10498 struct i40e_mirror_rule *parent = NULL;
10499 uint16_t seid, dst_seid, rule_id;
10503 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10505 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10507 "mirror rule can not be configured without veb or vfs.");
10510 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10511 PMD_DRV_LOG(ERR, "mirror table is full.");
10514 if (mirror_conf->dst_pool > pf->vf_num) {
10515 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10516 mirror_conf->dst_pool);
10520 seid = pf->main_vsi->veb->seid;
10522 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10523 if (sw_id <= it->index) {
10529 if (mirr_rule && sw_id == mirr_rule->index) {
10531 PMD_DRV_LOG(ERR, "mirror rule exists.");
10534 ret = i40e_aq_del_mirror_rule(hw, seid,
10535 mirr_rule->rule_type,
10536 mirr_rule->entries,
10537 mirr_rule->num_entries, mirr_rule->id);
10540 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10541 ret, hw->aq.asq_last_status);
10544 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10545 rte_free(mirr_rule);
10546 pf->nb_mirror_rule--;
10550 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10554 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10555 sizeof(struct i40e_mirror_rule) , 0);
10557 PMD_DRV_LOG(ERR, "failed to allocate memory");
10558 return I40E_ERR_NO_MEMORY;
10560 switch (mirror_conf->rule_type) {
10561 case ETH_MIRROR_VLAN:
10562 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10563 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10564 mirr_rule->entries[j] =
10565 mirror_conf->vlan.vlan_id[i];
10570 PMD_DRV_LOG(ERR, "vlan is not specified.");
10571 rte_free(mirr_rule);
10574 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10576 case ETH_MIRROR_VIRTUAL_POOL_UP:
10577 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10578 /* check if the specified pool bit is out of range */
10579 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10580 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10581 rte_free(mirr_rule);
10584 for (i = 0, j = 0; i < pf->vf_num; i++) {
10585 if (mirror_conf->pool_mask & (1ULL << i)) {
10586 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10590 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10591 /* add pf vsi to entries */
10592 mirr_rule->entries[j] = pf->main_vsi_seid;
10596 PMD_DRV_LOG(ERR, "pool is not specified.");
10597 rte_free(mirr_rule);
10600 /* egress and ingress in aq commands means from switch but not port */
10601 mirr_rule->rule_type =
10602 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10603 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10604 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10606 case ETH_MIRROR_UPLINK_PORT:
10607 /* egress and ingress in aq commands means from switch but not port*/
10608 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10610 case ETH_MIRROR_DOWNLINK_PORT:
10611 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10614 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10615 mirror_conf->rule_type);
10616 rte_free(mirr_rule);
10620 /* If the dst_pool is equal to vf_num, consider it as PF */
10621 if (mirror_conf->dst_pool == pf->vf_num)
10622 dst_seid = pf->main_vsi_seid;
10624 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10626 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10627 mirr_rule->rule_type, mirr_rule->entries,
10631 "failed to add mirror rule: ret = %d, aq_err = %d.",
10632 ret, hw->aq.asq_last_status);
10633 rte_free(mirr_rule);
10637 mirr_rule->index = sw_id;
10638 mirr_rule->num_entries = j;
10639 mirr_rule->id = rule_id;
10640 mirr_rule->dst_vsi_seid = dst_seid;
10643 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10645 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10647 pf->nb_mirror_rule++;
10652 * i40e_mirror_rule_reset
10653 * @dev: pointer to the device
10654 * @sw_id: mirror rule's sw_id
10656 * reset a mirror rule.
10660 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10662 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10664 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10668 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10670 seid = pf->main_vsi->veb->seid;
10672 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10673 if (sw_id == it->index) {
10679 ret = i40e_aq_del_mirror_rule(hw, seid,
10680 mirr_rule->rule_type,
10681 mirr_rule->entries,
10682 mirr_rule->num_entries, mirr_rule->id);
10685 "failed to remove mirror rule: status = %d, aq_err = %d.",
10686 ret, hw->aq.asq_last_status);
10689 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10690 rte_free(mirr_rule);
10691 pf->nb_mirror_rule--;
10693 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10700 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10703 uint64_t systim_cycles;
10705 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10706 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10709 return systim_cycles;
10713 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10716 uint64_t rx_tstamp;
10718 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10719 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10726 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10728 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10729 uint64_t tx_tstamp;
10731 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10732 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10739 i40e_start_timecounters(struct rte_eth_dev *dev)
10741 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10742 struct i40e_adapter *adapter =
10743 (struct i40e_adapter *)dev->data->dev_private;
10744 struct rte_eth_link link;
10745 uint32_t tsync_inc_l;
10746 uint32_t tsync_inc_h;
10748 /* Get current link speed. */
10749 i40e_dev_link_update(dev, 1);
10750 rte_eth_linkstatus_get(dev, &link);
10752 switch (link.link_speed) {
10753 case ETH_SPEED_NUM_40G:
10754 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10755 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10757 case ETH_SPEED_NUM_10G:
10758 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10759 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10761 case ETH_SPEED_NUM_1G:
10762 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10763 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10770 /* Set the timesync increment value. */
10771 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10772 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10774 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10775 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10776 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10778 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10779 adapter->systime_tc.cc_shift = 0;
10780 adapter->systime_tc.nsec_mask = 0;
10782 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10783 adapter->rx_tstamp_tc.cc_shift = 0;
10784 adapter->rx_tstamp_tc.nsec_mask = 0;
10786 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10787 adapter->tx_tstamp_tc.cc_shift = 0;
10788 adapter->tx_tstamp_tc.nsec_mask = 0;
10792 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10794 struct i40e_adapter *adapter =
10795 (struct i40e_adapter *)dev->data->dev_private;
10797 adapter->systime_tc.nsec += delta;
10798 adapter->rx_tstamp_tc.nsec += delta;
10799 adapter->tx_tstamp_tc.nsec += delta;
10805 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10808 struct i40e_adapter *adapter =
10809 (struct i40e_adapter *)dev->data->dev_private;
10811 ns = rte_timespec_to_ns(ts);
10813 /* Set the timecounters to a new value. */
10814 adapter->systime_tc.nsec = ns;
10815 adapter->rx_tstamp_tc.nsec = ns;
10816 adapter->tx_tstamp_tc.nsec = ns;
10822 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10824 uint64_t ns, systime_cycles;
10825 struct i40e_adapter *adapter =
10826 (struct i40e_adapter *)dev->data->dev_private;
10828 systime_cycles = i40e_read_systime_cyclecounter(dev);
10829 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10830 *ts = rte_ns_to_timespec(ns);
10836 i40e_timesync_enable(struct rte_eth_dev *dev)
10838 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10839 uint32_t tsync_ctl_l;
10840 uint32_t tsync_ctl_h;
10842 /* Stop the timesync system time. */
10843 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10844 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10845 /* Reset the timesync system time value. */
10846 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10847 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10849 i40e_start_timecounters(dev);
10851 /* Clear timesync registers. */
10852 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10853 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10854 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10855 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10856 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10857 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10859 /* Enable timestamping of PTP packets. */
10860 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10861 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10863 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10864 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10865 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10867 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10868 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10874 i40e_timesync_disable(struct rte_eth_dev *dev)
10876 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10877 uint32_t tsync_ctl_l;
10878 uint32_t tsync_ctl_h;
10880 /* Disable timestamping of transmitted PTP packets. */
10881 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10882 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10884 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10885 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10887 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10888 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10890 /* Reset the timesync increment value. */
10891 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10892 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10898 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10899 struct timespec *timestamp, uint32_t flags)
10901 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10902 struct i40e_adapter *adapter =
10903 (struct i40e_adapter *)dev->data->dev_private;
10905 uint32_t sync_status;
10906 uint32_t index = flags & 0x03;
10907 uint64_t rx_tstamp_cycles;
10910 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10911 if ((sync_status & (1 << index)) == 0)
10914 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10915 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10916 *timestamp = rte_ns_to_timespec(ns);
10922 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10923 struct timespec *timestamp)
10925 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10926 struct i40e_adapter *adapter =
10927 (struct i40e_adapter *)dev->data->dev_private;
10929 uint32_t sync_status;
10930 uint64_t tx_tstamp_cycles;
10933 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10934 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10937 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10938 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10939 *timestamp = rte_ns_to_timespec(ns);
10945 * i40e_parse_dcb_configure - parse dcb configure from user
10946 * @dev: the device being configured
10947 * @dcb_cfg: pointer of the result of parse
10948 * @*tc_map: bit map of enabled traffic classes
10950 * Returns 0 on success, negative value on failure
10953 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10954 struct i40e_dcbx_config *dcb_cfg,
10957 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10958 uint8_t i, tc_bw, bw_lf;
10960 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10962 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10963 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10964 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10968 /* assume each tc has the same bw */
10969 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10970 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10971 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10972 /* to ensure the sum of tcbw is equal to 100 */
10973 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10974 for (i = 0; i < bw_lf; i++)
10975 dcb_cfg->etscfg.tcbwtable[i]++;
10977 /* assume each tc has the same Transmission Selection Algorithm */
10978 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10979 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10981 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10982 dcb_cfg->etscfg.prioritytable[i] =
10983 dcb_rx_conf->dcb_tc[i];
10985 /* FW needs one App to configure HW */
10986 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10987 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10988 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10989 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10991 if (dcb_rx_conf->nb_tcs == 0)
10992 *tc_map = 1; /* tc0 only */
10994 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10996 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10997 dcb_cfg->pfc.willing = 0;
10998 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10999 dcb_cfg->pfc.pfcenable = *tc_map;
11005 static enum i40e_status_code
11006 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11007 struct i40e_aqc_vsi_properties_data *info,
11008 uint8_t enabled_tcmap)
11010 enum i40e_status_code ret;
11011 int i, total_tc = 0;
11012 uint16_t qpnum_per_tc, bsf, qp_idx;
11013 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11014 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11015 uint16_t used_queues;
11017 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11018 if (ret != I40E_SUCCESS)
11021 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11022 if (enabled_tcmap & (1 << i))
11027 vsi->enabled_tc = enabled_tcmap;
11029 /* different VSI has different queues assigned */
11030 if (vsi->type == I40E_VSI_MAIN)
11031 used_queues = dev_data->nb_rx_queues -
11032 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11033 else if (vsi->type == I40E_VSI_VMDQ2)
11034 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11036 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11037 return I40E_ERR_NO_AVAILABLE_VSI;
11040 qpnum_per_tc = used_queues / total_tc;
11041 /* Number of queues per enabled TC */
11042 if (qpnum_per_tc == 0) {
11043 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11044 return I40E_ERR_INVALID_QP_ID;
11046 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11047 I40E_MAX_Q_PER_TC);
11048 bsf = rte_bsf32(qpnum_per_tc);
11051 * Configure TC and queue mapping parameters, for enabled TC,
11052 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11053 * default queue will serve it.
11056 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11057 if (vsi->enabled_tc & (1 << i)) {
11058 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11059 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11060 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11061 qp_idx += qpnum_per_tc;
11063 info->tc_mapping[i] = 0;
11066 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11067 if (vsi->type == I40E_VSI_SRIOV) {
11068 info->mapping_flags |=
11069 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11070 for (i = 0; i < vsi->nb_qps; i++)
11071 info->queue_mapping[i] =
11072 rte_cpu_to_le_16(vsi->base_queue + i);
11074 info->mapping_flags |=
11075 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11076 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11078 info->valid_sections |=
11079 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11081 return I40E_SUCCESS;
11085 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11086 * @veb: VEB to be configured
11087 * @tc_map: enabled TC bitmap
11089 * Returns 0 on success, negative value on failure
11091 static enum i40e_status_code
11092 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11094 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11095 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11096 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11097 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11098 enum i40e_status_code ret = I40E_SUCCESS;
11102 /* Check if enabled_tc is same as existing or new TCs */
11103 if (veb->enabled_tc == tc_map)
11106 /* configure tc bandwidth */
11107 memset(&veb_bw, 0, sizeof(veb_bw));
11108 veb_bw.tc_valid_bits = tc_map;
11109 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11110 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11111 if (tc_map & BIT_ULL(i))
11112 veb_bw.tc_bw_share_credits[i] = 1;
11114 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11118 "AQ command Config switch_comp BW allocation per TC failed = %d",
11119 hw->aq.asq_last_status);
11123 memset(&ets_query, 0, sizeof(ets_query));
11124 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11126 if (ret != I40E_SUCCESS) {
11128 "Failed to get switch_comp ETS configuration %u",
11129 hw->aq.asq_last_status);
11132 memset(&bw_query, 0, sizeof(bw_query));
11133 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11135 if (ret != I40E_SUCCESS) {
11137 "Failed to get switch_comp bandwidth configuration %u",
11138 hw->aq.asq_last_status);
11142 /* store and print out BW info */
11143 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11144 veb->bw_info.bw_max = ets_query.tc_bw_max;
11145 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11146 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11147 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11148 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11149 I40E_16_BIT_WIDTH);
11150 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11151 veb->bw_info.bw_ets_share_credits[i] =
11152 bw_query.tc_bw_share_credits[i];
11153 veb->bw_info.bw_ets_credits[i] =
11154 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11155 /* 4 bits per TC, 4th bit is reserved */
11156 veb->bw_info.bw_ets_max[i] =
11157 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11158 RTE_LEN2MASK(3, uint8_t));
11159 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11160 veb->bw_info.bw_ets_share_credits[i]);
11161 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11162 veb->bw_info.bw_ets_credits[i]);
11163 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11164 veb->bw_info.bw_ets_max[i]);
11167 veb->enabled_tc = tc_map;
11174 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11175 * @vsi: VSI to be configured
11176 * @tc_map: enabled TC bitmap
11178 * Returns 0 on success, negative value on failure
11180 static enum i40e_status_code
11181 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11183 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11184 struct i40e_vsi_context ctxt;
11185 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11186 enum i40e_status_code ret = I40E_SUCCESS;
11189 /* Check if enabled_tc is same as existing or new TCs */
11190 if (vsi->enabled_tc == tc_map)
11193 /* configure tc bandwidth */
11194 memset(&bw_data, 0, sizeof(bw_data));
11195 bw_data.tc_valid_bits = tc_map;
11196 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11197 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11198 if (tc_map & BIT_ULL(i))
11199 bw_data.tc_bw_credits[i] = 1;
11201 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11204 "AQ command Config VSI BW allocation per TC failed = %d",
11205 hw->aq.asq_last_status);
11208 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11209 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11211 /* Update Queue Pairs Mapping for currently enabled UPs */
11212 ctxt.seid = vsi->seid;
11213 ctxt.pf_num = hw->pf_id;
11215 ctxt.uplink_seid = vsi->uplink_seid;
11216 ctxt.info = vsi->info;
11218 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11222 /* Update the VSI after updating the VSI queue-mapping information */
11223 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11225 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11226 hw->aq.asq_last_status);
11229 /* update the local VSI info with updated queue map */
11230 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11231 sizeof(vsi->info.tc_mapping));
11232 rte_memcpy(&vsi->info.queue_mapping,
11233 &ctxt.info.queue_mapping,
11234 sizeof(vsi->info.queue_mapping));
11235 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11236 vsi->info.valid_sections = 0;
11238 /* query and update current VSI BW information */
11239 ret = i40e_vsi_get_bw_config(vsi);
11242 "Failed updating vsi bw info, err %s aq_err %s",
11243 i40e_stat_str(hw, ret),
11244 i40e_aq_str(hw, hw->aq.asq_last_status));
11248 vsi->enabled_tc = tc_map;
11255 * i40e_dcb_hw_configure - program the dcb setting to hw
11256 * @pf: pf the configuration is taken on
11257 * @new_cfg: new configuration
11258 * @tc_map: enabled TC bitmap
11260 * Returns 0 on success, negative value on failure
11262 static enum i40e_status_code
11263 i40e_dcb_hw_configure(struct i40e_pf *pf,
11264 struct i40e_dcbx_config *new_cfg,
11267 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11268 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11269 struct i40e_vsi *main_vsi = pf->main_vsi;
11270 struct i40e_vsi_list *vsi_list;
11271 enum i40e_status_code ret;
11275 /* Use the FW API if FW > v4.4*/
11276 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11277 (hw->aq.fw_maj_ver >= 5))) {
11279 "FW < v4.4, can not use FW LLDP API to configure DCB");
11280 return I40E_ERR_FIRMWARE_API_VERSION;
11283 /* Check if need reconfiguration */
11284 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11285 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11286 return I40E_SUCCESS;
11289 /* Copy the new config to the current config */
11290 *old_cfg = *new_cfg;
11291 old_cfg->etsrec = old_cfg->etscfg;
11292 ret = i40e_set_dcb_config(hw);
11294 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11295 i40e_stat_str(hw, ret),
11296 i40e_aq_str(hw, hw->aq.asq_last_status));
11299 /* set receive Arbiter to RR mode and ETS scheme by default */
11300 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11301 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11302 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11303 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11304 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11305 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11306 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11307 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11308 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11309 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11310 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11311 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11312 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11314 /* get local mib to check whether it is configured correctly */
11316 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11317 /* Get Local DCB Config */
11318 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11319 &hw->local_dcbx_config);
11321 /* if Veb is created, need to update TC of it at first */
11322 if (main_vsi->veb) {
11323 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11325 PMD_INIT_LOG(WARNING,
11326 "Failed configuring TC for VEB seid=%d",
11327 main_vsi->veb->seid);
11329 /* Update each VSI */
11330 i40e_vsi_config_tc(main_vsi, tc_map);
11331 if (main_vsi->veb) {
11332 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11333 /* Beside main VSI and VMDQ VSIs, only enable default
11334 * TC for other VSIs
11336 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11337 ret = i40e_vsi_config_tc(vsi_list->vsi,
11340 ret = i40e_vsi_config_tc(vsi_list->vsi,
11341 I40E_DEFAULT_TCMAP);
11343 PMD_INIT_LOG(WARNING,
11344 "Failed configuring TC for VSI seid=%d",
11345 vsi_list->vsi->seid);
11349 return I40E_SUCCESS;
11353 * i40e_dcb_init_configure - initial dcb config
11354 * @dev: device being configured
11355 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11357 * Returns 0 on success, negative value on failure
11360 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11362 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11366 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11367 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11371 /* DCB initialization:
11372 * Update DCB configuration from the Firmware and configure
11373 * LLDP MIB change event.
11375 if (sw_dcb == TRUE) {
11376 /* When using NVM 6.01 or later, the RX data path does
11377 * not hang if the FW LLDP is stopped.
11379 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11380 ((hw->nvm.version >> 4) & 0xff) >= 1) {
11381 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11382 if (ret != I40E_SUCCESS)
11383 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11386 ret = i40e_init_dcb(hw);
11387 /* If lldp agent is stopped, the return value from
11388 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11389 * adminq status. Otherwise, it should return success.
11391 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11392 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11393 memset(&hw->local_dcbx_config, 0,
11394 sizeof(struct i40e_dcbx_config));
11395 /* set dcb default configuration */
11396 hw->local_dcbx_config.etscfg.willing = 0;
11397 hw->local_dcbx_config.etscfg.maxtcs = 0;
11398 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11399 hw->local_dcbx_config.etscfg.tsatable[0] =
11401 /* all UPs mapping to TC0 */
11402 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11403 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11404 hw->local_dcbx_config.etsrec =
11405 hw->local_dcbx_config.etscfg;
11406 hw->local_dcbx_config.pfc.willing = 0;
11407 hw->local_dcbx_config.pfc.pfccap =
11408 I40E_MAX_TRAFFIC_CLASS;
11409 /* FW needs one App to configure HW */
11410 hw->local_dcbx_config.numapps = 1;
11411 hw->local_dcbx_config.app[0].selector =
11412 I40E_APP_SEL_ETHTYPE;
11413 hw->local_dcbx_config.app[0].priority = 3;
11414 hw->local_dcbx_config.app[0].protocolid =
11415 I40E_APP_PROTOID_FCOE;
11416 ret = i40e_set_dcb_config(hw);
11419 "default dcb config fails. err = %d, aq_err = %d.",
11420 ret, hw->aq.asq_last_status);
11425 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11426 ret, hw->aq.asq_last_status);
11430 ret = i40e_aq_start_lldp(hw, NULL);
11431 if (ret != I40E_SUCCESS)
11432 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11434 ret = i40e_init_dcb(hw);
11436 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11438 "HW doesn't support DCBX offload.");
11443 "DCBX configuration failed, err = %d, aq_err = %d.",
11444 ret, hw->aq.asq_last_status);
11452 * i40e_dcb_setup - setup dcb related config
11453 * @dev: device being configured
11455 * Returns 0 on success, negative value on failure
11458 i40e_dcb_setup(struct rte_eth_dev *dev)
11460 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11461 struct i40e_dcbx_config dcb_cfg;
11462 uint8_t tc_map = 0;
11465 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11466 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11470 if (pf->vf_num != 0)
11471 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11473 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11475 PMD_INIT_LOG(ERR, "invalid dcb config");
11478 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11480 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11488 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11489 struct rte_eth_dcb_info *dcb_info)
11491 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11492 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11493 struct i40e_vsi *vsi = pf->main_vsi;
11494 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11495 uint16_t bsf, tc_mapping;
11498 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11499 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11501 dcb_info->nb_tcs = 1;
11502 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11503 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11504 for (i = 0; i < dcb_info->nb_tcs; i++)
11505 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11507 /* get queue mapping if vmdq is disabled */
11508 if (!pf->nb_cfg_vmdq_vsi) {
11509 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11510 if (!(vsi->enabled_tc & (1 << i)))
11512 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11513 dcb_info->tc_queue.tc_rxq[j][i].base =
11514 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11515 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11516 dcb_info->tc_queue.tc_txq[j][i].base =
11517 dcb_info->tc_queue.tc_rxq[j][i].base;
11518 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11519 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11520 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11521 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11522 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11527 /* get queue mapping if vmdq is enabled */
11529 vsi = pf->vmdq[j].vsi;
11530 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11531 if (!(vsi->enabled_tc & (1 << i)))
11533 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11534 dcb_info->tc_queue.tc_rxq[j][i].base =
11535 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11536 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11537 dcb_info->tc_queue.tc_txq[j][i].base =
11538 dcb_info->tc_queue.tc_rxq[j][i].base;
11539 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11540 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11541 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11542 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11543 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11546 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11551 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11553 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11554 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11555 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11556 uint16_t msix_intr;
11558 msix_intr = intr_handle->intr_vec[queue_id];
11559 if (msix_intr == I40E_MISC_VEC_ID)
11560 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11561 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11562 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11563 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11566 I40E_PFINT_DYN_CTLN(msix_intr -
11567 I40E_RX_VEC_START),
11568 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11569 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11570 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11572 I40E_WRITE_FLUSH(hw);
11573 rte_intr_enable(&pci_dev->intr_handle);
11579 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11581 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11582 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11583 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11584 uint16_t msix_intr;
11586 msix_intr = intr_handle->intr_vec[queue_id];
11587 if (msix_intr == I40E_MISC_VEC_ID)
11588 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11589 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11592 I40E_PFINT_DYN_CTLN(msix_intr -
11593 I40E_RX_VEC_START),
11594 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11595 I40E_WRITE_FLUSH(hw);
11600 static int i40e_get_regs(struct rte_eth_dev *dev,
11601 struct rte_dev_reg_info *regs)
11603 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11604 uint32_t *ptr_data = regs->data;
11605 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11606 const struct i40e_reg_info *reg_info;
11608 if (ptr_data == NULL) {
11609 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11610 regs->width = sizeof(uint32_t);
11614 /* The first few registers have to be read using AQ operations */
11616 while (i40e_regs_adminq[reg_idx].name) {
11617 reg_info = &i40e_regs_adminq[reg_idx++];
11618 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11620 arr_idx2 <= reg_info->count2;
11622 reg_offset = arr_idx * reg_info->stride1 +
11623 arr_idx2 * reg_info->stride2;
11624 reg_offset += reg_info->base_addr;
11625 ptr_data[reg_offset >> 2] =
11626 i40e_read_rx_ctl(hw, reg_offset);
11630 /* The remaining registers can be read using primitives */
11632 while (i40e_regs_others[reg_idx].name) {
11633 reg_info = &i40e_regs_others[reg_idx++];
11634 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11636 arr_idx2 <= reg_info->count2;
11638 reg_offset = arr_idx * reg_info->stride1 +
11639 arr_idx2 * reg_info->stride2;
11640 reg_offset += reg_info->base_addr;
11641 ptr_data[reg_offset >> 2] =
11642 I40E_READ_REG(hw, reg_offset);
11649 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11653 /* Convert word count to byte count */
11654 return hw->nvm.sr_size << 1;
11657 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11658 struct rte_dev_eeprom_info *eeprom)
11660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11661 uint16_t *data = eeprom->data;
11662 uint16_t offset, length, cnt_words;
11665 offset = eeprom->offset >> 1;
11666 length = eeprom->length >> 1;
11667 cnt_words = length;
11669 if (offset > hw->nvm.sr_size ||
11670 offset + length > hw->nvm.sr_size) {
11671 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11675 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11677 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11678 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11679 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11686 static int i40e_get_module_info(struct rte_eth_dev *dev,
11687 struct rte_eth_dev_module_info *modinfo)
11689 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11690 uint32_t sff8472_comp = 0;
11691 uint32_t sff8472_swap = 0;
11692 uint32_t sff8636_rev = 0;
11693 i40e_status status;
11696 /* Check if firmware supports reading module EEPROM. */
11697 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11699 "Module EEPROM memory read not supported. "
11700 "Please update the NVM image.\n");
11704 status = i40e_update_link_info(hw);
11708 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11710 "Cannot read module EEPROM memory. "
11711 "No module connected.\n");
11715 type = hw->phy.link_info.module_type[0];
11718 case I40E_MODULE_TYPE_SFP:
11719 status = i40e_aq_get_phy_register(hw,
11720 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11721 I40E_I2C_EEPROM_DEV_ADDR,
11722 I40E_MODULE_SFF_8472_COMP,
11723 &sff8472_comp, NULL);
11727 status = i40e_aq_get_phy_register(hw,
11728 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11729 I40E_I2C_EEPROM_DEV_ADDR,
11730 I40E_MODULE_SFF_8472_SWAP,
11731 &sff8472_swap, NULL);
11735 /* Check if the module requires address swap to access
11736 * the other EEPROM memory page.
11738 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11739 PMD_DRV_LOG(WARNING,
11740 "Module address swap to access "
11741 "page 0xA2 is not supported.\n");
11742 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11743 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11744 } else if (sff8472_comp == 0x00) {
11745 /* Module is not SFF-8472 compliant */
11746 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11747 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11749 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11750 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11753 case I40E_MODULE_TYPE_QSFP_PLUS:
11754 /* Read from memory page 0. */
11755 status = i40e_aq_get_phy_register(hw,
11756 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11758 I40E_MODULE_REVISION_ADDR,
11759 &sff8636_rev, NULL);
11762 /* Determine revision compliance byte */
11763 if (sff8636_rev > 0x02) {
11764 /* Module is SFF-8636 compliant */
11765 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11766 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11768 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11769 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11772 case I40E_MODULE_TYPE_QSFP28:
11773 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11774 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11777 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11783 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11784 struct rte_dev_eeprom_info *info)
11786 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11787 bool is_sfp = false;
11788 i40e_status status;
11789 uint8_t *data = info->data;
11790 uint32_t value = 0;
11793 if (!info || !info->length || !data)
11796 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11799 for (i = 0; i < info->length; i++) {
11800 u32 offset = i + info->offset;
11801 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11803 /* Check if we need to access the other memory page */
11805 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11806 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11807 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11810 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11811 /* Compute memory page number and offset. */
11812 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11816 status = i40e_aq_get_phy_register(hw,
11817 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11818 addr, offset, &value, NULL);
11821 data[i] = (uint8_t)value;
11826 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11827 struct ether_addr *mac_addr)
11829 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11830 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11831 struct i40e_vsi *vsi = pf->main_vsi;
11832 struct i40e_mac_filter_info mac_filter;
11833 struct i40e_mac_filter *f;
11836 if (!is_valid_assigned_ether_addr(mac_addr)) {
11837 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11841 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11842 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11847 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11851 mac_filter = f->mac_info;
11852 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11853 if (ret != I40E_SUCCESS) {
11854 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11857 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11858 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11859 if (ret != I40E_SUCCESS) {
11860 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11863 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11865 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11866 mac_addr->addr_bytes, NULL);
11867 if (ret != I40E_SUCCESS) {
11868 PMD_DRV_LOG(ERR, "Failed to change mac");
11876 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11878 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11879 struct rte_eth_dev_data *dev_data = pf->dev_data;
11880 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11883 /* check if mtu is within the allowed range */
11884 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11887 /* mtu setting is forbidden if port is start */
11888 if (dev_data->dev_started) {
11889 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11890 dev_data->port_id);
11894 if (frame_size > ETHER_MAX_LEN)
11895 dev_data->dev_conf.rxmode.offloads |=
11896 DEV_RX_OFFLOAD_JUMBO_FRAME;
11898 dev_data->dev_conf.rxmode.offloads &=
11899 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11901 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11906 /* Restore ethertype filter */
11908 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11910 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11911 struct i40e_ethertype_filter_list
11912 *ethertype_list = &pf->ethertype.ethertype_list;
11913 struct i40e_ethertype_filter *f;
11914 struct i40e_control_filter_stats stats;
11917 TAILQ_FOREACH(f, ethertype_list, rules) {
11919 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11920 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11921 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11922 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11923 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11925 memset(&stats, 0, sizeof(stats));
11926 i40e_aq_add_rem_control_packet_filter(hw,
11927 f->input.mac_addr.addr_bytes,
11928 f->input.ether_type,
11929 flags, pf->main_vsi->seid,
11930 f->queue, 1, &stats, NULL);
11932 PMD_DRV_LOG(INFO, "Ethertype filter:"
11933 " mac_etype_used = %u, etype_used = %u,"
11934 " mac_etype_free = %u, etype_free = %u",
11935 stats.mac_etype_used, stats.etype_used,
11936 stats.mac_etype_free, stats.etype_free);
11939 /* Restore tunnel filter */
11941 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11943 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11944 struct i40e_vsi *vsi;
11945 struct i40e_pf_vf *vf;
11946 struct i40e_tunnel_filter_list
11947 *tunnel_list = &pf->tunnel.tunnel_list;
11948 struct i40e_tunnel_filter *f;
11949 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11950 bool big_buffer = 0;
11952 TAILQ_FOREACH(f, tunnel_list, rules) {
11954 vsi = pf->main_vsi;
11956 vf = &pf->vfs[f->vf_id];
11959 memset(&cld_filter, 0, sizeof(cld_filter));
11960 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11961 (struct ether_addr *)&cld_filter.element.outer_mac);
11962 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11963 (struct ether_addr *)&cld_filter.element.inner_mac);
11964 cld_filter.element.inner_vlan = f->input.inner_vlan;
11965 cld_filter.element.flags = f->input.flags;
11966 cld_filter.element.tenant_id = f->input.tenant_id;
11967 cld_filter.element.queue_number = f->queue;
11968 rte_memcpy(cld_filter.general_fields,
11969 f->input.general_fields,
11970 sizeof(f->input.general_fields));
11972 if (((f->input.flags &
11973 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11974 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11976 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11977 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11979 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11980 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11984 i40e_aq_add_cloud_filters_big_buffer(hw,
11985 vsi->seid, &cld_filter, 1);
11987 i40e_aq_add_cloud_filters(hw, vsi->seid,
11988 &cld_filter.element, 1);
11992 /* Restore rss filter */
11994 i40e_rss_filter_restore(struct i40e_pf *pf)
11996 struct i40e_rte_flow_rss_conf *conf =
11998 if (conf->conf.queue_num)
11999 i40e_config_rss_filter(pf, conf, TRUE);
12003 i40e_filter_restore(struct i40e_pf *pf)
12005 i40e_ethertype_filter_restore(pf);
12006 i40e_tunnel_filter_restore(pf);
12007 i40e_fdir_filter_restore(pf);
12008 i40e_rss_filter_restore(pf);
12012 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12014 if (strcmp(dev->device->driver->name, drv->driver.name))
12021 is_i40e_supported(struct rte_eth_dev *dev)
12023 return is_device_supported(dev, &rte_i40e_pmd);
12026 struct i40e_customized_pctype*
12027 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12031 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12032 if (pf->customized_pctype[i].index == index)
12033 return &pf->customized_pctype[i];
12039 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12040 uint32_t pkg_size, uint32_t proto_num,
12041 struct rte_pmd_i40e_proto_info *proto,
12042 enum rte_pmd_i40e_package_op op)
12044 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12045 uint32_t pctype_num;
12046 struct rte_pmd_i40e_ptype_info *pctype;
12047 uint32_t buff_size;
12048 struct i40e_customized_pctype *new_pctype = NULL;
12050 uint8_t pctype_value;
12055 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12056 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12057 PMD_DRV_LOG(ERR, "Unsupported operation.");
12061 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12062 (uint8_t *)&pctype_num, sizeof(pctype_num),
12063 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12065 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12069 PMD_DRV_LOG(INFO, "No new pctype added");
12073 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12074 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12076 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12079 /* get information about new pctype list */
12080 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12081 (uint8_t *)pctype, buff_size,
12082 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12084 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12089 /* Update customized pctype. */
12090 for (i = 0; i < pctype_num; i++) {
12091 pctype_value = pctype[i].ptype_id;
12092 memset(name, 0, sizeof(name));
12093 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12094 proto_id = pctype[i].protocols[j];
12095 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12097 for (n = 0; n < proto_num; n++) {
12098 if (proto[n].proto_id != proto_id)
12100 strcat(name, proto[n].name);
12105 name[strlen(name) - 1] = '\0';
12106 if (!strcmp(name, "GTPC"))
12108 i40e_find_customized_pctype(pf,
12109 I40E_CUSTOMIZED_GTPC);
12110 else if (!strcmp(name, "GTPU_IPV4"))
12112 i40e_find_customized_pctype(pf,
12113 I40E_CUSTOMIZED_GTPU_IPV4);
12114 else if (!strcmp(name, "GTPU_IPV6"))
12116 i40e_find_customized_pctype(pf,
12117 I40E_CUSTOMIZED_GTPU_IPV6);
12118 else if (!strcmp(name, "GTPU"))
12120 i40e_find_customized_pctype(pf,
12121 I40E_CUSTOMIZED_GTPU);
12123 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12124 new_pctype->pctype = pctype_value;
12125 new_pctype->valid = true;
12127 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12128 new_pctype->valid = false;
12138 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12139 uint32_t pkg_size, uint32_t proto_num,
12140 struct rte_pmd_i40e_proto_info *proto,
12141 enum rte_pmd_i40e_package_op op)
12143 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12144 uint16_t port_id = dev->data->port_id;
12145 uint32_t ptype_num;
12146 struct rte_pmd_i40e_ptype_info *ptype;
12147 uint32_t buff_size;
12149 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12154 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12155 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12156 PMD_DRV_LOG(ERR, "Unsupported operation.");
12160 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12161 rte_pmd_i40e_ptype_mapping_reset(port_id);
12165 /* get information about new ptype num */
12166 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12167 (uint8_t *)&ptype_num, sizeof(ptype_num),
12168 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12170 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12174 PMD_DRV_LOG(INFO, "No new ptype added");
12178 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12179 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12181 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12185 /* get information about new ptype list */
12186 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12187 (uint8_t *)ptype, buff_size,
12188 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12190 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12195 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12196 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12197 if (!ptype_mapping) {
12198 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12203 /* Update ptype mapping table. */
12204 for (i = 0; i < ptype_num; i++) {
12205 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12206 ptype_mapping[i].sw_ptype = 0;
12208 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12209 proto_id = ptype[i].protocols[j];
12210 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12212 for (n = 0; n < proto_num; n++) {
12213 if (proto[n].proto_id != proto_id)
12215 memset(name, 0, sizeof(name));
12216 strcpy(name, proto[n].name);
12217 if (!strncasecmp(name, "PPPOE", 5))
12218 ptype_mapping[i].sw_ptype |=
12219 RTE_PTYPE_L2_ETHER_PPPOE;
12220 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12222 ptype_mapping[i].sw_ptype |=
12223 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12224 ptype_mapping[i].sw_ptype |=
12226 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12228 ptype_mapping[i].sw_ptype |=
12229 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12230 ptype_mapping[i].sw_ptype |=
12231 RTE_PTYPE_INNER_L4_FRAG;
12232 } else if (!strncasecmp(name, "OIPV4", 5)) {
12233 ptype_mapping[i].sw_ptype |=
12234 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12236 } else if (!strncasecmp(name, "IPV4", 4) &&
12238 ptype_mapping[i].sw_ptype |=
12239 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12240 else if (!strncasecmp(name, "IPV4", 4) &&
12242 ptype_mapping[i].sw_ptype |=
12243 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12244 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12246 ptype_mapping[i].sw_ptype |=
12247 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12248 ptype_mapping[i].sw_ptype |=
12250 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12252 ptype_mapping[i].sw_ptype |=
12253 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12254 ptype_mapping[i].sw_ptype |=
12255 RTE_PTYPE_INNER_L4_FRAG;
12256 } else if (!strncasecmp(name, "OIPV6", 5)) {
12257 ptype_mapping[i].sw_ptype |=
12258 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12260 } else if (!strncasecmp(name, "IPV6", 4) &&
12262 ptype_mapping[i].sw_ptype |=
12263 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12264 else if (!strncasecmp(name, "IPV6", 4) &&
12266 ptype_mapping[i].sw_ptype |=
12267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12268 else if (!strncasecmp(name, "UDP", 3) &&
12270 ptype_mapping[i].sw_ptype |=
12272 else if (!strncasecmp(name, "UDP", 3) &&
12274 ptype_mapping[i].sw_ptype |=
12275 RTE_PTYPE_INNER_L4_UDP;
12276 else if (!strncasecmp(name, "TCP", 3) &&
12278 ptype_mapping[i].sw_ptype |=
12280 else if (!strncasecmp(name, "TCP", 3) &&
12282 ptype_mapping[i].sw_ptype |=
12283 RTE_PTYPE_INNER_L4_TCP;
12284 else if (!strncasecmp(name, "SCTP", 4) &&
12286 ptype_mapping[i].sw_ptype |=
12288 else if (!strncasecmp(name, "SCTP", 4) &&
12290 ptype_mapping[i].sw_ptype |=
12291 RTE_PTYPE_INNER_L4_SCTP;
12292 else if ((!strncasecmp(name, "ICMP", 4) ||
12293 !strncasecmp(name, "ICMPV6", 6)) &&
12295 ptype_mapping[i].sw_ptype |=
12297 else if ((!strncasecmp(name, "ICMP", 4) ||
12298 !strncasecmp(name, "ICMPV6", 6)) &&
12300 ptype_mapping[i].sw_ptype |=
12301 RTE_PTYPE_INNER_L4_ICMP;
12302 else if (!strncasecmp(name, "GTPC", 4)) {
12303 ptype_mapping[i].sw_ptype |=
12304 RTE_PTYPE_TUNNEL_GTPC;
12306 } else if (!strncasecmp(name, "GTPU", 4)) {
12307 ptype_mapping[i].sw_ptype |=
12308 RTE_PTYPE_TUNNEL_GTPU;
12310 } else if (!strncasecmp(name, "GRENAT", 6)) {
12311 ptype_mapping[i].sw_ptype |=
12312 RTE_PTYPE_TUNNEL_GRENAT;
12314 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12315 !strncasecmp(name, "L2TPV2", 6)) {
12316 ptype_mapping[i].sw_ptype |=
12317 RTE_PTYPE_TUNNEL_L2TP;
12326 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12329 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12331 rte_free(ptype_mapping);
12337 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12338 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12341 uint32_t proto_num;
12342 struct rte_pmd_i40e_proto_info *proto;
12343 uint32_t buff_size;
12347 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12348 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12349 PMD_DRV_LOG(ERR, "Unsupported operation.");
12353 /* get information about protocol number */
12354 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12355 (uint8_t *)&proto_num, sizeof(proto_num),
12356 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12358 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12362 PMD_DRV_LOG(INFO, "No new protocol added");
12366 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12367 proto = rte_zmalloc("new_proto", buff_size, 0);
12369 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12373 /* get information about protocol list */
12374 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12375 (uint8_t *)proto, buff_size,
12376 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12378 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12383 /* Check if GTP is supported. */
12384 for (i = 0; i < proto_num; i++) {
12385 if (!strncmp(proto[i].name, "GTP", 3)) {
12386 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12387 pf->gtp_support = true;
12389 pf->gtp_support = false;
12394 /* Update customized pctype info */
12395 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12396 proto_num, proto, op);
12398 PMD_DRV_LOG(INFO, "No pctype is updated.");
12400 /* Update customized ptype info */
12401 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12402 proto_num, proto, op);
12404 PMD_DRV_LOG(INFO, "No ptype is updated.");
12409 /* Create a QinQ cloud filter
12411 * The Fortville NIC has limited resources for tunnel filters,
12412 * so we can only reuse existing filters.
12414 * In step 1 we define which Field Vector fields can be used for
12416 * As we do not have the inner tag defined as a field,
12417 * we have to define it first, by reusing one of L1 entries.
12419 * In step 2 we are replacing one of existing filter types with
12420 * a new one for QinQ.
12421 * As we reusing L1 and replacing L2, some of the default filter
12422 * types will disappear,which depends on L1 and L2 entries we reuse.
12424 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12426 * 1. Create L1 filter of outer vlan (12b) which will be in use
12427 * later when we define the cloud filter.
12428 * a. Valid_flags.replace_cloud = 0
12429 * b. Old_filter = 10 (Stag_Inner_Vlan)
12430 * c. New_filter = 0x10
12431 * d. TR bit = 0xff (optional, not used here)
12432 * e. Buffer – 2 entries:
12433 * i. Byte 0 = 8 (outer vlan FV index).
12435 * Byte 2-3 = 0x0fff
12436 * ii. Byte 0 = 37 (inner vlan FV index).
12438 * Byte 2-3 = 0x0fff
12441 * 2. Create cloud filter using two L1 filters entries: stag and
12442 * new filter(outer vlan+ inner vlan)
12443 * a. Valid_flags.replace_cloud = 1
12444 * b. Old_filter = 1 (instead of outer IP)
12445 * c. New_filter = 0x10
12446 * d. Buffer – 2 entries:
12447 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12448 * Byte 1-3 = 0 (rsv)
12449 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12450 * Byte 9-11 = 0 (rsv)
12453 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12455 int ret = -ENOTSUP;
12456 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12457 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12458 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12459 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12461 if (pf->support_multi_driver) {
12462 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12467 memset(&filter_replace, 0,
12468 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12469 memset(&filter_replace_buf, 0,
12470 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12472 /* create L1 filter */
12473 filter_replace.old_filter_type =
12474 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12475 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12476 filter_replace.tr_bit = 0;
12478 /* Prepare the buffer, 2 entries */
12479 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12480 filter_replace_buf.data[0] |=
12481 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12482 /* Field Vector 12b mask */
12483 filter_replace_buf.data[2] = 0xff;
12484 filter_replace_buf.data[3] = 0x0f;
12485 filter_replace_buf.data[4] =
12486 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12487 filter_replace_buf.data[4] |=
12488 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12489 /* Field Vector 12b mask */
12490 filter_replace_buf.data[6] = 0xff;
12491 filter_replace_buf.data[7] = 0x0f;
12492 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12493 &filter_replace_buf);
12494 if (ret != I40E_SUCCESS)
12497 if (filter_replace.old_filter_type !=
12498 filter_replace.new_filter_type)
12499 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12500 " original: 0x%x, new: 0x%x",
12502 filter_replace.old_filter_type,
12503 filter_replace.new_filter_type);
12505 /* Apply the second L2 cloud filter */
12506 memset(&filter_replace, 0,
12507 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12508 memset(&filter_replace_buf, 0,
12509 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12511 /* create L2 filter, input for L2 filter will be L1 filter */
12512 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12513 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12514 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12516 /* Prepare the buffer, 2 entries */
12517 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12518 filter_replace_buf.data[0] |=
12519 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12520 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12521 filter_replace_buf.data[4] |=
12522 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12523 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12524 &filter_replace_buf);
12525 if (!ret && (filter_replace.old_filter_type !=
12526 filter_replace.new_filter_type))
12527 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12528 " original: 0x%x, new: 0x%x",
12530 filter_replace.old_filter_type,
12531 filter_replace.new_filter_type);
12537 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12538 const struct rte_flow_action_rss *in)
12540 if (in->key_len > RTE_DIM(out->key) ||
12541 in->queue_num > RTE_DIM(out->queue))
12543 out->conf = (struct rte_flow_action_rss){
12545 .level = in->level,
12546 .types = in->types,
12547 .key_len = in->key_len,
12548 .queue_num = in->queue_num,
12549 .key = memcpy(out->key, in->key, in->key_len),
12550 .queue = memcpy(out->queue, in->queue,
12551 sizeof(*in->queue) * in->queue_num),
12557 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12558 const struct rte_flow_action_rss *with)
12560 return (comp->func == with->func &&
12561 comp->level == with->level &&
12562 comp->types == with->types &&
12563 comp->key_len == with->key_len &&
12564 comp->queue_num == with->queue_num &&
12565 !memcmp(comp->key, with->key, with->key_len) &&
12566 !memcmp(comp->queue, with->queue,
12567 sizeof(*with->queue) * with->queue_num));
12571 i40e_config_rss_filter(struct i40e_pf *pf,
12572 struct i40e_rte_flow_rss_conf *conf, bool add)
12574 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12575 uint32_t i, lut = 0;
12577 struct rte_eth_rss_conf rss_conf = {
12578 .rss_key = conf->conf.key_len ?
12579 (void *)(uintptr_t)conf->conf.key : NULL,
12580 .rss_key_len = conf->conf.key_len,
12581 .rss_hf = conf->conf.types,
12583 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12586 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12587 i40e_pf_disable_rss(pf);
12588 memset(rss_info, 0,
12589 sizeof(struct i40e_rte_flow_rss_conf));
12595 if (rss_info->conf.queue_num)
12598 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12599 * It's necessary to calculate the actual PF queues that are configured.
12601 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12602 num = i40e_pf_calc_configured_queues_num(pf);
12604 num = pf->dev_data->nb_rx_queues;
12606 num = RTE_MIN(num, conf->conf.queue_num);
12607 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12611 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12615 /* Fill in redirection table */
12616 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12619 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12620 hw->func_caps.rss_table_entry_width) - 1));
12622 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12625 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12626 i40e_pf_disable_rss(pf);
12629 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12630 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12631 /* Random default keys */
12632 static uint32_t rss_key_default[] = {0x6b793944,
12633 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12634 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12635 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12637 rss_conf.rss_key = (uint8_t *)rss_key_default;
12638 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12642 i40e_hw_rss_hash_set(pf, &rss_conf);
12644 if (i40e_rss_conf_init(rss_info, &conf->conf))
12650 RTE_INIT(i40e_init_log)
12652 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12653 if (i40e_logtype_init >= 0)
12654 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12655 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12656 if (i40e_logtype_driver >= 0)
12657 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12660 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12661 ETH_I40E_FLOATING_VEB_ARG "=1"
12662 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12663 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12664 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12665 ETH_I40E_USE_LATEST_VEC "=0|1");