drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .id_table = pci_id_i40e_map,
 667                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 668                         RTE_PCI_DRV_DETACHABLE,
 669                 .probe = rte_eth_dev_pci_probe,
 670                 .remove = rte_eth_dev_pci_remove,
 671         },
 672         .eth_dev_init = eth_i40e_dev_init,
 673         .eth_dev_uninit = eth_i40e_dev_uninit,
 674         .dev_private_size = sizeof(struct i40e_adapter),
 675 };
 676
 677 static inline int
 678 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 679                                      struct rte_eth_link *link)
 680 {
 681         struct rte_eth_link *dst = link;
 682         struct rte_eth_link *src = &(dev->data->dev_link);
 683
 684         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 685                                         *(uint64_t *)src) == 0)
 686                 return -1;
 687
 688         return 0;
 689 }
 690
 691 static inline int
 692 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 693                                       struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = &(dev->data->dev_link);
 696         struct rte_eth_link *src = link;
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 706 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 707
 708 #ifndef I40E_GLQF_ORT
 709 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 710 #endif
 711 #ifndef I40E_GLQF_PIT
 712 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 713 #endif
 714
 715 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 716 {
 717         /*
 718          * Initialize registers for flexible payload, which should be set by NVM.
 719          * This should be removed from code once it is fixed in NVM.
 720          */
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 732         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 733
 734         /* Initialize registers for parsing packet type of QinQ */
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 736         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 737 }
 738
 739 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 740
 741 /*
 742  * Add a ethertype filter to drop all flow control frames transmitted
 743  * from VSIs.
 744 */
 745 static void
 746 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 747 {
 748         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 749         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 750                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 751                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 752         int ret;
 753
 754         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 755                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 756                                 pf->main_vsi_seid, 0,
 757                                 TRUE, NULL, NULL);
 758         if (ret)
 759                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 760                                   " frames from VSIs.");
 761 }
 762
 763 static int
 764 floating_veb_list_handler(__rte_unused const char *key,
 765                           const char *floating_veb_value,
 766                           void *opaque)
 767 {
 768         int idx = 0;
 769         unsigned int count = 0;
 770         char *end = NULL;
 771         int min, max;
 772         bool *vf_floating_veb = opaque;
 773
 774         while (isblank(*floating_veb_value))
 775                 floating_veb_value++;
 776
 777         /* Reset floating VEB configuration for VFs */
 778         for (idx = 0; idx < I40E_MAX_VF; idx++)
 779                 vf_floating_veb[idx] = false;
 780
 781         min = I40E_MAX_VF;
 782         do {
 783                 while (isblank(*floating_veb_value))
 784                         floating_veb_value++;
 785                 if (*floating_veb_value == '\0')
 786                         return -1;
 787                 errno = 0;
 788                 idx = strtoul(floating_veb_value, &end, 10);
 789                 if (errno || end == NULL)
 790                         return -1;
 791                 while (isblank(*end))
 792                         end++;
 793                 if (*end == '-') {
 794                         min = idx;
 795                 } else if ((*end == ';') || (*end == '\0')) {
 796                         max = idx;
 797                         if (min == I40E_MAX_VF)
 798                                 min = idx;
 799                         if (max >= I40E_MAX_VF)
 800                                 max = I40E_MAX_VF - 1;
 801                         for (idx = min; idx <= max; idx++) {
 802                                 vf_floating_veb[idx] = true;
 803                                 count++;
 804                         }
 805                         min = I40E_MAX_VF;
 806                 } else {
 807                         return -1;
 808                 }
 809                 floating_veb_value = end + 1;
 810         } while (*end != '\0');
 811
 812         if (count == 0)
 813                 return -1;
 814
 815         return 0;
 816 }
 817
 818 static void
 819 config_vf_floating_veb(struct rte_devargs *devargs,
 820                        uint16_t floating_veb,
 821                        bool *vf_floating_veb)
 822 {
 823         struct rte_kvargs *kvlist;
 824         int i;
 825         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 826
 827         if (!floating_veb)
 828                 return;
 829         /* All the VFs attach to the floating VEB by default
 830          * when the floating VEB is enabled.
 831          */
 832         for (i = 0; i < I40E_MAX_VF; i++)
 833                 vf_floating_veb[i] = true;
 834
 835         if (devargs == NULL)
 836                 return;
 837
 838         kvlist = rte_kvargs_parse(devargs->args, NULL);
 839         if (kvlist == NULL)
 840                 return;
 841
 842         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 843                 rte_kvargs_free(kvlist);
 844                 return;
 845         }
 846         /* When the floating_veb_list parameter exists, all the VFs
 847          * will attach to the legacy VEB firstly, then configure VFs
 848          * to the floating VEB according to the floating_veb_list.
 849          */
 850         if (rte_kvargs_process(kvlist, floating_veb_list,
 851                                floating_veb_list_handler,
 852                                vf_floating_veb) < 0) {
 853                 rte_kvargs_free(kvlist);
 854                 return;
 855         }
 856         rte_kvargs_free(kvlist);
 857 }
 858
 859 static int
 860 i40e_check_floating_handler(__rte_unused const char *key,
 861                             const char *value,
 862                             __rte_unused void *opaque)
 863 {
 864         if (strcmp(value, "1"))
 865                 return -1;
 866
 867         return 0;
 868 }
 869
 870 static int
 871 is_floating_veb_supported(struct rte_devargs *devargs)
 872 {
 873         struct rte_kvargs *kvlist;
 874         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 875
 876         if (devargs == NULL)
 877                 return 0;
 878
 879         kvlist = rte_kvargs_parse(devargs->args, NULL);
 880         if (kvlist == NULL)
 881                 return 0;
 882
 883         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 884                 rte_kvargs_free(kvlist);
 885                 return 0;
 886         }
 887         /* Floating VEB is enabled when there's key-value:
 888          * enable_floating_veb=1
 889          */
 890         if (rte_kvargs_process(kvlist, floating_veb_key,
 891                                i40e_check_floating_handler, NULL) < 0) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         rte_kvargs_free(kvlist);
 896
 897         return 1;
 898 }
 899
 900 static void
 901 config_floating_veb(struct rte_eth_dev *dev)
 902 {
 903         struct rte_pci_device *pci_dev = dev->pci_dev;
 904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906
 907         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 908
 909         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 910                 pf->floating_veb =
 911                         is_floating_veb_supported(pci_dev->device.devargs);
 912                 config_vf_floating_veb(pci_dev->device.devargs,
 913                                        pf->floating_veb,
 914                                        pf->floating_veb_list);
 915         } else {
 916                 pf->floating_veb = false;
 917         }
 918 }
 919
 920 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 921 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 922
 923 static int
 924 eth_i40e_dev_init(struct rte_eth_dev *dev)
 925 {
 926         struct rte_pci_device *pci_dev;
 927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929         struct i40e_vsi *vsi;
 930         int ret;
 931         uint32_t len;
 932         uint8_t aq_fail = 0;
 933
 934         PMD_INIT_FUNC_TRACE();
 935
 936         dev->dev_ops = &i40e_eth_dev_ops;
 937         dev->rx_pkt_burst = i40e_recv_pkts;
 938         dev->tx_pkt_burst = i40e_xmit_pkts;
 939
 940         /* for secondary processes, we don't initialise any further as primary
 941          * has already done this work. Only check we don't need a different
 942          * RX function */
 943         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 944                 i40e_set_rx_function(dev);
 945                 i40e_set_tx_function(dev);
 946                 return 0;
 947         }
 948         pci_dev = dev->pci_dev;
 949
 950         rte_eth_copy_pci_info(dev, pci_dev);
 951
 952         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 953         pf->adapter->eth_dev = dev;
 954         pf->dev_data = dev->data;
 955
 956         hw->back = I40E_PF_TO_ADAPTER(pf);
 957         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 958         if (!hw->hw_addr) {
 959                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 960                              "as address is NULL");
 961                 return -ENODEV;
 962         }
 963
 964         hw->vendor_id = pci_dev->id.vendor_id;
 965         hw->device_id = pci_dev->id.device_id;
 966         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 967         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 968         hw->bus.device = pci_dev->addr.devid;
 969         hw->bus.func = pci_dev->addr.function;
 970         hw->adapter_stopped = 0;
 971
 972         /* Make sure all is clean before doing PF reset */
 973         i40e_clear_hw(hw);
 974
 975         /* Initialize the hardware */
 976         i40e_hw_init(dev);
 977
 978         /* Reset here to make sure all is clean for each PF */
 979         ret = i40e_pf_reset(hw);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 982                 return ret;
 983         }
 984
 985         /* Initialize the shared code (base driver) */
 986         ret = i40e_init_shared_code(hw);
 987         if (ret) {
 988                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 989                 return ret;
 990         }
 991
 992         /*
 993          * To work around the NVM issue, initialize registers
 994          * for flexible payload and packet type of QinQ by
 995          * software. It should be removed once issues are fixed
 996          * in NVM.
 997          */
 998         i40e_GLQF_reg_init(hw);
 999
1000         /* Initialize the input set for filters (hash and fd) to default value */
1001         i40e_filter_input_set_init(pf);
1002
1003         /* Initialize the parameters for adminq */
1004         i40e_init_adminq_parameter(hw);
1005         ret = i40e_init_adminq(hw);
1006         if (ret != I40E_SUCCESS) {
1007                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1008                 return -EIO;
1009         }
1010         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1011                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1012                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1013                      ((hw->nvm.version >> 12) & 0xf),
1014                      ((hw->nvm.version >> 4) & 0xff),
1015                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1016
1017         /* Need the special FW version to support floating VEB */
1018         config_floating_veb(dev);
1019         /* Clear PXE mode */
1020         i40e_clear_pxe_mode(hw);
1021
1022         /*
1023          * On X710, performance number is far from the expectation on recent
1024          * firmware versions. The fix for this issue may not be integrated in
1025          * the following firmware version. So the workaround in software driver
1026          * is needed. It needs to modify the initial values of 3 internal only
1027          * registers. Note that the workaround can be removed when it is fixed
1028          * in firmware in the future.
1029          */
1030         i40e_configure_registers(hw);
1031
1032         /* Get hw capabilities */
1033         ret = i40e_get_cap(hw);
1034         if (ret != I40E_SUCCESS) {
1035                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1036                 goto err_get_capabilities;
1037         }
1038
1039         /* Initialize parameters for PF */
1040         ret = i40e_pf_parameter_init(dev);
1041         if (ret != 0) {
1042                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1043                 goto err_parameter_init;
1044         }
1045
1046         /* Initialize the queue management */
1047         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1048         if (ret < 0) {
1049                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1050                 goto err_qp_pool_init;
1051         }
1052         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1053                                 hw->func_caps.num_msix_vectors - 1);
1054         if (ret < 0) {
1055                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1056                 goto err_msix_pool_init;
1057         }
1058
1059         /* Initialize lan hmc */
1060         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1061                                 hw->func_caps.num_rx_qp, 0, 0);
1062         if (ret != I40E_SUCCESS) {
1063                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1064                 goto err_init_lan_hmc;
1065         }
1066
1067         /* Configure lan hmc */
1068         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1069         if (ret != I40E_SUCCESS) {
1070                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1071                 goto err_configure_lan_hmc;
1072         }
1073
1074         /* Get and check the mac address */
1075         i40e_get_mac_addr(hw, hw->mac.addr);
1076         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "mac address is not valid");
1078                 ret = -EIO;
1079                 goto err_get_mac_addr;
1080         }
1081         /* Copy the permanent MAC address */
1082         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1083                         (struct ether_addr *) hw->mac.perm_addr);
1084
1085         /* Disable flow control */
1086         hw->fc.requested_mode = I40E_FC_NONE;
1087         i40e_set_fc(hw, &aq_fail, TRUE);
1088
1089         /* Set the global registers with default ether type value */
1090         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1091         if (ret != I40E_SUCCESS) {
1092                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1093                              "VLAN ether type");
1094                 goto err_setup_pf_switch;
1095         }
1096
1097         /* PF setup, which includes VSI setup */
1098         ret = i40e_pf_setup(pf);
1099         if (ret) {
1100                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1101                 goto err_setup_pf_switch;
1102         }
1103
1104         /* reset all stats of the device, including pf and main vsi */
1105         i40e_dev_stats_reset(dev);
1106
1107         vsi = pf->main_vsi;
1108
1109         /* Disable double vlan by default */
1110         i40e_vsi_config_double_vlan(vsi, FALSE);
1111
1112         /* Disable S-TAG identification by default */
1113         ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1114         if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1115                 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1116                 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1117         }
1118
1119         if (!vsi->max_macaddrs)
1120                 len = ETHER_ADDR_LEN;
1121         else
1122                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1123
1124         /* Should be after VSI initialized */
1125         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1126         if (!dev->data->mac_addrs) {
1127                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1128                                         "for storing mac address");
1129                 goto err_mac_alloc;
1130         }
1131         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1132                                         &dev->data->mac_addrs[0]);
1133
1134         /* initialize pf host driver to setup SRIOV resource if applicable */
1135         i40e_pf_host_init(dev);
1136
1137         /* register callback func to eal lib */
1138         rte_intr_callback_register(&(pci_dev->intr_handle),
1139                 i40e_dev_interrupt_handler, (void *)dev);
1140
1141         /* configure and enable device interrupt */
1142         i40e_pf_config_irq0(hw, TRUE);
1143         i40e_pf_enable_irq0(hw);
1144
1145         /* enable uio intr after callback register */
1146         rte_intr_enable(&(pci_dev->intr_handle));
1147         /*
1148          * Add an ethertype filter to drop all flow control frames transmitted
1149          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1150          * frames to wire.
1151          */
1152         i40e_add_tx_flow_control_drop_filter(pf);
1153
1154         /* Set the max frame size to 0x2600 by default,
1155          * in case other drivers changed the default value.
1156          */
1157         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1158
1159         /* initialize mirror rule list */
1160         TAILQ_INIT(&pf->mirror_list);
1161
1162         /* Init dcb to sw mode by default */
1163         ret = i40e_dcb_init_configure(dev, TRUE);
1164         if (ret != I40E_SUCCESS) {
1165                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1166                 pf->flags &= ~I40E_FLAG_DCB;
1167         }
1168
1169         return 0;
1170
1171 err_mac_alloc:
1172         i40e_vsi_release(pf->main_vsi);
1173 err_setup_pf_switch:
1174 err_get_mac_addr:
1175 err_configure_lan_hmc:
1176         (void)i40e_shutdown_lan_hmc(hw);
1177 err_init_lan_hmc:
1178         i40e_res_pool_destroy(&pf->msix_pool);
1179 err_msix_pool_init:
1180         i40e_res_pool_destroy(&pf->qp_pool);
1181 err_qp_pool_init:
1182 err_parameter_init:
1183 err_get_capabilities:
1184         (void)i40e_shutdown_adminq(hw);
1185
1186         return ret;
1187 }
1188
1189 static int
1190 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1191 {
1192         struct rte_pci_device *pci_dev;
1193         struct i40e_hw *hw;
1194         struct i40e_filter_control_settings settings;
1195         int ret;
1196         uint8_t aq_fail = 0;
1197
1198         PMD_INIT_FUNC_TRACE();
1199
1200         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1201                 return 0;
1202
1203         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         pci_dev = dev->pci_dev;
1205
1206         if (hw->adapter_stopped == 0)
1207                 i40e_dev_close(dev);
1208
1209         dev->dev_ops = NULL;
1210         dev->rx_pkt_burst = NULL;
1211         dev->tx_pkt_burst = NULL;
1212
1213         /* Disable LLDP */
1214         ret = i40e_aq_stop_lldp(hw, true, NULL);
1215         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1216                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1217
1218         /* Clear PXE mode */
1219         i40e_clear_pxe_mode(hw);
1220
1221         /* Unconfigure filter control */
1222         memset(&settings, 0, sizeof(settings));
1223         ret = i40e_set_filter_control(hw, &settings);
1224         if (ret)
1225                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1226                                         ret);
1227
1228         /* Disable flow control */
1229         hw->fc.requested_mode = I40E_FC_NONE;
1230         i40e_set_fc(hw, &aq_fail, TRUE);
1231
1232         /* uninitialize pf host driver */
1233         i40e_pf_host_uninit(dev);
1234
1235         rte_free(dev->data->mac_addrs);
1236         dev->data->mac_addrs = NULL;
1237
1238         /* disable uio intr before callback unregister */
1239         rte_intr_disable(&(pci_dev->intr_handle));
1240
1241         /* register callback func to eal lib */
1242         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1243                 i40e_dev_interrupt_handler, (void *)dev);
1244
1245         return 0;
1246 }
1247
1248 static int
1249 i40e_dev_configure(struct rte_eth_dev *dev)
1250 {
1251         struct i40e_adapter *ad =
1252                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1254         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1255         int i, ret;
1256
1257         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1258          * bulk allocation or vector Rx preconditions we will reset it.
1259          */
1260         ad->rx_bulk_alloc_allowed = true;
1261         ad->rx_vec_allowed = true;
1262         ad->tx_simple_allowed = true;
1263         ad->tx_vec_allowed = true;
1264
1265         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1266                 ret = i40e_fdir_setup(pf);
1267                 if (ret != I40E_SUCCESS) {
1268                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1269                         return -ENOTSUP;
1270                 }
1271                 ret = i40e_fdir_configure(dev);
1272                 if (ret < 0) {
1273                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1274                         goto err;
1275                 }
1276         } else
1277                 i40e_fdir_teardown(pf);
1278
1279         ret = i40e_dev_init_vlan(dev);
1280         if (ret < 0)
1281                 goto err;
1282
1283         /* VMDQ setup.
1284          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1285          *  RSS setting have different requirements.
1286          *  General PMD driver call sequence are NIC init, configure,
1287          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1288          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1289          *  applicable. So, VMDQ setting has to be done before
1290          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1291          *  For RSS setting, it will try to calculate actual configured RX queue
1292          *  number, which will be available after rx_queue_setup(). dev_start()
1293          *  function is good to place RSS setup.
1294          */
1295         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1296                 ret = i40e_vmdq_setup(dev);
1297                 if (ret)
1298                         goto err;
1299         }
1300
1301         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1302                 ret = i40e_dcb_setup(dev);
1303                 if (ret) {
1304                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1305                         goto err_dcb;
1306                 }
1307         }
1308
1309         return 0;
1310
1311 err_dcb:
1312         /* need to release vmdq resource if exists */
1313         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1314                 i40e_vsi_release(pf->vmdq[i].vsi);
1315                 pf->vmdq[i].vsi = NULL;
1316         }
1317         rte_free(pf->vmdq);
1318         pf->vmdq = NULL;
1319 err:
1320         /* need to release fdir resource if exists */
1321         i40e_fdir_teardown(pf);
1322         return ret;
1323 }
1324
1325 void
1326 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1327 {
1328         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1329         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1330         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1331         uint16_t msix_vect = vsi->msix_intr;
1332         uint16_t i;
1333
1334         for (i = 0; i < vsi->nb_qps; i++) {
1335                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1336                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1337                 rte_wmb();
1338         }
1339
1340         if (vsi->type != I40E_VSI_SRIOV) {
1341                 if (!rte_intr_allow_others(intr_handle)) {
1342                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1343                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1344                         I40E_WRITE_REG(hw,
1345                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1346                                        0);
1347                 } else {
1348                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1349                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1350                         I40E_WRITE_REG(hw,
1351                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1352                                                        msix_vect - 1), 0);
1353                 }
1354         } else {
1355                 uint32_t reg;
1356                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1357                         vsi->user_param + (msix_vect - 1);
1358
1359                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1360                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1361         }
1362         I40E_WRITE_FLUSH(hw);
1363 }
1364
1365 static void
1366 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1367                        int base_queue, int nb_queue)
1368 {
1369         int i;
1370         uint32_t val;
1371         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1372
1373         /* Bind all RX queues to allocated MSIX interrupt */
1374         for (i = 0; i < nb_queue; i++) {
1375                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1376                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1377                         ((base_queue + i + 1) <<
1378                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1379                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1380                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1381
1382                 if (i == nb_queue - 1)
1383                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1384                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1385         }
1386
1387         /* Write first RX queue to Link list register as the head element */
1388         if (vsi->type != I40E_VSI_SRIOV) {
1389                 uint16_t interval =
1390                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1391
1392                 if (msix_vect == I40E_MISC_VEC_ID) {
1393                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1394                                        (base_queue <<
1395                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1396                                        (0x0 <<
1397                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1398                         I40E_WRITE_REG(hw,
1399                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1400                                        interval);
1401                 } else {
1402                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1403                                        (base_queue <<
1404                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1405                                        (0x0 <<
1406                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1407                         I40E_WRITE_REG(hw,
1408                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1409                                                        msix_vect - 1),
1410                                        interval);
1411                 }
1412         } else {
1413                 uint32_t reg;
1414
1415                 if (msix_vect == I40E_MISC_VEC_ID) {
1416                         I40E_WRITE_REG(hw,
1417                                        I40E_VPINT_LNKLST0(vsi->user_param),
1418                                        (base_queue <<
1419                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1420                                        (0x0 <<
1421                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1422                 } else {
1423                         /* num_msix_vectors_vf needs to minus irq0 */
1424                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1425                                 vsi->user_param + (msix_vect - 1);
1426
1427                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1428                                        (base_queue <<
1429                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1430                                        (0x0 <<
1431                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1432                 }
1433         }
1434
1435         I40E_WRITE_FLUSH(hw);
1436 }
1437
1438 void
1439 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1440 {
1441         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1442         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1443         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1444         uint16_t msix_vect = vsi->msix_intr;
1445         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1446         uint16_t queue_idx = 0;
1447         int record = 0;
1448         uint32_t val;
1449         int i;
1450
1451         for (i = 0; i < vsi->nb_qps; i++) {
1452                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1453                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1454         }
1455
1456         /* INTENA flag is not auto-cleared for interrupt */
1457         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1458         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1459                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1460                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1461         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1462
1463         /* VF bind interrupt */
1464         if (vsi->type == I40E_VSI_SRIOV) {
1465                 __vsi_queues_bind_intr(vsi, msix_vect,
1466                                        vsi->base_queue, vsi->nb_qps);
1467                 return;
1468         }
1469
1470         /* PF & VMDq bind interrupt */
1471         if (rte_intr_dp_is_en(intr_handle)) {
1472                 if (vsi->type == I40E_VSI_MAIN) {
1473                         queue_idx = 0;
1474                         record = 1;
1475                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1476                         struct i40e_vsi *main_vsi =
1477                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1478                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1479                         record = 1;
1480                 }
1481         }
1482
1483         for (i = 0; i < vsi->nb_used_qps; i++) {
1484                 if (nb_msix <= 1) {
1485                         if (!rte_intr_allow_others(intr_handle))
1486                                 /* allow to share MISC_VEC_ID */
1487                                 msix_vect = I40E_MISC_VEC_ID;
1488
1489                         /* no enough msix_vect, map all to one */
1490                         __vsi_queues_bind_intr(vsi, msix_vect,
1491                                                vsi->base_queue + i,
1492                                                vsi->nb_used_qps - i);
1493                         for (; !!record && i < vsi->nb_used_qps; i++)
1494                                 intr_handle->intr_vec[queue_idx + i] =
1495                                         msix_vect;
1496                         break;
1497                 }
1498                 /* 1:1 queue/msix_vect mapping */
1499                 __vsi_queues_bind_intr(vsi, msix_vect,
1500                                        vsi->base_queue + i, 1);
1501                 if (!!record)
1502                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1503
1504                 msix_vect++;
1505                 nb_msix--;
1506         }
1507 }
1508
1509 static void
1510 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1511 {
1512         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1513         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1514         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1515         uint16_t interval = i40e_calc_itr_interval(\
1516                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1517         uint16_t msix_intr, i;
1518
1519         if (rte_intr_allow_others(intr_handle))
1520                 for (i = 0; i < vsi->nb_msix; i++) {
1521                         msix_intr = vsi->msix_intr + i;
1522                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1523                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1524                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1525                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1526                                 (interval <<
1527                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1528                 }
1529         else
1530                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1531                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1532                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1533                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1534                                (interval <<
1535                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1536
1537         I40E_WRITE_FLUSH(hw);
1538 }
1539
1540 static void
1541 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1542 {
1543         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1544         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1545         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1546         uint16_t msix_intr, i;
1547
1548         if (rte_intr_allow_others(intr_handle))
1549                 for (i = 0; i < vsi->nb_msix; i++) {
1550                         msix_intr = vsi->msix_intr + i;
1551                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1552                                        0);
1553                 }
1554         else
1555                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1556
1557         I40E_WRITE_FLUSH(hw);
1558 }
1559
1560 static inline uint8_t
1561 i40e_parse_link_speeds(uint16_t link_speeds)
1562 {
1563         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1564
1565         if (link_speeds & ETH_LINK_SPEED_40G)
1566                 link_speed |= I40E_LINK_SPEED_40GB;
1567         if (link_speeds & ETH_LINK_SPEED_20G)
1568                 link_speed |= I40E_LINK_SPEED_20GB;
1569         if (link_speeds & ETH_LINK_SPEED_10G)
1570                 link_speed |= I40E_LINK_SPEED_10GB;
1571         if (link_speeds & ETH_LINK_SPEED_1G)
1572                 link_speed |= I40E_LINK_SPEED_1GB;
1573         if (link_speeds & ETH_LINK_SPEED_100M)
1574                 link_speed |= I40E_LINK_SPEED_100MB;
1575
1576         return link_speed;
1577 }
1578
1579 static int
1580 i40e_phy_conf_link(struct i40e_hw *hw,
1581                    uint8_t abilities,
1582                    uint8_t force_speed)
1583 {
1584         enum i40e_status_code status;
1585         struct i40e_aq_get_phy_abilities_resp phy_ab;
1586         struct i40e_aq_set_phy_config phy_conf;
1587         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1588                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1589                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1590                         I40E_AQ_PHY_FLAG_LOW_POWER;
1591         const uint8_t advt = I40E_LINK_SPEED_40GB |
1592                         I40E_LINK_SPEED_10GB |
1593                         I40E_LINK_SPEED_1GB |
1594                         I40E_LINK_SPEED_100MB;
1595         int ret = -ENOTSUP;
1596
1597
1598         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1599                                               NULL);
1600         if (status)
1601                 return ret;
1602
1603         memset(&phy_conf, 0, sizeof(phy_conf));
1604
1605         /* bits 0-2 use the values from get_phy_abilities_resp */
1606         abilities &= ~mask;
1607         abilities |= phy_ab.abilities & mask;
1608
1609         /* update ablities and speed */
1610         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1611                 phy_conf.link_speed = advt;
1612         else
1613                 phy_conf.link_speed = force_speed;
1614
1615         phy_conf.abilities = abilities;
1616
1617         /* use get_phy_abilities_resp value for the rest */
1618         phy_conf.phy_type = phy_ab.phy_type;
1619         phy_conf.eee_capability = phy_ab.eee_capability;
1620         phy_conf.eeer = phy_ab.eeer_val;
1621         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1622
1623         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1624                     phy_ab.abilities, phy_ab.link_speed);
1625         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1626                     phy_conf.abilities, phy_conf.link_speed);
1627
1628         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1629         if (status)
1630                 return ret;
1631
1632         return I40E_SUCCESS;
1633 }
1634
1635 static int
1636 i40e_apply_link_speed(struct rte_eth_dev *dev)
1637 {
1638         uint8_t speed;
1639         uint8_t abilities = 0;
1640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1641         struct rte_eth_conf *conf = &dev->data->dev_conf;
1642
1643         speed = i40e_parse_link_speeds(conf->link_speeds);
1644         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1645         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1646                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1647         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1648
1649         /* Skip changing speed on 40G interfaces, FW does not support */
1650         if (i40e_is_40G_device(hw->device_id)) {
1651                 speed =  I40E_LINK_SPEED_UNKNOWN;
1652                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1653         }
1654
1655         return i40e_phy_conf_link(hw, abilities, speed);
1656 }
1657
1658 static int
1659 i40e_dev_start(struct rte_eth_dev *dev)
1660 {
1661         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         struct i40e_vsi *main_vsi = pf->main_vsi;
1664         int ret, i;
1665         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1666         uint32_t intr_vector = 0;
1667
1668         hw->adapter_stopped = 0;
1669
1670         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1671                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1672                              dev->data->port_id);
1673                 return -EINVAL;
1674         }
1675
1676         rte_intr_disable(intr_handle);
1677
1678         if ((rte_intr_cap_multiple(intr_handle) ||
1679              !RTE_ETH_DEV_SRIOV(dev).active) &&
1680             dev->data->dev_conf.intr_conf.rxq != 0) {
1681                 intr_vector = dev->data->nb_rx_queues;
1682                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1683                         return -1;
1684         }
1685
1686         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1687                 intr_handle->intr_vec =
1688                         rte_zmalloc("intr_vec",
1689                                     dev->data->nb_rx_queues * sizeof(int),
1690                                     0);
1691                 if (!intr_handle->intr_vec) {
1692                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1693                                      " intr_vec\n", dev->data->nb_rx_queues);
1694                         return -ENOMEM;
1695                 }
1696         }
1697
1698         /* Initialize VSI */
1699         ret = i40e_dev_rxtx_init(pf);
1700         if (ret != I40E_SUCCESS) {
1701                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1702                 goto err_up;
1703         }
1704
1705         /* Map queues with MSIX interrupt */
1706         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1707                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1708         i40e_vsi_queues_bind_intr(main_vsi);
1709         i40e_vsi_enable_queues_intr(main_vsi);
1710
1711         /* Map VMDQ VSI queues with MSIX interrupt */
1712         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1713                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1714                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1715                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1716         }
1717
1718         /* enable FDIR MSIX interrupt */
1719         if (pf->fdir.fdir_vsi) {
1720                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1721                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1722         }
1723
1724         /* Enable all queues which have been configured */
1725         ret = i40e_dev_switch_queues(pf, TRUE);
1726         if (ret != I40E_SUCCESS) {
1727                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1728                 goto err_up;
1729         }
1730
1731         /* Enable receiving broadcast packets */
1732         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1733         if (ret != I40E_SUCCESS)
1734                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1735
1736         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1737                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1738                                                 true, NULL);
1739                 if (ret != I40E_SUCCESS)
1740                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1741         }
1742
1743         /* Apply link configure */
1744         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1745                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1746                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1747                 PMD_DRV_LOG(ERR, "Invalid link setting");
1748                 goto err_up;
1749         }
1750         ret = i40e_apply_link_speed(dev);
1751         if (I40E_SUCCESS != ret) {
1752                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1753                 goto err_up;
1754         }
1755
1756         if (!rte_intr_allow_others(intr_handle)) {
1757                 rte_intr_callback_unregister(intr_handle,
1758                                              i40e_dev_interrupt_handler,
1759                                              (void *)dev);
1760                 /* configure and enable device interrupt */
1761                 i40e_pf_config_irq0(hw, FALSE);
1762                 i40e_pf_enable_irq0(hw);
1763
1764                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1765                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1766                                      " no intr multiplex\n");
1767         }
1768
1769         /* enable uio intr after callback register */
1770         rte_intr_enable(intr_handle);
1771
1772         return I40E_SUCCESS;
1773
1774 err_up:
1775         i40e_dev_switch_queues(pf, FALSE);
1776         i40e_dev_clear_queues(dev);
1777
1778         return ret;
1779 }
1780
1781 static void
1782 i40e_dev_stop(struct rte_eth_dev *dev)
1783 {
1784         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1785         struct i40e_vsi *main_vsi = pf->main_vsi;
1786         struct i40e_mirror_rule *p_mirror;
1787         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1788         int i;
1789
1790         /* Disable all queues */
1791         i40e_dev_switch_queues(pf, FALSE);
1792
1793         /* un-map queues with interrupt registers */
1794         i40e_vsi_disable_queues_intr(main_vsi);
1795         i40e_vsi_queues_unbind_intr(main_vsi);
1796
1797         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1798                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1799                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1800         }
1801
1802         if (pf->fdir.fdir_vsi) {
1803                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1804                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1805         }
1806         /* Clear all queues and release memory */
1807         i40e_dev_clear_queues(dev);
1808
1809         /* Set link down */
1810         i40e_dev_set_link_down(dev);
1811
1812         /* Remove all mirror rules */
1813         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1814                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1815                 rte_free(p_mirror);
1816         }
1817         pf->nb_mirror_rule = 0;
1818
1819         if (!rte_intr_allow_others(intr_handle))
1820                 /* resume to the default handler */
1821                 rte_intr_callback_register(intr_handle,
1822                                            i40e_dev_interrupt_handler,
1823                                            (void *)dev);
1824
1825         /* Clean datapath event and queue/vec mapping */
1826         rte_intr_efd_disable(intr_handle);
1827         if (intr_handle->intr_vec) {
1828                 rte_free(intr_handle->intr_vec);
1829                 intr_handle->intr_vec = NULL;
1830         }
1831 }
1832
1833 static void
1834 i40e_dev_close(struct rte_eth_dev *dev)
1835 {
1836         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         uint32_t reg;
1839         int i;
1840
1841         PMD_INIT_FUNC_TRACE();
1842
1843         i40e_dev_stop(dev);
1844         hw->adapter_stopped = 1;
1845         i40e_dev_free_queues(dev);
1846
1847         /* Disable interrupt */
1848         i40e_pf_disable_irq0(hw);
1849         rte_intr_disable(&(dev->pci_dev->intr_handle));
1850
1851         /* shutdown and destroy the HMC */
1852         i40e_shutdown_lan_hmc(hw);
1853
1854         /* release all the existing VSIs and VEBs */
1855         i40e_fdir_teardown(pf);
1856         i40e_vsi_release(pf->main_vsi);
1857
1858         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1859                 i40e_vsi_release(pf->vmdq[i].vsi);
1860                 pf->vmdq[i].vsi = NULL;
1861         }
1862
1863         rte_free(pf->vmdq);
1864         pf->vmdq = NULL;
1865
1866         /* shutdown the adminq */
1867         i40e_aq_queue_shutdown(hw, true);
1868         i40e_shutdown_adminq(hw);
1869
1870         i40e_res_pool_destroy(&pf->qp_pool);
1871         i40e_res_pool_destroy(&pf->msix_pool);
1872
1873         /* force a PF reset to clean anything leftover */
1874         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1875         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1876                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1877         I40E_WRITE_FLUSH(hw);
1878 }
1879
1880 static void
1881 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1882 {
1883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885         struct i40e_vsi *vsi = pf->main_vsi;
1886         int status;
1887
1888         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1889                                                      true, NULL, true);
1890         if (status != I40E_SUCCESS)
1891                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1892
1893         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1894                                                         TRUE, NULL);
1895         if (status != I40E_SUCCESS)
1896                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1897
1898 }
1899
1900 static void
1901 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1902 {
1903         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1904         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905         struct i40e_vsi *vsi = pf->main_vsi;
1906         int status;
1907
1908         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1909                                                      false, NULL, true);
1910         if (status != I40E_SUCCESS)
1911                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1912
1913         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1914                                                         false, NULL);
1915         if (status != I40E_SUCCESS)
1916                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1917 }
1918
1919 static void
1920 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1921 {
1922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924         struct i40e_vsi *vsi = pf->main_vsi;
1925         int ret;
1926
1927         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1928         if (ret != I40E_SUCCESS)
1929                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1930 }
1931
1932 static void
1933 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1934 {
1935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937         struct i40e_vsi *vsi = pf->main_vsi;
1938         int ret;
1939
1940         if (dev->data->promiscuous == 1)
1941                 return; /* must remain in all_multicast mode */
1942
1943         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1944                                 vsi->seid, FALSE, NULL);
1945         if (ret != I40E_SUCCESS)
1946                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1947 }
1948
1949 /*
1950  * Set device link up.
1951  */
1952 static int
1953 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1954 {
1955         /* re-apply link speed setting */
1956         return i40e_apply_link_speed(dev);
1957 }
1958
1959 /*
1960  * Set device link down.
1961  */
1962 static int
1963 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1964 {
1965         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1966         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1968
1969         return i40e_phy_conf_link(hw, abilities, speed);
1970 }
1971
1972 int
1973 i40e_dev_link_update(struct rte_eth_dev *dev,
1974                      int wait_to_complete)
1975 {
1976 #define CHECK_INTERVAL 100  /* 100ms */
1977 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1978         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         struct i40e_link_status link_status;
1980         struct rte_eth_link link, old;
1981         int status;
1982         unsigned rep_cnt = MAX_REPEAT_TIME;
1983
1984         memset(&link, 0, sizeof(link));
1985         memset(&old, 0, sizeof(old));
1986         memset(&link_status, 0, sizeof(link_status));
1987         rte_i40e_dev_atomic_read_link_status(dev, &old);
1988
1989         do {
1990                 /* Get link status information from hardware */
1991                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1992                 if (status != I40E_SUCCESS) {
1993                         link.link_speed = ETH_SPEED_NUM_100M;
1994                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1995                         PMD_DRV_LOG(ERR, "Failed to get link info");
1996                         goto out;
1997                 }
1998
1999                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2000                 if (!wait_to_complete)
2001                         break;
2002
2003                 rte_delay_ms(CHECK_INTERVAL);
2004         } while (!link.link_status && rep_cnt--);
2005
2006         if (!link.link_status)
2007                 goto out;
2008
2009         /* i40e uses full duplex only */
2010         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2011
2012         /* Parse the link status */
2013         switch (link_status.link_speed) {
2014         case I40E_LINK_SPEED_100MB:
2015                 link.link_speed = ETH_SPEED_NUM_100M;
2016                 break;
2017         case I40E_LINK_SPEED_1GB:
2018                 link.link_speed = ETH_SPEED_NUM_1G;
2019                 break;
2020         case I40E_LINK_SPEED_10GB:
2021                 link.link_speed = ETH_SPEED_NUM_10G;
2022                 break;
2023         case I40E_LINK_SPEED_20GB:
2024                 link.link_speed = ETH_SPEED_NUM_20G;
2025                 break;
2026         case I40E_LINK_SPEED_40GB:
2027                 link.link_speed = ETH_SPEED_NUM_40G;
2028                 break;
2029         default:
2030                 link.link_speed = ETH_SPEED_NUM_100M;
2031                 break;
2032         }
2033
2034         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2035                         ETH_LINK_SPEED_FIXED);
2036
2037 out:
2038         rte_i40e_dev_atomic_write_link_status(dev, &link);
2039         if (link.link_status == old.link_status)
2040                 return -1;
2041
2042         return 0;
2043 }
2044
2045 /* Get all the statistics of a VSI */
2046 void
2047 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2048 {
2049         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2050         struct i40e_eth_stats *nes = &vsi->eth_stats;
2051         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2052         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2053
2054         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2055                             vsi->offset_loaded, &oes->rx_bytes,
2056                             &nes->rx_bytes);
2057         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2058                             vsi->offset_loaded, &oes->rx_unicast,
2059                             &nes->rx_unicast);
2060         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2061                             vsi->offset_loaded, &oes->rx_multicast,
2062                             &nes->rx_multicast);
2063         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2064                             vsi->offset_loaded, &oes->rx_broadcast,
2065                             &nes->rx_broadcast);
2066         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2067                             &oes->rx_discards, &nes->rx_discards);
2068         /* GLV_REPC not supported */
2069         /* GLV_RMPC not supported */
2070         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2071                             &oes->rx_unknown_protocol,
2072                             &nes->rx_unknown_protocol);
2073         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2074                             vsi->offset_loaded, &oes->tx_bytes,
2075                             &nes->tx_bytes);
2076         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2077                             vsi->offset_loaded, &oes->tx_unicast,
2078                             &nes->tx_unicast);
2079         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2080                             vsi->offset_loaded, &oes->tx_multicast,
2081                             &nes->tx_multicast);
2082         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2083                             vsi->offset_loaded,  &oes->tx_broadcast,
2084                             &nes->tx_broadcast);
2085         /* GLV_TDPC not supported */
2086         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2087                             &oes->tx_errors, &nes->tx_errors);
2088         vsi->offset_loaded = true;
2089
2090         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2091                     vsi->vsi_id);
2092         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2093         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2094         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2095         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2096         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2097         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2098                     nes->rx_unknown_protocol);
2099         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2100         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2101         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2102         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2103         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2104         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2105         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2106                     vsi->vsi_id);
2107 }
2108
2109 static void
2110 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2111 {
2112         unsigned int i;
2113         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2114         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2115
2116         /* Get statistics of struct i40e_eth_stats */
2117         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2118                             I40E_GLPRT_GORCL(hw->port),
2119                             pf->offset_loaded, &os->eth.rx_bytes,
2120                             &ns->eth.rx_bytes);
2121         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2122                             I40E_GLPRT_UPRCL(hw->port),
2123                             pf->offset_loaded, &os->eth.rx_unicast,
2124                             &ns->eth.rx_unicast);
2125         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2126                             I40E_GLPRT_MPRCL(hw->port),
2127                             pf->offset_loaded, &os->eth.rx_multicast,
2128                             &ns->eth.rx_multicast);
2129         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2130                             I40E_GLPRT_BPRCL(hw->port),
2131                             pf->offset_loaded, &os->eth.rx_broadcast,
2132                             &ns->eth.rx_broadcast);
2133         /* Workaround: CRC size should not be included in byte statistics,
2134          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2135          */
2136         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2137                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2138
2139         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2140                             pf->offset_loaded, &os->eth.rx_discards,
2141                             &ns->eth.rx_discards);
2142         /* GLPRT_REPC not supported */
2143         /* GLPRT_RMPC not supported */
2144         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2145                             pf->offset_loaded,
2146                             &os->eth.rx_unknown_protocol,
2147                             &ns->eth.rx_unknown_protocol);
2148         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2149                             I40E_GLPRT_GOTCL(hw->port),
2150                             pf->offset_loaded, &os->eth.tx_bytes,
2151                             &ns->eth.tx_bytes);
2152         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2153                             I40E_GLPRT_UPTCL(hw->port),
2154                             pf->offset_loaded, &os->eth.tx_unicast,
2155                             &ns->eth.tx_unicast);
2156         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2157                             I40E_GLPRT_MPTCL(hw->port),
2158                             pf->offset_loaded, &os->eth.tx_multicast,
2159                             &ns->eth.tx_multicast);
2160         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2161                             I40E_GLPRT_BPTCL(hw->port),
2162                             pf->offset_loaded, &os->eth.tx_broadcast,
2163                             &ns->eth.tx_broadcast);
2164         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2165                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2166         /* GLPRT_TEPC not supported */
2167
2168         /* additional port specific stats */
2169         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2170                             pf->offset_loaded, &os->tx_dropped_link_down,
2171                             &ns->tx_dropped_link_down);
2172         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2173                             pf->offset_loaded, &os->crc_errors,
2174                             &ns->crc_errors);
2175         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2176                             pf->offset_loaded, &os->illegal_bytes,
2177                             &ns->illegal_bytes);
2178         /* GLPRT_ERRBC not supported */
2179         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2180                             pf->offset_loaded, &os->mac_local_faults,
2181                             &ns->mac_local_faults);
2182         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2183                             pf->offset_loaded, &os->mac_remote_faults,
2184                             &ns->mac_remote_faults);
2185         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2186                             pf->offset_loaded, &os->rx_length_errors,
2187                             &ns->rx_length_errors);
2188         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2189                             pf->offset_loaded, &os->link_xon_rx,
2190                             &ns->link_xon_rx);
2191         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2192                             pf->offset_loaded, &os->link_xoff_rx,
2193                             &ns->link_xoff_rx);
2194         for (i = 0; i < 8; i++) {
2195                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2196                                     pf->offset_loaded,
2197                                     &os->priority_xon_rx[i],
2198                                     &ns->priority_xon_rx[i]);
2199                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2200                                     pf->offset_loaded,
2201                                     &os->priority_xoff_rx[i],
2202                                     &ns->priority_xoff_rx[i]);
2203         }
2204         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2205                             pf->offset_loaded, &os->link_xon_tx,
2206                             &ns->link_xon_tx);
2207         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2208                             pf->offset_loaded, &os->link_xoff_tx,
2209                             &ns->link_xoff_tx);
2210         for (i = 0; i < 8; i++) {
2211                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2212                                     pf->offset_loaded,
2213                                     &os->priority_xon_tx[i],
2214                                     &ns->priority_xon_tx[i]);
2215                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2216                                     pf->offset_loaded,
2217                                     &os->priority_xoff_tx[i],
2218                                     &ns->priority_xoff_tx[i]);
2219                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2220                                     pf->offset_loaded,
2221                                     &os->priority_xon_2_xoff[i],
2222                                     &ns->priority_xon_2_xoff[i]);
2223         }
2224         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2225                             I40E_GLPRT_PRC64L(hw->port),
2226                             pf->offset_loaded, &os->rx_size_64,
2227                             &ns->rx_size_64);
2228         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2229                             I40E_GLPRT_PRC127L(hw->port),
2230                             pf->offset_loaded, &os->rx_size_127,
2231                             &ns->rx_size_127);
2232         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2233                             I40E_GLPRT_PRC255L(hw->port),
2234                             pf->offset_loaded, &os->rx_size_255,
2235                             &ns->rx_size_255);
2236         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2237                             I40E_GLPRT_PRC511L(hw->port),
2238                             pf->offset_loaded, &os->rx_size_511,
2239                             &ns->rx_size_511);
2240         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2241                             I40E_GLPRT_PRC1023L(hw->port),
2242                             pf->offset_loaded, &os->rx_size_1023,
2243                             &ns->rx_size_1023);
2244         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2245                             I40E_GLPRT_PRC1522L(hw->port),
2246                             pf->offset_loaded, &os->rx_size_1522,
2247                             &ns->rx_size_1522);
2248         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2249                             I40E_GLPRT_PRC9522L(hw->port),
2250                             pf->offset_loaded, &os->rx_size_big,
2251                             &ns->rx_size_big);
2252         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2253                             pf->offset_loaded, &os->rx_undersize,
2254                             &ns->rx_undersize);
2255         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2256                             pf->offset_loaded, &os->rx_fragments,
2257                             &ns->rx_fragments);
2258         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2259                             pf->offset_loaded, &os->rx_oversize,
2260                             &ns->rx_oversize);
2261         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2262                             pf->offset_loaded, &os->rx_jabber,
2263                             &ns->rx_jabber);
2264         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2265                             I40E_GLPRT_PTC64L(hw->port),
2266                             pf->offset_loaded, &os->tx_size_64,
2267                             &ns->tx_size_64);
2268         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2269                             I40E_GLPRT_PTC127L(hw->port),
2270                             pf->offset_loaded, &os->tx_size_127,
2271                             &ns->tx_size_127);
2272         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2273                             I40E_GLPRT_PTC255L(hw->port),
2274                             pf->offset_loaded, &os->tx_size_255,
2275                             &ns->tx_size_255);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2277                             I40E_GLPRT_PTC511L(hw->port),
2278                             pf->offset_loaded, &os->tx_size_511,
2279                             &ns->tx_size_511);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2281                             I40E_GLPRT_PTC1023L(hw->port),
2282                             pf->offset_loaded, &os->tx_size_1023,
2283                             &ns->tx_size_1023);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2285                             I40E_GLPRT_PTC1522L(hw->port),
2286                             pf->offset_loaded, &os->tx_size_1522,
2287                             &ns->tx_size_1522);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2289                             I40E_GLPRT_PTC9522L(hw->port),
2290                             pf->offset_loaded, &os->tx_size_big,
2291                             &ns->tx_size_big);
2292         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2293                            pf->offset_loaded,
2294                            &os->fd_sb_match, &ns->fd_sb_match);
2295         /* GLPRT_MSPDC not supported */
2296         /* GLPRT_XEC not supported */
2297
2298         pf->offset_loaded = true;
2299
2300         if (pf->main_vsi)
2301                 i40e_update_vsi_stats(pf->main_vsi);
2302 }
2303
2304 /* Get all statistics of a port */
2305 static void
2306 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2307 {
2308         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2309         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2310         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2311         unsigned i;
2312
2313         /* call read registers - updates values, now write them to struct */
2314         i40e_read_stats_registers(pf, hw);
2315
2316         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2317                         pf->main_vsi->eth_stats.rx_multicast +
2318                         pf->main_vsi->eth_stats.rx_broadcast -
2319                         pf->main_vsi->eth_stats.rx_discards;
2320         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2321                         pf->main_vsi->eth_stats.tx_multicast +
2322                         pf->main_vsi->eth_stats.tx_broadcast;
2323         stats->ibytes   = ns->eth.rx_bytes;
2324         stats->obytes   = ns->eth.tx_bytes;
2325         stats->oerrors  = ns->eth.tx_errors +
2326                         pf->main_vsi->eth_stats.tx_errors;
2327
2328         /* Rx Errors */
2329         stats->imissed  = ns->eth.rx_discards +
2330                         pf->main_vsi->eth_stats.rx_discards;
2331         stats->ierrors  = ns->crc_errors +
2332                         ns->rx_length_errors + ns->rx_undersize +
2333                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2334
2335         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2336         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2337         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2338         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2339         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2340         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2341         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2342                     ns->eth.rx_unknown_protocol);
2343         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2344         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2345         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2346         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2347         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2348         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2349
2350         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2351                     ns->tx_dropped_link_down);
2352         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2353         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2354                     ns->illegal_bytes);
2355         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2356         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2357                     ns->mac_local_faults);
2358         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2359                     ns->mac_remote_faults);
2360         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2361                     ns->rx_length_errors);
2362         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2363         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2364         for (i = 0; i < 8; i++) {
2365                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2366                                 i, ns->priority_xon_rx[i]);
2367                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2368                                 i, ns->priority_xoff_rx[i]);
2369         }
2370         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2371         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2372         for (i = 0; i < 8; i++) {
2373                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2374                                 i, ns->priority_xon_tx[i]);
2375                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2376                                 i, ns->priority_xoff_tx[i]);
2377                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2378                                 i, ns->priority_xon_2_xoff[i]);
2379         }
2380         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2381         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2382         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2383         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2384         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2385         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2386         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2387         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2388         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2389         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2390         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2391         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2392         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2393         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2394         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2395         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2396         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2397         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2398         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2399                         ns->mac_short_packet_dropped);
2400         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2401                     ns->checksum_error);
2402         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2403         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2404 }
2405
2406 /* Reset the statistics */
2407 static void
2408 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2409 {
2410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412
2413         /* Mark PF and VSI stats to update the offset, aka "reset" */
2414         pf->offset_loaded = false;
2415         if (pf->main_vsi)
2416                 pf->main_vsi->offset_loaded = false;
2417
2418         /* read the stats, reading current register values into offset */
2419         i40e_read_stats_registers(pf, hw);
2420 }
2421
2422 static uint32_t
2423 i40e_xstats_calc_num(void)
2424 {
2425         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2426                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2427                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2428 }
2429
2430 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2431                                      struct rte_eth_xstat_name *xstats_names,
2432                                      __rte_unused unsigned limit)
2433 {
2434         unsigned count = 0;
2435         unsigned i, prio;
2436
2437         if (xstats_names == NULL)
2438                 return i40e_xstats_calc_num();
2439
2440         /* Note: limit checked in rte_eth_xstats_names() */
2441
2442         /* Get stats from i40e_eth_stats struct */
2443         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2444                 snprintf(xstats_names[count].name,
2445                          sizeof(xstats_names[count].name),
2446                          "%s", rte_i40e_stats_strings[i].name);
2447                 count++;
2448         }
2449
2450         /* Get individiual stats from i40e_hw_port struct */
2451         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2452                 snprintf(xstats_names[count].name,
2453                         sizeof(xstats_names[count].name),
2454                          "%s", rte_i40e_hw_port_strings[i].name);
2455                 count++;
2456         }
2457
2458         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2459                 for (prio = 0; prio < 8; prio++) {
2460                         snprintf(xstats_names[count].name,
2461                                  sizeof(xstats_names[count].name),
2462                                  "rx_priority%u_%s", prio,
2463                                  rte_i40e_rxq_prio_strings[i].name);
2464                         count++;
2465                 }
2466         }
2467
2468         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2469                 for (prio = 0; prio < 8; prio++) {
2470                         snprintf(xstats_names[count].name,
2471                                  sizeof(xstats_names[count].name),
2472                                  "tx_priority%u_%s", prio,
2473                                  rte_i40e_txq_prio_strings[i].name);
2474                         count++;
2475                 }
2476         }
2477         return count;
2478 }
2479
2480 static int
2481 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2482                     unsigned n)
2483 {
2484         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2485         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         unsigned i, count, prio;
2487         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2488
2489         count = i40e_xstats_calc_num();
2490         if (n < count)
2491                 return count;
2492
2493         i40e_read_stats_registers(pf, hw);
2494
2495         if (xstats == NULL)
2496                 return 0;
2497
2498         count = 0;
2499
2500         /* Get stats from i40e_eth_stats struct */
2501         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2502                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2503                         rte_i40e_stats_strings[i].offset);
2504                 count++;
2505         }
2506
2507         /* Get individiual stats from i40e_hw_port struct */
2508         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2509                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2510                         rte_i40e_hw_port_strings[i].offset);
2511                 count++;
2512         }
2513
2514         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2515                 for (prio = 0; prio < 8; prio++) {
2516                         xstats[count].value =
2517                                 *(uint64_t *)(((char *)hw_stats) +
2518                                 rte_i40e_rxq_prio_strings[i].offset +
2519                                 (sizeof(uint64_t) * prio));
2520                         count++;
2521                 }
2522         }
2523
2524         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2525                 for (prio = 0; prio < 8; prio++) {
2526                         xstats[count].value =
2527                                 *(uint64_t *)(((char *)hw_stats) +
2528                                 rte_i40e_txq_prio_strings[i].offset +
2529                                 (sizeof(uint64_t) * prio));
2530                         count++;
2531                 }
2532         }
2533
2534         return count;
2535 }
2536
2537 static int
2538 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2539                                  __rte_unused uint16_t queue_id,
2540                                  __rte_unused uint8_t stat_idx,
2541                                  __rte_unused uint8_t is_rx)
2542 {
2543         PMD_INIT_FUNC_TRACE();
2544
2545         return -ENOSYS;
2546 }
2547
2548 static void
2549 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2550 {
2551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2552         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         struct i40e_vsi *vsi = pf->main_vsi;
2554
2555         dev_info->max_rx_queues = vsi->nb_qps;
2556         dev_info->max_tx_queues = vsi->nb_qps;
2557         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2558         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2559         dev_info->max_mac_addrs = vsi->max_macaddrs;
2560         dev_info->max_vfs = dev->pci_dev->max_vfs;
2561         dev_info->rx_offload_capa =
2562                 DEV_RX_OFFLOAD_VLAN_STRIP |
2563                 DEV_RX_OFFLOAD_QINQ_STRIP |
2564                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2565                 DEV_RX_OFFLOAD_UDP_CKSUM |
2566                 DEV_RX_OFFLOAD_TCP_CKSUM;
2567         dev_info->tx_offload_capa =
2568                 DEV_TX_OFFLOAD_VLAN_INSERT |
2569                 DEV_TX_OFFLOAD_QINQ_INSERT |
2570                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2571                 DEV_TX_OFFLOAD_UDP_CKSUM |
2572                 DEV_TX_OFFLOAD_TCP_CKSUM |
2573                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2574                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2575                 DEV_TX_OFFLOAD_TCP_TSO;
2576         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2577                                                 sizeof(uint32_t);
2578         dev_info->reta_size = pf->hash_lut_size;
2579         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2580
2581         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2582                 .rx_thresh = {
2583                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2584                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2585                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2586                 },
2587                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2588                 .rx_drop_en = 0,
2589         };
2590
2591         dev_info->default_txconf = (struct rte_eth_txconf) {
2592                 .tx_thresh = {
2593                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2594                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2595                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2596                 },
2597                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2598                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2599                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2600                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2601         };
2602
2603         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2604                 .nb_max = I40E_MAX_RING_DESC,
2605                 .nb_min = I40E_MIN_RING_DESC,
2606                 .nb_align = I40E_ALIGN_RING_DESC,
2607         };
2608
2609         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2610                 .nb_max = I40E_MAX_RING_DESC,
2611                 .nb_min = I40E_MIN_RING_DESC,
2612                 .nb_align = I40E_ALIGN_RING_DESC,
2613         };
2614
2615         if (pf->flags & I40E_FLAG_VMDQ) {
2616                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2617                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2618                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2619                                                 pf->max_nb_vmdq_vsi;
2620                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2621                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2622                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2623         }
2624
2625         if (i40e_is_40G_device(hw->device_id))
2626                 /* For XL710 */
2627                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2628         else
2629                 /* For X710 */
2630                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2631 }
2632
2633 static int
2634 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2635 {
2636         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2637         struct i40e_vsi *vsi = pf->main_vsi;
2638         PMD_INIT_FUNC_TRACE();
2639
2640         if (on)
2641                 return i40e_vsi_add_vlan(vsi, vlan_id);
2642         else
2643                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2644 }
2645
2646 static int
2647 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2648                    enum rte_vlan_type vlan_type,
2649                    uint16_t tpid)
2650 {
2651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652         uint64_t reg_r = 0, reg_w = 0;
2653         uint16_t reg_id = 0;
2654         int ret = 0;
2655         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2656
2657         switch (vlan_type) {
2658         case ETH_VLAN_TYPE_OUTER:
2659                 if (qinq)
2660                         reg_id = 2;
2661                 else
2662                         reg_id = 3;
2663                 break;
2664         case ETH_VLAN_TYPE_INNER:
2665                 if (qinq)
2666                         reg_id = 3;
2667                 else {
2668                         ret = -EINVAL;
2669                         PMD_DRV_LOG(ERR,
2670                                 "Unsupported vlan type in single vlan.\n");
2671                         return ret;
2672                 }
2673                 break;
2674         default:
2675                 ret = -EINVAL;
2676                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2677                 return ret;
2678         }
2679         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2680                                           &reg_r, NULL);
2681         if (ret != I40E_SUCCESS) {
2682                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2683                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2684                 ret = -EIO;
2685                 return ret;
2686         }
2687         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2688                     "0x%08"PRIx64"", reg_id, reg_r);
2689
2690         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2691         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2692         if (reg_r == reg_w) {
2693                 ret = 0;
2694                 PMD_DRV_LOG(DEBUG, "No need to write");
2695                 return ret;
2696         }
2697
2698         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2699                                            reg_w, NULL);
2700         if (ret != I40E_SUCCESS) {
2701                 ret = -EIO;
2702                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2703                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2704                 return ret;
2705         }
2706         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2707                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2708
2709         return ret;
2710 }
2711
2712 static void
2713 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2714 {
2715         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2716         struct i40e_vsi *vsi = pf->main_vsi;
2717
2718         if (mask & ETH_VLAN_FILTER_MASK) {
2719                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2720                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2721                 else
2722                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2723         }
2724
2725         if (mask & ETH_VLAN_STRIP_MASK) {
2726                 /* Enable or disable VLAN stripping */
2727                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2728                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2729                 else
2730                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2731         }
2732
2733         if (mask & ETH_VLAN_EXTEND_MASK) {
2734                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2735                         i40e_vsi_config_double_vlan(vsi, TRUE);
2736                         /* Set global registers with default ether type value */
2737                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2738                                            ETHER_TYPE_VLAN);
2739                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2740                                            ETHER_TYPE_VLAN);
2741                 }
2742                 else
2743                         i40e_vsi_config_double_vlan(vsi, FALSE);
2744         }
2745 }
2746
2747 static void
2748 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2749                           __rte_unused uint16_t queue,
2750                           __rte_unused int on)
2751 {
2752         PMD_INIT_FUNC_TRACE();
2753 }
2754
2755 static int
2756 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2757 {
2758         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2759         struct i40e_vsi *vsi = pf->main_vsi;
2760         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2761         struct i40e_vsi_vlan_pvid_info info;
2762
2763         memset(&info, 0, sizeof(info));
2764         info.on = on;
2765         if (info.on)
2766                 info.config.pvid = pvid;
2767         else {
2768                 info.config.reject.tagged =
2769                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2770                 info.config.reject.untagged =
2771                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2772         }
2773
2774         return i40e_vsi_vlan_pvid_set(vsi, &info);
2775 }
2776
2777 static int
2778 i40e_dev_led_on(struct rte_eth_dev *dev)
2779 {
2780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781         uint32_t mode = i40e_led_get(hw);
2782
2783         if (mode == 0)
2784                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2785
2786         return 0;
2787 }
2788
2789 static int
2790 i40e_dev_led_off(struct rte_eth_dev *dev)
2791 {
2792         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         uint32_t mode = i40e_led_get(hw);
2794
2795         if (mode != 0)
2796                 i40e_led_set(hw, 0, false);
2797
2798         return 0;
2799 }
2800
2801 static int
2802 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2803 {
2804         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2805         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2806
2807         fc_conf->pause_time = pf->fc_conf.pause_time;
2808         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2809         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2810
2811          /* Return current mode according to actual setting*/
2812         switch (hw->fc.current_mode) {
2813         case I40E_FC_FULL:
2814                 fc_conf->mode = RTE_FC_FULL;
2815                 break;
2816         case I40E_FC_TX_PAUSE:
2817                 fc_conf->mode = RTE_FC_TX_PAUSE;
2818                 break;
2819         case I40E_FC_RX_PAUSE:
2820                 fc_conf->mode = RTE_FC_RX_PAUSE;
2821                 break;
2822         case I40E_FC_NONE:
2823         default:
2824                 fc_conf->mode = RTE_FC_NONE;
2825         };
2826
2827         return 0;
2828 }
2829
2830 static int
2831 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2832 {
2833         uint32_t mflcn_reg, fctrl_reg, reg;
2834         uint32_t max_high_water;
2835         uint8_t i, aq_failure;
2836         int err;
2837         struct i40e_hw *hw;
2838         struct i40e_pf *pf;
2839         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2840                 [RTE_FC_NONE] = I40E_FC_NONE,
2841                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2842                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2843                 [RTE_FC_FULL] = I40E_FC_FULL
2844         };
2845
2846         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2847
2848         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2849         if ((fc_conf->high_water > max_high_water) ||
2850                         (fc_conf->high_water < fc_conf->low_water)) {
2851                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2852                         "High_water must <= %d.", max_high_water);
2853                 return -EINVAL;
2854         }
2855
2856         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2858         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2859
2860         pf->fc_conf.pause_time = fc_conf->pause_time;
2861         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2862         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2863
2864         PMD_INIT_FUNC_TRACE();
2865
2866         /* All the link flow control related enable/disable register
2867          * configuration is handle by the F/W
2868          */
2869         err = i40e_set_fc(hw, &aq_failure, true);
2870         if (err < 0)
2871                 return -ENOSYS;
2872
2873         if (i40e_is_40G_device(hw->device_id)) {
2874                 /* Configure flow control refresh threshold,
2875                  * the value for stat_tx_pause_refresh_timer[8]
2876                  * is used for global pause operation.
2877                  */
2878
2879                 I40E_WRITE_REG(hw,
2880                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2881                                pf->fc_conf.pause_time);
2882
2883                 /* configure the timer value included in transmitted pause
2884                  * frame,
2885                  * the value for stat_tx_pause_quanta[8] is used for global
2886                  * pause operation
2887                  */
2888                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2889                                pf->fc_conf.pause_time);
2890
2891                 fctrl_reg = I40E_READ_REG(hw,
2892                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2893
2894                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2895                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2896                 else
2897                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2898
2899                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2900                                fctrl_reg);
2901         } else {
2902                 /* Configure pause time (2 TCs per register) */
2903                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2904                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2905                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2906
2907                 /* Configure flow control refresh threshold value */
2908                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2909                                pf->fc_conf.pause_time / 2);
2910
2911                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2912
2913                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2914                  *depending on configuration
2915                  */
2916                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2917                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2918                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2919                 } else {
2920                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2921                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2922                 }
2923
2924                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2925         }
2926
2927         /* config the water marker both based on the packets and bytes */
2928         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2929                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2930                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2931         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2932                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2933                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2934         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2935                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2936                        << I40E_KILOSHIFT);
2937         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2938                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2939                        << I40E_KILOSHIFT);
2940
2941         I40E_WRITE_FLUSH(hw);
2942
2943         return 0;
2944 }
2945
2946 static int
2947 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2948                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2949 {
2950         PMD_INIT_FUNC_TRACE();
2951
2952         return -ENOSYS;
2953 }
2954
2955 /* Add a MAC address, and update filters */
2956 static void
2957 i40e_macaddr_add(struct rte_eth_dev *dev,
2958                  struct ether_addr *mac_addr,
2959                  __rte_unused uint32_t index,
2960                  uint32_t pool)
2961 {
2962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2963         struct i40e_mac_filter_info mac_filter;
2964         struct i40e_vsi *vsi;
2965         int ret;
2966
2967         /* If VMDQ not enabled or configured, return */
2968         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2969                           !pf->nb_cfg_vmdq_vsi)) {
2970                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2971                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2972                         pool);
2973                 return;
2974         }
2975
2976         if (pool > pf->nb_cfg_vmdq_vsi) {
2977                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2978                                 pool, pf->nb_cfg_vmdq_vsi);
2979                 return;
2980         }
2981
2982         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2983         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2984                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2985         else
2986                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2987
2988         if (pool == 0)
2989                 vsi = pf->main_vsi;
2990         else
2991                 vsi = pf->vmdq[pool - 1].vsi;
2992
2993         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2994         if (ret != I40E_SUCCESS) {
2995                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2996                 return;
2997         }
2998 }
2999
3000 /* Remove a MAC address, and update filters */
3001 static void
3002 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3003 {
3004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3005         struct i40e_vsi *vsi;
3006         struct rte_eth_dev_data *data = dev->data;
3007         struct ether_addr *macaddr;
3008         int ret;
3009         uint32_t i;
3010         uint64_t pool_sel;
3011
3012         macaddr = &(data->mac_addrs[index]);
3013
3014         pool_sel = dev->data->mac_pool_sel[index];
3015
3016         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3017                 if (pool_sel & (1ULL << i)) {
3018                         if (i == 0)
3019                                 vsi = pf->main_vsi;
3020                         else {
3021                                 /* No VMDQ pool enabled or configured */
3022                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3023                                         (i > pf->nb_cfg_vmdq_vsi)) {
3024                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3025                                                         "/configured");
3026                                         return;
3027                                 }
3028                                 vsi = pf->vmdq[i - 1].vsi;
3029                         }
3030                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3031
3032                         if (ret) {
3033                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3034                                 return;
3035                         }
3036                 }
3037         }
3038 }
3039
3040 /* Set perfect match or hash match of MAC and VLAN for a VF */
3041 static int
3042 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3043                  struct rte_eth_mac_filter *filter,
3044                  bool add)
3045 {
3046         struct i40e_hw *hw;
3047         struct i40e_mac_filter_info mac_filter;
3048         struct ether_addr old_mac;
3049         struct ether_addr *new_mac;
3050         struct i40e_pf_vf *vf = NULL;
3051         uint16_t vf_id;
3052         int ret;
3053
3054         if (pf == NULL) {
3055                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3056                 return -EINVAL;
3057         }
3058         hw = I40E_PF_TO_HW(pf);
3059
3060         if (filter == NULL) {
3061                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3062                 return -EINVAL;
3063         }
3064
3065         new_mac = &filter->mac_addr;
3066
3067         if (is_zero_ether_addr(new_mac)) {
3068                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3069                 return -EINVAL;
3070         }
3071
3072         vf_id = filter->dst_id;
3073
3074         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3075                 PMD_DRV_LOG(ERR, "Invalid argument.");
3076                 return -EINVAL;
3077         }
3078         vf = &pf->vfs[vf_id];
3079
3080         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3081                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3082                 return -EINVAL;
3083         }
3084
3085         if (add) {
3086                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3087                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3088                                 ETHER_ADDR_LEN);
3089                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3090                                  ETHER_ADDR_LEN);
3091
3092                 mac_filter.filter_type = filter->filter_type;
3093                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3094                 if (ret != I40E_SUCCESS) {
3095                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3096                         return -1;
3097                 }
3098                 ether_addr_copy(new_mac, &pf->dev_addr);
3099         } else {
3100                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3101                                 ETHER_ADDR_LEN);
3102                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3103                 if (ret != I40E_SUCCESS) {
3104                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3105                         return -1;
3106                 }
3107
3108                 /* Clear device address as it has been removed */
3109                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3110                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3111         }
3112
3113         return 0;
3114 }
3115
3116 /* MAC filter handle */
3117 static int
3118 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3119                 void *arg)
3120 {
3121         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3122         struct rte_eth_mac_filter *filter;
3123         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3124         int ret = I40E_NOT_SUPPORTED;
3125
3126         filter = (struct rte_eth_mac_filter *)(arg);
3127
3128         switch (filter_op) {
3129         case RTE_ETH_FILTER_NOP:
3130                 ret = I40E_SUCCESS;
3131                 break;
3132         case RTE_ETH_FILTER_ADD:
3133                 i40e_pf_disable_irq0(hw);
3134                 if (filter->is_vf)
3135                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3136                 i40e_pf_enable_irq0(hw);
3137                 break;
3138         case RTE_ETH_FILTER_DELETE:
3139                 i40e_pf_disable_irq0(hw);
3140                 if (filter->is_vf)
3141                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3142                 i40e_pf_enable_irq0(hw);
3143                 break;
3144         default:
3145                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3146                 ret = I40E_ERR_PARAM;
3147                 break;
3148         }
3149
3150         return ret;
3151 }
3152
3153 static int
3154 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3155 {
3156         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3157         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3158         int ret;
3159
3160         if (!lut)
3161                 return -EINVAL;
3162
3163         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3164                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3165                                           lut, lut_size);
3166                 if (ret) {
3167                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3168                         return ret;
3169                 }
3170         } else {
3171                 uint32_t *lut_dw = (uint32_t *)lut;
3172                 uint16_t i, lut_size_dw = lut_size / 4;
3173
3174                 for (i = 0; i < lut_size_dw; i++)
3175                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3176         }
3177
3178         return 0;
3179 }
3180
3181 static int
3182 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3183 {
3184         struct i40e_pf *pf;
3185         struct i40e_hw *hw;
3186         int ret;
3187
3188         if (!vsi || !lut)
3189                 return -EINVAL;
3190
3191         pf = I40E_VSI_TO_PF(vsi);
3192         hw = I40E_VSI_TO_HW(vsi);
3193
3194         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3195                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3196                                           lut, lut_size);
3197                 if (ret) {
3198                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3199                         return ret;
3200                 }
3201         } else {
3202                 uint32_t *lut_dw = (uint32_t *)lut;
3203                 uint16_t i, lut_size_dw = lut_size / 4;
3204
3205                 for (i = 0; i < lut_size_dw; i++)
3206                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3207                 I40E_WRITE_FLUSH(hw);
3208         }
3209
3210         return 0;
3211 }
3212
3213 static int
3214 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3215                          struct rte_eth_rss_reta_entry64 *reta_conf,
3216                          uint16_t reta_size)
3217 {
3218         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3219         uint16_t i, lut_size = pf->hash_lut_size;
3220         uint16_t idx, shift;
3221         uint8_t *lut;
3222         int ret;
3223
3224         if (reta_size != lut_size ||
3225                 reta_size > ETH_RSS_RETA_SIZE_512) {
3226                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3227                         "(%d) doesn't match the number hardware can supported "
3228                                         "(%d)\n", reta_size, lut_size);
3229                 return -EINVAL;
3230         }
3231
3232         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3233         if (!lut) {
3234                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3235                 return -ENOMEM;
3236         }
3237         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3238         if (ret)
3239                 goto out;
3240         for (i = 0; i < reta_size; i++) {
3241                 idx = i / RTE_RETA_GROUP_SIZE;
3242                 shift = i % RTE_RETA_GROUP_SIZE;
3243                 if (reta_conf[idx].mask & (1ULL << shift))
3244                         lut[i] = reta_conf[idx].reta[shift];
3245         }
3246         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3247
3248 out:
3249         rte_free(lut);
3250
3251         return ret;
3252 }
3253
3254 static int
3255 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3256                         struct rte_eth_rss_reta_entry64 *reta_conf,
3257                         uint16_t reta_size)
3258 {
3259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3260         uint16_t i, lut_size = pf->hash_lut_size;
3261         uint16_t idx, shift;
3262         uint8_t *lut;
3263         int ret;
3264
3265         if (reta_size != lut_size ||
3266                 reta_size > ETH_RSS_RETA_SIZE_512) {
3267                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3268                         "(%d) doesn't match the number hardware can supported "
3269                                         "(%d)\n", reta_size, lut_size);
3270                 return -EINVAL;
3271         }
3272
3273         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3274         if (!lut) {
3275                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3276                 return -ENOMEM;
3277         }
3278
3279         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3280         if (ret)
3281                 goto out;
3282         for (i = 0; i < reta_size; i++) {
3283                 idx = i / RTE_RETA_GROUP_SIZE;
3284                 shift = i % RTE_RETA_GROUP_SIZE;
3285                 if (reta_conf[idx].mask & (1ULL << shift))
3286                         reta_conf[idx].reta[shift] = lut[i];
3287         }
3288
3289 out:
3290         rte_free(lut);
3291
3292         return ret;
3293 }
3294
3295 /**
3296  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3297  * @hw:   pointer to the HW structure
3298  * @mem:  pointer to mem struct to fill out
3299  * @size: size of memory requested
3300  * @alignment: what to align the allocation to
3301  **/
3302 enum i40e_status_code
3303 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3304                         struct i40e_dma_mem *mem,
3305                         u64 size,
3306                         u32 alignment)
3307 {
3308         const struct rte_memzone *mz = NULL;
3309         char z_name[RTE_MEMZONE_NAMESIZE];
3310
3311         if (!mem)
3312                 return I40E_ERR_PARAM;
3313
3314         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3315         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3316                                          alignment, RTE_PGSIZE_2M);
3317         if (!mz)
3318                 return I40E_ERR_NO_MEMORY;
3319
3320         mem->size = size;
3321         mem->va = mz->addr;
3322         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3323         mem->zone = (const void *)mz;
3324         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3325                     "%"PRIu64, mz->name, mem->pa);
3326
3327         return I40E_SUCCESS;
3328 }
3329
3330 /**
3331  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3332  * @hw:   pointer to the HW structure
3333  * @mem:  ptr to mem struct to free
3334  **/
3335 enum i40e_status_code
3336 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3337                     struct i40e_dma_mem *mem)
3338 {
3339         if (!mem)
3340                 return I40E_ERR_PARAM;
3341
3342         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3343                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3344                     mem->pa);
3345         rte_memzone_free((const struct rte_memzone *)mem->zone);
3346         mem->zone = NULL;
3347         mem->va = NULL;
3348         mem->pa = (u64)0;
3349
3350         return I40E_SUCCESS;
3351 }
3352
3353 /**
3354  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3355  * @hw:   pointer to the HW structure
3356  * @mem:  pointer to mem struct to fill out
3357  * @size: size of memory requested
3358  **/
3359 enum i40e_status_code
3360 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3361                          struct i40e_virt_mem *mem,
3362                          u32 size)
3363 {
3364         if (!mem)
3365                 return I40E_ERR_PARAM;
3366
3367         mem->size = size;
3368         mem->va = rte_zmalloc("i40e", size, 0);
3369
3370         if (mem->va)
3371                 return I40E_SUCCESS;
3372         else
3373                 return I40E_ERR_NO_MEMORY;
3374 }
3375
3376 /**
3377  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3378  * @hw:   pointer to the HW structure
3379  * @mem:  pointer to mem struct to free
3380  **/
3381 enum i40e_status_code
3382 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3383                      struct i40e_virt_mem *mem)
3384 {
3385         if (!mem)
3386                 return I40E_ERR_PARAM;
3387
3388         rte_free(mem->va);
3389         mem->va = NULL;
3390
3391         return I40E_SUCCESS;
3392 }
3393
3394 void
3395 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3396 {
3397         rte_spinlock_init(&sp->spinlock);
3398 }
3399
3400 void
3401 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3402 {
3403         rte_spinlock_lock(&sp->spinlock);
3404 }
3405
3406 void
3407 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3408 {
3409         rte_spinlock_unlock(&sp->spinlock);
3410 }
3411
3412 void
3413 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3414 {
3415         return;
3416 }
3417
3418 /**
3419  * Get the hardware capabilities, which will be parsed
3420  * and saved into struct i40e_hw.
3421  */
3422 static int
3423 i40e_get_cap(struct i40e_hw *hw)
3424 {
3425         struct i40e_aqc_list_capabilities_element_resp *buf;
3426         uint16_t len, size = 0;
3427         int ret;
3428
3429         /* Calculate a huge enough buff for saving response data temporarily */
3430         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3431                                                 I40E_MAX_CAP_ELE_NUM;
3432         buf = rte_zmalloc("i40e", len, 0);
3433         if (!buf) {
3434                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3435                 return I40E_ERR_NO_MEMORY;
3436         }
3437
3438         /* Get, parse the capabilities and save it to hw */
3439         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3440                         i40e_aqc_opc_list_func_capabilities, NULL);
3441         if (ret != I40E_SUCCESS)
3442                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3443
3444         /* Free the temporary buffer after being used */
3445         rte_free(buf);
3446
3447         return ret;
3448 }
3449
3450 static int
3451 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3452 {
3453         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3454         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3455         uint16_t qp_count = 0, vsi_count = 0;
3456
3457         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3458                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3459                 return -EINVAL;
3460         }
3461         /* Add the parameter init for LFC */
3462         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3463         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3464         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3465
3466         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3467         pf->max_num_vsi = hw->func_caps.num_vsis;
3468         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3469         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3470         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3471
3472         /* FDir queue/VSI allocation */
3473         pf->fdir_qp_offset = 0;
3474         if (hw->func_caps.fd) {
3475                 pf->flags |= I40E_FLAG_FDIR;
3476                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3477         } else {
3478                 pf->fdir_nb_qps = 0;
3479         }
3480         qp_count += pf->fdir_nb_qps;
3481         vsi_count += 1;
3482
3483         /* LAN queue/VSI allocation */
3484         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3485         if (!hw->func_caps.rss) {
3486                 pf->lan_nb_qps = 1;
3487         } else {
3488                 pf->flags |= I40E_FLAG_RSS;
3489                 if (hw->mac.type == I40E_MAC_X722)
3490                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3491                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3492         }
3493         qp_count += pf->lan_nb_qps;
3494         vsi_count += 1;
3495
3496         /* VF queue/VSI allocation */
3497         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3498         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3499                 pf->flags |= I40E_FLAG_SRIOV;
3500                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3501                 pf->vf_num = dev->pci_dev->max_vfs;
3502                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3503                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3504                             pf->vf_nb_qps * pf->vf_num);
3505         } else {
3506                 pf->vf_nb_qps = 0;
3507                 pf->vf_num = 0;
3508         }
3509         qp_count += pf->vf_nb_qps * pf->vf_num;
3510         vsi_count += pf->vf_num;
3511
3512         /* VMDq queue/VSI allocation */
3513         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3514         pf->vmdq_nb_qps = 0;
3515         pf->max_nb_vmdq_vsi = 0;
3516         if (hw->func_caps.vmdq) {
3517                 if (qp_count < hw->func_caps.num_tx_qp &&
3518                         vsi_count < hw->func_caps.num_vsis) {
3519                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3520                                 qp_count) / pf->vmdq_nb_qp_max;
3521
3522                         /* Limit the maximum number of VMDq vsi to the maximum
3523                          * ethdev can support
3524                          */
3525                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3526                                 hw->func_caps.num_vsis - vsi_count);
3527                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3528                                 ETH_64_POOLS);
3529                         if (pf->max_nb_vmdq_vsi) {
3530                                 pf->flags |= I40E_FLAG_VMDQ;
3531                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3532                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3533                                             "per VMDQ VSI, in total %u queues",
3534                                             pf->max_nb_vmdq_vsi,
3535                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3536                                             pf->max_nb_vmdq_vsi);
3537                         } else {
3538                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3539                                             "VMDq");
3540                         }
3541                 } else {
3542                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3543                 }
3544         }
3545         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3546         vsi_count += pf->max_nb_vmdq_vsi;
3547
3548         if (hw->func_caps.dcb)
3549                 pf->flags |= I40E_FLAG_DCB;
3550
3551         if (qp_count > hw->func_caps.num_tx_qp) {
3552                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3553                             "the hardware maximum %u", qp_count,
3554                             hw->func_caps.num_tx_qp);
3555                 return -EINVAL;
3556         }
3557         if (vsi_count > hw->func_caps.num_vsis) {
3558                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3559                             "the hardware maximum %u", vsi_count,
3560                             hw->func_caps.num_vsis);
3561                 return -EINVAL;
3562         }
3563
3564         return 0;
3565 }
3566
3567 static int
3568 i40e_pf_get_switch_config(struct i40e_pf *pf)
3569 {
3570         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3571         struct i40e_aqc_get_switch_config_resp *switch_config;
3572         struct i40e_aqc_switch_config_element_resp *element;
3573         uint16_t start_seid = 0, num_reported;
3574         int ret;
3575
3576         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3577                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3578         if (!switch_config) {
3579                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3580                 return -ENOMEM;
3581         }
3582
3583         /* Get the switch configurations */
3584         ret = i40e_aq_get_switch_config(hw, switch_config,
3585                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3586         if (ret != I40E_SUCCESS) {
3587                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3588                 goto fail;
3589         }
3590         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3591         if (num_reported != 1) { /* The number should be 1 */
3592                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3593                 goto fail;
3594         }
3595
3596         /* Parse the switch configuration elements */
3597         element = &(switch_config->element[0]);
3598         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3599                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3600                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3601         } else
3602                 PMD_DRV_LOG(INFO, "Unknown element type");
3603
3604 fail:
3605         rte_free(switch_config);
3606
3607         return ret;
3608 }
3609
3610 static int
3611 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3612                         uint32_t num)
3613 {
3614         struct pool_entry *entry;
3615
3616         if (pool == NULL || num == 0)
3617                 return -EINVAL;
3618
3619         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3620         if (entry == NULL) {
3621                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3622                 return -ENOMEM;
3623         }
3624
3625         /* queue heap initialize */
3626         pool->num_free = num;
3627         pool->num_alloc = 0;
3628         pool->base = base;
3629         LIST_INIT(&pool->alloc_list);
3630         LIST_INIT(&pool->free_list);
3631
3632         /* Initialize element  */
3633         entry->base = 0;
3634         entry->len = num;
3635
3636         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3637         return 0;
3638 }
3639
3640 static void
3641 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3642 {
3643         struct pool_entry *entry, *next_entry;
3644
3645         if (pool == NULL)
3646                 return;
3647
3648         for (entry = LIST_FIRST(&pool->alloc_list);
3649                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3650                         entry = next_entry) {
3651                 LIST_REMOVE(entry, next);
3652                 rte_free(entry);
3653         }
3654
3655         for (entry = LIST_FIRST(&pool->free_list);
3656                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3657                         entry = next_entry) {
3658                 LIST_REMOVE(entry, next);
3659                 rte_free(entry);
3660         }
3661
3662         pool->num_free = 0;
3663         pool->num_alloc = 0;
3664         pool->base = 0;
3665         LIST_INIT(&pool->alloc_list);
3666         LIST_INIT(&pool->free_list);
3667 }
3668
3669 static int
3670 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3671                        uint32_t base)
3672 {
3673         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3674         uint32_t pool_offset;
3675         int insert;
3676
3677         if (pool == NULL) {
3678                 PMD_DRV_LOG(ERR, "Invalid parameter");
3679                 return -EINVAL;
3680         }
3681
3682         pool_offset = base - pool->base;
3683         /* Lookup in alloc list */
3684         LIST_FOREACH(entry, &pool->alloc_list, next) {
3685                 if (entry->base == pool_offset) {
3686                         valid_entry = entry;
3687                         LIST_REMOVE(entry, next);
3688                         break;
3689                 }
3690         }
3691
3692         /* Not find, return */
3693         if (valid_entry == NULL) {
3694                 PMD_DRV_LOG(ERR, "Failed to find entry");
3695                 return -EINVAL;
3696         }
3697
3698         /**
3699          * Found it, move it to free list  and try to merge.
3700          * In order to make merge easier, always sort it by qbase.
3701          * Find adjacent prev and last entries.
3702          */
3703         prev = next = NULL;
3704         LIST_FOREACH(entry, &pool->free_list, next) {
3705                 if (entry->base > valid_entry->base) {
3706                         next = entry;
3707                         break;
3708                 }
3709                 prev = entry;
3710         }
3711
3712         insert = 0;
3713         /* Try to merge with next one*/
3714         if (next != NULL) {
3715                 /* Merge with next one */
3716                 if (valid_entry->base + valid_entry->len == next->base) {
3717                         next->base = valid_entry->base;
3718                         next->len += valid_entry->len;
3719                         rte_free(valid_entry);
3720                         valid_entry = next;
3721                         insert = 1;
3722                 }
3723         }
3724
3725         if (prev != NULL) {
3726                 /* Merge with previous one */
3727                 if (prev->base + prev->len == valid_entry->base) {
3728                         prev->len += valid_entry->len;
3729                         /* If it merge with next one, remove next node */
3730                         if (insert == 1) {
3731                                 LIST_REMOVE(valid_entry, next);
3732                                 rte_free(valid_entry);
3733                         } else {
3734                                 rte_free(valid_entry);
3735                                 insert = 1;
3736                         }
3737                 }
3738         }
3739
3740         /* Not find any entry to merge, insert */
3741         if (insert == 0) {
3742                 if (prev != NULL)
3743                         LIST_INSERT_AFTER(prev, valid_entry, next);
3744                 else if (next != NULL)
3745                         LIST_INSERT_BEFORE(next, valid_entry, next);
3746                 else /* It's empty list, insert to head */
3747                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3748         }
3749
3750         pool->num_free += valid_entry->len;
3751         pool->num_alloc -= valid_entry->len;
3752
3753         return 0;
3754 }
3755
3756 static int
3757 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3758                        uint16_t num)
3759 {
3760         struct pool_entry *entry, *valid_entry;
3761
3762         if (pool == NULL || num == 0) {
3763                 PMD_DRV_LOG(ERR, "Invalid parameter");
3764                 return -EINVAL;
3765         }
3766
3767         if (pool->num_free < num) {
3768                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3769                             num, pool->num_free);
3770                 return -ENOMEM;
3771         }
3772
3773         valid_entry = NULL;
3774         /* Lookup  in free list and find most fit one */
3775         LIST_FOREACH(entry, &pool->free_list, next) {
3776                 if (entry->len >= num) {
3777                         /* Find best one */
3778                         if (entry->len == num) {
3779                                 valid_entry = entry;
3780                                 break;
3781                         }
3782                         if (valid_entry == NULL || valid_entry->len > entry->len)
3783                                 valid_entry = entry;
3784                 }
3785         }
3786
3787         /* Not find one to satisfy the request, return */
3788         if (valid_entry == NULL) {
3789                 PMD_DRV_LOG(ERR, "No valid entry found");
3790                 return -ENOMEM;
3791         }
3792         /**
3793          * The entry have equal queue number as requested,
3794          * remove it from alloc_list.
3795          */
3796         if (valid_entry->len == num) {
3797                 LIST_REMOVE(valid_entry, next);
3798         } else {
3799                 /**
3800                  * The entry have more numbers than requested,
3801                  * create a new entry for alloc_list and minus its
3802                  * queue base and number in free_list.
3803                  */
3804                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3805                 if (entry == NULL) {
3806                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3807                                     "resource pool");
3808                         return -ENOMEM;
3809                 }
3810                 entry->base = valid_entry->base;
3811                 entry->len = num;
3812                 valid_entry->base += num;
3813                 valid_entry->len -= num;
3814                 valid_entry = entry;
3815         }
3816
3817         /* Insert it into alloc list, not sorted */
3818         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3819
3820         pool->num_free -= valid_entry->len;
3821         pool->num_alloc += valid_entry->len;
3822
3823         return valid_entry->base + pool->base;
3824 }
3825
3826 /**
3827  * bitmap_is_subset - Check whether src2 is subset of src1
3828  **/
3829 static inline int
3830 bitmap_is_subset(uint8_t src1, uint8_t src2)
3831 {
3832         return !((src1 ^ src2) & src2);
3833 }
3834
3835 static enum i40e_status_code
3836 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3837 {
3838         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3839
3840         /* If DCB is not supported, only default TC is supported */
3841         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3842                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3843                 return I40E_NOT_SUPPORTED;
3844         }
3845
3846         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3847                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3848                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3849                             enabled_tcmap);
3850                 return I40E_NOT_SUPPORTED;
3851         }
3852         return I40E_SUCCESS;
3853 }
3854
3855 int
3856 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3857                                 struct i40e_vsi_vlan_pvid_info *info)
3858 {
3859         struct i40e_hw *hw;
3860         struct i40e_vsi_context ctxt;
3861         uint8_t vlan_flags = 0;
3862         int ret;
3863
3864         if (vsi == NULL || info == NULL) {
3865                 PMD_DRV_LOG(ERR, "invalid parameters");
3866                 return I40E_ERR_PARAM;
3867         }
3868
3869         if (info->on) {
3870                 vsi->info.pvid = info->config.pvid;
3871                 /**
3872                  * If insert pvid is enabled, only tagged pkts are
3873                  * allowed to be sent out.
3874                  */
3875                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3876                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3877         } else {
3878                 vsi->info.pvid = 0;
3879                 if (info->config.reject.tagged == 0)
3880                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3881
3882                 if (info->config.reject.untagged == 0)
3883                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3884         }
3885         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3886                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3887         vsi->info.port_vlan_flags |= vlan_flags;
3888         vsi->info.valid_sections =
3889                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3890         memset(&ctxt, 0, sizeof(ctxt));
3891         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3892         ctxt.seid = vsi->seid;
3893
3894         hw = I40E_VSI_TO_HW(vsi);
3895         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3896         if (ret != I40E_SUCCESS)
3897                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3898
3899         return ret;
3900 }
3901
3902 static int
3903 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3904 {
3905         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3906         int i, ret;
3907         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3908
3909         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3910         if (ret != I40E_SUCCESS)
3911                 return ret;
3912
3913         if (!vsi->seid) {
3914                 PMD_DRV_LOG(ERR, "seid not valid");
3915                 return -EINVAL;
3916         }
3917
3918         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3919         tc_bw_data.tc_valid_bits = enabled_tcmap;
3920         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3921                 tc_bw_data.tc_bw_credits[i] =
3922                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3923
3924         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3925         if (ret != I40E_SUCCESS) {
3926                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3927                 return ret;
3928         }
3929
3930         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3931                                         sizeof(vsi->info.qs_handle));
3932         return I40E_SUCCESS;
3933 }
3934
3935 static enum i40e_status_code
3936 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3937                                  struct i40e_aqc_vsi_properties_data *info,
3938                                  uint8_t enabled_tcmap)
3939 {
3940         enum i40e_status_code ret;
3941         int i, total_tc = 0;
3942         uint16_t qpnum_per_tc, bsf, qp_idx;
3943
3944         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3945         if (ret != I40E_SUCCESS)
3946                 return ret;
3947
3948         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3949                 if (enabled_tcmap & (1 << i))
3950                         total_tc++;
3951         vsi->enabled_tc = enabled_tcmap;
3952
3953         /* Number of queues per enabled TC */
3954         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3955         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3956         bsf = rte_bsf32(qpnum_per_tc);
3957
3958         /* Adjust the queue number to actual queues that can be applied */
3959         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3960                 vsi->nb_qps = qpnum_per_tc * total_tc;
3961
3962         /**
3963          * Configure TC and queue mapping parameters, for enabled TC,
3964          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3965          * default queue will serve it.
3966          */
3967         qp_idx = 0;
3968         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3969                 if (vsi->enabled_tc & (1 << i)) {
3970                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3971                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3972                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3973                         qp_idx += qpnum_per_tc;
3974                 } else
3975                         info->tc_mapping[i] = 0;
3976         }
3977
3978         /* Associate queue number with VSI */
3979         if (vsi->type == I40E_VSI_SRIOV) {
3980                 info->mapping_flags |=
3981                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3982                 for (i = 0; i < vsi->nb_qps; i++)
3983                         info->queue_mapping[i] =
3984                                 rte_cpu_to_le_16(vsi->base_queue + i);
3985         } else {
3986                 info->mapping_flags |=
3987                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3988                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3989         }
3990         info->valid_sections |=
3991                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3992
3993         return I40E_SUCCESS;
3994 }
3995
3996 static int
3997 i40e_veb_release(struct i40e_veb *veb)
3998 {
3999         struct i40e_vsi *vsi;
4000         struct i40e_hw *hw;
4001
4002         if (veb == NULL)
4003                 return -EINVAL;
4004
4005         if (!TAILQ_EMPTY(&veb->head)) {
4006                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4007                 return -EACCES;
4008         }
4009         /* associate_vsi field is NULL for floating VEB */
4010         if (veb->associate_vsi != NULL) {
4011                 vsi = veb->associate_vsi;
4012                 hw = I40E_VSI_TO_HW(vsi);
4013
4014                 vsi->uplink_seid = veb->uplink_seid;
4015                 vsi->veb = NULL;
4016         } else {
4017                 veb->associate_pf->main_vsi->floating_veb = NULL;
4018                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4019         }
4020
4021         i40e_aq_delete_element(hw, veb->seid, NULL);
4022         rte_free(veb);
4023         return I40E_SUCCESS;
4024 }
4025
4026 /* Setup a veb */
4027 static struct i40e_veb *
4028 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4029 {
4030         struct i40e_veb *veb;
4031         int ret;
4032         struct i40e_hw *hw;
4033
4034         if (pf == NULL) {
4035                 PMD_DRV_LOG(ERR,
4036                             "veb setup failed, associated PF shouldn't null");
4037                 return NULL;
4038         }
4039         hw = I40E_PF_TO_HW(pf);
4040
4041         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4042         if (!veb) {
4043                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4044                 goto fail;
4045         }
4046
4047         veb->associate_vsi = vsi;
4048         veb->associate_pf = pf;
4049         TAILQ_INIT(&veb->head);
4050         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4051
4052         /* create floating veb if vsi is NULL */
4053         if (vsi != NULL) {
4054                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4055                                       I40E_DEFAULT_TCMAP, false,
4056                                       &veb->seid, false, NULL);
4057         } else {
4058                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4059                                       true, &veb->seid, false, NULL);
4060         }
4061
4062         if (ret != I40E_SUCCESS) {
4063                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4064                             hw->aq.asq_last_status);
4065                 goto fail;
4066         }
4067
4068         /* get statistics index */
4069         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4070                                 &veb->stats_idx, NULL, NULL, NULL);
4071         if (ret != I40E_SUCCESS) {
4072                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4073                             hw->aq.asq_last_status);
4074                 goto fail;
4075         }
4076         /* Get VEB bandwidth, to be implemented */
4077         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4078         if (vsi)
4079                 vsi->uplink_seid = veb->seid;
4080
4081         return veb;
4082 fail:
4083         rte_free(veb);
4084         return NULL;
4085 }
4086
4087 int
4088 i40e_vsi_release(struct i40e_vsi *vsi)
4089 {
4090         struct i40e_pf *pf;
4091         struct i40e_hw *hw;
4092         struct i40e_vsi_list *vsi_list;
4093         void *temp;
4094         int ret;
4095         struct i40e_mac_filter *f;
4096         uint16_t user_param = vsi->user_param;
4097
4098         if (!vsi)
4099                 return I40E_SUCCESS;
4100
4101         pf = I40E_VSI_TO_PF(vsi);
4102         hw = I40E_VSI_TO_HW(vsi);
4103
4104         /* VSI has child to attach, release child first */
4105         if (vsi->veb) {
4106                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4107                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4108                                 return -1;
4109                 }
4110                 i40e_veb_release(vsi->veb);
4111         }
4112
4113         if (vsi->floating_veb) {
4114                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4115                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4116                                 return -1;
4117                 }
4118         }
4119
4120         /* Remove all macvlan filters of the VSI */
4121         i40e_vsi_remove_all_macvlan_filter(vsi);
4122         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4123                 rte_free(f);
4124
4125         if (vsi->type != I40E_VSI_MAIN &&
4126             ((vsi->type != I40E_VSI_SRIOV) ||
4127             !pf->floating_veb_list[user_param])) {
4128                 /* Remove vsi from parent's sibling list */
4129                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4130                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4131                         return I40E_ERR_PARAM;
4132                 }
4133                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4134                                 &vsi->sib_vsi_list, list);
4135
4136                 /* Remove all switch element of the VSI */
4137                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4138                 if (ret != I40E_SUCCESS)
4139                         PMD_DRV_LOG(ERR, "Failed to delete element");
4140         }
4141
4142         if ((vsi->type == I40E_VSI_SRIOV) &&
4143             pf->floating_veb_list[user_param]) {
4144                 /* Remove vsi from parent's sibling list */
4145                 if (vsi->parent_vsi == NULL ||
4146                     vsi->parent_vsi->floating_veb == NULL) {
4147                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4148                         return I40E_ERR_PARAM;
4149                 }
4150                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4151                              &vsi->sib_vsi_list, list);
4152
4153                 /* Remove all switch element of the VSI */
4154                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4155                 if (ret != I40E_SUCCESS)
4156                         PMD_DRV_LOG(ERR, "Failed to delete element");
4157         }
4158
4159         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4160
4161         if (vsi->type != I40E_VSI_SRIOV)
4162                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4163         rte_free(vsi);
4164
4165         return I40E_SUCCESS;
4166 }
4167
4168 static int
4169 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4170 {
4171         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4172         struct i40e_aqc_remove_macvlan_element_data def_filter;
4173         struct i40e_mac_filter_info filter;
4174         int ret;
4175
4176         if (vsi->type != I40E_VSI_MAIN)
4177                 return I40E_ERR_CONFIG;
4178         memset(&def_filter, 0, sizeof(def_filter));
4179         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4180                                         ETH_ADDR_LEN);
4181         def_filter.vlan_tag = 0;
4182         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4183                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4184         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4185         if (ret != I40E_SUCCESS) {
4186                 struct i40e_mac_filter *f;
4187                 struct ether_addr *mac;
4188
4189                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4190                             "macvlan filter");
4191                 /* It needs to add the permanent mac into mac list */
4192                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4193                 if (f == NULL) {
4194                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4195                         return I40E_ERR_NO_MEMORY;
4196                 }
4197                 mac = &f->mac_info.mac_addr;
4198                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4199                                 ETH_ADDR_LEN);
4200                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4201                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4202                 vsi->mac_num++;
4203
4204                 return ret;
4205         }
4206         (void)rte_memcpy(&filter.mac_addr,
4207                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4208         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4209         return i40e_vsi_add_mac(vsi, &filter);
4210 }
4211
4212 /*
4213  * i40e_vsi_get_bw_config - Query VSI BW Information
4214  * @vsi: the VSI to be queried
4215  *
4216  * Returns 0 on success, negative value on failure
4217  */
4218 static enum i40e_status_code
4219 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4220 {
4221         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4222         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4223         struct i40e_hw *hw = &vsi->adapter->hw;
4224         i40e_status ret;
4225         int i;
4226         uint32_t bw_max;
4227
4228         memset(&bw_config, 0, sizeof(bw_config));
4229         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4230         if (ret != I40E_SUCCESS) {
4231                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4232                             hw->aq.asq_last_status);
4233                 return ret;
4234         }
4235
4236         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4237         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4238                                         &ets_sla_config, NULL);
4239         if (ret != I40E_SUCCESS) {
4240                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4241                             "configuration %u", hw->aq.asq_last_status);
4242                 return ret;
4243         }
4244
4245         /* store and print out BW info */
4246         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4247         vsi->bw_info.bw_max = bw_config.max_bw;
4248         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4249         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4250         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4251                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4252                      I40E_16_BIT_WIDTH);
4253         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4254                 vsi->bw_info.bw_ets_share_credits[i] =
4255                                 ets_sla_config.share_credits[i];
4256                 vsi->bw_info.bw_ets_credits[i] =
4257                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4258                 /* 4 bits per TC, 4th bit is reserved */
4259                 vsi->bw_info.bw_ets_max[i] =
4260                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4261                                   RTE_LEN2MASK(3, uint8_t));
4262                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4263                             vsi->bw_info.bw_ets_share_credits[i]);
4264                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4265                             vsi->bw_info.bw_ets_credits[i]);
4266                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4267                             vsi->bw_info.bw_ets_max[i]);
4268         }
4269
4270         return I40E_SUCCESS;
4271 }
4272
4273 /* i40e_enable_pf_lb
4274  * @pf: pointer to the pf structure
4275  *
4276  * allow loopback on pf
4277  */
4278 static inline void
4279 i40e_enable_pf_lb(struct i40e_pf *pf)
4280 {
4281         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4282         struct i40e_vsi_context ctxt;
4283         int ret;
4284
4285         /* Use the FW API if FW >= v5.0 */
4286         if (hw->aq.fw_maj_ver < 5) {
4287                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4288                 return;
4289         }
4290
4291         memset(&ctxt, 0, sizeof(ctxt));
4292         ctxt.seid = pf->main_vsi_seid;
4293         ctxt.pf_num = hw->pf_id;
4294         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4295         if (ret) {
4296                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4297                             ret, hw->aq.asq_last_status);
4298                 return;
4299         }
4300         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4301         ctxt.info.valid_sections =
4302                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4303         ctxt.info.switch_id |=
4304                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4305
4306         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4307         if (ret)
4308                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4309                             hw->aq.asq_last_status);
4310 }
4311
4312 /* Setup a VSI */
4313 struct i40e_vsi *
4314 i40e_vsi_setup(struct i40e_pf *pf,
4315                enum i40e_vsi_type type,
4316                struct i40e_vsi *uplink_vsi,
4317                uint16_t user_param)
4318 {
4319         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4320         struct i40e_vsi *vsi;
4321         struct i40e_mac_filter_info filter;
4322         int ret;
4323         struct i40e_vsi_context ctxt;
4324         struct ether_addr broadcast =
4325                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4326
4327         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4328             uplink_vsi == NULL) {
4329                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4330                             "VSI link shouldn't be NULL");
4331                 return NULL;
4332         }
4333
4334         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4335                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4336                             "uplink VSI should be NULL");
4337                 return NULL;
4338         }
4339
4340         /* two situations
4341          * 1.type is not MAIN and uplink vsi is not NULL
4342          * If uplink vsi didn't setup VEB, create one first under veb field
4343          * 2.type is SRIOV and the uplink is NULL
4344          * If floating VEB is NULL, create one veb under floating veb field
4345          */
4346
4347         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4348             uplink_vsi->veb == NULL) {
4349                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4350
4351                 if (uplink_vsi->veb == NULL) {
4352                         PMD_DRV_LOG(ERR, "VEB setup failed");
4353                         return NULL;
4354                 }
4355                 /* set ALLOWLOOPBACk on pf, when veb is created */
4356                 i40e_enable_pf_lb(pf);
4357         }
4358
4359         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4360             pf->main_vsi->floating_veb == NULL) {
4361                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4362
4363                 if (pf->main_vsi->floating_veb == NULL) {
4364                         PMD_DRV_LOG(ERR, "VEB setup failed");
4365                         return NULL;
4366                 }
4367         }
4368
4369         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4370         if (!vsi) {
4371                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4372                 return NULL;
4373         }
4374         TAILQ_INIT(&vsi->mac_list);
4375         vsi->type = type;
4376         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4377         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4378         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4379         vsi->user_param = user_param;
4380         /* Allocate queues */
4381         switch (vsi->type) {
4382         case I40E_VSI_MAIN  :
4383                 vsi->nb_qps = pf->lan_nb_qps;
4384                 break;
4385         case I40E_VSI_SRIOV :
4386                 vsi->nb_qps = pf->vf_nb_qps;
4387                 break;
4388         case I40E_VSI_VMDQ2:
4389                 vsi->nb_qps = pf->vmdq_nb_qps;
4390                 break;
4391         case I40E_VSI_FDIR:
4392                 vsi->nb_qps = pf->fdir_nb_qps;
4393                 break;
4394         default:
4395                 goto fail_mem;
4396         }
4397         /*
4398          * The filter status descriptor is reported in rx queue 0,
4399          * while the tx queue for fdir filter programming has no
4400          * such constraints, can be non-zero queues.
4401          * To simplify it, choose FDIR vsi use queue 0 pair.
4402          * To make sure it will use queue 0 pair, queue allocation
4403          * need be done before this function is called
4404          */
4405         if (type != I40E_VSI_FDIR) {
4406                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4407                         if (ret < 0) {
4408                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4409                                                 vsi->seid, ret);
4410                                 goto fail_mem;
4411                         }
4412                         vsi->base_queue = ret;
4413         } else
4414                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4415
4416         /* VF has MSIX interrupt in VF range, don't allocate here */
4417         if (type == I40E_VSI_MAIN) {
4418                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4419                                           RTE_MIN(vsi->nb_qps,
4420                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4421                 if (ret < 0) {
4422                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4423                                     vsi->seid, ret);
4424                         goto fail_queue_alloc;
4425                 }
4426                 vsi->msix_intr = ret;
4427                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4428         } else if (type != I40E_VSI_SRIOV) {
4429                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4430                 if (ret < 0) {
4431                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4432                         goto fail_queue_alloc;
4433                 }
4434                 vsi->msix_intr = ret;
4435                 vsi->nb_msix = 1;
4436         } else {
4437                 vsi->msix_intr = 0;
4438                 vsi->nb_msix = 0;
4439         }
4440
4441         /* Add VSI */
4442         if (type == I40E_VSI_MAIN) {
4443                 /* For main VSI, no need to add since it's default one */
4444                 vsi->uplink_seid = pf->mac_seid;
4445                 vsi->seid = pf->main_vsi_seid;
4446                 /* Bind queues with specific MSIX interrupt */
4447                 /**
4448                  * Needs 2 interrupt at least, one for misc cause which will
4449                  * enabled from OS side, Another for queues binding the
4450                  * interrupt from device side only.
4451                  */
4452
4453                 /* Get default VSI parameters from hardware */
4454                 memset(&ctxt, 0, sizeof(ctxt));
4455                 ctxt.seid = vsi->seid;
4456                 ctxt.pf_num = hw->pf_id;
4457                 ctxt.uplink_seid = vsi->uplink_seid;
4458                 ctxt.vf_num = 0;
4459                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4460                 if (ret != I40E_SUCCESS) {
4461                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4462                         goto fail_msix_alloc;
4463                 }
4464                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4465                         sizeof(struct i40e_aqc_vsi_properties_data));
4466                 vsi->vsi_id = ctxt.vsi_number;
4467                 vsi->info.valid_sections = 0;
4468
4469                 /* Configure tc, enabled TC0 only */
4470                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4471                         I40E_SUCCESS) {
4472                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4473                         goto fail_msix_alloc;
4474                 }
4475
4476                 /* TC, queue mapping */
4477                 memset(&ctxt, 0, sizeof(ctxt));
4478                 vsi->info.valid_sections |=
4479                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4480                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4481                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4482                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4483                         sizeof(struct i40e_aqc_vsi_properties_data));
4484                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4485                                                 I40E_DEFAULT_TCMAP);
4486                 if (ret != I40E_SUCCESS) {
4487                         PMD_DRV_LOG(ERR, "Failed to configure "
4488                                     "TC queue mapping");
4489                         goto fail_msix_alloc;
4490                 }
4491                 ctxt.seid = vsi->seid;
4492                 ctxt.pf_num = hw->pf_id;
4493                 ctxt.uplink_seid = vsi->uplink_seid;
4494                 ctxt.vf_num = 0;
4495
4496                 /* Update VSI parameters */
4497                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4498                 if (ret != I40E_SUCCESS) {
4499                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4500                         goto fail_msix_alloc;
4501                 }
4502
4503                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4504                                                 sizeof(vsi->info.tc_mapping));
4505                 (void)rte_memcpy(&vsi->info.queue_mapping,
4506                                 &ctxt.info.queue_mapping,
4507                         sizeof(vsi->info.queue_mapping));
4508                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4509                 vsi->info.valid_sections = 0;
4510
4511                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4512                                 ETH_ADDR_LEN);
4513
4514                 /**
4515                  * Updating default filter settings are necessary to prevent
4516                  * reception of tagged packets.
4517                  * Some old firmware configurations load a default macvlan
4518                  * filter which accepts both tagged and untagged packets.
4519                  * The updating is to use a normal filter instead if needed.
4520                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4521                  * The firmware with correct configurations load the default
4522                  * macvlan filter which is expected and cannot be removed.
4523                  */
4524                 i40e_update_default_filter_setting(vsi);
4525                 i40e_config_qinq(hw, vsi);
4526         } else if (type == I40E_VSI_SRIOV) {
4527                 memset(&ctxt, 0, sizeof(ctxt));
4528                 /**
4529                  * For other VSI, the uplink_seid equals to uplink VSI's
4530                  * uplink_seid since they share same VEB
4531                  */
4532                 if (uplink_vsi == NULL)
4533                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4534                 else
4535                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4536                 ctxt.pf_num = hw->pf_id;
4537                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4538                 ctxt.uplink_seid = vsi->uplink_seid;
4539                 ctxt.connection_type = 0x1;
4540                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4541
4542                 /* Use the VEB configuration if FW >= v5.0 */
4543                 if (hw->aq.fw_maj_ver >= 5) {
4544                         /* Configure switch ID */
4545                         ctxt.info.valid_sections |=
4546                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4547                         ctxt.info.switch_id =
4548                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4549                 }
4550
4551                 /* Configure port/vlan */
4552                 ctxt.info.valid_sections |=
4553                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4554                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4555                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4556                                                 I40E_DEFAULT_TCMAP);
4557                 if (ret != I40E_SUCCESS) {
4558                         PMD_DRV_LOG(ERR, "Failed to configure "
4559                                     "TC queue mapping");
4560                         goto fail_msix_alloc;
4561                 }
4562                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4563                 ctxt.info.valid_sections |=
4564                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4565                 /**
4566                  * Since VSI is not created yet, only configure parameter,
4567                  * will add vsi below.
4568                  */
4569
4570                 i40e_config_qinq(hw, vsi);
4571         } else if (type == I40E_VSI_VMDQ2) {
4572                 memset(&ctxt, 0, sizeof(ctxt));
4573                 /*
4574                  * For other VSI, the uplink_seid equals to uplink VSI's
4575                  * uplink_seid since they share same VEB
4576                  */
4577                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4578                 ctxt.pf_num = hw->pf_id;
4579                 ctxt.vf_num = 0;
4580                 ctxt.uplink_seid = vsi->uplink_seid;
4581                 ctxt.connection_type = 0x1;
4582                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4583
4584                 ctxt.info.valid_sections |=
4585                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4586                 /* user_param carries flag to enable loop back */
4587                 if (user_param) {
4588                         ctxt.info.switch_id =
4589                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4590                         ctxt.info.switch_id |=
4591                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4592                 }
4593
4594                 /* Configure port/vlan */
4595                 ctxt.info.valid_sections |=
4596                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4597                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4598                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4599                                                 I40E_DEFAULT_TCMAP);
4600                 if (ret != I40E_SUCCESS) {
4601                         PMD_DRV_LOG(ERR, "Failed to configure "
4602                                         "TC queue mapping");
4603                         goto fail_msix_alloc;
4604                 }
4605                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4606                 ctxt.info.valid_sections |=
4607                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4608         } else if (type == I40E_VSI_FDIR) {
4609                 memset(&ctxt, 0, sizeof(ctxt));
4610                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4611                 ctxt.pf_num = hw->pf_id;
4612                 ctxt.vf_num = 0;
4613                 ctxt.uplink_seid = vsi->uplink_seid;
4614                 ctxt.connection_type = 0x1;     /* regular data port */
4615                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4616                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4617                                                 I40E_DEFAULT_TCMAP);
4618                 if (ret != I40E_SUCCESS) {
4619                         PMD_DRV_LOG(ERR, "Failed to configure "
4620                                         "TC queue mapping.");
4621                         goto fail_msix_alloc;
4622                 }
4623                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4624                 ctxt.info.valid_sections |=
4625                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4626         } else {
4627                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4628                 goto fail_msix_alloc;
4629         }
4630
4631         if (vsi->type != I40E_VSI_MAIN) {
4632                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4633                 if (ret != I40E_SUCCESS) {
4634                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4635                                     hw->aq.asq_last_status);
4636                         goto fail_msix_alloc;
4637                 }
4638                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4639                 vsi->info.valid_sections = 0;
4640                 vsi->seid = ctxt.seid;
4641                 vsi->vsi_id = ctxt.vsi_number;
4642                 vsi->sib_vsi_list.vsi = vsi;
4643                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4644                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4645                                           &vsi->sib_vsi_list, list);
4646                 } else {
4647                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4648                                           &vsi->sib_vsi_list, list);
4649                 }
4650         }
4651
4652         /* MAC/VLAN configuration */
4653         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4654         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4655
4656         ret = i40e_vsi_add_mac(vsi, &filter);
4657         if (ret != I40E_SUCCESS) {
4658                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4659                 goto fail_msix_alloc;
4660         }
4661
4662         /* Get VSI BW information */
4663         i40e_vsi_get_bw_config(vsi);
4664         return vsi;
4665 fail_msix_alloc:
4666         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4667 fail_queue_alloc:
4668         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4669 fail_mem:
4670         rte_free(vsi);
4671         return NULL;
4672 }
4673
4674 /* Configure vlan filter on or off */
4675 int
4676 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4677 {
4678         int i, num;
4679         struct i40e_mac_filter *f;
4680         void *temp;
4681         struct i40e_mac_filter_info *mac_filter;
4682         enum rte_mac_filter_type desired_filter;
4683         int ret = I40E_SUCCESS;
4684
4685         if (on) {
4686                 /* Filter to match MAC and VLAN */
4687                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4688         } else {
4689                 /* Filter to match only MAC */
4690                 desired_filter = RTE_MAC_PERFECT_MATCH;
4691         }
4692
4693         num = vsi->mac_num;
4694
4695         mac_filter = rte_zmalloc("mac_filter_info_data",
4696                                  num * sizeof(*mac_filter), 0);
4697         if (mac_filter == NULL) {
4698                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4699                 return I40E_ERR_NO_MEMORY;
4700         }
4701
4702         i = 0;
4703
4704         /* Remove all existing mac */
4705         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4706                 mac_filter[i] = f->mac_info;
4707                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4708                 if (ret) {
4709                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4710                                     on ? "enable" : "disable");
4711                         goto DONE;
4712                 }
4713                 i++;
4714         }
4715
4716         /* Override with new filter */
4717         for (i = 0; i < num; i++) {
4718                 mac_filter[i].filter_type = desired_filter;
4719                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4720                 if (ret) {
4721                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4722                                     on ? "enable" : "disable");
4723                         goto DONE;
4724                 }
4725         }
4726
4727 DONE:
4728         rte_free(mac_filter);
4729         return ret;
4730 }
4731
4732 /* Configure vlan stripping on or off */
4733 int
4734 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4735 {
4736         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4737         struct i40e_vsi_context ctxt;
4738         uint8_t vlan_flags;
4739         int ret = I40E_SUCCESS;
4740
4741         /* Check if it has been already on or off */
4742         if (vsi->info.valid_sections &
4743                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4744                 if (on) {
4745                         if ((vsi->info.port_vlan_flags &
4746                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4747                                 return 0; /* already on */
4748                 } else {
4749                         if ((vsi->info.port_vlan_flags &
4750                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4751                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4752                                 return 0; /* already off */
4753                 }
4754         }
4755
4756         if (on)
4757                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4758         else
4759                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4760         vsi->info.valid_sections =
4761                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4762         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4763         vsi->info.port_vlan_flags |= vlan_flags;
4764         ctxt.seid = vsi->seid;
4765         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4766         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4767         if (ret)
4768                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4769                             on ? "enable" : "disable");
4770
4771         return ret;
4772 }
4773
4774 static int
4775 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4776 {
4777         struct rte_eth_dev_data *data = dev->data;
4778         int ret;
4779         int mask = 0;
4780
4781         /* Apply vlan offload setting */
4782         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4783         i40e_vlan_offload_set(dev, mask);
4784
4785         /* Apply double-vlan setting, not implemented yet */
4786
4787         /* Apply pvid setting */
4788         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4789                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4790         if (ret)
4791                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4792
4793         return ret;
4794 }
4795
4796 static int
4797 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4798 {
4799         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4800
4801         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4802 }
4803
4804 static int
4805 i40e_update_flow_control(struct i40e_hw *hw)
4806 {
4807 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4808         struct i40e_link_status link_status;
4809         uint32_t rxfc = 0, txfc = 0, reg;
4810         uint8_t an_info;
4811         int ret;
4812
4813         memset(&link_status, 0, sizeof(link_status));
4814         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4815         if (ret != I40E_SUCCESS) {
4816                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4817                 goto write_reg; /* Disable flow control */
4818         }
4819
4820         an_info = hw->phy.link_info.an_info;
4821         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4822                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4823                 ret = I40E_ERR_NOT_READY;
4824                 goto write_reg; /* Disable flow control */
4825         }
4826         /**
4827          * If link auto negotiation is enabled, flow control needs to
4828          * be configured according to it
4829          */
4830         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4831         case I40E_LINK_PAUSE_RXTX:
4832                 rxfc = 1;
4833                 txfc = 1;
4834                 hw->fc.current_mode = I40E_FC_FULL;
4835                 break;
4836         case I40E_AQ_LINK_PAUSE_RX:
4837                 rxfc = 1;
4838                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4839                 break;
4840         case I40E_AQ_LINK_PAUSE_TX:
4841                 txfc = 1;
4842                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4843                 break;
4844         default:
4845                 hw->fc.current_mode = I40E_FC_NONE;
4846                 break;
4847         }
4848
4849 write_reg:
4850         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4851                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4852         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4853         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4854         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4855         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4856
4857         return ret;
4858 }
4859
4860 /* PF setup */
4861 static int
4862 i40e_pf_setup(struct i40e_pf *pf)
4863 {
4864         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4865         struct i40e_filter_control_settings settings;
4866         struct i40e_vsi *vsi;
4867         int ret;
4868
4869         /* Clear all stats counters */
4870         pf->offset_loaded = FALSE;
4871         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4872         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4873
4874         ret = i40e_pf_get_switch_config(pf);
4875         if (ret != I40E_SUCCESS) {
4876                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4877                 return ret;
4878         }
4879         if (pf->flags & I40E_FLAG_FDIR) {
4880                 /* make queue allocated first, let FDIR use queue pair 0*/
4881                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4882                 if (ret != I40E_FDIR_QUEUE_ID) {
4883                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4884                                     " ret =%d", ret);
4885                         pf->flags &= ~I40E_FLAG_FDIR;
4886                 }
4887         }
4888         /*  main VSI setup */
4889         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4890         if (!vsi) {
4891                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4892                 return I40E_ERR_NOT_READY;
4893         }
4894         pf->main_vsi = vsi;
4895
4896         /* Configure filter control */
4897         memset(&settings, 0, sizeof(settings));
4898         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4899                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4900         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4901                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4902         else {
4903                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4904                                                 hw->func_caps.rss_table_size);
4905                 return I40E_ERR_PARAM;
4906         }
4907         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4908                         "size: %u\n", hw->func_caps.rss_table_size);
4909         pf->hash_lut_size = hw->func_caps.rss_table_size;
4910
4911         /* Enable ethtype and macvlan filters */
4912         settings.enable_ethtype = TRUE;
4913         settings.enable_macvlan = TRUE;
4914         ret = i40e_set_filter_control(hw, &settings);
4915         if (ret)
4916                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4917                                                                 ret);
4918
4919         /* Update flow control according to the auto negotiation */
4920         i40e_update_flow_control(hw);
4921
4922         return I40E_SUCCESS;
4923 }
4924
4925 int
4926 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4927 {
4928         uint32_t reg;
4929         uint16_t j;
4930
4931         /**
4932          * Set or clear TX Queue Disable flags,
4933          * which is required by hardware.
4934          */
4935         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4936         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4937
4938         /* Wait until the request is finished */
4939         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4940                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4941                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4942                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4943                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4944                                                         & 0x1))) {
4945                         break;
4946                 }
4947         }
4948         if (on) {
4949                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4950                         return I40E_SUCCESS; /* already on, skip next steps */
4951
4952                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4953                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4954         } else {
4955                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4956                         return I40E_SUCCESS; /* already off, skip next steps */
4957                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4958         }
4959         /* Write the register */
4960         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4961         /* Check the result */
4962         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4963                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4964                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4965                 if (on) {
4966                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4967                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4968                                 break;
4969                 } else {
4970                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4971                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4972                                 break;
4973                 }
4974         }
4975         /* Check if it is timeout */
4976         if (j >= I40E_CHK_Q_ENA_COUNT) {
4977                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4978                             (on ? "enable" : "disable"), q_idx);
4979                 return I40E_ERR_TIMEOUT;
4980         }
4981
4982         return I40E_SUCCESS;
4983 }
4984
4985 /* Swith on or off the tx queues */
4986 static int
4987 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4988 {
4989         struct rte_eth_dev_data *dev_data = pf->dev_data;
4990         struct i40e_tx_queue *txq;
4991         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4992         uint16_t i;
4993         int ret;
4994
4995         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4996                 txq = dev_data->tx_queues[i];
4997                 /* Don't operate the queue if not configured or
4998                  * if starting only per queue */
4999                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5000                         continue;
5001                 if (on)
5002                         ret = i40e_dev_tx_queue_start(dev, i);
5003                 else
5004                         ret = i40e_dev_tx_queue_stop(dev, i);
5005                 if ( ret != I40E_SUCCESS)
5006                         return ret;
5007         }
5008
5009         return I40E_SUCCESS;
5010 }
5011
5012 int
5013 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5014 {
5015         uint32_t reg;
5016         uint16_t j;
5017
5018         /* Wait until the request is finished */
5019         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5020                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5021                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5022                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5023                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5024                         break;
5025         }
5026
5027         if (on) {
5028                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5029                         return I40E_SUCCESS; /* Already on, skip next steps */
5030                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5031         } else {
5032                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5033                         return I40E_SUCCESS; /* Already off, skip next steps */
5034                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5035         }
5036
5037         /* Write the register */
5038         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5039         /* Check the result */
5040         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5041                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5042                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5043                 if (on) {
5044                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5045                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5046                                 break;
5047                 } else {
5048                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5049                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5050                                 break;
5051                 }
5052         }
5053
5054         /* Check if it is timeout */
5055         if (j >= I40E_CHK_Q_ENA_COUNT) {
5056                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5057                             (on ? "enable" : "disable"), q_idx);
5058                 return I40E_ERR_TIMEOUT;
5059         }
5060
5061         return I40E_SUCCESS;
5062 }
5063 /* Switch on or off the rx queues */
5064 static int
5065 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5066 {
5067         struct rte_eth_dev_data *dev_data = pf->dev_data;
5068         struct i40e_rx_queue *rxq;
5069         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5070         uint16_t i;
5071         int ret;
5072
5073         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5074                 rxq = dev_data->rx_queues[i];
5075                 /* Don't operate the queue if not configured or
5076                  * if starting only per queue */
5077                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5078                         continue;
5079                 if (on)
5080                         ret = i40e_dev_rx_queue_start(dev, i);
5081                 else
5082                         ret = i40e_dev_rx_queue_stop(dev, i);
5083                 if (ret != I40E_SUCCESS)
5084                         return ret;
5085         }
5086
5087         return I40E_SUCCESS;
5088 }
5089
5090 /* Switch on or off all the rx/tx queues */
5091 int
5092 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5093 {
5094         int ret;
5095
5096         if (on) {
5097                 /* enable rx queues before enabling tx queues */
5098                 ret = i40e_dev_switch_rx_queues(pf, on);
5099                 if (ret) {
5100                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5101                         return ret;
5102                 }
5103                 ret = i40e_dev_switch_tx_queues(pf, on);
5104         } else {
5105                 /* Stop tx queues before stopping rx queues */
5106                 ret = i40e_dev_switch_tx_queues(pf, on);
5107                 if (ret) {
5108                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5109                         return ret;
5110                 }
5111                 ret = i40e_dev_switch_rx_queues(pf, on);
5112         }
5113
5114         return ret;
5115 }
5116
5117 /* Initialize VSI for TX */
5118 static int
5119 i40e_dev_tx_init(struct i40e_pf *pf)
5120 {
5121         struct rte_eth_dev_data *data = pf->dev_data;
5122         uint16_t i;
5123         uint32_t ret = I40E_SUCCESS;
5124         struct i40e_tx_queue *txq;
5125
5126         for (i = 0; i < data->nb_tx_queues; i++) {
5127                 txq = data->tx_queues[i];
5128                 if (!txq || !txq->q_set)
5129                         continue;
5130                 ret = i40e_tx_queue_init(txq);
5131                 if (ret != I40E_SUCCESS)
5132                         break;
5133         }
5134         if (ret == I40E_SUCCESS)
5135                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5136                                      ->eth_dev);
5137
5138         return ret;
5139 }
5140
5141 /* Initialize VSI for RX */
5142 static int
5143 i40e_dev_rx_init(struct i40e_pf *pf)
5144 {
5145         struct rte_eth_dev_data *data = pf->dev_data;
5146         int ret = I40E_SUCCESS;
5147         uint16_t i;
5148         struct i40e_rx_queue *rxq;
5149
5150         i40e_pf_config_mq_rx(pf);
5151         for (i = 0; i < data->nb_rx_queues; i++) {
5152                 rxq = data->rx_queues[i];
5153                 if (!rxq || !rxq->q_set)
5154                         continue;
5155
5156                 ret = i40e_rx_queue_init(rxq);
5157                 if (ret != I40E_SUCCESS) {
5158                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5159                                     "initialization");
5160                         break;
5161                 }
5162         }
5163         if (ret == I40E_SUCCESS)
5164                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5165                                      ->eth_dev);
5166
5167         return ret;
5168 }
5169
5170 static int
5171 i40e_dev_rxtx_init(struct i40e_pf *pf)
5172 {
5173         int err;
5174
5175         err = i40e_dev_tx_init(pf);
5176         if (err) {
5177                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5178                 return err;
5179         }
5180         err = i40e_dev_rx_init(pf);
5181         if (err) {
5182                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5183                 return err;
5184         }
5185
5186         return err;
5187 }
5188
5189 static int
5190 i40e_vmdq_setup(struct rte_eth_dev *dev)
5191 {
5192         struct rte_eth_conf *conf = &dev->data->dev_conf;
5193         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5194         int i, err, conf_vsis, j, loop;
5195         struct i40e_vsi *vsi;
5196         struct i40e_vmdq_info *vmdq_info;
5197         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5198         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5199
5200         /*
5201          * Disable interrupt to avoid message from VF. Furthermore, it will
5202          * avoid race condition in VSI creation/destroy.
5203          */
5204         i40e_pf_disable_irq0(hw);
5205
5206         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5207                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5208                 return -ENOTSUP;
5209         }
5210
5211         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5212         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5213                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5214                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5215                         pf->max_nb_vmdq_vsi);
5216                 return -ENOTSUP;
5217         }
5218
5219         if (pf->vmdq != NULL) {
5220                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5221                 return 0;
5222         }
5223
5224         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5225                                 sizeof(*vmdq_info) * conf_vsis, 0);
5226
5227         if (pf->vmdq == NULL) {
5228                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5229                 return -ENOMEM;
5230         }
5231
5232         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5233
5234         /* Create VMDQ VSI */
5235         for (i = 0; i < conf_vsis; i++) {
5236                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5237                                 vmdq_conf->enable_loop_back);
5238                 if (vsi == NULL) {
5239                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5240                         err = -1;
5241                         goto err_vsi_setup;
5242                 }
5243                 vmdq_info = &pf->vmdq[i];
5244                 vmdq_info->pf = pf;
5245                 vmdq_info->vsi = vsi;
5246         }
5247         pf->nb_cfg_vmdq_vsi = conf_vsis;
5248
5249         /* Configure Vlan */
5250         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5251         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5252                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5253                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5254                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5255                                         vmdq_conf->pool_map[i].vlan_id, j);
5256
5257                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5258                                                 vmdq_conf->pool_map[i].vlan_id);
5259                                 if (err) {
5260                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5261                                         err = -1;
5262                                         goto err_vsi_setup;
5263                                 }
5264                         }
5265                 }
5266         }
5267
5268         i40e_pf_enable_irq0(hw);
5269
5270         return 0;
5271
5272 err_vsi_setup:
5273         for (i = 0; i < conf_vsis; i++)
5274                 if (pf->vmdq[i].vsi == NULL)
5275                         break;
5276                 else
5277                         i40e_vsi_release(pf->vmdq[i].vsi);
5278
5279         rte_free(pf->vmdq);
5280         pf->vmdq = NULL;
5281         i40e_pf_enable_irq0(hw);
5282         return err;
5283 }
5284
5285 static void
5286 i40e_stat_update_32(struct i40e_hw *hw,
5287                    uint32_t reg,
5288                    bool offset_loaded,
5289                    uint64_t *offset,
5290                    uint64_t *stat)
5291 {
5292         uint64_t new_data;
5293
5294         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5295         if (!offset_loaded)
5296                 *offset = new_data;
5297
5298         if (new_data >= *offset)
5299                 *stat = (uint64_t)(new_data - *offset);
5300         else
5301                 *stat = (uint64_t)((new_data +
5302                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5303 }
5304
5305 static void
5306 i40e_stat_update_48(struct i40e_hw *hw,
5307                    uint32_t hireg,
5308                    uint32_t loreg,
5309                    bool offset_loaded,
5310                    uint64_t *offset,
5311                    uint64_t *stat)
5312 {
5313         uint64_t new_data;
5314
5315         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5316         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5317                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5318
5319         if (!offset_loaded)
5320                 *offset = new_data;
5321
5322         if (new_data >= *offset)
5323                 *stat = new_data - *offset;
5324         else
5325                 *stat = (uint64_t)((new_data +
5326                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5327
5328         *stat &= I40E_48_BIT_MASK;
5329 }
5330
5331 /* Disable IRQ0 */
5332 void
5333 i40e_pf_disable_irq0(struct i40e_hw *hw)
5334 {
5335         /* Disable all interrupt types */
5336         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5337         I40E_WRITE_FLUSH(hw);
5338 }
5339
5340 /* Enable IRQ0 */
5341 void
5342 i40e_pf_enable_irq0(struct i40e_hw *hw)
5343 {
5344         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5345                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5346                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5347                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5348         I40E_WRITE_FLUSH(hw);
5349 }
5350
5351 static void
5352 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5353 {
5354         /* read pending request and disable first */
5355         i40e_pf_disable_irq0(hw);
5356         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5357         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5358                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5359
5360         if (no_queue)
5361                 /* Link no queues with irq0 */
5362                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5363                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5364 }
5365
5366 static void
5367 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5368 {
5369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5371         int i;
5372         uint16_t abs_vf_id;
5373         uint32_t index, offset, val;
5374
5375         if (!pf->vfs)
5376                 return;
5377         /**
5378          * Try to find which VF trigger a reset, use absolute VF id to access
5379          * since the reg is global register.
5380          */
5381         for (i = 0; i < pf->vf_num; i++) {
5382                 abs_vf_id = hw->func_caps.vf_base_id + i;
5383                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5384                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5385                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5386                 /* VFR event occured */
5387                 if (val & (0x1 << offset)) {
5388                         int ret;
5389
5390                         /* Clear the event first */
5391                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5392                                                         (0x1 << offset));
5393                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5394                         /**
5395                          * Only notify a VF reset event occured,
5396                          * don't trigger another SW reset
5397                          */
5398                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5399                         if (ret != I40E_SUCCESS)
5400                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5401                 }
5402         }
5403 }
5404
5405 static void
5406 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5407 {
5408         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5409         struct i40e_arq_event_info info;
5410         uint16_t pending, opcode;
5411         int ret;
5412
5413         info.buf_len = I40E_AQ_BUF_SZ;
5414         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5415         if (!info.msg_buf) {
5416                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5417                 return;
5418         }
5419
5420         pending = 1;
5421         while (pending) {
5422                 ret = i40e_clean_arq_element(hw, &info, &pending);
5423
5424                 if (ret != I40E_SUCCESS) {
5425                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5426                                     "aq_err: %u", hw->aq.asq_last_status);
5427                         break;
5428                 }
5429                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5430
5431                 switch (opcode) {
5432                 case i40e_aqc_opc_send_msg_to_pf:
5433                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5434                         i40e_pf_host_handle_vf_msg(dev,
5435                                         rte_le_to_cpu_16(info.desc.retval),
5436                                         rte_le_to_cpu_32(info.desc.cookie_high),
5437                                         rte_le_to_cpu_32(info.desc.cookie_low),
5438                                         info.msg_buf,
5439                                         info.msg_len);
5440                         break;
5441                 default:
5442                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5443                                     opcode);
5444                         break;
5445                 }
5446         }
5447         rte_free(info.msg_buf);
5448 }
5449
5450 /*
5451  * Interrupt handler is registered as the alarm callback for handling LSC
5452  * interrupt in a definite of time, in order to wait the NIC into a stable
5453  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5454  * no need for link down interrupt.
5455  */
5456 static void
5457 i40e_dev_interrupt_delayed_handler(void *param)
5458 {
5459         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5461         uint32_t icr0;
5462
5463         /* read interrupt causes again */
5464         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5465
5466 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5467         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5468                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5469         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5470                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5471         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5472                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5473         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5474                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5475         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5476                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5477                                                                 "state\n");
5478         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5479                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5480         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5481                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5482 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5483
5484         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5485                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5486                 i40e_dev_handle_vfr_event(dev);
5487         }
5488         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5489                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5490                 i40e_dev_handle_aq_msg(dev);
5491         }
5492
5493         /* handle the link up interrupt in an alarm callback */
5494         i40e_dev_link_update(dev, 0);
5495         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5496
5497         i40e_pf_enable_irq0(hw);
5498         rte_intr_enable(&(dev->pci_dev->intr_handle));
5499 }
5500
5501 /**
5502  * Interrupt handler triggered by NIC  for handling
5503  * specific interrupt.
5504  *
5505  * @param handle
5506  *  Pointer to interrupt handle.
5507  * @param param
5508  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5509  *
5510  * @return
5511  *  void
5512  */
5513 static void
5514 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5515                            void *param)
5516 {
5517         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5519         uint32_t icr0;
5520
5521         /* Disable interrupt */
5522         i40e_pf_disable_irq0(hw);
5523
5524         /* read out interrupt causes */
5525         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5526
5527         /* No interrupt event indicated */
5528         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5529                 PMD_DRV_LOG(INFO, "No interrupt event");
5530                 goto done;
5531         }
5532 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5533         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5534                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5535         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5536                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5537         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5538                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5539         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5540                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5541         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5542                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5543         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5544                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5545         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5546                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5547 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5548
5549         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5550                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5551                 i40e_dev_handle_vfr_event(dev);
5552         }
5553         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5554                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5555                 i40e_dev_handle_aq_msg(dev);
5556         }
5557
5558         /* Link Status Change interrupt */
5559         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5560 #define I40E_US_PER_SECOND 1000000
5561                 struct rte_eth_link link;
5562
5563                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5564                 memset(&link, 0, sizeof(link));
5565                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5566                 i40e_dev_link_update(dev, 0);
5567
5568                 /*
5569                  * For link up interrupt, it needs to wait 1 second to let the
5570                  * hardware be a stable state. Otherwise several consecutive
5571                  * interrupts can be observed.
5572                  * For link down interrupt, no need to wait.
5573                  */
5574                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5575                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5576                         return;
5577                 else
5578                         _rte_eth_dev_callback_process(dev,
5579                                 RTE_ETH_EVENT_INTR_LSC);
5580         }
5581
5582 done:
5583         /* Enable interrupt */
5584         i40e_pf_enable_irq0(hw);
5585         rte_intr_enable(&(dev->pci_dev->intr_handle));
5586 }
5587
5588 static int
5589 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5590                          struct i40e_macvlan_filter *filter,
5591                          int total)
5592 {
5593         int ele_num, ele_buff_size;
5594         int num, actual_num, i;
5595         uint16_t flags;
5596         int ret = I40E_SUCCESS;
5597         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5598         struct i40e_aqc_add_macvlan_element_data *req_list;
5599
5600         if (filter == NULL  || total == 0)
5601                 return I40E_ERR_PARAM;
5602         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5603         ele_buff_size = hw->aq.asq_buf_size;
5604
5605         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5606         if (req_list == NULL) {
5607                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5608                 return I40E_ERR_NO_MEMORY;
5609         }
5610
5611         num = 0;
5612         do {
5613                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5614                 memset(req_list, 0, ele_buff_size);
5615
5616                 for (i = 0; i < actual_num; i++) {
5617                         (void)rte_memcpy(req_list[i].mac_addr,
5618                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5619                         req_list[i].vlan_tag =
5620                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5621
5622                         switch (filter[num + i].filter_type) {
5623                         case RTE_MAC_PERFECT_MATCH:
5624                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5625                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5626                                 break;
5627                         case RTE_MACVLAN_PERFECT_MATCH:
5628                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5629                                 break;
5630                         case RTE_MAC_HASH_MATCH:
5631                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5632                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5633                                 break;
5634                         case RTE_MACVLAN_HASH_MATCH:
5635                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5636                                 break;
5637                         default:
5638                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5639                                 ret = I40E_ERR_PARAM;
5640                                 goto DONE;
5641                         }
5642
5643                         req_list[i].queue_number = 0;
5644
5645                         req_list[i].flags = rte_cpu_to_le_16(flags);
5646                 }
5647
5648                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5649                                                 actual_num, NULL);
5650                 if (ret != I40E_SUCCESS) {
5651                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5652                         goto DONE;
5653                 }
5654                 num += actual_num;
5655         } while (num < total);
5656
5657 DONE:
5658         rte_free(req_list);
5659         return ret;
5660 }
5661
5662 static int
5663 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5664                             struct i40e_macvlan_filter *filter,
5665                             int total)
5666 {
5667         int ele_num, ele_buff_size;
5668         int num, actual_num, i;
5669         uint16_t flags;
5670         int ret = I40E_SUCCESS;
5671         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5672         struct i40e_aqc_remove_macvlan_element_data *req_list;
5673
5674         if (filter == NULL  || total == 0)
5675                 return I40E_ERR_PARAM;
5676
5677         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5678         ele_buff_size = hw->aq.asq_buf_size;
5679
5680         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5681         if (req_list == NULL) {
5682                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5683                 return I40E_ERR_NO_MEMORY;
5684         }
5685
5686         num = 0;
5687         do {
5688                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5689                 memset(req_list, 0, ele_buff_size);
5690
5691                 for (i = 0; i < actual_num; i++) {
5692                         (void)rte_memcpy(req_list[i].mac_addr,
5693                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5694                         req_list[i].vlan_tag =
5695                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5696
5697                         switch (filter[num + i].filter_type) {
5698                         case RTE_MAC_PERFECT_MATCH:
5699                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5700                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5701                                 break;
5702                         case RTE_MACVLAN_PERFECT_MATCH:
5703                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5704                                 break;
5705                         case RTE_MAC_HASH_MATCH:
5706                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5707                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5708                                 break;
5709                         case RTE_MACVLAN_HASH_MATCH:
5710                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5711                                 break;
5712                         default:
5713                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5714                                 ret = I40E_ERR_PARAM;
5715                                 goto DONE;
5716                         }
5717                         req_list[i].flags = rte_cpu_to_le_16(flags);
5718                 }
5719
5720                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5721                                                 actual_num, NULL);
5722                 if (ret != I40E_SUCCESS) {
5723                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5724                         goto DONE;
5725                 }
5726                 num += actual_num;
5727         } while (num < total);
5728
5729 DONE:
5730         rte_free(req_list);
5731         return ret;
5732 }
5733
5734 /* Find out specific MAC filter */
5735 static struct i40e_mac_filter *
5736 i40e_find_mac_filter(struct i40e_vsi *vsi,
5737                          struct ether_addr *macaddr)
5738 {
5739         struct i40e_mac_filter *f;
5740
5741         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5742                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5743                         return f;
5744         }
5745
5746         return NULL;
5747 }
5748
5749 static bool
5750 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5751                          uint16_t vlan_id)
5752 {
5753         uint32_t vid_idx, vid_bit;
5754
5755         if (vlan_id > ETH_VLAN_ID_MAX)
5756                 return 0;
5757
5758         vid_idx = I40E_VFTA_IDX(vlan_id);
5759         vid_bit = I40E_VFTA_BIT(vlan_id);
5760
5761         if (vsi->vfta[vid_idx] & vid_bit)
5762                 return 1;
5763         else
5764                 return 0;
5765 }
5766
5767 static void
5768 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5769                          uint16_t vlan_id, bool on)
5770 {
5771         uint32_t vid_idx, vid_bit;
5772
5773         if (vlan_id > ETH_VLAN_ID_MAX)
5774                 return;
5775
5776         vid_idx = I40E_VFTA_IDX(vlan_id);
5777         vid_bit = I40E_VFTA_BIT(vlan_id);
5778
5779         if (on)
5780                 vsi->vfta[vid_idx] |= vid_bit;
5781         else
5782                 vsi->vfta[vid_idx] &= ~vid_bit;
5783 }
5784
5785 /**
5786  * Find all vlan options for specific mac addr,
5787  * return with actual vlan found.
5788  */
5789 static inline int
5790 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5791                            struct i40e_macvlan_filter *mv_f,
5792                            int num, struct ether_addr *addr)
5793 {
5794         int i;
5795         uint32_t j, k;
5796
5797         /**
5798          * Not to use i40e_find_vlan_filter to decrease the loop time,
5799          * although the code looks complex.
5800           */
5801         if (num < vsi->vlan_num)
5802                 return I40E_ERR_PARAM;
5803
5804         i = 0;
5805         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5806                 if (vsi->vfta[j]) {
5807                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5808                                 if (vsi->vfta[j] & (1 << k)) {
5809                                         if (i > num - 1) {
5810                                                 PMD_DRV_LOG(ERR, "vlan number "
5811                                                             "not match");
5812                                                 return I40E_ERR_PARAM;
5813                                         }
5814                                         (void)rte_memcpy(&mv_f[i].macaddr,
5815                                                         addr, ETH_ADDR_LEN);
5816                                         mv_f[i].vlan_id =
5817                                                 j * I40E_UINT32_BIT_SIZE + k;
5818                                         i++;
5819                                 }
5820                         }
5821                 }
5822         }
5823         return I40E_SUCCESS;
5824 }
5825
5826 static inline int
5827 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5828                            struct i40e_macvlan_filter *mv_f,
5829                            int num,
5830                            uint16_t vlan)
5831 {
5832         int i = 0;
5833         struct i40e_mac_filter *f;
5834
5835         if (num < vsi->mac_num)
5836                 return I40E_ERR_PARAM;
5837
5838         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5839                 if (i > num - 1) {
5840                         PMD_DRV_LOG(ERR, "buffer number not match");
5841                         return I40E_ERR_PARAM;
5842                 }
5843                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5844                                 ETH_ADDR_LEN);
5845                 mv_f[i].vlan_id = vlan;
5846                 mv_f[i].filter_type = f->mac_info.filter_type;
5847                 i++;
5848         }
5849
5850         return I40E_SUCCESS;
5851 }
5852
5853 static int
5854 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5855 {
5856         int i, num;
5857         struct i40e_mac_filter *f;
5858         struct i40e_macvlan_filter *mv_f;
5859         int ret = I40E_SUCCESS;
5860
5861         if (vsi == NULL || vsi->mac_num == 0)
5862                 return I40E_ERR_PARAM;
5863
5864         /* Case that no vlan is set */
5865         if (vsi->vlan_num == 0)
5866                 num = vsi->mac_num;
5867         else
5868                 num = vsi->mac_num * vsi->vlan_num;
5869
5870         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5871         if (mv_f == NULL) {
5872                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5873                 return I40E_ERR_NO_MEMORY;
5874         }
5875
5876         i = 0;
5877         if (vsi->vlan_num == 0) {
5878                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5879                         (void)rte_memcpy(&mv_f[i].macaddr,
5880                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5881                         mv_f[i].vlan_id = 0;
5882                         i++;
5883                 }
5884         } else {
5885                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5886                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5887                                         vsi->vlan_num, &f->mac_info.mac_addr);
5888                         if (ret != I40E_SUCCESS)
5889                                 goto DONE;
5890                         i += vsi->vlan_num;
5891                 }
5892         }
5893
5894         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5895 DONE:
5896         rte_free(mv_f);
5897
5898         return ret;
5899 }
5900
5901 int
5902 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5903 {
5904         struct i40e_macvlan_filter *mv_f;
5905         int mac_num;
5906         int ret = I40E_SUCCESS;
5907
5908         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5909                 return I40E_ERR_PARAM;
5910
5911         /* If it's already set, just return */
5912         if (i40e_find_vlan_filter(vsi,vlan))
5913                 return I40E_SUCCESS;
5914
5915         mac_num = vsi->mac_num;
5916
5917         if (mac_num == 0) {
5918                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5919                 return I40E_ERR_PARAM;
5920         }
5921
5922         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5923
5924         if (mv_f == NULL) {
5925                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5926                 return I40E_ERR_NO_MEMORY;
5927         }
5928
5929         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5930
5931         if (ret != I40E_SUCCESS)
5932                 goto DONE;
5933
5934         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5935
5936         if (ret != I40E_SUCCESS)
5937                 goto DONE;
5938
5939         i40e_set_vlan_filter(vsi, vlan, 1);
5940
5941         vsi->vlan_num++;
5942         ret = I40E_SUCCESS;
5943 DONE:
5944         rte_free(mv_f);
5945         return ret;
5946 }
5947
5948 int
5949 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5950 {
5951         struct i40e_macvlan_filter *mv_f;
5952         int mac_num;
5953         int ret = I40E_SUCCESS;
5954
5955         /**
5956          * Vlan 0 is the generic filter for untagged packets
5957          * and can't be removed.
5958          */
5959         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5960                 return I40E_ERR_PARAM;
5961
5962         /* If can't find it, just return */
5963         if (!i40e_find_vlan_filter(vsi, vlan))
5964                 return I40E_ERR_PARAM;
5965
5966         mac_num = vsi->mac_num;
5967
5968         if (mac_num == 0) {
5969                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5970                 return I40E_ERR_PARAM;
5971         }
5972
5973         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5974
5975         if (mv_f == NULL) {
5976                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5977                 return I40E_ERR_NO_MEMORY;
5978         }
5979
5980         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5981
5982         if (ret != I40E_SUCCESS)
5983                 goto DONE;
5984
5985         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5986
5987         if (ret != I40E_SUCCESS)
5988                 goto DONE;
5989
5990         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5991         if (vsi->vlan_num == 1) {
5992                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5993                 if (ret != I40E_SUCCESS)
5994                         goto DONE;
5995
5996                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5997                 if (ret != I40E_SUCCESS)
5998                         goto DONE;
5999         }
6000
6001         i40e_set_vlan_filter(vsi, vlan, 0);
6002
6003         vsi->vlan_num--;
6004         ret = I40E_SUCCESS;
6005 DONE:
6006         rte_free(mv_f);
6007         return ret;
6008 }
6009
6010 int
6011 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6012 {
6013         struct i40e_mac_filter *f;
6014         struct i40e_macvlan_filter *mv_f;
6015         int i, vlan_num = 0;
6016         int ret = I40E_SUCCESS;
6017
6018         /* If it's add and we've config it, return */
6019         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6020         if (f != NULL)
6021                 return I40E_SUCCESS;
6022         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6023                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6024
6025                 /**
6026                  * If vlan_num is 0, that's the first time to add mac,
6027                  * set mask for vlan_id 0.
6028                  */
6029                 if (vsi->vlan_num == 0) {
6030                         i40e_set_vlan_filter(vsi, 0, 1);
6031                         vsi->vlan_num = 1;
6032                 }
6033                 vlan_num = vsi->vlan_num;
6034         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6035                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6036                 vlan_num = 1;
6037
6038         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6039         if (mv_f == NULL) {
6040                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6041                 return I40E_ERR_NO_MEMORY;
6042         }
6043
6044         for (i = 0; i < vlan_num; i++) {
6045                 mv_f[i].filter_type = mac_filter->filter_type;
6046                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6047                                 ETH_ADDR_LEN);
6048         }
6049
6050         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6051                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6052                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6053                                         &mac_filter->mac_addr);
6054                 if (ret != I40E_SUCCESS)
6055                         goto DONE;
6056         }
6057
6058         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6059         if (ret != I40E_SUCCESS)
6060                 goto DONE;
6061
6062         /* Add the mac addr into mac list */
6063         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6064         if (f == NULL) {
6065                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6066                 ret = I40E_ERR_NO_MEMORY;
6067                 goto DONE;
6068         }
6069         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6070                         ETH_ADDR_LEN);
6071         f->mac_info.filter_type = mac_filter->filter_type;
6072         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6073         vsi->mac_num++;
6074
6075         ret = I40E_SUCCESS;
6076 DONE:
6077         rte_free(mv_f);
6078
6079         return ret;
6080 }
6081
6082 int
6083 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6084 {
6085         struct i40e_mac_filter *f;
6086         struct i40e_macvlan_filter *mv_f;
6087         int i, vlan_num;
6088         enum rte_mac_filter_type filter_type;
6089         int ret = I40E_SUCCESS;
6090
6091         /* Can't find it, return an error */
6092         f = i40e_find_mac_filter(vsi, addr);
6093         if (f == NULL)
6094                 return I40E_ERR_PARAM;
6095
6096         vlan_num = vsi->vlan_num;
6097         filter_type = f->mac_info.filter_type;
6098         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6099                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6100                 if (vlan_num == 0) {
6101                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6102                         return I40E_ERR_PARAM;
6103                 }
6104         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6105                         filter_type == RTE_MAC_HASH_MATCH)
6106                 vlan_num = 1;
6107
6108         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6109         if (mv_f == NULL) {
6110                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6111                 return I40E_ERR_NO_MEMORY;
6112         }
6113
6114         for (i = 0; i < vlan_num; i++) {
6115                 mv_f[i].filter_type = filter_type;
6116                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6117                                 ETH_ADDR_LEN);
6118         }
6119         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6120                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6121                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6122                 if (ret != I40E_SUCCESS)
6123                         goto DONE;
6124         }
6125
6126         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6127         if (ret != I40E_SUCCESS)
6128                 goto DONE;
6129
6130         /* Remove the mac addr into mac list */
6131         TAILQ_REMOVE(&vsi->mac_list, f, next);
6132         rte_free(f);
6133         vsi->mac_num--;
6134
6135         ret = I40E_SUCCESS;
6136 DONE:
6137         rte_free(mv_f);
6138         return ret;
6139 }
6140
6141 /* Configure hash enable flags for RSS */
6142 uint64_t
6143 i40e_config_hena(uint64_t flags)
6144 {
6145         uint64_t hena = 0;
6146
6147         if (!flags)
6148                 return hena;
6149
6150         if (flags & ETH_RSS_FRAG_IPV4)
6151                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6152         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6153 #ifdef X722_SUPPORT
6154                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6155                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6156 #else
6157                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6158 #endif
6159         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6160 #ifdef X722_SUPPORT
6161                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6162                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6163                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6164 #else
6165                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6166 #endif
6167         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6168                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6169         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6170                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6171         if (flags & ETH_RSS_FRAG_IPV6)
6172                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6173         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6174 #ifdef X722_SUPPORT
6175                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6176                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6177 #else
6178                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6179 #endif
6180         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6181 #ifdef X722_SUPPORT
6182                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6183                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6184                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6185 #else
6186                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6187 #endif
6188         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6189                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6190         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6191                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6192         if (flags & ETH_RSS_L2_PAYLOAD)
6193                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6194
6195         return hena;
6196 }
6197
6198 /* Parse the hash enable flags */
6199 uint64_t
6200 i40e_parse_hena(uint64_t flags)
6201 {
6202         uint64_t rss_hf = 0;
6203
6204         if (!flags)
6205                 return rss_hf;
6206         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6207                 rss_hf |= ETH_RSS_FRAG_IPV4;
6208         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6209                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6210 #ifdef X722_SUPPORT
6211         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6212                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6213 #endif
6214         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6215                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6216 #ifdef X722_SUPPORT
6217         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6218                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6219         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6220                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6221 #endif
6222         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6223                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6224         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6225                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6226         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6227                 rss_hf |= ETH_RSS_FRAG_IPV6;
6228         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6229                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6230 #ifdef X722_SUPPORT
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6232                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6233 #endif
6234         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6235                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6236 #ifdef X722_SUPPORT
6237         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6238                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6239         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6240                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6241 #endif
6242         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6243                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6244         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6245                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6246         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6247                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6248
6249         return rss_hf;
6250 }
6251
6252 /* Disable RSS */
6253 static void
6254 i40e_pf_disable_rss(struct i40e_pf *pf)
6255 {
6256         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6257         uint64_t hena;
6258
6259         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6260         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6261         hena &= ~I40E_RSS_HENA_ALL;
6262         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6263         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6264         I40E_WRITE_FLUSH(hw);
6265 }
6266
6267 static int
6268 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6269 {
6270         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6271         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6272         int ret = 0;
6273
6274         if (!key || key_len == 0) {
6275                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6276                 return 0;
6277         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6278                 sizeof(uint32_t)) {
6279                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6280                 return -EINVAL;
6281         }
6282
6283         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6284                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6285                         (struct i40e_aqc_get_set_rss_key_data *)key;
6286
6287                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6288                 if (ret)
6289                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6290                                      "via AQ");
6291         } else {
6292                 uint32_t *hash_key = (uint32_t *)key;
6293                 uint16_t i;
6294
6295                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6296                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6297                 I40E_WRITE_FLUSH(hw);
6298         }
6299
6300         return ret;
6301 }
6302
6303 static int
6304 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6305 {
6306         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6307         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6308         int ret;
6309
6310         if (!key || !key_len)
6311                 return -EINVAL;
6312
6313         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6314                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6315                         (struct i40e_aqc_get_set_rss_key_data *)key);
6316                 if (ret) {
6317                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6318                         return ret;
6319                 }
6320         } else {
6321                 uint32_t *key_dw = (uint32_t *)key;
6322                 uint16_t i;
6323
6324                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6325                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6326         }
6327         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6328
6329         return 0;
6330 }
6331
6332 static int
6333 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6334 {
6335         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6336         uint64_t rss_hf;
6337         uint64_t hena;
6338         int ret;
6339
6340         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6341                                rss_conf->rss_key_len);
6342         if (ret)
6343                 return ret;
6344
6345         rss_hf = rss_conf->rss_hf;
6346         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6347         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6348         hena &= ~I40E_RSS_HENA_ALL;
6349         hena |= i40e_config_hena(rss_hf);
6350         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6351         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6352         I40E_WRITE_FLUSH(hw);
6353
6354         return 0;
6355 }
6356
6357 static int
6358 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6359                          struct rte_eth_rss_conf *rss_conf)
6360 {
6361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6363         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6364         uint64_t hena;
6365
6366         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6367         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6368         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6369                 if (rss_hf != 0) /* Enable RSS */
6370                         return -EINVAL;
6371                 return 0; /* Nothing to do */
6372         }
6373         /* RSS enabled */
6374         if (rss_hf == 0) /* Disable RSS */
6375                 return -EINVAL;
6376
6377         return i40e_hw_rss_hash_set(pf, rss_conf);
6378 }
6379
6380 static int
6381 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6382                            struct rte_eth_rss_conf *rss_conf)
6383 {
6384         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6385         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6386         uint64_t hena;
6387
6388         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6389                          &rss_conf->rss_key_len);
6390
6391         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6392         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6393         rss_conf->rss_hf = i40e_parse_hena(hena);
6394
6395         return 0;
6396 }
6397
6398 static int
6399 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6400 {
6401         switch (filter_type) {
6402         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6403                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6404                 break;
6405         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6406                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6407                 break;
6408         case RTE_TUNNEL_FILTER_IMAC_TENID:
6409                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6410                 break;
6411         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6412                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6413                 break;
6414         case ETH_TUNNEL_FILTER_IMAC:
6415                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6416                 break;
6417         case ETH_TUNNEL_FILTER_OIP:
6418                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6419                 break;
6420         case ETH_TUNNEL_FILTER_IIP:
6421                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6422                 break;
6423         default:
6424                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6425                 return -EINVAL;
6426         }
6427
6428         return 0;
6429 }
6430
6431 static int
6432 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6433                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6434                         uint8_t add)
6435 {
6436         uint16_t ip_type;
6437         uint32_t ipv4_addr;
6438         uint8_t i, tun_type = 0;
6439         /* internal varialbe to convert ipv6 byte order */
6440         uint32_t convert_ipv6[4];
6441         int val, ret = 0;
6442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6443         struct i40e_vsi *vsi = pf->main_vsi;
6444         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6445         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6446
6447         cld_filter = rte_zmalloc("tunnel_filter",
6448                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6449                 0);
6450
6451         if (NULL == cld_filter) {
6452                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6453                 return -EINVAL;
6454         }
6455         pfilter = cld_filter;
6456
6457         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6458         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6459
6460         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6461         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6462                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6463                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6464                 rte_memcpy(&pfilter->ipaddr.v4.data,
6465                                 &rte_cpu_to_le_32(ipv4_addr),
6466                                 sizeof(pfilter->ipaddr.v4.data));
6467         } else {
6468                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6469                 for (i = 0; i < 4; i++) {
6470                         convert_ipv6[i] =
6471                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6472                 }
6473                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6474                                 sizeof(pfilter->ipaddr.v6.data));
6475         }
6476
6477         /* check tunneled type */
6478         switch (tunnel_filter->tunnel_type) {
6479         case RTE_TUNNEL_TYPE_VXLAN:
6480                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6481                 break;
6482         case RTE_TUNNEL_TYPE_NVGRE:
6483                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6484                 break;
6485         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6486                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6487                 break;
6488         default:
6489                 /* Other tunnel types is not supported. */
6490                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6491                 rte_free(cld_filter);
6492                 return -EINVAL;
6493         }
6494
6495         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6496                                                 &pfilter->flags);
6497         if (val < 0) {
6498                 rte_free(cld_filter);
6499                 return -EINVAL;
6500         }
6501
6502         pfilter->flags |= rte_cpu_to_le_16(
6503                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6504                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6505         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6506         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6507
6508         if (add)
6509                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6510         else
6511                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6512                                                 cld_filter, 1);
6513
6514         rte_free(cld_filter);
6515         return ret;
6516 }
6517
6518 static int
6519 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6520 {
6521         uint8_t i;
6522
6523         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6524                 if (pf->vxlan_ports[i] == port)
6525                         return i;
6526         }
6527
6528         return -1;
6529 }
6530
6531 static int
6532 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6533 {
6534         int  idx, ret;
6535         uint8_t filter_idx;
6536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6537
6538         idx = i40e_get_vxlan_port_idx(pf, port);
6539
6540         /* Check if port already exists */
6541         if (idx >= 0) {
6542                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6543                 return -EINVAL;
6544         }
6545
6546         /* Now check if there is space to add the new port */
6547         idx = i40e_get_vxlan_port_idx(pf, 0);
6548         if (idx < 0) {
6549                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6550                         "not adding port %d", port);
6551                 return -ENOSPC;
6552         }
6553
6554         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6555                                         &filter_idx, NULL);
6556         if (ret < 0) {
6557                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6558                 return -1;
6559         }
6560
6561         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6562                          port,  filter_idx);
6563
6564         /* New port: add it and mark its index in the bitmap */
6565         pf->vxlan_ports[idx] = port;
6566         pf->vxlan_bitmap |= (1 << idx);
6567
6568         if (!(pf->flags & I40E_FLAG_VXLAN))
6569                 pf->flags |= I40E_FLAG_VXLAN;
6570
6571         return 0;
6572 }
6573
6574 static int
6575 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6576 {
6577         int idx;
6578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6579
6580         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6581                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6582                 return -EINVAL;
6583         }
6584
6585         idx = i40e_get_vxlan_port_idx(pf, port);
6586
6587         if (idx < 0) {
6588                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6589                 return -EINVAL;
6590         }
6591
6592         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6593                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6594                 return -1;
6595         }
6596
6597         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6598                         port, idx);
6599
6600         pf->vxlan_ports[idx] = 0;
6601         pf->vxlan_bitmap &= ~(1 << idx);
6602
6603         if (!pf->vxlan_bitmap)
6604                 pf->flags &= ~I40E_FLAG_VXLAN;
6605
6606         return 0;
6607 }
6608
6609 /* Add UDP tunneling port */
6610 static int
6611 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6612                              struct rte_eth_udp_tunnel *udp_tunnel)
6613 {
6614         int ret = 0;
6615         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6616
6617         if (udp_tunnel == NULL)
6618                 return -EINVAL;
6619
6620         switch (udp_tunnel->prot_type) {
6621         case RTE_TUNNEL_TYPE_VXLAN:
6622                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6623                 break;
6624
6625         case RTE_TUNNEL_TYPE_GENEVE:
6626         case RTE_TUNNEL_TYPE_TEREDO:
6627                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6628                 ret = -1;
6629                 break;
6630
6631         default:
6632                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6633                 ret = -1;
6634                 break;
6635         }
6636
6637         return ret;
6638 }
6639
6640 /* Remove UDP tunneling port */
6641 static int
6642 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6643                              struct rte_eth_udp_tunnel *udp_tunnel)
6644 {
6645         int ret = 0;
6646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6647
6648         if (udp_tunnel == NULL)
6649                 return -EINVAL;
6650
6651         switch (udp_tunnel->prot_type) {
6652         case RTE_TUNNEL_TYPE_VXLAN:
6653                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6654                 break;
6655         case RTE_TUNNEL_TYPE_GENEVE:
6656         case RTE_TUNNEL_TYPE_TEREDO:
6657                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6658                 ret = -1;
6659                 break;
6660         default:
6661                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6662                 ret = -1;
6663                 break;
6664         }
6665
6666         return ret;
6667 }
6668
6669 /* Calculate the maximum number of contiguous PF queues that are configured */
6670 static int
6671 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6672 {
6673         struct rte_eth_dev_data *data = pf->dev_data;
6674         int i, num;
6675         struct i40e_rx_queue *rxq;
6676
6677         num = 0;
6678         for (i = 0; i < pf->lan_nb_qps; i++) {
6679                 rxq = data->rx_queues[i];
6680                 if (rxq && rxq->q_set)
6681                         num++;
6682                 else
6683                         break;
6684         }
6685
6686         return num;
6687 }
6688
6689 /* Configure RSS */
6690 static int
6691 i40e_pf_config_rss(struct i40e_pf *pf)
6692 {
6693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6694         struct rte_eth_rss_conf rss_conf;
6695         uint32_t i, lut = 0;
6696         uint16_t j, num;
6697
6698         /*
6699          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6700          * It's necessary to calulate the actual PF queues that are configured.
6701          */
6702         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6703                 num = i40e_pf_calc_configured_queues_num(pf);
6704         else
6705                 num = pf->dev_data->nb_rx_queues;
6706
6707         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6708         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6709                         num);
6710
6711         if (num == 0) {
6712                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6713                 return -ENOTSUP;
6714         }
6715
6716         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6717                 if (j == num)
6718                         j = 0;
6719                 lut = (lut << 8) | (j & ((0x1 <<
6720                         hw->func_caps.rss_table_entry_width) - 1));
6721                 if ((i & 3) == 3)
6722                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6723         }
6724
6725         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6726         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6727                 i40e_pf_disable_rss(pf);
6728                 return 0;
6729         }
6730         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6731                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6732                 /* Random default keys */
6733                 static uint32_t rss_key_default[] = {0x6b793944,
6734                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6735                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6736                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6737
6738                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6739                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6740                                                         sizeof(uint32_t);
6741         }
6742
6743         return i40e_hw_rss_hash_set(pf, &rss_conf);
6744 }
6745
6746 static int
6747 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6748                                struct rte_eth_tunnel_filter_conf *filter)
6749 {
6750         if (pf == NULL || filter == NULL) {
6751                 PMD_DRV_LOG(ERR, "Invalid parameter");
6752                 return -EINVAL;
6753         }
6754
6755         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6756                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6757                 return -EINVAL;
6758         }
6759
6760         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6761                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6762                 return -EINVAL;
6763         }
6764
6765         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6766                 (is_zero_ether_addr(&filter->outer_mac))) {
6767                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6768                 return -EINVAL;
6769         }
6770
6771         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6772                 (is_zero_ether_addr(&filter->inner_mac))) {
6773                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6774                 return -EINVAL;
6775         }
6776
6777         return 0;
6778 }
6779
6780 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6781 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6782 static int
6783 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6784 {
6785         uint32_t val, reg;
6786         int ret = -EINVAL;
6787
6788         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6789         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6790
6791         if (len == 3) {
6792                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6793         } else if (len == 4) {
6794                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6795         } else {
6796                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6797                 return ret;
6798         }
6799
6800         if (reg != val) {
6801                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6802                                                    reg, NULL);
6803                 if (ret != 0)
6804                         return ret;
6805         } else {
6806                 ret = 0;
6807         }
6808         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6809                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6810
6811         return ret;
6812 }
6813
6814 static int
6815 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6816 {
6817         int ret = -EINVAL;
6818
6819         if (!hw || !cfg)
6820                 return -EINVAL;
6821
6822         switch (cfg->cfg_type) {
6823         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6824                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6825                 break;
6826         default:
6827                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6828                 break;
6829         }
6830
6831         return ret;
6832 }
6833
6834 static int
6835 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6836                                enum rte_filter_op filter_op,
6837                                void *arg)
6838 {
6839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6840         int ret = I40E_ERR_PARAM;
6841
6842         switch (filter_op) {
6843         case RTE_ETH_FILTER_SET:
6844                 ret = i40e_dev_global_config_set(hw,
6845                         (struct rte_eth_global_cfg *)arg);
6846                 break;
6847         default:
6848                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6849                 break;
6850         }
6851
6852         return ret;
6853 }
6854
6855 static int
6856 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6857                           enum rte_filter_op filter_op,
6858                           void *arg)
6859 {
6860         struct rte_eth_tunnel_filter_conf *filter;
6861         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6862         int ret = I40E_SUCCESS;
6863
6864         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6865
6866         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6867                 return I40E_ERR_PARAM;
6868
6869         switch (filter_op) {
6870         case RTE_ETH_FILTER_NOP:
6871                 if (!(pf->flags & I40E_FLAG_VXLAN))
6872                         ret = I40E_NOT_SUPPORTED;
6873                 break;
6874         case RTE_ETH_FILTER_ADD:
6875                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6876                 break;
6877         case RTE_ETH_FILTER_DELETE:
6878                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6879                 break;
6880         default:
6881                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6882                 ret = I40E_ERR_PARAM;
6883                 break;
6884         }
6885
6886         return ret;
6887 }
6888
6889 static int
6890 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6891 {
6892         int ret = 0;
6893         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6894
6895         /* RSS setup */
6896         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6897                 ret = i40e_pf_config_rss(pf);
6898         else
6899                 i40e_pf_disable_rss(pf);
6900
6901         return ret;
6902 }
6903
6904 /* Get the symmetric hash enable configurations per port */
6905 static void
6906 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6907 {
6908         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6909
6910         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6911 }
6912
6913 /* Set the symmetric hash enable configurations per port */
6914 static void
6915 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6916 {
6917         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6918
6919         if (enable > 0) {
6920                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6921                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6922                                                         "been enabled");
6923                         return;
6924                 }
6925                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6926         } else {
6927                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6928                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6929                                                         "been disabled");
6930                         return;
6931                 }
6932                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6933         }
6934         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6935         I40E_WRITE_FLUSH(hw);
6936 }
6937
6938 /*
6939  * Get global configurations of hash function type and symmetric hash enable
6940  * per flow type (pctype). Note that global configuration means it affects all
6941  * the ports on the same NIC.
6942  */
6943 static int
6944 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6945                                    struct rte_eth_hash_global_conf *g_cfg)
6946 {
6947         uint32_t reg, mask = I40E_FLOW_TYPES;
6948         uint16_t i;
6949         enum i40e_filter_pctype pctype;
6950
6951         memset(g_cfg, 0, sizeof(*g_cfg));
6952         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6953         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6954                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6955         else
6956                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6957         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6958                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6959
6960         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6961                 if (!(mask & (1UL << i)))
6962                         continue;
6963                 mask &= ~(1UL << i);
6964                 /* Bit set indicats the coresponding flow type is supported */
6965                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6966                 /* if flowtype is invalid, continue */
6967                 if (!I40E_VALID_FLOW(i))
6968                         continue;
6969                 pctype = i40e_flowtype_to_pctype(i);
6970                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6971                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6972                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6973         }
6974
6975         return 0;
6976 }
6977
6978 static int
6979 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6980 {
6981         uint32_t i;
6982         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6983
6984         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6985                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6986                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6987                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6988                                                 g_cfg->hash_func);
6989                 return -EINVAL;
6990         }
6991
6992         /*
6993          * As i40e supports less than 32 flow types, only first 32 bits need to
6994          * be checked.
6995          */
6996         mask0 = g_cfg->valid_bit_mask[0];
6997         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6998                 if (i == 0) {
6999                         /* Check if any unsupported flow type configured */
7000                         if ((mask0 | i40e_mask) ^ i40e_mask)
7001                                 goto mask_err;
7002                 } else {
7003                         if (g_cfg->valid_bit_mask[i])
7004                                 goto mask_err;
7005                 }
7006         }
7007
7008         return 0;
7009
7010 mask_err:
7011         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7012
7013         return -EINVAL;
7014 }
7015
7016 /*
7017  * Set global configurations of hash function type and symmetric hash enable
7018  * per flow type (pctype). Note any modifying global configuration will affect
7019  * all the ports on the same NIC.
7020  */
7021 static int
7022 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7023                                    struct rte_eth_hash_global_conf *g_cfg)
7024 {
7025         int ret;
7026         uint16_t i;
7027         uint32_t reg;
7028         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7029         enum i40e_filter_pctype pctype;
7030
7031         /* Check the input parameters */
7032         ret = i40e_hash_global_config_check(g_cfg);
7033         if (ret < 0)
7034                 return ret;
7035
7036         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7037                 if (!(mask0 & (1UL << i)))
7038                         continue;
7039                 mask0 &= ~(1UL << i);
7040                 /* if flowtype is invalid, continue */
7041                 if (!I40E_VALID_FLOW(i))
7042                         continue;
7043                 pctype = i40e_flowtype_to_pctype(i);
7044                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7045                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7046                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7047         }
7048
7049         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7050         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7051                 /* Toeplitz */
7052                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7053                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7054                                                                 "Toeplitz");
7055                         goto out;
7056                 }
7057                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7058         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7059                 /* Simple XOR */
7060                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7061                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7062                                                         "Simple XOR");
7063                         goto out;
7064                 }
7065                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7066         } else
7067                 /* Use the default, and keep it as it is */
7068                 goto out;
7069
7070         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7071
7072 out:
7073         I40E_WRITE_FLUSH(hw);
7074
7075         return 0;
7076 }
7077
7078 /**
7079  * Valid input sets for hash and flow director filters per PCTYPE
7080  */
7081 static uint64_t
7082 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7083                 enum rte_filter_type filter)
7084 {
7085         uint64_t valid;
7086
7087         static const uint64_t valid_hash_inset_table[] = {
7088                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7089                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7090                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7091                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7092                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7093                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7094                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7095                         I40E_INSET_FLEX_PAYLOAD,
7096                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7100                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7101                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7102                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7103                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7104                         I40E_INSET_FLEX_PAYLOAD,
7105 #ifdef X722_SUPPORT
7106                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7107                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7108                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7109                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7110                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7111                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7112                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7113                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7114                         I40E_INSET_FLEX_PAYLOAD,
7115                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7116                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7117                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7118                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7119                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7120                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7121                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7122                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7123                         I40E_INSET_FLEX_PAYLOAD,
7124 #endif
7125                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7129                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7130                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7131                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7132                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7133                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7134 #ifdef X722_SUPPORT
7135                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7136                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7137                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7138                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7139                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7140                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7141                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7142                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7143                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7144 #endif
7145                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7146                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7147                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7148                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7149                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7150                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7151                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7152                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7153                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7154                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7155                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7156                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7157                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7158                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7159                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7160                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7161                         I40E_INSET_FLEX_PAYLOAD,
7162                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7163                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7164                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7165                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7166                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7167                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7168                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7169                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7170                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7171                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7172                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7173                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7174                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7175                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7176                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7177                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7178 #ifdef X722_SUPPORT
7179                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7180                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7181                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7182                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7183                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7184                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7185                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7186                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7187                         I40E_INSET_FLEX_PAYLOAD,
7188                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7192                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7193                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7194                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7195                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7196                         I40E_INSET_FLEX_PAYLOAD,
7197 #endif
7198                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7199                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7200                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7201                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7202                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7203                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7204                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7205                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7206                         I40E_INSET_FLEX_PAYLOAD,
7207 #ifdef X722_SUPPORT
7208                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7209                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7210                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7211                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7212                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7213                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7214                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7215                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7216                         I40E_INSET_FLEX_PAYLOAD,
7217 #endif
7218                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7219                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7220                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7221                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7222                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7223                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7224                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7225                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7226                         I40E_INSET_FLEX_PAYLOAD,
7227                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7228                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7229                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7230                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7231                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7232                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7233                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7234                         I40E_INSET_FLEX_PAYLOAD,
7235                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7236                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7237                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7238                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7239                         I40E_INSET_FLEX_PAYLOAD,
7240         };
7241
7242         /**
7243          * Flow director supports only fields defined in
7244          * union rte_eth_fdir_flow.
7245          */
7246         static const uint64_t valid_fdir_inset_table[] = {
7247                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7248                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7249                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7250                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7251                 I40E_INSET_IPV4_TTL,
7252                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7253                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7254                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7255                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7256                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7257 #ifdef X722_SUPPORT
7258                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7259                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7260                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7261                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7262                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7263                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7264                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7265                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7266                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7267                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7268 #endif
7269                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7270                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7271                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7272                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7273                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7274 #ifdef X722_SUPPORT
7275                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7276                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7277                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7278                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7279                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7280 #endif
7281                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7283                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7284                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7286                 I40E_INSET_SCTP_VT,
7287                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7288                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7289                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7290                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7291                 I40E_INSET_IPV4_TTL,
7292                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7293                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7294                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7295                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7296                 I40E_INSET_IPV6_HOP_LIMIT,
7297                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7299                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7300                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7301                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7302 #ifdef X722_SUPPORT
7303                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7304                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7305                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7306                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7307                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7308                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7309                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7310                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7311                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7312                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7313 #endif
7314                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7315                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7316                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7317                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7318                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7319 #ifdef X722_SUPPORT
7320                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7321                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7322                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7323                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7324                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7325 #endif
7326                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7327                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7328                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7329                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7330                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7331                 I40E_INSET_SCTP_VT,
7332                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7333                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7334                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7335                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7336                 I40E_INSET_IPV6_HOP_LIMIT,
7337                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7338                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7339                 I40E_INSET_LAST_ETHER_TYPE,
7340         };
7341
7342         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7343                 return 0;
7344         if (filter == RTE_ETH_FILTER_HASH)
7345                 valid = valid_hash_inset_table[pctype];
7346         else
7347                 valid = valid_fdir_inset_table[pctype];
7348
7349         return valid;
7350 }
7351
7352 /**
7353  * Validate if the input set is allowed for a specific PCTYPE
7354  */
7355 static int
7356 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7357                 enum rte_filter_type filter, uint64_t inset)
7358 {
7359         uint64_t valid;
7360
7361         valid = i40e_get_valid_input_set(pctype, filter);
7362         if (inset & (~valid))
7363                 return -EINVAL;
7364
7365         return 0;
7366 }
7367
7368 /* default input set fields combination per pctype */
7369 static uint64_t
7370 i40e_get_default_input_set(uint16_t pctype)
7371 {
7372         static const uint64_t default_inset_table[] = {
7373                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7374                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7375                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7376                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7377                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7378 #ifdef X722_SUPPORT
7379                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7380                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7381                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7382                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7383                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7384                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7385 #endif
7386                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7387                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7388                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7389 #ifdef X722_SUPPORT
7390                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7391                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7392                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7393 #endif
7394                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7395                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7396                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7397                         I40E_INSET_SCTP_VT,
7398                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7399                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7400                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7401                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7402                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7403                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7404                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7405 #ifdef X722_SUPPORT
7406                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7407                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7408                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7409                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7410                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7411                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7412 #endif
7413                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7414                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7415                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7416 #ifdef X722_SUPPORT
7417                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7418                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7419                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7420 #endif
7421                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7422                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7423                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7424                         I40E_INSET_SCTP_VT,
7425                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7426                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7427                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7428                         I40E_INSET_LAST_ETHER_TYPE,
7429         };
7430
7431         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7432                 return 0;
7433
7434         return default_inset_table[pctype];
7435 }
7436
7437 /**
7438  * Parse the input set from index to logical bit masks
7439  */
7440 static int
7441 i40e_parse_input_set(uint64_t *inset,
7442                      enum i40e_filter_pctype pctype,
7443                      enum rte_eth_input_set_field *field,
7444                      uint16_t size)
7445 {
7446         uint16_t i, j;
7447         int ret = -EINVAL;
7448
7449         static const struct {
7450                 enum rte_eth_input_set_field field;
7451                 uint64_t inset;
7452         } inset_convert_table[] = {
7453                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7454                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7455                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7456                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7457                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7458                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7459                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7460                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7461                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7462                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7463                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7464                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7465                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7466                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7467                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7468                         I40E_INSET_IPV6_NEXT_HDR},
7469                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7470                         I40E_INSET_IPV6_HOP_LIMIT},
7471                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7472                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7473                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7474                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7475                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7476                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7477                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7478                         I40E_INSET_SCTP_VT},
7479                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7480                         I40E_INSET_TUNNEL_DMAC},
7481                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7482                         I40E_INSET_VLAN_TUNNEL},
7483                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7484                         I40E_INSET_TUNNEL_ID},
7485                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7486                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7487                         I40E_INSET_FLEX_PAYLOAD_W1},
7488                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7489                         I40E_INSET_FLEX_PAYLOAD_W2},
7490                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7491                         I40E_INSET_FLEX_PAYLOAD_W3},
7492                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7493                         I40E_INSET_FLEX_PAYLOAD_W4},
7494                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7495                         I40E_INSET_FLEX_PAYLOAD_W5},
7496                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7497                         I40E_INSET_FLEX_PAYLOAD_W6},
7498                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7499                         I40E_INSET_FLEX_PAYLOAD_W7},
7500                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7501                         I40E_INSET_FLEX_PAYLOAD_W8},
7502         };
7503
7504         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7505                 return ret;
7506
7507         /* Only one item allowed for default or all */
7508         if (size == 1) {
7509                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7510                         *inset = i40e_get_default_input_set(pctype);
7511                         return 0;
7512                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7513                         *inset = I40E_INSET_NONE;
7514                         return 0;
7515                 }
7516         }
7517
7518         for (i = 0, *inset = 0; i < size; i++) {
7519                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7520                         if (field[i] == inset_convert_table[j].field) {
7521                                 *inset |= inset_convert_table[j].inset;
7522                                 break;
7523                         }
7524                 }
7525
7526                 /* It contains unsupported input set, return immediately */
7527                 if (j == RTE_DIM(inset_convert_table))
7528                         return ret;
7529         }
7530
7531         return 0;
7532 }
7533
7534 /**
7535  * Translate the input set from bit masks to register aware bit masks
7536  * and vice versa
7537  */
7538 static uint64_t
7539 i40e_translate_input_set_reg(uint64_t input)
7540 {
7541         uint64_t val = 0;
7542         uint16_t i;
7543
7544         static const struct {
7545                 uint64_t inset;
7546                 uint64_t inset_reg;
7547         } inset_map[] = {
7548                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7549                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7550                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7551                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7552                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7553                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7554                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7555                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7556                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7557                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7558                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7559                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7560                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7561                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7562                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7563                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7564                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7565                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7566                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7567                 {I40E_INSET_TUNNEL_DMAC,
7568                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7569                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7570                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7571                 {I40E_INSET_TUNNEL_SRC_PORT,
7572                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7573                 {I40E_INSET_TUNNEL_DST_PORT,
7574                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7575                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7576                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7577                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7578                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7579                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7580                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7581                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7582                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7583                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7584         };
7585
7586         if (input == 0)
7587                 return val;
7588
7589         /* Translate input set to register aware inset */
7590         for (i = 0; i < RTE_DIM(inset_map); i++) {
7591                 if (input & inset_map[i].inset)
7592                         val |= inset_map[i].inset_reg;
7593         }
7594
7595         return val;
7596 }
7597
7598 static int
7599 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7600 {
7601         uint8_t i, idx = 0;
7602         uint64_t inset_need_mask = inset;
7603
7604         static const struct {
7605                 uint64_t inset;
7606                 uint32_t mask;
7607         } inset_mask_map[] = {
7608                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7609                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7610                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7611                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7612                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7613                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7614                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7615                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7616         };
7617
7618         if (!inset || !mask || !nb_elem)
7619                 return 0;
7620
7621         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7622                 /* Clear the inset bit, if no MASK is required,
7623                  * for example proto + ttl
7624                  */
7625                 if ((inset & inset_mask_map[i].inset) ==
7626                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7627                         inset_need_mask &= ~inset_mask_map[i].inset;
7628                 if (!inset_need_mask)
7629                         return 0;
7630         }
7631         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7632                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7633                     inset_mask_map[i].inset) {
7634                         if (idx >= nb_elem) {
7635                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7636                                 return -EINVAL;
7637                         }
7638                         mask[idx] = inset_mask_map[i].mask;
7639                         idx++;
7640                 }
7641         }
7642
7643         return idx;
7644 }
7645
7646 static void
7647 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7648 {
7649         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7650
7651         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7652         if (reg != val)
7653                 i40e_write_rx_ctl(hw, addr, val);
7654         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7655                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7656 }
7657
7658 static void
7659 i40e_filter_input_set_init(struct i40e_pf *pf)
7660 {
7661         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7662         enum i40e_filter_pctype pctype;
7663         uint64_t input_set, inset_reg;
7664         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7665         int num, i;
7666
7667         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7668              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7669                 if (!I40E_VALID_PCTYPE(pctype))
7670                         continue;
7671                 input_set = i40e_get_default_input_set(pctype);
7672
7673                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7674                                                    I40E_INSET_MASK_NUM_REG);
7675                 if (num < 0)
7676                         return;
7677                 inset_reg = i40e_translate_input_set_reg(input_set);
7678
7679                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7680                                       (uint32_t)(inset_reg & UINT32_MAX));
7681                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7682                                      (uint32_t)((inset_reg >>
7683                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7684                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7685                                       (uint32_t)(inset_reg & UINT32_MAX));
7686                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7687                                      (uint32_t)((inset_reg >>
7688                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7689
7690                 for (i = 0; i < num; i++) {
7691                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7692                                              mask_reg[i]);
7693                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7694                                              mask_reg[i]);
7695                 }
7696                 /*clear unused mask registers of the pctype */
7697                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7698                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7699                                              0);
7700                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7701                                              0);
7702                 }
7703                 I40E_WRITE_FLUSH(hw);
7704
7705                 /* store the default input set */
7706                 pf->hash_input_set[pctype] = input_set;
7707                 pf->fdir.input_set[pctype] = input_set;
7708         }
7709 }
7710
7711 int
7712 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7713                          struct rte_eth_input_set_conf *conf)
7714 {
7715         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7716         enum i40e_filter_pctype pctype;
7717         uint64_t input_set, inset_reg = 0;
7718         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7719         int ret, i, num;
7720
7721         if (!conf) {
7722                 PMD_DRV_LOG(ERR, "Invalid pointer");
7723                 return -EFAULT;
7724         }
7725         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7726             conf->op != RTE_ETH_INPUT_SET_ADD) {
7727                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7728                 return -EINVAL;
7729         }
7730
7731         if (!I40E_VALID_FLOW(conf->flow_type)) {
7732                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7733                 return -EINVAL;
7734         }
7735
7736 #ifdef X722_SUPPORT
7737         /* get translated pctype value in fd pctype register */
7738         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7739                 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7740                 conf->flow_type)));
7741 #else
7742         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7743 #endif
7744
7745         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7746                                    conf->inset_size);
7747         if (ret) {
7748                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7749                 return -EINVAL;
7750         }
7751         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7752                                     input_set) != 0) {
7753                 PMD_DRV_LOG(ERR, "Invalid input set");
7754                 return -EINVAL;
7755         }
7756         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7757                 /* get inset value in register */
7758                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7759                 inset_reg <<= I40E_32_BIT_WIDTH;
7760                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7761                 input_set |= pf->hash_input_set[pctype];
7762         }
7763         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7764                                            I40E_INSET_MASK_NUM_REG);
7765         if (num < 0)
7766                 return -EINVAL;
7767
7768         inset_reg |= i40e_translate_input_set_reg(input_set);
7769
7770         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7771                               (uint32_t)(inset_reg & UINT32_MAX));
7772         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7773                              (uint32_t)((inset_reg >>
7774                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7775
7776         for (i = 0; i < num; i++)
7777                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7778                                      mask_reg[i]);
7779         /*clear unused mask registers of the pctype */
7780         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7781                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7782                                      0);
7783         I40E_WRITE_FLUSH(hw);
7784
7785         pf->hash_input_set[pctype] = input_set;
7786         return 0;
7787 }
7788
7789 int
7790 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7791                          struct rte_eth_input_set_conf *conf)
7792 {
7793         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7794         enum i40e_filter_pctype pctype;
7795         uint64_t input_set, inset_reg = 0;
7796         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7797         int ret, i, num;
7798
7799         if (!hw || !conf) {
7800                 PMD_DRV_LOG(ERR, "Invalid pointer");
7801                 return -EFAULT;
7802         }
7803         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7804             conf->op != RTE_ETH_INPUT_SET_ADD) {
7805                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7806                 return -EINVAL;
7807         }
7808
7809         if (!I40E_VALID_FLOW(conf->flow_type)) {
7810                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7811                 return -EINVAL;
7812         }
7813
7814         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7815
7816         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7817                                    conf->inset_size);
7818         if (ret) {
7819                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7820                 return -EINVAL;
7821         }
7822         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7823                                     input_set) != 0) {
7824                 PMD_DRV_LOG(ERR, "Invalid input set");
7825                 return -EINVAL;
7826         }
7827
7828         /* get inset value in register */
7829         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7830         inset_reg <<= I40E_32_BIT_WIDTH;
7831         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7832
7833         /* Can not change the inset reg for flex payload for fdir,
7834          * it is done by writing I40E_PRTQF_FD_FLXINSET
7835          * in i40e_set_flex_mask_on_pctype.
7836          */
7837         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7838                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7839         else
7840                 input_set |= pf->fdir.input_set[pctype];
7841         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7842                                            I40E_INSET_MASK_NUM_REG);
7843         if (num < 0)
7844                 return -EINVAL;
7845
7846         inset_reg |= i40e_translate_input_set_reg(input_set);
7847
7848         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7849                               (uint32_t)(inset_reg & UINT32_MAX));
7850         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7851                              (uint32_t)((inset_reg >>
7852                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7853
7854         for (i = 0; i < num; i++)
7855                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7856                                      mask_reg[i]);
7857         /*clear unused mask registers of the pctype */
7858         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7859                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7860                                      0);
7861         I40E_WRITE_FLUSH(hw);
7862
7863         pf->fdir.input_set[pctype] = input_set;
7864         return 0;
7865 }
7866
7867 static int
7868 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7869 {
7870         int ret = 0;
7871
7872         if (!hw || !info) {
7873                 PMD_DRV_LOG(ERR, "Invalid pointer");
7874                 return -EFAULT;
7875         }
7876
7877         switch (info->info_type) {
7878         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7879                 i40e_get_symmetric_hash_enable_per_port(hw,
7880                                         &(info->info.enable));
7881                 break;
7882         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7883                 ret = i40e_get_hash_filter_global_config(hw,
7884                                 &(info->info.global_conf));
7885                 break;
7886         default:
7887                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7888                                                         info->info_type);
7889                 ret = -EINVAL;
7890                 break;
7891         }
7892
7893         return ret;
7894 }
7895
7896 static int
7897 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7898 {
7899         int ret = 0;
7900
7901         if (!hw || !info) {
7902                 PMD_DRV_LOG(ERR, "Invalid pointer");
7903                 return -EFAULT;
7904         }
7905
7906         switch (info->info_type) {
7907         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7908                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7909                 break;
7910         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7911                 ret = i40e_set_hash_filter_global_config(hw,
7912                                 &(info->info.global_conf));
7913                 break;
7914         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7915                 ret = i40e_hash_filter_inset_select(hw,
7916                                                &(info->info.input_set_conf));
7917                 break;
7918
7919         default:
7920                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7921                                                         info->info_type);
7922                 ret = -EINVAL;
7923                 break;
7924         }
7925
7926         return ret;
7927 }
7928
7929 /* Operations for hash function */
7930 static int
7931 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7932                       enum rte_filter_op filter_op,
7933                       void *arg)
7934 {
7935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7936         int ret = 0;
7937
7938         switch (filter_op) {
7939         case RTE_ETH_FILTER_NOP:
7940                 break;
7941         case RTE_ETH_FILTER_GET:
7942                 ret = i40e_hash_filter_get(hw,
7943                         (struct rte_eth_hash_filter_info *)arg);
7944                 break;
7945         case RTE_ETH_FILTER_SET:
7946                 ret = i40e_hash_filter_set(hw,
7947                         (struct rte_eth_hash_filter_info *)arg);
7948                 break;
7949         default:
7950                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7951                                                                 filter_op);
7952                 ret = -ENOTSUP;
7953                 break;
7954         }
7955
7956         return ret;
7957 }
7958
7959 /*
7960  * Configure ethertype filter, which can director packet by filtering
7961  * with mac address and ether_type or only ether_type
7962  */
7963 static int
7964 i40e_ethertype_filter_set(struct i40e_pf *pf,
7965                         struct rte_eth_ethertype_filter *filter,
7966                         bool add)
7967 {
7968         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7969         struct i40e_control_filter_stats stats;
7970         uint16_t flags = 0;
7971         int ret;
7972
7973         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7974                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7975                 return -EINVAL;
7976         }
7977         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7978                 filter->ether_type == ETHER_TYPE_IPv6) {
7979                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7980                         " control packet filter.", filter->ether_type);
7981                 return -EINVAL;
7982         }
7983         if (filter->ether_type == ETHER_TYPE_VLAN)
7984                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7985                         " not supported.");
7986
7987         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7988                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7989         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7990                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7991         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7992
7993         memset(&stats, 0, sizeof(stats));
7994         ret = i40e_aq_add_rem_control_packet_filter(hw,
7995                         filter->mac_addr.addr_bytes,
7996                         filter->ether_type, flags,
7997                         pf->main_vsi->seid,
7998                         filter->queue, add, &stats, NULL);
7999
8000         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8001                          " mac_etype_used = %u, etype_used = %u,"
8002                          " mac_etype_free = %u, etype_free = %u\n",
8003                          ret, stats.mac_etype_used, stats.etype_used,
8004                          stats.mac_etype_free, stats.etype_free);
8005         if (ret < 0)
8006                 return -ENOSYS;
8007         return 0;
8008 }
8009
8010 /*
8011  * Handle operations for ethertype filter.
8012  */
8013 static int
8014 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8015                                 enum rte_filter_op filter_op,
8016                                 void *arg)
8017 {
8018         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8019         int ret = 0;
8020
8021         if (filter_op == RTE_ETH_FILTER_NOP)
8022                 return ret;
8023
8024         if (arg == NULL) {
8025                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8026                             filter_op);
8027                 return -EINVAL;
8028         }
8029
8030         switch (filter_op) {
8031         case RTE_ETH_FILTER_ADD:
8032                 ret = i40e_ethertype_filter_set(pf,
8033                         (struct rte_eth_ethertype_filter *)arg,
8034                         TRUE);
8035                 break;
8036         case RTE_ETH_FILTER_DELETE:
8037                 ret = i40e_ethertype_filter_set(pf,
8038                         (struct rte_eth_ethertype_filter *)arg,
8039                         FALSE);
8040                 break;
8041         default:
8042                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8043                 ret = -ENOSYS;
8044                 break;
8045         }
8046         return ret;
8047 }
8048
8049 static int
8050 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8051                      enum rte_filter_type filter_type,
8052                      enum rte_filter_op filter_op,
8053                      void *arg)
8054 {
8055         int ret = 0;
8056
8057         if (dev == NULL)
8058                 return -EINVAL;
8059
8060         switch (filter_type) {
8061         case RTE_ETH_FILTER_NONE:
8062                 /* For global configuration */
8063                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8064                 break;
8065         case RTE_ETH_FILTER_HASH:
8066                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8067                 break;
8068         case RTE_ETH_FILTER_MACVLAN:
8069                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8070                 break;
8071         case RTE_ETH_FILTER_ETHERTYPE:
8072                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8073                 break;
8074         case RTE_ETH_FILTER_TUNNEL:
8075                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8076                 break;
8077         case RTE_ETH_FILTER_FDIR:
8078                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8079                 break;
8080         default:
8081                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8082                                                         filter_type);
8083                 ret = -EINVAL;
8084                 break;
8085         }
8086
8087         return ret;
8088 }
8089
8090 /*
8091  * Check and enable Extended Tag.
8092  * Enabling Extended Tag is important for 40G performance.
8093  */
8094 static void
8095 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8096 {
8097         uint32_t buf = 0;
8098         int ret;
8099
8100         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8101                                       PCI_DEV_CAP_REG);
8102         if (ret < 0) {
8103                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8104                             PCI_DEV_CAP_REG);
8105                 return;
8106         }
8107         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8108                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8109                 return;
8110         }
8111
8112         buf = 0;
8113         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8114                                       PCI_DEV_CTRL_REG);
8115         if (ret < 0) {
8116                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8117                             PCI_DEV_CTRL_REG);
8118                 return;
8119         }
8120         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8121                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8122                 return;
8123         }
8124         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8125         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8126                                        PCI_DEV_CTRL_REG);
8127         if (ret < 0) {
8128                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8129                             PCI_DEV_CTRL_REG);
8130                 return;
8131         }
8132 }
8133
8134 /*
8135  * As some registers wouldn't be reset unless a global hardware reset,
8136  * hardware initialization is needed to put those registers into an
8137  * expected initial state.
8138  */
8139 static void
8140 i40e_hw_init(struct rte_eth_dev *dev)
8141 {
8142         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8143
8144         i40e_enable_extended_tag(dev);
8145
8146         /* clear the PF Queue Filter control register */
8147         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8148
8149         /* Disable symmetric hash per port */
8150         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8151 }
8152
8153 enum i40e_filter_pctype
8154 i40e_flowtype_to_pctype(uint16_t flow_type)
8155 {
8156         static const enum i40e_filter_pctype pctype_table[] = {
8157                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8158                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8159                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8160                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8161                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8162                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8163                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8164                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8165                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8166                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8167                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8168                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8169                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8170                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8171                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8172                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8173                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8174                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8175                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8176         };
8177
8178         return pctype_table[flow_type];
8179 }
8180
8181 uint16_t
8182 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8183 {
8184         static const uint16_t flowtype_table[] = {
8185                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8186                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8187                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8188 #ifdef X722_SUPPORT
8189                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8190                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8191                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8192                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8193 #endif
8194                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8195                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8196 #ifdef X722_SUPPORT
8197                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8198                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8199 #endif
8200                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8201                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8202                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8203                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8204                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8205                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8206                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8207 #ifdef X722_SUPPORT
8208                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8209                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8210                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8211                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8212 #endif
8213                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8214                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8215 #ifdef X722_SUPPORT
8216                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8217                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8218 #endif
8219                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8220                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8221                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8222                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8223                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8224         };
8225
8226         return flowtype_table[pctype];
8227 }
8228
8229 /*
8230  * On X710, performance number is far from the expectation on recent firmware
8231  * versions; on XL710, performance number is also far from the expectation on
8232  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8233  * mode is enabled and port MAC address is equal to the packet destination MAC
8234  * address. The fix for this issue may not be integrated in the following
8235  * firmware version. So the workaround in software driver is needed. It needs
8236  * to modify the initial values of 3 internal only registers for both X710 and
8237  * XL710. Note that the values for X710 or XL710 could be different, and the
8238  * workaround can be removed when it is fixed in firmware in the future.
8239  */
8240
8241 /* For both X710 and XL710 */
8242 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8243 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8244
8245 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8246 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8247
8248 /* For X710 */
8249 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8250 /* For XL710 */
8251 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8252 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8253
8254 static void
8255 i40e_configure_registers(struct i40e_hw *hw)
8256 {
8257         static struct {
8258                 uint32_t addr;
8259                 uint64_t val;
8260         } reg_table[] = {
8261                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8262                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8263                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8264         };
8265         uint64_t reg;
8266         uint32_t i;
8267         int ret;
8268
8269         for (i = 0; i < RTE_DIM(reg_table); i++) {
8270                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8271                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8272                                 reg_table[i].val =
8273                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8274                         else /* For X710 */
8275                                 reg_table[i].val =
8276                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8277                 }
8278
8279                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8280                                                         &reg, NULL);
8281                 if (ret < 0) {
8282                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8283                                                         reg_table[i].addr);
8284                         break;
8285                 }
8286                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8287                                                 reg_table[i].addr, reg);
8288                 if (reg == reg_table[i].val)
8289                         continue;
8290
8291                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8292                                                 reg_table[i].val, NULL);
8293                 if (ret < 0) {
8294                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8295                                 "address of 0x%"PRIx32, reg_table[i].val,
8296                                                         reg_table[i].addr);
8297                         break;
8298                 }
8299                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8300                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8301         }
8302 }
8303
8304 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8305 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8306 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8307 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8308 static int
8309 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8310 {
8311         uint32_t reg;
8312         int ret;
8313
8314         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8315                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8316                 return -EINVAL;
8317         }
8318
8319         /* Configure for double VLAN RX stripping */
8320         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8321         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8322                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8323                 ret = i40e_aq_debug_write_register(hw,
8324                                                    I40E_VSI_TSR(vsi->vsi_id),
8325                                                    reg, NULL);
8326                 if (ret < 0) {
8327                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8328                                     vsi->vsi_id);
8329                         return I40E_ERR_CONFIG;
8330                 }
8331         }
8332
8333         /* Configure for double VLAN TX insertion */
8334         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8335         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8336                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8337                 ret = i40e_aq_debug_write_register(hw,
8338                                                    I40E_VSI_L2TAGSTXVALID(
8339                                                    vsi->vsi_id), reg, NULL);
8340                 if (ret < 0) {
8341                         PMD_DRV_LOG(ERR, "Failed to update "
8342                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8343                         return I40E_ERR_CONFIG;
8344                 }
8345         }
8346
8347         return 0;
8348 }
8349
8350 /**
8351  * i40e_aq_add_mirror_rule
8352  * @hw: pointer to the hardware structure
8353  * @seid: VEB seid to add mirror rule to
8354  * @dst_id: destination vsi seid
8355  * @entries: Buffer which contains the entities to be mirrored
8356  * @count: number of entities contained in the buffer
8357  * @rule_id:the rule_id of the rule to be added
8358  *
8359  * Add a mirror rule for a given veb.
8360  *
8361  **/
8362 static enum i40e_status_code
8363 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8364                         uint16_t seid, uint16_t dst_id,
8365                         uint16_t rule_type, uint16_t *entries,
8366                         uint16_t count, uint16_t *rule_id)
8367 {
8368         struct i40e_aq_desc desc;
8369         struct i40e_aqc_add_delete_mirror_rule cmd;
8370         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8371                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8372                 &desc.params.raw;
8373         uint16_t buff_len;
8374         enum i40e_status_code status;
8375
8376         i40e_fill_default_direct_cmd_desc(&desc,
8377                                           i40e_aqc_opc_add_mirror_rule);
8378         memset(&cmd, 0, sizeof(cmd));
8379
8380         buff_len = sizeof(uint16_t) * count;
8381         desc.datalen = rte_cpu_to_le_16(buff_len);
8382         if (buff_len > 0)
8383                 desc.flags |= rte_cpu_to_le_16(
8384                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8385         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8386                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8387         cmd.num_entries = rte_cpu_to_le_16(count);
8388         cmd.seid = rte_cpu_to_le_16(seid);
8389         cmd.destination = rte_cpu_to_le_16(dst_id);
8390
8391         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8392         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8393         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8394                          "rule_id = %u"
8395                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8396                          hw->aq.asq_last_status, resp->rule_id,
8397                          resp->mirror_rules_used, resp->mirror_rules_free);
8398         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8399
8400         return status;
8401 }
8402
8403 /**
8404  * i40e_aq_del_mirror_rule
8405  * @hw: pointer to the hardware structure
8406  * @seid: VEB seid to add mirror rule to
8407  * @entries: Buffer which contains the entities to be mirrored
8408  * @count: number of entities contained in the buffer
8409  * @rule_id:the rule_id of the rule to be delete
8410  *
8411  * Delete a mirror rule for a given veb.
8412  *
8413  **/
8414 static enum i40e_status_code
8415 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8416                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8417                 uint16_t count, uint16_t rule_id)
8418 {
8419         struct i40e_aq_desc desc;
8420         struct i40e_aqc_add_delete_mirror_rule cmd;
8421         uint16_t buff_len = 0;
8422         enum i40e_status_code status;
8423         void *buff = NULL;
8424
8425         i40e_fill_default_direct_cmd_desc(&desc,
8426                                           i40e_aqc_opc_delete_mirror_rule);
8427         memset(&cmd, 0, sizeof(cmd));
8428         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8429                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8430                                                           I40E_AQ_FLAG_RD));
8431                 cmd.num_entries = count;
8432                 buff_len = sizeof(uint16_t) * count;
8433                 desc.datalen = rte_cpu_to_le_16(buff_len);
8434                 buff = (void *)entries;
8435         } else
8436                 /* rule id is filled in destination field for deleting mirror rule */
8437                 cmd.destination = rte_cpu_to_le_16(rule_id);
8438
8439         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8440                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8441         cmd.seid = rte_cpu_to_le_16(seid);
8442
8443         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8444         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8445
8446         return status;
8447 }
8448
8449 /**
8450  * i40e_mirror_rule_set
8451  * @dev: pointer to the hardware structure
8452  * @mirror_conf: mirror rule info
8453  * @sw_id: mirror rule's sw_id
8454  * @on: enable/disable
8455  *
8456  * set a mirror rule.
8457  *
8458  **/
8459 static int
8460 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8461                         struct rte_eth_mirror_conf *mirror_conf,
8462                         uint8_t sw_id, uint8_t on)
8463 {
8464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8466         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8467         struct i40e_mirror_rule *parent = NULL;
8468         uint16_t seid, dst_seid, rule_id;
8469         uint16_t i, j = 0;
8470         int ret;
8471
8472         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8473
8474         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8475                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8476                         " without veb or vfs.");
8477                 return -ENOSYS;
8478         }
8479         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8480                 PMD_DRV_LOG(ERR, "mirror table is full.");
8481                 return -ENOSPC;
8482         }
8483         if (mirror_conf->dst_pool > pf->vf_num) {
8484                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8485                                  mirror_conf->dst_pool);
8486                 return -EINVAL;
8487         }
8488
8489         seid = pf->main_vsi->veb->seid;
8490
8491         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8492                 if (sw_id <= it->index) {
8493                         mirr_rule = it;
8494                         break;
8495                 }
8496                 parent = it;
8497         }
8498         if (mirr_rule && sw_id == mirr_rule->index) {
8499                 if (on) {
8500                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8501                         return -EEXIST;
8502                 } else {
8503                         ret = i40e_aq_del_mirror_rule(hw, seid,
8504                                         mirr_rule->rule_type,
8505                                         mirr_rule->entries,
8506                                         mirr_rule->num_entries, mirr_rule->id);
8507                         if (ret < 0) {
8508                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8509                                                    " ret = %d, aq_err = %d.",
8510                                                    ret, hw->aq.asq_last_status);
8511                                 return -ENOSYS;
8512                         }
8513                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8514                         rte_free(mirr_rule);
8515                         pf->nb_mirror_rule--;
8516                         return 0;
8517                 }
8518         } else if (!on) {
8519                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8520                 return -ENOENT;
8521         }
8522
8523         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8524                                 sizeof(struct i40e_mirror_rule) , 0);
8525         if (!mirr_rule) {
8526                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8527                 return I40E_ERR_NO_MEMORY;
8528         }
8529         switch (mirror_conf->rule_type) {
8530         case ETH_MIRROR_VLAN:
8531                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8532                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8533                                 mirr_rule->entries[j] =
8534                                         mirror_conf->vlan.vlan_id[i];
8535                                 j++;
8536                         }
8537                 }
8538                 if (j == 0) {
8539                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8540                         rte_free(mirr_rule);
8541                         return -EINVAL;
8542                 }
8543                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8544                 break;
8545         case ETH_MIRROR_VIRTUAL_POOL_UP:
8546         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8547                 /* check if the specified pool bit is out of range */
8548                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8549                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8550                         rte_free(mirr_rule);
8551                         return -EINVAL;
8552                 }
8553                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8554                         if (mirror_conf->pool_mask & (1ULL << i)) {
8555                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8556                                 j++;
8557                         }
8558                 }
8559                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8560                         /* add pf vsi to entries */
8561                         mirr_rule->entries[j] = pf->main_vsi_seid;
8562                         j++;
8563                 }
8564                 if (j == 0) {
8565                         PMD_DRV_LOG(ERR, "pool is not specified.");
8566                         rte_free(mirr_rule);
8567                         return -EINVAL;
8568                 }
8569                 /* egress and ingress in aq commands means from switch but not port */
8570                 mirr_rule->rule_type =
8571                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8572                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8573                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8574                 break;
8575         case ETH_MIRROR_UPLINK_PORT:
8576                 /* egress and ingress in aq commands means from switch but not port*/
8577                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8578                 break;
8579         case ETH_MIRROR_DOWNLINK_PORT:
8580                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8581                 break;
8582         default:
8583                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8584                         mirror_conf->rule_type);
8585                 rte_free(mirr_rule);
8586                 return -EINVAL;
8587         }
8588
8589         /* If the dst_pool is equal to vf_num, consider it as PF */
8590         if (mirror_conf->dst_pool == pf->vf_num)
8591                 dst_seid = pf->main_vsi_seid;
8592         else
8593                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8594
8595         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8596                                       mirr_rule->rule_type, mirr_rule->entries,
8597                                       j, &rule_id);
8598         if (ret < 0) {
8599                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8600                                    " ret = %d, aq_err = %d.",
8601                                    ret, hw->aq.asq_last_status);
8602                 rte_free(mirr_rule);
8603                 return -ENOSYS;
8604         }
8605
8606         mirr_rule->index = sw_id;
8607         mirr_rule->num_entries = j;
8608         mirr_rule->id = rule_id;
8609         mirr_rule->dst_vsi_seid = dst_seid;
8610
8611         if (parent)
8612                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8613         else
8614                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8615
8616         pf->nb_mirror_rule++;
8617         return 0;
8618 }
8619
8620 /**
8621  * i40e_mirror_rule_reset
8622  * @dev: pointer to the device
8623  * @sw_id: mirror rule's sw_id
8624  *
8625  * reset a mirror rule.
8626  *
8627  **/
8628 static int
8629 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8630 {
8631         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8633         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8634         uint16_t seid;
8635         int ret;
8636
8637         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8638
8639         seid = pf->main_vsi->veb->seid;
8640
8641         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8642                 if (sw_id == it->index) {
8643                         mirr_rule = it;
8644                         break;
8645                 }
8646         }
8647         if (mirr_rule) {
8648                 ret = i40e_aq_del_mirror_rule(hw, seid,
8649                                 mirr_rule->rule_type,
8650                                 mirr_rule->entries,
8651                                 mirr_rule->num_entries, mirr_rule->id);
8652                 if (ret < 0) {
8653                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8654                                            " status = %d, aq_err = %d.",
8655                                            ret, hw->aq.asq_last_status);
8656                         return -ENOSYS;
8657                 }
8658                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8659                 rte_free(mirr_rule);
8660                 pf->nb_mirror_rule--;
8661         } else {
8662                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8663                 return -ENOENT;
8664         }
8665         return 0;
8666 }
8667
8668 static uint64_t
8669 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8670 {
8671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8672         uint64_t systim_cycles;
8673
8674         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8675         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8676                         << 32;
8677
8678         return systim_cycles;
8679 }
8680
8681 static uint64_t
8682 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8683 {
8684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8685         uint64_t rx_tstamp;
8686
8687         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8688         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8689                         << 32;
8690
8691         return rx_tstamp;
8692 }
8693
8694 static uint64_t
8695 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8696 {
8697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8698         uint64_t tx_tstamp;
8699
8700         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8701         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8702                         << 32;
8703
8704         return tx_tstamp;
8705 }
8706
8707 static void
8708 i40e_start_timecounters(struct rte_eth_dev *dev)
8709 {
8710         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8711         struct i40e_adapter *adapter =
8712                         (struct i40e_adapter *)dev->data->dev_private;
8713         struct rte_eth_link link;
8714         uint32_t tsync_inc_l;
8715         uint32_t tsync_inc_h;
8716
8717         /* Get current link speed. */
8718         memset(&link, 0, sizeof(link));
8719         i40e_dev_link_update(dev, 1);
8720         rte_i40e_dev_atomic_read_link_status(dev, &link);
8721
8722         switch (link.link_speed) {
8723         case ETH_SPEED_NUM_40G:
8724                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8725                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8726                 break;
8727         case ETH_SPEED_NUM_10G:
8728                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8729                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8730                 break;
8731         case ETH_SPEED_NUM_1G:
8732                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8733                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8734                 break;
8735         default:
8736                 tsync_inc_l = 0x0;
8737                 tsync_inc_h = 0x0;
8738         }
8739
8740         /* Set the timesync increment value. */
8741         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8742         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8743
8744         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8745         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8746         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8747
8748         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8749         adapter->systime_tc.cc_shift = 0;
8750         adapter->systime_tc.nsec_mask = 0;
8751
8752         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8753         adapter->rx_tstamp_tc.cc_shift = 0;
8754         adapter->rx_tstamp_tc.nsec_mask = 0;
8755
8756         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8757         adapter->tx_tstamp_tc.cc_shift = 0;
8758         adapter->tx_tstamp_tc.nsec_mask = 0;
8759 }
8760
8761 static int
8762 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8763 {
8764         struct i40e_adapter *adapter =
8765                         (struct i40e_adapter *)dev->data->dev_private;
8766
8767         adapter->systime_tc.nsec += delta;
8768         adapter->rx_tstamp_tc.nsec += delta;
8769         adapter->tx_tstamp_tc.nsec += delta;
8770
8771         return 0;
8772 }
8773
8774 static int
8775 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8776 {
8777         uint64_t ns;
8778         struct i40e_adapter *adapter =
8779                         (struct i40e_adapter *)dev->data->dev_private;
8780
8781         ns = rte_timespec_to_ns(ts);
8782
8783         /* Set the timecounters to a new value. */
8784         adapter->systime_tc.nsec = ns;
8785         adapter->rx_tstamp_tc.nsec = ns;
8786         adapter->tx_tstamp_tc.nsec = ns;
8787
8788         return 0;
8789 }
8790
8791 static int
8792 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8793 {
8794         uint64_t ns, systime_cycles;
8795         struct i40e_adapter *adapter =
8796                         (struct i40e_adapter *)dev->data->dev_private;
8797
8798         systime_cycles = i40e_read_systime_cyclecounter(dev);
8799         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8800         *ts = rte_ns_to_timespec(ns);
8801
8802         return 0;
8803 }
8804
8805 static int
8806 i40e_timesync_enable(struct rte_eth_dev *dev)
8807 {
8808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8809         uint32_t tsync_ctl_l;
8810         uint32_t tsync_ctl_h;
8811
8812         /* Stop the timesync system time. */
8813         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8814         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8815         /* Reset the timesync system time value. */
8816         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8817         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8818
8819         i40e_start_timecounters(dev);
8820
8821         /* Clear timesync registers. */
8822         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8823         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8824         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8825         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8826         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8827         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8828
8829         /* Enable timestamping of PTP packets. */
8830         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8831         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8832
8833         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8834         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8835         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8836
8837         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8838         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8839
8840         return 0;
8841 }
8842
8843 static int
8844 i40e_timesync_disable(struct rte_eth_dev *dev)
8845 {
8846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8847         uint32_t tsync_ctl_l;
8848         uint32_t tsync_ctl_h;
8849
8850         /* Disable timestamping of transmitted PTP packets. */
8851         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8852         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8853
8854         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8855         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8856
8857         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8858         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8859
8860         /* Reset the timesync increment value. */
8861         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8862         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8863
8864         return 0;
8865 }
8866
8867 static int
8868 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8869                                 struct timespec *timestamp, uint32_t flags)
8870 {
8871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8872         struct i40e_adapter *adapter =
8873                 (struct i40e_adapter *)dev->data->dev_private;
8874
8875         uint32_t sync_status;
8876         uint32_t index = flags & 0x03;
8877         uint64_t rx_tstamp_cycles;
8878         uint64_t ns;
8879
8880         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8881         if ((sync_status & (1 << index)) == 0)
8882                 return -EINVAL;
8883
8884         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8885         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8886         *timestamp = rte_ns_to_timespec(ns);
8887
8888         return 0;
8889 }
8890
8891 static int
8892 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8893                                 struct timespec *timestamp)
8894 {
8895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8896         struct i40e_adapter *adapter =
8897                 (struct i40e_adapter *)dev->data->dev_private;
8898
8899         uint32_t sync_status;
8900         uint64_t tx_tstamp_cycles;
8901         uint64_t ns;
8902
8903         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8904         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8905                 return -EINVAL;
8906
8907         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8908         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8909         *timestamp = rte_ns_to_timespec(ns);
8910
8911         return 0;
8912 }
8913
8914 /*
8915  * i40e_parse_dcb_configure - parse dcb configure from user
8916  * @dev: the device being configured
8917  * @dcb_cfg: pointer of the result of parse
8918  * @*tc_map: bit map of enabled traffic classes
8919  *
8920  * Returns 0 on success, negative value on failure
8921  */
8922 static int
8923 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8924                          struct i40e_dcbx_config *dcb_cfg,
8925                          uint8_t *tc_map)
8926 {
8927         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8928         uint8_t i, tc_bw, bw_lf;
8929
8930         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8931
8932         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8933         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8934                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8935                 return -EINVAL;
8936         }
8937
8938         /* assume each tc has the same bw */
8939         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8940         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8941                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8942         /* to ensure the sum of tcbw is equal to 100 */
8943         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8944         for (i = 0; i < bw_lf; i++)
8945                 dcb_cfg->etscfg.tcbwtable[i]++;
8946
8947         /* assume each tc has the same Transmission Selection Algorithm */
8948         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8949                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8950
8951         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8952                 dcb_cfg->etscfg.prioritytable[i] =
8953                                 dcb_rx_conf->dcb_tc[i];
8954
8955         /* FW needs one App to configure HW */
8956         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8957         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8958         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8959         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8960
8961         if (dcb_rx_conf->nb_tcs == 0)
8962                 *tc_map = 1; /* tc0 only */
8963         else
8964                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8965
8966         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8967                 dcb_cfg->pfc.willing = 0;
8968                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8969                 dcb_cfg->pfc.pfcenable = *tc_map;
8970         }
8971         return 0;
8972 }
8973
8974
8975 static enum i40e_status_code
8976 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8977                               struct i40e_aqc_vsi_properties_data *info,
8978                               uint8_t enabled_tcmap)
8979 {
8980         enum i40e_status_code ret;
8981         int i, total_tc = 0;
8982         uint16_t qpnum_per_tc, bsf, qp_idx;
8983         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8984         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8985         uint16_t used_queues;
8986
8987         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8988         if (ret != I40E_SUCCESS)
8989                 return ret;
8990
8991         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8992                 if (enabled_tcmap & (1 << i))
8993                         total_tc++;
8994         }
8995         if (total_tc == 0)
8996                 total_tc = 1;
8997         vsi->enabled_tc = enabled_tcmap;
8998
8999         /* different VSI has different queues assigned */
9000         if (vsi->type == I40E_VSI_MAIN)
9001                 used_queues = dev_data->nb_rx_queues -
9002                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9003         else if (vsi->type == I40E_VSI_VMDQ2)
9004                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9005         else {
9006                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9007                 return I40E_ERR_NO_AVAILABLE_VSI;
9008         }
9009
9010         qpnum_per_tc = used_queues / total_tc;
9011         /* Number of queues per enabled TC */
9012         if (qpnum_per_tc == 0) {
9013                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9014                 return I40E_ERR_INVALID_QP_ID;
9015         }
9016         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9017                                 I40E_MAX_Q_PER_TC);
9018         bsf = rte_bsf32(qpnum_per_tc);
9019
9020         /**
9021          * Configure TC and queue mapping parameters, for enabled TC,
9022          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9023          * default queue will serve it.
9024          */
9025         qp_idx = 0;
9026         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9027                 if (vsi->enabled_tc & (1 << i)) {
9028                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9029                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9030                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9031                         qp_idx += qpnum_per_tc;
9032                 } else
9033                         info->tc_mapping[i] = 0;
9034         }
9035
9036         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9037         if (vsi->type == I40E_VSI_SRIOV) {
9038                 info->mapping_flags |=
9039                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9040                 for (i = 0; i < vsi->nb_qps; i++)
9041                         info->queue_mapping[i] =
9042                                 rte_cpu_to_le_16(vsi->base_queue + i);
9043         } else {
9044                 info->mapping_flags |=
9045                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9046                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9047         }
9048         info->valid_sections |=
9049                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9050
9051         return I40E_SUCCESS;
9052 }
9053
9054 /*
9055  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9056  * @veb: VEB to be configured
9057  * @tc_map: enabled TC bitmap
9058  *
9059  * Returns 0 on success, negative value on failure
9060  */
9061 static enum i40e_status_code
9062 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9063 {
9064         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9065         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9066         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9067         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9068         enum i40e_status_code ret = I40E_SUCCESS;
9069         int i;
9070         uint32_t bw_max;
9071
9072         /* Check if enabled_tc is same as existing or new TCs */
9073         if (veb->enabled_tc == tc_map)
9074                 return ret;
9075
9076         /* configure tc bandwidth */
9077         memset(&veb_bw, 0, sizeof(veb_bw));
9078         veb_bw.tc_valid_bits = tc_map;
9079         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9080         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9081                 if (tc_map & BIT_ULL(i))
9082                         veb_bw.tc_bw_share_credits[i] = 1;
9083         }
9084         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9085                                                    &veb_bw, NULL);
9086         if (ret) {
9087                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9088                                   " per TC failed = %d",
9089                                   hw->aq.asq_last_status);
9090                 return ret;
9091         }
9092
9093         memset(&ets_query, 0, sizeof(ets_query));
9094         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9095                                                    &ets_query, NULL);
9096         if (ret != I40E_SUCCESS) {
9097                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9098                                  " configuration %u", hw->aq.asq_last_status);
9099                 return ret;
9100         }
9101         memset(&bw_query, 0, sizeof(bw_query));
9102         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9103                                                   &bw_query, NULL);
9104         if (ret != I40E_SUCCESS) {
9105                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9106                                  " configuration %u", hw->aq.asq_last_status);
9107                 return ret;
9108         }
9109
9110         /* store and print out BW info */
9111         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9112         veb->bw_info.bw_max = ets_query.tc_bw_max;
9113         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9114         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9115         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9116                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9117                      I40E_16_BIT_WIDTH);
9118         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9119                 veb->bw_info.bw_ets_share_credits[i] =
9120                                 bw_query.tc_bw_share_credits[i];
9121                 veb->bw_info.bw_ets_credits[i] =
9122                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9123                 /* 4 bits per TC, 4th bit is reserved */
9124                 veb->bw_info.bw_ets_max[i] =
9125                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9126                                   RTE_LEN2MASK(3, uint8_t));
9127                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9128                             veb->bw_info.bw_ets_share_credits[i]);
9129                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9130                             veb->bw_info.bw_ets_credits[i]);
9131                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9132                             veb->bw_info.bw_ets_max[i]);
9133         }
9134
9135         veb->enabled_tc = tc_map;
9136
9137         return ret;
9138 }
9139
9140
9141 /*
9142  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9143  * @vsi: VSI to be configured
9144  * @tc_map: enabled TC bitmap
9145  *
9146  * Returns 0 on success, negative value on failure
9147  */
9148 static enum i40e_status_code
9149 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9150 {
9151         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9152         struct i40e_vsi_context ctxt;
9153         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9154         enum i40e_status_code ret = I40E_SUCCESS;
9155         int i;
9156
9157         /* Check if enabled_tc is same as existing or new TCs */
9158         if (vsi->enabled_tc == tc_map)
9159                 return ret;
9160
9161         /* configure tc bandwidth */
9162         memset(&bw_data, 0, sizeof(bw_data));
9163         bw_data.tc_valid_bits = tc_map;
9164         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9165         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9166                 if (tc_map & BIT_ULL(i))
9167                         bw_data.tc_bw_credits[i] = 1;
9168         }
9169         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9170         if (ret) {
9171                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9172                         " per TC failed = %d",
9173                         hw->aq.asq_last_status);
9174                 goto out;
9175         }
9176         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9177                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9178
9179         /* Update Queue Pairs Mapping for currently enabled UPs */
9180         ctxt.seid = vsi->seid;
9181         ctxt.pf_num = hw->pf_id;
9182         ctxt.vf_num = 0;
9183         ctxt.uplink_seid = vsi->uplink_seid;
9184         ctxt.info = vsi->info;
9185         i40e_get_cap(hw);
9186         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9187         if (ret)
9188                 goto out;
9189
9190         /* Update the VSI after updating the VSI queue-mapping information */
9191         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9192         if (ret) {
9193                 PMD_INIT_LOG(ERR, "Failed to configure "
9194                             "TC queue mapping = %d",
9195                             hw->aq.asq_last_status);
9196                 goto out;
9197         }
9198         /* update the local VSI info with updated queue map */
9199         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9200                                         sizeof(vsi->info.tc_mapping));
9201         (void)rte_memcpy(&vsi->info.queue_mapping,
9202                         &ctxt.info.queue_mapping,
9203                 sizeof(vsi->info.queue_mapping));
9204         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9205         vsi->info.valid_sections = 0;
9206
9207         /* query and update current VSI BW information */
9208         ret = i40e_vsi_get_bw_config(vsi);
9209         if (ret) {
9210                 PMD_INIT_LOG(ERR,
9211                          "Failed updating vsi bw info, err %s aq_err %s",
9212                          i40e_stat_str(hw, ret),
9213                          i40e_aq_str(hw, hw->aq.asq_last_status));
9214                 goto out;
9215         }
9216
9217         vsi->enabled_tc = tc_map;
9218
9219 out:
9220         return ret;
9221 }
9222
9223 /*
9224  * i40e_dcb_hw_configure - program the dcb setting to hw
9225  * @pf: pf the configuration is taken on
9226  * @new_cfg: new configuration
9227  * @tc_map: enabled TC bitmap
9228  *
9229  * Returns 0 on success, negative value on failure
9230  */
9231 static enum i40e_status_code
9232 i40e_dcb_hw_configure(struct i40e_pf *pf,
9233                       struct i40e_dcbx_config *new_cfg,
9234                       uint8_t tc_map)
9235 {
9236         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9237         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9238         struct i40e_vsi *main_vsi = pf->main_vsi;
9239         struct i40e_vsi_list *vsi_list;
9240         enum i40e_status_code ret;
9241         int i;
9242         uint32_t val;
9243
9244         /* Use the FW API if FW > v4.4*/
9245         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9246               (hw->aq.fw_maj_ver >= 5))) {
9247                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9248                                   " to configure DCB");
9249                 return I40E_ERR_FIRMWARE_API_VERSION;
9250         }
9251
9252         /* Check if need reconfiguration */
9253         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9254                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9255                 return I40E_SUCCESS;
9256         }
9257
9258         /* Copy the new config to the current config */
9259         *old_cfg = *new_cfg;
9260         old_cfg->etsrec = old_cfg->etscfg;
9261         ret = i40e_set_dcb_config(hw);
9262         if (ret) {
9263                 PMD_INIT_LOG(ERR,
9264                          "Set DCB Config failed, err %s aq_err %s\n",
9265                          i40e_stat_str(hw, ret),
9266                          i40e_aq_str(hw, hw->aq.asq_last_status));
9267                 return ret;
9268         }
9269         /* set receive Arbiter to RR mode and ETS scheme by default */
9270         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9271                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9272                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9273                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9274                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9275                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9276                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9277                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9278                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9279                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9280                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9281                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9282                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9283         }
9284         /* get local mib to check whether it is configured correctly */
9285         /* IEEE mode */
9286         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9287         /* Get Local DCB Config */
9288         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9289                                      &hw->local_dcbx_config);
9290
9291         /* if Veb is created, need to update TC of it at first */
9292         if (main_vsi->veb) {
9293                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9294                 if (ret)
9295                         PMD_INIT_LOG(WARNING,
9296                                  "Failed configuring TC for VEB seid=%d\n",
9297                                  main_vsi->veb->seid);
9298         }
9299         /* Update each VSI */
9300         i40e_vsi_config_tc(main_vsi, tc_map);
9301         if (main_vsi->veb) {
9302                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9303                         /* Beside main VSI and VMDQ VSIs, only enable default
9304                          * TC for other VSIs
9305                          */
9306                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9307                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9308                                                          tc_map);
9309                         else
9310                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9311                                                          I40E_DEFAULT_TCMAP);
9312                         if (ret)
9313                                 PMD_INIT_LOG(WARNING,
9314                                          "Failed configuring TC for VSI seid=%d\n",
9315                                          vsi_list->vsi->seid);
9316                         /* continue */
9317                 }
9318         }
9319         return I40E_SUCCESS;
9320 }
9321
9322 /*
9323  * i40e_dcb_init_configure - initial dcb config
9324  * @dev: device being configured
9325  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9326  *
9327  * Returns 0 on success, negative value on failure
9328  */
9329 static int
9330 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9331 {
9332         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9334         int ret = 0;
9335
9336         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9337                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9338                 return -ENOTSUP;
9339         }
9340
9341         /* DCB initialization:
9342          * Update DCB configuration from the Firmware and configure
9343          * LLDP MIB change event.
9344          */
9345         if (sw_dcb == TRUE) {
9346                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9347                 if (ret != I40E_SUCCESS)
9348                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9349
9350                 ret = i40e_init_dcb(hw);
9351                 /* if sw_dcb, lldp agent is stopped, the return from
9352                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9353                  * adminq status.
9354                  */
9355                 if (ret != I40E_SUCCESS &&
9356                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9357                         memset(&hw->local_dcbx_config, 0,
9358                                 sizeof(struct i40e_dcbx_config));
9359                         /* set dcb default configuration */
9360                         hw->local_dcbx_config.etscfg.willing = 0;
9361                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9362                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9363                         hw->local_dcbx_config.etscfg.tsatable[0] =
9364                                                 I40E_IEEE_TSA_ETS;
9365                         hw->local_dcbx_config.etsrec =
9366                                 hw->local_dcbx_config.etscfg;
9367                         hw->local_dcbx_config.pfc.willing = 0;
9368                         hw->local_dcbx_config.pfc.pfccap =
9369                                                 I40E_MAX_TRAFFIC_CLASS;
9370                         /* FW needs one App to configure HW */
9371                         hw->local_dcbx_config.numapps = 1;
9372                         hw->local_dcbx_config.app[0].selector =
9373                                                 I40E_APP_SEL_ETHTYPE;
9374                         hw->local_dcbx_config.app[0].priority = 3;
9375                         hw->local_dcbx_config.app[0].protocolid =
9376                                                 I40E_APP_PROTOID_FCOE;
9377                         ret = i40e_set_dcb_config(hw);
9378                         if (ret) {
9379                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9380                                         " err = %d, aq_err = %d.", ret,
9381                                           hw->aq.asq_last_status);
9382                                 return -ENOSYS;
9383                         }
9384                 } else {
9385                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9386                                           " aq_err = %d.", ret,
9387                                           hw->aq.asq_last_status);
9388                         return -ENOTSUP;
9389                 }
9390         } else {
9391                 ret = i40e_aq_start_lldp(hw, NULL);
9392                 if (ret != I40E_SUCCESS)
9393                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9394
9395                 ret = i40e_init_dcb(hw);
9396                 if (!ret) {
9397                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9398                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9399                                                   " DCBX offload.");
9400                                 return -ENOTSUP;
9401                         }
9402                 } else {
9403                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9404                                           " aq_err = %d.", ret,
9405                                           hw->aq.asq_last_status);
9406                         return -ENOTSUP;
9407                 }
9408         }
9409         return 0;
9410 }
9411
9412 /*
9413  * i40e_dcb_setup - setup dcb related config
9414  * @dev: device being configured
9415  *
9416  * Returns 0 on success, negative value on failure
9417  */
9418 static int
9419 i40e_dcb_setup(struct rte_eth_dev *dev)
9420 {
9421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9422         struct i40e_dcbx_config dcb_cfg;
9423         uint8_t tc_map = 0;
9424         int ret = 0;
9425
9426         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9427                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9428                 return -ENOTSUP;
9429         }
9430
9431         if (pf->vf_num != 0)
9432                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9433
9434         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9435         if (ret) {
9436                 PMD_INIT_LOG(ERR, "invalid dcb config");
9437                 return -EINVAL;
9438         }
9439         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9440         if (ret) {
9441                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9442                 return -ENOSYS;
9443         }
9444
9445         return 0;
9446 }
9447
9448 static int
9449 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9450                       struct rte_eth_dcb_info *dcb_info)
9451 {
9452         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9453         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9454         struct i40e_vsi *vsi = pf->main_vsi;
9455         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9456         uint16_t bsf, tc_mapping;
9457         int i, j = 0;
9458
9459         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9460                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9461         else
9462                 dcb_info->nb_tcs = 1;
9463         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9464                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9465         for (i = 0; i < dcb_info->nb_tcs; i++)
9466                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9467
9468         /* get queue mapping if vmdq is disabled */
9469         if (!pf->nb_cfg_vmdq_vsi) {
9470                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9471                         if (!(vsi->enabled_tc & (1 << i)))
9472                                 continue;
9473                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9474                         dcb_info->tc_queue.tc_rxq[j][i].base =
9475                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9476                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9477                         dcb_info->tc_queue.tc_txq[j][i].base =
9478                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9479                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9480                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9481                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9482                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9483                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9484                 }
9485                 return 0;
9486         }
9487
9488         /* get queue mapping if vmdq is enabled */
9489         do {
9490                 vsi = pf->vmdq[j].vsi;
9491                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9492                         if (!(vsi->enabled_tc & (1 << i)))
9493                                 continue;
9494                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9495                         dcb_info->tc_queue.tc_rxq[j][i].base =
9496                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9497                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9498                         dcb_info->tc_queue.tc_txq[j][i].base =
9499                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9500                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9501                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9502                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9503                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9504                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9505                 }
9506                 j++;
9507         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9508         return 0;
9509 }
9510
9511 static int
9512 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9513 {
9514         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9516         uint16_t interval =
9517                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9518         uint16_t msix_intr;
9519
9520         msix_intr = intr_handle->intr_vec[queue_id];
9521         if (msix_intr == I40E_MISC_VEC_ID)
9522                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9523                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9524                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9525                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9526                                (interval <<
9527                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9528         else
9529                 I40E_WRITE_REG(hw,
9530                                I40E_PFINT_DYN_CTLN(msix_intr -
9531                                                    I40E_RX_VEC_START),
9532                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9533                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9534                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9535                                (interval <<
9536                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9537
9538         I40E_WRITE_FLUSH(hw);
9539         rte_intr_enable(&dev->pci_dev->intr_handle);
9540
9541         return 0;
9542 }
9543
9544 static int
9545 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9546 {
9547         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9548         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9549         uint16_t msix_intr;
9550
9551         msix_intr = intr_handle->intr_vec[queue_id];
9552         if (msix_intr == I40E_MISC_VEC_ID)
9553                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9554         else
9555                 I40E_WRITE_REG(hw,
9556                                I40E_PFINT_DYN_CTLN(msix_intr -
9557                                                    I40E_RX_VEC_START),
9558                                0);
9559         I40E_WRITE_FLUSH(hw);
9560
9561         return 0;
9562 }
9563
9564 static int i40e_get_regs(struct rte_eth_dev *dev,
9565                          struct rte_dev_reg_info *regs)
9566 {
9567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9568         uint32_t *ptr_data = regs->data;
9569         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9570         const struct i40e_reg_info *reg_info;
9571
9572         if (ptr_data == NULL) {
9573                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9574                 regs->width = sizeof(uint32_t);
9575                 return 0;
9576         }
9577
9578         /* The first few registers have to be read using AQ operations */
9579         reg_idx = 0;
9580         while (i40e_regs_adminq[reg_idx].name) {
9581                 reg_info = &i40e_regs_adminq[reg_idx++];
9582                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9583                         for (arr_idx2 = 0;
9584                                         arr_idx2 <= reg_info->count2;
9585                                         arr_idx2++) {
9586                                 reg_offset = arr_idx * reg_info->stride1 +
9587                                         arr_idx2 * reg_info->stride2;
9588                                 reg_offset += reg_info->base_addr;
9589                                 ptr_data[reg_offset >> 2] =
9590                                         i40e_read_rx_ctl(hw, reg_offset);
9591                         }
9592         }
9593
9594         /* The remaining registers can be read using primitives */
9595         reg_idx = 0;
9596         while (i40e_regs_others[reg_idx].name) {
9597                 reg_info = &i40e_regs_others[reg_idx++];
9598                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9599                         for (arr_idx2 = 0;
9600                                         arr_idx2 <= reg_info->count2;
9601                                         arr_idx2++) {
9602                                 reg_offset = arr_idx * reg_info->stride1 +
9603                                         arr_idx2 * reg_info->stride2;
9604                                 reg_offset += reg_info->base_addr;
9605                                 ptr_data[reg_offset >> 2] =
9606                                         I40E_READ_REG(hw, reg_offset);
9607                         }
9608         }
9609
9610         return 0;
9611 }
9612
9613 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9614 {
9615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9616
9617         /* Convert word count to byte count */
9618         return hw->nvm.sr_size << 1;
9619 }
9620
9621 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9622                            struct rte_dev_eeprom_info *eeprom)
9623 {
9624         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9625         uint16_t *data = eeprom->data;
9626         uint16_t offset, length, cnt_words;
9627         int ret_code;
9628
9629         offset = eeprom->offset >> 1;
9630         length = eeprom->length >> 1;
9631         cnt_words = length;
9632
9633         if (offset > hw->nvm.sr_size ||
9634                 offset + length > hw->nvm.sr_size) {
9635                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9636                 return -EINVAL;
9637         }
9638
9639         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9640
9641         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9642         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9643                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9644                 return -EIO;
9645         }
9646
9647         return 0;
9648 }
9649
9650 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9651                                       struct ether_addr *mac_addr)
9652 {
9653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9654
9655         if (!is_valid_assigned_ether_addr(mac_addr)) {
9656                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9657                 return;
9658         }
9659
9660         /* Flags: 0x3 updates port address */
9661         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9662 }
9663
9664 static int
9665 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9666 {
9667         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9668         struct rte_eth_dev_data *dev_data = pf->dev_data;
9669         uint32_t frame_size = mtu + ETHER_HDR_LEN
9670                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9671         int ret = 0;
9672
9673         /* check if mtu is within the allowed range */
9674         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9675                 return -EINVAL;
9676
9677         /* mtu setting is forbidden if port is start */
9678         if (dev_data->dev_started) {
9679                 PMD_DRV_LOG(ERR,
9680                             "port %d must be stopped before configuration\n",
9681                             dev_data->port_id);
9682                 return -EBUSY;
9683         }
9684
9685         if (frame_size > ETHER_MAX_LEN)
9686                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9687         else
9688                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9689
9690         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9691
9692         return ret;
9693 }