4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
68 #include "rte_pmd_i40e.h"
70 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
71 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
73 #define I40E_CLEAR_PXE_WAIT_MS 200
75 /* Maximun number of capability elements */
76 #define I40E_MAX_CAP_ELE_NUM 128
78 /* Wait count and interval */
79 #define I40E_CHK_Q_ENA_COUNT 1000
80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
82 /* Maximun number of VSI */
83 #define I40E_MAX_NUM_VSIS (384UL)
85 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
87 /* Flow control default timer */
88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
90 /* Flow control enable fwd bit */
91 #define I40E_PRTMAC_FWD_CTRL 0x00000001
93 /* Receive Packet Buffer size */
94 #define I40E_RXPBSIZE (968 * 1024)
97 #define I40E_KILOSHIFT 10
99 /* Flow control default high water */
100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
102 /* Flow control default low water */
103 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
105 /* Receive Average Packet Size in Byte*/
106 #define I40E_PACKET_AVERAGE_SIZE 128
108 /* Mask of PF interrupt causes */
109 #define I40E_PFINT_ICR0_ENA_MASK ( \
110 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
112 I40E_PFINT_ICR0_ENA_GRST_MASK | \
113 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
114 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
115 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
116 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
117 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
118 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
120 #define I40E_FLOW_TYPES ( \
121 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
126 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
130 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
131 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
133 /* Additional timesync values. */
134 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
135 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
136 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
137 #define I40E_PRTTSYN_TSYNENA 0x80000000
138 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
139 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define I40E_MAX_PERCENT 100
142 #define I40E_DEFAULT_DCB_APP_NUM 1
143 #define I40E_DEFAULT_DCB_APP_PRIO 3
146 * Below are values for writing un-exposed registers suggested
149 /* Destination MAC address */
150 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
151 /* Source MAC address */
152 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
153 /* Outer (S-Tag) VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
155 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
156 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
157 /* Single VLAN tag in the inner L2 header */
158 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
159 /* Source IPv4 address */
160 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
161 /* Destination IPv4 address */
162 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
163 /* Source IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
165 /* Destination IPv4 address for X722 */
166 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
167 /* IPv4 Protocol for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
169 /* IPv4 Time to Live for X722 */
170 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
171 /* IPv4 Type of Service (TOS) */
172 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
174 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
175 /* IPv4 Time to Live */
176 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
177 /* Source IPv6 address */
178 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
179 /* Destination IPv6 address */
180 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
181 /* IPv6 Traffic Class (TC) */
182 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
183 /* IPv6 Next Header */
184 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
186 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
188 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
189 /* Destination L4 port */
190 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
191 /* SCTP verification tag */
192 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
193 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
194 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
195 /* Source port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
197 /* Destination port of tunneling UDP */
198 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
199 /* UDP Tunneling ID, NVGRE/GRE key */
200 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
201 /* Last ether type */
202 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
203 /* Tunneling outer destination IPv4 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
205 /* Tunneling outer destination IPv6 address */
206 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
207 /* 1st word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
209 /* 2nd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
211 /* 3rd word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
213 /* 4th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
215 /* 5th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
217 /* 6th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
219 /* 7th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
221 /* 8th word of flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
223 /* all 8 words flex payload */
224 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
225 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
227 #define I40E_TRANSLATE_INSET 0
228 #define I40E_TRANSLATE_REG 1
230 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
231 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
232 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
233 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
234 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
235 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
237 /* PCI offset for querying capability */
238 #define PCI_DEV_CAP_REG 0xA4
239 /* PCI offset for enabling/disabling Extended Tag */
240 #define PCI_DEV_CTRL_REG 0xA8
241 /* Bit mask of Extended Tag capability */
242 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
243 /* Bit shift of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
245 /* Bit mask of Extended Tag enable/disable */
246 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
248 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
249 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
250 static int i40e_dev_configure(struct rte_eth_dev *dev);
251 static int i40e_dev_start(struct rte_eth_dev *dev);
252 static void i40e_dev_stop(struct rte_eth_dev *dev);
253 static void i40e_dev_close(struct rte_eth_dev *dev);
254 static int i40e_dev_reset(struct rte_eth_dev *dev);
255 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
257 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
258 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
259 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
260 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
261 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
262 struct rte_eth_stats *stats);
263 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
264 struct rte_eth_xstat *xstats, unsigned n);
265 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
266 struct rte_eth_xstat_name *xstats_names,
268 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
269 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
273 static int i40e_fw_version_get(struct rte_eth_dev *dev,
274 char *fw_version, size_t fw_size);
275 static void i40e_dev_info_get(struct rte_eth_dev *dev,
276 struct rte_eth_dev_info *dev_info);
277 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
280 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
281 enum rte_vlan_type vlan_type,
283 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
284 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
287 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
288 static int i40e_dev_led_on(struct rte_eth_dev *dev);
289 static int i40e_dev_led_off(struct rte_eth_dev *dev);
290 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_fc_conf *fc_conf);
294 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
295 struct rte_eth_pfc_conf *pfc_conf);
296 static int i40e_macaddr_add(struct rte_eth_dev *dev,
297 struct ether_addr *mac_addr,
300 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
301 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
304 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
305 struct rte_eth_rss_reta_entry64 *reta_conf,
308 static int i40e_get_cap(struct i40e_hw *hw);
309 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
310 static int i40e_pf_setup(struct i40e_pf *pf);
311 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
312 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
313 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
314 static int i40e_dcb_setup(struct rte_eth_dev *dev);
315 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
316 bool offset_loaded, uint64_t *offset, uint64_t *stat);
317 static void i40e_stat_update_48(struct i40e_hw *hw,
323 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
324 static void i40e_dev_interrupt_handler(void *param);
325 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
326 uint32_t base, uint32_t num);
327 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
328 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
330 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
332 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
333 static int i40e_veb_release(struct i40e_veb *veb);
334 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
335 struct i40e_vsi *vsi);
336 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
337 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
338 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
339 struct i40e_macvlan_filter *mv_f,
342 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
343 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
347 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static void i40e_filter_input_set_init(struct i40e_pf *pf);
352 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
353 enum rte_filter_op filter_op,
355 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
356 enum rte_filter_type filter_type,
357 enum rte_filter_op filter_op,
359 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
360 struct rte_eth_dcb_info *dcb_info);
361 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
362 static void i40e_configure_registers(struct i40e_hw *hw);
363 static void i40e_hw_init(struct rte_eth_dev *dev);
364 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
365 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
371 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
372 struct rte_eth_mirror_conf *mirror_conf,
373 uint8_t sw_id, uint8_t on);
374 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
376 static int i40e_timesync_enable(struct rte_eth_dev *dev);
377 static int i40e_timesync_disable(struct rte_eth_dev *dev);
378 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
379 struct timespec *timestamp,
381 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
382 struct timespec *timestamp);
383 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
385 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
387 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
388 struct timespec *timestamp);
389 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
390 const struct timespec *timestamp);
392 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
394 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
397 static int i40e_get_regs(struct rte_eth_dev *dev,
398 struct rte_dev_reg_info *regs);
400 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
402 static int i40e_get_eeprom(struct rte_eth_dev *dev,
403 struct rte_dev_eeprom_info *eeprom);
405 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
406 struct ether_addr *mac_addr);
408 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
410 static int i40e_ethertype_filter_convert(
411 const struct rte_eth_ethertype_filter *input,
412 struct i40e_ethertype_filter *filter);
413 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
414 struct i40e_ethertype_filter *filter);
416 static int i40e_tunnel_filter_convert(
417 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
418 struct i40e_tunnel_filter *tunnel_filter);
419 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
420 struct i40e_tunnel_filter *tunnel_filter);
421 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
423 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
424 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
425 static void i40e_filter_restore(struct i40e_pf *pf);
426 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
428 int i40e_logtype_init;
429 int i40e_logtype_driver;
431 static const struct rte_pci_id pci_id_i40e_map[] = {
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
452 { .vendor_id = 0, /* sentinel */ },
455 static const struct eth_dev_ops i40e_eth_dev_ops = {
456 .dev_configure = i40e_dev_configure,
457 .dev_start = i40e_dev_start,
458 .dev_stop = i40e_dev_stop,
459 .dev_close = i40e_dev_close,
460 .dev_reset = i40e_dev_reset,
461 .promiscuous_enable = i40e_dev_promiscuous_enable,
462 .promiscuous_disable = i40e_dev_promiscuous_disable,
463 .allmulticast_enable = i40e_dev_allmulticast_enable,
464 .allmulticast_disable = i40e_dev_allmulticast_disable,
465 .dev_set_link_up = i40e_dev_set_link_up,
466 .dev_set_link_down = i40e_dev_set_link_down,
467 .link_update = i40e_dev_link_update,
468 .stats_get = i40e_dev_stats_get,
469 .xstats_get = i40e_dev_xstats_get,
470 .xstats_get_names = i40e_dev_xstats_get_names,
471 .stats_reset = i40e_dev_stats_reset,
472 .xstats_reset = i40e_dev_stats_reset,
473 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
474 .fw_version_get = i40e_fw_version_get,
475 .dev_infos_get = i40e_dev_info_get,
476 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
477 .vlan_filter_set = i40e_vlan_filter_set,
478 .vlan_tpid_set = i40e_vlan_tpid_set,
479 .vlan_offload_set = i40e_vlan_offload_set,
480 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
481 .vlan_pvid_set = i40e_vlan_pvid_set,
482 .rx_queue_start = i40e_dev_rx_queue_start,
483 .rx_queue_stop = i40e_dev_rx_queue_stop,
484 .tx_queue_start = i40e_dev_tx_queue_start,
485 .tx_queue_stop = i40e_dev_tx_queue_stop,
486 .rx_queue_setup = i40e_dev_rx_queue_setup,
487 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
488 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
489 .rx_queue_release = i40e_dev_rx_queue_release,
490 .rx_queue_count = i40e_dev_rx_queue_count,
491 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
492 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
493 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
494 .tx_queue_setup = i40e_dev_tx_queue_setup,
495 .tx_queue_release = i40e_dev_tx_queue_release,
496 .dev_led_on = i40e_dev_led_on,
497 .dev_led_off = i40e_dev_led_off,
498 .flow_ctrl_get = i40e_flow_ctrl_get,
499 .flow_ctrl_set = i40e_flow_ctrl_set,
500 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
501 .mac_addr_add = i40e_macaddr_add,
502 .mac_addr_remove = i40e_macaddr_remove,
503 .reta_update = i40e_dev_rss_reta_update,
504 .reta_query = i40e_dev_rss_reta_query,
505 .rss_hash_update = i40e_dev_rss_hash_update,
506 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
507 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
508 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
509 .filter_ctrl = i40e_dev_filter_ctrl,
510 .rxq_info_get = i40e_rxq_info_get,
511 .txq_info_get = i40e_txq_info_get,
512 .mirror_rule_set = i40e_mirror_rule_set,
513 .mirror_rule_reset = i40e_mirror_rule_reset,
514 .timesync_enable = i40e_timesync_enable,
515 .timesync_disable = i40e_timesync_disable,
516 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
517 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
518 .get_dcb_info = i40e_dev_get_dcb_info,
519 .timesync_adjust_time = i40e_timesync_adjust_time,
520 .timesync_read_time = i40e_timesync_read_time,
521 .timesync_write_time = i40e_timesync_write_time,
522 .get_reg = i40e_get_regs,
523 .get_eeprom_length = i40e_get_eeprom_length,
524 .get_eeprom = i40e_get_eeprom,
525 .mac_addr_set = i40e_set_default_mac_addr,
526 .mtu_set = i40e_dev_mtu_set,
527 .tm_ops_get = i40e_tm_ops_get,
530 /* store statistics names and its offset in stats structure */
531 struct rte_i40e_xstats_name_off {
532 char name[RTE_ETH_XSTATS_NAME_SIZE];
536 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
537 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
538 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
539 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
540 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
541 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
542 rx_unknown_protocol)},
543 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
544 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
545 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
546 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
549 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
550 sizeof(rte_i40e_stats_strings[0]))
552 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
553 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
554 tx_dropped_link_down)},
555 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
556 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
559 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
561 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
563 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
565 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
566 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
567 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
568 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
569 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
570 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
584 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
587 mac_short_packet_dropped)},
588 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
590 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
591 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
592 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
604 {"rx_flow_director_atr_match_packets",
605 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
606 {"rx_flow_director_sb_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
608 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
610 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
614 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
619 sizeof(rte_i40e_hw_port_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
628 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
629 sizeof(rte_i40e_rxq_prio_strings[0]))
631 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
632 {"xon_packets", offsetof(struct i40e_hw_port_stats,
634 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
636 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
637 priority_xon_2_xoff)},
640 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
641 sizeof(rte_i40e_txq_prio_strings[0]))
643 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
644 struct rte_pci_device *pci_dev)
646 return rte_eth_dev_pci_generic_probe(pci_dev,
647 sizeof(struct i40e_adapter), eth_i40e_dev_init);
650 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
652 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
655 static struct rte_pci_driver rte_i40e_pmd = {
656 .id_table = pci_id_i40e_map,
657 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
658 .probe = eth_i40e_pci_probe,
659 .remove = eth_i40e_pci_remove,
663 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
664 struct rte_eth_link *link)
666 struct rte_eth_link *dst = link;
667 struct rte_eth_link *src = &(dev->data->dev_link);
669 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
670 *(uint64_t *)src) == 0)
677 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
678 struct rte_eth_link *link)
680 struct rte_eth_link *dst = &(dev->data->dev_link);
681 struct rte_eth_link *src = link;
683 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
684 *(uint64_t *)src) == 0)
690 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
691 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
692 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
694 #ifndef I40E_GLQF_ORT
695 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
697 #ifndef I40E_GLQF_PIT
698 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
700 #ifndef I40E_GLQF_L3_MAP
701 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
704 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
707 * Initialize registers for flexible payload, which should be set by NVM.
708 * This should be removed from code once it is fixed in NVM.
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
720 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
721 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
723 /* Initialize registers for parsing packet type of QinQ */
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
725 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
728 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
731 * Add a ethertype filter to drop all flow control frames transmitted
735 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
737 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
738 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
739 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
740 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
743 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
744 I40E_FLOW_CONTROL_ETHERTYPE, flags,
745 pf->main_vsi_seid, 0,
749 "Failed to add filter to drop flow control frames from VSIs.");
753 floating_veb_list_handler(__rte_unused const char *key,
754 const char *floating_veb_value,
758 unsigned int count = 0;
761 bool *vf_floating_veb = opaque;
763 while (isblank(*floating_veb_value))
764 floating_veb_value++;
766 /* Reset floating VEB configuration for VFs */
767 for (idx = 0; idx < I40E_MAX_VF; idx++)
768 vf_floating_veb[idx] = false;
772 while (isblank(*floating_veb_value))
773 floating_veb_value++;
774 if (*floating_veb_value == '\0')
777 idx = strtoul(floating_veb_value, &end, 10);
778 if (errno || end == NULL)
780 while (isblank(*end))
784 } else if ((*end == ';') || (*end == '\0')) {
786 if (min == I40E_MAX_VF)
788 if (max >= I40E_MAX_VF)
789 max = I40E_MAX_VF - 1;
790 for (idx = min; idx <= max; idx++) {
791 vf_floating_veb[idx] = true;
798 floating_veb_value = end + 1;
799 } while (*end != '\0');
808 config_vf_floating_veb(struct rte_devargs *devargs,
809 uint16_t floating_veb,
810 bool *vf_floating_veb)
812 struct rte_kvargs *kvlist;
814 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
818 /* All the VFs attach to the floating VEB by default
819 * when the floating VEB is enabled.
821 for (i = 0; i < I40E_MAX_VF; i++)
822 vf_floating_veb[i] = true;
827 kvlist = rte_kvargs_parse(devargs->args, NULL);
831 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
832 rte_kvargs_free(kvlist);
835 /* When the floating_veb_list parameter exists, all the VFs
836 * will attach to the legacy VEB firstly, then configure VFs
837 * to the floating VEB according to the floating_veb_list.
839 if (rte_kvargs_process(kvlist, floating_veb_list,
840 floating_veb_list_handler,
841 vf_floating_veb) < 0) {
842 rte_kvargs_free(kvlist);
845 rte_kvargs_free(kvlist);
849 i40e_check_floating_handler(__rte_unused const char *key,
851 __rte_unused void *opaque)
853 if (strcmp(value, "1"))
860 is_floating_veb_supported(struct rte_devargs *devargs)
862 struct rte_kvargs *kvlist;
863 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
868 kvlist = rte_kvargs_parse(devargs->args, NULL);
872 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
873 rte_kvargs_free(kvlist);
876 /* Floating VEB is enabled when there's key-value:
877 * enable_floating_veb=1
879 if (rte_kvargs_process(kvlist, floating_veb_key,
880 i40e_check_floating_handler, NULL) < 0) {
881 rte_kvargs_free(kvlist);
884 rte_kvargs_free(kvlist);
890 config_floating_veb(struct rte_eth_dev *dev)
892 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
893 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
894 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
898 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
900 is_floating_veb_supported(pci_dev->device.devargs);
901 config_vf_floating_veb(pci_dev->device.devargs,
903 pf->floating_veb_list);
905 pf->floating_veb = false;
909 #define I40E_L2_TAGS_S_TAG_SHIFT 1
910 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
913 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
916 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
917 char ethertype_hash_name[RTE_HASH_NAMESIZE];
920 struct rte_hash_parameters ethertype_hash_params = {
921 .name = ethertype_hash_name,
922 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
923 .key_len = sizeof(struct i40e_ethertype_filter_input),
924 .hash_func = rte_hash_crc,
925 .hash_func_init_val = 0,
926 .socket_id = rte_socket_id(),
929 /* Initialize ethertype filter rule list and hash */
930 TAILQ_INIT(ðertype_rule->ethertype_list);
931 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
932 "ethertype_%s", dev->device->name);
933 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
934 if (!ethertype_rule->hash_table) {
935 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
938 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
939 sizeof(struct i40e_ethertype_filter *) *
940 I40E_MAX_ETHERTYPE_FILTER_NUM,
942 if (!ethertype_rule->hash_map) {
944 "Failed to allocate memory for ethertype hash map!");
946 goto err_ethertype_hash_map_alloc;
951 err_ethertype_hash_map_alloc:
952 rte_hash_free(ethertype_rule->hash_table);
958 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
960 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
961 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
962 char tunnel_hash_name[RTE_HASH_NAMESIZE];
965 struct rte_hash_parameters tunnel_hash_params = {
966 .name = tunnel_hash_name,
967 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
968 .key_len = sizeof(struct i40e_tunnel_filter_input),
969 .hash_func = rte_hash_crc,
970 .hash_func_init_val = 0,
971 .socket_id = rte_socket_id(),
974 /* Initialize tunnel filter rule list and hash */
975 TAILQ_INIT(&tunnel_rule->tunnel_list);
976 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
977 "tunnel_%s", dev->device->name);
978 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
979 if (!tunnel_rule->hash_table) {
980 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
983 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
984 sizeof(struct i40e_tunnel_filter *) *
985 I40E_MAX_TUNNEL_FILTER_NUM,
987 if (!tunnel_rule->hash_map) {
989 "Failed to allocate memory for tunnel hash map!");
991 goto err_tunnel_hash_map_alloc;
996 err_tunnel_hash_map_alloc:
997 rte_hash_free(tunnel_rule->hash_table);
1003 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1005 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1006 struct i40e_fdir_info *fdir_info = &pf->fdir;
1007 char fdir_hash_name[RTE_HASH_NAMESIZE];
1010 struct rte_hash_parameters fdir_hash_params = {
1011 .name = fdir_hash_name,
1012 .entries = I40E_MAX_FDIR_FILTER_NUM,
1013 .key_len = sizeof(struct rte_eth_fdir_input),
1014 .hash_func = rte_hash_crc,
1015 .hash_func_init_val = 0,
1016 .socket_id = rte_socket_id(),
1019 /* Initialize flow director filter rule list and hash */
1020 TAILQ_INIT(&fdir_info->fdir_list);
1021 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1022 "fdir_%s", dev->device->name);
1023 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1024 if (!fdir_info->hash_table) {
1025 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1028 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1029 sizeof(struct i40e_fdir_filter *) *
1030 I40E_MAX_FDIR_FILTER_NUM,
1032 if (!fdir_info->hash_map) {
1034 "Failed to allocate memory for fdir hash map!");
1036 goto err_fdir_hash_map_alloc;
1040 err_fdir_hash_map_alloc:
1041 rte_hash_free(fdir_info->hash_table);
1047 i40e_init_customized_info(struct i40e_pf *pf)
1051 /* Initialize customized pctype */
1052 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1053 pf->customized_pctype[i].index = i;
1054 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1055 pf->customized_pctype[i].valid = false;
1058 pf->gtp_support = false;
1062 eth_i40e_dev_init(struct rte_eth_dev *dev)
1064 struct rte_pci_device *pci_dev;
1065 struct rte_intr_handle *intr_handle;
1066 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1067 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1068 struct i40e_vsi *vsi;
1071 uint8_t aq_fail = 0;
1073 PMD_INIT_FUNC_TRACE();
1075 dev->dev_ops = &i40e_eth_dev_ops;
1076 dev->rx_pkt_burst = i40e_recv_pkts;
1077 dev->tx_pkt_burst = i40e_xmit_pkts;
1078 dev->tx_pkt_prepare = i40e_prep_pkts;
1080 /* for secondary processes, we don't initialise any further as primary
1081 * has already done this work. Only check we don't need a different
1083 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1084 i40e_set_rx_function(dev);
1085 i40e_set_tx_function(dev);
1088 i40e_set_default_ptype_table(dev);
1089 i40e_set_default_pctype_table(dev);
1090 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1091 intr_handle = &pci_dev->intr_handle;
1093 rte_eth_copy_pci_info(dev, pci_dev);
1094 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1096 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1097 pf->adapter->eth_dev = dev;
1098 pf->dev_data = dev->data;
1100 hw->back = I40E_PF_TO_ADAPTER(pf);
1101 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1104 "Hardware is not available, as address is NULL");
1108 hw->vendor_id = pci_dev->id.vendor_id;
1109 hw->device_id = pci_dev->id.device_id;
1110 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1111 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1112 hw->bus.device = pci_dev->addr.devid;
1113 hw->bus.func = pci_dev->addr.function;
1114 hw->adapter_stopped = 0;
1116 /* Make sure all is clean before doing PF reset */
1119 /* Initialize the hardware */
1122 /* Reset here to make sure all is clean for each PF */
1123 ret = i40e_pf_reset(hw);
1125 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1129 /* Initialize the shared code (base driver) */
1130 ret = i40e_init_shared_code(hw);
1132 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1137 * To work around the NVM issue, initialize registers
1138 * for flexible payload and packet type of QinQ by
1139 * software. It should be removed once issues are fixed
1142 i40e_GLQF_reg_init(hw);
1144 /* Initialize the input set for filters (hash and fd) to default value */
1145 i40e_filter_input_set_init(pf);
1147 /* Initialize the parameters for adminq */
1148 i40e_init_adminq_parameter(hw);
1149 ret = i40e_init_adminq(hw);
1150 if (ret != I40E_SUCCESS) {
1151 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1154 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1155 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1156 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1157 ((hw->nvm.version >> 12) & 0xf),
1158 ((hw->nvm.version >> 4) & 0xff),
1159 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1161 /* initialise the L3_MAP register */
1162 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1165 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1167 /* Need the special FW version to support floating VEB */
1168 config_floating_veb(dev);
1169 /* Clear PXE mode */
1170 i40e_clear_pxe_mode(hw);
1171 i40e_dev_sync_phy_type(hw);
1174 * On X710, performance number is far from the expectation on recent
1175 * firmware versions. The fix for this issue may not be integrated in
1176 * the following firmware version. So the workaround in software driver
1177 * is needed. It needs to modify the initial values of 3 internal only
1178 * registers. Note that the workaround can be removed when it is fixed
1179 * in firmware in the future.
1181 i40e_configure_registers(hw);
1183 /* Get hw capabilities */
1184 ret = i40e_get_cap(hw);
1185 if (ret != I40E_SUCCESS) {
1186 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1187 goto err_get_capabilities;
1190 /* Initialize parameters for PF */
1191 ret = i40e_pf_parameter_init(dev);
1193 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1194 goto err_parameter_init;
1197 /* Initialize the queue management */
1198 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1200 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1201 goto err_qp_pool_init;
1203 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1204 hw->func_caps.num_msix_vectors - 1);
1206 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1207 goto err_msix_pool_init;
1210 /* Initialize lan hmc */
1211 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1212 hw->func_caps.num_rx_qp, 0, 0);
1213 if (ret != I40E_SUCCESS) {
1214 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1215 goto err_init_lan_hmc;
1218 /* Configure lan hmc */
1219 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1220 if (ret != I40E_SUCCESS) {
1221 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1222 goto err_configure_lan_hmc;
1225 /* Get and check the mac address */
1226 i40e_get_mac_addr(hw, hw->mac.addr);
1227 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1228 PMD_INIT_LOG(ERR, "mac address is not valid");
1230 goto err_get_mac_addr;
1232 /* Copy the permanent MAC address */
1233 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1234 (struct ether_addr *) hw->mac.perm_addr);
1236 /* Disable flow control */
1237 hw->fc.requested_mode = I40E_FC_NONE;
1238 i40e_set_fc(hw, &aq_fail, TRUE);
1240 /* Set the global registers with default ether type value */
1241 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1242 if (ret != I40E_SUCCESS) {
1244 "Failed to set the default outer VLAN ether type");
1245 goto err_setup_pf_switch;
1248 /* PF setup, which includes VSI setup */
1249 ret = i40e_pf_setup(pf);
1251 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1252 goto err_setup_pf_switch;
1255 /* reset all stats of the device, including pf and main vsi */
1256 i40e_dev_stats_reset(dev);
1260 /* Disable double vlan by default */
1261 i40e_vsi_config_double_vlan(vsi, FALSE);
1263 /* Disable S-TAG identification when floating_veb is disabled */
1264 if (!pf->floating_veb) {
1265 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1266 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1267 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1268 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1272 if (!vsi->max_macaddrs)
1273 len = ETHER_ADDR_LEN;
1275 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1277 /* Should be after VSI initialized */
1278 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1279 if (!dev->data->mac_addrs) {
1281 "Failed to allocated memory for storing mac address");
1284 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1285 &dev->data->mac_addrs[0]);
1287 /* Init dcb to sw mode by default */
1288 ret = i40e_dcb_init_configure(dev, TRUE);
1289 if (ret != I40E_SUCCESS) {
1290 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1291 pf->flags &= ~I40E_FLAG_DCB;
1293 /* Update HW struct after DCB configuration */
1296 /* initialize pf host driver to setup SRIOV resource if applicable */
1297 i40e_pf_host_init(dev);
1299 /* register callback func to eal lib */
1300 rte_intr_callback_register(intr_handle,
1301 i40e_dev_interrupt_handler, dev);
1303 /* configure and enable device interrupt */
1304 i40e_pf_config_irq0(hw, TRUE);
1305 i40e_pf_enable_irq0(hw);
1307 /* enable uio intr after callback register */
1308 rte_intr_enable(intr_handle);
1310 * Add an ethertype filter to drop all flow control frames transmitted
1311 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1314 i40e_add_tx_flow_control_drop_filter(pf);
1316 /* Set the max frame size to 0x2600 by default,
1317 * in case other drivers changed the default value.
1319 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1321 /* initialize mirror rule list */
1322 TAILQ_INIT(&pf->mirror_list);
1324 /* initialize Traffic Manager configuration */
1325 i40e_tm_conf_init(dev);
1327 /* Initialize customized information */
1328 i40e_init_customized_info(pf);
1330 ret = i40e_init_ethtype_filter_list(dev);
1332 goto err_init_ethtype_filter_list;
1333 ret = i40e_init_tunnel_filter_list(dev);
1335 goto err_init_tunnel_filter_list;
1336 ret = i40e_init_fdir_filter_list(dev);
1338 goto err_init_fdir_filter_list;
1342 err_init_fdir_filter_list:
1343 rte_free(pf->tunnel.hash_table);
1344 rte_free(pf->tunnel.hash_map);
1345 err_init_tunnel_filter_list:
1346 rte_free(pf->ethertype.hash_table);
1347 rte_free(pf->ethertype.hash_map);
1348 err_init_ethtype_filter_list:
1349 rte_free(dev->data->mac_addrs);
1351 i40e_vsi_release(pf->main_vsi);
1352 err_setup_pf_switch:
1354 err_configure_lan_hmc:
1355 (void)i40e_shutdown_lan_hmc(hw);
1357 i40e_res_pool_destroy(&pf->msix_pool);
1359 i40e_res_pool_destroy(&pf->qp_pool);
1362 err_get_capabilities:
1363 (void)i40e_shutdown_adminq(hw);
1369 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1371 struct i40e_ethertype_filter *p_ethertype;
1372 struct i40e_ethertype_rule *ethertype_rule;
1374 ethertype_rule = &pf->ethertype;
1375 /* Remove all ethertype filter rules and hash */
1376 if (ethertype_rule->hash_map)
1377 rte_free(ethertype_rule->hash_map);
1378 if (ethertype_rule->hash_table)
1379 rte_hash_free(ethertype_rule->hash_table);
1381 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1382 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1383 p_ethertype, rules);
1384 rte_free(p_ethertype);
1389 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1391 struct i40e_tunnel_filter *p_tunnel;
1392 struct i40e_tunnel_rule *tunnel_rule;
1394 tunnel_rule = &pf->tunnel;
1395 /* Remove all tunnel director rules and hash */
1396 if (tunnel_rule->hash_map)
1397 rte_free(tunnel_rule->hash_map);
1398 if (tunnel_rule->hash_table)
1399 rte_hash_free(tunnel_rule->hash_table);
1401 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1402 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1408 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1410 struct i40e_fdir_filter *p_fdir;
1411 struct i40e_fdir_info *fdir_info;
1413 fdir_info = &pf->fdir;
1414 /* Remove all flow director rules and hash */
1415 if (fdir_info->hash_map)
1416 rte_free(fdir_info->hash_map);
1417 if (fdir_info->hash_table)
1418 rte_hash_free(fdir_info->hash_table);
1420 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1421 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1427 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1430 struct rte_pci_device *pci_dev;
1431 struct rte_intr_handle *intr_handle;
1433 struct i40e_filter_control_settings settings;
1434 struct rte_flow *p_flow;
1436 uint8_t aq_fail = 0;
1438 PMD_INIT_FUNC_TRACE();
1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1443 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1446 intr_handle = &pci_dev->intr_handle;
1448 if (hw->adapter_stopped == 0)
1449 i40e_dev_close(dev);
1451 dev->dev_ops = NULL;
1452 dev->rx_pkt_burst = NULL;
1453 dev->tx_pkt_burst = NULL;
1455 /* Clear PXE mode */
1456 i40e_clear_pxe_mode(hw);
1458 /* Unconfigure filter control */
1459 memset(&settings, 0, sizeof(settings));
1460 ret = i40e_set_filter_control(hw, &settings);
1462 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1465 /* Disable flow control */
1466 hw->fc.requested_mode = I40E_FC_NONE;
1467 i40e_set_fc(hw, &aq_fail, TRUE);
1469 /* uninitialize pf host driver */
1470 i40e_pf_host_uninit(dev);
1472 rte_free(dev->data->mac_addrs);
1473 dev->data->mac_addrs = NULL;
1475 /* disable uio intr before callback unregister */
1476 rte_intr_disable(intr_handle);
1478 /* register callback func to eal lib */
1479 rte_intr_callback_unregister(intr_handle,
1480 i40e_dev_interrupt_handler, dev);
1482 i40e_rm_ethtype_filter_list(pf);
1483 i40e_rm_tunnel_filter_list(pf);
1484 i40e_rm_fdir_filter_list(pf);
1486 /* Remove all flows */
1487 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1488 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1492 /* Remove all Traffic Manager configuration */
1493 i40e_tm_conf_uninit(dev);
1499 i40e_dev_configure(struct rte_eth_dev *dev)
1501 struct i40e_adapter *ad =
1502 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1503 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1508 ret = i40e_dev_sync_phy_type(hw);
1512 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1513 * bulk allocation or vector Rx preconditions we will reset it.
1515 ad->rx_bulk_alloc_allowed = true;
1516 ad->rx_vec_allowed = true;
1517 ad->tx_simple_allowed = true;
1518 ad->tx_vec_allowed = true;
1520 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1521 ret = i40e_fdir_setup(pf);
1522 if (ret != I40E_SUCCESS) {
1523 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1526 ret = i40e_fdir_configure(dev);
1528 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1532 i40e_fdir_teardown(pf);
1534 ret = i40e_dev_init_vlan(dev);
1539 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1540 * RSS setting have different requirements.
1541 * General PMD driver call sequence are NIC init, configure,
1542 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1543 * will try to lookup the VSI that specific queue belongs to if VMDQ
1544 * applicable. So, VMDQ setting has to be done before
1545 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1546 * For RSS setting, it will try to calculate actual configured RX queue
1547 * number, which will be available after rx_queue_setup(). dev_start()
1548 * function is good to place RSS setup.
1550 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1551 ret = i40e_vmdq_setup(dev);
1556 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1557 ret = i40e_dcb_setup(dev);
1559 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1564 TAILQ_INIT(&pf->flow_list);
1569 /* need to release vmdq resource if exists */
1570 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1571 i40e_vsi_release(pf->vmdq[i].vsi);
1572 pf->vmdq[i].vsi = NULL;
1577 /* need to release fdir resource if exists */
1578 i40e_fdir_teardown(pf);
1583 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1585 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1586 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1589 uint16_t msix_vect = vsi->msix_intr;
1592 for (i = 0; i < vsi->nb_qps; i++) {
1593 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1594 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1598 if (vsi->type != I40E_VSI_SRIOV) {
1599 if (!rte_intr_allow_others(intr_handle)) {
1600 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1601 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1603 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1606 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1607 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1609 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1614 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1615 vsi->user_param + (msix_vect - 1);
1617 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1618 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1620 I40E_WRITE_FLUSH(hw);
1624 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1625 int base_queue, int nb_queue,
1630 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1632 /* Bind all RX queues to allocated MSIX interrupt */
1633 for (i = 0; i < nb_queue; i++) {
1634 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1635 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1636 ((base_queue + i + 1) <<
1637 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1638 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1639 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1641 if (i == nb_queue - 1)
1642 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1643 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1646 /* Write first RX queue to Link list register as the head element */
1647 if (vsi->type != I40E_VSI_SRIOV) {
1649 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1651 if (msix_vect == I40E_MISC_VEC_ID) {
1652 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1654 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1656 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1658 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1661 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1663 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1665 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1667 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1674 if (msix_vect == I40E_MISC_VEC_ID) {
1676 I40E_VPINT_LNKLST0(vsi->user_param),
1678 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1680 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1682 /* num_msix_vectors_vf needs to minus irq0 */
1683 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1684 vsi->user_param + (msix_vect - 1);
1686 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1688 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1690 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1694 I40E_WRITE_FLUSH(hw);
1698 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1700 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1701 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1702 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1703 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1704 uint16_t msix_vect = vsi->msix_intr;
1705 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1706 uint16_t queue_idx = 0;
1711 for (i = 0; i < vsi->nb_qps; i++) {
1712 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1713 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1716 /* INTENA flag is not auto-cleared for interrupt */
1717 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1718 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1719 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1720 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1721 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1723 /* VF bind interrupt */
1724 if (vsi->type == I40E_VSI_SRIOV) {
1725 __vsi_queues_bind_intr(vsi, msix_vect,
1726 vsi->base_queue, vsi->nb_qps,
1731 /* PF & VMDq bind interrupt */
1732 if (rte_intr_dp_is_en(intr_handle)) {
1733 if (vsi->type == I40E_VSI_MAIN) {
1736 } else if (vsi->type == I40E_VSI_VMDQ2) {
1737 struct i40e_vsi *main_vsi =
1738 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1739 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1744 for (i = 0; i < vsi->nb_used_qps; i++) {
1746 if (!rte_intr_allow_others(intr_handle))
1747 /* allow to share MISC_VEC_ID */
1748 msix_vect = I40E_MISC_VEC_ID;
1750 /* no enough msix_vect, map all to one */
1751 __vsi_queues_bind_intr(vsi, msix_vect,
1752 vsi->base_queue + i,
1753 vsi->nb_used_qps - i,
1755 for (; !!record && i < vsi->nb_used_qps; i++)
1756 intr_handle->intr_vec[queue_idx + i] =
1760 /* 1:1 queue/msix_vect mapping */
1761 __vsi_queues_bind_intr(vsi, msix_vect,
1762 vsi->base_queue + i, 1,
1765 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1773 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1775 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779 uint16_t interval = i40e_calc_itr_interval(\
1780 RTE_LIBRTE_I40E_ITR_INTERVAL);
1781 uint16_t msix_intr, i;
1783 if (rte_intr_allow_others(intr_handle))
1784 for (i = 0; i < vsi->nb_msix; i++) {
1785 msix_intr = vsi->msix_intr + i;
1786 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1787 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1788 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1789 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1791 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1794 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1795 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1796 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1797 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1799 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1801 I40E_WRITE_FLUSH(hw);
1805 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1807 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1808 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1809 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1810 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1811 uint16_t msix_intr, i;
1813 if (rte_intr_allow_others(intr_handle))
1814 for (i = 0; i < vsi->nb_msix; i++) {
1815 msix_intr = vsi->msix_intr + i;
1816 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1820 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1822 I40E_WRITE_FLUSH(hw);
1825 static inline uint8_t
1826 i40e_parse_link_speeds(uint16_t link_speeds)
1828 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1830 if (link_speeds & ETH_LINK_SPEED_40G)
1831 link_speed |= I40E_LINK_SPEED_40GB;
1832 if (link_speeds & ETH_LINK_SPEED_25G)
1833 link_speed |= I40E_LINK_SPEED_25GB;
1834 if (link_speeds & ETH_LINK_SPEED_20G)
1835 link_speed |= I40E_LINK_SPEED_20GB;
1836 if (link_speeds & ETH_LINK_SPEED_10G)
1837 link_speed |= I40E_LINK_SPEED_10GB;
1838 if (link_speeds & ETH_LINK_SPEED_1G)
1839 link_speed |= I40E_LINK_SPEED_1GB;
1840 if (link_speeds & ETH_LINK_SPEED_100M)
1841 link_speed |= I40E_LINK_SPEED_100MB;
1847 i40e_phy_conf_link(struct i40e_hw *hw,
1849 uint8_t force_speed,
1852 enum i40e_status_code status;
1853 struct i40e_aq_get_phy_abilities_resp phy_ab;
1854 struct i40e_aq_set_phy_config phy_conf;
1855 enum i40e_aq_phy_type cnt;
1856 uint32_t phy_type_mask = 0;
1858 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1859 I40E_AQ_PHY_FLAG_PAUSE_RX |
1860 I40E_AQ_PHY_FLAG_PAUSE_RX |
1861 I40E_AQ_PHY_FLAG_LOW_POWER;
1862 const uint8_t advt = I40E_LINK_SPEED_40GB |
1863 I40E_LINK_SPEED_25GB |
1864 I40E_LINK_SPEED_10GB |
1865 I40E_LINK_SPEED_1GB |
1866 I40E_LINK_SPEED_100MB;
1870 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1875 /* If link already up, no need to set up again */
1876 if (is_up && phy_ab.phy_type != 0)
1877 return I40E_SUCCESS;
1879 memset(&phy_conf, 0, sizeof(phy_conf));
1881 /* bits 0-2 use the values from get_phy_abilities_resp */
1883 abilities |= phy_ab.abilities & mask;
1885 /* update ablities and speed */
1886 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1887 phy_conf.link_speed = advt;
1889 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1891 phy_conf.abilities = abilities;
1895 /* To enable link, phy_type mask needs to include each type */
1896 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1897 phy_type_mask |= 1 << cnt;
1899 /* use get_phy_abilities_resp value for the rest */
1900 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1901 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1902 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1903 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1904 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1905 phy_conf.eee_capability = phy_ab.eee_capability;
1906 phy_conf.eeer = phy_ab.eeer_val;
1907 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1909 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1910 phy_ab.abilities, phy_ab.link_speed);
1911 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1912 phy_conf.abilities, phy_conf.link_speed);
1914 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1918 return I40E_SUCCESS;
1922 i40e_apply_link_speed(struct rte_eth_dev *dev)
1925 uint8_t abilities = 0;
1926 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927 struct rte_eth_conf *conf = &dev->data->dev_conf;
1929 speed = i40e_parse_link_speeds(conf->link_speeds);
1930 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1931 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1932 abilities |= I40E_AQ_PHY_AN_ENABLED;
1933 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1935 return i40e_phy_conf_link(hw, abilities, speed, true);
1939 i40e_dev_start(struct rte_eth_dev *dev)
1941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943 struct i40e_vsi *main_vsi = pf->main_vsi;
1945 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1946 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1947 uint32_t intr_vector = 0;
1948 struct i40e_vsi *vsi;
1950 hw->adapter_stopped = 0;
1952 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1954 "Invalid link_speeds for port %u, autonegotiation disabled",
1955 dev->data->port_id);
1959 rte_intr_disable(intr_handle);
1961 if ((rte_intr_cap_multiple(intr_handle) ||
1962 !RTE_ETH_DEV_SRIOV(dev).active) &&
1963 dev->data->dev_conf.intr_conf.rxq != 0) {
1964 intr_vector = dev->data->nb_rx_queues;
1965 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1970 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1971 intr_handle->intr_vec =
1972 rte_zmalloc("intr_vec",
1973 dev->data->nb_rx_queues * sizeof(int),
1975 if (!intr_handle->intr_vec) {
1977 "Failed to allocate %d rx_queues intr_vec",
1978 dev->data->nb_rx_queues);
1983 /* Initialize VSI */
1984 ret = i40e_dev_rxtx_init(pf);
1985 if (ret != I40E_SUCCESS) {
1986 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1990 /* Map queues with MSIX interrupt */
1991 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1992 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1993 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1994 i40e_vsi_enable_queues_intr(main_vsi);
1996 /* Map VMDQ VSI queues with MSIX interrupt */
1997 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1998 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1999 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2000 I40E_ITR_INDEX_DEFAULT);
2001 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2004 /* enable FDIR MSIX interrupt */
2005 if (pf->fdir.fdir_vsi) {
2006 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2007 I40E_ITR_INDEX_NONE);
2008 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2011 /* Enable all queues which have been configured */
2012 ret = i40e_dev_switch_queues(pf, TRUE);
2013 if (ret != I40E_SUCCESS) {
2014 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2018 /* Enable receiving broadcast packets */
2019 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2020 if (ret != I40E_SUCCESS)
2021 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2023 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2024 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2026 if (ret != I40E_SUCCESS)
2027 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2030 /* Enable the VLAN promiscuous mode. */
2032 for (i = 0; i < pf->vf_num; i++) {
2033 vsi = pf->vfs[i].vsi;
2034 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2039 /* Apply link configure */
2040 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2041 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2042 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2043 ETH_LINK_SPEED_40G)) {
2044 PMD_DRV_LOG(ERR, "Invalid link setting");
2047 ret = i40e_apply_link_speed(dev);
2048 if (I40E_SUCCESS != ret) {
2049 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2053 if (!rte_intr_allow_others(intr_handle)) {
2054 rte_intr_callback_unregister(intr_handle,
2055 i40e_dev_interrupt_handler,
2057 /* configure and enable device interrupt */
2058 i40e_pf_config_irq0(hw, FALSE);
2059 i40e_pf_enable_irq0(hw);
2061 if (dev->data->dev_conf.intr_conf.lsc != 0)
2063 "lsc won't enable because of no intr multiplex");
2065 ret = i40e_aq_set_phy_int_mask(hw,
2066 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2067 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2068 I40E_AQ_EVENT_MEDIA_NA), NULL);
2069 if (ret != I40E_SUCCESS)
2070 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2072 /* Call get_link_info aq commond to enable/disable LSE */
2073 i40e_dev_link_update(dev, 0);
2076 /* enable uio intr after callback register */
2077 rte_intr_enable(intr_handle);
2079 i40e_filter_restore(pf);
2081 if (pf->tm_conf.root && !pf->tm_conf.committed)
2082 PMD_DRV_LOG(WARNING,
2083 "please call hierarchy_commit() "
2084 "before starting the port");
2086 return I40E_SUCCESS;
2089 i40e_dev_switch_queues(pf, FALSE);
2090 i40e_dev_clear_queues(dev);
2096 i40e_dev_stop(struct rte_eth_dev *dev)
2098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct i40e_vsi *main_vsi = pf->main_vsi;
2101 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2102 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2105 if (hw->adapter_stopped == 1)
2107 /* Disable all queues */
2108 i40e_dev_switch_queues(pf, FALSE);
2110 /* un-map queues with interrupt registers */
2111 i40e_vsi_disable_queues_intr(main_vsi);
2112 i40e_vsi_queues_unbind_intr(main_vsi);
2114 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2115 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2116 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2119 if (pf->fdir.fdir_vsi) {
2120 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2121 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2123 /* Clear all queues and release memory */
2124 i40e_dev_clear_queues(dev);
2127 i40e_dev_set_link_down(dev);
2129 if (!rte_intr_allow_others(intr_handle))
2130 /* resume to the default handler */
2131 rte_intr_callback_register(intr_handle,
2132 i40e_dev_interrupt_handler,
2135 /* Clean datapath event and queue/vec mapping */
2136 rte_intr_efd_disable(intr_handle);
2137 if (intr_handle->intr_vec) {
2138 rte_free(intr_handle->intr_vec);
2139 intr_handle->intr_vec = NULL;
2142 /* reset hierarchy commit */
2143 pf->tm_conf.committed = false;
2145 hw->adapter_stopped = 1;
2149 i40e_dev_close(struct rte_eth_dev *dev)
2151 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2154 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2155 struct i40e_mirror_rule *p_mirror;
2160 PMD_INIT_FUNC_TRACE();
2164 /* Remove all mirror rules */
2165 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2166 ret = i40e_aq_del_mirror_rule(hw,
2167 pf->main_vsi->veb->seid,
2168 p_mirror->rule_type,
2170 p_mirror->num_entries,
2173 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2174 "status = %d, aq_err = %d.", ret,
2175 hw->aq.asq_last_status);
2177 /* remove mirror software resource anyway */
2178 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2180 pf->nb_mirror_rule--;
2183 i40e_dev_free_queues(dev);
2185 /* Disable interrupt */
2186 i40e_pf_disable_irq0(hw);
2187 rte_intr_disable(intr_handle);
2189 /* shutdown and destroy the HMC */
2190 i40e_shutdown_lan_hmc(hw);
2192 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2193 i40e_vsi_release(pf->vmdq[i].vsi);
2194 pf->vmdq[i].vsi = NULL;
2199 /* release all the existing VSIs and VEBs */
2200 i40e_fdir_teardown(pf);
2201 i40e_vsi_release(pf->main_vsi);
2203 /* shutdown the adminq */
2204 i40e_aq_queue_shutdown(hw, true);
2205 i40e_shutdown_adminq(hw);
2207 i40e_res_pool_destroy(&pf->qp_pool);
2208 i40e_res_pool_destroy(&pf->msix_pool);
2210 /* force a PF reset to clean anything leftover */
2211 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2212 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2213 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2214 I40E_WRITE_FLUSH(hw);
2218 * Reset PF device only to re-initialize resources in PMD layer
2221 i40e_dev_reset(struct rte_eth_dev *dev)
2225 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2226 * its VF to make them align with it. The detailed notification
2227 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2228 * To avoid unexpected behavior in VF, currently reset of PF with
2229 * SR-IOV activation is not supported. It might be supported later.
2231 if (dev->data->sriov.active)
2234 ret = eth_i40e_dev_uninit(dev);
2238 ret = eth_i40e_dev_init(dev);
2244 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2246 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2247 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248 struct i40e_vsi *vsi = pf->main_vsi;
2251 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2253 if (status != I40E_SUCCESS)
2254 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2256 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2258 if (status != I40E_SUCCESS)
2259 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2264 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2268 struct i40e_vsi *vsi = pf->main_vsi;
2271 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2273 if (status != I40E_SUCCESS)
2274 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2276 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2278 if (status != I40E_SUCCESS)
2279 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2283 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2285 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2286 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287 struct i40e_vsi *vsi = pf->main_vsi;
2290 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2291 if (ret != I40E_SUCCESS)
2292 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2296 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2298 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2299 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300 struct i40e_vsi *vsi = pf->main_vsi;
2303 if (dev->data->promiscuous == 1)
2304 return; /* must remain in all_multicast mode */
2306 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2307 vsi->seid, FALSE, NULL);
2308 if (ret != I40E_SUCCESS)
2309 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2313 * Set device link up.
2316 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2318 /* re-apply link speed setting */
2319 return i40e_apply_link_speed(dev);
2323 * Set device link down.
2326 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2328 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2329 uint8_t abilities = 0;
2330 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2332 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2333 return i40e_phy_conf_link(hw, abilities, speed, false);
2337 i40e_dev_link_update(struct rte_eth_dev *dev,
2338 int wait_to_complete)
2340 #define CHECK_INTERVAL 100 /* 100ms */
2341 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343 struct i40e_link_status link_status;
2344 struct rte_eth_link link, old;
2346 unsigned rep_cnt = MAX_REPEAT_TIME;
2347 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2349 memset(&link, 0, sizeof(link));
2350 memset(&old, 0, sizeof(old));
2351 memset(&link_status, 0, sizeof(link_status));
2352 rte_i40e_dev_atomic_read_link_status(dev, &old);
2355 /* Get link status information from hardware */
2356 status = i40e_aq_get_link_info(hw, enable_lse,
2357 &link_status, NULL);
2358 if (status != I40E_SUCCESS) {
2359 link.link_speed = ETH_SPEED_NUM_100M;
2360 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2361 PMD_DRV_LOG(ERR, "Failed to get link info");
2365 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2366 if (!wait_to_complete || link.link_status)
2369 rte_delay_ms(CHECK_INTERVAL);
2370 } while (--rep_cnt);
2372 if (!link.link_status)
2375 /* i40e uses full duplex only */
2376 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2378 /* Parse the link status */
2379 switch (link_status.link_speed) {
2380 case I40E_LINK_SPEED_100MB:
2381 link.link_speed = ETH_SPEED_NUM_100M;
2383 case I40E_LINK_SPEED_1GB:
2384 link.link_speed = ETH_SPEED_NUM_1G;
2386 case I40E_LINK_SPEED_10GB:
2387 link.link_speed = ETH_SPEED_NUM_10G;
2389 case I40E_LINK_SPEED_20GB:
2390 link.link_speed = ETH_SPEED_NUM_20G;
2392 case I40E_LINK_SPEED_25GB:
2393 link.link_speed = ETH_SPEED_NUM_25G;
2395 case I40E_LINK_SPEED_40GB:
2396 link.link_speed = ETH_SPEED_NUM_40G;
2399 link.link_speed = ETH_SPEED_NUM_100M;
2403 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2404 ETH_LINK_SPEED_FIXED);
2407 rte_i40e_dev_atomic_write_link_status(dev, &link);
2408 if (link.link_status == old.link_status)
2411 i40e_notify_all_vfs_link_status(dev);
2416 /* Get all the statistics of a VSI */
2418 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2420 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2421 struct i40e_eth_stats *nes = &vsi->eth_stats;
2422 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2423 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2425 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2426 vsi->offset_loaded, &oes->rx_bytes,
2428 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2429 vsi->offset_loaded, &oes->rx_unicast,
2431 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2432 vsi->offset_loaded, &oes->rx_multicast,
2433 &nes->rx_multicast);
2434 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2435 vsi->offset_loaded, &oes->rx_broadcast,
2436 &nes->rx_broadcast);
2437 /* exclude CRC bytes */
2438 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2439 nes->rx_broadcast) * ETHER_CRC_LEN;
2441 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2442 &oes->rx_discards, &nes->rx_discards);
2443 /* GLV_REPC not supported */
2444 /* GLV_RMPC not supported */
2445 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2446 &oes->rx_unknown_protocol,
2447 &nes->rx_unknown_protocol);
2448 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2449 vsi->offset_loaded, &oes->tx_bytes,
2451 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2452 vsi->offset_loaded, &oes->tx_unicast,
2454 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2455 vsi->offset_loaded, &oes->tx_multicast,
2456 &nes->tx_multicast);
2457 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2458 vsi->offset_loaded, &oes->tx_broadcast,
2459 &nes->tx_broadcast);
2460 /* GLV_TDPC not supported */
2461 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2462 &oes->tx_errors, &nes->tx_errors);
2463 vsi->offset_loaded = true;
2465 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2467 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2468 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2469 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2470 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2471 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2472 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2473 nes->rx_unknown_protocol);
2474 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2475 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2476 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2477 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2478 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2479 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2480 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2485 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2488 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2489 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2491 /* Get rx/tx bytes of internal transfer packets */
2492 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2493 I40E_GLV_GORCL(hw->port),
2495 &pf->internal_stats_offset.rx_bytes,
2496 &pf->internal_stats.rx_bytes);
2498 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2499 I40E_GLV_GOTCL(hw->port),
2501 &pf->internal_stats_offset.tx_bytes,
2502 &pf->internal_stats.tx_bytes);
2503 /* Get total internal rx packet count */
2504 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2505 I40E_GLV_UPRCL(hw->port),
2507 &pf->internal_stats_offset.rx_unicast,
2508 &pf->internal_stats.rx_unicast);
2509 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2510 I40E_GLV_MPRCL(hw->port),
2512 &pf->internal_stats_offset.rx_multicast,
2513 &pf->internal_stats.rx_multicast);
2514 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2515 I40E_GLV_BPRCL(hw->port),
2517 &pf->internal_stats_offset.rx_broadcast,
2518 &pf->internal_stats.rx_broadcast);
2520 /* exclude CRC size */
2521 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2522 pf->internal_stats.rx_multicast +
2523 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2525 /* Get statistics of struct i40e_eth_stats */
2526 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2527 I40E_GLPRT_GORCL(hw->port),
2528 pf->offset_loaded, &os->eth.rx_bytes,
2530 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2531 I40E_GLPRT_UPRCL(hw->port),
2532 pf->offset_loaded, &os->eth.rx_unicast,
2533 &ns->eth.rx_unicast);
2534 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2535 I40E_GLPRT_MPRCL(hw->port),
2536 pf->offset_loaded, &os->eth.rx_multicast,
2537 &ns->eth.rx_multicast);
2538 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2539 I40E_GLPRT_BPRCL(hw->port),
2540 pf->offset_loaded, &os->eth.rx_broadcast,
2541 &ns->eth.rx_broadcast);
2542 /* Workaround: CRC size should not be included in byte statistics,
2543 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2545 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2546 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2548 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2549 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2552 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2553 ns->eth.rx_bytes = 0;
2554 /* exlude internal rx bytes */
2556 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2558 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2559 pf->offset_loaded, &os->eth.rx_discards,
2560 &ns->eth.rx_discards);
2561 /* GLPRT_REPC not supported */
2562 /* GLPRT_RMPC not supported */
2563 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2565 &os->eth.rx_unknown_protocol,
2566 &ns->eth.rx_unknown_protocol);
2567 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2568 I40E_GLPRT_GOTCL(hw->port),
2569 pf->offset_loaded, &os->eth.tx_bytes,
2571 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2572 I40E_GLPRT_UPTCL(hw->port),
2573 pf->offset_loaded, &os->eth.tx_unicast,
2574 &ns->eth.tx_unicast);
2575 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2576 I40E_GLPRT_MPTCL(hw->port),
2577 pf->offset_loaded, &os->eth.tx_multicast,
2578 &ns->eth.tx_multicast);
2579 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2580 I40E_GLPRT_BPTCL(hw->port),
2581 pf->offset_loaded, &os->eth.tx_broadcast,
2582 &ns->eth.tx_broadcast);
2583 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2584 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2586 /* exclude internal tx bytes */
2587 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2588 ns->eth.tx_bytes = 0;
2590 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2592 /* GLPRT_TEPC not supported */
2594 /* additional port specific stats */
2595 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2596 pf->offset_loaded, &os->tx_dropped_link_down,
2597 &ns->tx_dropped_link_down);
2598 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2599 pf->offset_loaded, &os->crc_errors,
2601 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2602 pf->offset_loaded, &os->illegal_bytes,
2603 &ns->illegal_bytes);
2604 /* GLPRT_ERRBC not supported */
2605 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2606 pf->offset_loaded, &os->mac_local_faults,
2607 &ns->mac_local_faults);
2608 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2609 pf->offset_loaded, &os->mac_remote_faults,
2610 &ns->mac_remote_faults);
2611 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2612 pf->offset_loaded, &os->rx_length_errors,
2613 &ns->rx_length_errors);
2614 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2615 pf->offset_loaded, &os->link_xon_rx,
2617 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2618 pf->offset_loaded, &os->link_xoff_rx,
2620 for (i = 0; i < 8; i++) {
2621 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2623 &os->priority_xon_rx[i],
2624 &ns->priority_xon_rx[i]);
2625 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2627 &os->priority_xoff_rx[i],
2628 &ns->priority_xoff_rx[i]);
2630 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2631 pf->offset_loaded, &os->link_xon_tx,
2633 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2634 pf->offset_loaded, &os->link_xoff_tx,
2636 for (i = 0; i < 8; i++) {
2637 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2639 &os->priority_xon_tx[i],
2640 &ns->priority_xon_tx[i]);
2641 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2643 &os->priority_xoff_tx[i],
2644 &ns->priority_xoff_tx[i]);
2645 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2647 &os->priority_xon_2_xoff[i],
2648 &ns->priority_xon_2_xoff[i]);
2650 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2651 I40E_GLPRT_PRC64L(hw->port),
2652 pf->offset_loaded, &os->rx_size_64,
2654 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2655 I40E_GLPRT_PRC127L(hw->port),
2656 pf->offset_loaded, &os->rx_size_127,
2658 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2659 I40E_GLPRT_PRC255L(hw->port),
2660 pf->offset_loaded, &os->rx_size_255,
2662 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2663 I40E_GLPRT_PRC511L(hw->port),
2664 pf->offset_loaded, &os->rx_size_511,
2666 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2667 I40E_GLPRT_PRC1023L(hw->port),
2668 pf->offset_loaded, &os->rx_size_1023,
2670 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2671 I40E_GLPRT_PRC1522L(hw->port),
2672 pf->offset_loaded, &os->rx_size_1522,
2674 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2675 I40E_GLPRT_PRC9522L(hw->port),
2676 pf->offset_loaded, &os->rx_size_big,
2678 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2679 pf->offset_loaded, &os->rx_undersize,
2681 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2682 pf->offset_loaded, &os->rx_fragments,
2684 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2685 pf->offset_loaded, &os->rx_oversize,
2687 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2688 pf->offset_loaded, &os->rx_jabber,
2690 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2691 I40E_GLPRT_PTC64L(hw->port),
2692 pf->offset_loaded, &os->tx_size_64,
2694 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2695 I40E_GLPRT_PTC127L(hw->port),
2696 pf->offset_loaded, &os->tx_size_127,
2698 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2699 I40E_GLPRT_PTC255L(hw->port),
2700 pf->offset_loaded, &os->tx_size_255,
2702 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2703 I40E_GLPRT_PTC511L(hw->port),
2704 pf->offset_loaded, &os->tx_size_511,
2706 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2707 I40E_GLPRT_PTC1023L(hw->port),
2708 pf->offset_loaded, &os->tx_size_1023,
2710 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2711 I40E_GLPRT_PTC1522L(hw->port),
2712 pf->offset_loaded, &os->tx_size_1522,
2714 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2715 I40E_GLPRT_PTC9522L(hw->port),
2716 pf->offset_loaded, &os->tx_size_big,
2718 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2720 &os->fd_sb_match, &ns->fd_sb_match);
2721 /* GLPRT_MSPDC not supported */
2722 /* GLPRT_XEC not supported */
2724 pf->offset_loaded = true;
2727 i40e_update_vsi_stats(pf->main_vsi);
2730 /* Get all statistics of a port */
2732 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2734 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2735 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2739 /* call read registers - updates values, now write them to struct */
2740 i40e_read_stats_registers(pf, hw);
2742 stats->ipackets = ns->eth.rx_unicast +
2743 ns->eth.rx_multicast +
2744 ns->eth.rx_broadcast -
2745 ns->eth.rx_discards -
2746 pf->main_vsi->eth_stats.rx_discards;
2747 stats->opackets = ns->eth.tx_unicast +
2748 ns->eth.tx_multicast +
2749 ns->eth.tx_broadcast;
2750 stats->ibytes = ns->eth.rx_bytes;
2751 stats->obytes = ns->eth.tx_bytes;
2752 stats->oerrors = ns->eth.tx_errors +
2753 pf->main_vsi->eth_stats.tx_errors;
2756 stats->imissed = ns->eth.rx_discards +
2757 pf->main_vsi->eth_stats.rx_discards;
2758 stats->ierrors = ns->crc_errors +
2759 ns->rx_length_errors + ns->rx_undersize +
2760 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2762 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2763 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2764 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2765 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2766 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2767 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2768 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2769 ns->eth.rx_unknown_protocol);
2770 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2771 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2772 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2773 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2774 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2775 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2777 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2778 ns->tx_dropped_link_down);
2779 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2780 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2782 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2783 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2784 ns->mac_local_faults);
2785 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2786 ns->mac_remote_faults);
2787 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2788 ns->rx_length_errors);
2789 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2790 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2791 for (i = 0; i < 8; i++) {
2792 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2793 i, ns->priority_xon_rx[i]);
2794 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2795 i, ns->priority_xoff_rx[i]);
2797 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2798 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2799 for (i = 0; i < 8; i++) {
2800 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2801 i, ns->priority_xon_tx[i]);
2802 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2803 i, ns->priority_xoff_tx[i]);
2804 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2805 i, ns->priority_xon_2_xoff[i]);
2807 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2808 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2809 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2810 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2811 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2812 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2813 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2814 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2815 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2816 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2817 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2818 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2819 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2820 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2821 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2822 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2823 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2824 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2825 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2826 ns->mac_short_packet_dropped);
2827 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2828 ns->checksum_error);
2829 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2830 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2833 /* Reset the statistics */
2835 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2837 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2838 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840 /* Mark PF and VSI stats to update the offset, aka "reset" */
2841 pf->offset_loaded = false;
2843 pf->main_vsi->offset_loaded = false;
2845 /* read the stats, reading current register values into offset */
2846 i40e_read_stats_registers(pf, hw);
2850 i40e_xstats_calc_num(void)
2852 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2853 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2854 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2857 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2858 struct rte_eth_xstat_name *xstats_names,
2859 __rte_unused unsigned limit)
2864 if (xstats_names == NULL)
2865 return i40e_xstats_calc_num();
2867 /* Note: limit checked in rte_eth_xstats_names() */
2869 /* Get stats from i40e_eth_stats struct */
2870 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2871 snprintf(xstats_names[count].name,
2872 sizeof(xstats_names[count].name),
2873 "%s", rte_i40e_stats_strings[i].name);
2877 /* Get individiual stats from i40e_hw_port struct */
2878 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2879 snprintf(xstats_names[count].name,
2880 sizeof(xstats_names[count].name),
2881 "%s", rte_i40e_hw_port_strings[i].name);
2885 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2886 for (prio = 0; prio < 8; prio++) {
2887 snprintf(xstats_names[count].name,
2888 sizeof(xstats_names[count].name),
2889 "rx_priority%u_%s", prio,
2890 rte_i40e_rxq_prio_strings[i].name);
2895 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2896 for (prio = 0; prio < 8; prio++) {
2897 snprintf(xstats_names[count].name,
2898 sizeof(xstats_names[count].name),
2899 "tx_priority%u_%s", prio,
2900 rte_i40e_txq_prio_strings[i].name);
2908 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913 unsigned i, count, prio;
2914 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2916 count = i40e_xstats_calc_num();
2920 i40e_read_stats_registers(pf, hw);
2927 /* Get stats from i40e_eth_stats struct */
2928 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2929 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2930 rte_i40e_stats_strings[i].offset);
2931 xstats[count].id = count;
2935 /* Get individiual stats from i40e_hw_port struct */
2936 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2937 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2938 rte_i40e_hw_port_strings[i].offset);
2939 xstats[count].id = count;
2943 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2944 for (prio = 0; prio < 8; prio++) {
2945 xstats[count].value =
2946 *(uint64_t *)(((char *)hw_stats) +
2947 rte_i40e_rxq_prio_strings[i].offset +
2948 (sizeof(uint64_t) * prio));
2949 xstats[count].id = count;
2954 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2955 for (prio = 0; prio < 8; prio++) {
2956 xstats[count].value =
2957 *(uint64_t *)(((char *)hw_stats) +
2958 rte_i40e_txq_prio_strings[i].offset +
2959 (sizeof(uint64_t) * prio));
2960 xstats[count].id = count;
2969 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2970 __rte_unused uint16_t queue_id,
2971 __rte_unused uint8_t stat_idx,
2972 __rte_unused uint8_t is_rx)
2974 PMD_INIT_FUNC_TRACE();
2980 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2982 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988 full_ver = hw->nvm.oem_ver;
2989 ver = (u8)(full_ver >> 24);
2990 build = (u16)((full_ver >> 8) & 0xffff);
2991 patch = (u8)(full_ver & 0xff);
2993 ret = snprintf(fw_version, fw_size,
2994 "%d.%d%d 0x%08x %d.%d.%d",
2995 ((hw->nvm.version >> 12) & 0xf),
2996 ((hw->nvm.version >> 4) & 0xff),
2997 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3000 ret += 1; /* add the size of '\0' */
3001 if (fw_size < (u32)ret)
3008 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3010 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3011 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3012 struct i40e_vsi *vsi = pf->main_vsi;
3013 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3015 dev_info->pci_dev = pci_dev;
3016 dev_info->max_rx_queues = vsi->nb_qps;
3017 dev_info->max_tx_queues = vsi->nb_qps;
3018 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3019 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3020 dev_info->max_mac_addrs = vsi->max_macaddrs;
3021 dev_info->max_vfs = pci_dev->max_vfs;
3022 dev_info->rx_offload_capa =
3023 DEV_RX_OFFLOAD_VLAN_STRIP |
3024 DEV_RX_OFFLOAD_QINQ_STRIP |
3025 DEV_RX_OFFLOAD_IPV4_CKSUM |
3026 DEV_RX_OFFLOAD_UDP_CKSUM |
3027 DEV_RX_OFFLOAD_TCP_CKSUM;
3028 dev_info->tx_offload_capa =
3029 DEV_TX_OFFLOAD_VLAN_INSERT |
3030 DEV_TX_OFFLOAD_QINQ_INSERT |
3031 DEV_TX_OFFLOAD_IPV4_CKSUM |
3032 DEV_TX_OFFLOAD_UDP_CKSUM |
3033 DEV_TX_OFFLOAD_TCP_CKSUM |
3034 DEV_TX_OFFLOAD_SCTP_CKSUM |
3035 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3036 DEV_TX_OFFLOAD_TCP_TSO |
3037 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3038 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3039 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3040 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3041 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3043 dev_info->reta_size = pf->hash_lut_size;
3044 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3046 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3048 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3049 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3050 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3052 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3056 dev_info->default_txconf = (struct rte_eth_txconf) {
3058 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3059 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3060 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3062 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3063 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3064 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3065 ETH_TXQ_FLAGS_NOOFFLOADS,
3068 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3069 .nb_max = I40E_MAX_RING_DESC,
3070 .nb_min = I40E_MIN_RING_DESC,
3071 .nb_align = I40E_ALIGN_RING_DESC,
3074 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3075 .nb_max = I40E_MAX_RING_DESC,
3076 .nb_min = I40E_MIN_RING_DESC,
3077 .nb_align = I40E_ALIGN_RING_DESC,
3078 .nb_seg_max = I40E_TX_MAX_SEG,
3079 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3082 if (pf->flags & I40E_FLAG_VMDQ) {
3083 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3084 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3085 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3086 pf->max_nb_vmdq_vsi;
3087 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3088 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3089 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3092 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3094 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3095 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3097 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3100 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3104 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3106 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3107 struct i40e_vsi *vsi = pf->main_vsi;
3108 PMD_INIT_FUNC_TRACE();
3111 return i40e_vsi_add_vlan(vsi, vlan_id);
3113 return i40e_vsi_delete_vlan(vsi, vlan_id);
3117 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3118 enum rte_vlan_type vlan_type,
3119 uint16_t tpid, int qinq)
3121 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124 uint16_t reg_id = 3;
3128 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3132 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3134 if (ret != I40E_SUCCESS) {
3136 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3141 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3144 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3145 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3146 if (reg_r == reg_w) {
3147 PMD_DRV_LOG(DEBUG, "No need to write");
3151 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3153 if (ret != I40E_SUCCESS) {
3155 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3160 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3167 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3168 enum rte_vlan_type vlan_type,
3171 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3172 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3175 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3176 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3177 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3179 "Unsupported vlan type.");
3182 /* 802.1ad frames ability is added in NVM API 1.7*/
3183 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3185 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3186 hw->first_tag = rte_cpu_to_le_16(tpid);
3187 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3188 hw->second_tag = rte_cpu_to_le_16(tpid);
3190 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3191 hw->second_tag = rte_cpu_to_le_16(tpid);
3193 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3194 if (ret != I40E_SUCCESS) {
3196 "Set switch config failed aq_err: %d",
3197 hw->aq.asq_last_status);
3201 /* If NVM API < 1.7, keep the register setting */
3202 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3209 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3211 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3212 struct i40e_vsi *vsi = pf->main_vsi;
3214 if (mask & ETH_VLAN_FILTER_MASK) {
3215 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3216 i40e_vsi_config_vlan_filter(vsi, TRUE);
3218 i40e_vsi_config_vlan_filter(vsi, FALSE);
3221 if (mask & ETH_VLAN_STRIP_MASK) {
3222 /* Enable or disable VLAN stripping */
3223 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3224 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3226 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3229 if (mask & ETH_VLAN_EXTEND_MASK) {
3230 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3231 i40e_vsi_config_double_vlan(vsi, TRUE);
3232 /* Set global registers with default ethertype. */
3233 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3235 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3239 i40e_vsi_config_double_vlan(vsi, FALSE);
3244 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3245 __rte_unused uint16_t queue,
3246 __rte_unused int on)
3248 PMD_INIT_FUNC_TRACE();
3252 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3254 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3255 struct i40e_vsi *vsi = pf->main_vsi;
3256 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3257 struct i40e_vsi_vlan_pvid_info info;
3259 memset(&info, 0, sizeof(info));
3262 info.config.pvid = pvid;
3264 info.config.reject.tagged =
3265 data->dev_conf.txmode.hw_vlan_reject_tagged;
3266 info.config.reject.untagged =
3267 data->dev_conf.txmode.hw_vlan_reject_untagged;
3270 return i40e_vsi_vlan_pvid_set(vsi, &info);
3274 i40e_dev_led_on(struct rte_eth_dev *dev)
3276 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3277 uint32_t mode = i40e_led_get(hw);
3280 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3286 i40e_dev_led_off(struct rte_eth_dev *dev)
3288 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289 uint32_t mode = i40e_led_get(hw);
3292 i40e_led_set(hw, 0, false);
3298 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3300 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3303 fc_conf->pause_time = pf->fc_conf.pause_time;
3305 /* read out from register, in case they are modified by other port */
3306 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3307 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3308 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3309 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3311 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3312 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3314 /* Return current mode according to actual setting*/
3315 switch (hw->fc.current_mode) {
3317 fc_conf->mode = RTE_FC_FULL;
3319 case I40E_FC_TX_PAUSE:
3320 fc_conf->mode = RTE_FC_TX_PAUSE;
3322 case I40E_FC_RX_PAUSE:
3323 fc_conf->mode = RTE_FC_RX_PAUSE;
3327 fc_conf->mode = RTE_FC_NONE;
3334 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3336 uint32_t mflcn_reg, fctrl_reg, reg;
3337 uint32_t max_high_water;
3338 uint8_t i, aq_failure;
3342 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3343 [RTE_FC_NONE] = I40E_FC_NONE,
3344 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3345 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3346 [RTE_FC_FULL] = I40E_FC_FULL
3349 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3351 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3352 if ((fc_conf->high_water > max_high_water) ||
3353 (fc_conf->high_water < fc_conf->low_water)) {
3355 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3360 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3362 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3364 pf->fc_conf.pause_time = fc_conf->pause_time;
3365 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3366 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3368 PMD_INIT_FUNC_TRACE();
3370 /* All the link flow control related enable/disable register
3371 * configuration is handle by the F/W
3373 err = i40e_set_fc(hw, &aq_failure, true);
3377 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3378 /* Configure flow control refresh threshold,
3379 * the value for stat_tx_pause_refresh_timer[8]
3380 * is used for global pause operation.
3384 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3385 pf->fc_conf.pause_time);
3387 /* configure the timer value included in transmitted pause
3389 * the value for stat_tx_pause_quanta[8] is used for global
3392 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3393 pf->fc_conf.pause_time);
3395 fctrl_reg = I40E_READ_REG(hw,
3396 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3398 if (fc_conf->mac_ctrl_frame_fwd != 0)
3399 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3401 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3403 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3406 /* Configure pause time (2 TCs per register) */
3407 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3408 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3409 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3411 /* Configure flow control refresh threshold value */
3412 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3413 pf->fc_conf.pause_time / 2);
3415 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3417 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3418 *depending on configuration
3420 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3421 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3422 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3424 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3425 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3428 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3431 /* config the water marker both based on the packets and bytes */
3432 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3433 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3434 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3435 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3436 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3437 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3438 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3439 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3441 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3442 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3445 I40E_WRITE_FLUSH(hw);
3451 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3452 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3454 PMD_INIT_FUNC_TRACE();
3459 /* Add a MAC address, and update filters */
3461 i40e_macaddr_add(struct rte_eth_dev *dev,
3462 struct ether_addr *mac_addr,
3463 __rte_unused uint32_t index,
3466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3467 struct i40e_mac_filter_info mac_filter;
3468 struct i40e_vsi *vsi;
3471 /* If VMDQ not enabled or configured, return */
3472 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3473 !pf->nb_cfg_vmdq_vsi)) {
3474 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3475 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3480 if (pool > pf->nb_cfg_vmdq_vsi) {
3481 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3482 pool, pf->nb_cfg_vmdq_vsi);
3486 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3487 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3488 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3490 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3495 vsi = pf->vmdq[pool - 1].vsi;
3497 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3498 if (ret != I40E_SUCCESS) {
3499 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3505 /* Remove a MAC address, and update filters */
3507 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3509 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3510 struct i40e_vsi *vsi;
3511 struct rte_eth_dev_data *data = dev->data;
3512 struct ether_addr *macaddr;
3517 macaddr = &(data->mac_addrs[index]);
3519 pool_sel = dev->data->mac_pool_sel[index];
3521 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3522 if (pool_sel & (1ULL << i)) {
3526 /* No VMDQ pool enabled or configured */
3527 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3528 (i > pf->nb_cfg_vmdq_vsi)) {
3530 "No VMDQ pool enabled/configured");
3533 vsi = pf->vmdq[i - 1].vsi;
3535 ret = i40e_vsi_delete_mac(vsi, macaddr);
3538 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3545 /* Set perfect match or hash match of MAC and VLAN for a VF */
3547 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3548 struct rte_eth_mac_filter *filter,
3552 struct i40e_mac_filter_info mac_filter;
3553 struct ether_addr old_mac;
3554 struct ether_addr *new_mac;
3555 struct i40e_pf_vf *vf = NULL;
3560 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3563 hw = I40E_PF_TO_HW(pf);
3565 if (filter == NULL) {
3566 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3570 new_mac = &filter->mac_addr;
3572 if (is_zero_ether_addr(new_mac)) {
3573 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3577 vf_id = filter->dst_id;
3579 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3580 PMD_DRV_LOG(ERR, "Invalid argument.");
3583 vf = &pf->vfs[vf_id];
3585 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3586 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3591 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3592 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3594 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3597 mac_filter.filter_type = filter->filter_type;
3598 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3599 if (ret != I40E_SUCCESS) {
3600 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3603 ether_addr_copy(new_mac, &pf->dev_addr);
3605 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3607 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3608 if (ret != I40E_SUCCESS) {
3609 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3613 /* Clear device address as it has been removed */
3614 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3615 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3621 /* MAC filter handle */
3623 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3626 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3627 struct rte_eth_mac_filter *filter;
3628 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3629 int ret = I40E_NOT_SUPPORTED;
3631 filter = (struct rte_eth_mac_filter *)(arg);
3633 switch (filter_op) {
3634 case RTE_ETH_FILTER_NOP:
3637 case RTE_ETH_FILTER_ADD:
3638 i40e_pf_disable_irq0(hw);
3640 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3641 i40e_pf_enable_irq0(hw);
3643 case RTE_ETH_FILTER_DELETE:
3644 i40e_pf_disable_irq0(hw);
3646 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3647 i40e_pf_enable_irq0(hw);
3650 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3651 ret = I40E_ERR_PARAM;
3659 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3661 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3662 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3668 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3669 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3672 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3676 uint32_t *lut_dw = (uint32_t *)lut;
3677 uint16_t i, lut_size_dw = lut_size / 4;
3679 for (i = 0; i < lut_size_dw; i++)
3680 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3687 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3696 pf = I40E_VSI_TO_PF(vsi);
3697 hw = I40E_VSI_TO_HW(vsi);
3699 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3700 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3703 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3707 uint32_t *lut_dw = (uint32_t *)lut;
3708 uint16_t i, lut_size_dw = lut_size / 4;
3710 for (i = 0; i < lut_size_dw; i++)
3711 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3712 I40E_WRITE_FLUSH(hw);
3719 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3720 struct rte_eth_rss_reta_entry64 *reta_conf,
3723 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3724 uint16_t i, lut_size = pf->hash_lut_size;
3725 uint16_t idx, shift;
3729 if (reta_size != lut_size ||
3730 reta_size > ETH_RSS_RETA_SIZE_512) {
3732 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3733 reta_size, lut_size);
3737 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3739 PMD_DRV_LOG(ERR, "No memory can be allocated");
3742 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3745 for (i = 0; i < reta_size; i++) {
3746 idx = i / RTE_RETA_GROUP_SIZE;
3747 shift = i % RTE_RETA_GROUP_SIZE;
3748 if (reta_conf[idx].mask & (1ULL << shift))
3749 lut[i] = reta_conf[idx].reta[shift];
3751 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3760 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3761 struct rte_eth_rss_reta_entry64 *reta_conf,
3764 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3765 uint16_t i, lut_size = pf->hash_lut_size;
3766 uint16_t idx, shift;
3770 if (reta_size != lut_size ||
3771 reta_size > ETH_RSS_RETA_SIZE_512) {
3773 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3774 reta_size, lut_size);
3778 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3780 PMD_DRV_LOG(ERR, "No memory can be allocated");
3784 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3787 for (i = 0; i < reta_size; i++) {
3788 idx = i / RTE_RETA_GROUP_SIZE;
3789 shift = i % RTE_RETA_GROUP_SIZE;
3790 if (reta_conf[idx].mask & (1ULL << shift))
3791 reta_conf[idx].reta[shift] = lut[i];
3801 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3802 * @hw: pointer to the HW structure
3803 * @mem: pointer to mem struct to fill out
3804 * @size: size of memory requested
3805 * @alignment: what to align the allocation to
3807 enum i40e_status_code
3808 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3809 struct i40e_dma_mem *mem,
3813 const struct rte_memzone *mz = NULL;
3814 char z_name[RTE_MEMZONE_NAMESIZE];
3817 return I40E_ERR_PARAM;
3819 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3820 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3821 alignment, RTE_PGSIZE_2M);
3823 return I40E_ERR_NO_MEMORY;
3827 mem->pa = mz->phys_addr;
3828 mem->zone = (const void *)mz;
3830 "memzone %s allocated with physical address: %"PRIu64,
3833 return I40E_SUCCESS;
3837 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3838 * @hw: pointer to the HW structure
3839 * @mem: ptr to mem struct to free
3841 enum i40e_status_code
3842 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3843 struct i40e_dma_mem *mem)
3846 return I40E_ERR_PARAM;
3849 "memzone %s to be freed with physical address: %"PRIu64,
3850 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3851 rte_memzone_free((const struct rte_memzone *)mem->zone);
3856 return I40E_SUCCESS;
3860 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3861 * @hw: pointer to the HW structure
3862 * @mem: pointer to mem struct to fill out
3863 * @size: size of memory requested
3865 enum i40e_status_code
3866 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3867 struct i40e_virt_mem *mem,
3871 return I40E_ERR_PARAM;
3874 mem->va = rte_zmalloc("i40e", size, 0);
3877 return I40E_SUCCESS;
3879 return I40E_ERR_NO_MEMORY;
3883 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3884 * @hw: pointer to the HW structure
3885 * @mem: pointer to mem struct to free
3887 enum i40e_status_code
3888 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3889 struct i40e_virt_mem *mem)
3892 return I40E_ERR_PARAM;
3897 return I40E_SUCCESS;
3901 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3903 rte_spinlock_init(&sp->spinlock);
3907 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3909 rte_spinlock_lock(&sp->spinlock);
3913 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3915 rte_spinlock_unlock(&sp->spinlock);
3919 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3925 * Get the hardware capabilities, which will be parsed
3926 * and saved into struct i40e_hw.
3929 i40e_get_cap(struct i40e_hw *hw)
3931 struct i40e_aqc_list_capabilities_element_resp *buf;
3932 uint16_t len, size = 0;
3935 /* Calculate a huge enough buff for saving response data temporarily */
3936 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3937 I40E_MAX_CAP_ELE_NUM;
3938 buf = rte_zmalloc("i40e", len, 0);
3940 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3941 return I40E_ERR_NO_MEMORY;
3944 /* Get, parse the capabilities and save it to hw */
3945 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3946 i40e_aqc_opc_list_func_capabilities, NULL);
3947 if (ret != I40E_SUCCESS)
3948 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3950 /* Free the temporary buffer after being used */
3957 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3960 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3961 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3962 uint16_t qp_count = 0, vsi_count = 0;
3964 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3965 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3968 /* Add the parameter init for LFC */
3969 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3970 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3971 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3973 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3974 pf->max_num_vsi = hw->func_caps.num_vsis;
3975 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3976 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3977 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3979 /* FDir queue/VSI allocation */
3980 pf->fdir_qp_offset = 0;
3981 if (hw->func_caps.fd) {
3982 pf->flags |= I40E_FLAG_FDIR;
3983 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3985 pf->fdir_nb_qps = 0;
3987 qp_count += pf->fdir_nb_qps;
3990 /* LAN queue/VSI allocation */
3991 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3992 if (!hw->func_caps.rss) {
3995 pf->flags |= I40E_FLAG_RSS;
3996 if (hw->mac.type == I40E_MAC_X722)
3997 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3998 pf->lan_nb_qps = pf->lan_nb_qp_max;
4000 qp_count += pf->lan_nb_qps;
4003 /* VF queue/VSI allocation */
4004 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4005 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4006 pf->flags |= I40E_FLAG_SRIOV;
4007 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4008 pf->vf_num = pci_dev->max_vfs;
4010 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4011 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4016 qp_count += pf->vf_nb_qps * pf->vf_num;
4017 vsi_count += pf->vf_num;
4019 /* VMDq queue/VSI allocation */
4020 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4021 pf->vmdq_nb_qps = 0;
4022 pf->max_nb_vmdq_vsi = 0;
4023 if (hw->func_caps.vmdq) {
4024 if (qp_count < hw->func_caps.num_tx_qp &&
4025 vsi_count < hw->func_caps.num_vsis) {
4026 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4027 qp_count) / pf->vmdq_nb_qp_max;
4029 /* Limit the maximum number of VMDq vsi to the maximum
4030 * ethdev can support
4032 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4033 hw->func_caps.num_vsis - vsi_count);
4034 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4036 if (pf->max_nb_vmdq_vsi) {
4037 pf->flags |= I40E_FLAG_VMDQ;
4038 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4040 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4041 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4042 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4045 "No enough queues left for VMDq");
4048 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4051 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4052 vsi_count += pf->max_nb_vmdq_vsi;
4054 if (hw->func_caps.dcb)
4055 pf->flags |= I40E_FLAG_DCB;
4057 if (qp_count > hw->func_caps.num_tx_qp) {
4059 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4060 qp_count, hw->func_caps.num_tx_qp);
4063 if (vsi_count > hw->func_caps.num_vsis) {
4065 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4066 vsi_count, hw->func_caps.num_vsis);
4074 i40e_pf_get_switch_config(struct i40e_pf *pf)
4076 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4077 struct i40e_aqc_get_switch_config_resp *switch_config;
4078 struct i40e_aqc_switch_config_element_resp *element;
4079 uint16_t start_seid = 0, num_reported;
4082 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4083 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4084 if (!switch_config) {
4085 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4089 /* Get the switch configurations */
4090 ret = i40e_aq_get_switch_config(hw, switch_config,
4091 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4092 if (ret != I40E_SUCCESS) {
4093 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4096 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4097 if (num_reported != 1) { /* The number should be 1 */
4098 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4102 /* Parse the switch configuration elements */
4103 element = &(switch_config->element[0]);
4104 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4105 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4106 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4108 PMD_DRV_LOG(INFO, "Unknown element type");
4111 rte_free(switch_config);
4117 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4120 struct pool_entry *entry;
4122 if (pool == NULL || num == 0)
4125 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4126 if (entry == NULL) {
4127 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4131 /* queue heap initialize */
4132 pool->num_free = num;
4133 pool->num_alloc = 0;
4135 LIST_INIT(&pool->alloc_list);
4136 LIST_INIT(&pool->free_list);
4138 /* Initialize element */
4142 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4147 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4149 struct pool_entry *entry, *next_entry;
4154 for (entry = LIST_FIRST(&pool->alloc_list);
4155 entry && (next_entry = LIST_NEXT(entry, next), 1);
4156 entry = next_entry) {
4157 LIST_REMOVE(entry, next);
4161 for (entry = LIST_FIRST(&pool->free_list);
4162 entry && (next_entry = LIST_NEXT(entry, next), 1);
4163 entry = next_entry) {
4164 LIST_REMOVE(entry, next);
4169 pool->num_alloc = 0;
4171 LIST_INIT(&pool->alloc_list);
4172 LIST_INIT(&pool->free_list);
4176 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4179 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4180 uint32_t pool_offset;
4184 PMD_DRV_LOG(ERR, "Invalid parameter");
4188 pool_offset = base - pool->base;
4189 /* Lookup in alloc list */
4190 LIST_FOREACH(entry, &pool->alloc_list, next) {
4191 if (entry->base == pool_offset) {
4192 valid_entry = entry;
4193 LIST_REMOVE(entry, next);
4198 /* Not find, return */
4199 if (valid_entry == NULL) {
4200 PMD_DRV_LOG(ERR, "Failed to find entry");
4205 * Found it, move it to free list and try to merge.
4206 * In order to make merge easier, always sort it by qbase.
4207 * Find adjacent prev and last entries.
4210 LIST_FOREACH(entry, &pool->free_list, next) {
4211 if (entry->base > valid_entry->base) {
4219 /* Try to merge with next one*/
4221 /* Merge with next one */
4222 if (valid_entry->base + valid_entry->len == next->base) {
4223 next->base = valid_entry->base;
4224 next->len += valid_entry->len;
4225 rte_free(valid_entry);
4232 /* Merge with previous one */
4233 if (prev->base + prev->len == valid_entry->base) {
4234 prev->len += valid_entry->len;
4235 /* If it merge with next one, remove next node */
4237 LIST_REMOVE(valid_entry, next);
4238 rte_free(valid_entry);
4240 rte_free(valid_entry);
4246 /* Not find any entry to merge, insert */
4249 LIST_INSERT_AFTER(prev, valid_entry, next);
4250 else if (next != NULL)
4251 LIST_INSERT_BEFORE(next, valid_entry, next);
4252 else /* It's empty list, insert to head */
4253 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4256 pool->num_free += valid_entry->len;
4257 pool->num_alloc -= valid_entry->len;
4263 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4266 struct pool_entry *entry, *valid_entry;
4268 if (pool == NULL || num == 0) {
4269 PMD_DRV_LOG(ERR, "Invalid parameter");
4273 if (pool->num_free < num) {
4274 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4275 num, pool->num_free);
4280 /* Lookup in free list and find most fit one */
4281 LIST_FOREACH(entry, &pool->free_list, next) {
4282 if (entry->len >= num) {
4284 if (entry->len == num) {
4285 valid_entry = entry;
4288 if (valid_entry == NULL || valid_entry->len > entry->len)
4289 valid_entry = entry;
4293 /* Not find one to satisfy the request, return */
4294 if (valid_entry == NULL) {
4295 PMD_DRV_LOG(ERR, "No valid entry found");
4299 * The entry have equal queue number as requested,
4300 * remove it from alloc_list.
4302 if (valid_entry->len == num) {
4303 LIST_REMOVE(valid_entry, next);
4306 * The entry have more numbers than requested,
4307 * create a new entry for alloc_list and minus its
4308 * queue base and number in free_list.
4310 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4311 if (entry == NULL) {
4313 "Failed to allocate memory for resource pool");
4316 entry->base = valid_entry->base;
4318 valid_entry->base += num;
4319 valid_entry->len -= num;
4320 valid_entry = entry;
4323 /* Insert it into alloc list, not sorted */
4324 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4326 pool->num_free -= valid_entry->len;
4327 pool->num_alloc += valid_entry->len;
4329 return valid_entry->base + pool->base;
4333 * bitmap_is_subset - Check whether src2 is subset of src1
4336 bitmap_is_subset(uint8_t src1, uint8_t src2)
4338 return !((src1 ^ src2) & src2);
4341 static enum i40e_status_code
4342 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4344 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4346 /* If DCB is not supported, only default TC is supported */
4347 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4348 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4349 return I40E_NOT_SUPPORTED;
4352 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4354 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4355 hw->func_caps.enabled_tcmap, enabled_tcmap);
4356 return I40E_NOT_SUPPORTED;
4358 return I40E_SUCCESS;
4362 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4363 struct i40e_vsi_vlan_pvid_info *info)
4366 struct i40e_vsi_context ctxt;
4367 uint8_t vlan_flags = 0;
4370 if (vsi == NULL || info == NULL) {
4371 PMD_DRV_LOG(ERR, "invalid parameters");
4372 return I40E_ERR_PARAM;
4376 vsi->info.pvid = info->config.pvid;
4378 * If insert pvid is enabled, only tagged pkts are
4379 * allowed to be sent out.
4381 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4382 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4385 if (info->config.reject.tagged == 0)
4386 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4388 if (info->config.reject.untagged == 0)
4389 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4391 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4392 I40E_AQ_VSI_PVLAN_MODE_MASK);
4393 vsi->info.port_vlan_flags |= vlan_flags;
4394 vsi->info.valid_sections =
4395 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4396 memset(&ctxt, 0, sizeof(ctxt));
4397 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4398 ctxt.seid = vsi->seid;
4400 hw = I40E_VSI_TO_HW(vsi);
4401 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4402 if (ret != I40E_SUCCESS)
4403 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4409 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4411 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4413 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4415 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4416 if (ret != I40E_SUCCESS)
4420 PMD_DRV_LOG(ERR, "seid not valid");
4424 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4425 tc_bw_data.tc_valid_bits = enabled_tcmap;
4426 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4427 tc_bw_data.tc_bw_credits[i] =
4428 (enabled_tcmap & (1 << i)) ? 1 : 0;
4430 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4431 if (ret != I40E_SUCCESS) {
4432 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4436 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4437 sizeof(vsi->info.qs_handle));
4438 return I40E_SUCCESS;
4441 static enum i40e_status_code
4442 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4443 struct i40e_aqc_vsi_properties_data *info,
4444 uint8_t enabled_tcmap)
4446 enum i40e_status_code ret;
4447 int i, total_tc = 0;
4448 uint16_t qpnum_per_tc, bsf, qp_idx;
4450 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4451 if (ret != I40E_SUCCESS)
4454 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4455 if (enabled_tcmap & (1 << i))
4459 vsi->enabled_tc = enabled_tcmap;
4461 /* Number of queues per enabled TC */
4462 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4463 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4464 bsf = rte_bsf32(qpnum_per_tc);
4466 /* Adjust the queue number to actual queues that can be applied */
4467 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4468 vsi->nb_qps = qpnum_per_tc * total_tc;
4471 * Configure TC and queue mapping parameters, for enabled TC,
4472 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4473 * default queue will serve it.
4476 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4477 if (vsi->enabled_tc & (1 << i)) {
4478 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4479 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4480 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4481 qp_idx += qpnum_per_tc;
4483 info->tc_mapping[i] = 0;
4486 /* Associate queue number with VSI */
4487 if (vsi->type == I40E_VSI_SRIOV) {
4488 info->mapping_flags |=
4489 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4490 for (i = 0; i < vsi->nb_qps; i++)
4491 info->queue_mapping[i] =
4492 rte_cpu_to_le_16(vsi->base_queue + i);
4494 info->mapping_flags |=
4495 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4496 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4498 info->valid_sections |=
4499 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4501 return I40E_SUCCESS;
4505 i40e_veb_release(struct i40e_veb *veb)
4507 struct i40e_vsi *vsi;
4513 if (!TAILQ_EMPTY(&veb->head)) {
4514 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4517 /* associate_vsi field is NULL for floating VEB */
4518 if (veb->associate_vsi != NULL) {
4519 vsi = veb->associate_vsi;
4520 hw = I40E_VSI_TO_HW(vsi);
4522 vsi->uplink_seid = veb->uplink_seid;
4525 veb->associate_pf->main_vsi->floating_veb = NULL;
4526 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4529 i40e_aq_delete_element(hw, veb->seid, NULL);
4531 return I40E_SUCCESS;
4535 static struct i40e_veb *
4536 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4538 struct i40e_veb *veb;
4544 "veb setup failed, associated PF shouldn't null");
4547 hw = I40E_PF_TO_HW(pf);
4549 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4551 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4555 veb->associate_vsi = vsi;
4556 veb->associate_pf = pf;
4557 TAILQ_INIT(&veb->head);
4558 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4560 /* create floating veb if vsi is NULL */
4562 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4563 I40E_DEFAULT_TCMAP, false,
4564 &veb->seid, false, NULL);
4566 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4567 true, &veb->seid, false, NULL);
4570 if (ret != I40E_SUCCESS) {
4571 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4572 hw->aq.asq_last_status);
4575 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4577 /* get statistics index */
4578 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4579 &veb->stats_idx, NULL, NULL, NULL);
4580 if (ret != I40E_SUCCESS) {
4581 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4582 hw->aq.asq_last_status);
4585 /* Get VEB bandwidth, to be implemented */
4586 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4588 vsi->uplink_seid = veb->seid;
4597 i40e_vsi_release(struct i40e_vsi *vsi)
4601 struct i40e_vsi_list *vsi_list;
4604 struct i40e_mac_filter *f;
4605 uint16_t user_param;
4608 return I40E_SUCCESS;
4613 user_param = vsi->user_param;
4615 pf = I40E_VSI_TO_PF(vsi);
4616 hw = I40E_VSI_TO_HW(vsi);
4618 /* VSI has child to attach, release child first */
4620 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4621 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4624 i40e_veb_release(vsi->veb);
4627 if (vsi->floating_veb) {
4628 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4629 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4634 /* Remove all macvlan filters of the VSI */
4635 i40e_vsi_remove_all_macvlan_filter(vsi);
4636 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4639 if (vsi->type != I40E_VSI_MAIN &&
4640 ((vsi->type != I40E_VSI_SRIOV) ||
4641 !pf->floating_veb_list[user_param])) {
4642 /* Remove vsi from parent's sibling list */
4643 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4644 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4645 return I40E_ERR_PARAM;
4647 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4648 &vsi->sib_vsi_list, list);
4650 /* Remove all switch element of the VSI */
4651 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4652 if (ret != I40E_SUCCESS)
4653 PMD_DRV_LOG(ERR, "Failed to delete element");
4656 if ((vsi->type == I40E_VSI_SRIOV) &&
4657 pf->floating_veb_list[user_param]) {
4658 /* Remove vsi from parent's sibling list */
4659 if (vsi->parent_vsi == NULL ||
4660 vsi->parent_vsi->floating_veb == NULL) {
4661 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4662 return I40E_ERR_PARAM;
4664 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4665 &vsi->sib_vsi_list, list);
4667 /* Remove all switch element of the VSI */
4668 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4669 if (ret != I40E_SUCCESS)
4670 PMD_DRV_LOG(ERR, "Failed to delete element");
4673 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4675 if (vsi->type != I40E_VSI_SRIOV)
4676 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4679 return I40E_SUCCESS;
4683 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4685 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4686 struct i40e_aqc_remove_macvlan_element_data def_filter;
4687 struct i40e_mac_filter_info filter;
4690 if (vsi->type != I40E_VSI_MAIN)
4691 return I40E_ERR_CONFIG;
4692 memset(&def_filter, 0, sizeof(def_filter));
4693 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4695 def_filter.vlan_tag = 0;
4696 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4697 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4698 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4699 if (ret != I40E_SUCCESS) {
4700 struct i40e_mac_filter *f;
4701 struct ether_addr *mac;
4704 "Cannot remove the default macvlan filter");
4705 /* It needs to add the permanent mac into mac list */
4706 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4708 PMD_DRV_LOG(ERR, "failed to allocate memory");
4709 return I40E_ERR_NO_MEMORY;
4711 mac = &f->mac_info.mac_addr;
4712 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4714 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4715 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4720 rte_memcpy(&filter.mac_addr,
4721 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4722 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4723 return i40e_vsi_add_mac(vsi, &filter);
4727 * i40e_vsi_get_bw_config - Query VSI BW Information
4728 * @vsi: the VSI to be queried
4730 * Returns 0 on success, negative value on failure
4732 static enum i40e_status_code
4733 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4735 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4736 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4737 struct i40e_hw *hw = &vsi->adapter->hw;
4742 memset(&bw_config, 0, sizeof(bw_config));
4743 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4744 if (ret != I40E_SUCCESS) {
4745 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4746 hw->aq.asq_last_status);
4750 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4751 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4752 &ets_sla_config, NULL);
4753 if (ret != I40E_SUCCESS) {
4755 "VSI failed to get TC bandwdith configuration %u",
4756 hw->aq.asq_last_status);
4760 /* store and print out BW info */
4761 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4762 vsi->bw_info.bw_max = bw_config.max_bw;
4763 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4764 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4765 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4766 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4768 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4769 vsi->bw_info.bw_ets_share_credits[i] =
4770 ets_sla_config.share_credits[i];
4771 vsi->bw_info.bw_ets_credits[i] =
4772 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4773 /* 4 bits per TC, 4th bit is reserved */
4774 vsi->bw_info.bw_ets_max[i] =
4775 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4776 RTE_LEN2MASK(3, uint8_t));
4777 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4778 vsi->bw_info.bw_ets_share_credits[i]);
4779 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4780 vsi->bw_info.bw_ets_credits[i]);
4781 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4782 vsi->bw_info.bw_ets_max[i]);
4785 return I40E_SUCCESS;
4788 /* i40e_enable_pf_lb
4789 * @pf: pointer to the pf structure
4791 * allow loopback on pf
4794 i40e_enable_pf_lb(struct i40e_pf *pf)
4796 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4797 struct i40e_vsi_context ctxt;
4800 /* Use the FW API if FW >= v5.0 */
4801 if (hw->aq.fw_maj_ver < 5) {
4802 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4806 memset(&ctxt, 0, sizeof(ctxt));
4807 ctxt.seid = pf->main_vsi_seid;
4808 ctxt.pf_num = hw->pf_id;
4809 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4811 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4812 ret, hw->aq.asq_last_status);
4815 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4816 ctxt.info.valid_sections =
4817 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4818 ctxt.info.switch_id |=
4819 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4821 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4823 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4824 hw->aq.asq_last_status);
4829 i40e_vsi_setup(struct i40e_pf *pf,
4830 enum i40e_vsi_type type,
4831 struct i40e_vsi *uplink_vsi,
4832 uint16_t user_param)
4834 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4835 struct i40e_vsi *vsi;
4836 struct i40e_mac_filter_info filter;
4838 struct i40e_vsi_context ctxt;
4839 struct ether_addr broadcast =
4840 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4842 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4843 uplink_vsi == NULL) {
4845 "VSI setup failed, VSI link shouldn't be NULL");
4849 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4851 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4856 * 1.type is not MAIN and uplink vsi is not NULL
4857 * If uplink vsi didn't setup VEB, create one first under veb field
4858 * 2.type is SRIOV and the uplink is NULL
4859 * If floating VEB is NULL, create one veb under floating veb field
4862 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4863 uplink_vsi->veb == NULL) {
4864 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4866 if (uplink_vsi->veb == NULL) {
4867 PMD_DRV_LOG(ERR, "VEB setup failed");
4870 /* set ALLOWLOOPBACk on pf, when veb is created */
4871 i40e_enable_pf_lb(pf);
4874 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4875 pf->main_vsi->floating_veb == NULL) {
4876 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4878 if (pf->main_vsi->floating_veb == NULL) {
4879 PMD_DRV_LOG(ERR, "VEB setup failed");
4884 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4886 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4889 TAILQ_INIT(&vsi->mac_list);
4891 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4892 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4893 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4894 vsi->user_param = user_param;
4895 vsi->vlan_anti_spoof_on = 0;
4896 vsi->vlan_filter_on = 0;
4897 /* Allocate queues */
4898 switch (vsi->type) {
4899 case I40E_VSI_MAIN :
4900 vsi->nb_qps = pf->lan_nb_qps;
4902 case I40E_VSI_SRIOV :
4903 vsi->nb_qps = pf->vf_nb_qps;
4905 case I40E_VSI_VMDQ2:
4906 vsi->nb_qps = pf->vmdq_nb_qps;
4909 vsi->nb_qps = pf->fdir_nb_qps;
4915 * The filter status descriptor is reported in rx queue 0,
4916 * while the tx queue for fdir filter programming has no
4917 * such constraints, can be non-zero queues.
4918 * To simplify it, choose FDIR vsi use queue 0 pair.
4919 * To make sure it will use queue 0 pair, queue allocation
4920 * need be done before this function is called
4922 if (type != I40E_VSI_FDIR) {
4923 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4925 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4929 vsi->base_queue = ret;
4931 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4933 /* VF has MSIX interrupt in VF range, don't allocate here */
4934 if (type == I40E_VSI_MAIN) {
4935 ret = i40e_res_pool_alloc(&pf->msix_pool,
4936 RTE_MIN(vsi->nb_qps,
4937 RTE_MAX_RXTX_INTR_VEC_ID));
4939 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4941 goto fail_queue_alloc;
4943 vsi->msix_intr = ret;
4944 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4945 } else if (type != I40E_VSI_SRIOV) {
4946 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4948 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4949 goto fail_queue_alloc;
4951 vsi->msix_intr = ret;
4959 if (type == I40E_VSI_MAIN) {
4960 /* For main VSI, no need to add since it's default one */
4961 vsi->uplink_seid = pf->mac_seid;
4962 vsi->seid = pf->main_vsi_seid;
4963 /* Bind queues with specific MSIX interrupt */
4965 * Needs 2 interrupt at least, one for misc cause which will
4966 * enabled from OS side, Another for queues binding the
4967 * interrupt from device side only.
4970 /* Get default VSI parameters from hardware */
4971 memset(&ctxt, 0, sizeof(ctxt));
4972 ctxt.seid = vsi->seid;
4973 ctxt.pf_num = hw->pf_id;
4974 ctxt.uplink_seid = vsi->uplink_seid;
4976 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4977 if (ret != I40E_SUCCESS) {
4978 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4979 goto fail_msix_alloc;
4981 rte_memcpy(&vsi->info, &ctxt.info,
4982 sizeof(struct i40e_aqc_vsi_properties_data));
4983 vsi->vsi_id = ctxt.vsi_number;
4984 vsi->info.valid_sections = 0;
4986 /* Configure tc, enabled TC0 only */
4987 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4989 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4990 goto fail_msix_alloc;
4993 /* TC, queue mapping */
4994 memset(&ctxt, 0, sizeof(ctxt));
4995 vsi->info.valid_sections |=
4996 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4997 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4998 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4999 rte_memcpy(&ctxt.info, &vsi->info,
5000 sizeof(struct i40e_aqc_vsi_properties_data));
5001 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5002 I40E_DEFAULT_TCMAP);
5003 if (ret != I40E_SUCCESS) {
5005 "Failed to configure TC queue mapping");
5006 goto fail_msix_alloc;
5008 ctxt.seid = vsi->seid;
5009 ctxt.pf_num = hw->pf_id;
5010 ctxt.uplink_seid = vsi->uplink_seid;
5013 /* Update VSI parameters */
5014 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5015 if (ret != I40E_SUCCESS) {
5016 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5017 goto fail_msix_alloc;
5020 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5021 sizeof(vsi->info.tc_mapping));
5022 rte_memcpy(&vsi->info.queue_mapping,
5023 &ctxt.info.queue_mapping,
5024 sizeof(vsi->info.queue_mapping));
5025 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5026 vsi->info.valid_sections = 0;
5028 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5032 * Updating default filter settings are necessary to prevent
5033 * reception of tagged packets.
5034 * Some old firmware configurations load a default macvlan
5035 * filter which accepts both tagged and untagged packets.
5036 * The updating is to use a normal filter instead if needed.
5037 * For NVM 4.2.2 or after, the updating is not needed anymore.
5038 * The firmware with correct configurations load the default
5039 * macvlan filter which is expected and cannot be removed.
5041 i40e_update_default_filter_setting(vsi);
5042 i40e_config_qinq(hw, vsi);
5043 } else if (type == I40E_VSI_SRIOV) {
5044 memset(&ctxt, 0, sizeof(ctxt));
5046 * For other VSI, the uplink_seid equals to uplink VSI's
5047 * uplink_seid since they share same VEB
5049 if (uplink_vsi == NULL)
5050 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5052 vsi->uplink_seid = uplink_vsi->uplink_seid;
5053 ctxt.pf_num = hw->pf_id;
5054 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5055 ctxt.uplink_seid = vsi->uplink_seid;
5056 ctxt.connection_type = 0x1;
5057 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5059 /* Use the VEB configuration if FW >= v5.0 */
5060 if (hw->aq.fw_maj_ver >= 5) {
5061 /* Configure switch ID */
5062 ctxt.info.valid_sections |=
5063 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5064 ctxt.info.switch_id =
5065 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5068 /* Configure port/vlan */
5069 ctxt.info.valid_sections |=
5070 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5071 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5072 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5073 hw->func_caps.enabled_tcmap);
5074 if (ret != I40E_SUCCESS) {
5076 "Failed to configure TC queue mapping");
5077 goto fail_msix_alloc;
5080 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5081 ctxt.info.valid_sections |=
5082 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5084 * Since VSI is not created yet, only configure parameter,
5085 * will add vsi below.
5088 i40e_config_qinq(hw, vsi);
5089 } else if (type == I40E_VSI_VMDQ2) {
5090 memset(&ctxt, 0, sizeof(ctxt));
5092 * For other VSI, the uplink_seid equals to uplink VSI's
5093 * uplink_seid since they share same VEB
5095 vsi->uplink_seid = uplink_vsi->uplink_seid;
5096 ctxt.pf_num = hw->pf_id;
5098 ctxt.uplink_seid = vsi->uplink_seid;
5099 ctxt.connection_type = 0x1;
5100 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5102 ctxt.info.valid_sections |=
5103 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5104 /* user_param carries flag to enable loop back */
5106 ctxt.info.switch_id =
5107 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5108 ctxt.info.switch_id |=
5109 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5112 /* Configure port/vlan */
5113 ctxt.info.valid_sections |=
5114 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5115 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5116 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5117 I40E_DEFAULT_TCMAP);
5118 if (ret != I40E_SUCCESS) {
5120 "Failed to configure TC queue mapping");
5121 goto fail_msix_alloc;
5123 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5124 ctxt.info.valid_sections |=
5125 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5126 } else if (type == I40E_VSI_FDIR) {
5127 memset(&ctxt, 0, sizeof(ctxt));
5128 vsi->uplink_seid = uplink_vsi->uplink_seid;
5129 ctxt.pf_num = hw->pf_id;
5131 ctxt.uplink_seid = vsi->uplink_seid;
5132 ctxt.connection_type = 0x1; /* regular data port */
5133 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5134 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5135 I40E_DEFAULT_TCMAP);
5136 if (ret != I40E_SUCCESS) {
5138 "Failed to configure TC queue mapping.");
5139 goto fail_msix_alloc;
5141 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5142 ctxt.info.valid_sections |=
5143 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5145 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5146 goto fail_msix_alloc;
5149 if (vsi->type != I40E_VSI_MAIN) {
5150 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5151 if (ret != I40E_SUCCESS) {
5152 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5153 hw->aq.asq_last_status);
5154 goto fail_msix_alloc;
5156 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5157 vsi->info.valid_sections = 0;
5158 vsi->seid = ctxt.seid;
5159 vsi->vsi_id = ctxt.vsi_number;
5160 vsi->sib_vsi_list.vsi = vsi;
5161 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5162 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5163 &vsi->sib_vsi_list, list);
5165 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5166 &vsi->sib_vsi_list, list);
5170 /* MAC/VLAN configuration */
5171 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5172 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5174 ret = i40e_vsi_add_mac(vsi, &filter);
5175 if (ret != I40E_SUCCESS) {
5176 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5177 goto fail_msix_alloc;
5180 /* Get VSI BW information */
5181 i40e_vsi_get_bw_config(vsi);
5184 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5186 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5192 /* Configure vlan filter on or off */
5194 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5197 struct i40e_mac_filter *f;
5199 struct i40e_mac_filter_info *mac_filter;
5200 enum rte_mac_filter_type desired_filter;
5201 int ret = I40E_SUCCESS;
5204 /* Filter to match MAC and VLAN */
5205 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5207 /* Filter to match only MAC */
5208 desired_filter = RTE_MAC_PERFECT_MATCH;
5213 mac_filter = rte_zmalloc("mac_filter_info_data",
5214 num * sizeof(*mac_filter), 0);
5215 if (mac_filter == NULL) {
5216 PMD_DRV_LOG(ERR, "failed to allocate memory");
5217 return I40E_ERR_NO_MEMORY;
5222 /* Remove all existing mac */
5223 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5224 mac_filter[i] = f->mac_info;
5225 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5227 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5228 on ? "enable" : "disable");
5234 /* Override with new filter */
5235 for (i = 0; i < num; i++) {
5236 mac_filter[i].filter_type = desired_filter;
5237 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5239 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5240 on ? "enable" : "disable");
5246 rte_free(mac_filter);
5250 /* Configure vlan stripping on or off */
5252 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5254 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5255 struct i40e_vsi_context ctxt;
5257 int ret = I40E_SUCCESS;
5259 /* Check if it has been already on or off */
5260 if (vsi->info.valid_sections &
5261 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5263 if ((vsi->info.port_vlan_flags &
5264 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5265 return 0; /* already on */
5267 if ((vsi->info.port_vlan_flags &
5268 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5269 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5270 return 0; /* already off */
5275 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5277 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5278 vsi->info.valid_sections =
5279 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5280 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5281 vsi->info.port_vlan_flags |= vlan_flags;
5282 ctxt.seid = vsi->seid;
5283 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5284 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5286 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5287 on ? "enable" : "disable");
5293 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5295 struct rte_eth_dev_data *data = dev->data;
5299 /* Apply vlan offload setting */
5300 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5301 i40e_vlan_offload_set(dev, mask);
5303 /* Apply double-vlan setting, not implemented yet */
5305 /* Apply pvid setting */
5306 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5307 data->dev_conf.txmode.hw_vlan_insert_pvid);
5309 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5315 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5319 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5323 i40e_update_flow_control(struct i40e_hw *hw)
5325 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5326 struct i40e_link_status link_status;
5327 uint32_t rxfc = 0, txfc = 0, reg;
5331 memset(&link_status, 0, sizeof(link_status));
5332 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5333 if (ret != I40E_SUCCESS) {
5334 PMD_DRV_LOG(ERR, "Failed to get link status information");
5335 goto write_reg; /* Disable flow control */
5338 an_info = hw->phy.link_info.an_info;
5339 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5340 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5341 ret = I40E_ERR_NOT_READY;
5342 goto write_reg; /* Disable flow control */
5345 * If link auto negotiation is enabled, flow control needs to
5346 * be configured according to it
5348 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5349 case I40E_LINK_PAUSE_RXTX:
5352 hw->fc.current_mode = I40E_FC_FULL;
5354 case I40E_AQ_LINK_PAUSE_RX:
5356 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5358 case I40E_AQ_LINK_PAUSE_TX:
5360 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5363 hw->fc.current_mode = I40E_FC_NONE;
5368 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5369 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5370 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5371 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5372 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5373 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5380 i40e_pf_setup(struct i40e_pf *pf)
5382 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5383 struct i40e_filter_control_settings settings;
5384 struct i40e_vsi *vsi;
5387 /* Clear all stats counters */
5388 pf->offset_loaded = FALSE;
5389 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5390 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5391 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5392 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5394 ret = i40e_pf_get_switch_config(pf);
5395 if (ret != I40E_SUCCESS) {
5396 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5399 if (pf->flags & I40E_FLAG_FDIR) {
5400 /* make queue allocated first, let FDIR use queue pair 0*/
5401 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5402 if (ret != I40E_FDIR_QUEUE_ID) {
5404 "queue allocation fails for FDIR: ret =%d",
5406 pf->flags &= ~I40E_FLAG_FDIR;
5409 /* main VSI setup */
5410 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5412 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5413 return I40E_ERR_NOT_READY;
5417 /* Configure filter control */
5418 memset(&settings, 0, sizeof(settings));
5419 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5420 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5421 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5422 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5424 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5425 hw->func_caps.rss_table_size);
5426 return I40E_ERR_PARAM;
5428 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5429 hw->func_caps.rss_table_size);
5430 pf->hash_lut_size = hw->func_caps.rss_table_size;
5432 /* Enable ethtype and macvlan filters */
5433 settings.enable_ethtype = TRUE;
5434 settings.enable_macvlan = TRUE;
5435 ret = i40e_set_filter_control(hw, &settings);
5437 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5440 /* Update flow control according to the auto negotiation */
5441 i40e_update_flow_control(hw);
5443 return I40E_SUCCESS;
5447 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5453 * Set or clear TX Queue Disable flags,
5454 * which is required by hardware.
5456 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5457 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5459 /* Wait until the request is finished */
5460 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5461 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5462 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5463 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5464 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5470 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5471 return I40E_SUCCESS; /* already on, skip next steps */
5473 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5474 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5476 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5477 return I40E_SUCCESS; /* already off, skip next steps */
5478 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5480 /* Write the register */
5481 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5482 /* Check the result */
5483 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5484 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5485 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5487 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5488 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5491 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5492 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5496 /* Check if it is timeout */
5497 if (j >= I40E_CHK_Q_ENA_COUNT) {
5498 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5499 (on ? "enable" : "disable"), q_idx);
5500 return I40E_ERR_TIMEOUT;
5503 return I40E_SUCCESS;
5506 /* Swith on or off the tx queues */
5508 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5510 struct rte_eth_dev_data *dev_data = pf->dev_data;
5511 struct i40e_tx_queue *txq;
5512 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5516 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5517 txq = dev_data->tx_queues[i];
5518 /* Don't operate the queue if not configured or
5519 * if starting only per queue */
5520 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5523 ret = i40e_dev_tx_queue_start(dev, i);
5525 ret = i40e_dev_tx_queue_stop(dev, i);
5526 if ( ret != I40E_SUCCESS)
5530 return I40E_SUCCESS;
5534 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5539 /* Wait until the request is finished */
5540 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5541 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5542 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5543 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5544 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5549 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5550 return I40E_SUCCESS; /* Already on, skip next steps */
5551 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5553 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5554 return I40E_SUCCESS; /* Already off, skip next steps */
5555 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5558 /* Write the register */
5559 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5560 /* Check the result */
5561 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5562 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5563 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5565 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5566 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5569 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5570 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5575 /* Check if it is timeout */
5576 if (j >= I40E_CHK_Q_ENA_COUNT) {
5577 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5578 (on ? "enable" : "disable"), q_idx);
5579 return I40E_ERR_TIMEOUT;
5582 return I40E_SUCCESS;
5584 /* Switch on or off the rx queues */
5586 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5588 struct rte_eth_dev_data *dev_data = pf->dev_data;
5589 struct i40e_rx_queue *rxq;
5590 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5594 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5595 rxq = dev_data->rx_queues[i];
5596 /* Don't operate the queue if not configured or
5597 * if starting only per queue */
5598 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5601 ret = i40e_dev_rx_queue_start(dev, i);
5603 ret = i40e_dev_rx_queue_stop(dev, i);
5604 if (ret != I40E_SUCCESS)
5608 return I40E_SUCCESS;
5611 /* Switch on or off all the rx/tx queues */
5613 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5618 /* enable rx queues before enabling tx queues */
5619 ret = i40e_dev_switch_rx_queues(pf, on);
5621 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5624 ret = i40e_dev_switch_tx_queues(pf, on);
5626 /* Stop tx queues before stopping rx queues */
5627 ret = i40e_dev_switch_tx_queues(pf, on);
5629 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5632 ret = i40e_dev_switch_rx_queues(pf, on);
5638 /* Initialize VSI for TX */
5640 i40e_dev_tx_init(struct i40e_pf *pf)
5642 struct rte_eth_dev_data *data = pf->dev_data;
5644 uint32_t ret = I40E_SUCCESS;
5645 struct i40e_tx_queue *txq;
5647 for (i = 0; i < data->nb_tx_queues; i++) {
5648 txq = data->tx_queues[i];
5649 if (!txq || !txq->q_set)
5651 ret = i40e_tx_queue_init(txq);
5652 if (ret != I40E_SUCCESS)
5655 if (ret == I40E_SUCCESS)
5656 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5662 /* Initialize VSI for RX */
5664 i40e_dev_rx_init(struct i40e_pf *pf)
5666 struct rte_eth_dev_data *data = pf->dev_data;
5667 int ret = I40E_SUCCESS;
5669 struct i40e_rx_queue *rxq;
5671 i40e_pf_config_mq_rx(pf);
5672 for (i = 0; i < data->nb_rx_queues; i++) {
5673 rxq = data->rx_queues[i];
5674 if (!rxq || !rxq->q_set)
5677 ret = i40e_rx_queue_init(rxq);
5678 if (ret != I40E_SUCCESS) {
5680 "Failed to do RX queue initialization");
5684 if (ret == I40E_SUCCESS)
5685 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5692 i40e_dev_rxtx_init(struct i40e_pf *pf)
5696 err = i40e_dev_tx_init(pf);
5698 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5701 err = i40e_dev_rx_init(pf);
5703 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5711 i40e_vmdq_setup(struct rte_eth_dev *dev)
5713 struct rte_eth_conf *conf = &dev->data->dev_conf;
5714 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5715 int i, err, conf_vsis, j, loop;
5716 struct i40e_vsi *vsi;
5717 struct i40e_vmdq_info *vmdq_info;
5718 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5719 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5722 * Disable interrupt to avoid message from VF. Furthermore, it will
5723 * avoid race condition in VSI creation/destroy.
5725 i40e_pf_disable_irq0(hw);
5727 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5728 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5732 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5733 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5734 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5735 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5736 pf->max_nb_vmdq_vsi);
5740 if (pf->vmdq != NULL) {
5741 PMD_INIT_LOG(INFO, "VMDQ already configured");
5745 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5746 sizeof(*vmdq_info) * conf_vsis, 0);
5748 if (pf->vmdq == NULL) {
5749 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5753 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5755 /* Create VMDQ VSI */
5756 for (i = 0; i < conf_vsis; i++) {
5757 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5758 vmdq_conf->enable_loop_back);
5760 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5764 vmdq_info = &pf->vmdq[i];
5766 vmdq_info->vsi = vsi;
5768 pf->nb_cfg_vmdq_vsi = conf_vsis;
5770 /* Configure Vlan */
5771 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5772 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5773 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5774 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5775 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5776 vmdq_conf->pool_map[i].vlan_id, j);
5778 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5779 vmdq_conf->pool_map[i].vlan_id);
5781 PMD_INIT_LOG(ERR, "Failed to add vlan");
5789 i40e_pf_enable_irq0(hw);
5794 for (i = 0; i < conf_vsis; i++)
5795 if (pf->vmdq[i].vsi == NULL)
5798 i40e_vsi_release(pf->vmdq[i].vsi);
5802 i40e_pf_enable_irq0(hw);
5807 i40e_stat_update_32(struct i40e_hw *hw,
5815 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5819 if (new_data >= *offset)
5820 *stat = (uint64_t)(new_data - *offset);
5822 *stat = (uint64_t)((new_data +
5823 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5827 i40e_stat_update_48(struct i40e_hw *hw,
5836 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5837 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5838 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5843 if (new_data >= *offset)
5844 *stat = new_data - *offset;
5846 *stat = (uint64_t)((new_data +
5847 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5849 *stat &= I40E_48_BIT_MASK;
5854 i40e_pf_disable_irq0(struct i40e_hw *hw)
5856 /* Disable all interrupt types */
5857 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5858 I40E_WRITE_FLUSH(hw);
5863 i40e_pf_enable_irq0(struct i40e_hw *hw)
5865 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5866 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5867 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5868 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5869 I40E_WRITE_FLUSH(hw);
5873 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5875 /* read pending request and disable first */
5876 i40e_pf_disable_irq0(hw);
5877 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5878 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5879 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5882 /* Link no queues with irq0 */
5883 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5884 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5888 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5894 uint32_t index, offset, val;
5899 * Try to find which VF trigger a reset, use absolute VF id to access
5900 * since the reg is global register.
5902 for (i = 0; i < pf->vf_num; i++) {
5903 abs_vf_id = hw->func_caps.vf_base_id + i;
5904 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5905 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5906 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5907 /* VFR event occurred */
5908 if (val & (0x1 << offset)) {
5911 /* Clear the event first */
5912 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5914 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5916 * Only notify a VF reset event occurred,
5917 * don't trigger another SW reset
5919 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5920 if (ret != I40E_SUCCESS)
5921 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5927 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5932 for (i = 0; i < pf->vf_num; i++)
5933 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5937 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940 struct i40e_arq_event_info info;
5941 uint16_t pending, opcode;
5944 info.buf_len = I40E_AQ_BUF_SZ;
5945 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5946 if (!info.msg_buf) {
5947 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5953 ret = i40e_clean_arq_element(hw, &info, &pending);
5955 if (ret != I40E_SUCCESS) {
5957 "Failed to read msg from AdminQ, aq_err: %u",
5958 hw->aq.asq_last_status);
5961 opcode = rte_le_to_cpu_16(info.desc.opcode);
5964 case i40e_aqc_opc_send_msg_to_pf:
5965 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5966 i40e_pf_host_handle_vf_msg(dev,
5967 rte_le_to_cpu_16(info.desc.retval),
5968 rte_le_to_cpu_32(info.desc.cookie_high),
5969 rte_le_to_cpu_32(info.desc.cookie_low),
5973 case i40e_aqc_opc_get_link_status:
5974 ret = i40e_dev_link_update(dev, 0);
5976 _rte_eth_dev_callback_process(dev,
5977 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5980 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5985 rte_free(info.msg_buf);
5989 * Interrupt handler triggered by NIC for handling
5990 * specific interrupt.
5993 * Pointer to interrupt handle.
5995 * The address of parameter (struct rte_eth_dev *) regsitered before.
6001 i40e_dev_interrupt_handler(void *param)
6003 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6004 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007 /* Disable interrupt */
6008 i40e_pf_disable_irq0(hw);
6010 /* read out interrupt causes */
6011 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6013 /* No interrupt event indicated */
6014 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6015 PMD_DRV_LOG(INFO, "No interrupt event");
6018 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6019 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6020 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6021 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6022 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6023 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6024 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6025 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6026 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6027 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6028 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6029 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6030 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6031 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6033 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6034 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6035 i40e_dev_handle_vfr_event(dev);
6037 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6038 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6039 i40e_dev_handle_aq_msg(dev);
6043 /* Enable interrupt */
6044 i40e_pf_enable_irq0(hw);
6045 rte_intr_enable(dev->intr_handle);
6049 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6050 struct i40e_macvlan_filter *filter,
6053 int ele_num, ele_buff_size;
6054 int num, actual_num, i;
6056 int ret = I40E_SUCCESS;
6057 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6058 struct i40e_aqc_add_macvlan_element_data *req_list;
6060 if (filter == NULL || total == 0)
6061 return I40E_ERR_PARAM;
6062 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6063 ele_buff_size = hw->aq.asq_buf_size;
6065 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6066 if (req_list == NULL) {
6067 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6068 return I40E_ERR_NO_MEMORY;
6073 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6074 memset(req_list, 0, ele_buff_size);
6076 for (i = 0; i < actual_num; i++) {
6077 rte_memcpy(req_list[i].mac_addr,
6078 &filter[num + i].macaddr, ETH_ADDR_LEN);
6079 req_list[i].vlan_tag =
6080 rte_cpu_to_le_16(filter[num + i].vlan_id);
6082 switch (filter[num + i].filter_type) {
6083 case RTE_MAC_PERFECT_MATCH:
6084 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6085 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6087 case RTE_MACVLAN_PERFECT_MATCH:
6088 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6090 case RTE_MAC_HASH_MATCH:
6091 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6092 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6094 case RTE_MACVLAN_HASH_MATCH:
6095 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6098 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6099 ret = I40E_ERR_PARAM;
6103 req_list[i].queue_number = 0;
6105 req_list[i].flags = rte_cpu_to_le_16(flags);
6108 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6110 if (ret != I40E_SUCCESS) {
6111 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6115 } while (num < total);
6123 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6124 struct i40e_macvlan_filter *filter,
6127 int ele_num, ele_buff_size;
6128 int num, actual_num, i;
6130 int ret = I40E_SUCCESS;
6131 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6132 struct i40e_aqc_remove_macvlan_element_data *req_list;
6134 if (filter == NULL || total == 0)
6135 return I40E_ERR_PARAM;
6137 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6138 ele_buff_size = hw->aq.asq_buf_size;
6140 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6141 if (req_list == NULL) {
6142 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6143 return I40E_ERR_NO_MEMORY;
6148 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6149 memset(req_list, 0, ele_buff_size);
6151 for (i = 0; i < actual_num; i++) {
6152 rte_memcpy(req_list[i].mac_addr,
6153 &filter[num + i].macaddr, ETH_ADDR_LEN);
6154 req_list[i].vlan_tag =
6155 rte_cpu_to_le_16(filter[num + i].vlan_id);
6157 switch (filter[num + i].filter_type) {
6158 case RTE_MAC_PERFECT_MATCH:
6159 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6160 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6162 case RTE_MACVLAN_PERFECT_MATCH:
6163 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6165 case RTE_MAC_HASH_MATCH:
6166 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6167 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6169 case RTE_MACVLAN_HASH_MATCH:
6170 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6173 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6174 ret = I40E_ERR_PARAM;
6177 req_list[i].flags = rte_cpu_to_le_16(flags);
6180 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6182 if (ret != I40E_SUCCESS) {
6183 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6187 } while (num < total);
6194 /* Find out specific MAC filter */
6195 static struct i40e_mac_filter *
6196 i40e_find_mac_filter(struct i40e_vsi *vsi,
6197 struct ether_addr *macaddr)
6199 struct i40e_mac_filter *f;
6201 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6202 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6210 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6213 uint32_t vid_idx, vid_bit;
6215 if (vlan_id > ETH_VLAN_ID_MAX)
6218 vid_idx = I40E_VFTA_IDX(vlan_id);
6219 vid_bit = I40E_VFTA_BIT(vlan_id);
6221 if (vsi->vfta[vid_idx] & vid_bit)
6228 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6229 uint16_t vlan_id, bool on)
6231 uint32_t vid_idx, vid_bit;
6233 vid_idx = I40E_VFTA_IDX(vlan_id);
6234 vid_bit = I40E_VFTA_BIT(vlan_id);
6237 vsi->vfta[vid_idx] |= vid_bit;
6239 vsi->vfta[vid_idx] &= ~vid_bit;
6243 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6244 uint16_t vlan_id, bool on)
6246 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6247 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6250 if (vlan_id > ETH_VLAN_ID_MAX)
6253 i40e_store_vlan_filter(vsi, vlan_id, on);
6255 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6258 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6261 ret = i40e_aq_add_vlan(hw, vsi->seid,
6262 &vlan_data, 1, NULL);
6263 if (ret != I40E_SUCCESS)
6264 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6266 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6267 &vlan_data, 1, NULL);
6268 if (ret != I40E_SUCCESS)
6270 "Failed to remove vlan filter");
6275 * Find all vlan options for specific mac addr,
6276 * return with actual vlan found.
6279 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6280 struct i40e_macvlan_filter *mv_f,
6281 int num, struct ether_addr *addr)
6287 * Not to use i40e_find_vlan_filter to decrease the loop time,
6288 * although the code looks complex.
6290 if (num < vsi->vlan_num)
6291 return I40E_ERR_PARAM;
6294 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6296 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6297 if (vsi->vfta[j] & (1 << k)) {
6300 "vlan number doesn't match");
6301 return I40E_ERR_PARAM;
6303 rte_memcpy(&mv_f[i].macaddr,
6304 addr, ETH_ADDR_LEN);
6306 j * I40E_UINT32_BIT_SIZE + k;
6312 return I40E_SUCCESS;
6316 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6317 struct i40e_macvlan_filter *mv_f,
6322 struct i40e_mac_filter *f;
6324 if (num < vsi->mac_num)
6325 return I40E_ERR_PARAM;
6327 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6329 PMD_DRV_LOG(ERR, "buffer number not match");
6330 return I40E_ERR_PARAM;
6332 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6334 mv_f[i].vlan_id = vlan;
6335 mv_f[i].filter_type = f->mac_info.filter_type;
6339 return I40E_SUCCESS;
6343 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6346 struct i40e_mac_filter *f;
6347 struct i40e_macvlan_filter *mv_f;
6348 int ret = I40E_SUCCESS;
6350 if (vsi == NULL || vsi->mac_num == 0)
6351 return I40E_ERR_PARAM;
6353 /* Case that no vlan is set */
6354 if (vsi->vlan_num == 0)
6357 num = vsi->mac_num * vsi->vlan_num;
6359 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6361 PMD_DRV_LOG(ERR, "failed to allocate memory");
6362 return I40E_ERR_NO_MEMORY;
6366 if (vsi->vlan_num == 0) {
6367 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6368 rte_memcpy(&mv_f[i].macaddr,
6369 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6370 mv_f[i].filter_type = f->mac_info.filter_type;
6371 mv_f[i].vlan_id = 0;
6375 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6376 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6377 vsi->vlan_num, &f->mac_info.mac_addr);
6378 if (ret != I40E_SUCCESS)
6380 for (j = i; j < i + vsi->vlan_num; j++)
6381 mv_f[j].filter_type = f->mac_info.filter_type;
6386 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6394 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6396 struct i40e_macvlan_filter *mv_f;
6398 int ret = I40E_SUCCESS;
6400 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6401 return I40E_ERR_PARAM;
6403 /* If it's already set, just return */
6404 if (i40e_find_vlan_filter(vsi,vlan))
6405 return I40E_SUCCESS;
6407 mac_num = vsi->mac_num;
6410 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6411 return I40E_ERR_PARAM;
6414 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6417 PMD_DRV_LOG(ERR, "failed to allocate memory");
6418 return I40E_ERR_NO_MEMORY;
6421 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6423 if (ret != I40E_SUCCESS)
6426 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6428 if (ret != I40E_SUCCESS)
6431 i40e_set_vlan_filter(vsi, vlan, 1);
6441 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6443 struct i40e_macvlan_filter *mv_f;
6445 int ret = I40E_SUCCESS;
6448 * Vlan 0 is the generic filter for untagged packets
6449 * and can't be removed.
6451 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6452 return I40E_ERR_PARAM;
6454 /* If can't find it, just return */
6455 if (!i40e_find_vlan_filter(vsi, vlan))
6456 return I40E_ERR_PARAM;
6458 mac_num = vsi->mac_num;
6461 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6462 return I40E_ERR_PARAM;
6465 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6468 PMD_DRV_LOG(ERR, "failed to allocate memory");
6469 return I40E_ERR_NO_MEMORY;
6472 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6474 if (ret != I40E_SUCCESS)
6477 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6479 if (ret != I40E_SUCCESS)
6482 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6483 if (vsi->vlan_num == 1) {
6484 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6485 if (ret != I40E_SUCCESS)
6488 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6489 if (ret != I40E_SUCCESS)
6493 i40e_set_vlan_filter(vsi, vlan, 0);
6503 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6505 struct i40e_mac_filter *f;
6506 struct i40e_macvlan_filter *mv_f;
6507 int i, vlan_num = 0;
6508 int ret = I40E_SUCCESS;
6510 /* If it's add and we've config it, return */
6511 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6513 return I40E_SUCCESS;
6514 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6515 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6518 * If vlan_num is 0, that's the first time to add mac,
6519 * set mask for vlan_id 0.
6521 if (vsi->vlan_num == 0) {
6522 i40e_set_vlan_filter(vsi, 0, 1);
6525 vlan_num = vsi->vlan_num;
6526 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6527 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6530 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6532 PMD_DRV_LOG(ERR, "failed to allocate memory");
6533 return I40E_ERR_NO_MEMORY;
6536 for (i = 0; i < vlan_num; i++) {
6537 mv_f[i].filter_type = mac_filter->filter_type;
6538 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6542 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6543 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6544 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6545 &mac_filter->mac_addr);
6546 if (ret != I40E_SUCCESS)
6550 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6551 if (ret != I40E_SUCCESS)
6554 /* Add the mac addr into mac list */
6555 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6557 PMD_DRV_LOG(ERR, "failed to allocate memory");
6558 ret = I40E_ERR_NO_MEMORY;
6561 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6563 f->mac_info.filter_type = mac_filter->filter_type;
6564 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6575 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6577 struct i40e_mac_filter *f;
6578 struct i40e_macvlan_filter *mv_f;
6580 enum rte_mac_filter_type filter_type;
6581 int ret = I40E_SUCCESS;
6583 /* Can't find it, return an error */
6584 f = i40e_find_mac_filter(vsi, addr);
6586 return I40E_ERR_PARAM;
6588 vlan_num = vsi->vlan_num;
6589 filter_type = f->mac_info.filter_type;
6590 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6591 filter_type == RTE_MACVLAN_HASH_MATCH) {
6592 if (vlan_num == 0) {
6593 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6594 return I40E_ERR_PARAM;
6596 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6597 filter_type == RTE_MAC_HASH_MATCH)
6600 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6602 PMD_DRV_LOG(ERR, "failed to allocate memory");
6603 return I40E_ERR_NO_MEMORY;
6606 for (i = 0; i < vlan_num; i++) {
6607 mv_f[i].filter_type = filter_type;
6608 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6611 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6612 filter_type == RTE_MACVLAN_HASH_MATCH) {
6613 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6614 if (ret != I40E_SUCCESS)
6618 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6619 if (ret != I40E_SUCCESS)
6622 /* Remove the mac addr into mac list */
6623 TAILQ_REMOVE(&vsi->mac_list, f, next);
6633 /* Configure hash enable flags for RSS */
6635 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6643 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6644 if (flags & (1ULL << i))
6645 hena |= adapter->pctypes_tbl[i];
6651 /* Parse the hash enable flags */
6653 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6655 uint64_t rss_hf = 0;
6661 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6662 if (flags & adapter->pctypes_tbl[i])
6663 rss_hf |= (1ULL << i);
6670 i40e_pf_disable_rss(struct i40e_pf *pf)
6672 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6674 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6675 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6676 I40E_WRITE_FLUSH(hw);
6680 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6682 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6683 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6686 if (!key || key_len == 0) {
6687 PMD_DRV_LOG(DEBUG, "No key to be configured");
6689 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6691 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6695 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6696 struct i40e_aqc_get_set_rss_key_data *key_dw =
6697 (struct i40e_aqc_get_set_rss_key_data *)key;
6699 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6701 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6703 uint32_t *hash_key = (uint32_t *)key;
6706 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6707 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6708 I40E_WRITE_FLUSH(hw);
6715 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6717 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6718 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6721 if (!key || !key_len)
6724 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6725 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6726 (struct i40e_aqc_get_set_rss_key_data *)key);
6728 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6732 uint32_t *key_dw = (uint32_t *)key;
6735 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6736 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6738 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6744 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6750 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6751 rss_conf->rss_key_len);
6755 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6756 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6757 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6758 I40E_WRITE_FLUSH(hw);
6764 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6765 struct rte_eth_rss_conf *rss_conf)
6767 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6768 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6772 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6773 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6775 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6776 if (rss_hf != 0) /* Enable RSS */
6778 return 0; /* Nothing to do */
6781 if (rss_hf == 0) /* Disable RSS */
6784 return i40e_hw_rss_hash_set(pf, rss_conf);
6788 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6789 struct rte_eth_rss_conf *rss_conf)
6791 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6792 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6795 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6796 &rss_conf->rss_key_len);
6798 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6799 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6800 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6806 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6808 switch (filter_type) {
6809 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6810 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6812 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6813 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6815 case RTE_TUNNEL_FILTER_IMAC_TENID:
6816 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6818 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6819 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6821 case ETH_TUNNEL_FILTER_IMAC:
6822 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6824 case ETH_TUNNEL_FILTER_OIP:
6825 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6827 case ETH_TUNNEL_FILTER_IIP:
6828 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6831 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6838 /* Convert tunnel filter structure */
6840 i40e_tunnel_filter_convert(
6841 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6842 struct i40e_tunnel_filter *tunnel_filter)
6844 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6845 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6846 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6847 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6848 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6849 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6850 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6851 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6852 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6854 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6855 tunnel_filter->input.flags = cld_filter->element.flags;
6856 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6857 tunnel_filter->queue = cld_filter->element.queue_number;
6858 rte_memcpy(tunnel_filter->input.general_fields,
6859 cld_filter->general_fields,
6860 sizeof(cld_filter->general_fields));
6865 /* Check if there exists the tunnel filter */
6866 struct i40e_tunnel_filter *
6867 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6868 const struct i40e_tunnel_filter_input *input)
6872 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6876 return tunnel_rule->hash_map[ret];
6879 /* Add a tunnel filter into the SW list */
6881 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6882 struct i40e_tunnel_filter *tunnel_filter)
6884 struct i40e_tunnel_rule *rule = &pf->tunnel;
6887 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6890 "Failed to insert tunnel filter to hash table %d!",
6894 rule->hash_map[ret] = tunnel_filter;
6896 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6901 /* Delete a tunnel filter from the SW list */
6903 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6904 struct i40e_tunnel_filter_input *input)
6906 struct i40e_tunnel_rule *rule = &pf->tunnel;
6907 struct i40e_tunnel_filter *tunnel_filter;
6910 ret = rte_hash_del_key(rule->hash_table, input);
6913 "Failed to delete tunnel filter to hash table %d!",
6917 tunnel_filter = rule->hash_map[ret];
6918 rule->hash_map[ret] = NULL;
6920 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6921 rte_free(tunnel_filter);
6927 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6928 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6933 uint8_t i, tun_type = 0;
6934 /* internal varialbe to convert ipv6 byte order */
6935 uint32_t convert_ipv6[4];
6937 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6938 struct i40e_vsi *vsi = pf->main_vsi;
6939 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6940 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6941 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6942 struct i40e_tunnel_filter *tunnel, *node;
6943 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6945 cld_filter = rte_zmalloc("tunnel_filter",
6946 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6949 if (NULL == cld_filter) {
6950 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6953 pfilter = cld_filter;
6955 ether_addr_copy(&tunnel_filter->outer_mac,
6956 (struct ether_addr *)&pfilter->element.outer_mac);
6957 ether_addr_copy(&tunnel_filter->inner_mac,
6958 (struct ether_addr *)&pfilter->element.inner_mac);
6960 pfilter->element.inner_vlan =
6961 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6962 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6963 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6964 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6965 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6966 &rte_cpu_to_le_32(ipv4_addr),
6967 sizeof(pfilter->element.ipaddr.v4.data));
6969 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6970 for (i = 0; i < 4; i++) {
6972 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6974 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6976 sizeof(pfilter->element.ipaddr.v6.data));
6979 /* check tunneled type */
6980 switch (tunnel_filter->tunnel_type) {
6981 case RTE_TUNNEL_TYPE_VXLAN:
6982 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6984 case RTE_TUNNEL_TYPE_NVGRE:
6985 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6987 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6988 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6991 /* Other tunnel types is not supported. */
6992 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6993 rte_free(cld_filter);
6997 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6998 &pfilter->element.flags);
7000 rte_free(cld_filter);
7004 pfilter->element.flags |= rte_cpu_to_le_16(
7005 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7006 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7007 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7008 pfilter->element.queue_number =
7009 rte_cpu_to_le_16(tunnel_filter->queue_id);
7011 /* Check if there is the filter in SW list */
7012 memset(&check_filter, 0, sizeof(check_filter));
7013 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7014 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7016 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7020 if (!add && !node) {
7021 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7026 ret = i40e_aq_add_cloud_filters(hw,
7027 vsi->seid, &cld_filter->element, 1);
7029 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7032 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7033 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7034 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7036 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7037 &cld_filter->element, 1);
7039 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7042 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7045 rte_free(cld_filter);
7049 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7050 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7051 #define I40E_TR_GENEVE_KEY_MASK 0x8
7052 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7053 #define I40E_TR_GRE_KEY_MASK 0x400
7054 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7055 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7058 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7060 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7061 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7062 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7063 enum i40e_status_code status = I40E_SUCCESS;
7065 memset(&filter_replace, 0,
7066 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7067 memset(&filter_replace_buf, 0,
7068 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7070 /* create L1 filter */
7071 filter_replace.old_filter_type =
7072 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7073 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7074 filter_replace.tr_bit = 0;
7076 /* Prepare the buffer, 3 entries */
7077 filter_replace_buf.data[0] =
7078 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7079 filter_replace_buf.data[0] |=
7080 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7081 filter_replace_buf.data[2] = 0xFF;
7082 filter_replace_buf.data[3] = 0xFF;
7083 filter_replace_buf.data[4] =
7084 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7085 filter_replace_buf.data[4] |=
7086 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7087 filter_replace_buf.data[7] = 0xF0;
7088 filter_replace_buf.data[8]
7089 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7090 filter_replace_buf.data[8] |=
7091 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7092 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7093 I40E_TR_GENEVE_KEY_MASK |
7094 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7095 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7096 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7097 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7099 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7100 &filter_replace_buf);
7105 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7107 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7108 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7109 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7110 enum i40e_status_code status = I40E_SUCCESS;
7113 memset(&filter_replace, 0,
7114 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7115 memset(&filter_replace_buf, 0,
7116 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7117 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7118 I40E_AQC_MIRROR_CLOUD_FILTER;
7119 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7120 filter_replace.new_filter_type =
7121 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7122 /* Prepare the buffer, 2 entries */
7123 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7124 filter_replace_buf.data[0] |=
7125 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7126 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7127 filter_replace_buf.data[4] |=
7128 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7129 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7130 &filter_replace_buf);
7135 memset(&filter_replace, 0,
7136 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7137 memset(&filter_replace_buf, 0,
7138 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7140 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7141 I40E_AQC_MIRROR_CLOUD_FILTER;
7142 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7143 filter_replace.new_filter_type =
7144 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7145 /* Prepare the buffer, 2 entries */
7146 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7147 filter_replace_buf.data[0] |=
7148 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7149 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7150 filter_replace_buf.data[4] |=
7151 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7153 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7154 &filter_replace_buf);
7158 static enum i40e_status_code
7159 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7161 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7162 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7163 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7164 enum i40e_status_code status = I40E_SUCCESS;
7167 memset(&filter_replace, 0,
7168 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7169 memset(&filter_replace_buf, 0,
7170 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7171 /* create L1 filter */
7172 filter_replace.old_filter_type =
7173 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7174 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7175 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7176 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7177 /* Prepare the buffer, 2 entries */
7178 filter_replace_buf.data[0] =
7179 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7180 filter_replace_buf.data[0] |=
7181 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7182 filter_replace_buf.data[2] = 0xFF;
7183 filter_replace_buf.data[3] = 0xFF;
7184 filter_replace_buf.data[4] =
7185 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7186 filter_replace_buf.data[4] |=
7187 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7188 filter_replace_buf.data[6] = 0xFF;
7189 filter_replace_buf.data[7] = 0xFF;
7190 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7191 &filter_replace_buf);
7196 memset(&filter_replace, 0,
7197 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7198 memset(&filter_replace_buf, 0,
7199 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7200 /* create L1 filter */
7201 filter_replace.old_filter_type =
7202 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7203 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7204 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7205 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7206 /* Prepare the buffer, 2 entries */
7207 filter_replace_buf.data[0] =
7208 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7209 filter_replace_buf.data[0] |=
7210 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7211 filter_replace_buf.data[2] = 0xFF;
7212 filter_replace_buf.data[3] = 0xFF;
7213 filter_replace_buf.data[4] =
7214 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7215 filter_replace_buf.data[4] |=
7216 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7217 filter_replace_buf.data[6] = 0xFF;
7218 filter_replace_buf.data[7] = 0xFF;
7220 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7221 &filter_replace_buf);
7226 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7228 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7229 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7230 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7231 enum i40e_status_code status = I40E_SUCCESS;
7234 memset(&filter_replace, 0,
7235 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7236 memset(&filter_replace_buf, 0,
7237 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7238 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7239 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7240 filter_replace.new_filter_type =
7241 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7242 /* Prepare the buffer, 2 entries */
7243 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7244 filter_replace_buf.data[0] |=
7245 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7246 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7247 filter_replace_buf.data[4] |=
7248 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7249 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7250 &filter_replace_buf);
7255 memset(&filter_replace, 0,
7256 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7257 memset(&filter_replace_buf, 0,
7258 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7259 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7260 filter_replace.old_filter_type =
7261 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7262 filter_replace.new_filter_type =
7263 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7264 /* Prepare the buffer, 2 entries */
7265 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7266 filter_replace_buf.data[0] |=
7267 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7268 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7269 filter_replace_buf.data[4] |=
7270 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7272 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7273 &filter_replace_buf);
7278 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7279 struct i40e_tunnel_filter_conf *tunnel_filter,
7284 uint8_t i, tun_type = 0;
7285 /* internal variable to convert ipv6 byte order */
7286 uint32_t convert_ipv6[4];
7288 struct i40e_pf_vf *vf = NULL;
7289 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7290 struct i40e_vsi *vsi;
7291 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7292 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7293 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7294 struct i40e_tunnel_filter *tunnel, *node;
7295 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7297 bool big_buffer = 0;
7299 cld_filter = rte_zmalloc("tunnel_filter",
7300 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7303 if (cld_filter == NULL) {
7304 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7307 pfilter = cld_filter;
7309 ether_addr_copy(&tunnel_filter->outer_mac,
7310 (struct ether_addr *)&pfilter->element.outer_mac);
7311 ether_addr_copy(&tunnel_filter->inner_mac,
7312 (struct ether_addr *)&pfilter->element.inner_mac);
7314 pfilter->element.inner_vlan =
7315 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7316 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7317 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7318 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7319 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7320 &rte_cpu_to_le_32(ipv4_addr),
7321 sizeof(pfilter->element.ipaddr.v4.data));
7323 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7324 for (i = 0; i < 4; i++) {
7326 rte_cpu_to_le_32(rte_be_to_cpu_32(
7327 tunnel_filter->ip_addr.ipv6_addr[i]));
7329 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7331 sizeof(pfilter->element.ipaddr.v6.data));
7334 /* check tunneled type */
7335 switch (tunnel_filter->tunnel_type) {
7336 case I40E_TUNNEL_TYPE_VXLAN:
7337 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7339 case I40E_TUNNEL_TYPE_NVGRE:
7340 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7342 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7343 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7345 case I40E_TUNNEL_TYPE_MPLSoUDP:
7346 if (!pf->mpls_replace_flag) {
7347 i40e_replace_mpls_l1_filter(pf);
7348 i40e_replace_mpls_cloud_filter(pf);
7349 pf->mpls_replace_flag = 1;
7351 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7352 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7354 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7355 (teid_le & 0xF) << 12;
7356 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7359 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7361 case I40E_TUNNEL_TYPE_MPLSoGRE:
7362 if (!pf->mpls_replace_flag) {
7363 i40e_replace_mpls_l1_filter(pf);
7364 i40e_replace_mpls_cloud_filter(pf);
7365 pf->mpls_replace_flag = 1;
7367 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7368 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7370 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7371 (teid_le & 0xF) << 12;
7372 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7375 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7377 case I40E_TUNNEL_TYPE_GTPC:
7378 if (!pf->gtp_replace_flag) {
7379 i40e_replace_gtp_l1_filter(pf);
7380 i40e_replace_gtp_cloud_filter(pf);
7381 pf->gtp_replace_flag = 1;
7383 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7384 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7385 (teid_le >> 16) & 0xFFFF;
7386 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7388 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7392 case I40E_TUNNEL_TYPE_GTPU:
7393 if (!pf->gtp_replace_flag) {
7394 i40e_replace_gtp_l1_filter(pf);
7395 i40e_replace_gtp_cloud_filter(pf);
7396 pf->gtp_replace_flag = 1;
7398 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7399 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7400 (teid_le >> 16) & 0xFFFF;
7401 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7403 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7407 case I40E_TUNNEL_TYPE_QINQ:
7408 if (!pf->qinq_replace_flag) {
7409 ret = i40e_cloud_filter_qinq_create(pf);
7412 "QinQ tunnel filter already created.");
7413 pf->qinq_replace_flag = 1;
7415 /* Add in the General fields the values of
7416 * the Outer and Inner VLAN
7417 * Big Buffer should be set, see changes in
7418 * i40e_aq_add_cloud_filters
7420 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7421 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7425 /* Other tunnel types is not supported. */
7426 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7427 rte_free(cld_filter);
7431 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7432 pfilter->element.flags =
7433 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7434 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7435 pfilter->element.flags =
7436 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7437 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7438 pfilter->element.flags =
7439 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7440 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7441 pfilter->element.flags =
7442 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7443 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7444 pfilter->element.flags |=
7445 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7447 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7448 &pfilter->element.flags);
7450 rte_free(cld_filter);
7455 pfilter->element.flags |= rte_cpu_to_le_16(
7456 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7457 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7458 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7459 pfilter->element.queue_number =
7460 rte_cpu_to_le_16(tunnel_filter->queue_id);
7462 if (!tunnel_filter->is_to_vf)
7465 if (tunnel_filter->vf_id >= pf->vf_num) {
7466 PMD_DRV_LOG(ERR, "Invalid argument.");
7469 vf = &pf->vfs[tunnel_filter->vf_id];
7473 /* Check if there is the filter in SW list */
7474 memset(&check_filter, 0, sizeof(check_filter));
7475 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7476 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7477 check_filter.vf_id = tunnel_filter->vf_id;
7478 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7480 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7484 if (!add && !node) {
7485 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7491 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7492 vsi->seid, cld_filter, 1);
7494 ret = i40e_aq_add_cloud_filters(hw,
7495 vsi->seid, &cld_filter->element, 1);
7497 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7500 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7501 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7502 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7505 ret = i40e_aq_remove_cloud_filters_big_buffer(
7506 hw, vsi->seid, cld_filter, 1);
7508 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7509 &cld_filter->element, 1);
7511 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7514 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7517 rte_free(cld_filter);
7522 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7526 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7527 if (pf->vxlan_ports[i] == port)
7535 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7539 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7541 idx = i40e_get_vxlan_port_idx(pf, port);
7543 /* Check if port already exists */
7545 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7549 /* Now check if there is space to add the new port */
7550 idx = i40e_get_vxlan_port_idx(pf, 0);
7553 "Maximum number of UDP ports reached, not adding port %d",
7558 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7561 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7565 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7568 /* New port: add it and mark its index in the bitmap */
7569 pf->vxlan_ports[idx] = port;
7570 pf->vxlan_bitmap |= (1 << idx);
7572 if (!(pf->flags & I40E_FLAG_VXLAN))
7573 pf->flags |= I40E_FLAG_VXLAN;
7579 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7582 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7584 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7585 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7589 idx = i40e_get_vxlan_port_idx(pf, port);
7592 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7596 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7597 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7601 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7604 pf->vxlan_ports[idx] = 0;
7605 pf->vxlan_bitmap &= ~(1 << idx);
7607 if (!pf->vxlan_bitmap)
7608 pf->flags &= ~I40E_FLAG_VXLAN;
7613 /* Add UDP tunneling port */
7615 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7616 struct rte_eth_udp_tunnel *udp_tunnel)
7619 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7621 if (udp_tunnel == NULL)
7624 switch (udp_tunnel->prot_type) {
7625 case RTE_TUNNEL_TYPE_VXLAN:
7626 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7629 case RTE_TUNNEL_TYPE_GENEVE:
7630 case RTE_TUNNEL_TYPE_TEREDO:
7631 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7636 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7644 /* Remove UDP tunneling port */
7646 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7647 struct rte_eth_udp_tunnel *udp_tunnel)
7650 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7652 if (udp_tunnel == NULL)
7655 switch (udp_tunnel->prot_type) {
7656 case RTE_TUNNEL_TYPE_VXLAN:
7657 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7659 case RTE_TUNNEL_TYPE_GENEVE:
7660 case RTE_TUNNEL_TYPE_TEREDO:
7661 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7665 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7673 /* Calculate the maximum number of contiguous PF queues that are configured */
7675 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7677 struct rte_eth_dev_data *data = pf->dev_data;
7679 struct i40e_rx_queue *rxq;
7682 for (i = 0; i < pf->lan_nb_qps; i++) {
7683 rxq = data->rx_queues[i];
7684 if (rxq && rxq->q_set)
7695 i40e_pf_config_rss(struct i40e_pf *pf)
7697 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7698 struct rte_eth_rss_conf rss_conf;
7699 uint32_t i, lut = 0;
7703 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7704 * It's necessary to calculate the actual PF queues that are configured.
7706 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7707 num = i40e_pf_calc_configured_queues_num(pf);
7709 num = pf->dev_data->nb_rx_queues;
7711 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7712 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7716 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7720 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7723 lut = (lut << 8) | (j & ((0x1 <<
7724 hw->func_caps.rss_table_entry_width) - 1));
7726 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7729 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7730 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7731 i40e_pf_disable_rss(pf);
7734 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7735 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7736 /* Random default keys */
7737 static uint32_t rss_key_default[] = {0x6b793944,
7738 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7739 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7740 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7742 rss_conf.rss_key = (uint8_t *)rss_key_default;
7743 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7747 return i40e_hw_rss_hash_set(pf, &rss_conf);
7751 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7752 struct rte_eth_tunnel_filter_conf *filter)
7754 if (pf == NULL || filter == NULL) {
7755 PMD_DRV_LOG(ERR, "Invalid parameter");
7759 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7760 PMD_DRV_LOG(ERR, "Invalid queue ID");
7764 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7765 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7769 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7770 (is_zero_ether_addr(&filter->outer_mac))) {
7771 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7775 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7776 (is_zero_ether_addr(&filter->inner_mac))) {
7777 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7784 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7785 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7787 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7792 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7793 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7796 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7797 } else if (len == 4) {
7798 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7800 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7805 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7812 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7813 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7819 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7826 switch (cfg->cfg_type) {
7827 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7828 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7831 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7839 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7840 enum rte_filter_op filter_op,
7843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7844 int ret = I40E_ERR_PARAM;
7846 switch (filter_op) {
7847 case RTE_ETH_FILTER_SET:
7848 ret = i40e_dev_global_config_set(hw,
7849 (struct rte_eth_global_cfg *)arg);
7852 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7860 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7861 enum rte_filter_op filter_op,
7864 struct rte_eth_tunnel_filter_conf *filter;
7865 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7866 int ret = I40E_SUCCESS;
7868 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7870 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7871 return I40E_ERR_PARAM;
7873 switch (filter_op) {
7874 case RTE_ETH_FILTER_NOP:
7875 if (!(pf->flags & I40E_FLAG_VXLAN))
7876 ret = I40E_NOT_SUPPORTED;
7878 case RTE_ETH_FILTER_ADD:
7879 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7881 case RTE_ETH_FILTER_DELETE:
7882 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7885 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7886 ret = I40E_ERR_PARAM;
7894 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7897 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7900 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7901 ret = i40e_pf_config_rss(pf);
7903 i40e_pf_disable_rss(pf);
7908 /* Get the symmetric hash enable configurations per port */
7910 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7912 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7914 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7917 /* Set the symmetric hash enable configurations per port */
7919 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7921 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7924 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7926 "Symmetric hash has already been enabled");
7929 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7931 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7933 "Symmetric hash has already been disabled");
7936 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7938 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7939 I40E_WRITE_FLUSH(hw);
7943 * Get global configurations of hash function type and symmetric hash enable
7944 * per flow type (pctype). Note that global configuration means it affects all
7945 * the ports on the same NIC.
7948 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7949 struct rte_eth_hash_global_conf *g_cfg)
7951 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7955 memset(g_cfg, 0, sizeof(*g_cfg));
7956 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7957 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7958 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7960 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7961 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7962 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7965 * We work only with lowest 32 bits which is not correct, but to work
7966 * properly the valid_bit_mask size should be increased up to 64 bits
7967 * and this will brake ABI. This modification will be done in next
7970 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7972 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7973 if (!adapter->pctypes_tbl[i])
7975 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7976 j < I40E_FILTER_PCTYPE_MAX; j++) {
7977 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7978 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7979 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7980 g_cfg->sym_hash_enable_mask[0] |=
7991 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7992 const struct rte_eth_hash_global_conf *g_cfg)
7995 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
7997 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7998 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7999 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8000 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8006 * As i40e supports less than 32 flow types, only first 32 bits need to
8009 mask0 = g_cfg->valid_bit_mask[0];
8010 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8012 /* Check if any unsupported flow type configured */
8013 if ((mask0 | i40e_mask) ^ i40e_mask)
8016 if (g_cfg->valid_bit_mask[i])
8024 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8030 * Set global configurations of hash function type and symmetric hash enable
8031 * per flow type (pctype). Note any modifying global configuration will affect
8032 * all the ports on the same NIC.
8035 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8036 struct rte_eth_hash_global_conf *g_cfg)
8038 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8043 * We work only with lowest 32 bits which is not correct, but to work
8044 * properly the valid_bit_mask size should be increased up to 64 bits
8045 * and this will brake ABI. This modification will be done in next
8048 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8049 (uint32_t)adapter->flow_types_mask;
8051 /* Check the input parameters */
8052 ret = i40e_hash_global_config_check(adapter, g_cfg);
8056 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8057 if (mask0 & (1UL << i)) {
8058 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8059 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8061 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8062 j < I40E_FILTER_PCTYPE_MAX; j++) {
8063 if (adapter->pctypes_tbl[i] & (1ULL << j))
8064 i40e_write_rx_ctl(hw,
8071 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8072 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8074 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8076 "Hash function already set to Toeplitz");
8079 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8080 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8082 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8084 "Hash function already set to Simple XOR");
8087 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8089 /* Use the default, and keep it as it is */
8092 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8095 I40E_WRITE_FLUSH(hw);
8101 * Valid input sets for hash and flow director filters per PCTYPE
8104 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8105 enum rte_filter_type filter)
8109 static const uint64_t valid_hash_inset_table[] = {
8110 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8111 I40E_INSET_DMAC | I40E_INSET_SMAC |
8112 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8113 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8114 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8115 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8116 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8117 I40E_INSET_FLEX_PAYLOAD,
8118 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8119 I40E_INSET_DMAC | I40E_INSET_SMAC |
8120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8121 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8122 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8123 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8124 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8125 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8126 I40E_INSET_FLEX_PAYLOAD,
8127 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8128 I40E_INSET_DMAC | I40E_INSET_SMAC |
8129 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8130 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8131 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8132 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8133 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8134 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8135 I40E_INSET_FLEX_PAYLOAD,
8136 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8137 I40E_INSET_DMAC | I40E_INSET_SMAC |
8138 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8139 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8140 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8141 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8142 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8143 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8144 I40E_INSET_FLEX_PAYLOAD,
8145 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8146 I40E_INSET_DMAC | I40E_INSET_SMAC |
8147 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8149 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8150 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8151 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8152 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8153 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8154 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8155 I40E_INSET_DMAC | I40E_INSET_SMAC |
8156 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8157 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8158 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8159 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8160 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8161 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8162 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8163 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8164 I40E_INSET_DMAC | I40E_INSET_SMAC |
8165 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8166 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8167 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8168 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8169 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8170 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8171 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8172 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8173 I40E_INSET_DMAC | I40E_INSET_SMAC |
8174 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8175 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8176 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8177 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8178 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8179 I40E_INSET_FLEX_PAYLOAD,
8180 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8181 I40E_INSET_DMAC | I40E_INSET_SMAC |
8182 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8183 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8184 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8185 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8186 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8187 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8188 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8189 I40E_INSET_DMAC | I40E_INSET_SMAC |
8190 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8191 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8192 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8193 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8194 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8195 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8196 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8197 I40E_INSET_DMAC | I40E_INSET_SMAC |
8198 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8200 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8201 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8202 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8203 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8204 I40E_INSET_FLEX_PAYLOAD,
8205 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8206 I40E_INSET_DMAC | I40E_INSET_SMAC |
8207 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8208 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8209 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8210 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8211 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8212 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8213 I40E_INSET_FLEX_PAYLOAD,
8214 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8215 I40E_INSET_DMAC | I40E_INSET_SMAC |
8216 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8217 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8218 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8219 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8220 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8221 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8222 I40E_INSET_FLEX_PAYLOAD,
8223 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8224 I40E_INSET_DMAC | I40E_INSET_SMAC |
8225 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8226 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8227 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8228 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8229 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8230 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8231 I40E_INSET_FLEX_PAYLOAD,
8232 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8233 I40E_INSET_DMAC | I40E_INSET_SMAC |
8234 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8235 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8236 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8237 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8238 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8239 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8240 I40E_INSET_FLEX_PAYLOAD,
8241 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8242 I40E_INSET_DMAC | I40E_INSET_SMAC |
8243 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8244 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8245 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8246 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8247 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8248 I40E_INSET_FLEX_PAYLOAD,
8249 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8250 I40E_INSET_DMAC | I40E_INSET_SMAC |
8251 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8252 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8253 I40E_INSET_FLEX_PAYLOAD,
8257 * Flow director supports only fields defined in
8258 * union rte_eth_fdir_flow.
8260 static const uint64_t valid_fdir_inset_table[] = {
8261 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8262 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8263 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8264 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8265 I40E_INSET_IPV4_TTL,
8266 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8267 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8268 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8269 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8270 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8271 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8272 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8273 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8274 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8275 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8276 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8277 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8278 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8279 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8280 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8281 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8282 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8283 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8284 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8285 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8286 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8287 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8288 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8290 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8291 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8292 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8293 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8294 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8297 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8298 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8299 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8300 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8301 I40E_INSET_IPV4_TTL,
8302 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8303 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8304 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8305 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8306 I40E_INSET_IPV6_HOP_LIMIT,
8307 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8308 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8309 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8310 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8311 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8312 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8313 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8315 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8316 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8317 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8318 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8319 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8320 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8321 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8322 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8323 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8324 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8325 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8326 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8327 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8328 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8329 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8330 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8331 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8332 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8333 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8334 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8335 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8336 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8338 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8339 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8340 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8341 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8342 I40E_INSET_IPV6_HOP_LIMIT,
8343 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8344 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345 I40E_INSET_LAST_ETHER_TYPE,
8348 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8350 if (filter == RTE_ETH_FILTER_HASH)
8351 valid = valid_hash_inset_table[pctype];
8353 valid = valid_fdir_inset_table[pctype];
8359 * Validate if the input set is allowed for a specific PCTYPE
8362 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8363 enum rte_filter_type filter, uint64_t inset)
8367 valid = i40e_get_valid_input_set(pctype, filter);
8368 if (inset & (~valid))
8374 /* default input set fields combination per pctype */
8376 i40e_get_default_input_set(uint16_t pctype)
8378 static const uint64_t default_inset_table[] = {
8379 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8380 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8381 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8382 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8383 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8384 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8385 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8386 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8387 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8388 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8389 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8390 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8391 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8392 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8393 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8394 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8395 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8396 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8397 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8398 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8400 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8401 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8402 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8403 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8404 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8405 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8406 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8407 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8408 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8409 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8410 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8411 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8412 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8413 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8414 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8415 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8416 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8417 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8418 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8419 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8420 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8421 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8423 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8424 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8425 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8426 I40E_INSET_LAST_ETHER_TYPE,
8429 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8432 return default_inset_table[pctype];
8436 * Parse the input set from index to logical bit masks
8439 i40e_parse_input_set(uint64_t *inset,
8440 enum i40e_filter_pctype pctype,
8441 enum rte_eth_input_set_field *field,
8447 static const struct {
8448 enum rte_eth_input_set_field field;
8450 } inset_convert_table[] = {
8451 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8452 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8453 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8454 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8455 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8456 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8457 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8458 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8459 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8460 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8461 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8462 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8463 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8464 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8465 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8466 I40E_INSET_IPV6_NEXT_HDR},
8467 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8468 I40E_INSET_IPV6_HOP_LIMIT},
8469 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8470 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8471 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8472 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8473 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8474 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8475 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8476 I40E_INSET_SCTP_VT},
8477 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8478 I40E_INSET_TUNNEL_DMAC},
8479 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8480 I40E_INSET_VLAN_TUNNEL},
8481 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8482 I40E_INSET_TUNNEL_ID},
8483 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8484 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8485 I40E_INSET_FLEX_PAYLOAD_W1},
8486 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8487 I40E_INSET_FLEX_PAYLOAD_W2},
8488 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8489 I40E_INSET_FLEX_PAYLOAD_W3},
8490 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8491 I40E_INSET_FLEX_PAYLOAD_W4},
8492 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8493 I40E_INSET_FLEX_PAYLOAD_W5},
8494 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8495 I40E_INSET_FLEX_PAYLOAD_W6},
8496 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8497 I40E_INSET_FLEX_PAYLOAD_W7},
8498 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8499 I40E_INSET_FLEX_PAYLOAD_W8},
8502 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8505 /* Only one item allowed for default or all */
8507 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8508 *inset = i40e_get_default_input_set(pctype);
8510 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8511 *inset = I40E_INSET_NONE;
8516 for (i = 0, *inset = 0; i < size; i++) {
8517 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8518 if (field[i] == inset_convert_table[j].field) {
8519 *inset |= inset_convert_table[j].inset;
8524 /* It contains unsupported input set, return immediately */
8525 if (j == RTE_DIM(inset_convert_table))
8533 * Translate the input set from bit masks to register aware bit masks
8537 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8547 static const struct inset_map inset_map_common[] = {
8548 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8549 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8550 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8551 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8552 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8553 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8554 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8555 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8556 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8557 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8558 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8559 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8560 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8561 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8562 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8563 {I40E_INSET_TUNNEL_DMAC,
8564 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8565 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8566 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8567 {I40E_INSET_TUNNEL_SRC_PORT,
8568 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8569 {I40E_INSET_TUNNEL_DST_PORT,
8570 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8571 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8572 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8573 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8574 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8575 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8576 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8577 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8578 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8579 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8582 /* some different registers map in x722*/
8583 static const struct inset_map inset_map_diff_x722[] = {
8584 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8585 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8586 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8587 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8590 static const struct inset_map inset_map_diff_not_x722[] = {
8591 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8592 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8593 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8594 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8600 /* Translate input set to register aware inset */
8601 if (type == I40E_MAC_X722) {
8602 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8603 if (input & inset_map_diff_x722[i].inset)
8604 val |= inset_map_diff_x722[i].inset_reg;
8607 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8608 if (input & inset_map_diff_not_x722[i].inset)
8609 val |= inset_map_diff_not_x722[i].inset_reg;
8613 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8614 if (input & inset_map_common[i].inset)
8615 val |= inset_map_common[i].inset_reg;
8622 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8625 uint64_t inset_need_mask = inset;
8627 static const struct {
8630 } inset_mask_map[] = {
8631 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8632 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8633 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8634 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8635 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8636 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8637 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8638 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8641 if (!inset || !mask || !nb_elem)
8644 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8645 /* Clear the inset bit, if no MASK is required,
8646 * for example proto + ttl
8648 if ((inset & inset_mask_map[i].inset) ==
8649 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8650 inset_need_mask &= ~inset_mask_map[i].inset;
8651 if (!inset_need_mask)
8654 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8655 if ((inset_need_mask & inset_mask_map[i].inset) ==
8656 inset_mask_map[i].inset) {
8657 if (idx >= nb_elem) {
8658 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8661 mask[idx] = inset_mask_map[i].mask;
8670 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8672 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8674 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8676 i40e_write_rx_ctl(hw, addr, val);
8677 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8678 (uint32_t)i40e_read_rx_ctl(hw, addr));
8682 i40e_filter_input_set_init(struct i40e_pf *pf)
8684 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8685 enum i40e_filter_pctype pctype;
8686 uint64_t input_set, inset_reg;
8687 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8691 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8692 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8693 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8695 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8698 input_set = i40e_get_default_input_set(pctype);
8700 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8701 I40E_INSET_MASK_NUM_REG);
8704 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8707 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8708 (uint32_t)(inset_reg & UINT32_MAX));
8709 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8710 (uint32_t)((inset_reg >>
8711 I40E_32_BIT_WIDTH) & UINT32_MAX));
8712 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8713 (uint32_t)(inset_reg & UINT32_MAX));
8714 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8715 (uint32_t)((inset_reg >>
8716 I40E_32_BIT_WIDTH) & UINT32_MAX));
8718 for (i = 0; i < num; i++) {
8719 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8721 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8724 /*clear unused mask registers of the pctype */
8725 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8726 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8728 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8731 I40E_WRITE_FLUSH(hw);
8733 /* store the default input set */
8734 pf->hash_input_set[pctype] = input_set;
8735 pf->fdir.input_set[pctype] = input_set;
8740 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8741 struct rte_eth_input_set_conf *conf)
8743 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8744 enum i40e_filter_pctype pctype;
8745 uint64_t input_set, inset_reg = 0;
8746 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8750 PMD_DRV_LOG(ERR, "Invalid pointer");
8753 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8754 conf->op != RTE_ETH_INPUT_SET_ADD) {
8755 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8759 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8760 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8761 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8765 if (hw->mac.type == I40E_MAC_X722) {
8766 /* get translated pctype value in fd pctype register */
8767 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8768 I40E_GLQF_FD_PCTYPES((int)pctype));
8771 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8774 PMD_DRV_LOG(ERR, "Failed to parse input set");
8778 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8779 /* get inset value in register */
8780 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8781 inset_reg <<= I40E_32_BIT_WIDTH;
8782 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8783 input_set |= pf->hash_input_set[pctype];
8785 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8786 I40E_INSET_MASK_NUM_REG);
8790 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8792 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8793 (uint32_t)(inset_reg & UINT32_MAX));
8794 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8795 (uint32_t)((inset_reg >>
8796 I40E_32_BIT_WIDTH) & UINT32_MAX));
8798 for (i = 0; i < num; i++)
8799 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8801 /*clear unused mask registers of the pctype */
8802 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8803 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8805 I40E_WRITE_FLUSH(hw);
8807 pf->hash_input_set[pctype] = input_set;
8812 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8813 struct rte_eth_input_set_conf *conf)
8815 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8816 enum i40e_filter_pctype pctype;
8817 uint64_t input_set, inset_reg = 0;
8818 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8822 PMD_DRV_LOG(ERR, "Invalid pointer");
8825 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8826 conf->op != RTE_ETH_INPUT_SET_ADD) {
8827 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8831 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8833 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8834 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8838 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8841 PMD_DRV_LOG(ERR, "Failed to parse input set");
8845 /* get inset value in register */
8846 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8847 inset_reg <<= I40E_32_BIT_WIDTH;
8848 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8850 /* Can not change the inset reg for flex payload for fdir,
8851 * it is done by writing I40E_PRTQF_FD_FLXINSET
8852 * in i40e_set_flex_mask_on_pctype.
8854 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8855 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8857 input_set |= pf->fdir.input_set[pctype];
8858 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8859 I40E_INSET_MASK_NUM_REG);
8863 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8865 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8866 (uint32_t)(inset_reg & UINT32_MAX));
8867 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8868 (uint32_t)((inset_reg >>
8869 I40E_32_BIT_WIDTH) & UINT32_MAX));
8871 for (i = 0; i < num; i++)
8872 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8874 /*clear unused mask registers of the pctype */
8875 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8876 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8878 I40E_WRITE_FLUSH(hw);
8880 pf->fdir.input_set[pctype] = input_set;
8885 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8890 PMD_DRV_LOG(ERR, "Invalid pointer");
8894 switch (info->info_type) {
8895 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8896 i40e_get_symmetric_hash_enable_per_port(hw,
8897 &(info->info.enable));
8899 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8900 ret = i40e_get_hash_filter_global_config(hw,
8901 &(info->info.global_conf));
8904 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8914 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8919 PMD_DRV_LOG(ERR, "Invalid pointer");
8923 switch (info->info_type) {
8924 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8925 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8927 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8928 ret = i40e_set_hash_filter_global_config(hw,
8929 &(info->info.global_conf));
8931 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8932 ret = i40e_hash_filter_inset_select(hw,
8933 &(info->info.input_set_conf));
8937 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8946 /* Operations for hash function */
8948 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8949 enum rte_filter_op filter_op,
8952 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8955 switch (filter_op) {
8956 case RTE_ETH_FILTER_NOP:
8958 case RTE_ETH_FILTER_GET:
8959 ret = i40e_hash_filter_get(hw,
8960 (struct rte_eth_hash_filter_info *)arg);
8962 case RTE_ETH_FILTER_SET:
8963 ret = i40e_hash_filter_set(hw,
8964 (struct rte_eth_hash_filter_info *)arg);
8967 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8976 /* Convert ethertype filter structure */
8978 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8979 struct i40e_ethertype_filter *filter)
8981 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8982 filter->input.ether_type = input->ether_type;
8983 filter->flags = input->flags;
8984 filter->queue = input->queue;
8989 /* Check if there exists the ehtertype filter */
8990 struct i40e_ethertype_filter *
8991 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8992 const struct i40e_ethertype_filter_input *input)
8996 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9000 return ethertype_rule->hash_map[ret];
9003 /* Add ethertype filter in SW list */
9005 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9006 struct i40e_ethertype_filter *filter)
9008 struct i40e_ethertype_rule *rule = &pf->ethertype;
9011 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9014 "Failed to insert ethertype filter"
9015 " to hash table %d!",
9019 rule->hash_map[ret] = filter;
9021 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9026 /* Delete ethertype filter in SW list */
9028 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9029 struct i40e_ethertype_filter_input *input)
9031 struct i40e_ethertype_rule *rule = &pf->ethertype;
9032 struct i40e_ethertype_filter *filter;
9035 ret = rte_hash_del_key(rule->hash_table, input);
9038 "Failed to delete ethertype filter"
9039 " to hash table %d!",
9043 filter = rule->hash_map[ret];
9044 rule->hash_map[ret] = NULL;
9046 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9053 * Configure ethertype filter, which can director packet by filtering
9054 * with mac address and ether_type or only ether_type
9057 i40e_ethertype_filter_set(struct i40e_pf *pf,
9058 struct rte_eth_ethertype_filter *filter,
9061 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9062 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9063 struct i40e_ethertype_filter *ethertype_filter, *node;
9064 struct i40e_ethertype_filter check_filter;
9065 struct i40e_control_filter_stats stats;
9069 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9070 PMD_DRV_LOG(ERR, "Invalid queue ID");
9073 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9074 filter->ether_type == ETHER_TYPE_IPv6) {
9076 "unsupported ether_type(0x%04x) in control packet filter.",
9077 filter->ether_type);
9080 if (filter->ether_type == ETHER_TYPE_VLAN)
9081 PMD_DRV_LOG(WARNING,
9082 "filter vlan ether_type in first tag is not supported.");
9084 /* Check if there is the filter in SW list */
9085 memset(&check_filter, 0, sizeof(check_filter));
9086 i40e_ethertype_filter_convert(filter, &check_filter);
9087 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9088 &check_filter.input);
9090 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9094 if (!add && !node) {
9095 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9099 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9100 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9101 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9102 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9103 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9105 memset(&stats, 0, sizeof(stats));
9106 ret = i40e_aq_add_rem_control_packet_filter(hw,
9107 filter->mac_addr.addr_bytes,
9108 filter->ether_type, flags,
9110 filter->queue, add, &stats, NULL);
9113 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9114 ret, stats.mac_etype_used, stats.etype_used,
9115 stats.mac_etype_free, stats.etype_free);
9119 /* Add or delete a filter in SW list */
9121 ethertype_filter = rte_zmalloc("ethertype_filter",
9122 sizeof(*ethertype_filter), 0);
9123 rte_memcpy(ethertype_filter, &check_filter,
9124 sizeof(check_filter));
9125 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9127 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9134 * Handle operations for ethertype filter.
9137 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9138 enum rte_filter_op filter_op,
9141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9144 if (filter_op == RTE_ETH_FILTER_NOP)
9148 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9153 switch (filter_op) {
9154 case RTE_ETH_FILTER_ADD:
9155 ret = i40e_ethertype_filter_set(pf,
9156 (struct rte_eth_ethertype_filter *)arg,
9159 case RTE_ETH_FILTER_DELETE:
9160 ret = i40e_ethertype_filter_set(pf,
9161 (struct rte_eth_ethertype_filter *)arg,
9165 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9173 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9174 enum rte_filter_type filter_type,
9175 enum rte_filter_op filter_op,
9183 switch (filter_type) {
9184 case RTE_ETH_FILTER_NONE:
9185 /* For global configuration */
9186 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9188 case RTE_ETH_FILTER_HASH:
9189 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9191 case RTE_ETH_FILTER_MACVLAN:
9192 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9194 case RTE_ETH_FILTER_ETHERTYPE:
9195 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9197 case RTE_ETH_FILTER_TUNNEL:
9198 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9200 case RTE_ETH_FILTER_FDIR:
9201 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9203 case RTE_ETH_FILTER_GENERIC:
9204 if (filter_op != RTE_ETH_FILTER_GET)
9206 *(const void **)arg = &i40e_flow_ops;
9209 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9219 * Check and enable Extended Tag.
9220 * Enabling Extended Tag is important for 40G performance.
9223 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9225 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9229 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9232 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9236 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9237 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9242 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9245 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9249 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9250 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9253 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9254 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9257 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9264 * As some registers wouldn't be reset unless a global hardware reset,
9265 * hardware initialization is needed to put those registers into an
9266 * expected initial state.
9269 i40e_hw_init(struct rte_eth_dev *dev)
9271 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9273 i40e_enable_extended_tag(dev);
9275 /* clear the PF Queue Filter control register */
9276 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9278 /* Disable symmetric hash per port */
9279 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9283 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9284 * however this function will return only one highest pctype index,
9285 * which is not quite correct. This is known problem of i40e driver
9286 * and needs to be fixed later.
9288 enum i40e_filter_pctype
9289 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9292 uint64_t pctype_mask;
9294 if (flow_type < I40E_FLOW_TYPE_MAX) {
9295 pctype_mask = adapter->pctypes_tbl[flow_type];
9296 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9297 if (pctype_mask & (1ULL << i))
9298 return (enum i40e_filter_pctype)i;
9301 return I40E_FILTER_PCTYPE_INVALID;
9305 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9306 enum i40e_filter_pctype pctype)
9309 uint64_t pctype_mask = 1ULL << pctype;
9311 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9313 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9317 return RTE_ETH_FLOW_UNKNOWN;
9321 * On X710, performance number is far from the expectation on recent firmware
9322 * versions; on XL710, performance number is also far from the expectation on
9323 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9324 * mode is enabled and port MAC address is equal to the packet destination MAC
9325 * address. The fix for this issue may not be integrated in the following
9326 * firmware version. So the workaround in software driver is needed. It needs
9327 * to modify the initial values of 3 internal only registers for both X710 and
9328 * XL710. Note that the values for X710 or XL710 could be different, and the
9329 * workaround can be removed when it is fixed in firmware in the future.
9332 /* For both X710 and XL710 */
9333 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9334 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9335 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9337 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9338 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9341 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9342 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9345 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9347 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9348 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9351 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9353 enum i40e_status_code status;
9354 struct i40e_aq_get_phy_abilities_resp phy_ab;
9358 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9362 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9365 rte_delay_us(100000);
9367 status = i40e_aq_get_phy_capabilities(hw, false,
9368 true, &phy_ab, NULL);
9376 i40e_configure_registers(struct i40e_hw *hw)
9382 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9383 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9384 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9390 for (i = 0; i < RTE_DIM(reg_table); i++) {
9391 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9392 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9394 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9395 else /* For X710/XL710/XXV710 */
9396 if (hw->aq.fw_maj_ver < 6)
9398 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9401 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9404 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9405 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9407 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9408 else /* For X710/XL710/XXV710 */
9410 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9413 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9414 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9415 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9417 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9420 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9423 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9426 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9430 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9431 reg_table[i].addr, reg);
9432 if (reg == reg_table[i].val)
9435 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9436 reg_table[i].val, NULL);
9439 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9440 reg_table[i].val, reg_table[i].addr);
9443 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9444 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9448 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9449 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9450 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9451 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9453 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9458 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9459 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9463 /* Configure for double VLAN RX stripping */
9464 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9465 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9466 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9467 ret = i40e_aq_debug_write_register(hw,
9468 I40E_VSI_TSR(vsi->vsi_id),
9471 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9473 return I40E_ERR_CONFIG;
9477 /* Configure for double VLAN TX insertion */
9478 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9479 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9480 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9481 ret = i40e_aq_debug_write_register(hw,
9482 I40E_VSI_L2TAGSTXVALID(
9483 vsi->vsi_id), reg, NULL);
9486 "Failed to update VSI_L2TAGSTXVALID[%d]",
9488 return I40E_ERR_CONFIG;
9496 * i40e_aq_add_mirror_rule
9497 * @hw: pointer to the hardware structure
9498 * @seid: VEB seid to add mirror rule to
9499 * @dst_id: destination vsi seid
9500 * @entries: Buffer which contains the entities to be mirrored
9501 * @count: number of entities contained in the buffer
9502 * @rule_id:the rule_id of the rule to be added
9504 * Add a mirror rule for a given veb.
9507 static enum i40e_status_code
9508 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9509 uint16_t seid, uint16_t dst_id,
9510 uint16_t rule_type, uint16_t *entries,
9511 uint16_t count, uint16_t *rule_id)
9513 struct i40e_aq_desc desc;
9514 struct i40e_aqc_add_delete_mirror_rule cmd;
9515 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9516 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9519 enum i40e_status_code status;
9521 i40e_fill_default_direct_cmd_desc(&desc,
9522 i40e_aqc_opc_add_mirror_rule);
9523 memset(&cmd, 0, sizeof(cmd));
9525 buff_len = sizeof(uint16_t) * count;
9526 desc.datalen = rte_cpu_to_le_16(buff_len);
9528 desc.flags |= rte_cpu_to_le_16(
9529 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9530 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9531 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9532 cmd.num_entries = rte_cpu_to_le_16(count);
9533 cmd.seid = rte_cpu_to_le_16(seid);
9534 cmd.destination = rte_cpu_to_le_16(dst_id);
9536 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9537 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9539 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9540 hw->aq.asq_last_status, resp->rule_id,
9541 resp->mirror_rules_used, resp->mirror_rules_free);
9542 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9548 * i40e_aq_del_mirror_rule
9549 * @hw: pointer to the hardware structure
9550 * @seid: VEB seid to add mirror rule to
9551 * @entries: Buffer which contains the entities to be mirrored
9552 * @count: number of entities contained in the buffer
9553 * @rule_id:the rule_id of the rule to be delete
9555 * Delete a mirror rule for a given veb.
9558 static enum i40e_status_code
9559 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9560 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9561 uint16_t count, uint16_t rule_id)
9563 struct i40e_aq_desc desc;
9564 struct i40e_aqc_add_delete_mirror_rule cmd;
9565 uint16_t buff_len = 0;
9566 enum i40e_status_code status;
9569 i40e_fill_default_direct_cmd_desc(&desc,
9570 i40e_aqc_opc_delete_mirror_rule);
9571 memset(&cmd, 0, sizeof(cmd));
9572 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9573 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9575 cmd.num_entries = count;
9576 buff_len = sizeof(uint16_t) * count;
9577 desc.datalen = rte_cpu_to_le_16(buff_len);
9578 buff = (void *)entries;
9580 /* rule id is filled in destination field for deleting mirror rule */
9581 cmd.destination = rte_cpu_to_le_16(rule_id);
9583 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9584 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9585 cmd.seid = rte_cpu_to_le_16(seid);
9587 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9588 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9594 * i40e_mirror_rule_set
9595 * @dev: pointer to the hardware structure
9596 * @mirror_conf: mirror rule info
9597 * @sw_id: mirror rule's sw_id
9598 * @on: enable/disable
9600 * set a mirror rule.
9604 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9605 struct rte_eth_mirror_conf *mirror_conf,
9606 uint8_t sw_id, uint8_t on)
9608 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9609 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9610 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9611 struct i40e_mirror_rule *parent = NULL;
9612 uint16_t seid, dst_seid, rule_id;
9616 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9618 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9620 "mirror rule can not be configured without veb or vfs.");
9623 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9624 PMD_DRV_LOG(ERR, "mirror table is full.");
9627 if (mirror_conf->dst_pool > pf->vf_num) {
9628 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9629 mirror_conf->dst_pool);
9633 seid = pf->main_vsi->veb->seid;
9635 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9636 if (sw_id <= it->index) {
9642 if (mirr_rule && sw_id == mirr_rule->index) {
9644 PMD_DRV_LOG(ERR, "mirror rule exists.");
9647 ret = i40e_aq_del_mirror_rule(hw, seid,
9648 mirr_rule->rule_type,
9650 mirr_rule->num_entries, mirr_rule->id);
9653 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9654 ret, hw->aq.asq_last_status);
9657 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9658 rte_free(mirr_rule);
9659 pf->nb_mirror_rule--;
9663 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9667 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9668 sizeof(struct i40e_mirror_rule) , 0);
9670 PMD_DRV_LOG(ERR, "failed to allocate memory");
9671 return I40E_ERR_NO_MEMORY;
9673 switch (mirror_conf->rule_type) {
9674 case ETH_MIRROR_VLAN:
9675 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9676 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9677 mirr_rule->entries[j] =
9678 mirror_conf->vlan.vlan_id[i];
9683 PMD_DRV_LOG(ERR, "vlan is not specified.");
9684 rte_free(mirr_rule);
9687 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9689 case ETH_MIRROR_VIRTUAL_POOL_UP:
9690 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9691 /* check if the specified pool bit is out of range */
9692 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9693 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9694 rte_free(mirr_rule);
9697 for (i = 0, j = 0; i < pf->vf_num; i++) {
9698 if (mirror_conf->pool_mask & (1ULL << i)) {
9699 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9703 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9704 /* add pf vsi to entries */
9705 mirr_rule->entries[j] = pf->main_vsi_seid;
9709 PMD_DRV_LOG(ERR, "pool is not specified.");
9710 rte_free(mirr_rule);
9713 /* egress and ingress in aq commands means from switch but not port */
9714 mirr_rule->rule_type =
9715 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9716 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9717 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9719 case ETH_MIRROR_UPLINK_PORT:
9720 /* egress and ingress in aq commands means from switch but not port*/
9721 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9723 case ETH_MIRROR_DOWNLINK_PORT:
9724 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9727 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9728 mirror_conf->rule_type);
9729 rte_free(mirr_rule);
9733 /* If the dst_pool is equal to vf_num, consider it as PF */
9734 if (mirror_conf->dst_pool == pf->vf_num)
9735 dst_seid = pf->main_vsi_seid;
9737 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9739 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9740 mirr_rule->rule_type, mirr_rule->entries,
9744 "failed to add mirror rule: ret = %d, aq_err = %d.",
9745 ret, hw->aq.asq_last_status);
9746 rte_free(mirr_rule);
9750 mirr_rule->index = sw_id;
9751 mirr_rule->num_entries = j;
9752 mirr_rule->id = rule_id;
9753 mirr_rule->dst_vsi_seid = dst_seid;
9756 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9758 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9760 pf->nb_mirror_rule++;
9765 * i40e_mirror_rule_reset
9766 * @dev: pointer to the device
9767 * @sw_id: mirror rule's sw_id
9769 * reset a mirror rule.
9773 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9775 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9776 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9777 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9781 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9783 seid = pf->main_vsi->veb->seid;
9785 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9786 if (sw_id == it->index) {
9792 ret = i40e_aq_del_mirror_rule(hw, seid,
9793 mirr_rule->rule_type,
9795 mirr_rule->num_entries, mirr_rule->id);
9798 "failed to remove mirror rule: status = %d, aq_err = %d.",
9799 ret, hw->aq.asq_last_status);
9802 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9803 rte_free(mirr_rule);
9804 pf->nb_mirror_rule--;
9806 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9813 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9815 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9816 uint64_t systim_cycles;
9818 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9819 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9822 return systim_cycles;
9826 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9831 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9832 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9839 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9844 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9845 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9852 i40e_start_timecounters(struct rte_eth_dev *dev)
9854 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9855 struct i40e_adapter *adapter =
9856 (struct i40e_adapter *)dev->data->dev_private;
9857 struct rte_eth_link link;
9858 uint32_t tsync_inc_l;
9859 uint32_t tsync_inc_h;
9861 /* Get current link speed. */
9862 memset(&link, 0, sizeof(link));
9863 i40e_dev_link_update(dev, 1);
9864 rte_i40e_dev_atomic_read_link_status(dev, &link);
9866 switch (link.link_speed) {
9867 case ETH_SPEED_NUM_40G:
9868 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9869 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9871 case ETH_SPEED_NUM_10G:
9872 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9873 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9875 case ETH_SPEED_NUM_1G:
9876 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9877 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9884 /* Set the timesync increment value. */
9885 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9886 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9888 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9889 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9890 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9892 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9893 adapter->systime_tc.cc_shift = 0;
9894 adapter->systime_tc.nsec_mask = 0;
9896 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9897 adapter->rx_tstamp_tc.cc_shift = 0;
9898 adapter->rx_tstamp_tc.nsec_mask = 0;
9900 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9901 adapter->tx_tstamp_tc.cc_shift = 0;
9902 adapter->tx_tstamp_tc.nsec_mask = 0;
9906 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9908 struct i40e_adapter *adapter =
9909 (struct i40e_adapter *)dev->data->dev_private;
9911 adapter->systime_tc.nsec += delta;
9912 adapter->rx_tstamp_tc.nsec += delta;
9913 adapter->tx_tstamp_tc.nsec += delta;
9919 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9922 struct i40e_adapter *adapter =
9923 (struct i40e_adapter *)dev->data->dev_private;
9925 ns = rte_timespec_to_ns(ts);
9927 /* Set the timecounters to a new value. */
9928 adapter->systime_tc.nsec = ns;
9929 adapter->rx_tstamp_tc.nsec = ns;
9930 adapter->tx_tstamp_tc.nsec = ns;
9936 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9938 uint64_t ns, systime_cycles;
9939 struct i40e_adapter *adapter =
9940 (struct i40e_adapter *)dev->data->dev_private;
9942 systime_cycles = i40e_read_systime_cyclecounter(dev);
9943 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9944 *ts = rte_ns_to_timespec(ns);
9950 i40e_timesync_enable(struct rte_eth_dev *dev)
9952 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9953 uint32_t tsync_ctl_l;
9954 uint32_t tsync_ctl_h;
9956 /* Stop the timesync system time. */
9957 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9958 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9959 /* Reset the timesync system time value. */
9960 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9961 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9963 i40e_start_timecounters(dev);
9965 /* Clear timesync registers. */
9966 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9967 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9968 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9969 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9970 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9971 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9973 /* Enable timestamping of PTP packets. */
9974 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9975 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9977 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9978 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9979 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9981 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9982 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9988 i40e_timesync_disable(struct rte_eth_dev *dev)
9990 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9991 uint32_t tsync_ctl_l;
9992 uint32_t tsync_ctl_h;
9994 /* Disable timestamping of transmitted PTP packets. */
9995 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9996 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9998 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9999 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10001 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10002 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10004 /* Reset the timesync increment value. */
10005 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10006 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10012 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10013 struct timespec *timestamp, uint32_t flags)
10015 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10016 struct i40e_adapter *adapter =
10017 (struct i40e_adapter *)dev->data->dev_private;
10019 uint32_t sync_status;
10020 uint32_t index = flags & 0x03;
10021 uint64_t rx_tstamp_cycles;
10024 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10025 if ((sync_status & (1 << index)) == 0)
10028 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10029 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10030 *timestamp = rte_ns_to_timespec(ns);
10036 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10037 struct timespec *timestamp)
10039 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10040 struct i40e_adapter *adapter =
10041 (struct i40e_adapter *)dev->data->dev_private;
10043 uint32_t sync_status;
10044 uint64_t tx_tstamp_cycles;
10047 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10048 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10051 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10052 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10053 *timestamp = rte_ns_to_timespec(ns);
10059 * i40e_parse_dcb_configure - parse dcb configure from user
10060 * @dev: the device being configured
10061 * @dcb_cfg: pointer of the result of parse
10062 * @*tc_map: bit map of enabled traffic classes
10064 * Returns 0 on success, negative value on failure
10067 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10068 struct i40e_dcbx_config *dcb_cfg,
10071 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10072 uint8_t i, tc_bw, bw_lf;
10074 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10076 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10077 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10078 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10082 /* assume each tc has the same bw */
10083 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10084 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10085 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10086 /* to ensure the sum of tcbw is equal to 100 */
10087 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10088 for (i = 0; i < bw_lf; i++)
10089 dcb_cfg->etscfg.tcbwtable[i]++;
10091 /* assume each tc has the same Transmission Selection Algorithm */
10092 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10093 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10095 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10096 dcb_cfg->etscfg.prioritytable[i] =
10097 dcb_rx_conf->dcb_tc[i];
10099 /* FW needs one App to configure HW */
10100 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10101 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10102 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10103 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10105 if (dcb_rx_conf->nb_tcs == 0)
10106 *tc_map = 1; /* tc0 only */
10108 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10110 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10111 dcb_cfg->pfc.willing = 0;
10112 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10113 dcb_cfg->pfc.pfcenable = *tc_map;
10119 static enum i40e_status_code
10120 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10121 struct i40e_aqc_vsi_properties_data *info,
10122 uint8_t enabled_tcmap)
10124 enum i40e_status_code ret;
10125 int i, total_tc = 0;
10126 uint16_t qpnum_per_tc, bsf, qp_idx;
10127 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10128 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10129 uint16_t used_queues;
10131 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10132 if (ret != I40E_SUCCESS)
10135 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10136 if (enabled_tcmap & (1 << i))
10141 vsi->enabled_tc = enabled_tcmap;
10143 /* different VSI has different queues assigned */
10144 if (vsi->type == I40E_VSI_MAIN)
10145 used_queues = dev_data->nb_rx_queues -
10146 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10147 else if (vsi->type == I40E_VSI_VMDQ2)
10148 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10150 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10151 return I40E_ERR_NO_AVAILABLE_VSI;
10154 qpnum_per_tc = used_queues / total_tc;
10155 /* Number of queues per enabled TC */
10156 if (qpnum_per_tc == 0) {
10157 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10158 return I40E_ERR_INVALID_QP_ID;
10160 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10161 I40E_MAX_Q_PER_TC);
10162 bsf = rte_bsf32(qpnum_per_tc);
10165 * Configure TC and queue mapping parameters, for enabled TC,
10166 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10167 * default queue will serve it.
10170 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10171 if (vsi->enabled_tc & (1 << i)) {
10172 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10173 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10174 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10175 qp_idx += qpnum_per_tc;
10177 info->tc_mapping[i] = 0;
10180 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10181 if (vsi->type == I40E_VSI_SRIOV) {
10182 info->mapping_flags |=
10183 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10184 for (i = 0; i < vsi->nb_qps; i++)
10185 info->queue_mapping[i] =
10186 rte_cpu_to_le_16(vsi->base_queue + i);
10188 info->mapping_flags |=
10189 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10190 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10192 info->valid_sections |=
10193 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10195 return I40E_SUCCESS;
10199 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10200 * @veb: VEB to be configured
10201 * @tc_map: enabled TC bitmap
10203 * Returns 0 on success, negative value on failure
10205 static enum i40e_status_code
10206 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10208 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10209 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10210 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10211 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10212 enum i40e_status_code ret = I40E_SUCCESS;
10216 /* Check if enabled_tc is same as existing or new TCs */
10217 if (veb->enabled_tc == tc_map)
10220 /* configure tc bandwidth */
10221 memset(&veb_bw, 0, sizeof(veb_bw));
10222 veb_bw.tc_valid_bits = tc_map;
10223 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10224 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10225 if (tc_map & BIT_ULL(i))
10226 veb_bw.tc_bw_share_credits[i] = 1;
10228 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10232 "AQ command Config switch_comp BW allocation per TC failed = %d",
10233 hw->aq.asq_last_status);
10237 memset(&ets_query, 0, sizeof(ets_query));
10238 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10240 if (ret != I40E_SUCCESS) {
10242 "Failed to get switch_comp ETS configuration %u",
10243 hw->aq.asq_last_status);
10246 memset(&bw_query, 0, sizeof(bw_query));
10247 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10249 if (ret != I40E_SUCCESS) {
10251 "Failed to get switch_comp bandwidth configuration %u",
10252 hw->aq.asq_last_status);
10256 /* store and print out BW info */
10257 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10258 veb->bw_info.bw_max = ets_query.tc_bw_max;
10259 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10260 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10261 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10262 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10263 I40E_16_BIT_WIDTH);
10264 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10265 veb->bw_info.bw_ets_share_credits[i] =
10266 bw_query.tc_bw_share_credits[i];
10267 veb->bw_info.bw_ets_credits[i] =
10268 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10269 /* 4 bits per TC, 4th bit is reserved */
10270 veb->bw_info.bw_ets_max[i] =
10271 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10272 RTE_LEN2MASK(3, uint8_t));
10273 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10274 veb->bw_info.bw_ets_share_credits[i]);
10275 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10276 veb->bw_info.bw_ets_credits[i]);
10277 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10278 veb->bw_info.bw_ets_max[i]);
10281 veb->enabled_tc = tc_map;
10288 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10289 * @vsi: VSI to be configured
10290 * @tc_map: enabled TC bitmap
10292 * Returns 0 on success, negative value on failure
10294 static enum i40e_status_code
10295 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10297 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10298 struct i40e_vsi_context ctxt;
10299 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10300 enum i40e_status_code ret = I40E_SUCCESS;
10303 /* Check if enabled_tc is same as existing or new TCs */
10304 if (vsi->enabled_tc == tc_map)
10307 /* configure tc bandwidth */
10308 memset(&bw_data, 0, sizeof(bw_data));
10309 bw_data.tc_valid_bits = tc_map;
10310 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10311 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10312 if (tc_map & BIT_ULL(i))
10313 bw_data.tc_bw_credits[i] = 1;
10315 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10318 "AQ command Config VSI BW allocation per TC failed = %d",
10319 hw->aq.asq_last_status);
10322 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10323 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10325 /* Update Queue Pairs Mapping for currently enabled UPs */
10326 ctxt.seid = vsi->seid;
10327 ctxt.pf_num = hw->pf_id;
10329 ctxt.uplink_seid = vsi->uplink_seid;
10330 ctxt.info = vsi->info;
10332 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10336 /* Update the VSI after updating the VSI queue-mapping information */
10337 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10339 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10340 hw->aq.asq_last_status);
10343 /* update the local VSI info with updated queue map */
10344 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10345 sizeof(vsi->info.tc_mapping));
10346 rte_memcpy(&vsi->info.queue_mapping,
10347 &ctxt.info.queue_mapping,
10348 sizeof(vsi->info.queue_mapping));
10349 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10350 vsi->info.valid_sections = 0;
10352 /* query and update current VSI BW information */
10353 ret = i40e_vsi_get_bw_config(vsi);
10356 "Failed updating vsi bw info, err %s aq_err %s",
10357 i40e_stat_str(hw, ret),
10358 i40e_aq_str(hw, hw->aq.asq_last_status));
10362 vsi->enabled_tc = tc_map;
10369 * i40e_dcb_hw_configure - program the dcb setting to hw
10370 * @pf: pf the configuration is taken on
10371 * @new_cfg: new configuration
10372 * @tc_map: enabled TC bitmap
10374 * Returns 0 on success, negative value on failure
10376 static enum i40e_status_code
10377 i40e_dcb_hw_configure(struct i40e_pf *pf,
10378 struct i40e_dcbx_config *new_cfg,
10381 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10382 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10383 struct i40e_vsi *main_vsi = pf->main_vsi;
10384 struct i40e_vsi_list *vsi_list;
10385 enum i40e_status_code ret;
10389 /* Use the FW API if FW > v4.4*/
10390 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10391 (hw->aq.fw_maj_ver >= 5))) {
10393 "FW < v4.4, can not use FW LLDP API to configure DCB");
10394 return I40E_ERR_FIRMWARE_API_VERSION;
10397 /* Check if need reconfiguration */
10398 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10399 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10400 return I40E_SUCCESS;
10403 /* Copy the new config to the current config */
10404 *old_cfg = *new_cfg;
10405 old_cfg->etsrec = old_cfg->etscfg;
10406 ret = i40e_set_dcb_config(hw);
10408 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10409 i40e_stat_str(hw, ret),
10410 i40e_aq_str(hw, hw->aq.asq_last_status));
10413 /* set receive Arbiter to RR mode and ETS scheme by default */
10414 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10415 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10416 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10417 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10418 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10419 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10420 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10421 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10422 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10423 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10424 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10425 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10426 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10428 /* get local mib to check whether it is configured correctly */
10430 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10431 /* Get Local DCB Config */
10432 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10433 &hw->local_dcbx_config);
10435 /* if Veb is created, need to update TC of it at first */
10436 if (main_vsi->veb) {
10437 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10439 PMD_INIT_LOG(WARNING,
10440 "Failed configuring TC for VEB seid=%d",
10441 main_vsi->veb->seid);
10443 /* Update each VSI */
10444 i40e_vsi_config_tc(main_vsi, tc_map);
10445 if (main_vsi->veb) {
10446 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10447 /* Beside main VSI and VMDQ VSIs, only enable default
10448 * TC for other VSIs
10450 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10451 ret = i40e_vsi_config_tc(vsi_list->vsi,
10454 ret = i40e_vsi_config_tc(vsi_list->vsi,
10455 I40E_DEFAULT_TCMAP);
10457 PMD_INIT_LOG(WARNING,
10458 "Failed configuring TC for VSI seid=%d",
10459 vsi_list->vsi->seid);
10463 return I40E_SUCCESS;
10467 * i40e_dcb_init_configure - initial dcb config
10468 * @dev: device being configured
10469 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10471 * Returns 0 on success, negative value on failure
10474 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10476 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10477 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10480 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10481 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10485 /* DCB initialization:
10486 * Update DCB configuration from the Firmware and configure
10487 * LLDP MIB change event.
10489 if (sw_dcb == TRUE) {
10490 ret = i40e_init_dcb(hw);
10491 /* If lldp agent is stopped, the return value from
10492 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10493 * adminq status. Otherwise, it should return success.
10495 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10496 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10497 memset(&hw->local_dcbx_config, 0,
10498 sizeof(struct i40e_dcbx_config));
10499 /* set dcb default configuration */
10500 hw->local_dcbx_config.etscfg.willing = 0;
10501 hw->local_dcbx_config.etscfg.maxtcs = 0;
10502 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10503 hw->local_dcbx_config.etscfg.tsatable[0] =
10505 /* all UPs mapping to TC0 */
10506 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10507 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10508 hw->local_dcbx_config.etsrec =
10509 hw->local_dcbx_config.etscfg;
10510 hw->local_dcbx_config.pfc.willing = 0;
10511 hw->local_dcbx_config.pfc.pfccap =
10512 I40E_MAX_TRAFFIC_CLASS;
10513 /* FW needs one App to configure HW */
10514 hw->local_dcbx_config.numapps = 1;
10515 hw->local_dcbx_config.app[0].selector =
10516 I40E_APP_SEL_ETHTYPE;
10517 hw->local_dcbx_config.app[0].priority = 3;
10518 hw->local_dcbx_config.app[0].protocolid =
10519 I40E_APP_PROTOID_FCOE;
10520 ret = i40e_set_dcb_config(hw);
10523 "default dcb config fails. err = %d, aq_err = %d.",
10524 ret, hw->aq.asq_last_status);
10529 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10530 ret, hw->aq.asq_last_status);
10534 ret = i40e_aq_start_lldp(hw, NULL);
10535 if (ret != I40E_SUCCESS)
10536 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10538 ret = i40e_init_dcb(hw);
10540 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10542 "HW doesn't support DCBX offload.");
10547 "DCBX configuration failed, err = %d, aq_err = %d.",
10548 ret, hw->aq.asq_last_status);
10556 * i40e_dcb_setup - setup dcb related config
10557 * @dev: device being configured
10559 * Returns 0 on success, negative value on failure
10562 i40e_dcb_setup(struct rte_eth_dev *dev)
10564 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10565 struct i40e_dcbx_config dcb_cfg;
10566 uint8_t tc_map = 0;
10569 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10570 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10574 if (pf->vf_num != 0)
10575 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10577 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10579 PMD_INIT_LOG(ERR, "invalid dcb config");
10582 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10584 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10592 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10593 struct rte_eth_dcb_info *dcb_info)
10595 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10597 struct i40e_vsi *vsi = pf->main_vsi;
10598 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10599 uint16_t bsf, tc_mapping;
10602 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10603 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10605 dcb_info->nb_tcs = 1;
10606 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10607 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10608 for (i = 0; i < dcb_info->nb_tcs; i++)
10609 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10611 /* get queue mapping if vmdq is disabled */
10612 if (!pf->nb_cfg_vmdq_vsi) {
10613 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10614 if (!(vsi->enabled_tc & (1 << i)))
10616 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10617 dcb_info->tc_queue.tc_rxq[j][i].base =
10618 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10619 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10620 dcb_info->tc_queue.tc_txq[j][i].base =
10621 dcb_info->tc_queue.tc_rxq[j][i].base;
10622 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10623 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10624 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10625 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10626 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10631 /* get queue mapping if vmdq is enabled */
10633 vsi = pf->vmdq[j].vsi;
10634 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10635 if (!(vsi->enabled_tc & (1 << i)))
10637 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10638 dcb_info->tc_queue.tc_rxq[j][i].base =
10639 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10640 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10641 dcb_info->tc_queue.tc_txq[j][i].base =
10642 dcb_info->tc_queue.tc_rxq[j][i].base;
10643 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10644 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10645 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10646 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10647 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10650 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10655 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10657 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10658 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10660 uint16_t interval =
10661 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10662 uint16_t msix_intr;
10664 msix_intr = intr_handle->intr_vec[queue_id];
10665 if (msix_intr == I40E_MISC_VEC_ID)
10666 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10667 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10668 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10669 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10671 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10674 I40E_PFINT_DYN_CTLN(msix_intr -
10675 I40E_RX_VEC_START),
10676 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10677 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10678 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10680 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10682 I40E_WRITE_FLUSH(hw);
10683 rte_intr_enable(&pci_dev->intr_handle);
10689 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10691 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10692 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10694 uint16_t msix_intr;
10696 msix_intr = intr_handle->intr_vec[queue_id];
10697 if (msix_intr == I40E_MISC_VEC_ID)
10698 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10701 I40E_PFINT_DYN_CTLN(msix_intr -
10702 I40E_RX_VEC_START),
10704 I40E_WRITE_FLUSH(hw);
10709 static int i40e_get_regs(struct rte_eth_dev *dev,
10710 struct rte_dev_reg_info *regs)
10712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10713 uint32_t *ptr_data = regs->data;
10714 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10715 const struct i40e_reg_info *reg_info;
10717 if (ptr_data == NULL) {
10718 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10719 regs->width = sizeof(uint32_t);
10723 /* The first few registers have to be read using AQ operations */
10725 while (i40e_regs_adminq[reg_idx].name) {
10726 reg_info = &i40e_regs_adminq[reg_idx++];
10727 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10729 arr_idx2 <= reg_info->count2;
10731 reg_offset = arr_idx * reg_info->stride1 +
10732 arr_idx2 * reg_info->stride2;
10733 reg_offset += reg_info->base_addr;
10734 ptr_data[reg_offset >> 2] =
10735 i40e_read_rx_ctl(hw, reg_offset);
10739 /* The remaining registers can be read using primitives */
10741 while (i40e_regs_others[reg_idx].name) {
10742 reg_info = &i40e_regs_others[reg_idx++];
10743 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10745 arr_idx2 <= reg_info->count2;
10747 reg_offset = arr_idx * reg_info->stride1 +
10748 arr_idx2 * reg_info->stride2;
10749 reg_offset += reg_info->base_addr;
10750 ptr_data[reg_offset >> 2] =
10751 I40E_READ_REG(hw, reg_offset);
10758 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10762 /* Convert word count to byte count */
10763 return hw->nvm.sr_size << 1;
10766 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10767 struct rte_dev_eeprom_info *eeprom)
10769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10770 uint16_t *data = eeprom->data;
10771 uint16_t offset, length, cnt_words;
10774 offset = eeprom->offset >> 1;
10775 length = eeprom->length >> 1;
10776 cnt_words = length;
10778 if (offset > hw->nvm.sr_size ||
10779 offset + length > hw->nvm.sr_size) {
10780 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10784 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10786 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10787 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10788 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10795 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10796 struct ether_addr *mac_addr)
10798 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10800 if (!is_valid_assigned_ether_addr(mac_addr)) {
10801 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10805 /* Flags: 0x3 updates port address */
10806 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10810 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10812 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10813 struct rte_eth_dev_data *dev_data = pf->dev_data;
10814 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10817 /* check if mtu is within the allowed range */
10818 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10821 /* mtu setting is forbidden if port is start */
10822 if (dev_data->dev_started) {
10823 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10824 dev_data->port_id);
10828 if (frame_size > ETHER_MAX_LEN)
10829 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10831 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10833 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10838 /* Restore ethertype filter */
10840 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10842 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10843 struct i40e_ethertype_filter_list
10844 *ethertype_list = &pf->ethertype.ethertype_list;
10845 struct i40e_ethertype_filter *f;
10846 struct i40e_control_filter_stats stats;
10849 TAILQ_FOREACH(f, ethertype_list, rules) {
10851 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10852 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10853 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10854 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10855 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10857 memset(&stats, 0, sizeof(stats));
10858 i40e_aq_add_rem_control_packet_filter(hw,
10859 f->input.mac_addr.addr_bytes,
10860 f->input.ether_type,
10861 flags, pf->main_vsi->seid,
10862 f->queue, 1, &stats, NULL);
10864 PMD_DRV_LOG(INFO, "Ethertype filter:"
10865 " mac_etype_used = %u, etype_used = %u,"
10866 " mac_etype_free = %u, etype_free = %u",
10867 stats.mac_etype_used, stats.etype_used,
10868 stats.mac_etype_free, stats.etype_free);
10871 /* Restore tunnel filter */
10873 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10875 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10876 struct i40e_vsi *vsi;
10877 struct i40e_pf_vf *vf;
10878 struct i40e_tunnel_filter_list
10879 *tunnel_list = &pf->tunnel.tunnel_list;
10880 struct i40e_tunnel_filter *f;
10881 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10882 bool big_buffer = 0;
10884 TAILQ_FOREACH(f, tunnel_list, rules) {
10886 vsi = pf->main_vsi;
10888 vf = &pf->vfs[f->vf_id];
10891 memset(&cld_filter, 0, sizeof(cld_filter));
10892 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10893 (struct ether_addr *)&cld_filter.element.outer_mac);
10894 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10895 (struct ether_addr *)&cld_filter.element.inner_mac);
10896 cld_filter.element.inner_vlan = f->input.inner_vlan;
10897 cld_filter.element.flags = f->input.flags;
10898 cld_filter.element.tenant_id = f->input.tenant_id;
10899 cld_filter.element.queue_number = f->queue;
10900 rte_memcpy(cld_filter.general_fields,
10901 f->input.general_fields,
10902 sizeof(f->input.general_fields));
10904 if (((f->input.flags &
10905 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10906 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10908 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10909 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10911 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10912 I40E_AQC_ADD_CLOUD_FILTER_0X10))
10916 i40e_aq_add_cloud_filters_big_buffer(hw,
10917 vsi->seid, &cld_filter, 1);
10919 i40e_aq_add_cloud_filters(hw, vsi->seid,
10920 &cld_filter.element, 1);
10925 i40e_filter_restore(struct i40e_pf *pf)
10927 i40e_ethertype_filter_restore(pf);
10928 i40e_tunnel_filter_restore(pf);
10929 i40e_fdir_filter_restore(pf);
10933 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10935 if (strcmp(dev->device->driver->name, drv->driver.name))
10942 is_i40e_supported(struct rte_eth_dev *dev)
10944 return is_device_supported(dev, &rte_i40e_pmd);
10947 struct i40e_customized_pctype*
10948 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10952 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10953 if (pf->customized_pctype[i].index == index)
10954 return &pf->customized_pctype[i];
10960 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10961 uint32_t pkg_size, uint32_t proto_num,
10962 struct rte_pmd_i40e_proto_info *proto)
10964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10965 uint32_t pctype_num;
10966 struct rte_pmd_i40e_ptype_info *pctype;
10967 uint32_t buff_size;
10968 struct i40e_customized_pctype *new_pctype = NULL;
10970 uint8_t pctype_value;
10975 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10976 (uint8_t *)&pctype_num, sizeof(pctype_num),
10977 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10979 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10983 PMD_DRV_LOG(INFO, "No new pctype added");
10987 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
10988 pctype = rte_zmalloc("new_pctype", buff_size, 0);
10990 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10993 /* get information about new pctype list */
10994 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10995 (uint8_t *)pctype, buff_size,
10996 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
10998 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11003 /* Update customized pctype. */
11004 for (i = 0; i < pctype_num; i++) {
11005 pctype_value = pctype[i].ptype_id;
11006 memset(name, 0, sizeof(name));
11007 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11008 proto_id = pctype[i].protocols[j];
11009 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11011 for (n = 0; n < proto_num; n++) {
11012 if (proto[n].proto_id != proto_id)
11014 strcat(name, proto[n].name);
11019 name[strlen(name) - 1] = '\0';
11020 if (!strcmp(name, "GTPC"))
11022 i40e_find_customized_pctype(pf,
11023 I40E_CUSTOMIZED_GTPC);
11024 else if (!strcmp(name, "GTPU_IPV4"))
11026 i40e_find_customized_pctype(pf,
11027 I40E_CUSTOMIZED_GTPU_IPV4);
11028 else if (!strcmp(name, "GTPU_IPV6"))
11030 i40e_find_customized_pctype(pf,
11031 I40E_CUSTOMIZED_GTPU_IPV6);
11032 else if (!strcmp(name, "GTPU"))
11034 i40e_find_customized_pctype(pf,
11035 I40E_CUSTOMIZED_GTPU);
11037 new_pctype->pctype = pctype_value;
11038 new_pctype->valid = true;
11047 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11048 uint32_t pkg_size, uint32_t proto_num,
11049 struct rte_pmd_i40e_proto_info *proto)
11051 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11052 uint8_t port_id = dev->data->port_id;
11053 uint32_t ptype_num;
11054 struct rte_pmd_i40e_ptype_info *ptype;
11055 uint32_t buff_size;
11062 /* get information about new ptype num */
11063 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11064 (uint8_t *)&ptype_num, sizeof(ptype_num),
11065 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11067 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11071 PMD_DRV_LOG(INFO, "No new ptype added");
11075 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11076 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11078 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11082 /* get information about new ptype list */
11083 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11084 (uint8_t *)ptype, buff_size,
11085 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11087 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11092 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11093 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11094 if (!ptype_mapping) {
11095 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11100 /* Update ptype mapping table. */
11101 for (i = 0; i < ptype_num; i++) {
11102 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11103 ptype_mapping[i].sw_ptype = 0;
11105 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11106 proto_id = ptype[i].protocols[j];
11107 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11109 for (n = 0; n < proto_num; n++) {
11110 if (proto[n].proto_id != proto_id)
11112 memset(name, 0, sizeof(name));
11113 strcpy(name, proto[n].name);
11114 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11115 ptype_mapping[i].sw_ptype |=
11116 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11118 } else if (!strncmp(name, "IPV4", 4) &&
11120 ptype_mapping[i].sw_ptype |=
11121 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11122 } else if (!strncmp(name, "IPV6", 4) &&
11124 ptype_mapping[i].sw_ptype |=
11125 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11127 } else if (!strncmp(name, "IPV6", 4) &&
11129 ptype_mapping[i].sw_ptype |=
11130 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11131 } else if (!strncmp(name, "IPV4FRAG", 8)) {
11132 ptype_mapping[i].sw_ptype |=
11133 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11134 ptype_mapping[i].sw_ptype |=
11135 RTE_PTYPE_INNER_L4_FRAG;
11136 } else if (!strncmp(name, "IPV6FRAG", 8)) {
11137 ptype_mapping[i].sw_ptype |=
11138 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11139 ptype_mapping[i].sw_ptype |=
11140 RTE_PTYPE_INNER_L4_FRAG;
11141 } else if (!strncmp(name, "GTPC", 4))
11142 ptype_mapping[i].sw_ptype |=
11143 RTE_PTYPE_TUNNEL_GTPC;
11144 else if (!strncmp(name, "GTPU", 4))
11145 ptype_mapping[i].sw_ptype |=
11146 RTE_PTYPE_TUNNEL_GTPU;
11147 else if (!strncmp(name, "UDP", 3))
11148 ptype_mapping[i].sw_ptype |=
11149 RTE_PTYPE_INNER_L4_UDP;
11150 else if (!strncmp(name, "TCP", 3))
11151 ptype_mapping[i].sw_ptype |=
11152 RTE_PTYPE_INNER_L4_TCP;
11153 else if (!strncmp(name, "SCTP", 4))
11154 ptype_mapping[i].sw_ptype |=
11155 RTE_PTYPE_INNER_L4_SCTP;
11156 else if (!strncmp(name, "ICMP", 4) ||
11157 !strncmp(name, "ICMPV6", 6))
11158 ptype_mapping[i].sw_ptype |=
11159 RTE_PTYPE_INNER_L4_ICMP;
11166 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11169 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11171 rte_free(ptype_mapping);
11177 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11181 uint32_t proto_num;
11182 struct rte_pmd_i40e_proto_info *proto;
11183 uint32_t buff_size;
11187 /* get information about protocol number */
11188 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11189 (uint8_t *)&proto_num, sizeof(proto_num),
11190 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11192 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11196 PMD_DRV_LOG(INFO, "No new protocol added");
11200 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11201 proto = rte_zmalloc("new_proto", buff_size, 0);
11203 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11207 /* get information about protocol list */
11208 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11209 (uint8_t *)proto, buff_size,
11210 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11212 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11217 /* Check if GTP is supported. */
11218 for (i = 0; i < proto_num; i++) {
11219 if (!strncmp(proto[i].name, "GTP", 3)) {
11220 pf->gtp_support = true;
11225 /* Update customized pctype info */
11226 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11229 PMD_DRV_LOG(INFO, "No pctype is updated.");
11231 /* Update customized ptype info */
11232 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11235 PMD_DRV_LOG(INFO, "No ptype is updated.");
11240 /* Create a QinQ cloud filter
11242 * The Fortville NIC has limited resources for tunnel filters,
11243 * so we can only reuse existing filters.
11245 * In step 1 we define which Field Vector fields can be used for
11247 * As we do not have the inner tag defined as a field,
11248 * we have to define it first, by reusing one of L1 entries.
11250 * In step 2 we are replacing one of existing filter types with
11251 * a new one for QinQ.
11252 * As we reusing L1 and replacing L2, some of the default filter
11253 * types will disappear,which depends on L1 and L2 entries we reuse.
11255 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11257 * 1. Create L1 filter of outer vlan (12b) which will be in use
11258 * later when we define the cloud filter.
11259 * a. Valid_flags.replace_cloud = 0
11260 * b. Old_filter = 10 (Stag_Inner_Vlan)
11261 * c. New_filter = 0x10
11262 * d. TR bit = 0xff (optional, not used here)
11263 * e. Buffer – 2 entries:
11264 * i. Byte 0 = 8 (outer vlan FV index).
11266 * Byte 2-3 = 0x0fff
11267 * ii. Byte 0 = 37 (inner vlan FV index).
11269 * Byte 2-3 = 0x0fff
11272 * 2. Create cloud filter using two L1 filters entries: stag and
11273 * new filter(outer vlan+ inner vlan)
11274 * a. Valid_flags.replace_cloud = 1
11275 * b. Old_filter = 1 (instead of outer IP)
11276 * c. New_filter = 0x10
11277 * d. Buffer – 2 entries:
11278 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11279 * Byte 1-3 = 0 (rsv)
11280 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11281 * Byte 9-11 = 0 (rsv)
11284 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11286 int ret = -ENOTSUP;
11287 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11288 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11289 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11292 memset(&filter_replace, 0,
11293 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11294 memset(&filter_replace_buf, 0,
11295 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11297 /* create L1 filter */
11298 filter_replace.old_filter_type =
11299 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11300 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11301 filter_replace.tr_bit = 0;
11303 /* Prepare the buffer, 2 entries */
11304 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11305 filter_replace_buf.data[0] |=
11306 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11307 /* Field Vector 12b mask */
11308 filter_replace_buf.data[2] = 0xff;
11309 filter_replace_buf.data[3] = 0x0f;
11310 filter_replace_buf.data[4] =
11311 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11312 filter_replace_buf.data[4] |=
11313 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11314 /* Field Vector 12b mask */
11315 filter_replace_buf.data[6] = 0xff;
11316 filter_replace_buf.data[7] = 0x0f;
11317 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11318 &filter_replace_buf);
11319 if (ret != I40E_SUCCESS)
11322 /* Apply the second L2 cloud filter */
11323 memset(&filter_replace, 0,
11324 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11325 memset(&filter_replace_buf, 0,
11326 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11328 /* create L2 filter, input for L2 filter will be L1 filter */
11329 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11330 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11331 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11333 /* Prepare the buffer, 2 entries */
11334 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11335 filter_replace_buf.data[0] |=
11336 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11337 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11338 filter_replace_buf.data[4] |=
11339 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11340 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11341 &filter_replace_buf);
11345 RTE_INIT(i40e_init_log);
11347 i40e_init_log(void)
11349 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11350 if (i40e_logtype_init >= 0)
11351 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11352 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11353 if (i40e_logtype_driver >= 0)
11354 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);