1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct rte_ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static void i40e_dev_alarm_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct rte_ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
410 int i40e_logtype_tx_free;
413 static const char *const valid_keys[] = {
414 ETH_I40E_FLOATING_VEB_ARG,
415 ETH_I40E_FLOATING_VEB_LIST_ARG,
416 ETH_I40E_SUPPORT_MULTI_DRIVER,
417 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
418 ETH_I40E_USE_LATEST_VEC,
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
449 { .vendor_id = 0, /* sentinel */ },
452 static const struct eth_dev_ops i40e_eth_dev_ops = {
453 .dev_configure = i40e_dev_configure,
454 .dev_start = i40e_dev_start,
455 .dev_stop = i40e_dev_stop,
456 .dev_close = i40e_dev_close,
457 .dev_reset = i40e_dev_reset,
458 .promiscuous_enable = i40e_dev_promiscuous_enable,
459 .promiscuous_disable = i40e_dev_promiscuous_disable,
460 .allmulticast_enable = i40e_dev_allmulticast_enable,
461 .allmulticast_disable = i40e_dev_allmulticast_disable,
462 .dev_set_link_up = i40e_dev_set_link_up,
463 .dev_set_link_down = i40e_dev_set_link_down,
464 .link_update = i40e_dev_link_update,
465 .stats_get = i40e_dev_stats_get,
466 .xstats_get = i40e_dev_xstats_get,
467 .xstats_get_names = i40e_dev_xstats_get_names,
468 .stats_reset = i40e_dev_stats_reset,
469 .xstats_reset = i40e_dev_stats_reset,
470 .fw_version_get = i40e_fw_version_get,
471 .dev_infos_get = i40e_dev_info_get,
472 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
473 .vlan_filter_set = i40e_vlan_filter_set,
474 .vlan_tpid_set = i40e_vlan_tpid_set,
475 .vlan_offload_set = i40e_vlan_offload_set,
476 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
477 .vlan_pvid_set = i40e_vlan_pvid_set,
478 .rx_queue_start = i40e_dev_rx_queue_start,
479 .rx_queue_stop = i40e_dev_rx_queue_stop,
480 .tx_queue_start = i40e_dev_tx_queue_start,
481 .tx_queue_stop = i40e_dev_tx_queue_stop,
482 .rx_queue_setup = i40e_dev_rx_queue_setup,
483 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
484 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
485 .rx_queue_release = i40e_dev_rx_queue_release,
486 .rx_queue_count = i40e_dev_rx_queue_count,
487 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
488 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
489 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .filter_ctrl = i40e_dev_filter_ctrl,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .rx_burst_mode_get = i40e_rx_burst_mode_get,
509 .tx_burst_mode_get = i40e_tx_burst_mode_get,
510 .mirror_rule_set = i40e_mirror_rule_set,
511 .mirror_rule_reset = i40e_mirror_rule_reset,
512 .timesync_enable = i40e_timesync_enable,
513 .timesync_disable = i40e_timesync_disable,
514 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
515 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
516 .get_dcb_info = i40e_dev_get_dcb_info,
517 .timesync_adjust_time = i40e_timesync_adjust_time,
518 .timesync_read_time = i40e_timesync_read_time,
519 .timesync_write_time = i40e_timesync_write_time,
520 .get_reg = i40e_get_regs,
521 .get_eeprom_length = i40e_get_eeprom_length,
522 .get_eeprom = i40e_get_eeprom,
523 .get_module_info = i40e_get_module_info,
524 .get_module_eeprom = i40e_get_module_eeprom,
525 .mac_addr_set = i40e_set_default_mac_addr,
526 .mtu_set = i40e_dev_mtu_set,
527 .tm_ops_get = i40e_tm_ops_get,
528 .tx_done_cleanup = i40e_tx_done_cleanup,
531 /* store statistics names and its offset in stats structure */
532 struct rte_i40e_xstats_name_off {
533 char name[RTE_ETH_XSTATS_NAME_SIZE];
537 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
538 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
539 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
540 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
541 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
542 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
543 rx_unknown_protocol)},
544 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
545 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
546 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
547 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
550 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
551 sizeof(rte_i40e_stats_strings[0]))
553 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
554 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
555 tx_dropped_link_down)},
556 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
557 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
560 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
562 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
564 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
566 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
567 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
568 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
569 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
570 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
571 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
583 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
587 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
588 mac_short_packet_dropped)},
589 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
591 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
592 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
593 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
603 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
605 {"rx_flow_director_atr_match_packets",
606 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
607 {"rx_flow_director_sb_match_packets",
608 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
609 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
611 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
613 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
615 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
619 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
620 sizeof(rte_i40e_hw_port_strings[0]))
622 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
623 {"xon_packets", offsetof(struct i40e_hw_port_stats,
625 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
629 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
630 sizeof(rte_i40e_rxq_prio_strings[0]))
632 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
633 {"xon_packets", offsetof(struct i40e_hw_port_stats,
635 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
637 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
638 priority_xon_2_xoff)},
641 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
642 sizeof(rte_i40e_txq_prio_strings[0]))
645 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
646 struct rte_pci_device *pci_dev)
648 char name[RTE_ETH_NAME_MAX_LEN];
649 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
652 if (pci_dev->device.devargs) {
653 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
659 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
660 sizeof(struct i40e_adapter),
661 eth_dev_pci_specific_init, pci_dev,
662 eth_i40e_dev_init, NULL);
664 if (retval || eth_da.nb_representor_ports < 1)
667 /* probe VF representor ports */
668 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
669 pci_dev->device.name);
671 if (pf_ethdev == NULL)
674 for (i = 0; i < eth_da.nb_representor_ports; i++) {
675 struct i40e_vf_representor representor = {
676 .vf_id = eth_da.representor_ports[i],
677 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
678 pf_ethdev->data->dev_private)->switch_domain_id,
679 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
680 pf_ethdev->data->dev_private)
683 /* representor port net_bdf_port */
684 snprintf(name, sizeof(name), "net_%s_representor_%d",
685 pci_dev->device.name, eth_da.representor_ports[i]);
687 retval = rte_eth_dev_create(&pci_dev->device, name,
688 sizeof(struct i40e_vf_representor), NULL, NULL,
689 i40e_vf_representor_init, &representor);
692 PMD_DRV_LOG(ERR, "failed to create i40e vf "
693 "representor %s.", name);
699 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
701 struct rte_eth_dev *ethdev;
703 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
707 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
708 return rte_eth_dev_pci_generic_remove(pci_dev,
709 i40e_vf_representor_uninit);
711 return rte_eth_dev_pci_generic_remove(pci_dev,
712 eth_i40e_dev_uninit);
715 static struct rte_pci_driver rte_i40e_pmd = {
716 .id_table = pci_id_i40e_map,
717 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
718 .probe = eth_i40e_pci_probe,
719 .remove = eth_i40e_pci_remove,
723 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
726 uint32_t ori_reg_val;
727 struct rte_eth_dev *dev;
729 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
730 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
731 i40e_write_rx_ctl(hw, reg_addr, reg_val);
732 if (ori_reg_val != reg_val)
734 "i40e device %s changed global register [0x%08x]."
735 " original: 0x%08x, new: 0x%08x",
736 dev->device->name, reg_addr, ori_reg_val, reg_val);
739 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
740 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
741 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
743 #ifndef I40E_GLQF_ORT
744 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
746 #ifndef I40E_GLQF_PIT
747 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
749 #ifndef I40E_GLQF_L3_MAP
750 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
753 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
756 * Initialize registers for parsing packet type of QinQ
757 * This should be removed from code once proper
758 * configuration API is added to avoid configuration conflicts
759 * between ports of the same device.
761 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
762 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
765 static inline void i40e_config_automask(struct i40e_pf *pf)
767 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
770 /* INTENA flag is not auto-cleared for interrupt */
771 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
772 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
773 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
775 /* If support multi-driver, PF will use INT0. */
776 if (!pf->support_multi_driver)
777 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
779 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
782 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
785 * Add a ethertype filter to drop all flow control frames transmitted
789 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
791 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
792 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
793 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
794 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
797 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
798 I40E_FLOW_CONTROL_ETHERTYPE, flags,
799 pf->main_vsi_seid, 0,
803 "Failed to add filter to drop flow control frames from VSIs.");
807 floating_veb_list_handler(__rte_unused const char *key,
808 const char *floating_veb_value,
812 unsigned int count = 0;
815 bool *vf_floating_veb = opaque;
817 while (isblank(*floating_veb_value))
818 floating_veb_value++;
820 /* Reset floating VEB configuration for VFs */
821 for (idx = 0; idx < I40E_MAX_VF; idx++)
822 vf_floating_veb[idx] = false;
826 while (isblank(*floating_veb_value))
827 floating_veb_value++;
828 if (*floating_veb_value == '\0')
831 idx = strtoul(floating_veb_value, &end, 10);
832 if (errno || end == NULL)
834 while (isblank(*end))
838 } else if ((*end == ';') || (*end == '\0')) {
840 if (min == I40E_MAX_VF)
842 if (max >= I40E_MAX_VF)
843 max = I40E_MAX_VF - 1;
844 for (idx = min; idx <= max; idx++) {
845 vf_floating_veb[idx] = true;
852 floating_veb_value = end + 1;
853 } while (*end != '\0');
862 config_vf_floating_veb(struct rte_devargs *devargs,
863 uint16_t floating_veb,
864 bool *vf_floating_veb)
866 struct rte_kvargs *kvlist;
868 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
872 /* All the VFs attach to the floating VEB by default
873 * when the floating VEB is enabled.
875 for (i = 0; i < I40E_MAX_VF; i++)
876 vf_floating_veb[i] = true;
881 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
885 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
886 rte_kvargs_free(kvlist);
889 /* When the floating_veb_list parameter exists, all the VFs
890 * will attach to the legacy VEB firstly, then configure VFs
891 * to the floating VEB according to the floating_veb_list.
893 if (rte_kvargs_process(kvlist, floating_veb_list,
894 floating_veb_list_handler,
895 vf_floating_veb) < 0) {
896 rte_kvargs_free(kvlist);
899 rte_kvargs_free(kvlist);
903 i40e_check_floating_handler(__rte_unused const char *key,
905 __rte_unused void *opaque)
907 if (strcmp(value, "1"))
914 is_floating_veb_supported(struct rte_devargs *devargs)
916 struct rte_kvargs *kvlist;
917 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
922 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
926 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
927 rte_kvargs_free(kvlist);
930 /* Floating VEB is enabled when there's key-value:
931 * enable_floating_veb=1
933 if (rte_kvargs_process(kvlist, floating_veb_key,
934 i40e_check_floating_handler, NULL) < 0) {
935 rte_kvargs_free(kvlist);
938 rte_kvargs_free(kvlist);
944 config_floating_veb(struct rte_eth_dev *dev)
946 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
947 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
948 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
950 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
952 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
954 is_floating_veb_supported(pci_dev->device.devargs);
955 config_vf_floating_veb(pci_dev->device.devargs,
957 pf->floating_veb_list);
959 pf->floating_veb = false;
963 #define I40E_L2_TAGS_S_TAG_SHIFT 1
964 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
967 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
969 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
970 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
971 char ethertype_hash_name[RTE_HASH_NAMESIZE];
974 struct rte_hash_parameters ethertype_hash_params = {
975 .name = ethertype_hash_name,
976 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
977 .key_len = sizeof(struct i40e_ethertype_filter_input),
978 .hash_func = rte_hash_crc,
979 .hash_func_init_val = 0,
980 .socket_id = rte_socket_id(),
983 /* Initialize ethertype filter rule list and hash */
984 TAILQ_INIT(ðertype_rule->ethertype_list);
985 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
986 "ethertype_%s", dev->device->name);
987 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
988 if (!ethertype_rule->hash_table) {
989 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
992 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
993 sizeof(struct i40e_ethertype_filter *) *
994 I40E_MAX_ETHERTYPE_FILTER_NUM,
996 if (!ethertype_rule->hash_map) {
998 "Failed to allocate memory for ethertype hash map!");
1000 goto err_ethertype_hash_map_alloc;
1005 err_ethertype_hash_map_alloc:
1006 rte_hash_free(ethertype_rule->hash_table);
1012 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1014 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1015 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1016 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1019 struct rte_hash_parameters tunnel_hash_params = {
1020 .name = tunnel_hash_name,
1021 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1022 .key_len = sizeof(struct i40e_tunnel_filter_input),
1023 .hash_func = rte_hash_crc,
1024 .hash_func_init_val = 0,
1025 .socket_id = rte_socket_id(),
1028 /* Initialize tunnel filter rule list and hash */
1029 TAILQ_INIT(&tunnel_rule->tunnel_list);
1030 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1031 "tunnel_%s", dev->device->name);
1032 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1033 if (!tunnel_rule->hash_table) {
1034 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1037 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1038 sizeof(struct i40e_tunnel_filter *) *
1039 I40E_MAX_TUNNEL_FILTER_NUM,
1041 if (!tunnel_rule->hash_map) {
1043 "Failed to allocate memory for tunnel hash map!");
1045 goto err_tunnel_hash_map_alloc;
1050 err_tunnel_hash_map_alloc:
1051 rte_hash_free(tunnel_rule->hash_table);
1057 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1059 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1060 struct i40e_fdir_info *fdir_info = &pf->fdir;
1061 char fdir_hash_name[RTE_HASH_NAMESIZE];
1064 struct rte_hash_parameters fdir_hash_params = {
1065 .name = fdir_hash_name,
1066 .entries = I40E_MAX_FDIR_FILTER_NUM,
1067 .key_len = sizeof(struct i40e_fdir_input),
1068 .hash_func = rte_hash_crc,
1069 .hash_func_init_val = 0,
1070 .socket_id = rte_socket_id(),
1073 /* Initialize flow director filter rule list and hash */
1074 TAILQ_INIT(&fdir_info->fdir_list);
1075 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1076 "fdir_%s", dev->device->name);
1077 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1078 if (!fdir_info->hash_table) {
1079 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1082 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1083 sizeof(struct i40e_fdir_filter *) *
1084 I40E_MAX_FDIR_FILTER_NUM,
1086 if (!fdir_info->hash_map) {
1088 "Failed to allocate memory for fdir hash map!");
1090 goto err_fdir_hash_map_alloc;
1094 err_fdir_hash_map_alloc:
1095 rte_hash_free(fdir_info->hash_table);
1101 i40e_init_customized_info(struct i40e_pf *pf)
1105 /* Initialize customized pctype */
1106 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1107 pf->customized_pctype[i].index = i;
1108 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1109 pf->customized_pctype[i].valid = false;
1112 pf->gtp_support = false;
1113 pf->esp_support = false;
1117 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1119 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1120 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1121 struct i40e_queue_regions *info = &pf->queue_region;
1124 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1125 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1127 memset(info, 0, sizeof(struct i40e_queue_regions));
1131 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1136 unsigned long support_multi_driver;
1139 pf = (struct i40e_pf *)opaque;
1142 support_multi_driver = strtoul(value, &end, 10);
1143 if (errno != 0 || end == value || *end != 0) {
1144 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1148 if (support_multi_driver == 1 || support_multi_driver == 0)
1149 pf->support_multi_driver = (bool)support_multi_driver;
1151 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1152 "enable global configuration by default."
1153 ETH_I40E_SUPPORT_MULTI_DRIVER);
1158 i40e_support_multi_driver(struct rte_eth_dev *dev)
1160 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1161 struct rte_kvargs *kvlist;
1164 /* Enable global configuration by default */
1165 pf->support_multi_driver = false;
1167 if (!dev->device->devargs)
1170 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1174 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1175 if (!kvargs_count) {
1176 rte_kvargs_free(kvlist);
1180 if (kvargs_count > 1)
1181 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1182 "the first invalid or last valid one is used !",
1183 ETH_I40E_SUPPORT_MULTI_DRIVER);
1185 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1186 i40e_parse_multi_drv_handler, pf) < 0) {
1187 rte_kvargs_free(kvlist);
1191 rte_kvargs_free(kvlist);
1196 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1197 uint32_t reg_addr, uint64_t reg_val,
1198 struct i40e_asq_cmd_details *cmd_details)
1200 uint64_t ori_reg_val;
1201 struct rte_eth_dev *dev;
1204 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1205 if (ret != I40E_SUCCESS) {
1207 "Fail to debug read from 0x%08x",
1211 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1213 if (ori_reg_val != reg_val)
1214 PMD_DRV_LOG(WARNING,
1215 "i40e device %s changed global register [0x%08x]."
1216 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1217 dev->device->name, reg_addr, ori_reg_val, reg_val);
1219 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1223 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1227 struct i40e_adapter *ad = opaque;
1230 use_latest_vec = atoi(value);
1232 if (use_latest_vec != 0 && use_latest_vec != 1)
1233 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1235 ad->use_latest_vec = (uint8_t)use_latest_vec;
1241 i40e_use_latest_vec(struct rte_eth_dev *dev)
1243 struct i40e_adapter *ad =
1244 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1245 struct rte_kvargs *kvlist;
1248 ad->use_latest_vec = false;
1250 if (!dev->device->devargs)
1253 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1257 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1258 if (!kvargs_count) {
1259 rte_kvargs_free(kvlist);
1263 if (kvargs_count > 1)
1264 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1265 "the first invalid or last valid one is used !",
1266 ETH_I40E_USE_LATEST_VEC);
1268 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1269 i40e_parse_latest_vec_handler, ad) < 0) {
1270 rte_kvargs_free(kvlist);
1274 rte_kvargs_free(kvlist);
1279 read_vf_msg_config(__rte_unused const char *key,
1283 struct i40e_vf_msg_cfg *cfg = opaque;
1285 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1286 &cfg->ignore_second) != 3) {
1287 memset(cfg, 0, sizeof(*cfg));
1288 PMD_DRV_LOG(ERR, "format error! example: "
1289 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1294 * If the message validation function been enabled, the 'period'
1295 * and 'ignore_second' must greater than 0.
1297 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1298 memset(cfg, 0, sizeof(*cfg));
1299 PMD_DRV_LOG(ERR, "%s error! the second and third"
1300 " number must be greater than 0!",
1301 ETH_I40E_VF_MSG_CFG);
1309 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1310 struct i40e_vf_msg_cfg *msg_cfg)
1312 struct rte_kvargs *kvlist;
1316 memset(msg_cfg, 0, sizeof(*msg_cfg));
1318 if (!dev->device->devargs)
1321 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1325 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1329 if (kvargs_count > 1) {
1330 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1331 ETH_I40E_VF_MSG_CFG);
1336 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1337 read_vf_msg_config, msg_cfg) < 0)
1341 rte_kvargs_free(kvlist);
1345 #define I40E_ALARM_INTERVAL 50000 /* us */
1348 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1350 struct rte_pci_device *pci_dev;
1351 struct rte_intr_handle *intr_handle;
1352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354 struct i40e_vsi *vsi;
1357 uint8_t aq_fail = 0;
1359 PMD_INIT_FUNC_TRACE();
1361 dev->dev_ops = &i40e_eth_dev_ops;
1362 dev->rx_pkt_burst = i40e_recv_pkts;
1363 dev->tx_pkt_burst = i40e_xmit_pkts;
1364 dev->tx_pkt_prepare = i40e_prep_pkts;
1366 /* for secondary processes, we don't initialise any further as primary
1367 * has already done this work. Only check we don't need a different
1369 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1370 i40e_set_rx_function(dev);
1371 i40e_set_tx_function(dev);
1374 i40e_set_default_ptype_table(dev);
1375 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1376 intr_handle = &pci_dev->intr_handle;
1378 rte_eth_copy_pci_info(dev, pci_dev);
1380 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1381 pf->adapter->eth_dev = dev;
1382 pf->dev_data = dev->data;
1384 hw->back = I40E_PF_TO_ADAPTER(pf);
1385 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1388 "Hardware is not available, as address is NULL");
1392 hw->vendor_id = pci_dev->id.vendor_id;
1393 hw->device_id = pci_dev->id.device_id;
1394 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1395 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1396 hw->bus.device = pci_dev->addr.devid;
1397 hw->bus.func = pci_dev->addr.function;
1398 hw->adapter_stopped = 0;
1399 hw->adapter_closed = 0;
1401 /* Init switch device pointer */
1402 hw->switch_dev = NULL;
1405 * Switch Tag value should not be identical to either the First Tag
1406 * or Second Tag values. So set something other than common Ethertype
1407 * for internal switching.
1409 hw->switch_tag = 0xffff;
1411 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1412 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1413 PMD_INIT_LOG(ERR, "\nERROR: "
1414 "Firmware recovery mode detected. Limiting functionality.\n"
1415 "Refer to the Intel(R) Ethernet Adapters and Devices "
1416 "User Guide for details on firmware recovery mode.");
1420 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1421 /* Check if need to support multi-driver */
1422 i40e_support_multi_driver(dev);
1423 /* Check if users want the latest supported vec path */
1424 i40e_use_latest_vec(dev);
1426 /* Make sure all is clean before doing PF reset */
1429 /* Reset here to make sure all is clean for each PF */
1430 ret = i40e_pf_reset(hw);
1432 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1436 /* Initialize the shared code (base driver) */
1437 ret = i40e_init_shared_code(hw);
1439 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1443 /* Initialize the parameters for adminq */
1444 i40e_init_adminq_parameter(hw);
1445 ret = i40e_init_adminq(hw);
1446 if (ret != I40E_SUCCESS) {
1447 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1450 /* Firmware of SFP x722 does not support adminq option */
1451 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1452 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1454 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1455 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1456 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1457 ((hw->nvm.version >> 12) & 0xf),
1458 ((hw->nvm.version >> 4) & 0xff),
1459 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1461 /* Initialize the hardware */
1464 i40e_config_automask(pf);
1466 i40e_set_default_pctype_table(dev);
1469 * To work around the NVM issue, initialize registers
1470 * for packet type of QinQ by software.
1471 * It should be removed once issues are fixed in NVM.
1473 if (!pf->support_multi_driver)
1474 i40e_GLQF_reg_init(hw);
1476 /* Initialize the input set for filters (hash and fd) to default value */
1477 i40e_filter_input_set_init(pf);
1479 /* initialise the L3_MAP register */
1480 if (!pf->support_multi_driver) {
1481 ret = i40e_aq_debug_write_global_register(hw,
1482 I40E_GLQF_L3_MAP(40),
1485 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1488 "Global register 0x%08x is changed with 0x28",
1489 I40E_GLQF_L3_MAP(40));
1492 /* Need the special FW version to support floating VEB */
1493 config_floating_veb(dev);
1494 /* Clear PXE mode */
1495 i40e_clear_pxe_mode(hw);
1496 i40e_dev_sync_phy_type(hw);
1499 * On X710, performance number is far from the expectation on recent
1500 * firmware versions. The fix for this issue may not be integrated in
1501 * the following firmware version. So the workaround in software driver
1502 * is needed. It needs to modify the initial values of 3 internal only
1503 * registers. Note that the workaround can be removed when it is fixed
1504 * in firmware in the future.
1506 i40e_configure_registers(hw);
1508 /* Get hw capabilities */
1509 ret = i40e_get_cap(hw);
1510 if (ret != I40E_SUCCESS) {
1511 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1512 goto err_get_capabilities;
1515 /* Initialize parameters for PF */
1516 ret = i40e_pf_parameter_init(dev);
1518 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1519 goto err_parameter_init;
1522 /* Initialize the queue management */
1523 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1525 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1526 goto err_qp_pool_init;
1528 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1529 hw->func_caps.num_msix_vectors - 1);
1531 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1532 goto err_msix_pool_init;
1535 /* Initialize lan hmc */
1536 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1537 hw->func_caps.num_rx_qp, 0, 0);
1538 if (ret != I40E_SUCCESS) {
1539 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1540 goto err_init_lan_hmc;
1543 /* Configure lan hmc */
1544 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1545 if (ret != I40E_SUCCESS) {
1546 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1547 goto err_configure_lan_hmc;
1550 /* Get and check the mac address */
1551 i40e_get_mac_addr(hw, hw->mac.addr);
1552 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1553 PMD_INIT_LOG(ERR, "mac address is not valid");
1555 goto err_get_mac_addr;
1557 /* Copy the permanent MAC address */
1558 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1559 (struct rte_ether_addr *)hw->mac.perm_addr);
1561 /* Disable flow control */
1562 hw->fc.requested_mode = I40E_FC_NONE;
1563 i40e_set_fc(hw, &aq_fail, TRUE);
1565 /* Set the global registers with default ether type value */
1566 if (!pf->support_multi_driver) {
1567 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1568 RTE_ETHER_TYPE_VLAN);
1569 if (ret != I40E_SUCCESS) {
1571 "Failed to set the default outer "
1573 goto err_setup_pf_switch;
1577 /* PF setup, which includes VSI setup */
1578 ret = i40e_pf_setup(pf);
1580 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1581 goto err_setup_pf_switch;
1586 /* Disable double vlan by default */
1587 i40e_vsi_config_double_vlan(vsi, FALSE);
1589 /* Disable S-TAG identification when floating_veb is disabled */
1590 if (!pf->floating_veb) {
1591 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1592 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1593 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1594 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1598 if (!vsi->max_macaddrs)
1599 len = RTE_ETHER_ADDR_LEN;
1601 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1603 /* Should be after VSI initialized */
1604 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1605 if (!dev->data->mac_addrs) {
1607 "Failed to allocated memory for storing mac address");
1610 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1611 &dev->data->mac_addrs[0]);
1613 /* Pass the information to the rte_eth_dev_close() that it should also
1614 * release the private port resources.
1616 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1618 /* Init dcb to sw mode by default */
1619 ret = i40e_dcb_init_configure(dev, TRUE);
1620 if (ret != I40E_SUCCESS) {
1621 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1622 pf->flags &= ~I40E_FLAG_DCB;
1624 /* Update HW struct after DCB configuration */
1627 /* initialize pf host driver to setup SRIOV resource if applicable */
1628 i40e_pf_host_init(dev);
1630 /* register callback func to eal lib */
1631 rte_intr_callback_register(intr_handle,
1632 i40e_dev_interrupt_handler, dev);
1634 /* configure and enable device interrupt */
1635 i40e_pf_config_irq0(hw, TRUE);
1636 i40e_pf_enable_irq0(hw);
1638 /* enable uio intr after callback register */
1639 rte_intr_enable(intr_handle);
1641 /* By default disable flexible payload in global configuration */
1642 if (!pf->support_multi_driver)
1643 i40e_flex_payload_reg_set_default(hw);
1646 * Add an ethertype filter to drop all flow control frames transmitted
1647 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1650 i40e_add_tx_flow_control_drop_filter(pf);
1652 /* Set the max frame size to 0x2600 by default,
1653 * in case other drivers changed the default value.
1655 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1657 /* initialize mirror rule list */
1658 TAILQ_INIT(&pf->mirror_list);
1660 /* initialize Traffic Manager configuration */
1661 i40e_tm_conf_init(dev);
1663 /* Initialize customized information */
1664 i40e_init_customized_info(pf);
1666 ret = i40e_init_ethtype_filter_list(dev);
1668 goto err_init_ethtype_filter_list;
1669 ret = i40e_init_tunnel_filter_list(dev);
1671 goto err_init_tunnel_filter_list;
1672 ret = i40e_init_fdir_filter_list(dev);
1674 goto err_init_fdir_filter_list;
1676 /* initialize queue region configuration */
1677 i40e_init_queue_region_conf(dev);
1679 /* initialize rss configuration from rte_flow */
1680 memset(&pf->rss_info, 0,
1681 sizeof(struct i40e_rte_flow_rss_conf));
1683 /* reset all stats of the device, including pf and main vsi */
1684 i40e_dev_stats_reset(dev);
1688 err_init_fdir_filter_list:
1689 rte_free(pf->tunnel.hash_table);
1690 rte_free(pf->tunnel.hash_map);
1691 err_init_tunnel_filter_list:
1692 rte_free(pf->ethertype.hash_table);
1693 rte_free(pf->ethertype.hash_map);
1694 err_init_ethtype_filter_list:
1695 rte_free(dev->data->mac_addrs);
1696 dev->data->mac_addrs = NULL;
1698 i40e_vsi_release(pf->main_vsi);
1699 err_setup_pf_switch:
1701 err_configure_lan_hmc:
1702 (void)i40e_shutdown_lan_hmc(hw);
1704 i40e_res_pool_destroy(&pf->msix_pool);
1706 i40e_res_pool_destroy(&pf->qp_pool);
1709 err_get_capabilities:
1710 (void)i40e_shutdown_adminq(hw);
1716 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1718 struct i40e_ethertype_filter *p_ethertype;
1719 struct i40e_ethertype_rule *ethertype_rule;
1721 ethertype_rule = &pf->ethertype;
1722 /* Remove all ethertype filter rules and hash */
1723 if (ethertype_rule->hash_map)
1724 rte_free(ethertype_rule->hash_map);
1725 if (ethertype_rule->hash_table)
1726 rte_hash_free(ethertype_rule->hash_table);
1728 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1729 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1730 p_ethertype, rules);
1731 rte_free(p_ethertype);
1736 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1738 struct i40e_tunnel_filter *p_tunnel;
1739 struct i40e_tunnel_rule *tunnel_rule;
1741 tunnel_rule = &pf->tunnel;
1742 /* Remove all tunnel director rules and hash */
1743 if (tunnel_rule->hash_map)
1744 rte_free(tunnel_rule->hash_map);
1745 if (tunnel_rule->hash_table)
1746 rte_hash_free(tunnel_rule->hash_table);
1748 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1749 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1755 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1757 struct i40e_fdir_filter *p_fdir;
1758 struct i40e_fdir_info *fdir_info;
1760 fdir_info = &pf->fdir;
1761 /* Remove all flow director rules and hash */
1762 if (fdir_info->hash_map)
1763 rte_free(fdir_info->hash_map);
1764 if (fdir_info->hash_table)
1765 rte_hash_free(fdir_info->hash_table);
1767 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1768 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1773 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1776 * Disable by default flexible payload
1777 * for corresponding L2/L3/L4 layers.
1779 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1780 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1781 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1785 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1789 PMD_INIT_FUNC_TRACE();
1791 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1794 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796 if (hw->adapter_closed == 0)
1797 i40e_dev_close(dev);
1803 i40e_dev_configure(struct rte_eth_dev *dev)
1805 struct i40e_adapter *ad =
1806 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1807 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1809 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1812 ret = i40e_dev_sync_phy_type(hw);
1816 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1817 * bulk allocation or vector Rx preconditions we will reset it.
1819 ad->rx_bulk_alloc_allowed = true;
1820 ad->rx_vec_allowed = true;
1821 ad->tx_simple_allowed = true;
1822 ad->tx_vec_allowed = true;
1824 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1825 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1827 /* Only legacy filter API needs the following fdir config. So when the
1828 * legacy filter API is deprecated, the following codes should also be
1831 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1832 ret = i40e_fdir_setup(pf);
1833 if (ret != I40E_SUCCESS) {
1834 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1837 ret = i40e_fdir_configure(dev);
1839 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1843 i40e_fdir_teardown(pf);
1845 ret = i40e_dev_init_vlan(dev);
1850 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1851 * RSS setting have different requirements.
1852 * General PMD driver call sequence are NIC init, configure,
1853 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1854 * will try to lookup the VSI that specific queue belongs to if VMDQ
1855 * applicable. So, VMDQ setting has to be done before
1856 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1857 * For RSS setting, it will try to calculate actual configured RX queue
1858 * number, which will be available after rx_queue_setup(). dev_start()
1859 * function is good to place RSS setup.
1861 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1862 ret = i40e_vmdq_setup(dev);
1867 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1868 ret = i40e_dcb_setup(dev);
1870 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1875 TAILQ_INIT(&pf->flow_list);
1880 /* need to release vmdq resource if exists */
1881 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1882 i40e_vsi_release(pf->vmdq[i].vsi);
1883 pf->vmdq[i].vsi = NULL;
1888 /* Need to release fdir resource if exists.
1889 * Only legacy filter API needs the following fdir config. So when the
1890 * legacy filter API is deprecated, the following code should also be
1893 i40e_fdir_teardown(pf);
1898 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1900 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1901 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1902 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1903 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1904 uint16_t msix_vect = vsi->msix_intr;
1907 for (i = 0; i < vsi->nb_qps; i++) {
1908 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1909 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1913 if (vsi->type != I40E_VSI_SRIOV) {
1914 if (!rte_intr_allow_others(intr_handle)) {
1915 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1916 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1918 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1921 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1922 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1924 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1929 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1930 vsi->user_param + (msix_vect - 1);
1932 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1933 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1935 I40E_WRITE_FLUSH(hw);
1939 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1940 int base_queue, int nb_queue,
1945 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1946 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1948 /* Bind all RX queues to allocated MSIX interrupt */
1949 for (i = 0; i < nb_queue; i++) {
1950 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1951 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1952 ((base_queue + i + 1) <<
1953 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1954 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1955 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1957 if (i == nb_queue - 1)
1958 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1959 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1962 /* Write first RX queue to Link list register as the head element */
1963 if (vsi->type != I40E_VSI_SRIOV) {
1965 i40e_calc_itr_interval(1, pf->support_multi_driver);
1967 if (msix_vect == I40E_MISC_VEC_ID) {
1968 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1970 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1972 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1974 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1977 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1979 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1981 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1983 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1990 if (msix_vect == I40E_MISC_VEC_ID) {
1992 I40E_VPINT_LNKLST0(vsi->user_param),
1994 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1996 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1998 /* num_msix_vectors_vf needs to minus irq0 */
1999 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2000 vsi->user_param + (msix_vect - 1);
2002 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2004 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2006 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2010 I40E_WRITE_FLUSH(hw);
2014 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2016 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2017 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2018 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2019 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2020 uint16_t msix_vect = vsi->msix_intr;
2021 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2022 uint16_t queue_idx = 0;
2026 for (i = 0; i < vsi->nb_qps; i++) {
2027 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2028 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2031 /* VF bind interrupt */
2032 if (vsi->type == I40E_VSI_SRIOV) {
2033 __vsi_queues_bind_intr(vsi, msix_vect,
2034 vsi->base_queue, vsi->nb_qps,
2039 /* PF & VMDq bind interrupt */
2040 if (rte_intr_dp_is_en(intr_handle)) {
2041 if (vsi->type == I40E_VSI_MAIN) {
2044 } else if (vsi->type == I40E_VSI_VMDQ2) {
2045 struct i40e_vsi *main_vsi =
2046 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2047 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2052 for (i = 0; i < vsi->nb_used_qps; i++) {
2054 if (!rte_intr_allow_others(intr_handle))
2055 /* allow to share MISC_VEC_ID */
2056 msix_vect = I40E_MISC_VEC_ID;
2058 /* no enough msix_vect, map all to one */
2059 __vsi_queues_bind_intr(vsi, msix_vect,
2060 vsi->base_queue + i,
2061 vsi->nb_used_qps - i,
2063 for (; !!record && i < vsi->nb_used_qps; i++)
2064 intr_handle->intr_vec[queue_idx + i] =
2068 /* 1:1 queue/msix_vect mapping */
2069 __vsi_queues_bind_intr(vsi, msix_vect,
2070 vsi->base_queue + i, 1,
2073 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2081 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2083 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2084 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2085 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2086 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2087 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2088 uint16_t msix_intr, i;
2090 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2091 for (i = 0; i < vsi->nb_msix; i++) {
2092 msix_intr = vsi->msix_intr + i;
2093 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2094 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2095 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2096 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2099 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2100 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2101 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2102 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2104 I40E_WRITE_FLUSH(hw);
2108 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2110 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2111 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2112 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2113 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2114 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2115 uint16_t msix_intr, i;
2117 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2118 for (i = 0; i < vsi->nb_msix; i++) {
2119 msix_intr = vsi->msix_intr + i;
2120 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2121 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2124 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2125 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2127 I40E_WRITE_FLUSH(hw);
2130 static inline uint8_t
2131 i40e_parse_link_speeds(uint16_t link_speeds)
2133 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2135 if (link_speeds & ETH_LINK_SPEED_40G)
2136 link_speed |= I40E_LINK_SPEED_40GB;
2137 if (link_speeds & ETH_LINK_SPEED_25G)
2138 link_speed |= I40E_LINK_SPEED_25GB;
2139 if (link_speeds & ETH_LINK_SPEED_20G)
2140 link_speed |= I40E_LINK_SPEED_20GB;
2141 if (link_speeds & ETH_LINK_SPEED_10G)
2142 link_speed |= I40E_LINK_SPEED_10GB;
2143 if (link_speeds & ETH_LINK_SPEED_1G)
2144 link_speed |= I40E_LINK_SPEED_1GB;
2145 if (link_speeds & ETH_LINK_SPEED_100M)
2146 link_speed |= I40E_LINK_SPEED_100MB;
2152 i40e_phy_conf_link(struct i40e_hw *hw,
2154 uint8_t force_speed,
2157 enum i40e_status_code status;
2158 struct i40e_aq_get_phy_abilities_resp phy_ab;
2159 struct i40e_aq_set_phy_config phy_conf;
2160 enum i40e_aq_phy_type cnt;
2161 uint8_t avail_speed;
2162 uint32_t phy_type_mask = 0;
2164 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2165 I40E_AQ_PHY_FLAG_PAUSE_RX |
2166 I40E_AQ_PHY_FLAG_PAUSE_RX |
2167 I40E_AQ_PHY_FLAG_LOW_POWER;
2170 /* To get phy capabilities of available speeds. */
2171 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2174 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2178 avail_speed = phy_ab.link_speed;
2180 /* To get the current phy config. */
2181 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2184 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2189 /* If link needs to go up and it is in autoneg mode the speed is OK,
2190 * no need to set up again.
2192 if (is_up && phy_ab.phy_type != 0 &&
2193 abilities & I40E_AQ_PHY_AN_ENABLED &&
2194 phy_ab.link_speed != 0)
2195 return I40E_SUCCESS;
2197 memset(&phy_conf, 0, sizeof(phy_conf));
2199 /* bits 0-2 use the values from get_phy_abilities_resp */
2201 abilities |= phy_ab.abilities & mask;
2203 phy_conf.abilities = abilities;
2205 /* If link needs to go up, but the force speed is not supported,
2206 * Warn users and config the default available speeds.
2208 if (is_up && !(force_speed & avail_speed)) {
2209 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2210 phy_conf.link_speed = avail_speed;
2212 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2215 /* PHY type mask needs to include each type except PHY type extension */
2216 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2217 phy_type_mask |= 1 << cnt;
2219 /* use get_phy_abilities_resp value for the rest */
2220 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2221 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2222 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2223 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2224 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2225 phy_conf.eee_capability = phy_ab.eee_capability;
2226 phy_conf.eeer = phy_ab.eeer_val;
2227 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2229 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2230 phy_ab.abilities, phy_ab.link_speed);
2231 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2232 phy_conf.abilities, phy_conf.link_speed);
2234 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2238 return I40E_SUCCESS;
2242 i40e_apply_link_speed(struct rte_eth_dev *dev)
2245 uint8_t abilities = 0;
2246 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247 struct rte_eth_conf *conf = &dev->data->dev_conf;
2249 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2250 I40E_AQ_PHY_LINK_ENABLED;
2252 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2253 conf->link_speeds = ETH_LINK_SPEED_40G |
2254 ETH_LINK_SPEED_25G |
2255 ETH_LINK_SPEED_20G |
2256 ETH_LINK_SPEED_10G |
2258 ETH_LINK_SPEED_100M;
2260 abilities |= I40E_AQ_PHY_AN_ENABLED;
2262 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2264 speed = i40e_parse_link_speeds(conf->link_speeds);
2266 return i40e_phy_conf_link(hw, abilities, speed, true);
2270 i40e_dev_start(struct rte_eth_dev *dev)
2272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274 struct i40e_vsi *main_vsi = pf->main_vsi;
2276 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2277 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2278 uint32_t intr_vector = 0;
2279 struct i40e_vsi *vsi;
2281 hw->adapter_stopped = 0;
2283 rte_intr_disable(intr_handle);
2285 if ((rte_intr_cap_multiple(intr_handle) ||
2286 !RTE_ETH_DEV_SRIOV(dev).active) &&
2287 dev->data->dev_conf.intr_conf.rxq != 0) {
2288 intr_vector = dev->data->nb_rx_queues;
2289 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2294 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2295 intr_handle->intr_vec =
2296 rte_zmalloc("intr_vec",
2297 dev->data->nb_rx_queues * sizeof(int),
2299 if (!intr_handle->intr_vec) {
2301 "Failed to allocate %d rx_queues intr_vec",
2302 dev->data->nb_rx_queues);
2307 /* Initialize VSI */
2308 ret = i40e_dev_rxtx_init(pf);
2309 if (ret != I40E_SUCCESS) {
2310 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2314 /* Map queues with MSIX interrupt */
2315 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2316 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2317 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2318 i40e_vsi_enable_queues_intr(main_vsi);
2320 /* Map VMDQ VSI queues with MSIX interrupt */
2321 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2322 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2323 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2324 I40E_ITR_INDEX_DEFAULT);
2325 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2328 /* enable FDIR MSIX interrupt */
2329 if (pf->fdir.fdir_vsi) {
2330 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2331 I40E_ITR_INDEX_NONE);
2332 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2335 /* Enable all queues which have been configured */
2336 ret = i40e_dev_switch_queues(pf, TRUE);
2337 if (ret != I40E_SUCCESS) {
2338 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2342 /* Enable receiving broadcast packets */
2343 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2344 if (ret != I40E_SUCCESS)
2345 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2347 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2348 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2350 if (ret != I40E_SUCCESS)
2351 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2354 /* Enable the VLAN promiscuous mode. */
2356 for (i = 0; i < pf->vf_num; i++) {
2357 vsi = pf->vfs[i].vsi;
2358 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2363 /* Enable mac loopback mode */
2364 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2365 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2366 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2367 if (ret != I40E_SUCCESS) {
2368 PMD_DRV_LOG(ERR, "fail to set loopback link");
2373 /* Apply link configure */
2374 ret = i40e_apply_link_speed(dev);
2375 if (I40E_SUCCESS != ret) {
2376 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2380 if (!rte_intr_allow_others(intr_handle)) {
2381 rte_intr_callback_unregister(intr_handle,
2382 i40e_dev_interrupt_handler,
2384 /* configure and enable device interrupt */
2385 i40e_pf_config_irq0(hw, FALSE);
2386 i40e_pf_enable_irq0(hw);
2388 if (dev->data->dev_conf.intr_conf.lsc != 0)
2390 "lsc won't enable because of no intr multiplex");
2392 ret = i40e_aq_set_phy_int_mask(hw,
2393 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2394 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2395 I40E_AQ_EVENT_MEDIA_NA), NULL);
2396 if (ret != I40E_SUCCESS)
2397 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2399 /* Call get_link_info aq commond to enable/disable LSE */
2400 i40e_dev_link_update(dev, 0);
2403 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2404 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2405 i40e_dev_alarm_handler, dev);
2407 /* enable uio intr after callback register */
2408 rte_intr_enable(intr_handle);
2411 i40e_filter_restore(pf);
2413 if (pf->tm_conf.root && !pf->tm_conf.committed)
2414 PMD_DRV_LOG(WARNING,
2415 "please call hierarchy_commit() "
2416 "before starting the port");
2418 return I40E_SUCCESS;
2421 i40e_dev_switch_queues(pf, FALSE);
2422 i40e_dev_clear_queues(dev);
2428 i40e_dev_stop(struct rte_eth_dev *dev)
2430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432 struct i40e_vsi *main_vsi = pf->main_vsi;
2433 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2434 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2437 if (hw->adapter_stopped == 1)
2440 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2441 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2442 rte_intr_enable(intr_handle);
2445 /* Disable all queues */
2446 i40e_dev_switch_queues(pf, FALSE);
2448 /* un-map queues with interrupt registers */
2449 i40e_vsi_disable_queues_intr(main_vsi);
2450 i40e_vsi_queues_unbind_intr(main_vsi);
2452 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2453 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2454 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2457 if (pf->fdir.fdir_vsi) {
2458 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2459 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2461 /* Clear all queues and release memory */
2462 i40e_dev_clear_queues(dev);
2465 i40e_dev_set_link_down(dev);
2467 if (!rte_intr_allow_others(intr_handle))
2468 /* resume to the default handler */
2469 rte_intr_callback_register(intr_handle,
2470 i40e_dev_interrupt_handler,
2473 /* Clean datapath event and queue/vec mapping */
2474 rte_intr_efd_disable(intr_handle);
2475 if (intr_handle->intr_vec) {
2476 rte_free(intr_handle->intr_vec);
2477 intr_handle->intr_vec = NULL;
2480 /* reset hierarchy commit */
2481 pf->tm_conf.committed = false;
2483 hw->adapter_stopped = 1;
2485 pf->adapter->rss_reta_updated = 0;
2489 i40e_dev_close(struct rte_eth_dev *dev)
2491 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2492 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2494 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2495 struct i40e_mirror_rule *p_mirror;
2496 struct i40e_filter_control_settings settings;
2497 struct rte_flow *p_flow;
2501 uint8_t aq_fail = 0;
2504 PMD_INIT_FUNC_TRACE();
2506 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2508 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2513 /* Remove all mirror rules */
2514 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2515 ret = i40e_aq_del_mirror_rule(hw,
2516 pf->main_vsi->veb->seid,
2517 p_mirror->rule_type,
2519 p_mirror->num_entries,
2522 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2523 "status = %d, aq_err = %d.", ret,
2524 hw->aq.asq_last_status);
2526 /* remove mirror software resource anyway */
2527 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2529 pf->nb_mirror_rule--;
2532 i40e_dev_free_queues(dev);
2534 /* Disable interrupt */
2535 i40e_pf_disable_irq0(hw);
2536 rte_intr_disable(intr_handle);
2539 * Only legacy filter API needs the following fdir config. So when the
2540 * legacy filter API is deprecated, the following code should also be
2543 i40e_fdir_teardown(pf);
2545 /* shutdown and destroy the HMC */
2546 i40e_shutdown_lan_hmc(hw);
2548 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2549 i40e_vsi_release(pf->vmdq[i].vsi);
2550 pf->vmdq[i].vsi = NULL;
2555 /* release all the existing VSIs and VEBs */
2556 i40e_vsi_release(pf->main_vsi);
2558 /* shutdown the adminq */
2559 i40e_aq_queue_shutdown(hw, true);
2560 i40e_shutdown_adminq(hw);
2562 i40e_res_pool_destroy(&pf->qp_pool);
2563 i40e_res_pool_destroy(&pf->msix_pool);
2565 /* Disable flexible payload in global configuration */
2566 if (!pf->support_multi_driver)
2567 i40e_flex_payload_reg_set_default(hw);
2569 /* force a PF reset to clean anything leftover */
2570 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2571 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2572 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2573 I40E_WRITE_FLUSH(hw);
2575 dev->dev_ops = NULL;
2576 dev->rx_pkt_burst = NULL;
2577 dev->tx_pkt_burst = NULL;
2579 /* Clear PXE mode */
2580 i40e_clear_pxe_mode(hw);
2582 /* Unconfigure filter control */
2583 memset(&settings, 0, sizeof(settings));
2584 ret = i40e_set_filter_control(hw, &settings);
2586 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2589 /* Disable flow control */
2590 hw->fc.requested_mode = I40E_FC_NONE;
2591 i40e_set_fc(hw, &aq_fail, TRUE);
2593 /* uninitialize pf host driver */
2594 i40e_pf_host_uninit(dev);
2597 ret = rte_intr_callback_unregister(intr_handle,
2598 i40e_dev_interrupt_handler, dev);
2599 if (ret >= 0 || ret == -ENOENT) {
2601 } else if (ret != -EAGAIN) {
2603 "intr callback unregister failed: %d",
2606 i40e_msec_delay(500);
2607 } while (retries++ < 5);
2609 i40e_rm_ethtype_filter_list(pf);
2610 i40e_rm_tunnel_filter_list(pf);
2611 i40e_rm_fdir_filter_list(pf);
2613 /* Remove all flows */
2614 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2615 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2619 /* Remove all Traffic Manager configuration */
2620 i40e_tm_conf_uninit(dev);
2622 hw->adapter_closed = 1;
2626 * Reset PF device only to re-initialize resources in PMD layer
2629 i40e_dev_reset(struct rte_eth_dev *dev)
2633 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2634 * its VF to make them align with it. The detailed notification
2635 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2636 * To avoid unexpected behavior in VF, currently reset of PF with
2637 * SR-IOV activation is not supported. It might be supported later.
2639 if (dev->data->sriov.active)
2642 ret = eth_i40e_dev_uninit(dev);
2646 ret = eth_i40e_dev_init(dev, NULL);
2652 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2654 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2655 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656 struct i40e_vsi *vsi = pf->main_vsi;
2659 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2661 if (status != I40E_SUCCESS) {
2662 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2666 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2668 if (status != I40E_SUCCESS) {
2669 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2670 /* Rollback unicast promiscuous mode */
2671 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2680 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684 struct i40e_vsi *vsi = pf->main_vsi;
2687 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2689 if (status != I40E_SUCCESS) {
2690 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2694 /* must remain in all_multicast mode */
2695 if (dev->data->all_multicast == 1)
2698 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2700 if (status != I40E_SUCCESS) {
2701 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2702 /* Rollback unicast promiscuous mode */
2703 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2712 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2714 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2716 struct i40e_vsi *vsi = pf->main_vsi;
2719 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2720 if (ret != I40E_SUCCESS) {
2721 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2729 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2731 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733 struct i40e_vsi *vsi = pf->main_vsi;
2736 if (dev->data->promiscuous == 1)
2737 return 0; /* must remain in all_multicast mode */
2739 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2740 vsi->seid, FALSE, NULL);
2741 if (ret != I40E_SUCCESS) {
2742 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2750 * Set device link up.
2753 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2755 /* re-apply link speed setting */
2756 return i40e_apply_link_speed(dev);
2760 * Set device link down.
2763 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2765 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2766 uint8_t abilities = 0;
2767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2769 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2770 return i40e_phy_conf_link(hw, abilities, speed, false);
2773 static __rte_always_inline void
2774 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2776 /* Link status registers and values*/
2777 #define I40E_PRTMAC_LINKSTA 0x001E2420
2778 #define I40E_REG_LINK_UP 0x40000080
2779 #define I40E_PRTMAC_MACC 0x001E24E0
2780 #define I40E_REG_MACC_25GB 0x00020000
2781 #define I40E_REG_SPEED_MASK 0x38000000
2782 #define I40E_REG_SPEED_0 0x00000000
2783 #define I40E_REG_SPEED_1 0x08000000
2784 #define I40E_REG_SPEED_2 0x10000000
2785 #define I40E_REG_SPEED_3 0x18000000
2786 #define I40E_REG_SPEED_4 0x20000000
2787 uint32_t link_speed;
2790 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2791 link_speed = reg_val & I40E_REG_SPEED_MASK;
2792 reg_val &= I40E_REG_LINK_UP;
2793 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2795 if (unlikely(link->link_status == 0))
2798 /* Parse the link status */
2799 switch (link_speed) {
2800 case I40E_REG_SPEED_0:
2801 link->link_speed = ETH_SPEED_NUM_100M;
2803 case I40E_REG_SPEED_1:
2804 link->link_speed = ETH_SPEED_NUM_1G;
2806 case I40E_REG_SPEED_2:
2807 if (hw->mac.type == I40E_MAC_X722)
2808 link->link_speed = ETH_SPEED_NUM_2_5G;
2810 link->link_speed = ETH_SPEED_NUM_10G;
2812 case I40E_REG_SPEED_3:
2813 if (hw->mac.type == I40E_MAC_X722) {
2814 link->link_speed = ETH_SPEED_NUM_5G;
2816 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2818 if (reg_val & I40E_REG_MACC_25GB)
2819 link->link_speed = ETH_SPEED_NUM_25G;
2821 link->link_speed = ETH_SPEED_NUM_40G;
2824 case I40E_REG_SPEED_4:
2825 if (hw->mac.type == I40E_MAC_X722)
2826 link->link_speed = ETH_SPEED_NUM_10G;
2828 link->link_speed = ETH_SPEED_NUM_20G;
2831 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2836 static __rte_always_inline void
2837 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2838 bool enable_lse, int wait_to_complete)
2840 #define CHECK_INTERVAL 100 /* 100ms */
2841 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2842 uint32_t rep_cnt = MAX_REPEAT_TIME;
2843 struct i40e_link_status link_status;
2846 memset(&link_status, 0, sizeof(link_status));
2849 memset(&link_status, 0, sizeof(link_status));
2851 /* Get link status information from hardware */
2852 status = i40e_aq_get_link_info(hw, enable_lse,
2853 &link_status, NULL);
2854 if (unlikely(status != I40E_SUCCESS)) {
2855 link->link_speed = ETH_SPEED_NUM_NONE;
2856 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2857 PMD_DRV_LOG(ERR, "Failed to get link info");
2861 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2862 if (!wait_to_complete || link->link_status)
2865 rte_delay_ms(CHECK_INTERVAL);
2866 } while (--rep_cnt);
2868 /* Parse the link status */
2869 switch (link_status.link_speed) {
2870 case I40E_LINK_SPEED_100MB:
2871 link->link_speed = ETH_SPEED_NUM_100M;
2873 case I40E_LINK_SPEED_1GB:
2874 link->link_speed = ETH_SPEED_NUM_1G;
2876 case I40E_LINK_SPEED_10GB:
2877 link->link_speed = ETH_SPEED_NUM_10G;
2879 case I40E_LINK_SPEED_20GB:
2880 link->link_speed = ETH_SPEED_NUM_20G;
2882 case I40E_LINK_SPEED_25GB:
2883 link->link_speed = ETH_SPEED_NUM_25G;
2885 case I40E_LINK_SPEED_40GB:
2886 link->link_speed = ETH_SPEED_NUM_40G;
2889 link->link_speed = ETH_SPEED_NUM_NONE;
2895 i40e_dev_link_update(struct rte_eth_dev *dev,
2896 int wait_to_complete)
2898 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899 struct rte_eth_link link;
2900 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2903 memset(&link, 0, sizeof(link));
2905 /* i40e uses full duplex only */
2906 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2907 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2908 ETH_LINK_SPEED_FIXED);
2910 if (!wait_to_complete && !enable_lse)
2911 update_link_reg(hw, &link);
2913 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2916 rte_eth_linkstatus_get(hw->switch_dev, &link);
2918 ret = rte_eth_linkstatus_set(dev, &link);
2919 i40e_notify_all_vfs_link_status(dev);
2924 /* Get all the statistics of a VSI */
2926 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2928 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2929 struct i40e_eth_stats *nes = &vsi->eth_stats;
2930 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2931 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2933 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2934 vsi->offset_loaded, &oes->rx_bytes,
2936 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2937 vsi->offset_loaded, &oes->rx_unicast,
2939 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2940 vsi->offset_loaded, &oes->rx_multicast,
2941 &nes->rx_multicast);
2942 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2943 vsi->offset_loaded, &oes->rx_broadcast,
2944 &nes->rx_broadcast);
2945 /* exclude CRC bytes */
2946 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2947 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2949 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2950 &oes->rx_discards, &nes->rx_discards);
2951 /* GLV_REPC not supported */
2952 /* GLV_RMPC not supported */
2953 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2954 &oes->rx_unknown_protocol,
2955 &nes->rx_unknown_protocol);
2956 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2957 vsi->offset_loaded, &oes->tx_bytes,
2959 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2960 vsi->offset_loaded, &oes->tx_unicast,
2962 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2963 vsi->offset_loaded, &oes->tx_multicast,
2964 &nes->tx_multicast);
2965 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2966 vsi->offset_loaded, &oes->tx_broadcast,
2967 &nes->tx_broadcast);
2968 /* GLV_TDPC not supported */
2969 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2970 &oes->tx_errors, &nes->tx_errors);
2971 vsi->offset_loaded = true;
2973 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2975 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2976 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2977 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2978 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2979 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2980 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2981 nes->rx_unknown_protocol);
2982 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2983 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2984 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2985 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2986 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2987 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2988 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2993 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2996 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2997 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2999 /* Get rx/tx bytes of internal transfer packets */
3000 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3001 I40E_GLV_GORCL(hw->port),
3003 &pf->internal_stats_offset.rx_bytes,
3004 &pf->internal_stats.rx_bytes);
3006 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3007 I40E_GLV_GOTCL(hw->port),
3009 &pf->internal_stats_offset.tx_bytes,
3010 &pf->internal_stats.tx_bytes);
3011 /* Get total internal rx packet count */
3012 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3013 I40E_GLV_UPRCL(hw->port),
3015 &pf->internal_stats_offset.rx_unicast,
3016 &pf->internal_stats.rx_unicast);
3017 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3018 I40E_GLV_MPRCL(hw->port),
3020 &pf->internal_stats_offset.rx_multicast,
3021 &pf->internal_stats.rx_multicast);
3022 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3023 I40E_GLV_BPRCL(hw->port),
3025 &pf->internal_stats_offset.rx_broadcast,
3026 &pf->internal_stats.rx_broadcast);
3027 /* Get total internal tx packet count */
3028 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3029 I40E_GLV_UPTCL(hw->port),
3031 &pf->internal_stats_offset.tx_unicast,
3032 &pf->internal_stats.tx_unicast);
3033 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3034 I40E_GLV_MPTCL(hw->port),
3036 &pf->internal_stats_offset.tx_multicast,
3037 &pf->internal_stats.tx_multicast);
3038 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3039 I40E_GLV_BPTCL(hw->port),
3041 &pf->internal_stats_offset.tx_broadcast,
3042 &pf->internal_stats.tx_broadcast);
3044 /* exclude CRC size */
3045 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3046 pf->internal_stats.rx_multicast +
3047 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3049 /* Get statistics of struct i40e_eth_stats */
3050 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3051 I40E_GLPRT_GORCL(hw->port),
3052 pf->offset_loaded, &os->eth.rx_bytes,
3054 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3055 I40E_GLPRT_UPRCL(hw->port),
3056 pf->offset_loaded, &os->eth.rx_unicast,
3057 &ns->eth.rx_unicast);
3058 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3059 I40E_GLPRT_MPRCL(hw->port),
3060 pf->offset_loaded, &os->eth.rx_multicast,
3061 &ns->eth.rx_multicast);
3062 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3063 I40E_GLPRT_BPRCL(hw->port),
3064 pf->offset_loaded, &os->eth.rx_broadcast,
3065 &ns->eth.rx_broadcast);
3066 /* Workaround: CRC size should not be included in byte statistics,
3067 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3070 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3071 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3073 /* exclude internal rx bytes
3074 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3075 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3077 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3079 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3080 ns->eth.rx_bytes = 0;
3082 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3084 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3085 ns->eth.rx_unicast = 0;
3087 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3089 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3090 ns->eth.rx_multicast = 0;
3092 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3094 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3095 ns->eth.rx_broadcast = 0;
3097 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3099 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3100 pf->offset_loaded, &os->eth.rx_discards,
3101 &ns->eth.rx_discards);
3102 /* GLPRT_REPC not supported */
3103 /* GLPRT_RMPC not supported */
3104 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3106 &os->eth.rx_unknown_protocol,
3107 &ns->eth.rx_unknown_protocol);
3108 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3109 I40E_GLPRT_GOTCL(hw->port),
3110 pf->offset_loaded, &os->eth.tx_bytes,
3112 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3113 I40E_GLPRT_UPTCL(hw->port),
3114 pf->offset_loaded, &os->eth.tx_unicast,
3115 &ns->eth.tx_unicast);
3116 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3117 I40E_GLPRT_MPTCL(hw->port),
3118 pf->offset_loaded, &os->eth.tx_multicast,
3119 &ns->eth.tx_multicast);
3120 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3121 I40E_GLPRT_BPTCL(hw->port),
3122 pf->offset_loaded, &os->eth.tx_broadcast,
3123 &ns->eth.tx_broadcast);
3124 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3125 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3127 /* exclude internal tx bytes
3128 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3129 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3131 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3133 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3134 ns->eth.tx_bytes = 0;
3136 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3138 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3139 ns->eth.tx_unicast = 0;
3141 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3143 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3144 ns->eth.tx_multicast = 0;
3146 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3148 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3149 ns->eth.tx_broadcast = 0;
3151 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3153 /* GLPRT_TEPC not supported */
3155 /* additional port specific stats */
3156 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3157 pf->offset_loaded, &os->tx_dropped_link_down,
3158 &ns->tx_dropped_link_down);
3159 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3160 pf->offset_loaded, &os->crc_errors,
3162 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3163 pf->offset_loaded, &os->illegal_bytes,
3164 &ns->illegal_bytes);
3165 /* GLPRT_ERRBC not supported */
3166 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3167 pf->offset_loaded, &os->mac_local_faults,
3168 &ns->mac_local_faults);
3169 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3170 pf->offset_loaded, &os->mac_remote_faults,
3171 &ns->mac_remote_faults);
3172 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3173 pf->offset_loaded, &os->rx_length_errors,
3174 &ns->rx_length_errors);
3175 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3176 pf->offset_loaded, &os->link_xon_rx,
3178 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3179 pf->offset_loaded, &os->link_xoff_rx,
3181 for (i = 0; i < 8; i++) {
3182 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3184 &os->priority_xon_rx[i],
3185 &ns->priority_xon_rx[i]);
3186 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3188 &os->priority_xoff_rx[i],
3189 &ns->priority_xoff_rx[i]);
3191 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3192 pf->offset_loaded, &os->link_xon_tx,
3194 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3195 pf->offset_loaded, &os->link_xoff_tx,
3197 for (i = 0; i < 8; i++) {
3198 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3200 &os->priority_xon_tx[i],
3201 &ns->priority_xon_tx[i]);
3202 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3204 &os->priority_xoff_tx[i],
3205 &ns->priority_xoff_tx[i]);
3206 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3208 &os->priority_xon_2_xoff[i],
3209 &ns->priority_xon_2_xoff[i]);
3211 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3212 I40E_GLPRT_PRC64L(hw->port),
3213 pf->offset_loaded, &os->rx_size_64,
3215 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3216 I40E_GLPRT_PRC127L(hw->port),
3217 pf->offset_loaded, &os->rx_size_127,
3219 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3220 I40E_GLPRT_PRC255L(hw->port),
3221 pf->offset_loaded, &os->rx_size_255,
3223 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3224 I40E_GLPRT_PRC511L(hw->port),
3225 pf->offset_loaded, &os->rx_size_511,
3227 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3228 I40E_GLPRT_PRC1023L(hw->port),
3229 pf->offset_loaded, &os->rx_size_1023,
3231 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3232 I40E_GLPRT_PRC1522L(hw->port),
3233 pf->offset_loaded, &os->rx_size_1522,
3235 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3236 I40E_GLPRT_PRC9522L(hw->port),
3237 pf->offset_loaded, &os->rx_size_big,
3239 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3240 pf->offset_loaded, &os->rx_undersize,
3242 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3243 pf->offset_loaded, &os->rx_fragments,
3245 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3246 pf->offset_loaded, &os->rx_oversize,
3248 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3249 pf->offset_loaded, &os->rx_jabber,
3251 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3252 I40E_GLPRT_PTC64L(hw->port),
3253 pf->offset_loaded, &os->tx_size_64,
3255 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3256 I40E_GLPRT_PTC127L(hw->port),
3257 pf->offset_loaded, &os->tx_size_127,
3259 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3260 I40E_GLPRT_PTC255L(hw->port),
3261 pf->offset_loaded, &os->tx_size_255,
3263 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3264 I40E_GLPRT_PTC511L(hw->port),
3265 pf->offset_loaded, &os->tx_size_511,
3267 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3268 I40E_GLPRT_PTC1023L(hw->port),
3269 pf->offset_loaded, &os->tx_size_1023,
3271 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3272 I40E_GLPRT_PTC1522L(hw->port),
3273 pf->offset_loaded, &os->tx_size_1522,
3275 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3276 I40E_GLPRT_PTC9522L(hw->port),
3277 pf->offset_loaded, &os->tx_size_big,
3279 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3281 &os->fd_sb_match, &ns->fd_sb_match);
3282 /* GLPRT_MSPDC not supported */
3283 /* GLPRT_XEC not supported */
3285 pf->offset_loaded = true;
3288 i40e_update_vsi_stats(pf->main_vsi);
3291 /* Get all statistics of a port */
3293 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3296 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3297 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3298 struct i40e_vsi *vsi;
3301 /* call read registers - updates values, now write them to struct */
3302 i40e_read_stats_registers(pf, hw);
3304 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3305 pf->main_vsi->eth_stats.rx_multicast +
3306 pf->main_vsi->eth_stats.rx_broadcast -
3307 pf->main_vsi->eth_stats.rx_discards;
3308 stats->opackets = ns->eth.tx_unicast +
3309 ns->eth.tx_multicast +
3310 ns->eth.tx_broadcast;
3311 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3312 stats->obytes = ns->eth.tx_bytes;
3313 stats->oerrors = ns->eth.tx_errors +
3314 pf->main_vsi->eth_stats.tx_errors;
3317 stats->imissed = ns->eth.rx_discards +
3318 pf->main_vsi->eth_stats.rx_discards;
3319 stats->ierrors = ns->crc_errors +
3320 ns->rx_length_errors + ns->rx_undersize +
3321 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3324 for (i = 0; i < pf->vf_num; i++) {
3325 vsi = pf->vfs[i].vsi;
3326 i40e_update_vsi_stats(vsi);
3328 stats->ipackets += (vsi->eth_stats.rx_unicast +
3329 vsi->eth_stats.rx_multicast +
3330 vsi->eth_stats.rx_broadcast -
3331 vsi->eth_stats.rx_discards);
3332 stats->ibytes += vsi->eth_stats.rx_bytes;
3333 stats->oerrors += vsi->eth_stats.tx_errors;
3334 stats->imissed += vsi->eth_stats.rx_discards;
3338 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3339 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3340 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3341 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3342 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3343 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3344 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3345 ns->eth.rx_unknown_protocol);
3346 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3347 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3348 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3349 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3350 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3351 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3353 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3354 ns->tx_dropped_link_down);
3355 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3356 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3358 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3359 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3360 ns->mac_local_faults);
3361 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3362 ns->mac_remote_faults);
3363 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3364 ns->rx_length_errors);
3365 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3366 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3367 for (i = 0; i < 8; i++) {
3368 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3369 i, ns->priority_xon_rx[i]);
3370 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3371 i, ns->priority_xoff_rx[i]);
3373 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3374 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3375 for (i = 0; i < 8; i++) {
3376 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3377 i, ns->priority_xon_tx[i]);
3378 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3379 i, ns->priority_xoff_tx[i]);
3380 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3381 i, ns->priority_xon_2_xoff[i]);
3383 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3384 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3385 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3386 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3387 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3388 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3389 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3390 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3391 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3392 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3393 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3394 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3395 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3396 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3397 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3398 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3399 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3400 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3401 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3402 ns->mac_short_packet_dropped);
3403 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3404 ns->checksum_error);
3405 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3406 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3410 /* Reset the statistics */
3412 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3414 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3415 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417 /* Mark PF and VSI stats to update the offset, aka "reset" */
3418 pf->offset_loaded = false;
3420 pf->main_vsi->offset_loaded = false;
3422 /* read the stats, reading current register values into offset */
3423 i40e_read_stats_registers(pf, hw);
3429 i40e_xstats_calc_num(void)
3431 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3432 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3433 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3436 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3437 struct rte_eth_xstat_name *xstats_names,
3438 __rte_unused unsigned limit)
3443 if (xstats_names == NULL)
3444 return i40e_xstats_calc_num();
3446 /* Note: limit checked in rte_eth_xstats_names() */
3448 /* Get stats from i40e_eth_stats struct */
3449 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3450 strlcpy(xstats_names[count].name,
3451 rte_i40e_stats_strings[i].name,
3452 sizeof(xstats_names[count].name));
3456 /* Get individiual stats from i40e_hw_port struct */
3457 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3458 strlcpy(xstats_names[count].name,
3459 rte_i40e_hw_port_strings[i].name,
3460 sizeof(xstats_names[count].name));
3464 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3465 for (prio = 0; prio < 8; prio++) {
3466 snprintf(xstats_names[count].name,
3467 sizeof(xstats_names[count].name),
3468 "rx_priority%u_%s", prio,
3469 rte_i40e_rxq_prio_strings[i].name);
3474 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3475 for (prio = 0; prio < 8; prio++) {
3476 snprintf(xstats_names[count].name,
3477 sizeof(xstats_names[count].name),
3478 "tx_priority%u_%s", prio,
3479 rte_i40e_txq_prio_strings[i].name);
3487 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3490 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3492 unsigned i, count, prio;
3493 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3495 count = i40e_xstats_calc_num();
3499 i40e_read_stats_registers(pf, hw);
3506 /* Get stats from i40e_eth_stats struct */
3507 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3508 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3509 rte_i40e_stats_strings[i].offset);
3510 xstats[count].id = count;
3514 /* Get individiual stats from i40e_hw_port struct */
3515 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3516 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3517 rte_i40e_hw_port_strings[i].offset);
3518 xstats[count].id = count;
3522 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3523 for (prio = 0; prio < 8; prio++) {
3524 xstats[count].value =
3525 *(uint64_t *)(((char *)hw_stats) +
3526 rte_i40e_rxq_prio_strings[i].offset +
3527 (sizeof(uint64_t) * prio));
3528 xstats[count].id = count;
3533 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3534 for (prio = 0; prio < 8; prio++) {
3535 xstats[count].value =
3536 *(uint64_t *)(((char *)hw_stats) +
3537 rte_i40e_txq_prio_strings[i].offset +
3538 (sizeof(uint64_t) * prio));
3539 xstats[count].id = count;
3548 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3550 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3556 full_ver = hw->nvm.oem_ver;
3557 ver = (u8)(full_ver >> 24);
3558 build = (u16)((full_ver >> 8) & 0xffff);
3559 patch = (u8)(full_ver & 0xff);
3561 ret = snprintf(fw_version, fw_size,
3562 "%d.%d%d 0x%08x %d.%d.%d",
3563 ((hw->nvm.version >> 12) & 0xf),
3564 ((hw->nvm.version >> 4) & 0xff),
3565 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3568 ret += 1; /* add the size of '\0' */
3569 if (fw_size < (u32)ret)
3576 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3577 * the Rx data path does not hang if the FW LLDP is stopped.
3578 * return true if lldp need to stop
3579 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3582 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3585 char ver_str[64] = {0};
3586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588 i40e_fw_version_get(dev, ver_str, 64);
3589 nvm_ver = atof(ver_str);
3590 if ((hw->mac.type == I40E_MAC_X722 ||
3591 hw->mac.type == I40E_MAC_X722_VF) &&
3592 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3594 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3601 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3603 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605 struct i40e_vsi *vsi = pf->main_vsi;
3606 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3608 dev_info->max_rx_queues = vsi->nb_qps;
3609 dev_info->max_tx_queues = vsi->nb_qps;
3610 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3611 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3612 dev_info->max_mac_addrs = vsi->max_macaddrs;
3613 dev_info->max_vfs = pci_dev->max_vfs;
3614 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3615 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3616 dev_info->rx_queue_offload_capa = 0;
3617 dev_info->rx_offload_capa =
3618 DEV_RX_OFFLOAD_VLAN_STRIP |
3619 DEV_RX_OFFLOAD_QINQ_STRIP |
3620 DEV_RX_OFFLOAD_IPV4_CKSUM |
3621 DEV_RX_OFFLOAD_UDP_CKSUM |
3622 DEV_RX_OFFLOAD_TCP_CKSUM |
3623 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3624 DEV_RX_OFFLOAD_KEEP_CRC |
3625 DEV_RX_OFFLOAD_SCATTER |
3626 DEV_RX_OFFLOAD_VLAN_EXTEND |
3627 DEV_RX_OFFLOAD_VLAN_FILTER |
3628 DEV_RX_OFFLOAD_JUMBO_FRAME |
3629 DEV_RX_OFFLOAD_RSS_HASH;
3631 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3632 dev_info->tx_offload_capa =
3633 DEV_TX_OFFLOAD_VLAN_INSERT |
3634 DEV_TX_OFFLOAD_QINQ_INSERT |
3635 DEV_TX_OFFLOAD_IPV4_CKSUM |
3636 DEV_TX_OFFLOAD_UDP_CKSUM |
3637 DEV_TX_OFFLOAD_TCP_CKSUM |
3638 DEV_TX_OFFLOAD_SCTP_CKSUM |
3639 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3640 DEV_TX_OFFLOAD_TCP_TSO |
3641 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3642 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3643 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3644 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3645 DEV_TX_OFFLOAD_MULTI_SEGS |
3646 dev_info->tx_queue_offload_capa;
3647 dev_info->dev_capa =
3648 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3649 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3651 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3653 dev_info->reta_size = pf->hash_lut_size;
3654 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3656 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3658 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3659 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3660 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3662 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3667 dev_info->default_txconf = (struct rte_eth_txconf) {
3669 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3670 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3671 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3673 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3674 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3678 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3679 .nb_max = I40E_MAX_RING_DESC,
3680 .nb_min = I40E_MIN_RING_DESC,
3681 .nb_align = I40E_ALIGN_RING_DESC,
3684 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3685 .nb_max = I40E_MAX_RING_DESC,
3686 .nb_min = I40E_MIN_RING_DESC,
3687 .nb_align = I40E_ALIGN_RING_DESC,
3688 .nb_seg_max = I40E_TX_MAX_SEG,
3689 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3692 if (pf->flags & I40E_FLAG_VMDQ) {
3693 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3694 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3695 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3696 pf->max_nb_vmdq_vsi;
3697 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3698 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3699 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3702 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3704 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3705 dev_info->default_rxportconf.nb_queues = 2;
3706 dev_info->default_txportconf.nb_queues = 2;
3707 if (dev->data->nb_rx_queues == 1)
3708 dev_info->default_rxportconf.ring_size = 2048;
3710 dev_info->default_rxportconf.ring_size = 1024;
3711 if (dev->data->nb_tx_queues == 1)
3712 dev_info->default_txportconf.ring_size = 1024;
3714 dev_info->default_txportconf.ring_size = 512;
3716 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3718 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3719 dev_info->default_rxportconf.nb_queues = 1;
3720 dev_info->default_txportconf.nb_queues = 1;
3721 dev_info->default_rxportconf.ring_size = 256;
3722 dev_info->default_txportconf.ring_size = 256;
3725 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3726 dev_info->default_rxportconf.nb_queues = 1;
3727 dev_info->default_txportconf.nb_queues = 1;
3728 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3729 dev_info->default_rxportconf.ring_size = 512;
3730 dev_info->default_txportconf.ring_size = 256;
3732 dev_info->default_rxportconf.ring_size = 256;
3733 dev_info->default_txportconf.ring_size = 256;
3736 dev_info->default_rxportconf.burst_size = 32;
3737 dev_info->default_txportconf.burst_size = 32;
3743 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3745 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3746 struct i40e_vsi *vsi = pf->main_vsi;
3747 PMD_INIT_FUNC_TRACE();
3750 return i40e_vsi_add_vlan(vsi, vlan_id);
3752 return i40e_vsi_delete_vlan(vsi, vlan_id);
3756 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3757 enum rte_vlan_type vlan_type,
3758 uint16_t tpid, int qinq)
3760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763 uint16_t reg_id = 3;
3767 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3771 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3773 if (ret != I40E_SUCCESS) {
3775 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3780 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3783 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3784 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3785 if (reg_r == reg_w) {
3786 PMD_DRV_LOG(DEBUG, "No need to write");
3790 ret = i40e_aq_debug_write_global_register(hw,
3791 I40E_GL_SWT_L2TAGCTRL(reg_id),
3793 if (ret != I40E_SUCCESS) {
3795 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3800 "Global register 0x%08x is changed with value 0x%08x",
3801 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3807 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3808 enum rte_vlan_type vlan_type,
3811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3813 int qinq = dev->data->dev_conf.rxmode.offloads &
3814 DEV_RX_OFFLOAD_VLAN_EXTEND;
3817 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3818 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3819 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3821 "Unsupported vlan type.");
3825 if (pf->support_multi_driver) {
3826 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3830 /* 802.1ad frames ability is added in NVM API 1.7*/
3831 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3833 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3834 hw->first_tag = rte_cpu_to_le_16(tpid);
3835 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3836 hw->second_tag = rte_cpu_to_le_16(tpid);
3838 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3839 hw->second_tag = rte_cpu_to_le_16(tpid);
3841 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3842 if (ret != I40E_SUCCESS) {
3844 "Set switch config failed aq_err: %d",
3845 hw->aq.asq_last_status);
3849 /* If NVM API < 1.7, keep the register setting */
3850 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3857 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3859 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3860 struct i40e_vsi *vsi = pf->main_vsi;
3861 struct rte_eth_rxmode *rxmode;
3863 if (mask & ETH_QINQ_STRIP_MASK) {
3864 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3868 rxmode = &dev->data->dev_conf.rxmode;
3869 if (mask & ETH_VLAN_FILTER_MASK) {
3870 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3871 i40e_vsi_config_vlan_filter(vsi, TRUE);
3873 i40e_vsi_config_vlan_filter(vsi, FALSE);
3876 if (mask & ETH_VLAN_STRIP_MASK) {
3877 /* Enable or disable VLAN stripping */
3878 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3879 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3881 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3884 if (mask & ETH_VLAN_EXTEND_MASK) {
3885 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3886 i40e_vsi_config_double_vlan(vsi, TRUE);
3887 /* Set global registers with default ethertype. */
3888 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3889 RTE_ETHER_TYPE_VLAN);
3890 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3891 RTE_ETHER_TYPE_VLAN);
3894 i40e_vsi_config_double_vlan(vsi, FALSE);
3901 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3902 __rte_unused uint16_t queue,
3903 __rte_unused int on)
3905 PMD_INIT_FUNC_TRACE();
3909 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3912 struct i40e_vsi *vsi = pf->main_vsi;
3913 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3914 struct i40e_vsi_vlan_pvid_info info;
3916 memset(&info, 0, sizeof(info));
3919 info.config.pvid = pvid;
3921 info.config.reject.tagged =
3922 data->dev_conf.txmode.hw_vlan_reject_tagged;
3923 info.config.reject.untagged =
3924 data->dev_conf.txmode.hw_vlan_reject_untagged;
3927 return i40e_vsi_vlan_pvid_set(vsi, &info);
3931 i40e_dev_led_on(struct rte_eth_dev *dev)
3933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934 uint32_t mode = i40e_led_get(hw);
3937 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3943 i40e_dev_led_off(struct rte_eth_dev *dev)
3945 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946 uint32_t mode = i40e_led_get(hw);
3949 i40e_led_set(hw, 0, false);
3955 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3957 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3960 fc_conf->pause_time = pf->fc_conf.pause_time;
3962 /* read out from register, in case they are modified by other port */
3963 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3964 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3965 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3966 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3968 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3969 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3971 /* Return current mode according to actual setting*/
3972 switch (hw->fc.current_mode) {
3974 fc_conf->mode = RTE_FC_FULL;
3976 case I40E_FC_TX_PAUSE:
3977 fc_conf->mode = RTE_FC_TX_PAUSE;
3979 case I40E_FC_RX_PAUSE:
3980 fc_conf->mode = RTE_FC_RX_PAUSE;
3984 fc_conf->mode = RTE_FC_NONE;
3991 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3993 uint32_t mflcn_reg, fctrl_reg, reg;
3994 uint32_t max_high_water;
3995 uint8_t i, aq_failure;
3999 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4000 [RTE_FC_NONE] = I40E_FC_NONE,
4001 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4002 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4003 [RTE_FC_FULL] = I40E_FC_FULL
4006 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4008 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4009 if ((fc_conf->high_water > max_high_water) ||
4010 (fc_conf->high_water < fc_conf->low_water)) {
4012 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4017 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4018 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4019 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4021 pf->fc_conf.pause_time = fc_conf->pause_time;
4022 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4023 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4025 PMD_INIT_FUNC_TRACE();
4027 /* All the link flow control related enable/disable register
4028 * configuration is handle by the F/W
4030 err = i40e_set_fc(hw, &aq_failure, true);
4034 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4035 /* Configure flow control refresh threshold,
4036 * the value for stat_tx_pause_refresh_timer[8]
4037 * is used for global pause operation.
4041 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4042 pf->fc_conf.pause_time);
4044 /* configure the timer value included in transmitted pause
4046 * the value for stat_tx_pause_quanta[8] is used for global
4049 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4050 pf->fc_conf.pause_time);
4052 fctrl_reg = I40E_READ_REG(hw,
4053 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4055 if (fc_conf->mac_ctrl_frame_fwd != 0)
4056 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4058 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4060 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4063 /* Configure pause time (2 TCs per register) */
4064 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4065 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4066 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4068 /* Configure flow control refresh threshold value */
4069 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4070 pf->fc_conf.pause_time / 2);
4072 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4074 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4075 *depending on configuration
4077 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4078 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4079 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4081 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4082 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4085 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4088 if (!pf->support_multi_driver) {
4089 /* config water marker both based on the packets and bytes */
4090 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4091 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4092 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4093 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4094 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4095 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4096 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4097 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4099 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4100 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4104 "Water marker configuration is not supported.");
4107 I40E_WRITE_FLUSH(hw);
4113 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4114 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4116 PMD_INIT_FUNC_TRACE();
4121 /* Add a MAC address, and update filters */
4123 i40e_macaddr_add(struct rte_eth_dev *dev,
4124 struct rte_ether_addr *mac_addr,
4125 __rte_unused uint32_t index,
4128 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4129 struct i40e_mac_filter_info mac_filter;
4130 struct i40e_vsi *vsi;
4131 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4134 /* If VMDQ not enabled or configured, return */
4135 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4136 !pf->nb_cfg_vmdq_vsi)) {
4137 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4138 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4143 if (pool > pf->nb_cfg_vmdq_vsi) {
4144 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4145 pool, pf->nb_cfg_vmdq_vsi);
4149 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4150 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4151 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4153 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4158 vsi = pf->vmdq[pool - 1].vsi;
4160 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4161 if (ret != I40E_SUCCESS) {
4162 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4168 /* Remove a MAC address, and update filters */
4170 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4172 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4173 struct i40e_vsi *vsi;
4174 struct rte_eth_dev_data *data = dev->data;
4175 struct rte_ether_addr *macaddr;
4180 macaddr = &(data->mac_addrs[index]);
4182 pool_sel = dev->data->mac_pool_sel[index];
4184 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4185 if (pool_sel & (1ULL << i)) {
4189 /* No VMDQ pool enabled or configured */
4190 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4191 (i > pf->nb_cfg_vmdq_vsi)) {
4193 "No VMDQ pool enabled/configured");
4196 vsi = pf->vmdq[i - 1].vsi;
4198 ret = i40e_vsi_delete_mac(vsi, macaddr);
4201 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4208 /* Set perfect match or hash match of MAC and VLAN for a VF */
4210 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4211 struct rte_eth_mac_filter *filter,
4215 struct i40e_mac_filter_info mac_filter;
4216 struct rte_ether_addr old_mac;
4217 struct rte_ether_addr *new_mac;
4218 struct i40e_pf_vf *vf = NULL;
4223 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4226 hw = I40E_PF_TO_HW(pf);
4228 if (filter == NULL) {
4229 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4233 new_mac = &filter->mac_addr;
4235 if (rte_is_zero_ether_addr(new_mac)) {
4236 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4240 vf_id = filter->dst_id;
4242 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4243 PMD_DRV_LOG(ERR, "Invalid argument.");
4246 vf = &pf->vfs[vf_id];
4248 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4249 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4254 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4255 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4256 RTE_ETHER_ADDR_LEN);
4257 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4258 RTE_ETHER_ADDR_LEN);
4260 mac_filter.filter_type = filter->filter_type;
4261 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4262 if (ret != I40E_SUCCESS) {
4263 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4266 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4268 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4269 RTE_ETHER_ADDR_LEN);
4270 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4271 if (ret != I40E_SUCCESS) {
4272 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4276 /* Clear device address as it has been removed */
4277 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4278 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4284 /* MAC filter handle */
4286 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4289 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4290 struct rte_eth_mac_filter *filter;
4291 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4292 int ret = I40E_NOT_SUPPORTED;
4294 filter = (struct rte_eth_mac_filter *)(arg);
4296 switch (filter_op) {
4297 case RTE_ETH_FILTER_NOP:
4300 case RTE_ETH_FILTER_ADD:
4301 i40e_pf_disable_irq0(hw);
4303 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4304 i40e_pf_enable_irq0(hw);
4306 case RTE_ETH_FILTER_DELETE:
4307 i40e_pf_disable_irq0(hw);
4309 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4310 i40e_pf_enable_irq0(hw);
4313 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4314 ret = I40E_ERR_PARAM;
4322 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4324 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4325 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4332 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4333 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4334 vsi->type != I40E_VSI_SRIOV,
4337 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4341 uint32_t *lut_dw = (uint32_t *)lut;
4342 uint16_t i, lut_size_dw = lut_size / 4;
4344 if (vsi->type == I40E_VSI_SRIOV) {
4345 for (i = 0; i <= lut_size_dw; i++) {
4346 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4347 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4350 for (i = 0; i < lut_size_dw; i++)
4351 lut_dw[i] = I40E_READ_REG(hw,
4360 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4369 pf = I40E_VSI_TO_PF(vsi);
4370 hw = I40E_VSI_TO_HW(vsi);
4372 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4373 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4374 vsi->type != I40E_VSI_SRIOV,
4377 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4381 uint32_t *lut_dw = (uint32_t *)lut;
4382 uint16_t i, lut_size_dw = lut_size / 4;
4384 if (vsi->type == I40E_VSI_SRIOV) {
4385 for (i = 0; i < lut_size_dw; i++)
4388 I40E_VFQF_HLUT1(i, vsi->user_param),
4391 for (i = 0; i < lut_size_dw; i++)
4392 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4395 I40E_WRITE_FLUSH(hw);
4402 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4403 struct rte_eth_rss_reta_entry64 *reta_conf,
4406 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4407 uint16_t i, lut_size = pf->hash_lut_size;
4408 uint16_t idx, shift;
4412 if (reta_size != lut_size ||
4413 reta_size > ETH_RSS_RETA_SIZE_512) {
4415 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4416 reta_size, lut_size);
4420 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4422 PMD_DRV_LOG(ERR, "No memory can be allocated");
4425 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4428 for (i = 0; i < reta_size; i++) {
4429 idx = i / RTE_RETA_GROUP_SIZE;
4430 shift = i % RTE_RETA_GROUP_SIZE;
4431 if (reta_conf[idx].mask & (1ULL << shift))
4432 lut[i] = reta_conf[idx].reta[shift];
4434 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4436 pf->adapter->rss_reta_updated = 1;
4445 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4446 struct rte_eth_rss_reta_entry64 *reta_conf,
4449 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4450 uint16_t i, lut_size = pf->hash_lut_size;
4451 uint16_t idx, shift;
4455 if (reta_size != lut_size ||
4456 reta_size > ETH_RSS_RETA_SIZE_512) {
4458 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4459 reta_size, lut_size);
4463 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4465 PMD_DRV_LOG(ERR, "No memory can be allocated");
4469 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4472 for (i = 0; i < reta_size; i++) {
4473 idx = i / RTE_RETA_GROUP_SIZE;
4474 shift = i % RTE_RETA_GROUP_SIZE;
4475 if (reta_conf[idx].mask & (1ULL << shift))
4476 reta_conf[idx].reta[shift] = lut[i];
4486 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4487 * @hw: pointer to the HW structure
4488 * @mem: pointer to mem struct to fill out
4489 * @size: size of memory requested
4490 * @alignment: what to align the allocation to
4492 enum i40e_status_code
4493 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4494 struct i40e_dma_mem *mem,
4498 const struct rte_memzone *mz = NULL;
4499 char z_name[RTE_MEMZONE_NAMESIZE];
4502 return I40E_ERR_PARAM;
4504 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4505 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4506 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4508 return I40E_ERR_NO_MEMORY;
4513 mem->zone = (const void *)mz;
4515 "memzone %s allocated with physical address: %"PRIu64,
4518 return I40E_SUCCESS;
4522 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4523 * @hw: pointer to the HW structure
4524 * @mem: ptr to mem struct to free
4526 enum i40e_status_code
4527 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4528 struct i40e_dma_mem *mem)
4531 return I40E_ERR_PARAM;
4534 "memzone %s to be freed with physical address: %"PRIu64,
4535 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4536 rte_memzone_free((const struct rte_memzone *)mem->zone);
4541 return I40E_SUCCESS;
4545 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4546 * @hw: pointer to the HW structure
4547 * @mem: pointer to mem struct to fill out
4548 * @size: size of memory requested
4550 enum i40e_status_code
4551 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4552 struct i40e_virt_mem *mem,
4556 return I40E_ERR_PARAM;
4559 mem->va = rte_zmalloc("i40e", size, 0);
4562 return I40E_SUCCESS;
4564 return I40E_ERR_NO_MEMORY;
4568 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4569 * @hw: pointer to the HW structure
4570 * @mem: pointer to mem struct to free
4572 enum i40e_status_code
4573 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4574 struct i40e_virt_mem *mem)
4577 return I40E_ERR_PARAM;
4582 return I40E_SUCCESS;
4586 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4588 rte_spinlock_init(&sp->spinlock);
4592 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4594 rte_spinlock_lock(&sp->spinlock);
4598 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4600 rte_spinlock_unlock(&sp->spinlock);
4604 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4610 * Get the hardware capabilities, which will be parsed
4611 * and saved into struct i40e_hw.
4614 i40e_get_cap(struct i40e_hw *hw)
4616 struct i40e_aqc_list_capabilities_element_resp *buf;
4617 uint16_t len, size = 0;
4620 /* Calculate a huge enough buff for saving response data temporarily */
4621 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4622 I40E_MAX_CAP_ELE_NUM;
4623 buf = rte_zmalloc("i40e", len, 0);
4625 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4626 return I40E_ERR_NO_MEMORY;
4629 /* Get, parse the capabilities and save it to hw */
4630 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4631 i40e_aqc_opc_list_func_capabilities, NULL);
4632 if (ret != I40E_SUCCESS)
4633 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4635 /* Free the temporary buffer after being used */
4641 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4643 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4651 pf = (struct i40e_pf *)opaque;
4655 num = strtoul(value, &end, 0);
4656 if (errno != 0 || end == value || *end != 0) {
4657 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4658 "kept the value = %hu", value, pf->vf_nb_qp_max);
4662 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4663 pf->vf_nb_qp_max = (uint16_t)num;
4665 /* here return 0 to make next valid same argument work */
4666 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4667 "power of 2 and equal or less than 16 !, Now it is "
4668 "kept the value = %hu", num, pf->vf_nb_qp_max);
4673 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4675 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4676 struct rte_kvargs *kvlist;
4679 /* set default queue number per VF as 4 */
4680 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4682 if (dev->device->devargs == NULL)
4685 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4689 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4690 if (!kvargs_count) {
4691 rte_kvargs_free(kvlist);
4695 if (kvargs_count > 1)
4696 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4697 "the first invalid or last valid one is used !",
4698 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4700 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4701 i40e_pf_parse_vf_queue_number_handler, pf);
4703 rte_kvargs_free(kvlist);
4709 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4712 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4713 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4714 uint16_t qp_count = 0, vsi_count = 0;
4716 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4717 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4721 i40e_pf_config_vf_rxq_number(dev);
4723 /* Add the parameter init for LFC */
4724 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4725 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4726 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4728 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4729 pf->max_num_vsi = hw->func_caps.num_vsis;
4730 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4731 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4733 /* FDir queue/VSI allocation */
4734 pf->fdir_qp_offset = 0;
4735 if (hw->func_caps.fd) {
4736 pf->flags |= I40E_FLAG_FDIR;
4737 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4739 pf->fdir_nb_qps = 0;
4741 qp_count += pf->fdir_nb_qps;
4744 /* LAN queue/VSI allocation */
4745 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4746 if (!hw->func_caps.rss) {
4749 pf->flags |= I40E_FLAG_RSS;
4750 if (hw->mac.type == I40E_MAC_X722)
4751 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4752 pf->lan_nb_qps = pf->lan_nb_qp_max;
4754 qp_count += pf->lan_nb_qps;
4757 /* VF queue/VSI allocation */
4758 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4759 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4760 pf->flags |= I40E_FLAG_SRIOV;
4761 pf->vf_nb_qps = pf->vf_nb_qp_max;
4762 pf->vf_num = pci_dev->max_vfs;
4764 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4765 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4770 qp_count += pf->vf_nb_qps * pf->vf_num;
4771 vsi_count += pf->vf_num;
4773 /* VMDq queue/VSI allocation */
4774 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4775 pf->vmdq_nb_qps = 0;
4776 pf->max_nb_vmdq_vsi = 0;
4777 if (hw->func_caps.vmdq) {
4778 if (qp_count < hw->func_caps.num_tx_qp &&
4779 vsi_count < hw->func_caps.num_vsis) {
4780 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4781 qp_count) / pf->vmdq_nb_qp_max;
4783 /* Limit the maximum number of VMDq vsi to the maximum
4784 * ethdev can support
4786 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4787 hw->func_caps.num_vsis - vsi_count);
4788 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4790 if (pf->max_nb_vmdq_vsi) {
4791 pf->flags |= I40E_FLAG_VMDQ;
4792 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4794 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4795 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4796 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4799 "No enough queues left for VMDq");
4802 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4805 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4806 vsi_count += pf->max_nb_vmdq_vsi;
4808 if (hw->func_caps.dcb)
4809 pf->flags |= I40E_FLAG_DCB;
4811 if (qp_count > hw->func_caps.num_tx_qp) {
4813 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4814 qp_count, hw->func_caps.num_tx_qp);
4817 if (vsi_count > hw->func_caps.num_vsis) {
4819 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4820 vsi_count, hw->func_caps.num_vsis);
4828 i40e_pf_get_switch_config(struct i40e_pf *pf)
4830 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4831 struct i40e_aqc_get_switch_config_resp *switch_config;
4832 struct i40e_aqc_switch_config_element_resp *element;
4833 uint16_t start_seid = 0, num_reported;
4836 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4837 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4838 if (!switch_config) {
4839 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4843 /* Get the switch configurations */
4844 ret = i40e_aq_get_switch_config(hw, switch_config,
4845 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4846 if (ret != I40E_SUCCESS) {
4847 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4850 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4851 if (num_reported != 1) { /* The number should be 1 */
4852 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4856 /* Parse the switch configuration elements */
4857 element = &(switch_config->element[0]);
4858 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4859 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4860 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4862 PMD_DRV_LOG(INFO, "Unknown element type");
4865 rte_free(switch_config);
4871 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4874 struct pool_entry *entry;
4876 if (pool == NULL || num == 0)
4879 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4880 if (entry == NULL) {
4881 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4885 /* queue heap initialize */
4886 pool->num_free = num;
4887 pool->num_alloc = 0;
4889 LIST_INIT(&pool->alloc_list);
4890 LIST_INIT(&pool->free_list);
4892 /* Initialize element */
4896 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4901 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4903 struct pool_entry *entry, *next_entry;
4908 for (entry = LIST_FIRST(&pool->alloc_list);
4909 entry && (next_entry = LIST_NEXT(entry, next), 1);
4910 entry = next_entry) {
4911 LIST_REMOVE(entry, next);
4915 for (entry = LIST_FIRST(&pool->free_list);
4916 entry && (next_entry = LIST_NEXT(entry, next), 1);
4917 entry = next_entry) {
4918 LIST_REMOVE(entry, next);
4923 pool->num_alloc = 0;
4925 LIST_INIT(&pool->alloc_list);
4926 LIST_INIT(&pool->free_list);
4930 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4933 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4934 uint32_t pool_offset;
4938 PMD_DRV_LOG(ERR, "Invalid parameter");
4942 pool_offset = base - pool->base;
4943 /* Lookup in alloc list */
4944 LIST_FOREACH(entry, &pool->alloc_list, next) {
4945 if (entry->base == pool_offset) {
4946 valid_entry = entry;
4947 LIST_REMOVE(entry, next);
4952 /* Not find, return */
4953 if (valid_entry == NULL) {
4954 PMD_DRV_LOG(ERR, "Failed to find entry");
4959 * Found it, move it to free list and try to merge.
4960 * In order to make merge easier, always sort it by qbase.
4961 * Find adjacent prev and last entries.
4964 LIST_FOREACH(entry, &pool->free_list, next) {
4965 if (entry->base > valid_entry->base) {
4973 /* Try to merge with next one*/
4975 /* Merge with next one */
4976 if (valid_entry->base + valid_entry->len == next->base) {
4977 next->base = valid_entry->base;
4978 next->len += valid_entry->len;
4979 rte_free(valid_entry);
4986 /* Merge with previous one */
4987 if (prev->base + prev->len == valid_entry->base) {
4988 prev->len += valid_entry->len;
4989 /* If it merge with next one, remove next node */
4991 LIST_REMOVE(valid_entry, next);
4992 rte_free(valid_entry);
4994 rte_free(valid_entry);
5000 /* Not find any entry to merge, insert */
5003 LIST_INSERT_AFTER(prev, valid_entry, next);
5004 else if (next != NULL)
5005 LIST_INSERT_BEFORE(next, valid_entry, next);
5006 else /* It's empty list, insert to head */
5007 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5010 pool->num_free += valid_entry->len;
5011 pool->num_alloc -= valid_entry->len;
5017 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5020 struct pool_entry *entry, *valid_entry;
5022 if (pool == NULL || num == 0) {
5023 PMD_DRV_LOG(ERR, "Invalid parameter");
5027 if (pool->num_free < num) {
5028 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5029 num, pool->num_free);
5034 /* Lookup in free list and find most fit one */
5035 LIST_FOREACH(entry, &pool->free_list, next) {
5036 if (entry->len >= num) {
5038 if (entry->len == num) {
5039 valid_entry = entry;
5042 if (valid_entry == NULL || valid_entry->len > entry->len)
5043 valid_entry = entry;
5047 /* Not find one to satisfy the request, return */
5048 if (valid_entry == NULL) {
5049 PMD_DRV_LOG(ERR, "No valid entry found");
5053 * The entry have equal queue number as requested,
5054 * remove it from alloc_list.
5056 if (valid_entry->len == num) {
5057 LIST_REMOVE(valid_entry, next);
5060 * The entry have more numbers than requested,
5061 * create a new entry for alloc_list and minus its
5062 * queue base and number in free_list.
5064 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5065 if (entry == NULL) {
5067 "Failed to allocate memory for resource pool");
5070 entry->base = valid_entry->base;
5072 valid_entry->base += num;
5073 valid_entry->len -= num;
5074 valid_entry = entry;
5077 /* Insert it into alloc list, not sorted */
5078 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5080 pool->num_free -= valid_entry->len;
5081 pool->num_alloc += valid_entry->len;
5083 return valid_entry->base + pool->base;
5087 * bitmap_is_subset - Check whether src2 is subset of src1
5090 bitmap_is_subset(uint8_t src1, uint8_t src2)
5092 return !((src1 ^ src2) & src2);
5095 static enum i40e_status_code
5096 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5098 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5100 /* If DCB is not supported, only default TC is supported */
5101 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5102 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5103 return I40E_NOT_SUPPORTED;
5106 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5108 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5109 hw->func_caps.enabled_tcmap, enabled_tcmap);
5110 return I40E_NOT_SUPPORTED;
5112 return I40E_SUCCESS;
5116 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5117 struct i40e_vsi_vlan_pvid_info *info)
5120 struct i40e_vsi_context ctxt;
5121 uint8_t vlan_flags = 0;
5124 if (vsi == NULL || info == NULL) {
5125 PMD_DRV_LOG(ERR, "invalid parameters");
5126 return I40E_ERR_PARAM;
5130 vsi->info.pvid = info->config.pvid;
5132 * If insert pvid is enabled, only tagged pkts are
5133 * allowed to be sent out.
5135 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5136 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5139 if (info->config.reject.tagged == 0)
5140 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5142 if (info->config.reject.untagged == 0)
5143 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5145 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5146 I40E_AQ_VSI_PVLAN_MODE_MASK);
5147 vsi->info.port_vlan_flags |= vlan_flags;
5148 vsi->info.valid_sections =
5149 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5150 memset(&ctxt, 0, sizeof(ctxt));
5151 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5152 ctxt.seid = vsi->seid;
5154 hw = I40E_VSI_TO_HW(vsi);
5155 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5156 if (ret != I40E_SUCCESS)
5157 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5163 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5165 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5167 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5169 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5170 if (ret != I40E_SUCCESS)
5174 PMD_DRV_LOG(ERR, "seid not valid");
5178 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5179 tc_bw_data.tc_valid_bits = enabled_tcmap;
5180 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5181 tc_bw_data.tc_bw_credits[i] =
5182 (enabled_tcmap & (1 << i)) ? 1 : 0;
5184 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5185 if (ret != I40E_SUCCESS) {
5186 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5190 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5191 sizeof(vsi->info.qs_handle));
5192 return I40E_SUCCESS;
5195 static enum i40e_status_code
5196 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5197 struct i40e_aqc_vsi_properties_data *info,
5198 uint8_t enabled_tcmap)
5200 enum i40e_status_code ret;
5201 int i, total_tc = 0;
5202 uint16_t qpnum_per_tc, bsf, qp_idx;
5204 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5205 if (ret != I40E_SUCCESS)
5208 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5209 if (enabled_tcmap & (1 << i))
5213 vsi->enabled_tc = enabled_tcmap;
5215 /* Number of queues per enabled TC */
5216 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5217 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5218 bsf = rte_bsf32(qpnum_per_tc);
5220 /* Adjust the queue number to actual queues that can be applied */
5221 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5222 vsi->nb_qps = qpnum_per_tc * total_tc;
5225 * Configure TC and queue mapping parameters, for enabled TC,
5226 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5227 * default queue will serve it.
5230 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5231 if (vsi->enabled_tc & (1 << i)) {
5232 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5233 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5234 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5235 qp_idx += qpnum_per_tc;
5237 info->tc_mapping[i] = 0;
5240 /* Associate queue number with VSI */
5241 if (vsi->type == I40E_VSI_SRIOV) {
5242 info->mapping_flags |=
5243 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5244 for (i = 0; i < vsi->nb_qps; i++)
5245 info->queue_mapping[i] =
5246 rte_cpu_to_le_16(vsi->base_queue + i);
5248 info->mapping_flags |=
5249 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5250 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5252 info->valid_sections |=
5253 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5255 return I40E_SUCCESS;
5259 i40e_veb_release(struct i40e_veb *veb)
5261 struct i40e_vsi *vsi;
5267 if (!TAILQ_EMPTY(&veb->head)) {
5268 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5271 /* associate_vsi field is NULL for floating VEB */
5272 if (veb->associate_vsi != NULL) {
5273 vsi = veb->associate_vsi;
5274 hw = I40E_VSI_TO_HW(vsi);
5276 vsi->uplink_seid = veb->uplink_seid;
5279 veb->associate_pf->main_vsi->floating_veb = NULL;
5280 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5283 i40e_aq_delete_element(hw, veb->seid, NULL);
5285 return I40E_SUCCESS;
5289 static struct i40e_veb *
5290 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5292 struct i40e_veb *veb;
5298 "veb setup failed, associated PF shouldn't null");
5301 hw = I40E_PF_TO_HW(pf);
5303 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5305 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5309 veb->associate_vsi = vsi;
5310 veb->associate_pf = pf;
5311 TAILQ_INIT(&veb->head);
5312 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5314 /* create floating veb if vsi is NULL */
5316 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5317 I40E_DEFAULT_TCMAP, false,
5318 &veb->seid, false, NULL);
5320 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5321 true, &veb->seid, false, NULL);
5324 if (ret != I40E_SUCCESS) {
5325 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5326 hw->aq.asq_last_status);
5329 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5331 /* get statistics index */
5332 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5333 &veb->stats_idx, NULL, NULL, NULL);
5334 if (ret != I40E_SUCCESS) {
5335 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5336 hw->aq.asq_last_status);
5339 /* Get VEB bandwidth, to be implemented */
5340 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5342 vsi->uplink_seid = veb->seid;
5351 i40e_vsi_release(struct i40e_vsi *vsi)
5355 struct i40e_vsi_list *vsi_list;
5358 struct i40e_mac_filter *f;
5359 uint16_t user_param;
5362 return I40E_SUCCESS;
5367 user_param = vsi->user_param;
5369 pf = I40E_VSI_TO_PF(vsi);
5370 hw = I40E_VSI_TO_HW(vsi);
5372 /* VSI has child to attach, release child first */
5374 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5375 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5378 i40e_veb_release(vsi->veb);
5381 if (vsi->floating_veb) {
5382 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5383 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5388 /* Remove all macvlan filters of the VSI */
5389 i40e_vsi_remove_all_macvlan_filter(vsi);
5390 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5393 if (vsi->type != I40E_VSI_MAIN &&
5394 ((vsi->type != I40E_VSI_SRIOV) ||
5395 !pf->floating_veb_list[user_param])) {
5396 /* Remove vsi from parent's sibling list */
5397 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5398 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5399 return I40E_ERR_PARAM;
5401 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5402 &vsi->sib_vsi_list, list);
5404 /* Remove all switch element of the VSI */
5405 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5406 if (ret != I40E_SUCCESS)
5407 PMD_DRV_LOG(ERR, "Failed to delete element");
5410 if ((vsi->type == I40E_VSI_SRIOV) &&
5411 pf->floating_veb_list[user_param]) {
5412 /* Remove vsi from parent's sibling list */
5413 if (vsi->parent_vsi == NULL ||
5414 vsi->parent_vsi->floating_veb == NULL) {
5415 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5416 return I40E_ERR_PARAM;
5418 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5419 &vsi->sib_vsi_list, list);
5421 /* Remove all switch element of the VSI */
5422 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5423 if (ret != I40E_SUCCESS)
5424 PMD_DRV_LOG(ERR, "Failed to delete element");
5427 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5429 if (vsi->type != I40E_VSI_SRIOV)
5430 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5433 return I40E_SUCCESS;
5437 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5439 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5440 struct i40e_aqc_remove_macvlan_element_data def_filter;
5441 struct i40e_mac_filter_info filter;
5444 if (vsi->type != I40E_VSI_MAIN)
5445 return I40E_ERR_CONFIG;
5446 memset(&def_filter, 0, sizeof(def_filter));
5447 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5449 def_filter.vlan_tag = 0;
5450 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5451 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5452 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5453 if (ret != I40E_SUCCESS) {
5454 struct i40e_mac_filter *f;
5455 struct rte_ether_addr *mac;
5458 "Cannot remove the default macvlan filter");
5459 /* It needs to add the permanent mac into mac list */
5460 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5462 PMD_DRV_LOG(ERR, "failed to allocate memory");
5463 return I40E_ERR_NO_MEMORY;
5465 mac = &f->mac_info.mac_addr;
5466 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5468 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5469 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5474 rte_memcpy(&filter.mac_addr,
5475 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5476 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5477 return i40e_vsi_add_mac(vsi, &filter);
5481 * i40e_vsi_get_bw_config - Query VSI BW Information
5482 * @vsi: the VSI to be queried
5484 * Returns 0 on success, negative value on failure
5486 static enum i40e_status_code
5487 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5489 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5490 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5491 struct i40e_hw *hw = &vsi->adapter->hw;
5496 memset(&bw_config, 0, sizeof(bw_config));
5497 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5498 if (ret != I40E_SUCCESS) {
5499 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5500 hw->aq.asq_last_status);
5504 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5505 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5506 &ets_sla_config, NULL);
5507 if (ret != I40E_SUCCESS) {
5509 "VSI failed to get TC bandwdith configuration %u",
5510 hw->aq.asq_last_status);
5514 /* store and print out BW info */
5515 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5516 vsi->bw_info.bw_max = bw_config.max_bw;
5517 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5518 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5519 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5520 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5522 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5523 vsi->bw_info.bw_ets_share_credits[i] =
5524 ets_sla_config.share_credits[i];
5525 vsi->bw_info.bw_ets_credits[i] =
5526 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5527 /* 4 bits per TC, 4th bit is reserved */
5528 vsi->bw_info.bw_ets_max[i] =
5529 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5530 RTE_LEN2MASK(3, uint8_t));
5531 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5532 vsi->bw_info.bw_ets_share_credits[i]);
5533 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5534 vsi->bw_info.bw_ets_credits[i]);
5535 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5536 vsi->bw_info.bw_ets_max[i]);
5539 return I40E_SUCCESS;
5542 /* i40e_enable_pf_lb
5543 * @pf: pointer to the pf structure
5545 * allow loopback on pf
5548 i40e_enable_pf_lb(struct i40e_pf *pf)
5550 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5551 struct i40e_vsi_context ctxt;
5554 /* Use the FW API if FW >= v5.0 */
5555 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5556 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5560 memset(&ctxt, 0, sizeof(ctxt));
5561 ctxt.seid = pf->main_vsi_seid;
5562 ctxt.pf_num = hw->pf_id;
5563 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5565 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5566 ret, hw->aq.asq_last_status);
5569 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5570 ctxt.info.valid_sections =
5571 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5572 ctxt.info.switch_id |=
5573 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5575 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5577 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5578 hw->aq.asq_last_status);
5583 i40e_vsi_setup(struct i40e_pf *pf,
5584 enum i40e_vsi_type type,
5585 struct i40e_vsi *uplink_vsi,
5586 uint16_t user_param)
5588 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5589 struct i40e_vsi *vsi;
5590 struct i40e_mac_filter_info filter;
5592 struct i40e_vsi_context ctxt;
5593 struct rte_ether_addr broadcast =
5594 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5596 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5597 uplink_vsi == NULL) {
5599 "VSI setup failed, VSI link shouldn't be NULL");
5603 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5605 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5610 * 1.type is not MAIN and uplink vsi is not NULL
5611 * If uplink vsi didn't setup VEB, create one first under veb field
5612 * 2.type is SRIOV and the uplink is NULL
5613 * If floating VEB is NULL, create one veb under floating veb field
5616 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5617 uplink_vsi->veb == NULL) {
5618 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5620 if (uplink_vsi->veb == NULL) {
5621 PMD_DRV_LOG(ERR, "VEB setup failed");
5624 /* set ALLOWLOOPBACk on pf, when veb is created */
5625 i40e_enable_pf_lb(pf);
5628 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5629 pf->main_vsi->floating_veb == NULL) {
5630 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5632 if (pf->main_vsi->floating_veb == NULL) {
5633 PMD_DRV_LOG(ERR, "VEB setup failed");
5638 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5640 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5643 TAILQ_INIT(&vsi->mac_list);
5645 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5646 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5647 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5648 vsi->user_param = user_param;
5649 vsi->vlan_anti_spoof_on = 0;
5650 vsi->vlan_filter_on = 0;
5651 /* Allocate queues */
5652 switch (vsi->type) {
5653 case I40E_VSI_MAIN :
5654 vsi->nb_qps = pf->lan_nb_qps;
5656 case I40E_VSI_SRIOV :
5657 vsi->nb_qps = pf->vf_nb_qps;
5659 case I40E_VSI_VMDQ2:
5660 vsi->nb_qps = pf->vmdq_nb_qps;
5663 vsi->nb_qps = pf->fdir_nb_qps;
5669 * The filter status descriptor is reported in rx queue 0,
5670 * while the tx queue for fdir filter programming has no
5671 * such constraints, can be non-zero queues.
5672 * To simplify it, choose FDIR vsi use queue 0 pair.
5673 * To make sure it will use queue 0 pair, queue allocation
5674 * need be done before this function is called
5676 if (type != I40E_VSI_FDIR) {
5677 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5679 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5683 vsi->base_queue = ret;
5685 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5687 /* VF has MSIX interrupt in VF range, don't allocate here */
5688 if (type == I40E_VSI_MAIN) {
5689 if (pf->support_multi_driver) {
5690 /* If support multi-driver, need to use INT0 instead of
5691 * allocating from msix pool. The Msix pool is init from
5692 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5693 * to 1 without calling i40e_res_pool_alloc.
5698 ret = i40e_res_pool_alloc(&pf->msix_pool,
5699 RTE_MIN(vsi->nb_qps,
5700 RTE_MAX_RXTX_INTR_VEC_ID));
5703 "VSI MAIN %d get heap failed %d",
5705 goto fail_queue_alloc;
5707 vsi->msix_intr = ret;
5708 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5709 RTE_MAX_RXTX_INTR_VEC_ID);
5711 } else if (type != I40E_VSI_SRIOV) {
5712 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5714 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5715 goto fail_queue_alloc;
5717 vsi->msix_intr = ret;
5725 if (type == I40E_VSI_MAIN) {
5726 /* For main VSI, no need to add since it's default one */
5727 vsi->uplink_seid = pf->mac_seid;
5728 vsi->seid = pf->main_vsi_seid;
5729 /* Bind queues with specific MSIX interrupt */
5731 * Needs 2 interrupt at least, one for misc cause which will
5732 * enabled from OS side, Another for queues binding the
5733 * interrupt from device side only.
5736 /* Get default VSI parameters from hardware */
5737 memset(&ctxt, 0, sizeof(ctxt));
5738 ctxt.seid = vsi->seid;
5739 ctxt.pf_num = hw->pf_id;
5740 ctxt.uplink_seid = vsi->uplink_seid;
5742 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5743 if (ret != I40E_SUCCESS) {
5744 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5745 goto fail_msix_alloc;
5747 rte_memcpy(&vsi->info, &ctxt.info,
5748 sizeof(struct i40e_aqc_vsi_properties_data));
5749 vsi->vsi_id = ctxt.vsi_number;
5750 vsi->info.valid_sections = 0;
5752 /* Configure tc, enabled TC0 only */
5753 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5755 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5756 goto fail_msix_alloc;
5759 /* TC, queue mapping */
5760 memset(&ctxt, 0, sizeof(ctxt));
5761 vsi->info.valid_sections |=
5762 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5763 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5764 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5765 rte_memcpy(&ctxt.info, &vsi->info,
5766 sizeof(struct i40e_aqc_vsi_properties_data));
5767 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5768 I40E_DEFAULT_TCMAP);
5769 if (ret != I40E_SUCCESS) {
5771 "Failed to configure TC queue mapping");
5772 goto fail_msix_alloc;
5774 ctxt.seid = vsi->seid;
5775 ctxt.pf_num = hw->pf_id;
5776 ctxt.uplink_seid = vsi->uplink_seid;
5779 /* Update VSI parameters */
5780 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5781 if (ret != I40E_SUCCESS) {
5782 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5783 goto fail_msix_alloc;
5786 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5787 sizeof(vsi->info.tc_mapping));
5788 rte_memcpy(&vsi->info.queue_mapping,
5789 &ctxt.info.queue_mapping,
5790 sizeof(vsi->info.queue_mapping));
5791 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5792 vsi->info.valid_sections = 0;
5794 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5798 * Updating default filter settings are necessary to prevent
5799 * reception of tagged packets.
5800 * Some old firmware configurations load a default macvlan
5801 * filter which accepts both tagged and untagged packets.
5802 * The updating is to use a normal filter instead if needed.
5803 * For NVM 4.2.2 or after, the updating is not needed anymore.
5804 * The firmware with correct configurations load the default
5805 * macvlan filter which is expected and cannot be removed.
5807 i40e_update_default_filter_setting(vsi);
5808 i40e_config_qinq(hw, vsi);
5809 } else if (type == I40E_VSI_SRIOV) {
5810 memset(&ctxt, 0, sizeof(ctxt));
5812 * For other VSI, the uplink_seid equals to uplink VSI's
5813 * uplink_seid since they share same VEB
5815 if (uplink_vsi == NULL)
5816 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5818 vsi->uplink_seid = uplink_vsi->uplink_seid;
5819 ctxt.pf_num = hw->pf_id;
5820 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5821 ctxt.uplink_seid = vsi->uplink_seid;
5822 ctxt.connection_type = 0x1;
5823 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5825 /* Use the VEB configuration if FW >= v5.0 */
5826 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5827 /* Configure switch ID */
5828 ctxt.info.valid_sections |=
5829 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5830 ctxt.info.switch_id =
5831 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5834 /* Configure port/vlan */
5835 ctxt.info.valid_sections |=
5836 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5837 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5838 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5839 hw->func_caps.enabled_tcmap);
5840 if (ret != I40E_SUCCESS) {
5842 "Failed to configure TC queue mapping");
5843 goto fail_msix_alloc;
5846 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5847 ctxt.info.valid_sections |=
5848 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5850 * Since VSI is not created yet, only configure parameter,
5851 * will add vsi below.
5854 i40e_config_qinq(hw, vsi);
5855 } else if (type == I40E_VSI_VMDQ2) {
5856 memset(&ctxt, 0, sizeof(ctxt));
5858 * For other VSI, the uplink_seid equals to uplink VSI's
5859 * uplink_seid since they share same VEB
5861 vsi->uplink_seid = uplink_vsi->uplink_seid;
5862 ctxt.pf_num = hw->pf_id;
5864 ctxt.uplink_seid = vsi->uplink_seid;
5865 ctxt.connection_type = 0x1;
5866 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5868 ctxt.info.valid_sections |=
5869 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5870 /* user_param carries flag to enable loop back */
5872 ctxt.info.switch_id =
5873 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5874 ctxt.info.switch_id |=
5875 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5878 /* Configure port/vlan */
5879 ctxt.info.valid_sections |=
5880 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5881 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5882 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5883 I40E_DEFAULT_TCMAP);
5884 if (ret != I40E_SUCCESS) {
5886 "Failed to configure TC queue mapping");
5887 goto fail_msix_alloc;
5889 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5890 ctxt.info.valid_sections |=
5891 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5892 } else if (type == I40E_VSI_FDIR) {
5893 memset(&ctxt, 0, sizeof(ctxt));
5894 vsi->uplink_seid = uplink_vsi->uplink_seid;
5895 ctxt.pf_num = hw->pf_id;
5897 ctxt.uplink_seid = vsi->uplink_seid;
5898 ctxt.connection_type = 0x1; /* regular data port */
5899 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5900 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5901 I40E_DEFAULT_TCMAP);
5902 if (ret != I40E_SUCCESS) {
5904 "Failed to configure TC queue mapping.");
5905 goto fail_msix_alloc;
5907 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5908 ctxt.info.valid_sections |=
5909 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5911 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5912 goto fail_msix_alloc;
5915 if (vsi->type != I40E_VSI_MAIN) {
5916 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5917 if (ret != I40E_SUCCESS) {
5918 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5919 hw->aq.asq_last_status);
5920 goto fail_msix_alloc;
5922 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5923 vsi->info.valid_sections = 0;
5924 vsi->seid = ctxt.seid;
5925 vsi->vsi_id = ctxt.vsi_number;
5926 vsi->sib_vsi_list.vsi = vsi;
5927 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5928 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5929 &vsi->sib_vsi_list, list);
5931 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5932 &vsi->sib_vsi_list, list);
5936 /* MAC/VLAN configuration */
5937 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5938 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5940 ret = i40e_vsi_add_mac(vsi, &filter);
5941 if (ret != I40E_SUCCESS) {
5942 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5943 goto fail_msix_alloc;
5946 /* Get VSI BW information */
5947 i40e_vsi_get_bw_config(vsi);
5950 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5952 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5958 /* Configure vlan filter on or off */
5960 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5963 struct i40e_mac_filter *f;
5965 struct i40e_mac_filter_info *mac_filter;
5966 enum rte_mac_filter_type desired_filter;
5967 int ret = I40E_SUCCESS;
5970 /* Filter to match MAC and VLAN */
5971 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5973 /* Filter to match only MAC */
5974 desired_filter = RTE_MAC_PERFECT_MATCH;
5979 mac_filter = rte_zmalloc("mac_filter_info_data",
5980 num * sizeof(*mac_filter), 0);
5981 if (mac_filter == NULL) {
5982 PMD_DRV_LOG(ERR, "failed to allocate memory");
5983 return I40E_ERR_NO_MEMORY;
5988 /* Remove all existing mac */
5989 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5990 mac_filter[i] = f->mac_info;
5991 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5993 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5994 on ? "enable" : "disable");
6000 /* Override with new filter */
6001 for (i = 0; i < num; i++) {
6002 mac_filter[i].filter_type = desired_filter;
6003 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6005 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6006 on ? "enable" : "disable");
6012 rte_free(mac_filter);
6016 /* Configure vlan stripping on or off */
6018 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6020 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6021 struct i40e_vsi_context ctxt;
6023 int ret = I40E_SUCCESS;
6025 /* Check if it has been already on or off */
6026 if (vsi->info.valid_sections &
6027 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6029 if ((vsi->info.port_vlan_flags &
6030 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6031 return 0; /* already on */
6033 if ((vsi->info.port_vlan_flags &
6034 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6035 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6036 return 0; /* already off */
6041 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6043 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6044 vsi->info.valid_sections =
6045 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6046 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6047 vsi->info.port_vlan_flags |= vlan_flags;
6048 ctxt.seid = vsi->seid;
6049 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6050 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6052 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6053 on ? "enable" : "disable");
6059 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6061 struct rte_eth_dev_data *data = dev->data;
6065 /* Apply vlan offload setting */
6066 mask = ETH_VLAN_STRIP_MASK |
6067 ETH_VLAN_FILTER_MASK |
6068 ETH_VLAN_EXTEND_MASK;
6069 ret = i40e_vlan_offload_set(dev, mask);
6071 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6075 /* Apply pvid setting */
6076 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6077 data->dev_conf.txmode.hw_vlan_insert_pvid);
6079 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6085 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6087 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6089 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6093 i40e_update_flow_control(struct i40e_hw *hw)
6095 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6096 struct i40e_link_status link_status;
6097 uint32_t rxfc = 0, txfc = 0, reg;
6101 memset(&link_status, 0, sizeof(link_status));
6102 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6103 if (ret != I40E_SUCCESS) {
6104 PMD_DRV_LOG(ERR, "Failed to get link status information");
6105 goto write_reg; /* Disable flow control */
6108 an_info = hw->phy.link_info.an_info;
6109 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6110 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6111 ret = I40E_ERR_NOT_READY;
6112 goto write_reg; /* Disable flow control */
6115 * If link auto negotiation is enabled, flow control needs to
6116 * be configured according to it
6118 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6119 case I40E_LINK_PAUSE_RXTX:
6122 hw->fc.current_mode = I40E_FC_FULL;
6124 case I40E_AQ_LINK_PAUSE_RX:
6126 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6128 case I40E_AQ_LINK_PAUSE_TX:
6130 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6133 hw->fc.current_mode = I40E_FC_NONE;
6138 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6139 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6140 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6141 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6142 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6143 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6150 i40e_pf_setup(struct i40e_pf *pf)
6152 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6153 struct i40e_filter_control_settings settings;
6154 struct i40e_vsi *vsi;
6157 /* Clear all stats counters */
6158 pf->offset_loaded = FALSE;
6159 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6160 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6161 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6162 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6164 ret = i40e_pf_get_switch_config(pf);
6165 if (ret != I40E_SUCCESS) {
6166 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6170 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6172 PMD_INIT_LOG(WARNING,
6173 "failed to allocate switch domain for device %d", ret);
6175 if (pf->flags & I40E_FLAG_FDIR) {
6176 /* make queue allocated first, let FDIR use queue pair 0*/
6177 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6178 if (ret != I40E_FDIR_QUEUE_ID) {
6180 "queue allocation fails for FDIR: ret =%d",
6182 pf->flags &= ~I40E_FLAG_FDIR;
6185 /* main VSI setup */
6186 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6188 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6189 return I40E_ERR_NOT_READY;
6193 /* Configure filter control */
6194 memset(&settings, 0, sizeof(settings));
6195 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6196 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6197 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6198 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6200 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6201 hw->func_caps.rss_table_size);
6202 return I40E_ERR_PARAM;
6204 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6205 hw->func_caps.rss_table_size);
6206 pf->hash_lut_size = hw->func_caps.rss_table_size;
6208 /* Enable ethtype and macvlan filters */
6209 settings.enable_ethtype = TRUE;
6210 settings.enable_macvlan = TRUE;
6211 ret = i40e_set_filter_control(hw, &settings);
6213 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6216 /* Update flow control according to the auto negotiation */
6217 i40e_update_flow_control(hw);
6219 return I40E_SUCCESS;
6223 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6229 * Set or clear TX Queue Disable flags,
6230 * which is required by hardware.
6232 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6233 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6235 /* Wait until the request is finished */
6236 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6237 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6238 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6239 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6240 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6246 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6247 return I40E_SUCCESS; /* already on, skip next steps */
6249 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6250 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6252 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6253 return I40E_SUCCESS; /* already off, skip next steps */
6254 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6256 /* Write the register */
6257 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6258 /* Check the result */
6259 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6260 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6261 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6263 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6264 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6267 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6268 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6272 /* Check if it is timeout */
6273 if (j >= I40E_CHK_Q_ENA_COUNT) {
6274 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6275 (on ? "enable" : "disable"), q_idx);
6276 return I40E_ERR_TIMEOUT;
6279 return I40E_SUCCESS;
6282 /* Swith on or off the tx queues */
6284 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6286 struct rte_eth_dev_data *dev_data = pf->dev_data;
6287 struct i40e_tx_queue *txq;
6288 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6292 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6293 txq = dev_data->tx_queues[i];
6294 /* Don't operate the queue if not configured or
6295 * if starting only per queue */
6296 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6299 ret = i40e_dev_tx_queue_start(dev, i);
6301 ret = i40e_dev_tx_queue_stop(dev, i);
6302 if ( ret != I40E_SUCCESS)
6306 return I40E_SUCCESS;
6310 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6315 /* Wait until the request is finished */
6316 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6317 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6318 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6319 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6320 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6325 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6326 return I40E_SUCCESS; /* Already on, skip next steps */
6327 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6329 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6330 return I40E_SUCCESS; /* Already off, skip next steps */
6331 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6334 /* Write the register */
6335 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6336 /* Check the result */
6337 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6338 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6339 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6341 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6342 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6345 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6346 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6351 /* Check if it is timeout */
6352 if (j >= I40E_CHK_Q_ENA_COUNT) {
6353 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6354 (on ? "enable" : "disable"), q_idx);
6355 return I40E_ERR_TIMEOUT;
6358 return I40E_SUCCESS;
6360 /* Switch on or off the rx queues */
6362 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6364 struct rte_eth_dev_data *dev_data = pf->dev_data;
6365 struct i40e_rx_queue *rxq;
6366 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6370 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6371 rxq = dev_data->rx_queues[i];
6372 /* Don't operate the queue if not configured or
6373 * if starting only per queue */
6374 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6377 ret = i40e_dev_rx_queue_start(dev, i);
6379 ret = i40e_dev_rx_queue_stop(dev, i);
6380 if (ret != I40E_SUCCESS)
6384 return I40E_SUCCESS;
6387 /* Switch on or off all the rx/tx queues */
6389 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6394 /* enable rx queues before enabling tx queues */
6395 ret = i40e_dev_switch_rx_queues(pf, on);
6397 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6400 ret = i40e_dev_switch_tx_queues(pf, on);
6402 /* Stop tx queues before stopping rx queues */
6403 ret = i40e_dev_switch_tx_queues(pf, on);
6405 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6408 ret = i40e_dev_switch_rx_queues(pf, on);
6414 /* Initialize VSI for TX */
6416 i40e_dev_tx_init(struct i40e_pf *pf)
6418 struct rte_eth_dev_data *data = pf->dev_data;
6420 uint32_t ret = I40E_SUCCESS;
6421 struct i40e_tx_queue *txq;
6423 for (i = 0; i < data->nb_tx_queues; i++) {
6424 txq = data->tx_queues[i];
6425 if (!txq || !txq->q_set)
6427 ret = i40e_tx_queue_init(txq);
6428 if (ret != I40E_SUCCESS)
6431 if (ret == I40E_SUCCESS)
6432 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6438 /* Initialize VSI for RX */
6440 i40e_dev_rx_init(struct i40e_pf *pf)
6442 struct rte_eth_dev_data *data = pf->dev_data;
6443 int ret = I40E_SUCCESS;
6445 struct i40e_rx_queue *rxq;
6447 i40e_pf_config_mq_rx(pf);
6448 for (i = 0; i < data->nb_rx_queues; i++) {
6449 rxq = data->rx_queues[i];
6450 if (!rxq || !rxq->q_set)
6453 ret = i40e_rx_queue_init(rxq);
6454 if (ret != I40E_SUCCESS) {
6456 "Failed to do RX queue initialization");
6460 if (ret == I40E_SUCCESS)
6461 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6468 i40e_dev_rxtx_init(struct i40e_pf *pf)
6472 err = i40e_dev_tx_init(pf);
6474 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6477 err = i40e_dev_rx_init(pf);
6479 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6487 i40e_vmdq_setup(struct rte_eth_dev *dev)
6489 struct rte_eth_conf *conf = &dev->data->dev_conf;
6490 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6491 int i, err, conf_vsis, j, loop;
6492 struct i40e_vsi *vsi;
6493 struct i40e_vmdq_info *vmdq_info;
6494 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6495 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6498 * Disable interrupt to avoid message from VF. Furthermore, it will
6499 * avoid race condition in VSI creation/destroy.
6501 i40e_pf_disable_irq0(hw);
6503 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6504 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6508 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6509 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6510 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6511 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6512 pf->max_nb_vmdq_vsi);
6516 if (pf->vmdq != NULL) {
6517 PMD_INIT_LOG(INFO, "VMDQ already configured");
6521 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6522 sizeof(*vmdq_info) * conf_vsis, 0);
6524 if (pf->vmdq == NULL) {
6525 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6529 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6531 /* Create VMDQ VSI */
6532 for (i = 0; i < conf_vsis; i++) {
6533 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6534 vmdq_conf->enable_loop_back);
6536 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6540 vmdq_info = &pf->vmdq[i];
6542 vmdq_info->vsi = vsi;
6544 pf->nb_cfg_vmdq_vsi = conf_vsis;
6546 /* Configure Vlan */
6547 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6548 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6549 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6550 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6551 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6552 vmdq_conf->pool_map[i].vlan_id, j);
6554 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6555 vmdq_conf->pool_map[i].vlan_id);
6557 PMD_INIT_LOG(ERR, "Failed to add vlan");
6565 i40e_pf_enable_irq0(hw);
6570 for (i = 0; i < conf_vsis; i++)
6571 if (pf->vmdq[i].vsi == NULL)
6574 i40e_vsi_release(pf->vmdq[i].vsi);
6578 i40e_pf_enable_irq0(hw);
6583 i40e_stat_update_32(struct i40e_hw *hw,
6591 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6595 if (new_data >= *offset)
6596 *stat = (uint64_t)(new_data - *offset);
6598 *stat = (uint64_t)((new_data +
6599 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6603 i40e_stat_update_48(struct i40e_hw *hw,
6612 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6613 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6614 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6619 if (new_data >= *offset)
6620 *stat = new_data - *offset;
6622 *stat = (uint64_t)((new_data +
6623 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6625 *stat &= I40E_48_BIT_MASK;
6630 i40e_pf_disable_irq0(struct i40e_hw *hw)
6632 /* Disable all interrupt types */
6633 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6634 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6635 I40E_WRITE_FLUSH(hw);
6640 i40e_pf_enable_irq0(struct i40e_hw *hw)
6642 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6643 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6644 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6645 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6646 I40E_WRITE_FLUSH(hw);
6650 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6652 /* read pending request and disable first */
6653 i40e_pf_disable_irq0(hw);
6654 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6655 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6656 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6659 /* Link no queues with irq0 */
6660 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6661 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6665 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6667 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6668 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6671 uint32_t index, offset, val;
6676 * Try to find which VF trigger a reset, use absolute VF id to access
6677 * since the reg is global register.
6679 for (i = 0; i < pf->vf_num; i++) {
6680 abs_vf_id = hw->func_caps.vf_base_id + i;
6681 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6682 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6683 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6684 /* VFR event occurred */
6685 if (val & (0x1 << offset)) {
6688 /* Clear the event first */
6689 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6691 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6693 * Only notify a VF reset event occurred,
6694 * don't trigger another SW reset
6696 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6697 if (ret != I40E_SUCCESS)
6698 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6704 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6706 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6709 for (i = 0; i < pf->vf_num; i++)
6710 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6714 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6716 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6717 struct i40e_arq_event_info info;
6718 uint16_t pending, opcode;
6721 info.buf_len = I40E_AQ_BUF_SZ;
6722 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6723 if (!info.msg_buf) {
6724 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6730 ret = i40e_clean_arq_element(hw, &info, &pending);
6732 if (ret != I40E_SUCCESS) {
6734 "Failed to read msg from AdminQ, aq_err: %u",
6735 hw->aq.asq_last_status);
6738 opcode = rte_le_to_cpu_16(info.desc.opcode);
6741 case i40e_aqc_opc_send_msg_to_pf:
6742 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6743 i40e_pf_host_handle_vf_msg(dev,
6744 rte_le_to_cpu_16(info.desc.retval),
6745 rte_le_to_cpu_32(info.desc.cookie_high),
6746 rte_le_to_cpu_32(info.desc.cookie_low),
6750 case i40e_aqc_opc_get_link_status:
6751 ret = i40e_dev_link_update(dev, 0);
6753 _rte_eth_dev_callback_process(dev,
6754 RTE_ETH_EVENT_INTR_LSC, NULL);
6757 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6762 rte_free(info.msg_buf);
6766 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6768 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6769 #define I40E_MDD_CLEAR16 0xFFFF
6770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6772 bool mdd_detected = false;
6773 struct i40e_pf_vf *vf;
6777 /* find what triggered the MDD event */
6778 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6779 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6780 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6781 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6782 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6783 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6784 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6785 I40E_GL_MDET_TX_EVENT_SHIFT;
6786 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6787 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6788 hw->func_caps.base_queue;
6789 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6790 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6791 event, queue, pf_num, vf_num, dev->data->name);
6792 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6793 mdd_detected = true;
6795 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6796 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6797 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6798 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6799 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6800 I40E_GL_MDET_RX_EVENT_SHIFT;
6801 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6802 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6803 hw->func_caps.base_queue;
6805 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6806 "queue %d of function 0x%02x device %s\n",
6807 event, queue, func, dev->data->name);
6808 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6809 mdd_detected = true;
6813 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6814 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6815 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6816 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6818 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6819 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6820 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6822 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6826 /* see if one of the VFs needs its hand slapped */
6827 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6829 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6830 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6831 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6833 vf->num_mdd_events++;
6834 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6836 i, vf->num_mdd_events);
6839 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6840 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6841 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6843 vf->num_mdd_events++;
6844 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6846 i, vf->num_mdd_events);
6852 * Interrupt handler triggered by NIC for handling
6853 * specific interrupt.
6856 * Pointer to interrupt handle.
6858 * The address of parameter (struct rte_eth_dev *) regsitered before.
6864 i40e_dev_interrupt_handler(void *param)
6866 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6867 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6870 /* Disable interrupt */
6871 i40e_pf_disable_irq0(hw);
6873 /* read out interrupt causes */
6874 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6876 /* No interrupt event indicated */
6877 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6878 PMD_DRV_LOG(INFO, "No interrupt event");
6881 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6882 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6883 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6884 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6885 i40e_handle_mdd_event(dev);
6887 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6888 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6889 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6890 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6891 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6892 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6893 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6894 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6895 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6896 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6898 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6899 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6900 i40e_dev_handle_vfr_event(dev);
6902 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6903 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6904 i40e_dev_handle_aq_msg(dev);
6908 /* Enable interrupt */
6909 i40e_pf_enable_irq0(hw);
6913 i40e_dev_alarm_handler(void *param)
6915 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919 /* Disable interrupt */
6920 i40e_pf_disable_irq0(hw);
6922 /* read out interrupt causes */
6923 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6925 /* No interrupt event indicated */
6926 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6928 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6929 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6930 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6931 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6932 i40e_handle_mdd_event(dev);
6934 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6935 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6936 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6937 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6938 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6939 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6940 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6941 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6942 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6943 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6945 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6946 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6947 i40e_dev_handle_vfr_event(dev);
6949 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6950 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6951 i40e_dev_handle_aq_msg(dev);
6955 /* Enable interrupt */
6956 i40e_pf_enable_irq0(hw);
6957 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6958 i40e_dev_alarm_handler, dev);
6962 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6963 struct i40e_macvlan_filter *filter,
6966 int ele_num, ele_buff_size;
6967 int num, actual_num, i;
6969 int ret = I40E_SUCCESS;
6970 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6971 struct i40e_aqc_add_macvlan_element_data *req_list;
6973 if (filter == NULL || total == 0)
6974 return I40E_ERR_PARAM;
6975 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6976 ele_buff_size = hw->aq.asq_buf_size;
6978 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6979 if (req_list == NULL) {
6980 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6981 return I40E_ERR_NO_MEMORY;
6986 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6987 memset(req_list, 0, ele_buff_size);
6989 for (i = 0; i < actual_num; i++) {
6990 rte_memcpy(req_list[i].mac_addr,
6991 &filter[num + i].macaddr, ETH_ADDR_LEN);
6992 req_list[i].vlan_tag =
6993 rte_cpu_to_le_16(filter[num + i].vlan_id);
6995 switch (filter[num + i].filter_type) {
6996 case RTE_MAC_PERFECT_MATCH:
6997 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6998 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7000 case RTE_MACVLAN_PERFECT_MATCH:
7001 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7003 case RTE_MAC_HASH_MATCH:
7004 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7005 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7007 case RTE_MACVLAN_HASH_MATCH:
7008 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7011 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7012 ret = I40E_ERR_PARAM;
7016 req_list[i].queue_number = 0;
7018 req_list[i].flags = rte_cpu_to_le_16(flags);
7021 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7023 if (ret != I40E_SUCCESS) {
7024 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7028 } while (num < total);
7036 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7037 struct i40e_macvlan_filter *filter,
7040 int ele_num, ele_buff_size;
7041 int num, actual_num, i;
7043 int ret = I40E_SUCCESS;
7044 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7045 struct i40e_aqc_remove_macvlan_element_data *req_list;
7047 if (filter == NULL || total == 0)
7048 return I40E_ERR_PARAM;
7050 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7051 ele_buff_size = hw->aq.asq_buf_size;
7053 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7054 if (req_list == NULL) {
7055 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7056 return I40E_ERR_NO_MEMORY;
7061 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7062 memset(req_list, 0, ele_buff_size);
7064 for (i = 0; i < actual_num; i++) {
7065 rte_memcpy(req_list[i].mac_addr,
7066 &filter[num + i].macaddr, ETH_ADDR_LEN);
7067 req_list[i].vlan_tag =
7068 rte_cpu_to_le_16(filter[num + i].vlan_id);
7070 switch (filter[num + i].filter_type) {
7071 case RTE_MAC_PERFECT_MATCH:
7072 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7073 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7075 case RTE_MACVLAN_PERFECT_MATCH:
7076 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7078 case RTE_MAC_HASH_MATCH:
7079 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7080 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7082 case RTE_MACVLAN_HASH_MATCH:
7083 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7086 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7087 ret = I40E_ERR_PARAM;
7090 req_list[i].flags = rte_cpu_to_le_16(flags);
7093 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7095 if (ret != I40E_SUCCESS) {
7096 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7100 } while (num < total);
7107 /* Find out specific MAC filter */
7108 static struct i40e_mac_filter *
7109 i40e_find_mac_filter(struct i40e_vsi *vsi,
7110 struct rte_ether_addr *macaddr)
7112 struct i40e_mac_filter *f;
7114 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7115 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7123 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7126 uint32_t vid_idx, vid_bit;
7128 if (vlan_id > ETH_VLAN_ID_MAX)
7131 vid_idx = I40E_VFTA_IDX(vlan_id);
7132 vid_bit = I40E_VFTA_BIT(vlan_id);
7134 if (vsi->vfta[vid_idx] & vid_bit)
7141 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7142 uint16_t vlan_id, bool on)
7144 uint32_t vid_idx, vid_bit;
7146 vid_idx = I40E_VFTA_IDX(vlan_id);
7147 vid_bit = I40E_VFTA_BIT(vlan_id);
7150 vsi->vfta[vid_idx] |= vid_bit;
7152 vsi->vfta[vid_idx] &= ~vid_bit;
7156 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7157 uint16_t vlan_id, bool on)
7159 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7160 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7163 if (vlan_id > ETH_VLAN_ID_MAX)
7166 i40e_store_vlan_filter(vsi, vlan_id, on);
7168 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7171 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7174 ret = i40e_aq_add_vlan(hw, vsi->seid,
7175 &vlan_data, 1, NULL);
7176 if (ret != I40E_SUCCESS)
7177 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7179 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7180 &vlan_data, 1, NULL);
7181 if (ret != I40E_SUCCESS)
7183 "Failed to remove vlan filter");
7188 * Find all vlan options for specific mac addr,
7189 * return with actual vlan found.
7192 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7193 struct i40e_macvlan_filter *mv_f,
7194 int num, struct rte_ether_addr *addr)
7200 * Not to use i40e_find_vlan_filter to decrease the loop time,
7201 * although the code looks complex.
7203 if (num < vsi->vlan_num)
7204 return I40E_ERR_PARAM;
7207 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7209 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7210 if (vsi->vfta[j] & (1 << k)) {
7213 "vlan number doesn't match");
7214 return I40E_ERR_PARAM;
7216 rte_memcpy(&mv_f[i].macaddr,
7217 addr, ETH_ADDR_LEN);
7219 j * I40E_UINT32_BIT_SIZE + k;
7225 return I40E_SUCCESS;
7229 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7230 struct i40e_macvlan_filter *mv_f,
7235 struct i40e_mac_filter *f;
7237 if (num < vsi->mac_num)
7238 return I40E_ERR_PARAM;
7240 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7242 PMD_DRV_LOG(ERR, "buffer number not match");
7243 return I40E_ERR_PARAM;
7245 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7247 mv_f[i].vlan_id = vlan;
7248 mv_f[i].filter_type = f->mac_info.filter_type;
7252 return I40E_SUCCESS;
7256 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7259 struct i40e_mac_filter *f;
7260 struct i40e_macvlan_filter *mv_f;
7261 int ret = I40E_SUCCESS;
7263 if (vsi == NULL || vsi->mac_num == 0)
7264 return I40E_ERR_PARAM;
7266 /* Case that no vlan is set */
7267 if (vsi->vlan_num == 0)
7270 num = vsi->mac_num * vsi->vlan_num;
7272 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7274 PMD_DRV_LOG(ERR, "failed to allocate memory");
7275 return I40E_ERR_NO_MEMORY;
7279 if (vsi->vlan_num == 0) {
7280 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7281 rte_memcpy(&mv_f[i].macaddr,
7282 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7283 mv_f[i].filter_type = f->mac_info.filter_type;
7284 mv_f[i].vlan_id = 0;
7288 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7289 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7290 vsi->vlan_num, &f->mac_info.mac_addr);
7291 if (ret != I40E_SUCCESS)
7293 for (j = i; j < i + vsi->vlan_num; j++)
7294 mv_f[j].filter_type = f->mac_info.filter_type;
7299 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7307 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7309 struct i40e_macvlan_filter *mv_f;
7311 int ret = I40E_SUCCESS;
7313 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7314 return I40E_ERR_PARAM;
7316 /* If it's already set, just return */
7317 if (i40e_find_vlan_filter(vsi,vlan))
7318 return I40E_SUCCESS;
7320 mac_num = vsi->mac_num;
7323 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7324 return I40E_ERR_PARAM;
7327 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7330 PMD_DRV_LOG(ERR, "failed to allocate memory");
7331 return I40E_ERR_NO_MEMORY;
7334 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7336 if (ret != I40E_SUCCESS)
7339 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7341 if (ret != I40E_SUCCESS)
7344 i40e_set_vlan_filter(vsi, vlan, 1);
7354 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7356 struct i40e_macvlan_filter *mv_f;
7358 int ret = I40E_SUCCESS;
7361 * Vlan 0 is the generic filter for untagged packets
7362 * and can't be removed.
7364 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7365 return I40E_ERR_PARAM;
7367 /* If can't find it, just return */
7368 if (!i40e_find_vlan_filter(vsi, vlan))
7369 return I40E_ERR_PARAM;
7371 mac_num = vsi->mac_num;
7374 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7375 return I40E_ERR_PARAM;
7378 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7381 PMD_DRV_LOG(ERR, "failed to allocate memory");
7382 return I40E_ERR_NO_MEMORY;
7385 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7387 if (ret != I40E_SUCCESS)
7390 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7392 if (ret != I40E_SUCCESS)
7395 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7396 if (vsi->vlan_num == 1) {
7397 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7398 if (ret != I40E_SUCCESS)
7401 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7402 if (ret != I40E_SUCCESS)
7406 i40e_set_vlan_filter(vsi, vlan, 0);
7416 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7418 struct i40e_mac_filter *f;
7419 struct i40e_macvlan_filter *mv_f;
7420 int i, vlan_num = 0;
7421 int ret = I40E_SUCCESS;
7423 /* If it's add and we've config it, return */
7424 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7426 return I40E_SUCCESS;
7427 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7428 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7431 * If vlan_num is 0, that's the first time to add mac,
7432 * set mask for vlan_id 0.
7434 if (vsi->vlan_num == 0) {
7435 i40e_set_vlan_filter(vsi, 0, 1);
7438 vlan_num = vsi->vlan_num;
7439 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7440 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7443 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7445 PMD_DRV_LOG(ERR, "failed to allocate memory");
7446 return I40E_ERR_NO_MEMORY;
7449 for (i = 0; i < vlan_num; i++) {
7450 mv_f[i].filter_type = mac_filter->filter_type;
7451 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7455 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7456 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7457 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7458 &mac_filter->mac_addr);
7459 if (ret != I40E_SUCCESS)
7463 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7464 if (ret != I40E_SUCCESS)
7467 /* Add the mac addr into mac list */
7468 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7470 PMD_DRV_LOG(ERR, "failed to allocate memory");
7471 ret = I40E_ERR_NO_MEMORY;
7474 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7476 f->mac_info.filter_type = mac_filter->filter_type;
7477 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7488 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7490 struct i40e_mac_filter *f;
7491 struct i40e_macvlan_filter *mv_f;
7493 enum rte_mac_filter_type filter_type;
7494 int ret = I40E_SUCCESS;
7496 /* Can't find it, return an error */
7497 f = i40e_find_mac_filter(vsi, addr);
7499 return I40E_ERR_PARAM;
7501 vlan_num = vsi->vlan_num;
7502 filter_type = f->mac_info.filter_type;
7503 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7504 filter_type == RTE_MACVLAN_HASH_MATCH) {
7505 if (vlan_num == 0) {
7506 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7507 return I40E_ERR_PARAM;
7509 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7510 filter_type == RTE_MAC_HASH_MATCH)
7513 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7515 PMD_DRV_LOG(ERR, "failed to allocate memory");
7516 return I40E_ERR_NO_MEMORY;
7519 for (i = 0; i < vlan_num; i++) {
7520 mv_f[i].filter_type = filter_type;
7521 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7524 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7525 filter_type == RTE_MACVLAN_HASH_MATCH) {
7526 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7527 if (ret != I40E_SUCCESS)
7531 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7532 if (ret != I40E_SUCCESS)
7535 /* Remove the mac addr into mac list */
7536 TAILQ_REMOVE(&vsi->mac_list, f, next);
7546 /* Configure hash enable flags for RSS */
7548 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7556 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7557 if (flags & (1ULL << i))
7558 hena |= adapter->pctypes_tbl[i];
7564 /* Parse the hash enable flags */
7566 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7568 uint64_t rss_hf = 0;
7574 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7575 if (flags & adapter->pctypes_tbl[i])
7576 rss_hf |= (1ULL << i);
7583 i40e_pf_disable_rss(struct i40e_pf *pf)
7585 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7587 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7588 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7589 I40E_WRITE_FLUSH(hw);
7593 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7595 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7596 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7597 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7598 I40E_VFQF_HKEY_MAX_INDEX :
7599 I40E_PFQF_HKEY_MAX_INDEX;
7602 if (!key || key_len == 0) {
7603 PMD_DRV_LOG(DEBUG, "No key to be configured");
7605 } else if (key_len != (key_idx + 1) *
7607 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7611 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7612 struct i40e_aqc_get_set_rss_key_data *key_dw =
7613 (struct i40e_aqc_get_set_rss_key_data *)key;
7615 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7617 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7619 uint32_t *hash_key = (uint32_t *)key;
7622 if (vsi->type == I40E_VSI_SRIOV) {
7623 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7626 I40E_VFQF_HKEY1(i, vsi->user_param),
7630 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7631 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7634 I40E_WRITE_FLUSH(hw);
7641 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7643 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7644 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7648 if (!key || !key_len)
7651 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7652 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7653 (struct i40e_aqc_get_set_rss_key_data *)key);
7655 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7659 uint32_t *key_dw = (uint32_t *)key;
7662 if (vsi->type == I40E_VSI_SRIOV) {
7663 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7664 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7665 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7667 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7670 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7671 reg = I40E_PFQF_HKEY(i);
7672 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7674 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7682 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7684 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7688 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7689 rss_conf->rss_key_len);
7693 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7694 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7695 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7696 I40E_WRITE_FLUSH(hw);
7702 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7703 struct rte_eth_rss_conf *rss_conf)
7705 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7707 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7710 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7711 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7713 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7714 if (rss_hf != 0) /* Enable RSS */
7716 return 0; /* Nothing to do */
7719 if (rss_hf == 0) /* Disable RSS */
7722 return i40e_hw_rss_hash_set(pf, rss_conf);
7726 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7727 struct rte_eth_rss_conf *rss_conf)
7729 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7730 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7737 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7738 &rss_conf->rss_key_len);
7742 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7743 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7744 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7750 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7752 switch (filter_type) {
7753 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7754 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7756 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7757 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7759 case RTE_TUNNEL_FILTER_IMAC_TENID:
7760 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7762 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7763 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7765 case ETH_TUNNEL_FILTER_IMAC:
7766 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7768 case ETH_TUNNEL_FILTER_OIP:
7769 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7771 case ETH_TUNNEL_FILTER_IIP:
7772 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7775 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7782 /* Convert tunnel filter structure */
7784 i40e_tunnel_filter_convert(
7785 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7786 struct i40e_tunnel_filter *tunnel_filter)
7788 rte_ether_addr_copy((struct rte_ether_addr *)
7789 &cld_filter->element.outer_mac,
7790 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7791 rte_ether_addr_copy((struct rte_ether_addr *)
7792 &cld_filter->element.inner_mac,
7793 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7794 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7795 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7796 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7797 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7798 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7800 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7801 tunnel_filter->input.flags = cld_filter->element.flags;
7802 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7803 tunnel_filter->queue = cld_filter->element.queue_number;
7804 rte_memcpy(tunnel_filter->input.general_fields,
7805 cld_filter->general_fields,
7806 sizeof(cld_filter->general_fields));
7811 /* Check if there exists the tunnel filter */
7812 struct i40e_tunnel_filter *
7813 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7814 const struct i40e_tunnel_filter_input *input)
7818 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7822 return tunnel_rule->hash_map[ret];
7825 /* Add a tunnel filter into the SW list */
7827 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7828 struct i40e_tunnel_filter *tunnel_filter)
7830 struct i40e_tunnel_rule *rule = &pf->tunnel;
7833 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7836 "Failed to insert tunnel filter to hash table %d!",
7840 rule->hash_map[ret] = tunnel_filter;
7842 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7847 /* Delete a tunnel filter from the SW list */
7849 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7850 struct i40e_tunnel_filter_input *input)
7852 struct i40e_tunnel_rule *rule = &pf->tunnel;
7853 struct i40e_tunnel_filter *tunnel_filter;
7856 ret = rte_hash_del_key(rule->hash_table, input);
7859 "Failed to delete tunnel filter to hash table %d!",
7863 tunnel_filter = rule->hash_map[ret];
7864 rule->hash_map[ret] = NULL;
7866 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7867 rte_free(tunnel_filter);
7873 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7874 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7878 uint32_t ipv4_addr, ipv4_addr_le;
7879 uint8_t i, tun_type = 0;
7880 /* internal varialbe to convert ipv6 byte order */
7881 uint32_t convert_ipv6[4];
7883 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7884 struct i40e_vsi *vsi = pf->main_vsi;
7885 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7886 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7887 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7888 struct i40e_tunnel_filter *tunnel, *node;
7889 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7891 cld_filter = rte_zmalloc("tunnel_filter",
7892 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7895 if (NULL == cld_filter) {
7896 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7899 pfilter = cld_filter;
7901 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7902 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7903 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7904 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7906 pfilter->element.inner_vlan =
7907 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7908 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7909 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7910 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7911 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7912 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7914 sizeof(pfilter->element.ipaddr.v4.data));
7916 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7917 for (i = 0; i < 4; i++) {
7919 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7921 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7923 sizeof(pfilter->element.ipaddr.v6.data));
7926 /* check tunneled type */
7927 switch (tunnel_filter->tunnel_type) {
7928 case RTE_TUNNEL_TYPE_VXLAN:
7929 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7931 case RTE_TUNNEL_TYPE_NVGRE:
7932 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7934 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7935 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7937 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7938 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7941 /* Other tunnel types is not supported. */
7942 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7943 rte_free(cld_filter);
7947 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7948 &pfilter->element.flags);
7950 rte_free(cld_filter);
7954 pfilter->element.flags |= rte_cpu_to_le_16(
7955 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7956 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7957 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7958 pfilter->element.queue_number =
7959 rte_cpu_to_le_16(tunnel_filter->queue_id);
7961 /* Check if there is the filter in SW list */
7962 memset(&check_filter, 0, sizeof(check_filter));
7963 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7964 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7966 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7967 rte_free(cld_filter);
7971 if (!add && !node) {
7972 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7973 rte_free(cld_filter);
7978 ret = i40e_aq_add_cloud_filters(hw,
7979 vsi->seid, &cld_filter->element, 1);
7981 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7982 rte_free(cld_filter);
7985 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7986 if (tunnel == NULL) {
7987 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7988 rte_free(cld_filter);
7992 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7993 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7997 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7998 &cld_filter->element, 1);
8000 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8001 rte_free(cld_filter);
8004 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8007 rte_free(cld_filter);
8011 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8012 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
8013 #define I40E_TR_GENEVE_KEY_MASK 0x8
8014 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
8015 #define I40E_TR_GRE_KEY_MASK 0x400
8016 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
8017 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
8020 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8022 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8023 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8024 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8025 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8026 enum i40e_status_code status = I40E_SUCCESS;
8028 if (pf->support_multi_driver) {
8029 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8030 return I40E_NOT_SUPPORTED;
8033 memset(&filter_replace, 0,
8034 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8035 memset(&filter_replace_buf, 0,
8036 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8038 /* create L1 filter */
8039 filter_replace.old_filter_type =
8040 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8041 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8042 filter_replace.tr_bit = 0;
8044 /* Prepare the buffer, 3 entries */
8045 filter_replace_buf.data[0] =
8046 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8047 filter_replace_buf.data[0] |=
8048 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8049 filter_replace_buf.data[2] = 0xFF;
8050 filter_replace_buf.data[3] = 0xFF;
8051 filter_replace_buf.data[4] =
8052 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8053 filter_replace_buf.data[4] |=
8054 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8055 filter_replace_buf.data[7] = 0xF0;
8056 filter_replace_buf.data[8]
8057 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8058 filter_replace_buf.data[8] |=
8059 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8060 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8061 I40E_TR_GENEVE_KEY_MASK |
8062 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8063 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8064 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8065 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8067 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8068 &filter_replace_buf);
8069 if (!status && (filter_replace.old_filter_type !=
8070 filter_replace.new_filter_type))
8071 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8072 " original: 0x%x, new: 0x%x",
8074 filter_replace.old_filter_type,
8075 filter_replace.new_filter_type);
8081 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8083 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8084 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8085 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8086 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8087 enum i40e_status_code status = I40E_SUCCESS;
8089 if (pf->support_multi_driver) {
8090 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8091 return I40E_NOT_SUPPORTED;
8095 memset(&filter_replace, 0,
8096 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8097 memset(&filter_replace_buf, 0,
8098 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8099 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8100 I40E_AQC_MIRROR_CLOUD_FILTER;
8101 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8102 filter_replace.new_filter_type =
8103 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8104 /* Prepare the buffer, 2 entries */
8105 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8106 filter_replace_buf.data[0] |=
8107 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8108 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8109 filter_replace_buf.data[4] |=
8110 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8111 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8112 &filter_replace_buf);
8115 if (filter_replace.old_filter_type !=
8116 filter_replace.new_filter_type)
8117 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8118 " original: 0x%x, new: 0x%x",
8120 filter_replace.old_filter_type,
8121 filter_replace.new_filter_type);
8124 memset(&filter_replace, 0,
8125 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8126 memset(&filter_replace_buf, 0,
8127 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8129 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8130 I40E_AQC_MIRROR_CLOUD_FILTER;
8131 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8132 filter_replace.new_filter_type =
8133 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8134 /* Prepare the buffer, 2 entries */
8135 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8136 filter_replace_buf.data[0] |=
8137 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8138 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8139 filter_replace_buf.data[4] |=
8140 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8142 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8143 &filter_replace_buf);
8144 if (!status && (filter_replace.old_filter_type !=
8145 filter_replace.new_filter_type))
8146 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8147 " original: 0x%x, new: 0x%x",
8149 filter_replace.old_filter_type,
8150 filter_replace.new_filter_type);
8155 static enum i40e_status_code
8156 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8158 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8159 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8160 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8161 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8162 enum i40e_status_code status = I40E_SUCCESS;
8164 if (pf->support_multi_driver) {
8165 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8166 return I40E_NOT_SUPPORTED;
8170 memset(&filter_replace, 0,
8171 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8172 memset(&filter_replace_buf, 0,
8173 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8174 /* create L1 filter */
8175 filter_replace.old_filter_type =
8176 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8177 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8178 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8179 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8180 /* Prepare the buffer, 2 entries */
8181 filter_replace_buf.data[0] =
8182 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8183 filter_replace_buf.data[0] |=
8184 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8185 filter_replace_buf.data[2] = 0xFF;
8186 filter_replace_buf.data[3] = 0xFF;
8187 filter_replace_buf.data[4] =
8188 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8189 filter_replace_buf.data[4] |=
8190 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8191 filter_replace_buf.data[6] = 0xFF;
8192 filter_replace_buf.data[7] = 0xFF;
8193 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8194 &filter_replace_buf);
8197 if (filter_replace.old_filter_type !=
8198 filter_replace.new_filter_type)
8199 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8200 " original: 0x%x, new: 0x%x",
8202 filter_replace.old_filter_type,
8203 filter_replace.new_filter_type);
8206 memset(&filter_replace, 0,
8207 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8208 memset(&filter_replace_buf, 0,
8209 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8210 /* create L1 filter */
8211 filter_replace.old_filter_type =
8212 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8213 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8214 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8215 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8216 /* Prepare the buffer, 2 entries */
8217 filter_replace_buf.data[0] =
8218 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8219 filter_replace_buf.data[0] |=
8220 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8221 filter_replace_buf.data[2] = 0xFF;
8222 filter_replace_buf.data[3] = 0xFF;
8223 filter_replace_buf.data[4] =
8224 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8225 filter_replace_buf.data[4] |=
8226 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8227 filter_replace_buf.data[6] = 0xFF;
8228 filter_replace_buf.data[7] = 0xFF;
8230 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8231 &filter_replace_buf);
8232 if (!status && (filter_replace.old_filter_type !=
8233 filter_replace.new_filter_type))
8234 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8235 " original: 0x%x, new: 0x%x",
8237 filter_replace.old_filter_type,
8238 filter_replace.new_filter_type);
8244 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8246 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8247 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8248 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8249 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8250 enum i40e_status_code status = I40E_SUCCESS;
8252 if (pf->support_multi_driver) {
8253 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8254 return I40E_NOT_SUPPORTED;
8258 memset(&filter_replace, 0,
8259 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8260 memset(&filter_replace_buf, 0,
8261 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8262 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8263 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8264 filter_replace.new_filter_type =
8265 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8266 /* Prepare the buffer, 2 entries */
8267 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8268 filter_replace_buf.data[0] |=
8269 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8270 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8271 filter_replace_buf.data[4] |=
8272 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8273 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8274 &filter_replace_buf);
8277 if (filter_replace.old_filter_type !=
8278 filter_replace.new_filter_type)
8279 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8280 " original: 0x%x, new: 0x%x",
8282 filter_replace.old_filter_type,
8283 filter_replace.new_filter_type);
8286 memset(&filter_replace, 0,
8287 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8288 memset(&filter_replace_buf, 0,
8289 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8290 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8291 filter_replace.old_filter_type =
8292 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8293 filter_replace.new_filter_type =
8294 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8295 /* Prepare the buffer, 2 entries */
8296 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8297 filter_replace_buf.data[0] |=
8298 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8299 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8300 filter_replace_buf.data[4] |=
8301 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8303 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8304 &filter_replace_buf);
8305 if (!status && (filter_replace.old_filter_type !=
8306 filter_replace.new_filter_type))
8307 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8308 " original: 0x%x, new: 0x%x",
8310 filter_replace.old_filter_type,
8311 filter_replace.new_filter_type);
8317 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8318 struct i40e_tunnel_filter_conf *tunnel_filter,
8322 uint32_t ipv4_addr, ipv4_addr_le;
8323 uint8_t i, tun_type = 0;
8324 /* internal variable to convert ipv6 byte order */
8325 uint32_t convert_ipv6[4];
8327 struct i40e_pf_vf *vf = NULL;
8328 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8329 struct i40e_vsi *vsi;
8330 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8331 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8332 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8333 struct i40e_tunnel_filter *tunnel, *node;
8334 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8336 bool big_buffer = 0;
8338 cld_filter = rte_zmalloc("tunnel_filter",
8339 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8342 if (cld_filter == NULL) {
8343 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8346 pfilter = cld_filter;
8348 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8349 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8350 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8351 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8353 pfilter->element.inner_vlan =
8354 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8355 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8356 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8357 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8358 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8359 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8361 sizeof(pfilter->element.ipaddr.v4.data));
8363 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8364 for (i = 0; i < 4; i++) {
8366 rte_cpu_to_le_32(rte_be_to_cpu_32(
8367 tunnel_filter->ip_addr.ipv6_addr[i]));
8369 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8371 sizeof(pfilter->element.ipaddr.v6.data));
8374 /* check tunneled type */
8375 switch (tunnel_filter->tunnel_type) {
8376 case I40E_TUNNEL_TYPE_VXLAN:
8377 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8379 case I40E_TUNNEL_TYPE_NVGRE:
8380 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8382 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8383 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8385 case I40E_TUNNEL_TYPE_MPLSoUDP:
8386 if (!pf->mpls_replace_flag) {
8387 i40e_replace_mpls_l1_filter(pf);
8388 i40e_replace_mpls_cloud_filter(pf);
8389 pf->mpls_replace_flag = 1;
8391 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8392 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8394 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8395 (teid_le & 0xF) << 12;
8396 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8399 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8401 case I40E_TUNNEL_TYPE_MPLSoGRE:
8402 if (!pf->mpls_replace_flag) {
8403 i40e_replace_mpls_l1_filter(pf);
8404 i40e_replace_mpls_cloud_filter(pf);
8405 pf->mpls_replace_flag = 1;
8407 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8408 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8410 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8411 (teid_le & 0xF) << 12;
8412 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8415 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8417 case I40E_TUNNEL_TYPE_GTPC:
8418 if (!pf->gtp_replace_flag) {
8419 i40e_replace_gtp_l1_filter(pf);
8420 i40e_replace_gtp_cloud_filter(pf);
8421 pf->gtp_replace_flag = 1;
8423 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8424 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8425 (teid_le >> 16) & 0xFFFF;
8426 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8428 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8432 case I40E_TUNNEL_TYPE_GTPU:
8433 if (!pf->gtp_replace_flag) {
8434 i40e_replace_gtp_l1_filter(pf);
8435 i40e_replace_gtp_cloud_filter(pf);
8436 pf->gtp_replace_flag = 1;
8438 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8439 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8440 (teid_le >> 16) & 0xFFFF;
8441 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8443 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8447 case I40E_TUNNEL_TYPE_QINQ:
8448 if (!pf->qinq_replace_flag) {
8449 ret = i40e_cloud_filter_qinq_create(pf);
8452 "QinQ tunnel filter already created.");
8453 pf->qinq_replace_flag = 1;
8455 /* Add in the General fields the values of
8456 * the Outer and Inner VLAN
8457 * Big Buffer should be set, see changes in
8458 * i40e_aq_add_cloud_filters
8460 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8461 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8465 /* Other tunnel types is not supported. */
8466 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8467 rte_free(cld_filter);
8471 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8472 pfilter->element.flags =
8473 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8474 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8475 pfilter->element.flags =
8476 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8477 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8478 pfilter->element.flags =
8479 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8480 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8481 pfilter->element.flags =
8482 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8483 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8484 pfilter->element.flags |=
8485 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8487 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8488 &pfilter->element.flags);
8490 rte_free(cld_filter);
8495 pfilter->element.flags |= rte_cpu_to_le_16(
8496 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8497 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8498 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8499 pfilter->element.queue_number =
8500 rte_cpu_to_le_16(tunnel_filter->queue_id);
8502 if (!tunnel_filter->is_to_vf)
8505 if (tunnel_filter->vf_id >= pf->vf_num) {
8506 PMD_DRV_LOG(ERR, "Invalid argument.");
8507 rte_free(cld_filter);
8510 vf = &pf->vfs[tunnel_filter->vf_id];
8514 /* Check if there is the filter in SW list */
8515 memset(&check_filter, 0, sizeof(check_filter));
8516 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8517 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8518 check_filter.vf_id = tunnel_filter->vf_id;
8519 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8521 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8522 rte_free(cld_filter);
8526 if (!add && !node) {
8527 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8528 rte_free(cld_filter);
8534 ret = i40e_aq_add_cloud_filters_bb(hw,
8535 vsi->seid, cld_filter, 1);
8537 ret = i40e_aq_add_cloud_filters(hw,
8538 vsi->seid, &cld_filter->element, 1);
8540 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8541 rte_free(cld_filter);
8544 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8545 if (tunnel == NULL) {
8546 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8547 rte_free(cld_filter);
8551 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8552 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8557 ret = i40e_aq_rem_cloud_filters_bb(
8558 hw, vsi->seid, cld_filter, 1);
8560 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8561 &cld_filter->element, 1);
8563 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8564 rte_free(cld_filter);
8567 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8570 rte_free(cld_filter);
8575 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8579 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8580 if (pf->vxlan_ports[i] == port)
8588 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8591 uint8_t filter_idx = 0;
8592 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8594 idx = i40e_get_vxlan_port_idx(pf, port);
8596 /* Check if port already exists */
8598 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8602 /* Now check if there is space to add the new port */
8603 idx = i40e_get_vxlan_port_idx(pf, 0);
8606 "Maximum number of UDP ports reached, not adding port %d",
8611 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8614 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8618 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8621 /* New port: add it and mark its index in the bitmap */
8622 pf->vxlan_ports[idx] = port;
8623 pf->vxlan_bitmap |= (1 << idx);
8625 if (!(pf->flags & I40E_FLAG_VXLAN))
8626 pf->flags |= I40E_FLAG_VXLAN;
8632 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8635 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8637 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8638 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8642 idx = i40e_get_vxlan_port_idx(pf, port);
8645 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8649 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8650 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8654 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8657 pf->vxlan_ports[idx] = 0;
8658 pf->vxlan_bitmap &= ~(1 << idx);
8660 if (!pf->vxlan_bitmap)
8661 pf->flags &= ~I40E_FLAG_VXLAN;
8666 /* Add UDP tunneling port */
8668 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8669 struct rte_eth_udp_tunnel *udp_tunnel)
8672 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8674 if (udp_tunnel == NULL)
8677 switch (udp_tunnel->prot_type) {
8678 case RTE_TUNNEL_TYPE_VXLAN:
8679 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8680 I40E_AQC_TUNNEL_TYPE_VXLAN);
8682 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8683 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8684 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8686 case RTE_TUNNEL_TYPE_GENEVE:
8687 case RTE_TUNNEL_TYPE_TEREDO:
8688 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8693 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8701 /* Remove UDP tunneling port */
8703 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8704 struct rte_eth_udp_tunnel *udp_tunnel)
8707 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8709 if (udp_tunnel == NULL)
8712 switch (udp_tunnel->prot_type) {
8713 case RTE_TUNNEL_TYPE_VXLAN:
8714 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8715 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8717 case RTE_TUNNEL_TYPE_GENEVE:
8718 case RTE_TUNNEL_TYPE_TEREDO:
8719 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8723 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8731 /* Calculate the maximum number of contiguous PF queues that are configured */
8733 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8735 struct rte_eth_dev_data *data = pf->dev_data;
8737 struct i40e_rx_queue *rxq;
8740 for (i = 0; i < pf->lan_nb_qps; i++) {
8741 rxq = data->rx_queues[i];
8742 if (rxq && rxq->q_set)
8753 i40e_pf_config_rss(struct i40e_pf *pf)
8755 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8756 struct rte_eth_rss_conf rss_conf;
8757 uint32_t i, lut = 0;
8761 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8762 * It's necessary to calculate the actual PF queues that are configured.
8764 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8765 num = i40e_pf_calc_configured_queues_num(pf);
8767 num = pf->dev_data->nb_rx_queues;
8769 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8770 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8775 "No PF queues are configured to enable RSS for port %u",
8776 pf->dev_data->port_id);
8780 if (pf->adapter->rss_reta_updated == 0) {
8781 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8784 lut = (lut << 8) | (j & ((0x1 <<
8785 hw->func_caps.rss_table_entry_width) - 1));
8787 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8792 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8793 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8794 i40e_pf_disable_rss(pf);
8797 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8798 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8799 /* Random default keys */
8800 static uint32_t rss_key_default[] = {0x6b793944,
8801 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8802 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8803 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8805 rss_conf.rss_key = (uint8_t *)rss_key_default;
8806 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8810 return i40e_hw_rss_hash_set(pf, &rss_conf);
8814 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8815 struct rte_eth_tunnel_filter_conf *filter)
8817 if (pf == NULL || filter == NULL) {
8818 PMD_DRV_LOG(ERR, "Invalid parameter");
8822 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8823 PMD_DRV_LOG(ERR, "Invalid queue ID");
8827 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8828 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8832 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8833 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8834 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8838 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8839 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8840 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8847 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8848 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8850 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8852 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8856 if (pf->support_multi_driver) {
8857 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8861 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8862 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8865 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8866 } else if (len == 4) {
8867 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8869 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8874 ret = i40e_aq_debug_write_global_register(hw,
8875 I40E_GL_PRS_FVBM(2),
8879 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8880 "with value 0x%08x",
8881 I40E_GL_PRS_FVBM(2), reg);
8885 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8886 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8892 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8899 switch (cfg->cfg_type) {
8900 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8901 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8904 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8912 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8913 enum rte_filter_op filter_op,
8916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8917 int ret = I40E_ERR_PARAM;
8919 switch (filter_op) {
8920 case RTE_ETH_FILTER_SET:
8921 ret = i40e_dev_global_config_set(hw,
8922 (struct rte_eth_global_cfg *)arg);
8925 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8933 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8934 enum rte_filter_op filter_op,
8937 struct rte_eth_tunnel_filter_conf *filter;
8938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8939 int ret = I40E_SUCCESS;
8941 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8943 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8944 return I40E_ERR_PARAM;
8946 switch (filter_op) {
8947 case RTE_ETH_FILTER_NOP:
8948 if (!(pf->flags & I40E_FLAG_VXLAN))
8949 ret = I40E_NOT_SUPPORTED;
8951 case RTE_ETH_FILTER_ADD:
8952 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8954 case RTE_ETH_FILTER_DELETE:
8955 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8958 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8959 ret = I40E_ERR_PARAM;
8967 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8970 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8973 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8974 ret = i40e_pf_config_rss(pf);
8976 i40e_pf_disable_rss(pf);
8981 /* Get the symmetric hash enable configurations per port */
8983 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8985 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8987 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8990 /* Set the symmetric hash enable configurations per port */
8992 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8994 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8997 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8999 "Symmetric hash has already been enabled");
9002 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9004 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9006 "Symmetric hash has already been disabled");
9009 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9011 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9012 I40E_WRITE_FLUSH(hw);
9016 * Get global configurations of hash function type and symmetric hash enable
9017 * per flow type (pctype). Note that global configuration means it affects all
9018 * the ports on the same NIC.
9021 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9022 struct rte_eth_hash_global_conf *g_cfg)
9024 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9028 memset(g_cfg, 0, sizeof(*g_cfg));
9029 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9030 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9031 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9033 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9034 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9035 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9038 * As i40e supports less than 64 flow types, only first 64 bits need to
9041 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9042 g_cfg->valid_bit_mask[i] = 0ULL;
9043 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9046 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9048 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9049 if (!adapter->pctypes_tbl[i])
9051 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9052 j < I40E_FILTER_PCTYPE_MAX; j++) {
9053 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9054 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9055 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9056 g_cfg->sym_hash_enable_mask[0] |=
9067 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9068 const struct rte_eth_hash_global_conf *g_cfg)
9071 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9073 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9074 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9075 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9076 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9082 * As i40e supports less than 64 flow types, only first 64 bits need to
9085 mask0 = g_cfg->valid_bit_mask[0];
9086 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9088 /* Check if any unsupported flow type configured */
9089 if ((mask0 | i40e_mask) ^ i40e_mask)
9092 if (g_cfg->valid_bit_mask[i])
9100 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9106 * Set global configurations of hash function type and symmetric hash enable
9107 * per flow type (pctype). Note any modifying global configuration will affect
9108 * all the ports on the same NIC.
9111 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9112 struct rte_eth_hash_global_conf *g_cfg)
9114 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9115 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9119 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9121 if (pf->support_multi_driver) {
9122 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9126 /* Check the input parameters */
9127 ret = i40e_hash_global_config_check(adapter, g_cfg);
9132 * As i40e supports less than 64 flow types, only first 64 bits need to
9135 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9136 if (mask0 & (1UL << i)) {
9137 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9138 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9140 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9141 j < I40E_FILTER_PCTYPE_MAX; j++) {
9142 if (adapter->pctypes_tbl[i] & (1ULL << j))
9143 i40e_write_global_rx_ctl(hw,
9150 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9151 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9153 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9155 "Hash function already set to Toeplitz");
9158 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9159 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9161 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9163 "Hash function already set to Simple XOR");
9166 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9168 /* Use the default, and keep it as it is */
9171 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9174 I40E_WRITE_FLUSH(hw);
9180 * Valid input sets for hash and flow director filters per PCTYPE
9183 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9184 enum rte_filter_type filter)
9188 static const uint64_t valid_hash_inset_table[] = {
9189 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9190 I40E_INSET_DMAC | I40E_INSET_SMAC |
9191 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9192 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9193 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9194 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9195 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9196 I40E_INSET_FLEX_PAYLOAD,
9197 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9198 I40E_INSET_DMAC | I40E_INSET_SMAC |
9199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9200 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9201 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9202 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9203 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9204 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9205 I40E_INSET_FLEX_PAYLOAD,
9206 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9207 I40E_INSET_DMAC | I40E_INSET_SMAC |
9208 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9209 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9210 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9211 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9212 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9213 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9214 I40E_INSET_FLEX_PAYLOAD,
9215 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9216 I40E_INSET_DMAC | I40E_INSET_SMAC |
9217 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9219 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9220 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9221 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9222 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9223 I40E_INSET_FLEX_PAYLOAD,
9224 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9225 I40E_INSET_DMAC | I40E_INSET_SMAC |
9226 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9227 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9228 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9229 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9230 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9231 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9232 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9233 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9234 I40E_INSET_DMAC | I40E_INSET_SMAC |
9235 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9236 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9237 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9238 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9239 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9240 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9241 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9242 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9243 I40E_INSET_DMAC | I40E_INSET_SMAC |
9244 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9245 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9246 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9247 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9248 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9249 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9250 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9251 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9252 I40E_INSET_DMAC | I40E_INSET_SMAC |
9253 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9254 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9255 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9256 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9257 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9258 I40E_INSET_FLEX_PAYLOAD,
9259 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9260 I40E_INSET_DMAC | I40E_INSET_SMAC |
9261 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9262 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9263 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9264 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9265 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9266 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9267 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9268 I40E_INSET_DMAC | I40E_INSET_SMAC |
9269 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9270 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9271 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9272 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9273 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9274 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9275 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9276 I40E_INSET_DMAC | I40E_INSET_SMAC |
9277 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9278 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9279 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9280 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9281 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9282 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9283 I40E_INSET_FLEX_PAYLOAD,
9284 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9285 I40E_INSET_DMAC | I40E_INSET_SMAC |
9286 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9287 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9288 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9289 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9290 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9291 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9292 I40E_INSET_FLEX_PAYLOAD,
9293 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9294 I40E_INSET_DMAC | I40E_INSET_SMAC |
9295 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9296 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9297 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9298 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9299 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9300 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9301 I40E_INSET_FLEX_PAYLOAD,
9302 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9303 I40E_INSET_DMAC | I40E_INSET_SMAC |
9304 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9305 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9306 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9307 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9308 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9309 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9310 I40E_INSET_FLEX_PAYLOAD,
9311 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9312 I40E_INSET_DMAC | I40E_INSET_SMAC |
9313 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9314 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9315 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9316 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9317 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9318 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9319 I40E_INSET_FLEX_PAYLOAD,
9320 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9321 I40E_INSET_DMAC | I40E_INSET_SMAC |
9322 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9323 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9324 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9325 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9326 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9327 I40E_INSET_FLEX_PAYLOAD,
9328 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9329 I40E_INSET_DMAC | I40E_INSET_SMAC |
9330 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9331 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9332 I40E_INSET_FLEX_PAYLOAD,
9336 * Flow director supports only fields defined in
9337 * union rte_eth_fdir_flow.
9339 static const uint64_t valid_fdir_inset_table[] = {
9340 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9341 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9342 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9343 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9344 I40E_INSET_IPV4_TTL,
9345 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9346 I40E_INSET_DMAC | I40E_INSET_SMAC |
9347 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9348 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9349 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9350 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9351 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9352 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9353 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9354 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9355 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9356 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9357 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9358 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9359 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9360 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9361 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9362 I40E_INSET_DMAC | I40E_INSET_SMAC |
9363 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9364 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9365 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9366 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9367 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9368 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9369 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9370 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9371 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9372 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9373 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9374 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9375 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9376 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9378 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9379 I40E_INSET_DMAC | I40E_INSET_SMAC |
9380 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9381 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9382 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9383 I40E_INSET_IPV4_TTL,
9384 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9385 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9386 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9387 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9388 I40E_INSET_IPV6_HOP_LIMIT,
9389 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9390 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9391 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9392 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9393 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9394 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9395 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9396 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9397 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9398 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9399 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9400 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9401 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9402 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9403 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9404 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9405 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9406 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9407 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9408 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9409 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9410 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9411 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9412 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9413 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9414 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9415 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9416 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9417 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9418 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9420 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9421 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9422 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9423 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9424 I40E_INSET_IPV6_HOP_LIMIT,
9425 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9426 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9427 I40E_INSET_LAST_ETHER_TYPE,
9430 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9432 if (filter == RTE_ETH_FILTER_HASH)
9433 valid = valid_hash_inset_table[pctype];
9435 valid = valid_fdir_inset_table[pctype];
9441 * Validate if the input set is allowed for a specific PCTYPE
9444 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9445 enum rte_filter_type filter, uint64_t inset)
9449 valid = i40e_get_valid_input_set(pctype, filter);
9450 if (inset & (~valid))
9456 /* default input set fields combination per pctype */
9458 i40e_get_default_input_set(uint16_t pctype)
9460 static const uint64_t default_inset_table[] = {
9461 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9462 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9463 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9464 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9465 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9466 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9467 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9468 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9469 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9470 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9471 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9472 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9473 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9474 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9475 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9476 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9477 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9478 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9479 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9480 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9482 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9483 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9484 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9485 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9486 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9487 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9488 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9489 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9490 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9491 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9492 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9493 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9494 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9495 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9496 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9497 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9498 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9499 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9500 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9501 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9502 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9503 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9505 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9506 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9507 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9508 I40E_INSET_LAST_ETHER_TYPE,
9511 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9514 return default_inset_table[pctype];
9518 * Parse the input set from index to logical bit masks
9521 i40e_parse_input_set(uint64_t *inset,
9522 enum i40e_filter_pctype pctype,
9523 enum rte_eth_input_set_field *field,
9529 static const struct {
9530 enum rte_eth_input_set_field field;
9532 } inset_convert_table[] = {
9533 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9534 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9535 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9536 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9537 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9538 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9539 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9540 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9541 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9542 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9543 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9544 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9545 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9546 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9547 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9548 I40E_INSET_IPV6_NEXT_HDR},
9549 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9550 I40E_INSET_IPV6_HOP_LIMIT},
9551 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9552 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9553 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9554 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9555 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9556 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9557 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9558 I40E_INSET_SCTP_VT},
9559 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9560 I40E_INSET_TUNNEL_DMAC},
9561 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9562 I40E_INSET_VLAN_TUNNEL},
9563 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9564 I40E_INSET_TUNNEL_ID},
9565 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9566 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9567 I40E_INSET_FLEX_PAYLOAD_W1},
9568 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9569 I40E_INSET_FLEX_PAYLOAD_W2},
9570 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9571 I40E_INSET_FLEX_PAYLOAD_W3},
9572 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9573 I40E_INSET_FLEX_PAYLOAD_W4},
9574 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9575 I40E_INSET_FLEX_PAYLOAD_W5},
9576 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9577 I40E_INSET_FLEX_PAYLOAD_W6},
9578 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9579 I40E_INSET_FLEX_PAYLOAD_W7},
9580 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9581 I40E_INSET_FLEX_PAYLOAD_W8},
9584 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9587 /* Only one item allowed for default or all */
9589 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9590 *inset = i40e_get_default_input_set(pctype);
9592 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9593 *inset = I40E_INSET_NONE;
9598 for (i = 0, *inset = 0; i < size; i++) {
9599 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9600 if (field[i] == inset_convert_table[j].field) {
9601 *inset |= inset_convert_table[j].inset;
9606 /* It contains unsupported input set, return immediately */
9607 if (j == RTE_DIM(inset_convert_table))
9615 * Translate the input set from bit masks to register aware bit masks
9619 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9629 static const struct inset_map inset_map_common[] = {
9630 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9631 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9632 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9633 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9634 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9635 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9636 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9637 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9638 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9639 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9640 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9641 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9642 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9643 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9644 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9645 {I40E_INSET_TUNNEL_DMAC,
9646 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9647 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9648 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9649 {I40E_INSET_TUNNEL_SRC_PORT,
9650 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9651 {I40E_INSET_TUNNEL_DST_PORT,
9652 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9653 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9654 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9655 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9656 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9657 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9658 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9659 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9660 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9661 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9664 /* some different registers map in x722*/
9665 static const struct inset_map inset_map_diff_x722[] = {
9666 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9667 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9668 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9669 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9672 static const struct inset_map inset_map_diff_not_x722[] = {
9673 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9674 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9675 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9676 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9682 /* Translate input set to register aware inset */
9683 if (type == I40E_MAC_X722) {
9684 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9685 if (input & inset_map_diff_x722[i].inset)
9686 val |= inset_map_diff_x722[i].inset_reg;
9689 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9690 if (input & inset_map_diff_not_x722[i].inset)
9691 val |= inset_map_diff_not_x722[i].inset_reg;
9695 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9696 if (input & inset_map_common[i].inset)
9697 val |= inset_map_common[i].inset_reg;
9704 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9707 uint64_t inset_need_mask = inset;
9709 static const struct {
9712 } inset_mask_map[] = {
9713 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9714 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9715 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9716 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9717 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9718 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9719 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9720 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9723 if (!inset || !mask || !nb_elem)
9726 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9727 /* Clear the inset bit, if no MASK is required,
9728 * for example proto + ttl
9730 if ((inset & inset_mask_map[i].inset) ==
9731 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9732 inset_need_mask &= ~inset_mask_map[i].inset;
9733 if (!inset_need_mask)
9736 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9737 if ((inset_need_mask & inset_mask_map[i].inset) ==
9738 inset_mask_map[i].inset) {
9739 if (idx >= nb_elem) {
9740 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9743 mask[idx] = inset_mask_map[i].mask;
9752 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9754 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9756 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9758 i40e_write_rx_ctl(hw, addr, val);
9759 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9760 (uint32_t)i40e_read_rx_ctl(hw, addr));
9764 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9766 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9767 struct rte_eth_dev *dev;
9769 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9771 i40e_write_rx_ctl(hw, addr, val);
9772 PMD_DRV_LOG(WARNING,
9773 "i40e device %s changed global register [0x%08x]."
9774 " original: 0x%08x, new: 0x%08x",
9775 dev->device->name, addr, reg,
9776 (uint32_t)i40e_read_rx_ctl(hw, addr));
9781 i40e_filter_input_set_init(struct i40e_pf *pf)
9783 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9784 enum i40e_filter_pctype pctype;
9785 uint64_t input_set, inset_reg;
9786 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9790 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9791 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9792 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9794 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9797 input_set = i40e_get_default_input_set(pctype);
9799 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9800 I40E_INSET_MASK_NUM_REG);
9803 if (pf->support_multi_driver && num > 0) {
9804 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9807 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9810 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9811 (uint32_t)(inset_reg & UINT32_MAX));
9812 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9813 (uint32_t)((inset_reg >>
9814 I40E_32_BIT_WIDTH) & UINT32_MAX));
9815 if (!pf->support_multi_driver) {
9816 i40e_check_write_global_reg(hw,
9817 I40E_GLQF_HASH_INSET(0, pctype),
9818 (uint32_t)(inset_reg & UINT32_MAX));
9819 i40e_check_write_global_reg(hw,
9820 I40E_GLQF_HASH_INSET(1, pctype),
9821 (uint32_t)((inset_reg >>
9822 I40E_32_BIT_WIDTH) & UINT32_MAX));
9824 for (i = 0; i < num; i++) {
9825 i40e_check_write_global_reg(hw,
9826 I40E_GLQF_FD_MSK(i, pctype),
9828 i40e_check_write_global_reg(hw,
9829 I40E_GLQF_HASH_MSK(i, pctype),
9832 /*clear unused mask registers of the pctype */
9833 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9834 i40e_check_write_global_reg(hw,
9835 I40E_GLQF_FD_MSK(i, pctype),
9837 i40e_check_write_global_reg(hw,
9838 I40E_GLQF_HASH_MSK(i, pctype),
9842 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9844 I40E_WRITE_FLUSH(hw);
9846 /* store the default input set */
9847 if (!pf->support_multi_driver)
9848 pf->hash_input_set[pctype] = input_set;
9849 pf->fdir.input_set[pctype] = input_set;
9854 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9855 struct rte_eth_input_set_conf *conf)
9857 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9858 enum i40e_filter_pctype pctype;
9859 uint64_t input_set, inset_reg = 0;
9860 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9864 PMD_DRV_LOG(ERR, "Invalid pointer");
9867 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9868 conf->op != RTE_ETH_INPUT_SET_ADD) {
9869 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9873 if (pf->support_multi_driver) {
9874 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9878 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9879 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9880 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9884 if (hw->mac.type == I40E_MAC_X722) {
9885 /* get translated pctype value in fd pctype register */
9886 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9887 I40E_GLQF_FD_PCTYPES((int)pctype));
9890 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9893 PMD_DRV_LOG(ERR, "Failed to parse input set");
9897 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9898 /* get inset value in register */
9899 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9900 inset_reg <<= I40E_32_BIT_WIDTH;
9901 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9902 input_set |= pf->hash_input_set[pctype];
9904 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9905 I40E_INSET_MASK_NUM_REG);
9909 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9911 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9912 (uint32_t)(inset_reg & UINT32_MAX));
9913 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9914 (uint32_t)((inset_reg >>
9915 I40E_32_BIT_WIDTH) & UINT32_MAX));
9917 for (i = 0; i < num; i++)
9918 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9920 /*clear unused mask registers of the pctype */
9921 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9922 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9924 I40E_WRITE_FLUSH(hw);
9926 pf->hash_input_set[pctype] = input_set;
9931 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9932 struct rte_eth_input_set_conf *conf)
9934 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9935 enum i40e_filter_pctype pctype;
9936 uint64_t input_set, inset_reg = 0;
9937 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9941 PMD_DRV_LOG(ERR, "Invalid pointer");
9944 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9945 conf->op != RTE_ETH_INPUT_SET_ADD) {
9946 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9950 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9952 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9953 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9957 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9960 PMD_DRV_LOG(ERR, "Failed to parse input set");
9964 /* get inset value in register */
9965 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9966 inset_reg <<= I40E_32_BIT_WIDTH;
9967 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9969 /* Can not change the inset reg for flex payload for fdir,
9970 * it is done by writing I40E_PRTQF_FD_FLXINSET
9971 * in i40e_set_flex_mask_on_pctype.
9973 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9974 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9976 input_set |= pf->fdir.input_set[pctype];
9977 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9978 I40E_INSET_MASK_NUM_REG);
9981 if (pf->support_multi_driver && num > 0) {
9982 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9986 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9988 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9989 (uint32_t)(inset_reg & UINT32_MAX));
9990 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9991 (uint32_t)((inset_reg >>
9992 I40E_32_BIT_WIDTH) & UINT32_MAX));
9994 if (!pf->support_multi_driver) {
9995 for (i = 0; i < num; i++)
9996 i40e_check_write_global_reg(hw,
9997 I40E_GLQF_FD_MSK(i, pctype),
9999 /*clear unused mask registers of the pctype */
10000 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10001 i40e_check_write_global_reg(hw,
10002 I40E_GLQF_FD_MSK(i, pctype),
10005 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10007 I40E_WRITE_FLUSH(hw);
10009 pf->fdir.input_set[pctype] = input_set;
10014 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10018 if (!hw || !info) {
10019 PMD_DRV_LOG(ERR, "Invalid pointer");
10023 switch (info->info_type) {
10024 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10025 i40e_get_symmetric_hash_enable_per_port(hw,
10026 &(info->info.enable));
10028 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10029 ret = i40e_get_hash_filter_global_config(hw,
10030 &(info->info.global_conf));
10033 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10043 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10047 if (!hw || !info) {
10048 PMD_DRV_LOG(ERR, "Invalid pointer");
10052 switch (info->info_type) {
10053 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10054 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10056 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10057 ret = i40e_set_hash_filter_global_config(hw,
10058 &(info->info.global_conf));
10060 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10061 ret = i40e_hash_filter_inset_select(hw,
10062 &(info->info.input_set_conf));
10066 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10075 /* Operations for hash function */
10077 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10078 enum rte_filter_op filter_op,
10081 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10084 switch (filter_op) {
10085 case RTE_ETH_FILTER_NOP:
10087 case RTE_ETH_FILTER_GET:
10088 ret = i40e_hash_filter_get(hw,
10089 (struct rte_eth_hash_filter_info *)arg);
10091 case RTE_ETH_FILTER_SET:
10092 ret = i40e_hash_filter_set(hw,
10093 (struct rte_eth_hash_filter_info *)arg);
10096 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10105 /* Convert ethertype filter structure */
10107 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10108 struct i40e_ethertype_filter *filter)
10110 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10111 RTE_ETHER_ADDR_LEN);
10112 filter->input.ether_type = input->ether_type;
10113 filter->flags = input->flags;
10114 filter->queue = input->queue;
10119 /* Check if there exists the ehtertype filter */
10120 struct i40e_ethertype_filter *
10121 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10122 const struct i40e_ethertype_filter_input *input)
10126 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10130 return ethertype_rule->hash_map[ret];
10133 /* Add ethertype filter in SW list */
10135 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10136 struct i40e_ethertype_filter *filter)
10138 struct i40e_ethertype_rule *rule = &pf->ethertype;
10141 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10144 "Failed to insert ethertype filter"
10145 " to hash table %d!",
10149 rule->hash_map[ret] = filter;
10151 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10156 /* Delete ethertype filter in SW list */
10158 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10159 struct i40e_ethertype_filter_input *input)
10161 struct i40e_ethertype_rule *rule = &pf->ethertype;
10162 struct i40e_ethertype_filter *filter;
10165 ret = rte_hash_del_key(rule->hash_table, input);
10168 "Failed to delete ethertype filter"
10169 " to hash table %d!",
10173 filter = rule->hash_map[ret];
10174 rule->hash_map[ret] = NULL;
10176 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10183 * Configure ethertype filter, which can director packet by filtering
10184 * with mac address and ether_type or only ether_type
10187 i40e_ethertype_filter_set(struct i40e_pf *pf,
10188 struct rte_eth_ethertype_filter *filter,
10191 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10192 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10193 struct i40e_ethertype_filter *ethertype_filter, *node;
10194 struct i40e_ethertype_filter check_filter;
10195 struct i40e_control_filter_stats stats;
10196 uint16_t flags = 0;
10199 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10200 PMD_DRV_LOG(ERR, "Invalid queue ID");
10203 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10204 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10206 "unsupported ether_type(0x%04x) in control packet filter.",
10207 filter->ether_type);
10210 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10211 PMD_DRV_LOG(WARNING,
10212 "filter vlan ether_type in first tag is not supported.");
10214 /* Check if there is the filter in SW list */
10215 memset(&check_filter, 0, sizeof(check_filter));
10216 i40e_ethertype_filter_convert(filter, &check_filter);
10217 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10218 &check_filter.input);
10220 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10224 if (!add && !node) {
10225 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10229 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10230 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10231 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10232 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10233 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10235 memset(&stats, 0, sizeof(stats));
10236 ret = i40e_aq_add_rem_control_packet_filter(hw,
10237 filter->mac_addr.addr_bytes,
10238 filter->ether_type, flags,
10239 pf->main_vsi->seid,
10240 filter->queue, add, &stats, NULL);
10243 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10244 ret, stats.mac_etype_used, stats.etype_used,
10245 stats.mac_etype_free, stats.etype_free);
10249 /* Add or delete a filter in SW list */
10251 ethertype_filter = rte_zmalloc("ethertype_filter",
10252 sizeof(*ethertype_filter), 0);
10253 if (ethertype_filter == NULL) {
10254 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10258 rte_memcpy(ethertype_filter, &check_filter,
10259 sizeof(check_filter));
10260 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10262 rte_free(ethertype_filter);
10264 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10271 * Handle operations for ethertype filter.
10274 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10275 enum rte_filter_op filter_op,
10278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10281 if (filter_op == RTE_ETH_FILTER_NOP)
10285 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10290 switch (filter_op) {
10291 case RTE_ETH_FILTER_ADD:
10292 ret = i40e_ethertype_filter_set(pf,
10293 (struct rte_eth_ethertype_filter *)arg,
10296 case RTE_ETH_FILTER_DELETE:
10297 ret = i40e_ethertype_filter_set(pf,
10298 (struct rte_eth_ethertype_filter *)arg,
10302 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10310 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10311 enum rte_filter_type filter_type,
10312 enum rte_filter_op filter_op,
10320 switch (filter_type) {
10321 case RTE_ETH_FILTER_NONE:
10322 /* For global configuration */
10323 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10325 case RTE_ETH_FILTER_HASH:
10326 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10328 case RTE_ETH_FILTER_MACVLAN:
10329 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10331 case RTE_ETH_FILTER_ETHERTYPE:
10332 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10334 case RTE_ETH_FILTER_TUNNEL:
10335 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10337 case RTE_ETH_FILTER_FDIR:
10338 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10340 case RTE_ETH_FILTER_GENERIC:
10341 if (filter_op != RTE_ETH_FILTER_GET)
10343 *(const void **)arg = &i40e_flow_ops;
10346 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10356 * Check and enable Extended Tag.
10357 * Enabling Extended Tag is important for 40G performance.
10360 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10362 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10366 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10369 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10373 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10374 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10379 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10382 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10386 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10387 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10390 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10391 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10394 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10401 * As some registers wouldn't be reset unless a global hardware reset,
10402 * hardware initialization is needed to put those registers into an
10403 * expected initial state.
10406 i40e_hw_init(struct rte_eth_dev *dev)
10408 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10410 i40e_enable_extended_tag(dev);
10412 /* clear the PF Queue Filter control register */
10413 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10415 /* Disable symmetric hash per port */
10416 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10420 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10421 * however this function will return only one highest pctype index,
10422 * which is not quite correct. This is known problem of i40e driver
10423 * and needs to be fixed later.
10425 enum i40e_filter_pctype
10426 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10429 uint64_t pctype_mask;
10431 if (flow_type < I40E_FLOW_TYPE_MAX) {
10432 pctype_mask = adapter->pctypes_tbl[flow_type];
10433 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10434 if (pctype_mask & (1ULL << i))
10435 return (enum i40e_filter_pctype)i;
10438 return I40E_FILTER_PCTYPE_INVALID;
10442 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10443 enum i40e_filter_pctype pctype)
10446 uint64_t pctype_mask = 1ULL << pctype;
10448 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10450 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10454 return RTE_ETH_FLOW_UNKNOWN;
10458 * On X710, performance number is far from the expectation on recent firmware
10459 * versions; on XL710, performance number is also far from the expectation on
10460 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10461 * mode is enabled and port MAC address is equal to the packet destination MAC
10462 * address. The fix for this issue may not be integrated in the following
10463 * firmware version. So the workaround in software driver is needed. It needs
10464 * to modify the initial values of 3 internal only registers for both X710 and
10465 * XL710. Note that the values for X710 or XL710 could be different, and the
10466 * workaround can be removed when it is fixed in firmware in the future.
10469 /* For both X710 and XL710 */
10470 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10471 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10472 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10474 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10475 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10478 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10479 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10482 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10484 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10485 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10488 * GL_SWR_PM_UP_THR:
10489 * The value is not impacted from the link speed, its value is set according
10490 * to the total number of ports for a better pipe-monitor configuration.
10493 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10495 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10496 .device_id = (dev), \
10497 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10499 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10500 .device_id = (dev), \
10501 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10503 static const struct {
10504 uint16_t device_id;
10506 } swr_pm_table[] = {
10507 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10508 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10509 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10510 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10511 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10513 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10514 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10515 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10516 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10517 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10518 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10519 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10523 if (value == NULL) {
10524 PMD_DRV_LOG(ERR, "value is NULL");
10528 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10529 if (hw->device_id == swr_pm_table[i].device_id) {
10530 *value = swr_pm_table[i].val;
10532 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10534 hw->device_id, *value);
10543 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10545 enum i40e_status_code status;
10546 struct i40e_aq_get_phy_abilities_resp phy_ab;
10547 int ret = -ENOTSUP;
10550 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10554 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10557 rte_delay_us(100000);
10559 status = i40e_aq_get_phy_capabilities(hw, false,
10560 true, &phy_ab, NULL);
10568 i40e_configure_registers(struct i40e_hw *hw)
10574 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10575 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10576 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10582 for (i = 0; i < RTE_DIM(reg_table); i++) {
10583 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10584 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10586 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10587 else /* For X710/XL710/XXV710 */
10588 if (hw->aq.fw_maj_ver < 6)
10590 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10593 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10596 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10597 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10599 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10600 else /* For X710/XL710/XXV710 */
10602 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10605 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10608 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10609 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10610 "GL_SWR_PM_UP_THR value fixup",
10615 reg_table[i].val = cfg_val;
10618 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10621 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10622 reg_table[i].addr);
10625 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10626 reg_table[i].addr, reg);
10627 if (reg == reg_table[i].val)
10630 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10631 reg_table[i].val, NULL);
10634 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10635 reg_table[i].val, reg_table[i].addr);
10638 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10639 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10643 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10644 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10645 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10646 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10648 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10653 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10654 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10658 /* Configure for double VLAN RX stripping */
10659 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10660 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10661 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10662 ret = i40e_aq_debug_write_register(hw,
10663 I40E_VSI_TSR(vsi->vsi_id),
10666 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10668 return I40E_ERR_CONFIG;
10672 /* Configure for double VLAN TX insertion */
10673 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10674 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10675 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10676 ret = i40e_aq_debug_write_register(hw,
10677 I40E_VSI_L2TAGSTXVALID(
10678 vsi->vsi_id), reg, NULL);
10681 "Failed to update VSI_L2TAGSTXVALID[%d]",
10683 return I40E_ERR_CONFIG;
10691 * i40e_aq_add_mirror_rule
10692 * @hw: pointer to the hardware structure
10693 * @seid: VEB seid to add mirror rule to
10694 * @dst_id: destination vsi seid
10695 * @entries: Buffer which contains the entities to be mirrored
10696 * @count: number of entities contained in the buffer
10697 * @rule_id:the rule_id of the rule to be added
10699 * Add a mirror rule for a given veb.
10702 static enum i40e_status_code
10703 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10704 uint16_t seid, uint16_t dst_id,
10705 uint16_t rule_type, uint16_t *entries,
10706 uint16_t count, uint16_t *rule_id)
10708 struct i40e_aq_desc desc;
10709 struct i40e_aqc_add_delete_mirror_rule cmd;
10710 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10711 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10714 enum i40e_status_code status;
10716 i40e_fill_default_direct_cmd_desc(&desc,
10717 i40e_aqc_opc_add_mirror_rule);
10718 memset(&cmd, 0, sizeof(cmd));
10720 buff_len = sizeof(uint16_t) * count;
10721 desc.datalen = rte_cpu_to_le_16(buff_len);
10723 desc.flags |= rte_cpu_to_le_16(
10724 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10725 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10726 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10727 cmd.num_entries = rte_cpu_to_le_16(count);
10728 cmd.seid = rte_cpu_to_le_16(seid);
10729 cmd.destination = rte_cpu_to_le_16(dst_id);
10731 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10732 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10734 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10735 hw->aq.asq_last_status, resp->rule_id,
10736 resp->mirror_rules_used, resp->mirror_rules_free);
10737 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10743 * i40e_aq_del_mirror_rule
10744 * @hw: pointer to the hardware structure
10745 * @seid: VEB seid to add mirror rule to
10746 * @entries: Buffer which contains the entities to be mirrored
10747 * @count: number of entities contained in the buffer
10748 * @rule_id:the rule_id of the rule to be delete
10750 * Delete a mirror rule for a given veb.
10753 static enum i40e_status_code
10754 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10755 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10756 uint16_t count, uint16_t rule_id)
10758 struct i40e_aq_desc desc;
10759 struct i40e_aqc_add_delete_mirror_rule cmd;
10760 uint16_t buff_len = 0;
10761 enum i40e_status_code status;
10764 i40e_fill_default_direct_cmd_desc(&desc,
10765 i40e_aqc_opc_delete_mirror_rule);
10766 memset(&cmd, 0, sizeof(cmd));
10767 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10768 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10770 cmd.num_entries = count;
10771 buff_len = sizeof(uint16_t) * count;
10772 desc.datalen = rte_cpu_to_le_16(buff_len);
10773 buff = (void *)entries;
10775 /* rule id is filled in destination field for deleting mirror rule */
10776 cmd.destination = rte_cpu_to_le_16(rule_id);
10778 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10779 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10780 cmd.seid = rte_cpu_to_le_16(seid);
10782 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10783 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10789 * i40e_mirror_rule_set
10790 * @dev: pointer to the hardware structure
10791 * @mirror_conf: mirror rule info
10792 * @sw_id: mirror rule's sw_id
10793 * @on: enable/disable
10795 * set a mirror rule.
10799 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10800 struct rte_eth_mirror_conf *mirror_conf,
10801 uint8_t sw_id, uint8_t on)
10803 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10804 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10805 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10806 struct i40e_mirror_rule *parent = NULL;
10807 uint16_t seid, dst_seid, rule_id;
10811 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10813 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10815 "mirror rule can not be configured without veb or vfs.");
10818 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10819 PMD_DRV_LOG(ERR, "mirror table is full.");
10822 if (mirror_conf->dst_pool > pf->vf_num) {
10823 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10824 mirror_conf->dst_pool);
10828 seid = pf->main_vsi->veb->seid;
10830 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10831 if (sw_id <= it->index) {
10837 if (mirr_rule && sw_id == mirr_rule->index) {
10839 PMD_DRV_LOG(ERR, "mirror rule exists.");
10842 ret = i40e_aq_del_mirror_rule(hw, seid,
10843 mirr_rule->rule_type,
10844 mirr_rule->entries,
10845 mirr_rule->num_entries, mirr_rule->id);
10848 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10849 ret, hw->aq.asq_last_status);
10852 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10853 rte_free(mirr_rule);
10854 pf->nb_mirror_rule--;
10858 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10862 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10863 sizeof(struct i40e_mirror_rule) , 0);
10865 PMD_DRV_LOG(ERR, "failed to allocate memory");
10866 return I40E_ERR_NO_MEMORY;
10868 switch (mirror_conf->rule_type) {
10869 case ETH_MIRROR_VLAN:
10870 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10871 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10872 mirr_rule->entries[j] =
10873 mirror_conf->vlan.vlan_id[i];
10878 PMD_DRV_LOG(ERR, "vlan is not specified.");
10879 rte_free(mirr_rule);
10882 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10884 case ETH_MIRROR_VIRTUAL_POOL_UP:
10885 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10886 /* check if the specified pool bit is out of range */
10887 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10888 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10889 rte_free(mirr_rule);
10892 for (i = 0, j = 0; i < pf->vf_num; i++) {
10893 if (mirror_conf->pool_mask & (1ULL << i)) {
10894 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10898 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10899 /* add pf vsi to entries */
10900 mirr_rule->entries[j] = pf->main_vsi_seid;
10904 PMD_DRV_LOG(ERR, "pool is not specified.");
10905 rte_free(mirr_rule);
10908 /* egress and ingress in aq commands means from switch but not port */
10909 mirr_rule->rule_type =
10910 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10911 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10912 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10914 case ETH_MIRROR_UPLINK_PORT:
10915 /* egress and ingress in aq commands means from switch but not port*/
10916 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10918 case ETH_MIRROR_DOWNLINK_PORT:
10919 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10922 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10923 mirror_conf->rule_type);
10924 rte_free(mirr_rule);
10928 /* If the dst_pool is equal to vf_num, consider it as PF */
10929 if (mirror_conf->dst_pool == pf->vf_num)
10930 dst_seid = pf->main_vsi_seid;
10932 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10934 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10935 mirr_rule->rule_type, mirr_rule->entries,
10939 "failed to add mirror rule: ret = %d, aq_err = %d.",
10940 ret, hw->aq.asq_last_status);
10941 rte_free(mirr_rule);
10945 mirr_rule->index = sw_id;
10946 mirr_rule->num_entries = j;
10947 mirr_rule->id = rule_id;
10948 mirr_rule->dst_vsi_seid = dst_seid;
10951 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10953 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10955 pf->nb_mirror_rule++;
10960 * i40e_mirror_rule_reset
10961 * @dev: pointer to the device
10962 * @sw_id: mirror rule's sw_id
10964 * reset a mirror rule.
10968 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10970 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10971 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10972 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10976 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10978 seid = pf->main_vsi->veb->seid;
10980 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10981 if (sw_id == it->index) {
10987 ret = i40e_aq_del_mirror_rule(hw, seid,
10988 mirr_rule->rule_type,
10989 mirr_rule->entries,
10990 mirr_rule->num_entries, mirr_rule->id);
10993 "failed to remove mirror rule: status = %d, aq_err = %d.",
10994 ret, hw->aq.asq_last_status);
10997 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10998 rte_free(mirr_rule);
10999 pf->nb_mirror_rule--;
11001 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11008 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11011 uint64_t systim_cycles;
11013 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11014 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11017 return systim_cycles;
11021 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11023 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11024 uint64_t rx_tstamp;
11026 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11027 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11034 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11036 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11037 uint64_t tx_tstamp;
11039 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11040 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11047 i40e_start_timecounters(struct rte_eth_dev *dev)
11049 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11050 struct i40e_adapter *adapter = dev->data->dev_private;
11051 struct rte_eth_link link;
11052 uint32_t tsync_inc_l;
11053 uint32_t tsync_inc_h;
11055 /* Get current link speed. */
11056 i40e_dev_link_update(dev, 1);
11057 rte_eth_linkstatus_get(dev, &link);
11059 switch (link.link_speed) {
11060 case ETH_SPEED_NUM_40G:
11061 case ETH_SPEED_NUM_25G:
11062 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11063 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11065 case ETH_SPEED_NUM_10G:
11066 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11067 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11069 case ETH_SPEED_NUM_1G:
11070 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11071 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11078 /* Set the timesync increment value. */
11079 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11080 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11082 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11083 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11084 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11086 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11087 adapter->systime_tc.cc_shift = 0;
11088 adapter->systime_tc.nsec_mask = 0;
11090 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11091 adapter->rx_tstamp_tc.cc_shift = 0;
11092 adapter->rx_tstamp_tc.nsec_mask = 0;
11094 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11095 adapter->tx_tstamp_tc.cc_shift = 0;
11096 adapter->tx_tstamp_tc.nsec_mask = 0;
11100 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11102 struct i40e_adapter *adapter = dev->data->dev_private;
11104 adapter->systime_tc.nsec += delta;
11105 adapter->rx_tstamp_tc.nsec += delta;
11106 adapter->tx_tstamp_tc.nsec += delta;
11112 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11115 struct i40e_adapter *adapter = dev->data->dev_private;
11117 ns = rte_timespec_to_ns(ts);
11119 /* Set the timecounters to a new value. */
11120 adapter->systime_tc.nsec = ns;
11121 adapter->rx_tstamp_tc.nsec = ns;
11122 adapter->tx_tstamp_tc.nsec = ns;
11128 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11130 uint64_t ns, systime_cycles;
11131 struct i40e_adapter *adapter = dev->data->dev_private;
11133 systime_cycles = i40e_read_systime_cyclecounter(dev);
11134 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11135 *ts = rte_ns_to_timespec(ns);
11141 i40e_timesync_enable(struct rte_eth_dev *dev)
11143 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11144 uint32_t tsync_ctl_l;
11145 uint32_t tsync_ctl_h;
11147 /* Stop the timesync system time. */
11148 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11149 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11150 /* Reset the timesync system time value. */
11151 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11152 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11154 i40e_start_timecounters(dev);
11156 /* Clear timesync registers. */
11157 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11158 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11159 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11160 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11161 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11162 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11164 /* Enable timestamping of PTP packets. */
11165 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11166 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11168 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11169 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11170 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11172 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11173 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11179 i40e_timesync_disable(struct rte_eth_dev *dev)
11181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11182 uint32_t tsync_ctl_l;
11183 uint32_t tsync_ctl_h;
11185 /* Disable timestamping of transmitted PTP packets. */
11186 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11187 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11189 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11190 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11192 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11193 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11195 /* Reset the timesync increment value. */
11196 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11197 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11203 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11204 struct timespec *timestamp, uint32_t flags)
11206 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11207 struct i40e_adapter *adapter = dev->data->dev_private;
11208 uint32_t sync_status;
11209 uint32_t index = flags & 0x03;
11210 uint64_t rx_tstamp_cycles;
11213 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11214 if ((sync_status & (1 << index)) == 0)
11217 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11218 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11219 *timestamp = rte_ns_to_timespec(ns);
11225 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11226 struct timespec *timestamp)
11228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11229 struct i40e_adapter *adapter = dev->data->dev_private;
11230 uint32_t sync_status;
11231 uint64_t tx_tstamp_cycles;
11234 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11235 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11238 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11239 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11240 *timestamp = rte_ns_to_timespec(ns);
11246 * i40e_parse_dcb_configure - parse dcb configure from user
11247 * @dev: the device being configured
11248 * @dcb_cfg: pointer of the result of parse
11249 * @*tc_map: bit map of enabled traffic classes
11251 * Returns 0 on success, negative value on failure
11254 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11255 struct i40e_dcbx_config *dcb_cfg,
11258 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11259 uint8_t i, tc_bw, bw_lf;
11261 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11263 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11264 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11265 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11269 /* assume each tc has the same bw */
11270 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11271 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11272 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11273 /* to ensure the sum of tcbw is equal to 100 */
11274 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11275 for (i = 0; i < bw_lf; i++)
11276 dcb_cfg->etscfg.tcbwtable[i]++;
11278 /* assume each tc has the same Transmission Selection Algorithm */
11279 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11280 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11282 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11283 dcb_cfg->etscfg.prioritytable[i] =
11284 dcb_rx_conf->dcb_tc[i];
11286 /* FW needs one App to configure HW */
11287 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11288 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11289 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11290 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11292 if (dcb_rx_conf->nb_tcs == 0)
11293 *tc_map = 1; /* tc0 only */
11295 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11297 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11298 dcb_cfg->pfc.willing = 0;
11299 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11300 dcb_cfg->pfc.pfcenable = *tc_map;
11306 static enum i40e_status_code
11307 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11308 struct i40e_aqc_vsi_properties_data *info,
11309 uint8_t enabled_tcmap)
11311 enum i40e_status_code ret;
11312 int i, total_tc = 0;
11313 uint16_t qpnum_per_tc, bsf, qp_idx;
11314 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11315 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11316 uint16_t used_queues;
11318 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11319 if (ret != I40E_SUCCESS)
11322 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11323 if (enabled_tcmap & (1 << i))
11328 vsi->enabled_tc = enabled_tcmap;
11330 /* different VSI has different queues assigned */
11331 if (vsi->type == I40E_VSI_MAIN)
11332 used_queues = dev_data->nb_rx_queues -
11333 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11334 else if (vsi->type == I40E_VSI_VMDQ2)
11335 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11337 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11338 return I40E_ERR_NO_AVAILABLE_VSI;
11341 qpnum_per_tc = used_queues / total_tc;
11342 /* Number of queues per enabled TC */
11343 if (qpnum_per_tc == 0) {
11344 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11345 return I40E_ERR_INVALID_QP_ID;
11347 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11348 I40E_MAX_Q_PER_TC);
11349 bsf = rte_bsf32(qpnum_per_tc);
11352 * Configure TC and queue mapping parameters, for enabled TC,
11353 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11354 * default queue will serve it.
11357 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11358 if (vsi->enabled_tc & (1 << i)) {
11359 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11360 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11361 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11362 qp_idx += qpnum_per_tc;
11364 info->tc_mapping[i] = 0;
11367 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11368 if (vsi->type == I40E_VSI_SRIOV) {
11369 info->mapping_flags |=
11370 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11371 for (i = 0; i < vsi->nb_qps; i++)
11372 info->queue_mapping[i] =
11373 rte_cpu_to_le_16(vsi->base_queue + i);
11375 info->mapping_flags |=
11376 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11377 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11379 info->valid_sections |=
11380 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11382 return I40E_SUCCESS;
11386 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11387 * @veb: VEB to be configured
11388 * @tc_map: enabled TC bitmap
11390 * Returns 0 on success, negative value on failure
11392 static enum i40e_status_code
11393 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11395 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11396 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11397 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11398 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11399 enum i40e_status_code ret = I40E_SUCCESS;
11403 /* Check if enabled_tc is same as existing or new TCs */
11404 if (veb->enabled_tc == tc_map)
11407 /* configure tc bandwidth */
11408 memset(&veb_bw, 0, sizeof(veb_bw));
11409 veb_bw.tc_valid_bits = tc_map;
11410 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11411 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11412 if (tc_map & BIT_ULL(i))
11413 veb_bw.tc_bw_share_credits[i] = 1;
11415 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11419 "AQ command Config switch_comp BW allocation per TC failed = %d",
11420 hw->aq.asq_last_status);
11424 memset(&ets_query, 0, sizeof(ets_query));
11425 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11427 if (ret != I40E_SUCCESS) {
11429 "Failed to get switch_comp ETS configuration %u",
11430 hw->aq.asq_last_status);
11433 memset(&bw_query, 0, sizeof(bw_query));
11434 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11436 if (ret != I40E_SUCCESS) {
11438 "Failed to get switch_comp bandwidth configuration %u",
11439 hw->aq.asq_last_status);
11443 /* store and print out BW info */
11444 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11445 veb->bw_info.bw_max = ets_query.tc_bw_max;
11446 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11447 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11448 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11449 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11450 I40E_16_BIT_WIDTH);
11451 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11452 veb->bw_info.bw_ets_share_credits[i] =
11453 bw_query.tc_bw_share_credits[i];
11454 veb->bw_info.bw_ets_credits[i] =
11455 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11456 /* 4 bits per TC, 4th bit is reserved */
11457 veb->bw_info.bw_ets_max[i] =
11458 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11459 RTE_LEN2MASK(3, uint8_t));
11460 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11461 veb->bw_info.bw_ets_share_credits[i]);
11462 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11463 veb->bw_info.bw_ets_credits[i]);
11464 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11465 veb->bw_info.bw_ets_max[i]);
11468 veb->enabled_tc = tc_map;
11475 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11476 * @vsi: VSI to be configured
11477 * @tc_map: enabled TC bitmap
11479 * Returns 0 on success, negative value on failure
11481 static enum i40e_status_code
11482 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11484 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11485 struct i40e_vsi_context ctxt;
11486 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11487 enum i40e_status_code ret = I40E_SUCCESS;
11490 /* Check if enabled_tc is same as existing or new TCs */
11491 if (vsi->enabled_tc == tc_map)
11494 /* configure tc bandwidth */
11495 memset(&bw_data, 0, sizeof(bw_data));
11496 bw_data.tc_valid_bits = tc_map;
11497 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11498 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11499 if (tc_map & BIT_ULL(i))
11500 bw_data.tc_bw_credits[i] = 1;
11502 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11505 "AQ command Config VSI BW allocation per TC failed = %d",
11506 hw->aq.asq_last_status);
11509 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11510 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11512 /* Update Queue Pairs Mapping for currently enabled UPs */
11513 ctxt.seid = vsi->seid;
11514 ctxt.pf_num = hw->pf_id;
11516 ctxt.uplink_seid = vsi->uplink_seid;
11517 ctxt.info = vsi->info;
11519 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11523 /* Update the VSI after updating the VSI queue-mapping information */
11524 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11526 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11527 hw->aq.asq_last_status);
11530 /* update the local VSI info with updated queue map */
11531 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11532 sizeof(vsi->info.tc_mapping));
11533 rte_memcpy(&vsi->info.queue_mapping,
11534 &ctxt.info.queue_mapping,
11535 sizeof(vsi->info.queue_mapping));
11536 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11537 vsi->info.valid_sections = 0;
11539 /* query and update current VSI BW information */
11540 ret = i40e_vsi_get_bw_config(vsi);
11543 "Failed updating vsi bw info, err %s aq_err %s",
11544 i40e_stat_str(hw, ret),
11545 i40e_aq_str(hw, hw->aq.asq_last_status));
11549 vsi->enabled_tc = tc_map;
11556 * i40e_dcb_hw_configure - program the dcb setting to hw
11557 * @pf: pf the configuration is taken on
11558 * @new_cfg: new configuration
11559 * @tc_map: enabled TC bitmap
11561 * Returns 0 on success, negative value on failure
11563 static enum i40e_status_code
11564 i40e_dcb_hw_configure(struct i40e_pf *pf,
11565 struct i40e_dcbx_config *new_cfg,
11568 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11569 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11570 struct i40e_vsi *main_vsi = pf->main_vsi;
11571 struct i40e_vsi_list *vsi_list;
11572 enum i40e_status_code ret;
11576 /* Use the FW API if FW > v4.4*/
11577 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11578 (hw->aq.fw_maj_ver >= 5))) {
11580 "FW < v4.4, can not use FW LLDP API to configure DCB");
11581 return I40E_ERR_FIRMWARE_API_VERSION;
11584 /* Check if need reconfiguration */
11585 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11586 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11587 return I40E_SUCCESS;
11590 /* Copy the new config to the current config */
11591 *old_cfg = *new_cfg;
11592 old_cfg->etsrec = old_cfg->etscfg;
11593 ret = i40e_set_dcb_config(hw);
11595 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11596 i40e_stat_str(hw, ret),
11597 i40e_aq_str(hw, hw->aq.asq_last_status));
11600 /* set receive Arbiter to RR mode and ETS scheme by default */
11601 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11602 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11603 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11604 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11605 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11606 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11607 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11608 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11609 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11610 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11611 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11612 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11613 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11615 /* get local mib to check whether it is configured correctly */
11617 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11618 /* Get Local DCB Config */
11619 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11620 &hw->local_dcbx_config);
11622 /* if Veb is created, need to update TC of it at first */
11623 if (main_vsi->veb) {
11624 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11626 PMD_INIT_LOG(WARNING,
11627 "Failed configuring TC for VEB seid=%d",
11628 main_vsi->veb->seid);
11630 /* Update each VSI */
11631 i40e_vsi_config_tc(main_vsi, tc_map);
11632 if (main_vsi->veb) {
11633 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11634 /* Beside main VSI and VMDQ VSIs, only enable default
11635 * TC for other VSIs
11637 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11638 ret = i40e_vsi_config_tc(vsi_list->vsi,
11641 ret = i40e_vsi_config_tc(vsi_list->vsi,
11642 I40E_DEFAULT_TCMAP);
11644 PMD_INIT_LOG(WARNING,
11645 "Failed configuring TC for VSI seid=%d",
11646 vsi_list->vsi->seid);
11650 return I40E_SUCCESS;
11654 * i40e_dcb_init_configure - initial dcb config
11655 * @dev: device being configured
11656 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11658 * Returns 0 on success, negative value on failure
11661 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11663 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11667 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11668 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11672 /* DCB initialization:
11673 * Update DCB configuration from the Firmware and configure
11674 * LLDP MIB change event.
11676 if (sw_dcb == TRUE) {
11677 /* Stopping lldp is necessary for DPDK, but it will cause
11678 * DCB init failed. For i40e_init_dcb(), the prerequisite
11679 * for successful initialization of DCB is that LLDP is
11680 * enabled. So it is needed to start lldp before DCB init
11681 * and stop it after initialization.
11683 ret = i40e_aq_start_lldp(hw, true, NULL);
11684 if (ret != I40E_SUCCESS)
11685 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11687 ret = i40e_init_dcb(hw, true);
11688 /* If lldp agent is stopped, the return value from
11689 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11690 * adminq status. Otherwise, it should return success.
11692 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11693 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11694 memset(&hw->local_dcbx_config, 0,
11695 sizeof(struct i40e_dcbx_config));
11696 /* set dcb default configuration */
11697 hw->local_dcbx_config.etscfg.willing = 0;
11698 hw->local_dcbx_config.etscfg.maxtcs = 0;
11699 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11700 hw->local_dcbx_config.etscfg.tsatable[0] =
11702 /* all UPs mapping to TC0 */
11703 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11704 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11705 hw->local_dcbx_config.etsrec =
11706 hw->local_dcbx_config.etscfg;
11707 hw->local_dcbx_config.pfc.willing = 0;
11708 hw->local_dcbx_config.pfc.pfccap =
11709 I40E_MAX_TRAFFIC_CLASS;
11710 /* FW needs one App to configure HW */
11711 hw->local_dcbx_config.numapps = 1;
11712 hw->local_dcbx_config.app[0].selector =
11713 I40E_APP_SEL_ETHTYPE;
11714 hw->local_dcbx_config.app[0].priority = 3;
11715 hw->local_dcbx_config.app[0].protocolid =
11716 I40E_APP_PROTOID_FCOE;
11717 ret = i40e_set_dcb_config(hw);
11720 "default dcb config fails. err = %d, aq_err = %d.",
11721 ret, hw->aq.asq_last_status);
11726 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11727 ret, hw->aq.asq_last_status);
11731 if (i40e_need_stop_lldp(dev)) {
11732 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11733 if (ret != I40E_SUCCESS)
11734 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11737 ret = i40e_aq_start_lldp(hw, true, NULL);
11738 if (ret != I40E_SUCCESS)
11739 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11741 ret = i40e_init_dcb(hw, true);
11743 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11745 "HW doesn't support DCBX offload.");
11750 "DCBX configuration failed, err = %d, aq_err = %d.",
11751 ret, hw->aq.asq_last_status);
11759 * i40e_dcb_setup - setup dcb related config
11760 * @dev: device being configured
11762 * Returns 0 on success, negative value on failure
11765 i40e_dcb_setup(struct rte_eth_dev *dev)
11767 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11768 struct i40e_dcbx_config dcb_cfg;
11769 uint8_t tc_map = 0;
11772 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11773 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11777 if (pf->vf_num != 0)
11778 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11780 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11782 PMD_INIT_LOG(ERR, "invalid dcb config");
11785 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11787 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11795 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11796 struct rte_eth_dcb_info *dcb_info)
11798 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11800 struct i40e_vsi *vsi = pf->main_vsi;
11801 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11802 uint16_t bsf, tc_mapping;
11805 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11806 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11808 dcb_info->nb_tcs = 1;
11809 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11810 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11811 for (i = 0; i < dcb_info->nb_tcs; i++)
11812 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11814 /* get queue mapping if vmdq is disabled */
11815 if (!pf->nb_cfg_vmdq_vsi) {
11816 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11817 if (!(vsi->enabled_tc & (1 << i)))
11819 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11820 dcb_info->tc_queue.tc_rxq[j][i].base =
11821 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11822 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11823 dcb_info->tc_queue.tc_txq[j][i].base =
11824 dcb_info->tc_queue.tc_rxq[j][i].base;
11825 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11826 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11827 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11828 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11829 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11834 /* get queue mapping if vmdq is enabled */
11836 vsi = pf->vmdq[j].vsi;
11837 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11838 if (!(vsi->enabled_tc & (1 << i)))
11840 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11841 dcb_info->tc_queue.tc_rxq[j][i].base =
11842 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11843 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11844 dcb_info->tc_queue.tc_txq[j][i].base =
11845 dcb_info->tc_queue.tc_rxq[j][i].base;
11846 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11847 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11848 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11849 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11850 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11853 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11858 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11860 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11861 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11862 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11863 uint16_t msix_intr;
11865 msix_intr = intr_handle->intr_vec[queue_id];
11866 if (msix_intr == I40E_MISC_VEC_ID)
11867 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11868 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11869 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11870 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11873 I40E_PFINT_DYN_CTLN(msix_intr -
11874 I40E_RX_VEC_START),
11875 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11876 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11877 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11879 I40E_WRITE_FLUSH(hw);
11880 rte_intr_ack(&pci_dev->intr_handle);
11886 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11888 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11889 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11891 uint16_t msix_intr;
11893 msix_intr = intr_handle->intr_vec[queue_id];
11894 if (msix_intr == I40E_MISC_VEC_ID)
11895 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11896 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11899 I40E_PFINT_DYN_CTLN(msix_intr -
11900 I40E_RX_VEC_START),
11901 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11902 I40E_WRITE_FLUSH(hw);
11908 * This function is used to check if the register is valid.
11909 * Below is the valid registers list for X722 only:
11913 * 0x208e00--0x209000
11914 * 0x20be00--0x20c000
11915 * 0x263c00--0x264000
11916 * 0x265c00--0x266000
11918 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11920 if ((type != I40E_MAC_X722) &&
11921 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11922 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11923 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11924 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11925 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11926 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11927 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11933 static int i40e_get_regs(struct rte_eth_dev *dev,
11934 struct rte_dev_reg_info *regs)
11936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11937 uint32_t *ptr_data = regs->data;
11938 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11939 const struct i40e_reg_info *reg_info;
11941 if (ptr_data == NULL) {
11942 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11943 regs->width = sizeof(uint32_t);
11947 /* The first few registers have to be read using AQ operations */
11949 while (i40e_regs_adminq[reg_idx].name) {
11950 reg_info = &i40e_regs_adminq[reg_idx++];
11951 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11953 arr_idx2 <= reg_info->count2;
11955 reg_offset = arr_idx * reg_info->stride1 +
11956 arr_idx2 * reg_info->stride2;
11957 reg_offset += reg_info->base_addr;
11958 ptr_data[reg_offset >> 2] =
11959 i40e_read_rx_ctl(hw, reg_offset);
11963 /* The remaining registers can be read using primitives */
11965 while (i40e_regs_others[reg_idx].name) {
11966 reg_info = &i40e_regs_others[reg_idx++];
11967 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11969 arr_idx2 <= reg_info->count2;
11971 reg_offset = arr_idx * reg_info->stride1 +
11972 arr_idx2 * reg_info->stride2;
11973 reg_offset += reg_info->base_addr;
11974 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11975 ptr_data[reg_offset >> 2] = 0;
11977 ptr_data[reg_offset >> 2] =
11978 I40E_READ_REG(hw, reg_offset);
11985 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11987 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11989 /* Convert word count to byte count */
11990 return hw->nvm.sr_size << 1;
11993 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11994 struct rte_dev_eeprom_info *eeprom)
11996 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11997 uint16_t *data = eeprom->data;
11998 uint16_t offset, length, cnt_words;
12001 offset = eeprom->offset >> 1;
12002 length = eeprom->length >> 1;
12003 cnt_words = length;
12005 if (offset > hw->nvm.sr_size ||
12006 offset + length > hw->nvm.sr_size) {
12007 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12011 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12013 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12014 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12015 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12022 static int i40e_get_module_info(struct rte_eth_dev *dev,
12023 struct rte_eth_dev_module_info *modinfo)
12025 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12026 uint32_t sff8472_comp = 0;
12027 uint32_t sff8472_swap = 0;
12028 uint32_t sff8636_rev = 0;
12029 i40e_status status;
12032 /* Check if firmware supports reading module EEPROM. */
12033 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12035 "Module EEPROM memory read not supported. "
12036 "Please update the NVM image.\n");
12040 status = i40e_update_link_info(hw);
12044 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12046 "Cannot read module EEPROM memory. "
12047 "No module connected.\n");
12051 type = hw->phy.link_info.module_type[0];
12054 case I40E_MODULE_TYPE_SFP:
12055 status = i40e_aq_get_phy_register(hw,
12056 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12057 I40E_I2C_EEPROM_DEV_ADDR, 1,
12058 I40E_MODULE_SFF_8472_COMP,
12059 &sff8472_comp, NULL);
12063 status = i40e_aq_get_phy_register(hw,
12064 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12065 I40E_I2C_EEPROM_DEV_ADDR, 1,
12066 I40E_MODULE_SFF_8472_SWAP,
12067 &sff8472_swap, NULL);
12071 /* Check if the module requires address swap to access
12072 * the other EEPROM memory page.
12074 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12075 PMD_DRV_LOG(WARNING,
12076 "Module address swap to access "
12077 "page 0xA2 is not supported.\n");
12078 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12079 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12080 } else if (sff8472_comp == 0x00) {
12081 /* Module is not SFF-8472 compliant */
12082 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12083 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12085 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12086 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12089 case I40E_MODULE_TYPE_QSFP_PLUS:
12090 /* Read from memory page 0. */
12091 status = i40e_aq_get_phy_register(hw,
12092 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12094 I40E_MODULE_REVISION_ADDR,
12095 &sff8636_rev, NULL);
12098 /* Determine revision compliance byte */
12099 if (sff8636_rev > 0x02) {
12100 /* Module is SFF-8636 compliant */
12101 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12102 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12104 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12105 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12108 case I40E_MODULE_TYPE_QSFP28:
12109 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12110 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12113 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12119 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12120 struct rte_dev_eeprom_info *info)
12122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12123 bool is_sfp = false;
12124 i40e_status status;
12126 uint32_t value = 0;
12129 if (!info || !info->length || !info->data)
12132 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12136 for (i = 0; i < info->length; i++) {
12137 u32 offset = i + info->offset;
12138 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12140 /* Check if we need to access the other memory page */
12142 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12143 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12144 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12147 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12148 /* Compute memory page number and offset. */
12149 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12153 status = i40e_aq_get_phy_register(hw,
12154 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12155 addr, offset, 1, &value, NULL);
12158 data[i] = (uint8_t)value;
12163 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12164 struct rte_ether_addr *mac_addr)
12166 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12167 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12168 struct i40e_vsi *vsi = pf->main_vsi;
12169 struct i40e_mac_filter_info mac_filter;
12170 struct i40e_mac_filter *f;
12173 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12174 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12178 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12179 if (rte_is_same_ether_addr(&pf->dev_addr,
12180 &f->mac_info.mac_addr))
12185 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12189 mac_filter = f->mac_info;
12190 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12191 if (ret != I40E_SUCCESS) {
12192 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12195 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12196 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12197 if (ret != I40E_SUCCESS) {
12198 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12201 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12203 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12204 mac_addr->addr_bytes, NULL);
12205 if (ret != I40E_SUCCESS) {
12206 PMD_DRV_LOG(ERR, "Failed to change mac");
12214 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12216 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12217 struct rte_eth_dev_data *dev_data = pf->dev_data;
12218 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12221 /* check if mtu is within the allowed range */
12222 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12225 /* mtu setting is forbidden if port is start */
12226 if (dev_data->dev_started) {
12227 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12228 dev_data->port_id);
12232 if (frame_size > RTE_ETHER_MAX_LEN)
12233 dev_data->dev_conf.rxmode.offloads |=
12234 DEV_RX_OFFLOAD_JUMBO_FRAME;
12236 dev_data->dev_conf.rxmode.offloads &=
12237 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12239 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12244 /* Restore ethertype filter */
12246 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12248 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12249 struct i40e_ethertype_filter_list
12250 *ethertype_list = &pf->ethertype.ethertype_list;
12251 struct i40e_ethertype_filter *f;
12252 struct i40e_control_filter_stats stats;
12255 TAILQ_FOREACH(f, ethertype_list, rules) {
12257 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12258 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12259 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12260 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12261 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12263 memset(&stats, 0, sizeof(stats));
12264 i40e_aq_add_rem_control_packet_filter(hw,
12265 f->input.mac_addr.addr_bytes,
12266 f->input.ether_type,
12267 flags, pf->main_vsi->seid,
12268 f->queue, 1, &stats, NULL);
12270 PMD_DRV_LOG(INFO, "Ethertype filter:"
12271 " mac_etype_used = %u, etype_used = %u,"
12272 " mac_etype_free = %u, etype_free = %u",
12273 stats.mac_etype_used, stats.etype_used,
12274 stats.mac_etype_free, stats.etype_free);
12277 /* Restore tunnel filter */
12279 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12281 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12282 struct i40e_vsi *vsi;
12283 struct i40e_pf_vf *vf;
12284 struct i40e_tunnel_filter_list
12285 *tunnel_list = &pf->tunnel.tunnel_list;
12286 struct i40e_tunnel_filter *f;
12287 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12288 bool big_buffer = 0;
12290 TAILQ_FOREACH(f, tunnel_list, rules) {
12292 vsi = pf->main_vsi;
12294 vf = &pf->vfs[f->vf_id];
12297 memset(&cld_filter, 0, sizeof(cld_filter));
12298 rte_ether_addr_copy((struct rte_ether_addr *)
12299 &f->input.outer_mac,
12300 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12301 rte_ether_addr_copy((struct rte_ether_addr *)
12302 &f->input.inner_mac,
12303 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12304 cld_filter.element.inner_vlan = f->input.inner_vlan;
12305 cld_filter.element.flags = f->input.flags;
12306 cld_filter.element.tenant_id = f->input.tenant_id;
12307 cld_filter.element.queue_number = f->queue;
12308 rte_memcpy(cld_filter.general_fields,
12309 f->input.general_fields,
12310 sizeof(f->input.general_fields));
12312 if (((f->input.flags &
12313 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12314 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12316 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12317 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12319 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12320 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12324 i40e_aq_add_cloud_filters_bb(hw,
12325 vsi->seid, &cld_filter, 1);
12327 i40e_aq_add_cloud_filters(hw, vsi->seid,
12328 &cld_filter.element, 1);
12332 /* Restore rss filter */
12334 i40e_rss_filter_restore(struct i40e_pf *pf)
12336 struct i40e_rte_flow_rss_conf *conf =
12338 if (conf->conf.queue_num)
12339 i40e_config_rss_filter(pf, conf, TRUE);
12343 i40e_filter_restore(struct i40e_pf *pf)
12345 i40e_ethertype_filter_restore(pf);
12346 i40e_tunnel_filter_restore(pf);
12347 i40e_fdir_filter_restore(pf);
12348 i40e_rss_filter_restore(pf);
12352 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12354 if (strcmp(dev->device->driver->name, drv->driver.name))
12361 is_i40e_supported(struct rte_eth_dev *dev)
12363 return is_device_supported(dev, &rte_i40e_pmd);
12366 struct i40e_customized_pctype*
12367 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12371 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12372 if (pf->customized_pctype[i].index == index)
12373 return &pf->customized_pctype[i];
12379 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12380 uint32_t pkg_size, uint32_t proto_num,
12381 struct rte_pmd_i40e_proto_info *proto,
12382 enum rte_pmd_i40e_package_op op)
12384 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12385 uint32_t pctype_num;
12386 struct rte_pmd_i40e_ptype_info *pctype;
12387 uint32_t buff_size;
12388 struct i40e_customized_pctype *new_pctype = NULL;
12390 uint8_t pctype_value;
12395 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12396 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12397 PMD_DRV_LOG(ERR, "Unsupported operation.");
12401 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12402 (uint8_t *)&pctype_num, sizeof(pctype_num),
12403 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12405 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12409 PMD_DRV_LOG(INFO, "No new pctype added");
12413 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12414 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12416 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12419 /* get information about new pctype list */
12420 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12421 (uint8_t *)pctype, buff_size,
12422 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12424 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12429 /* Update customized pctype. */
12430 for (i = 0; i < pctype_num; i++) {
12431 pctype_value = pctype[i].ptype_id;
12432 memset(name, 0, sizeof(name));
12433 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12434 proto_id = pctype[i].protocols[j];
12435 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12437 for (n = 0; n < proto_num; n++) {
12438 if (proto[n].proto_id != proto_id)
12440 strlcat(name, proto[n].name, sizeof(name));
12441 strlcat(name, "_", sizeof(name));
12445 name[strlen(name) - 1] = '\0';
12446 PMD_DRV_LOG(INFO, "name = %s\n", name);
12447 if (!strcmp(name, "GTPC"))
12449 i40e_find_customized_pctype(pf,
12450 I40E_CUSTOMIZED_GTPC);
12451 else if (!strcmp(name, "GTPU_IPV4"))
12453 i40e_find_customized_pctype(pf,
12454 I40E_CUSTOMIZED_GTPU_IPV4);
12455 else if (!strcmp(name, "GTPU_IPV6"))
12457 i40e_find_customized_pctype(pf,
12458 I40E_CUSTOMIZED_GTPU_IPV6);
12459 else if (!strcmp(name, "GTPU"))
12461 i40e_find_customized_pctype(pf,
12462 I40E_CUSTOMIZED_GTPU);
12463 else if (!strcmp(name, "IPV4_L2TPV3"))
12465 i40e_find_customized_pctype(pf,
12466 I40E_CUSTOMIZED_IPV4_L2TPV3);
12467 else if (!strcmp(name, "IPV6_L2TPV3"))
12469 i40e_find_customized_pctype(pf,
12470 I40E_CUSTOMIZED_IPV6_L2TPV3);
12471 else if (!strcmp(name, "IPV4_ESP"))
12473 i40e_find_customized_pctype(pf,
12474 I40E_CUSTOMIZED_ESP_IPV4);
12475 else if (!strcmp(name, "IPV6_ESP"))
12477 i40e_find_customized_pctype(pf,
12478 I40E_CUSTOMIZED_ESP_IPV6);
12479 else if (!strcmp(name, "IPV4_UDP_ESP"))
12481 i40e_find_customized_pctype(pf,
12482 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12483 else if (!strcmp(name, "IPV6_UDP_ESP"))
12485 i40e_find_customized_pctype(pf,
12486 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12487 else if (!strcmp(name, "IPV4_AH"))
12489 i40e_find_customized_pctype(pf,
12490 I40E_CUSTOMIZED_AH_IPV4);
12491 else if (!strcmp(name, "IPV6_AH"))
12493 i40e_find_customized_pctype(pf,
12494 I40E_CUSTOMIZED_AH_IPV6);
12496 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12497 new_pctype->pctype = pctype_value;
12498 new_pctype->valid = true;
12500 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12501 new_pctype->valid = false;
12511 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12512 uint32_t pkg_size, uint32_t proto_num,
12513 struct rte_pmd_i40e_proto_info *proto,
12514 enum rte_pmd_i40e_package_op op)
12516 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12517 uint16_t port_id = dev->data->port_id;
12518 uint32_t ptype_num;
12519 struct rte_pmd_i40e_ptype_info *ptype;
12520 uint32_t buff_size;
12522 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12527 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12528 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12529 PMD_DRV_LOG(ERR, "Unsupported operation.");
12533 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12534 rte_pmd_i40e_ptype_mapping_reset(port_id);
12538 /* get information about new ptype num */
12539 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12540 (uint8_t *)&ptype_num, sizeof(ptype_num),
12541 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12543 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12547 PMD_DRV_LOG(INFO, "No new ptype added");
12551 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12552 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12554 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12558 /* get information about new ptype list */
12559 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12560 (uint8_t *)ptype, buff_size,
12561 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12563 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12568 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12569 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12570 if (!ptype_mapping) {
12571 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12576 /* Update ptype mapping table. */
12577 for (i = 0; i < ptype_num; i++) {
12578 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12579 ptype_mapping[i].sw_ptype = 0;
12581 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12582 proto_id = ptype[i].protocols[j];
12583 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12585 for (n = 0; n < proto_num; n++) {
12586 if (proto[n].proto_id != proto_id)
12588 memset(name, 0, sizeof(name));
12589 strcpy(name, proto[n].name);
12590 PMD_DRV_LOG(INFO, "name = %s\n", name);
12591 if (!strncasecmp(name, "PPPOE", 5))
12592 ptype_mapping[i].sw_ptype |=
12593 RTE_PTYPE_L2_ETHER_PPPOE;
12594 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12596 ptype_mapping[i].sw_ptype |=
12597 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12598 ptype_mapping[i].sw_ptype |=
12600 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12602 ptype_mapping[i].sw_ptype |=
12603 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12604 ptype_mapping[i].sw_ptype |=
12605 RTE_PTYPE_INNER_L4_FRAG;
12606 } else if (!strncasecmp(name, "OIPV4", 5)) {
12607 ptype_mapping[i].sw_ptype |=
12608 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12610 } else if (!strncasecmp(name, "IPV4", 4) &&
12612 ptype_mapping[i].sw_ptype |=
12613 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12614 else if (!strncasecmp(name, "IPV4", 4) &&
12616 ptype_mapping[i].sw_ptype |=
12617 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12618 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12620 ptype_mapping[i].sw_ptype |=
12621 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12622 ptype_mapping[i].sw_ptype |=
12624 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12626 ptype_mapping[i].sw_ptype |=
12627 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12628 ptype_mapping[i].sw_ptype |=
12629 RTE_PTYPE_INNER_L4_FRAG;
12630 } else if (!strncasecmp(name, "OIPV6", 5)) {
12631 ptype_mapping[i].sw_ptype |=
12632 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12634 } else if (!strncasecmp(name, "IPV6", 4) &&
12636 ptype_mapping[i].sw_ptype |=
12637 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12638 else if (!strncasecmp(name, "IPV6", 4) &&
12640 ptype_mapping[i].sw_ptype |=
12641 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12642 else if (!strncasecmp(name, "UDP", 3) &&
12644 ptype_mapping[i].sw_ptype |=
12646 else if (!strncasecmp(name, "UDP", 3) &&
12648 ptype_mapping[i].sw_ptype |=
12649 RTE_PTYPE_INNER_L4_UDP;
12650 else if (!strncasecmp(name, "TCP", 3) &&
12652 ptype_mapping[i].sw_ptype |=
12654 else if (!strncasecmp(name, "TCP", 3) &&
12656 ptype_mapping[i].sw_ptype |=
12657 RTE_PTYPE_INNER_L4_TCP;
12658 else if (!strncasecmp(name, "SCTP", 4) &&
12660 ptype_mapping[i].sw_ptype |=
12662 else if (!strncasecmp(name, "SCTP", 4) &&
12664 ptype_mapping[i].sw_ptype |=
12665 RTE_PTYPE_INNER_L4_SCTP;
12666 else if ((!strncasecmp(name, "ICMP", 4) ||
12667 !strncasecmp(name, "ICMPV6", 6)) &&
12669 ptype_mapping[i].sw_ptype |=
12671 else if ((!strncasecmp(name, "ICMP", 4) ||
12672 !strncasecmp(name, "ICMPV6", 6)) &&
12674 ptype_mapping[i].sw_ptype |=
12675 RTE_PTYPE_INNER_L4_ICMP;
12676 else if (!strncasecmp(name, "GTPC", 4)) {
12677 ptype_mapping[i].sw_ptype |=
12678 RTE_PTYPE_TUNNEL_GTPC;
12680 } else if (!strncasecmp(name, "GTPU", 4)) {
12681 ptype_mapping[i].sw_ptype |=
12682 RTE_PTYPE_TUNNEL_GTPU;
12684 } else if (!strncasecmp(name, "ESP", 3)) {
12685 ptype_mapping[i].sw_ptype |=
12686 RTE_PTYPE_TUNNEL_ESP;
12688 } else if (!strncasecmp(name, "GRENAT", 6)) {
12689 ptype_mapping[i].sw_ptype |=
12690 RTE_PTYPE_TUNNEL_GRENAT;
12692 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12693 !strncasecmp(name, "L2TPV2", 6) ||
12694 !strncasecmp(name, "L2TPV3", 6)) {
12695 ptype_mapping[i].sw_ptype |=
12696 RTE_PTYPE_TUNNEL_L2TP;
12705 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12708 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12710 rte_free(ptype_mapping);
12716 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12717 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12720 uint32_t proto_num;
12721 struct rte_pmd_i40e_proto_info *proto;
12722 uint32_t buff_size;
12726 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12727 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12728 PMD_DRV_LOG(ERR, "Unsupported operation.");
12732 /* get information about protocol number */
12733 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12734 (uint8_t *)&proto_num, sizeof(proto_num),
12735 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12737 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12741 PMD_DRV_LOG(INFO, "No new protocol added");
12745 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12746 proto = rte_zmalloc("new_proto", buff_size, 0);
12748 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12752 /* get information about protocol list */
12753 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12754 (uint8_t *)proto, buff_size,
12755 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12757 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12762 /* Check if GTP is supported. */
12763 for (i = 0; i < proto_num; i++) {
12764 if (!strncmp(proto[i].name, "GTP", 3)) {
12765 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12766 pf->gtp_support = true;
12768 pf->gtp_support = false;
12773 /* Check if ESP is supported. */
12774 for (i = 0; i < proto_num; i++) {
12775 if (!strncmp(proto[i].name, "ESP", 3)) {
12776 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12777 pf->esp_support = true;
12779 pf->esp_support = false;
12784 /* Update customized pctype info */
12785 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12786 proto_num, proto, op);
12788 PMD_DRV_LOG(INFO, "No pctype is updated.");
12790 /* Update customized ptype info */
12791 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12792 proto_num, proto, op);
12794 PMD_DRV_LOG(INFO, "No ptype is updated.");
12799 /* Create a QinQ cloud filter
12801 * The Fortville NIC has limited resources for tunnel filters,
12802 * so we can only reuse existing filters.
12804 * In step 1 we define which Field Vector fields can be used for
12806 * As we do not have the inner tag defined as a field,
12807 * we have to define it first, by reusing one of L1 entries.
12809 * In step 2 we are replacing one of existing filter types with
12810 * a new one for QinQ.
12811 * As we reusing L1 and replacing L2, some of the default filter
12812 * types will disappear,which depends on L1 and L2 entries we reuse.
12814 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12816 * 1. Create L1 filter of outer vlan (12b) which will be in use
12817 * later when we define the cloud filter.
12818 * a. Valid_flags.replace_cloud = 0
12819 * b. Old_filter = 10 (Stag_Inner_Vlan)
12820 * c. New_filter = 0x10
12821 * d. TR bit = 0xff (optional, not used here)
12822 * e. Buffer – 2 entries:
12823 * i. Byte 0 = 8 (outer vlan FV index).
12825 * Byte 2-3 = 0x0fff
12826 * ii. Byte 0 = 37 (inner vlan FV index).
12828 * Byte 2-3 = 0x0fff
12831 * 2. Create cloud filter using two L1 filters entries: stag and
12832 * new filter(outer vlan+ inner vlan)
12833 * a. Valid_flags.replace_cloud = 1
12834 * b. Old_filter = 1 (instead of outer IP)
12835 * c. New_filter = 0x10
12836 * d. Buffer – 2 entries:
12837 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12838 * Byte 1-3 = 0 (rsv)
12839 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12840 * Byte 9-11 = 0 (rsv)
12843 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12845 int ret = -ENOTSUP;
12846 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12847 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12848 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12849 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12851 if (pf->support_multi_driver) {
12852 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12857 memset(&filter_replace, 0,
12858 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12859 memset(&filter_replace_buf, 0,
12860 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12862 /* create L1 filter */
12863 filter_replace.old_filter_type =
12864 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12865 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12866 filter_replace.tr_bit = 0;
12868 /* Prepare the buffer, 2 entries */
12869 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12870 filter_replace_buf.data[0] |=
12871 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12872 /* Field Vector 12b mask */
12873 filter_replace_buf.data[2] = 0xff;
12874 filter_replace_buf.data[3] = 0x0f;
12875 filter_replace_buf.data[4] =
12876 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12877 filter_replace_buf.data[4] |=
12878 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12879 /* Field Vector 12b mask */
12880 filter_replace_buf.data[6] = 0xff;
12881 filter_replace_buf.data[7] = 0x0f;
12882 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12883 &filter_replace_buf);
12884 if (ret != I40E_SUCCESS)
12887 if (filter_replace.old_filter_type !=
12888 filter_replace.new_filter_type)
12889 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12890 " original: 0x%x, new: 0x%x",
12892 filter_replace.old_filter_type,
12893 filter_replace.new_filter_type);
12895 /* Apply the second L2 cloud filter */
12896 memset(&filter_replace, 0,
12897 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12898 memset(&filter_replace_buf, 0,
12899 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12901 /* create L2 filter, input for L2 filter will be L1 filter */
12902 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12903 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12904 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12906 /* Prepare the buffer, 2 entries */
12907 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12908 filter_replace_buf.data[0] |=
12909 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12910 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12911 filter_replace_buf.data[4] |=
12912 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12913 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12914 &filter_replace_buf);
12915 if (!ret && (filter_replace.old_filter_type !=
12916 filter_replace.new_filter_type))
12917 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12918 " original: 0x%x, new: 0x%x",
12920 filter_replace.old_filter_type,
12921 filter_replace.new_filter_type);
12927 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12928 const struct rte_flow_action_rss *in)
12930 if (in->key_len > RTE_DIM(out->key) ||
12931 in->queue_num > RTE_DIM(out->queue))
12933 if (!in->key && in->key_len)
12935 out->conf = (struct rte_flow_action_rss){
12937 .level = in->level,
12938 .types = in->types,
12939 .key_len = in->key_len,
12940 .queue_num = in->queue_num,
12941 .queue = memcpy(out->queue, in->queue,
12942 sizeof(*in->queue) * in->queue_num),
12945 out->conf.key = memcpy(out->key, in->key, in->key_len);
12950 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12951 const struct rte_flow_action_rss *with)
12953 return (comp->func == with->func &&
12954 comp->level == with->level &&
12955 comp->types == with->types &&
12956 comp->key_len == with->key_len &&
12957 comp->queue_num == with->queue_num &&
12958 !memcmp(comp->key, with->key, with->key_len) &&
12959 !memcmp(comp->queue, with->queue,
12960 sizeof(*with->queue) * with->queue_num));
12964 i40e_config_rss_filter(struct i40e_pf *pf,
12965 struct i40e_rte_flow_rss_conf *conf, bool add)
12967 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12968 uint32_t i, lut = 0;
12970 struct rte_eth_rss_conf rss_conf = {
12971 .rss_key = conf->conf.key_len ?
12972 (void *)(uintptr_t)conf->conf.key : NULL,
12973 .rss_key_len = conf->conf.key_len,
12974 .rss_hf = conf->conf.types,
12976 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12979 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12980 i40e_pf_disable_rss(pf);
12981 memset(rss_info, 0,
12982 sizeof(struct i40e_rte_flow_rss_conf));
12988 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12989 * It's necessary to calculate the actual PF queues that are configured.
12991 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12992 num = i40e_pf_calc_configured_queues_num(pf);
12994 num = pf->dev_data->nb_rx_queues;
12996 num = RTE_MIN(num, conf->conf.queue_num);
12997 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13002 "No PF queues are configured to enable RSS for port %u",
13003 pf->dev_data->port_id);
13007 /* Fill in redirection table */
13008 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13011 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13012 hw->func_caps.rss_table_entry_width) - 1));
13014 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13017 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
13018 i40e_pf_disable_rss(pf);
13021 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
13022 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13023 /* Random default keys */
13024 static uint32_t rss_key_default[] = {0x6b793944,
13025 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13026 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13027 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13029 rss_conf.rss_key = (uint8_t *)rss_key_default;
13030 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13033 "No valid RSS key config for i40e, using default\n");
13036 i40e_hw_rss_hash_set(pf, &rss_conf);
13038 if (i40e_rss_conf_init(rss_info, &conf->conf))
13044 RTE_INIT(i40e_init_log)
13046 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
13047 if (i40e_logtype_init >= 0)
13048 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
13049 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
13050 if (i40e_logtype_driver >= 0)
13051 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
13053 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13054 i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
13055 if (i40e_logtype_rx >= 0)
13056 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
13059 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13060 i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
13061 if (i40e_logtype_tx >= 0)
13062 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
13065 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13066 i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
13067 if (i40e_logtype_tx_free >= 0)
13068 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
13072 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13073 ETH_I40E_FLOATING_VEB_ARG "=1"
13074 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13075 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13076 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13077 ETH_I40E_USE_LATEST_VEC "=0|1");