4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_adminq_cmd.h"
57 #include "base/i40e_type.h"
58 #include "base/i40e_register.h"
59 #include "base/i40e_dcb.h"
60 #include "i40e_ethdev.h"
61 #include "i40e_rxtx.h"
64 /* Maximun number of MAC addresses */
65 #define I40E_NUM_MACADDR_MAX 64
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 /* Default queue interrupt throttling time in microseconds */
79 #define I40E_ITR_INDEX_DEFAULT 0
80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
81 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
143 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
144 static int i40e_dev_configure(struct rte_eth_dev *dev);
145 static int i40e_dev_start(struct rte_eth_dev *dev);
146 static void i40e_dev_stop(struct rte_eth_dev *dev);
147 static void i40e_dev_close(struct rte_eth_dev *dev);
148 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
149 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
150 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
151 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
152 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
153 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
154 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
155 struct rte_eth_stats *stats);
156 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
157 struct rte_eth_xstats *xstats, unsigned n);
158 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
159 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
160 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
164 static void i40e_dev_info_get(struct rte_eth_dev *dev,
165 struct rte_eth_dev_info *dev_info);
166 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
169 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
170 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
171 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
174 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
175 static int i40e_dev_led_on(struct rte_eth_dev *dev);
176 static int i40e_dev_led_off(struct rte_eth_dev *dev);
177 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
178 struct rte_eth_fc_conf *fc_conf);
179 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
180 struct rte_eth_fc_conf *fc_conf);
181 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
182 struct rte_eth_pfc_conf *pfc_conf);
183 static void i40e_macaddr_add(struct rte_eth_dev *dev,
184 struct ether_addr *mac_addr,
187 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
188 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
189 struct rte_eth_rss_reta_entry64 *reta_conf,
191 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
192 struct rte_eth_rss_reta_entry64 *reta_conf,
195 static int i40e_get_cap(struct i40e_hw *hw);
196 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
197 static int i40e_pf_setup(struct i40e_pf *pf);
198 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
199 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
200 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
201 static int i40e_dcb_setup(struct rte_eth_dev *dev);
202 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
203 bool offset_loaded, uint64_t *offset, uint64_t *stat);
204 static void i40e_stat_update_48(struct i40e_hw *hw,
210 static void i40e_pf_config_irq0(struct i40e_hw *hw);
211 static void i40e_dev_interrupt_handler(
212 __rte_unused struct rte_intr_handle *handle, void *param);
213 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
214 uint32_t base, uint32_t num);
215 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
216 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
218 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
220 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
221 static int i40e_veb_release(struct i40e_veb *veb);
222 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
223 struct i40e_vsi *vsi);
224 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
225 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
226 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
227 struct i40e_macvlan_filter *mv_f,
229 struct ether_addr *addr);
230 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
231 struct i40e_macvlan_filter *mv_f,
234 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
235 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
236 struct rte_eth_rss_conf *rss_conf);
237 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
238 struct rte_eth_rss_conf *rss_conf);
239 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
240 struct rte_eth_udp_tunnel *udp_tunnel);
241 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
242 struct rte_eth_udp_tunnel *udp_tunnel);
243 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
244 struct rte_eth_ethertype_filter *filter,
246 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
247 enum rte_filter_op filter_op,
249 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
250 enum rte_filter_type filter_type,
251 enum rte_filter_op filter_op,
253 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
254 struct rte_eth_dcb_info *dcb_info);
255 static void i40e_configure_registers(struct i40e_hw *hw);
256 static void i40e_hw_init(struct i40e_hw *hw);
257 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
258 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
259 struct rte_eth_mirror_conf *mirror_conf,
260 uint8_t sw_id, uint8_t on);
261 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
263 static int i40e_timesync_enable(struct rte_eth_dev *dev);
264 static int i40e_timesync_disable(struct rte_eth_dev *dev);
265 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
266 struct timespec *timestamp,
268 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
269 struct timespec *timestamp);
270 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
273 static const struct rte_pci_id pci_id_i40e_map[] = {
274 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
275 #include "rte_pci_dev_ids.h"
276 { .vendor_id = 0, /* sentinel */ },
279 static const struct eth_dev_ops i40e_eth_dev_ops = {
280 .dev_configure = i40e_dev_configure,
281 .dev_start = i40e_dev_start,
282 .dev_stop = i40e_dev_stop,
283 .dev_close = i40e_dev_close,
284 .promiscuous_enable = i40e_dev_promiscuous_enable,
285 .promiscuous_disable = i40e_dev_promiscuous_disable,
286 .allmulticast_enable = i40e_dev_allmulticast_enable,
287 .allmulticast_disable = i40e_dev_allmulticast_disable,
288 .dev_set_link_up = i40e_dev_set_link_up,
289 .dev_set_link_down = i40e_dev_set_link_down,
290 .link_update = i40e_dev_link_update,
291 .stats_get = i40e_dev_stats_get,
292 .xstats_get = i40e_dev_xstats_get,
293 .stats_reset = i40e_dev_stats_reset,
294 .xstats_reset = i40e_dev_xstats_reset,
295 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
296 .dev_infos_get = i40e_dev_info_get,
297 .vlan_filter_set = i40e_vlan_filter_set,
298 .vlan_tpid_set = i40e_vlan_tpid_set,
299 .vlan_offload_set = i40e_vlan_offload_set,
300 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
301 .vlan_pvid_set = i40e_vlan_pvid_set,
302 .rx_queue_start = i40e_dev_rx_queue_start,
303 .rx_queue_stop = i40e_dev_rx_queue_stop,
304 .tx_queue_start = i40e_dev_tx_queue_start,
305 .tx_queue_stop = i40e_dev_tx_queue_stop,
306 .rx_queue_setup = i40e_dev_rx_queue_setup,
307 .rx_queue_release = i40e_dev_rx_queue_release,
308 .rx_queue_count = i40e_dev_rx_queue_count,
309 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
310 .tx_queue_setup = i40e_dev_tx_queue_setup,
311 .tx_queue_release = i40e_dev_tx_queue_release,
312 .dev_led_on = i40e_dev_led_on,
313 .dev_led_off = i40e_dev_led_off,
314 .flow_ctrl_get = i40e_flow_ctrl_get,
315 .flow_ctrl_set = i40e_flow_ctrl_set,
316 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
317 .mac_addr_add = i40e_macaddr_add,
318 .mac_addr_remove = i40e_macaddr_remove,
319 .reta_update = i40e_dev_rss_reta_update,
320 .reta_query = i40e_dev_rss_reta_query,
321 .rss_hash_update = i40e_dev_rss_hash_update,
322 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
323 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
324 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
325 .filter_ctrl = i40e_dev_filter_ctrl,
326 .rxq_info_get = i40e_rxq_info_get,
327 .txq_info_get = i40e_txq_info_get,
328 .mirror_rule_set = i40e_mirror_rule_set,
329 .mirror_rule_reset = i40e_mirror_rule_reset,
330 .timesync_enable = i40e_timesync_enable,
331 .timesync_disable = i40e_timesync_disable,
332 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
333 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
334 .get_dcb_info = i40e_dev_get_dcb_info,
337 /* store statistics names and its offset in stats structure */
338 struct rte_i40e_xstats_name_off {
339 char name[RTE_ETH_XSTATS_NAME_SIZE];
343 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
344 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
345 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
346 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
347 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
348 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
349 rx_unknown_protocol)},
350 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
351 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
352 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
353 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
356 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
357 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
358 tx_dropped_link_down)},
359 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
360 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
362 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
363 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
365 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
367 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
369 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
370 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
371 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
372 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
373 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
374 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
376 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
378 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
380 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
382 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
384 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
386 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
388 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
390 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
391 mac_short_packet_dropped)},
392 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
394 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
395 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
396 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
398 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
400 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
402 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
404 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
406 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
408 {"rx_flow_director_atr_match_packets",
409 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
410 {"rx_flow_director_sb_match_packets",
411 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
412 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
414 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
416 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
418 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
422 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
423 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
425 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
426 sizeof(rte_i40e_stats_strings[0]))
427 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
428 sizeof(rte_i40e_hw_port_strings[0]))
429 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
430 I40E_NB_HW_PORT_Q_STATS)
432 static struct eth_driver rte_i40e_pmd = {
434 .name = "rte_i40e_pmd",
435 .id_table = pci_id_i40e_map,
436 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
437 RTE_PCI_DRV_DETACHABLE,
439 .eth_dev_init = eth_i40e_dev_init,
440 .eth_dev_uninit = eth_i40e_dev_uninit,
441 .dev_private_size = sizeof(struct i40e_adapter),
445 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
446 struct rte_eth_link *link)
448 struct rte_eth_link *dst = link;
449 struct rte_eth_link *src = &(dev->data->dev_link);
451 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
452 *(uint64_t *)src) == 0)
459 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
460 struct rte_eth_link *link)
462 struct rte_eth_link *dst = &(dev->data->dev_link);
463 struct rte_eth_link *src = link;
465 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
466 *(uint64_t *)src) == 0)
473 * Driver initialization routine.
474 * Invoked once at EAL init time.
475 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
478 rte_i40e_pmd_init(const char *name __rte_unused,
479 const char *params __rte_unused)
481 PMD_INIT_FUNC_TRACE();
482 rte_eth_driver_register(&rte_i40e_pmd);
487 static struct rte_driver rte_i40e_driver = {
489 .init = rte_i40e_pmd_init,
492 PMD_REGISTER_DRIVER(rte_i40e_driver);
495 * Initialize registers for flexible payload, which should be set by NVM.
496 * This should be removed from code once it is fixed in NVM.
498 #ifndef I40E_GLQF_ORT
499 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
501 #ifndef I40E_GLQF_PIT
502 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
505 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
507 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
508 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
509 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
510 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
511 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
512 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
513 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
514 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
515 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
516 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
518 /* GLQF_PIT Registers */
519 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
520 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
523 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
526 * Add a ethertype filter to drop all flow control frames transmitted
530 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
532 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
533 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
534 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
535 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
538 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
539 I40E_FLOW_CONTROL_ETHERTYPE, flags,
540 pf->main_vsi_seid, 0,
543 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
544 " frames from VSIs.");
548 eth_i40e_dev_init(struct rte_eth_dev *dev)
550 struct rte_pci_device *pci_dev;
551 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
552 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 struct i40e_vsi *vsi;
558 PMD_INIT_FUNC_TRACE();
560 dev->dev_ops = &i40e_eth_dev_ops;
561 dev->rx_pkt_burst = i40e_recv_pkts;
562 dev->tx_pkt_burst = i40e_xmit_pkts;
564 /* for secondary processes, we don't initialise any further as primary
565 * has already done this work. Only check we don't need a different
567 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
568 i40e_set_rx_function(dev);
569 i40e_set_tx_function(dev);
572 pci_dev = dev->pci_dev;
573 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
574 pf->adapter->eth_dev = dev;
575 pf->dev_data = dev->data;
577 hw->back = I40E_PF_TO_ADAPTER(pf);
578 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
580 PMD_INIT_LOG(ERR, "Hardware is not available, "
581 "as address is NULL");
585 hw->vendor_id = pci_dev->id.vendor_id;
586 hw->device_id = pci_dev->id.device_id;
587 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
588 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
589 hw->bus.device = pci_dev->addr.devid;
590 hw->bus.func = pci_dev->addr.function;
591 hw->adapter_stopped = 0;
593 /* Make sure all is clean before doing PF reset */
596 /* Initialize the hardware */
599 /* Reset here to make sure all is clean for each PF */
600 ret = i40e_pf_reset(hw);
602 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
606 /* Initialize the shared code (base driver) */
607 ret = i40e_init_shared_code(hw);
609 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
614 * To work around the NVM issue,initialize registers
615 * for flexible payload by software.
616 * It should be removed once issues are fixed in NVM.
618 i40e_flex_payload_reg_init(hw);
620 /* Initialize the parameters for adminq */
621 i40e_init_adminq_parameter(hw);
622 ret = i40e_init_adminq(hw);
623 if (ret != I40E_SUCCESS) {
624 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
627 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
628 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
629 hw->aq.api_maj_ver, hw->aq.api_min_ver,
630 ((hw->nvm.version >> 12) & 0xf),
631 ((hw->nvm.version >> 4) & 0xff),
632 (hw->nvm.version & 0xf), hw->nvm.eetrack);
635 i40e_clear_pxe_mode(hw);
638 * On X710, performance number is far from the expectation on recent
639 * firmware versions. The fix for this issue may not be integrated in
640 * the following firmware version. So the workaround in software driver
641 * is needed. It needs to modify the initial values of 3 internal only
642 * registers. Note that the workaround can be removed when it is fixed
643 * in firmware in the future.
645 i40e_configure_registers(hw);
647 /* Get hw capabilities */
648 ret = i40e_get_cap(hw);
649 if (ret != I40E_SUCCESS) {
650 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
651 goto err_get_capabilities;
654 /* Initialize parameters for PF */
655 ret = i40e_pf_parameter_init(dev);
657 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
658 goto err_parameter_init;
661 /* Initialize the queue management */
662 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
664 PMD_INIT_LOG(ERR, "Failed to init queue pool");
665 goto err_qp_pool_init;
667 ret = i40e_res_pool_init(&pf->msix_pool, 1,
668 hw->func_caps.num_msix_vectors - 1);
670 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
671 goto err_msix_pool_init;
674 /* Initialize lan hmc */
675 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
676 hw->func_caps.num_rx_qp, 0, 0);
677 if (ret != I40E_SUCCESS) {
678 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
679 goto err_init_lan_hmc;
682 /* Configure lan hmc */
683 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
684 if (ret != I40E_SUCCESS) {
685 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
686 goto err_configure_lan_hmc;
689 /* Get and check the mac address */
690 i40e_get_mac_addr(hw, hw->mac.addr);
691 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
692 PMD_INIT_LOG(ERR, "mac address is not valid");
694 goto err_get_mac_addr;
696 /* Copy the permanent MAC address */
697 ether_addr_copy((struct ether_addr *) hw->mac.addr,
698 (struct ether_addr *) hw->mac.perm_addr);
700 /* Disable flow control */
701 hw->fc.requested_mode = I40E_FC_NONE;
702 i40e_set_fc(hw, &aq_fail, TRUE);
704 /* PF setup, which includes VSI setup */
705 ret = i40e_pf_setup(pf);
707 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
708 goto err_setup_pf_switch;
713 /* Disable double vlan by default */
714 i40e_vsi_config_double_vlan(vsi, FALSE);
716 if (!vsi->max_macaddrs)
717 len = ETHER_ADDR_LEN;
719 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
721 /* Should be after VSI initialized */
722 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
723 if (!dev->data->mac_addrs) {
724 PMD_INIT_LOG(ERR, "Failed to allocated memory "
725 "for storing mac address");
728 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
729 &dev->data->mac_addrs[0]);
731 /* initialize pf host driver to setup SRIOV resource if applicable */
732 i40e_pf_host_init(dev);
734 /* register callback func to eal lib */
735 rte_intr_callback_register(&(pci_dev->intr_handle),
736 i40e_dev_interrupt_handler, (void *)dev);
738 /* configure and enable device interrupt */
739 i40e_pf_config_irq0(hw);
740 i40e_pf_enable_irq0(hw);
742 /* enable uio intr after callback register */
743 rte_intr_enable(&(pci_dev->intr_handle));
745 * Add an ethertype filter to drop all flow control frames transmitted
746 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
749 i40e_add_tx_flow_control_drop_filter(pf);
751 /* initialize mirror rule list */
752 TAILQ_INIT(&pf->mirror_list);
754 /* Init dcb to sw mode by default */
755 ret = i40e_dcb_init_configure(dev, TRUE);
756 if (ret != I40E_SUCCESS) {
757 PMD_INIT_LOG(INFO, "Failed to init dcb.");
758 pf->flags &= ~I40E_FLAG_DCB;
764 i40e_vsi_release(pf->main_vsi);
767 err_configure_lan_hmc:
768 (void)i40e_shutdown_lan_hmc(hw);
770 i40e_res_pool_destroy(&pf->msix_pool);
772 i40e_res_pool_destroy(&pf->qp_pool);
775 err_get_capabilities:
776 (void)i40e_shutdown_adminq(hw);
782 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
784 struct rte_pci_device *pci_dev;
786 struct i40e_filter_control_settings settings;
790 PMD_INIT_FUNC_TRACE();
792 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
795 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
796 pci_dev = dev->pci_dev;
798 if (hw->adapter_stopped == 0)
802 dev->rx_pkt_burst = NULL;
803 dev->tx_pkt_burst = NULL;
806 ret = i40e_aq_stop_lldp(hw, true, NULL);
807 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
808 PMD_INIT_LOG(INFO, "Failed to stop lldp");
811 i40e_clear_pxe_mode(hw);
813 /* Unconfigure filter control */
814 memset(&settings, 0, sizeof(settings));
815 ret = i40e_set_filter_control(hw, &settings);
817 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
820 /* Disable flow control */
821 hw->fc.requested_mode = I40E_FC_NONE;
822 i40e_set_fc(hw, &aq_fail, TRUE);
824 /* uninitialize pf host driver */
825 i40e_pf_host_uninit(dev);
827 rte_free(dev->data->mac_addrs);
828 dev->data->mac_addrs = NULL;
830 /* disable uio intr before callback unregister */
831 rte_intr_disable(&(pci_dev->intr_handle));
833 /* register callback func to eal lib */
834 rte_intr_callback_unregister(&(pci_dev->intr_handle),
835 i40e_dev_interrupt_handler, (void *)dev);
841 i40e_dev_configure(struct rte_eth_dev *dev)
843 struct i40e_adapter *ad =
844 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
845 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
846 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
849 /* Initialize to TRUE. If any of Rx queues doesn't meet the
850 * bulk allocation or vector Rx preconditions we will reset it.
852 ad->rx_bulk_alloc_allowed = true;
853 ad->rx_vec_allowed = true;
854 ad->tx_simple_allowed = true;
855 ad->tx_vec_allowed = true;
857 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
858 ret = i40e_fdir_setup(pf);
859 if (ret != I40E_SUCCESS) {
860 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
863 ret = i40e_fdir_configure(dev);
865 PMD_DRV_LOG(ERR, "failed to configure fdir.");
869 i40e_fdir_teardown(pf);
871 ret = i40e_dev_init_vlan(dev);
876 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
877 * RSS setting have different requirements.
878 * General PMD driver call sequence are NIC init, configure,
879 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
880 * will try to lookup the VSI that specific queue belongs to if VMDQ
881 * applicable. So, VMDQ setting has to be done before
882 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
883 * For RSS setting, it will try to calculate actual configured RX queue
884 * number, which will be available after rx_queue_setup(). dev_start()
885 * function is good to place RSS setup.
887 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
888 ret = i40e_vmdq_setup(dev);
893 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
894 ret = i40e_dcb_setup(dev);
896 PMD_DRV_LOG(ERR, "failed to configure DCB.");
904 /* need to release vmdq resource if exists */
905 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
906 i40e_vsi_release(pf->vmdq[i].vsi);
907 pf->vmdq[i].vsi = NULL;
912 /* need to release fdir resource if exists */
913 i40e_fdir_teardown(pf);
918 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
920 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
921 uint16_t msix_vect = vsi->msix_intr;
924 for (i = 0; i < vsi->nb_qps; i++) {
925 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
926 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
930 if (vsi->type != I40E_VSI_SRIOV) {
931 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
932 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
936 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
937 vsi->user_param + (msix_vect - 1);
939 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
941 I40E_WRITE_FLUSH(hw);
944 static inline uint16_t
945 i40e_calc_itr_interval(int16_t interval)
947 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
948 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
950 /* Convert to hardware count, as writing each 1 represents 2 us */
955 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
958 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
959 uint16_t msix_vect = vsi->msix_intr;
962 for (i = 0; i < vsi->nb_qps; i++)
963 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
965 /* Bind all RX queues to allocated MSIX interrupt */
966 for (i = 0; i < vsi->nb_qps; i++) {
967 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
968 I40E_QINT_RQCTL_ITR_INDX_MASK |
969 ((vsi->base_queue + i + 1) <<
970 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
971 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
972 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
974 if (i == vsi->nb_qps - 1)
975 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
976 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
979 /* Write first RX queue to Link list register as the head element */
980 if (vsi->type != I40E_VSI_SRIOV) {
982 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
984 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
986 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
987 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
989 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
990 msix_vect - 1), interval);
992 #ifndef I40E_GLINT_CTL
993 #define I40E_GLINT_CTL 0x0003F800
994 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
996 /* Disable auto-mask on enabling of all none-zero interrupt */
997 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
998 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
1002 /* num_msix_vectors_vf needs to minus irq0 */
1003 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1004 vsi->user_param + (msix_vect - 1);
1006 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
1007 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1008 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1011 I40E_WRITE_FLUSH(hw);
1015 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1017 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1018 uint16_t interval = i40e_calc_itr_interval(\
1019 RTE_LIBRTE_I40E_ITR_INTERVAL);
1021 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
1022 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1023 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1024 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1025 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1029 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1031 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1033 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
1036 static inline uint8_t
1037 i40e_parse_link_speed(uint16_t eth_link_speed)
1039 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1041 switch (eth_link_speed) {
1042 case ETH_LINK_SPEED_40G:
1043 link_speed = I40E_LINK_SPEED_40GB;
1045 case ETH_LINK_SPEED_20G:
1046 link_speed = I40E_LINK_SPEED_20GB;
1048 case ETH_LINK_SPEED_10G:
1049 link_speed = I40E_LINK_SPEED_10GB;
1051 case ETH_LINK_SPEED_1000:
1052 link_speed = I40E_LINK_SPEED_1GB;
1054 case ETH_LINK_SPEED_100:
1055 link_speed = I40E_LINK_SPEED_100MB;
1063 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1065 enum i40e_status_code status;
1066 struct i40e_aq_get_phy_abilities_resp phy_ab;
1067 struct i40e_aq_set_phy_config phy_conf;
1068 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1069 I40E_AQ_PHY_FLAG_PAUSE_RX |
1070 I40E_AQ_PHY_FLAG_LOW_POWER;
1071 const uint8_t advt = I40E_LINK_SPEED_40GB |
1072 I40E_LINK_SPEED_10GB |
1073 I40E_LINK_SPEED_1GB |
1074 I40E_LINK_SPEED_100MB;
1077 /* Skip it on 40G interfaces, as a workaround for the link issue */
1078 if (i40e_is_40G_device(hw->device_id))
1079 return I40E_SUCCESS;
1081 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1086 memset(&phy_conf, 0, sizeof(phy_conf));
1088 /* bits 0-2 use the values from get_phy_abilities_resp */
1090 abilities |= phy_ab.abilities & mask;
1092 /* update ablities and speed */
1093 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1094 phy_conf.link_speed = advt;
1096 phy_conf.link_speed = force_speed;
1098 phy_conf.abilities = abilities;
1100 /* use get_phy_abilities_resp value for the rest */
1101 phy_conf.phy_type = phy_ab.phy_type;
1102 phy_conf.eee_capability = phy_ab.eee_capability;
1103 phy_conf.eeer = phy_ab.eeer_val;
1104 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1106 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1107 phy_ab.abilities, phy_ab.link_speed);
1108 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1109 phy_conf.abilities, phy_conf.link_speed);
1111 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1115 return I40E_SUCCESS;
1119 i40e_apply_link_speed(struct rte_eth_dev *dev)
1122 uint8_t abilities = 0;
1123 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1124 struct rte_eth_conf *conf = &dev->data->dev_conf;
1126 speed = i40e_parse_link_speed(conf->link_speed);
1127 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1128 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1129 abilities |= I40E_AQ_PHY_AN_ENABLED;
1131 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1133 return i40e_phy_conf_link(hw, abilities, speed);
1137 i40e_dev_start(struct rte_eth_dev *dev)
1139 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1140 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141 struct i40e_vsi *main_vsi = pf->main_vsi;
1144 hw->adapter_stopped = 0;
1146 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1147 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1148 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1149 dev->data->dev_conf.link_duplex,
1150 dev->data->port_id);
1154 /* Initialize VSI */
1155 ret = i40e_dev_rxtx_init(pf);
1156 if (ret != I40E_SUCCESS) {
1157 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1161 /* Map queues with MSIX interrupt */
1162 i40e_vsi_queues_bind_intr(main_vsi);
1163 i40e_vsi_enable_queues_intr(main_vsi);
1165 /* Map VMDQ VSI queues with MSIX interrupt */
1166 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1167 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1168 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1171 /* enable FDIR MSIX interrupt */
1172 if (pf->fdir.fdir_vsi) {
1173 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1174 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1177 /* Enable all queues which have been configured */
1178 ret = i40e_dev_switch_queues(pf, TRUE);
1179 if (ret != I40E_SUCCESS) {
1180 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1184 /* Enable receiving broadcast packets */
1185 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1186 if (ret != I40E_SUCCESS)
1187 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1189 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1190 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1192 if (ret != I40E_SUCCESS)
1193 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1196 /* Apply link configure */
1197 ret = i40e_apply_link_speed(dev);
1198 if (I40E_SUCCESS != ret) {
1199 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1203 return I40E_SUCCESS;
1206 i40e_dev_switch_queues(pf, FALSE);
1207 i40e_dev_clear_queues(dev);
1213 i40e_dev_stop(struct rte_eth_dev *dev)
1215 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1216 struct i40e_vsi *main_vsi = pf->main_vsi;
1217 struct i40e_mirror_rule *p_mirror;
1220 /* Disable all queues */
1221 i40e_dev_switch_queues(pf, FALSE);
1223 /* un-map queues with interrupt registers */
1224 i40e_vsi_disable_queues_intr(main_vsi);
1225 i40e_vsi_queues_unbind_intr(main_vsi);
1227 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1228 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1229 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1232 if (pf->fdir.fdir_vsi) {
1233 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1234 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1236 /* Clear all queues and release memory */
1237 i40e_dev_clear_queues(dev);
1240 i40e_dev_set_link_down(dev);
1242 /* Remove all mirror rules */
1243 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1244 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1247 pf->nb_mirror_rule = 0;
1252 i40e_dev_close(struct rte_eth_dev *dev)
1254 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259 PMD_INIT_FUNC_TRACE();
1262 hw->adapter_stopped = 1;
1263 i40e_dev_free_queues(dev);
1265 /* Disable interrupt */
1266 i40e_pf_disable_irq0(hw);
1267 rte_intr_disable(&(dev->pci_dev->intr_handle));
1269 /* shutdown and destroy the HMC */
1270 i40e_shutdown_lan_hmc(hw);
1272 /* release all the existing VSIs and VEBs */
1273 i40e_fdir_teardown(pf);
1274 i40e_vsi_release(pf->main_vsi);
1276 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1277 i40e_vsi_release(pf->vmdq[i].vsi);
1278 pf->vmdq[i].vsi = NULL;
1284 /* shutdown the adminq */
1285 i40e_aq_queue_shutdown(hw, true);
1286 i40e_shutdown_adminq(hw);
1288 i40e_res_pool_destroy(&pf->qp_pool);
1289 i40e_res_pool_destroy(&pf->msix_pool);
1291 /* force a PF reset to clean anything leftover */
1292 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1293 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1294 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1295 I40E_WRITE_FLUSH(hw);
1299 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1301 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1302 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303 struct i40e_vsi *vsi = pf->main_vsi;
1306 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1308 if (status != I40E_SUCCESS)
1309 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1311 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1313 if (status != I40E_SUCCESS)
1314 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1319 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1321 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1323 struct i40e_vsi *vsi = pf->main_vsi;
1326 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1328 if (status != I40E_SUCCESS)
1329 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1331 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1333 if (status != I40E_SUCCESS)
1334 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1338 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342 struct i40e_vsi *vsi = pf->main_vsi;
1345 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1346 if (ret != I40E_SUCCESS)
1347 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1351 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1354 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1355 struct i40e_vsi *vsi = pf->main_vsi;
1358 if (dev->data->promiscuous == 1)
1359 return; /* must remain in all_multicast mode */
1361 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1362 vsi->seid, FALSE, NULL);
1363 if (ret != I40E_SUCCESS)
1364 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1368 * Set device link up.
1371 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1373 /* re-apply link speed setting */
1374 return i40e_apply_link_speed(dev);
1378 * Set device link down.
1381 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1383 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1384 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1385 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387 return i40e_phy_conf_link(hw, abilities, speed);
1391 i40e_dev_link_update(struct rte_eth_dev *dev,
1392 int wait_to_complete)
1394 #define CHECK_INTERVAL 100 /* 100ms */
1395 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1396 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 struct i40e_link_status link_status;
1398 struct rte_eth_link link, old;
1400 unsigned rep_cnt = MAX_REPEAT_TIME;
1402 memset(&link, 0, sizeof(link));
1403 memset(&old, 0, sizeof(old));
1404 memset(&link_status, 0, sizeof(link_status));
1405 rte_i40e_dev_atomic_read_link_status(dev, &old);
1408 /* Get link status information from hardware */
1409 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1410 if (status != I40E_SUCCESS) {
1411 link.link_speed = ETH_LINK_SPEED_100;
1412 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1413 PMD_DRV_LOG(ERR, "Failed to get link info");
1417 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1418 if (!wait_to_complete)
1421 rte_delay_ms(CHECK_INTERVAL);
1422 } while (!link.link_status && rep_cnt--);
1424 if (!link.link_status)
1427 /* i40e uses full duplex only */
1428 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1430 /* Parse the link status */
1431 switch (link_status.link_speed) {
1432 case I40E_LINK_SPEED_100MB:
1433 link.link_speed = ETH_LINK_SPEED_100;
1435 case I40E_LINK_SPEED_1GB:
1436 link.link_speed = ETH_LINK_SPEED_1000;
1438 case I40E_LINK_SPEED_10GB:
1439 link.link_speed = ETH_LINK_SPEED_10G;
1441 case I40E_LINK_SPEED_20GB:
1442 link.link_speed = ETH_LINK_SPEED_20G;
1444 case I40E_LINK_SPEED_40GB:
1445 link.link_speed = ETH_LINK_SPEED_40G;
1448 link.link_speed = ETH_LINK_SPEED_100;
1453 rte_i40e_dev_atomic_write_link_status(dev, &link);
1454 if (link.link_status == old.link_status)
1460 /* Get all the statistics of a VSI */
1462 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1464 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1465 struct i40e_eth_stats *nes = &vsi->eth_stats;
1466 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1467 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1469 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1470 vsi->offset_loaded, &oes->rx_bytes,
1472 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1473 vsi->offset_loaded, &oes->rx_unicast,
1475 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1476 vsi->offset_loaded, &oes->rx_multicast,
1477 &nes->rx_multicast);
1478 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1479 vsi->offset_loaded, &oes->rx_broadcast,
1480 &nes->rx_broadcast);
1481 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1482 &oes->rx_discards, &nes->rx_discards);
1483 /* GLV_REPC not supported */
1484 /* GLV_RMPC not supported */
1485 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1486 &oes->rx_unknown_protocol,
1487 &nes->rx_unknown_protocol);
1488 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1489 vsi->offset_loaded, &oes->tx_bytes,
1491 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1492 vsi->offset_loaded, &oes->tx_unicast,
1494 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1495 vsi->offset_loaded, &oes->tx_multicast,
1496 &nes->tx_multicast);
1497 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1498 vsi->offset_loaded, &oes->tx_broadcast,
1499 &nes->tx_broadcast);
1500 /* GLV_TDPC not supported */
1501 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1502 &oes->tx_errors, &nes->tx_errors);
1503 vsi->offset_loaded = true;
1505 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1507 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1508 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1509 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1510 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1511 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1512 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1513 nes->rx_unknown_protocol);
1514 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1515 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1516 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1517 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1518 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1519 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1520 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1525 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1528 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1529 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1530 /* Get statistics of struct i40e_eth_stats */
1531 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1532 I40E_GLPRT_GORCL(hw->port),
1533 pf->offset_loaded, &os->eth.rx_bytes,
1535 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1536 I40E_GLPRT_UPRCL(hw->port),
1537 pf->offset_loaded, &os->eth.rx_unicast,
1538 &ns->eth.rx_unicast);
1539 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1540 I40E_GLPRT_MPRCL(hw->port),
1541 pf->offset_loaded, &os->eth.rx_multicast,
1542 &ns->eth.rx_multicast);
1543 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1544 I40E_GLPRT_BPRCL(hw->port),
1545 pf->offset_loaded, &os->eth.rx_broadcast,
1546 &ns->eth.rx_broadcast);
1547 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1548 pf->offset_loaded, &os->eth.rx_discards,
1549 &ns->eth.rx_discards);
1550 /* GLPRT_REPC not supported */
1551 /* GLPRT_RMPC not supported */
1552 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1554 &os->eth.rx_unknown_protocol,
1555 &ns->eth.rx_unknown_protocol);
1556 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1557 I40E_GLPRT_GOTCL(hw->port),
1558 pf->offset_loaded, &os->eth.tx_bytes,
1560 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1561 I40E_GLPRT_UPTCL(hw->port),
1562 pf->offset_loaded, &os->eth.tx_unicast,
1563 &ns->eth.tx_unicast);
1564 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1565 I40E_GLPRT_MPTCL(hw->port),
1566 pf->offset_loaded, &os->eth.tx_multicast,
1567 &ns->eth.tx_multicast);
1568 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1569 I40E_GLPRT_BPTCL(hw->port),
1570 pf->offset_loaded, &os->eth.tx_broadcast,
1571 &ns->eth.tx_broadcast);
1572 /* GLPRT_TEPC not supported */
1574 /* additional port specific stats */
1575 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1576 pf->offset_loaded, &os->tx_dropped_link_down,
1577 &ns->tx_dropped_link_down);
1578 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1579 pf->offset_loaded, &os->crc_errors,
1581 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1582 pf->offset_loaded, &os->illegal_bytes,
1583 &ns->illegal_bytes);
1584 /* GLPRT_ERRBC not supported */
1585 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1586 pf->offset_loaded, &os->mac_local_faults,
1587 &ns->mac_local_faults);
1588 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1589 pf->offset_loaded, &os->mac_remote_faults,
1590 &ns->mac_remote_faults);
1591 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1592 pf->offset_loaded, &os->rx_length_errors,
1593 &ns->rx_length_errors);
1594 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1595 pf->offset_loaded, &os->link_xon_rx,
1597 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1598 pf->offset_loaded, &os->link_xoff_rx,
1600 for (i = 0; i < 8; i++) {
1601 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1603 &os->priority_xon_rx[i],
1604 &ns->priority_xon_rx[i]);
1605 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1607 &os->priority_xoff_rx[i],
1608 &ns->priority_xoff_rx[i]);
1610 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1611 pf->offset_loaded, &os->link_xon_tx,
1613 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1614 pf->offset_loaded, &os->link_xoff_tx,
1616 for (i = 0; i < 8; i++) {
1617 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1619 &os->priority_xon_tx[i],
1620 &ns->priority_xon_tx[i]);
1621 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1623 &os->priority_xoff_tx[i],
1624 &ns->priority_xoff_tx[i]);
1625 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1627 &os->priority_xon_2_xoff[i],
1628 &ns->priority_xon_2_xoff[i]);
1630 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1631 I40E_GLPRT_PRC64L(hw->port),
1632 pf->offset_loaded, &os->rx_size_64,
1634 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1635 I40E_GLPRT_PRC127L(hw->port),
1636 pf->offset_loaded, &os->rx_size_127,
1638 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1639 I40E_GLPRT_PRC255L(hw->port),
1640 pf->offset_loaded, &os->rx_size_255,
1642 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1643 I40E_GLPRT_PRC511L(hw->port),
1644 pf->offset_loaded, &os->rx_size_511,
1646 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1647 I40E_GLPRT_PRC1023L(hw->port),
1648 pf->offset_loaded, &os->rx_size_1023,
1650 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1651 I40E_GLPRT_PRC1522L(hw->port),
1652 pf->offset_loaded, &os->rx_size_1522,
1654 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1655 I40E_GLPRT_PRC9522L(hw->port),
1656 pf->offset_loaded, &os->rx_size_big,
1658 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1659 pf->offset_loaded, &os->rx_undersize,
1661 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1662 pf->offset_loaded, &os->rx_fragments,
1664 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1665 pf->offset_loaded, &os->rx_oversize,
1667 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1668 pf->offset_loaded, &os->rx_jabber,
1670 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1671 I40E_GLPRT_PTC64L(hw->port),
1672 pf->offset_loaded, &os->tx_size_64,
1674 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1675 I40E_GLPRT_PTC127L(hw->port),
1676 pf->offset_loaded, &os->tx_size_127,
1678 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1679 I40E_GLPRT_PTC255L(hw->port),
1680 pf->offset_loaded, &os->tx_size_255,
1682 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1683 I40E_GLPRT_PTC511L(hw->port),
1684 pf->offset_loaded, &os->tx_size_511,
1686 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1687 I40E_GLPRT_PTC1023L(hw->port),
1688 pf->offset_loaded, &os->tx_size_1023,
1690 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1691 I40E_GLPRT_PTC1522L(hw->port),
1692 pf->offset_loaded, &os->tx_size_1522,
1694 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1695 I40E_GLPRT_PTC9522L(hw->port),
1696 pf->offset_loaded, &os->tx_size_big,
1698 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1700 &os->fd_sb_match, &ns->fd_sb_match);
1701 /* GLPRT_MSPDC not supported */
1702 /* GLPRT_XEC not supported */
1704 pf->offset_loaded = true;
1707 i40e_update_vsi_stats(pf->main_vsi);
1710 /* Get all statistics of a port */
1712 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1714 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1719 /* call read registers - updates values, now write them to struct */
1720 i40e_read_stats_registers(pf, hw);
1722 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1723 ns->eth.rx_broadcast;
1724 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1725 ns->eth.tx_broadcast;
1726 stats->ibytes = ns->eth.rx_bytes;
1727 stats->obytes = ns->eth.tx_bytes;
1728 stats->oerrors = ns->eth.tx_errors;
1729 stats->imcasts = ns->eth.rx_multicast;
1730 stats->fdirmatch = ns->fd_sb_match;
1733 stats->ibadcrc = ns->crc_errors;
1734 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1735 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1736 stats->imissed = ns->eth.rx_discards;
1737 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1739 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1740 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
1741 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
1742 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
1743 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
1744 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
1745 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1746 ns->eth.rx_unknown_protocol);
1747 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
1748 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
1749 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
1750 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
1751 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
1752 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
1754 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
1755 ns->tx_dropped_link_down);
1756 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
1757 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
1759 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
1760 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
1761 ns->mac_local_faults);
1762 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
1763 ns->mac_remote_faults);
1764 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
1765 ns->rx_length_errors);
1766 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
1767 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
1768 for (i = 0; i < 8; i++) {
1769 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
1770 i, ns->priority_xon_rx[i]);
1771 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
1772 i, ns->priority_xoff_rx[i]);
1774 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
1775 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
1776 for (i = 0; i < 8; i++) {
1777 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
1778 i, ns->priority_xon_tx[i]);
1779 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
1780 i, ns->priority_xoff_tx[i]);
1781 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
1782 i, ns->priority_xon_2_xoff[i]);
1784 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
1785 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
1786 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
1787 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
1788 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
1789 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
1790 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
1791 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
1792 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
1793 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
1794 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
1795 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
1796 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
1797 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
1798 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
1799 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
1800 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
1801 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
1802 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1803 ns->mac_short_packet_dropped);
1804 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
1805 ns->checksum_error);
1806 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
1807 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1811 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
1813 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1814 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1815 struct i40e_hw_port_stats *hw_stats = &pf->stats;
1817 /* The hw registers are cleared on read */
1818 pf->offset_loaded = false;
1819 i40e_read_stats_registers(pf, hw);
1821 /* reset software counters */
1822 memset(hw_stats, 0, sizeof(*hw_stats));
1826 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1829 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1830 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831 unsigned i, count = 0;
1832 struct i40e_hw_port_stats *hw_stats = &pf->stats;
1834 if (n < I40E_NB_XSTATS)
1835 return I40E_NB_XSTATS;
1837 i40e_read_stats_registers(pf, hw);
1843 /* Get stats from i40e_eth_stats struct */
1844 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
1845 snprintf(xstats[count].name, sizeof(xstats[count].name),
1846 "%s", rte_i40e_stats_strings[i].name);
1847 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
1848 rte_i40e_stats_strings[i].offset);
1852 /* Get individiual stats from i40e_hw_port struct */
1853 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
1854 snprintf(xstats[count].name, sizeof(xstats[count].name),
1855 "%s", rte_i40e_hw_port_strings[i].name);
1856 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1857 rte_i40e_hw_port_strings[i].offset);
1861 /* Get per-queue stats from i40e_hw_port struct */
1862 for (i = 0; i < 8; i++) {
1863 snprintf(xstats[count].name, sizeof(xstats[count].name),
1864 "rx_q%u_xon_priority_packets", i);
1865 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1866 offsetof(struct i40e_hw_port_stats,
1867 priority_xon_rx[i]));
1870 snprintf(xstats[count].name, sizeof(xstats[count].name),
1871 "rx_q%u_xoff_priority_packets", i);
1872 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1873 offsetof(struct i40e_hw_port_stats,
1874 priority_xoff_rx[i]));
1877 snprintf(xstats[count].name, sizeof(xstats[count].name),
1878 "tx_q%u_xon_priority_packets", i);
1879 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1880 offsetof(struct i40e_hw_port_stats,
1881 priority_xon_tx[i]));
1884 snprintf(xstats[count].name, sizeof(xstats[count].name),
1885 "tx_q%u_xoff_priority_packets", i);
1886 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1887 offsetof(struct i40e_hw_port_stats,
1888 priority_xoff_tx[i]));
1891 snprintf(xstats[count].name, sizeof(xstats[count].name),
1892 "xx_q%u_xon_to_xoff_priority_packets", i);
1893 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1894 offsetof(struct i40e_hw_port_stats,
1895 priority_xon_2_xoff[i]));
1899 return I40E_NB_XSTATS;
1902 /* Reset the statistics */
1904 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908 /* It results in reloading the start point of each counter */
1909 pf->offset_loaded = false;
1913 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1914 __rte_unused uint16_t queue_id,
1915 __rte_unused uint8_t stat_idx,
1916 __rte_unused uint8_t is_rx)
1918 PMD_INIT_FUNC_TRACE();
1924 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1926 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1927 struct i40e_vsi *vsi = pf->main_vsi;
1929 dev_info->max_rx_queues = vsi->nb_qps;
1930 dev_info->max_tx_queues = vsi->nb_qps;
1931 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1932 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1933 dev_info->max_mac_addrs = vsi->max_macaddrs;
1934 dev_info->max_vfs = dev->pci_dev->max_vfs;
1935 dev_info->rx_offload_capa =
1936 DEV_RX_OFFLOAD_VLAN_STRIP |
1937 DEV_RX_OFFLOAD_QINQ_STRIP |
1938 DEV_RX_OFFLOAD_IPV4_CKSUM |
1939 DEV_RX_OFFLOAD_UDP_CKSUM |
1940 DEV_RX_OFFLOAD_TCP_CKSUM;
1941 dev_info->tx_offload_capa =
1942 DEV_TX_OFFLOAD_VLAN_INSERT |
1943 DEV_TX_OFFLOAD_QINQ_INSERT |
1944 DEV_TX_OFFLOAD_IPV4_CKSUM |
1945 DEV_TX_OFFLOAD_UDP_CKSUM |
1946 DEV_TX_OFFLOAD_TCP_CKSUM |
1947 DEV_TX_OFFLOAD_SCTP_CKSUM |
1948 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1949 DEV_TX_OFFLOAD_TCP_TSO;
1950 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1952 dev_info->reta_size = pf->hash_lut_size;
1953 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1955 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1957 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1958 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1959 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1961 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1965 dev_info->default_txconf = (struct rte_eth_txconf) {
1967 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1968 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1969 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1971 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1972 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1973 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1974 ETH_TXQ_FLAGS_NOOFFLOADS,
1977 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1978 .nb_max = I40E_MAX_RING_DESC,
1979 .nb_min = I40E_MIN_RING_DESC,
1980 .nb_align = I40E_ALIGN_RING_DESC,
1983 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1984 .nb_max = I40E_MAX_RING_DESC,
1985 .nb_min = I40E_MIN_RING_DESC,
1986 .nb_align = I40E_ALIGN_RING_DESC,
1989 if (pf->flags & I40E_FLAG_VMDQ) {
1990 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1991 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1992 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1993 pf->max_nb_vmdq_vsi;
1994 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1995 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1996 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2001 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2004 struct i40e_vsi *vsi = pf->main_vsi;
2005 PMD_INIT_FUNC_TRACE();
2008 return i40e_vsi_add_vlan(vsi, vlan_id);
2010 return i40e_vsi_delete_vlan(vsi, vlan_id);
2014 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2015 __rte_unused uint16_t tpid)
2017 PMD_INIT_FUNC_TRACE();
2021 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2024 struct i40e_vsi *vsi = pf->main_vsi;
2026 if (mask & ETH_VLAN_STRIP_MASK) {
2027 /* Enable or disable VLAN stripping */
2028 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2029 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2031 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2034 if (mask & ETH_VLAN_EXTEND_MASK) {
2035 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2036 i40e_vsi_config_double_vlan(vsi, TRUE);
2038 i40e_vsi_config_double_vlan(vsi, FALSE);
2043 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2044 __rte_unused uint16_t queue,
2045 __rte_unused int on)
2047 PMD_INIT_FUNC_TRACE();
2051 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054 struct i40e_vsi *vsi = pf->main_vsi;
2055 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2056 struct i40e_vsi_vlan_pvid_info info;
2058 memset(&info, 0, sizeof(info));
2061 info.config.pvid = pvid;
2063 info.config.reject.tagged =
2064 data->dev_conf.txmode.hw_vlan_reject_tagged;
2065 info.config.reject.untagged =
2066 data->dev_conf.txmode.hw_vlan_reject_untagged;
2069 return i40e_vsi_vlan_pvid_set(vsi, &info);
2073 i40e_dev_led_on(struct rte_eth_dev *dev)
2075 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076 uint32_t mode = i40e_led_get(hw);
2079 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2085 i40e_dev_led_off(struct rte_eth_dev *dev)
2087 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 uint32_t mode = i40e_led_get(hw);
2091 i40e_led_set(hw, 0, false);
2097 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2102 fc_conf->pause_time = pf->fc_conf.pause_time;
2103 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2104 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2106 /* Return current mode according to actual setting*/
2107 switch (hw->fc.current_mode) {
2109 fc_conf->mode = RTE_FC_FULL;
2111 case I40E_FC_TX_PAUSE:
2112 fc_conf->mode = RTE_FC_TX_PAUSE;
2114 case I40E_FC_RX_PAUSE:
2115 fc_conf->mode = RTE_FC_RX_PAUSE;
2119 fc_conf->mode = RTE_FC_NONE;
2126 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2128 uint32_t mflcn_reg, fctrl_reg, reg;
2129 uint32_t max_high_water;
2130 uint8_t i, aq_failure;
2134 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2135 [RTE_FC_NONE] = I40E_FC_NONE,
2136 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2137 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2138 [RTE_FC_FULL] = I40E_FC_FULL
2141 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2143 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2144 if ((fc_conf->high_water > max_high_water) ||
2145 (fc_conf->high_water < fc_conf->low_water)) {
2146 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2147 "High_water must <= %d.", max_high_water);
2151 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2155 pf->fc_conf.pause_time = fc_conf->pause_time;
2156 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2157 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2159 PMD_INIT_FUNC_TRACE();
2161 /* All the link flow control related enable/disable register
2162 * configuration is handle by the F/W
2164 err = i40e_set_fc(hw, &aq_failure, true);
2168 if (i40e_is_40G_device(hw->device_id)) {
2169 /* Configure flow control refresh threshold,
2170 * the value for stat_tx_pause_refresh_timer[8]
2171 * is used for global pause operation.
2175 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2176 pf->fc_conf.pause_time);
2178 /* configure the timer value included in transmitted pause
2180 * the value for stat_tx_pause_quanta[8] is used for global
2183 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2184 pf->fc_conf.pause_time);
2186 fctrl_reg = I40E_READ_REG(hw,
2187 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2189 if (fc_conf->mac_ctrl_frame_fwd != 0)
2190 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2192 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2194 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2197 /* Configure pause time (2 TCs per register) */
2198 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2199 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2200 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2202 /* Configure flow control refresh threshold value */
2203 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2204 pf->fc_conf.pause_time / 2);
2206 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2208 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2209 *depending on configuration
2211 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2212 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2213 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2215 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2216 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2219 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2222 /* config the water marker both based on the packets and bytes */
2223 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2224 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2225 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2226 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2227 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2228 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2229 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2230 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2232 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2233 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2236 I40E_WRITE_FLUSH(hw);
2242 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2243 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2245 PMD_INIT_FUNC_TRACE();
2250 /* Add a MAC address, and update filters */
2252 i40e_macaddr_add(struct rte_eth_dev *dev,
2253 struct ether_addr *mac_addr,
2254 __rte_unused uint32_t index,
2257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2258 struct i40e_mac_filter_info mac_filter;
2259 struct i40e_vsi *vsi;
2262 /* If VMDQ not enabled or configured, return */
2263 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2264 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2265 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2270 if (pool > pf->nb_cfg_vmdq_vsi) {
2271 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2272 pool, pf->nb_cfg_vmdq_vsi);
2276 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2277 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2282 vsi = pf->vmdq[pool - 1].vsi;
2284 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2285 if (ret != I40E_SUCCESS) {
2286 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2291 /* Remove a MAC address, and update filters */
2293 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296 struct i40e_vsi *vsi;
2297 struct rte_eth_dev_data *data = dev->data;
2298 struct ether_addr *macaddr;
2303 macaddr = &(data->mac_addrs[index]);
2305 pool_sel = dev->data->mac_pool_sel[index];
2307 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2308 if (pool_sel & (1ULL << i)) {
2312 /* No VMDQ pool enabled or configured */
2313 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2314 (i > pf->nb_cfg_vmdq_vsi)) {
2315 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2319 vsi = pf->vmdq[i - 1].vsi;
2321 ret = i40e_vsi_delete_mac(vsi, macaddr);
2324 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2331 /* Set perfect match or hash match of MAC and VLAN for a VF */
2333 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2334 struct rte_eth_mac_filter *filter,
2338 struct i40e_mac_filter_info mac_filter;
2339 struct ether_addr old_mac;
2340 struct ether_addr *new_mac;
2341 struct i40e_pf_vf *vf = NULL;
2346 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2349 hw = I40E_PF_TO_HW(pf);
2351 if (filter == NULL) {
2352 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2356 new_mac = &filter->mac_addr;
2358 if (is_zero_ether_addr(new_mac)) {
2359 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2363 vf_id = filter->dst_id;
2365 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2366 PMD_DRV_LOG(ERR, "Invalid argument.");
2369 vf = &pf->vfs[vf_id];
2371 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2372 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2377 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2378 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2380 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2383 mac_filter.filter_type = filter->filter_type;
2384 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2385 if (ret != I40E_SUCCESS) {
2386 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2389 ether_addr_copy(new_mac, &pf->dev_addr);
2391 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2393 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2394 if (ret != I40E_SUCCESS) {
2395 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2399 /* Clear device address as it has been removed */
2400 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2401 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2407 /* MAC filter handle */
2409 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2412 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2413 struct rte_eth_mac_filter *filter;
2414 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2415 int ret = I40E_NOT_SUPPORTED;
2417 filter = (struct rte_eth_mac_filter *)(arg);
2419 switch (filter_op) {
2420 case RTE_ETH_FILTER_NOP:
2423 case RTE_ETH_FILTER_ADD:
2424 i40e_pf_disable_irq0(hw);
2426 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2427 i40e_pf_enable_irq0(hw);
2429 case RTE_ETH_FILTER_DELETE:
2430 i40e_pf_disable_irq0(hw);
2432 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2433 i40e_pf_enable_irq0(hw);
2436 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2437 ret = I40E_ERR_PARAM;
2445 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2447 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2448 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2454 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2455 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2458 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2462 uint32_t *lut_dw = (uint32_t *)lut;
2463 uint16_t i, lut_size_dw = lut_size / 4;
2465 for (i = 0; i < lut_size_dw; i++)
2466 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2473 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2475 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2476 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2482 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2483 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2486 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2490 uint32_t *lut_dw = (uint32_t *)lut;
2491 uint16_t i, lut_size_dw = lut_size / 4;
2493 for (i = 0; i < lut_size_dw; i++)
2494 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2495 I40E_WRITE_FLUSH(hw);
2502 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2503 struct rte_eth_rss_reta_entry64 *reta_conf,
2506 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2507 uint16_t i, lut_size = pf->hash_lut_size;
2508 uint16_t idx, shift;
2512 if (reta_size != lut_size ||
2513 reta_size > ETH_RSS_RETA_SIZE_512) {
2514 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2515 "(%d) doesn't match the number hardware can supported "
2516 "(%d)\n", reta_size, lut_size);
2520 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2522 PMD_DRV_LOG(ERR, "No memory can be allocated");
2525 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2528 for (i = 0; i < reta_size; i++) {
2529 idx = i / RTE_RETA_GROUP_SIZE;
2530 shift = i % RTE_RETA_GROUP_SIZE;
2531 if (reta_conf[idx].mask & (1ULL << shift))
2532 lut[i] = reta_conf[idx].reta[shift];
2534 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2543 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2544 struct rte_eth_rss_reta_entry64 *reta_conf,
2547 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2548 uint16_t i, lut_size = pf->hash_lut_size;
2549 uint16_t idx, shift;
2553 if (reta_size != lut_size ||
2554 reta_size > ETH_RSS_RETA_SIZE_512) {
2555 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2556 "(%d) doesn't match the number hardware can supported "
2557 "(%d)\n", reta_size, lut_size);
2561 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2563 PMD_DRV_LOG(ERR, "No memory can be allocated");
2567 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2570 for (i = 0; i < reta_size; i++) {
2571 idx = i / RTE_RETA_GROUP_SIZE;
2572 shift = i % RTE_RETA_GROUP_SIZE;
2573 if (reta_conf[idx].mask & (1ULL << shift))
2574 reta_conf[idx].reta[shift] = lut[i];
2584 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2585 * @hw: pointer to the HW structure
2586 * @mem: pointer to mem struct to fill out
2587 * @size: size of memory requested
2588 * @alignment: what to align the allocation to
2590 enum i40e_status_code
2591 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2592 struct i40e_dma_mem *mem,
2596 static uint64_t id = 0;
2597 const struct rte_memzone *mz = NULL;
2598 char z_name[RTE_MEMZONE_NAMESIZE];
2601 return I40E_ERR_PARAM;
2604 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2605 #ifdef RTE_LIBRTE_XEN_DOM0
2606 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2607 alignment, RTE_PGSIZE_2M);
2609 mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2613 return I40E_ERR_NO_MEMORY;
2618 #ifdef RTE_LIBRTE_XEN_DOM0
2619 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2621 mem->pa = mz->phys_addr;
2624 return I40E_SUCCESS;
2628 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2629 * @hw: pointer to the HW structure
2630 * @mem: ptr to mem struct to free
2632 enum i40e_status_code
2633 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2634 struct i40e_dma_mem *mem)
2636 if (!mem || !mem->va)
2637 return I40E_ERR_PARAM;
2642 return I40E_SUCCESS;
2646 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2647 * @hw: pointer to the HW structure
2648 * @mem: pointer to mem struct to fill out
2649 * @size: size of memory requested
2651 enum i40e_status_code
2652 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2653 struct i40e_virt_mem *mem,
2657 return I40E_ERR_PARAM;
2660 mem->va = rte_zmalloc("i40e", size, 0);
2663 return I40E_SUCCESS;
2665 return I40E_ERR_NO_MEMORY;
2669 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2670 * @hw: pointer to the HW structure
2671 * @mem: pointer to mem struct to free
2673 enum i40e_status_code
2674 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2675 struct i40e_virt_mem *mem)
2678 return I40E_ERR_PARAM;
2683 return I40E_SUCCESS;
2687 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2689 rte_spinlock_init(&sp->spinlock);
2693 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2695 rte_spinlock_lock(&sp->spinlock);
2699 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2701 rte_spinlock_unlock(&sp->spinlock);
2705 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2711 * Get the hardware capabilities, which will be parsed
2712 * and saved into struct i40e_hw.
2715 i40e_get_cap(struct i40e_hw *hw)
2717 struct i40e_aqc_list_capabilities_element_resp *buf;
2718 uint16_t len, size = 0;
2721 /* Calculate a huge enough buff for saving response data temporarily */
2722 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2723 I40E_MAX_CAP_ELE_NUM;
2724 buf = rte_zmalloc("i40e", len, 0);
2726 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2727 return I40E_ERR_NO_MEMORY;
2730 /* Get, parse the capabilities and save it to hw */
2731 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2732 i40e_aqc_opc_list_func_capabilities, NULL);
2733 if (ret != I40E_SUCCESS)
2734 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2736 /* Free the temporary buffer after being used */
2743 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2745 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2747 uint16_t sum_queues = 0, sum_vsis, left_queues;
2749 /* First check if FW support SRIOV */
2750 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2751 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2754 /* Add the parameter init for LFC */
2755 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2756 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2757 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2759 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2760 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2761 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2762 /* Allocate queues for pf */
2763 if (hw->func_caps.rss) {
2764 pf->flags |= I40E_FLAG_RSS;
2765 if (hw->mac.type == I40E_MAC_X722)
2766 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
2767 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2768 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2769 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2772 sum_queues = pf->lan_nb_qps;
2773 /* Default VSI is not counted in */
2775 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2777 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2778 pf->flags |= I40E_FLAG_SRIOV;
2779 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2780 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2781 PMD_INIT_LOG(ERR, "Config VF number %u, "
2782 "max supported %u.",
2783 dev->pci_dev->max_vfs,
2784 hw->func_caps.num_vfs);
2787 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2788 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2789 "max support %u queues.",
2790 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2793 pf->vf_num = dev->pci_dev->max_vfs;
2794 sum_queues += pf->vf_nb_qps * pf->vf_num;
2795 sum_vsis += pf->vf_num;
2796 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2797 pf->vf_num, pf->vf_nb_qps);
2801 if (hw->func_caps.vmdq) {
2802 pf->flags |= I40E_FLAG_VMDQ;
2803 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2804 pf->max_nb_vmdq_vsi = 1;
2806 * If VMDQ available, assume a single VSI can be created. Will adjust
2809 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2810 sum_vsis += pf->max_nb_vmdq_vsi;
2812 pf->vmdq_nb_qps = 0;
2813 pf->max_nb_vmdq_vsi = 0;
2815 pf->nb_cfg_vmdq_vsi = 0;
2817 if (hw->func_caps.fd) {
2818 pf->flags |= I40E_FLAG_FDIR;
2819 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2821 * Each flow director consumes one VSI and one queue,
2822 * but can't calculate out predictably here.
2826 if (hw->func_caps.dcb)
2827 pf->flags |= I40E_FLAG_DCB;
2829 if (sum_vsis > pf->max_num_vsi ||
2830 sum_queues > hw->func_caps.num_rx_qp) {
2831 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2832 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2833 pf->max_num_vsi, sum_vsis);
2834 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2835 hw->func_caps.num_rx_qp, sum_queues);
2839 /* Adjust VMDQ setting to support as many VMs as possible */
2840 if (pf->flags & I40E_FLAG_VMDQ) {
2841 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2843 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2844 pf->max_num_vsi - sum_vsis);
2846 /* Limit the max VMDQ number that rte_ether that can support */
2847 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2850 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2851 pf->max_nb_vmdq_vsi);
2852 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2855 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2857 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2858 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2859 sum_vsis, hw->func_caps.num_msix_vectors);
2862 return I40E_SUCCESS;
2866 i40e_pf_get_switch_config(struct i40e_pf *pf)
2868 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2869 struct i40e_aqc_get_switch_config_resp *switch_config;
2870 struct i40e_aqc_switch_config_element_resp *element;
2871 uint16_t start_seid = 0, num_reported;
2874 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2875 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2876 if (!switch_config) {
2877 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2881 /* Get the switch configurations */
2882 ret = i40e_aq_get_switch_config(hw, switch_config,
2883 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2884 if (ret != I40E_SUCCESS) {
2885 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2888 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2889 if (num_reported != 1) { /* The number should be 1 */
2890 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2894 /* Parse the switch configuration elements */
2895 element = &(switch_config->element[0]);
2896 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2897 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2898 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2900 PMD_DRV_LOG(INFO, "Unknown element type");
2903 rte_free(switch_config);
2909 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2912 struct pool_entry *entry;
2914 if (pool == NULL || num == 0)
2917 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2918 if (entry == NULL) {
2919 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2923 /* queue heap initialize */
2924 pool->num_free = num;
2925 pool->num_alloc = 0;
2927 LIST_INIT(&pool->alloc_list);
2928 LIST_INIT(&pool->free_list);
2930 /* Initialize element */
2934 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2939 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2941 struct pool_entry *entry;
2946 LIST_FOREACH(entry, &pool->alloc_list, next) {
2947 LIST_REMOVE(entry, next);
2951 LIST_FOREACH(entry, &pool->free_list, next) {
2952 LIST_REMOVE(entry, next);
2957 pool->num_alloc = 0;
2959 LIST_INIT(&pool->alloc_list);
2960 LIST_INIT(&pool->free_list);
2964 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2967 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2968 uint32_t pool_offset;
2972 PMD_DRV_LOG(ERR, "Invalid parameter");
2976 pool_offset = base - pool->base;
2977 /* Lookup in alloc list */
2978 LIST_FOREACH(entry, &pool->alloc_list, next) {
2979 if (entry->base == pool_offset) {
2980 valid_entry = entry;
2981 LIST_REMOVE(entry, next);
2986 /* Not find, return */
2987 if (valid_entry == NULL) {
2988 PMD_DRV_LOG(ERR, "Failed to find entry");
2993 * Found it, move it to free list and try to merge.
2994 * In order to make merge easier, always sort it by qbase.
2995 * Find adjacent prev and last entries.
2998 LIST_FOREACH(entry, &pool->free_list, next) {
2999 if (entry->base > valid_entry->base) {
3007 /* Try to merge with next one*/
3009 /* Merge with next one */
3010 if (valid_entry->base + valid_entry->len == next->base) {
3011 next->base = valid_entry->base;
3012 next->len += valid_entry->len;
3013 rte_free(valid_entry);
3020 /* Merge with previous one */
3021 if (prev->base + prev->len == valid_entry->base) {
3022 prev->len += valid_entry->len;
3023 /* If it merge with next one, remove next node */
3025 LIST_REMOVE(valid_entry, next);
3026 rte_free(valid_entry);
3028 rte_free(valid_entry);
3034 /* Not find any entry to merge, insert */
3037 LIST_INSERT_AFTER(prev, valid_entry, next);
3038 else if (next != NULL)
3039 LIST_INSERT_BEFORE(next, valid_entry, next);
3040 else /* It's empty list, insert to head */
3041 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3044 pool->num_free += valid_entry->len;
3045 pool->num_alloc -= valid_entry->len;
3051 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3054 struct pool_entry *entry, *valid_entry;
3056 if (pool == NULL || num == 0) {
3057 PMD_DRV_LOG(ERR, "Invalid parameter");
3061 if (pool->num_free < num) {
3062 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3063 num, pool->num_free);
3068 /* Lookup in free list and find most fit one */
3069 LIST_FOREACH(entry, &pool->free_list, next) {
3070 if (entry->len >= num) {
3072 if (entry->len == num) {
3073 valid_entry = entry;
3076 if (valid_entry == NULL || valid_entry->len > entry->len)
3077 valid_entry = entry;
3081 /* Not find one to satisfy the request, return */
3082 if (valid_entry == NULL) {
3083 PMD_DRV_LOG(ERR, "No valid entry found");
3087 * The entry have equal queue number as requested,
3088 * remove it from alloc_list.
3090 if (valid_entry->len == num) {
3091 LIST_REMOVE(valid_entry, next);
3094 * The entry have more numbers than requested,
3095 * create a new entry for alloc_list and minus its
3096 * queue base and number in free_list.
3098 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3099 if (entry == NULL) {
3100 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3104 entry->base = valid_entry->base;
3106 valid_entry->base += num;
3107 valid_entry->len -= num;
3108 valid_entry = entry;
3111 /* Insert it into alloc list, not sorted */
3112 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3114 pool->num_free -= valid_entry->len;
3115 pool->num_alloc += valid_entry->len;
3117 return (valid_entry->base + pool->base);
3121 * bitmap_is_subset - Check whether src2 is subset of src1
3124 bitmap_is_subset(uint8_t src1, uint8_t src2)
3126 return !((src1 ^ src2) & src2);
3130 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3132 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3134 /* If DCB is not supported, only default TC is supported */
3135 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3136 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3140 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3141 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3142 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3146 return I40E_SUCCESS;
3150 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3151 struct i40e_vsi_vlan_pvid_info *info)
3154 struct i40e_vsi_context ctxt;
3155 uint8_t vlan_flags = 0;
3158 if (vsi == NULL || info == NULL) {
3159 PMD_DRV_LOG(ERR, "invalid parameters");
3160 return I40E_ERR_PARAM;
3164 vsi->info.pvid = info->config.pvid;
3166 * If insert pvid is enabled, only tagged pkts are
3167 * allowed to be sent out.
3169 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3170 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3173 if (info->config.reject.tagged == 0)
3174 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3176 if (info->config.reject.untagged == 0)
3177 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3179 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3180 I40E_AQ_VSI_PVLAN_MODE_MASK);
3181 vsi->info.port_vlan_flags |= vlan_flags;
3182 vsi->info.valid_sections =
3183 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3184 memset(&ctxt, 0, sizeof(ctxt));
3185 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3186 ctxt.seid = vsi->seid;
3188 hw = I40E_VSI_TO_HW(vsi);
3189 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3190 if (ret != I40E_SUCCESS)
3191 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3197 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3199 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3201 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3203 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3204 if (ret != I40E_SUCCESS)
3208 PMD_DRV_LOG(ERR, "seid not valid");
3212 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3213 tc_bw_data.tc_valid_bits = enabled_tcmap;
3214 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3215 tc_bw_data.tc_bw_credits[i] =
3216 (enabled_tcmap & (1 << i)) ? 1 : 0;
3218 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3219 if (ret != I40E_SUCCESS) {
3220 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3224 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3225 sizeof(vsi->info.qs_handle));
3226 return I40E_SUCCESS;
3230 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3231 struct i40e_aqc_vsi_properties_data *info,
3232 uint8_t enabled_tcmap)
3234 int ret, i, total_tc = 0;
3235 uint16_t qpnum_per_tc, bsf, qp_idx;
3237 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3238 if (ret != I40E_SUCCESS)
3241 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3242 if (enabled_tcmap & (1 << i))
3244 vsi->enabled_tc = enabled_tcmap;
3246 /* Number of queues per enabled TC */
3247 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3248 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3249 bsf = rte_bsf32(qpnum_per_tc);
3251 /* Adjust the queue number to actual queues that can be applied */
3252 vsi->nb_qps = qpnum_per_tc * total_tc;
3255 * Configure TC and queue mapping parameters, for enabled TC,
3256 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3257 * default queue will serve it.
3260 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3261 if (vsi->enabled_tc & (1 << i)) {
3262 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3263 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3264 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3265 qp_idx += qpnum_per_tc;
3267 info->tc_mapping[i] = 0;
3270 /* Associate queue number with VSI */
3271 if (vsi->type == I40E_VSI_SRIOV) {
3272 info->mapping_flags |=
3273 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3274 for (i = 0; i < vsi->nb_qps; i++)
3275 info->queue_mapping[i] =
3276 rte_cpu_to_le_16(vsi->base_queue + i);
3278 info->mapping_flags |=
3279 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3280 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3282 info->valid_sections |=
3283 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3285 return I40E_SUCCESS;
3289 i40e_veb_release(struct i40e_veb *veb)
3291 struct i40e_vsi *vsi;
3294 if (veb == NULL || veb->associate_vsi == NULL)
3297 if (!TAILQ_EMPTY(&veb->head)) {
3298 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3302 vsi = veb->associate_vsi;
3303 hw = I40E_VSI_TO_HW(vsi);
3305 vsi->uplink_seid = veb->uplink_seid;
3306 i40e_aq_delete_element(hw, veb->seid, NULL);
3309 return I40E_SUCCESS;
3313 static struct i40e_veb *
3314 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3316 struct i40e_veb *veb;
3320 if (NULL == pf || vsi == NULL) {
3321 PMD_DRV_LOG(ERR, "veb setup failed, "
3322 "associated VSI shouldn't null");
3325 hw = I40E_PF_TO_HW(pf);
3327 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3329 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3333 veb->associate_vsi = vsi;
3334 TAILQ_INIT(&veb->head);
3335 veb->uplink_seid = vsi->uplink_seid;
3337 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3338 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3340 if (ret != I40E_SUCCESS) {
3341 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3342 hw->aq.asq_last_status);
3346 /* get statistics index */
3347 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3348 &veb->stats_idx, NULL, NULL, NULL);
3349 if (ret != I40E_SUCCESS) {
3350 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3351 hw->aq.asq_last_status);
3355 /* Get VEB bandwidth, to be implemented */
3356 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3357 vsi->uplink_seid = veb->seid;
3366 i40e_vsi_release(struct i40e_vsi *vsi)
3370 struct i40e_vsi_list *vsi_list;
3372 struct i40e_mac_filter *f;
3375 return I40E_SUCCESS;
3377 pf = I40E_VSI_TO_PF(vsi);
3378 hw = I40E_VSI_TO_HW(vsi);
3380 /* VSI has child to attach, release child first */
3382 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3383 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3385 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3387 i40e_veb_release(vsi->veb);
3390 /* Remove all macvlan filters of the VSI */
3391 i40e_vsi_remove_all_macvlan_filter(vsi);
3392 TAILQ_FOREACH(f, &vsi->mac_list, next)
3395 if (vsi->type != I40E_VSI_MAIN) {
3396 /* Remove vsi from parent's sibling list */
3397 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3398 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3399 return I40E_ERR_PARAM;
3401 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3402 &vsi->sib_vsi_list, list);
3404 /* Remove all switch element of the VSI */
3405 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3406 if (ret != I40E_SUCCESS)
3407 PMD_DRV_LOG(ERR, "Failed to delete element");
3409 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3411 if (vsi->type != I40E_VSI_SRIOV)
3412 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3415 return I40E_SUCCESS;
3419 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3421 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3422 struct i40e_aqc_remove_macvlan_element_data def_filter;
3423 struct i40e_mac_filter_info filter;
3426 if (vsi->type != I40E_VSI_MAIN)
3427 return I40E_ERR_CONFIG;
3428 memset(&def_filter, 0, sizeof(def_filter));
3429 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3431 def_filter.vlan_tag = 0;
3432 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3433 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3434 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3435 if (ret != I40E_SUCCESS) {
3436 struct i40e_mac_filter *f;
3437 struct ether_addr *mac;
3439 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3441 /* It needs to add the permanent mac into mac list */
3442 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3444 PMD_DRV_LOG(ERR, "failed to allocate memory");
3445 return I40E_ERR_NO_MEMORY;
3447 mac = &f->mac_info.mac_addr;
3448 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3450 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3451 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3456 (void)rte_memcpy(&filter.mac_addr,
3457 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3458 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3459 return i40e_vsi_add_mac(vsi, &filter);
3463 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3465 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3466 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3467 struct i40e_hw *hw = &vsi->adapter->hw;
3471 memset(&bw_config, 0, sizeof(bw_config));
3472 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3473 if (ret != I40E_SUCCESS) {
3474 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3475 hw->aq.asq_last_status);
3479 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3480 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3481 &ets_sla_config, NULL);
3482 if (ret != I40E_SUCCESS) {
3483 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3484 "configuration %u", hw->aq.asq_last_status);
3488 /* Not store the info yet, just print out */
3489 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3490 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3491 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3492 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3493 ets_sla_config.share_credits[i]);
3494 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3495 rte_le_to_cpu_16(ets_sla_config.credits[i]));
3496 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3497 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3506 i40e_vsi_setup(struct i40e_pf *pf,
3507 enum i40e_vsi_type type,
3508 struct i40e_vsi *uplink_vsi,
3509 uint16_t user_param)
3511 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3512 struct i40e_vsi *vsi;
3513 struct i40e_mac_filter_info filter;
3515 struct i40e_vsi_context ctxt;
3516 struct ether_addr broadcast =
3517 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3519 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3520 PMD_DRV_LOG(ERR, "VSI setup failed, "
3521 "VSI link shouldn't be NULL");
3525 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3526 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3527 "uplink VSI should be NULL");
3531 /* If uplink vsi didn't setup VEB, create one first */
3532 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3533 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3535 if (NULL == uplink_vsi->veb) {
3536 PMD_DRV_LOG(ERR, "VEB setup failed");
3541 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3543 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3546 TAILQ_INIT(&vsi->mac_list);
3548 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3549 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3550 vsi->parent_vsi = uplink_vsi;
3551 vsi->user_param = user_param;
3552 /* Allocate queues */
3553 switch (vsi->type) {
3554 case I40E_VSI_MAIN :
3555 vsi->nb_qps = pf->lan_nb_qps;
3557 case I40E_VSI_SRIOV :
3558 vsi->nb_qps = pf->vf_nb_qps;
3560 case I40E_VSI_VMDQ2:
3561 vsi->nb_qps = pf->vmdq_nb_qps;
3564 vsi->nb_qps = pf->fdir_nb_qps;
3570 * The filter status descriptor is reported in rx queue 0,
3571 * while the tx queue for fdir filter programming has no
3572 * such constraints, can be non-zero queues.
3573 * To simplify it, choose FDIR vsi use queue 0 pair.
3574 * To make sure it will use queue 0 pair, queue allocation
3575 * need be done before this function is called
3577 if (type != I40E_VSI_FDIR) {
3578 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3580 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3584 vsi->base_queue = ret;
3586 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3588 /* VF has MSIX interrupt in VF range, don't allocate here */
3589 if (type != I40E_VSI_SRIOV) {
3590 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3592 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3593 goto fail_queue_alloc;
3595 vsi->msix_intr = ret;
3599 if (type == I40E_VSI_MAIN) {
3600 /* For main VSI, no need to add since it's default one */
3601 vsi->uplink_seid = pf->mac_seid;
3602 vsi->seid = pf->main_vsi_seid;
3603 /* Bind queues with specific MSIX interrupt */
3605 * Needs 2 interrupt at least, one for misc cause which will
3606 * enabled from OS side, Another for queues binding the
3607 * interrupt from device side only.
3610 /* Get default VSI parameters from hardware */
3611 memset(&ctxt, 0, sizeof(ctxt));
3612 ctxt.seid = vsi->seid;
3613 ctxt.pf_num = hw->pf_id;
3614 ctxt.uplink_seid = vsi->uplink_seid;
3616 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3617 if (ret != I40E_SUCCESS) {
3618 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3619 goto fail_msix_alloc;
3621 (void)rte_memcpy(&vsi->info, &ctxt.info,
3622 sizeof(struct i40e_aqc_vsi_properties_data));
3623 vsi->vsi_id = ctxt.vsi_number;
3624 vsi->info.valid_sections = 0;
3626 /* Configure tc, enabled TC0 only */
3627 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3629 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3630 goto fail_msix_alloc;
3633 /* TC, queue mapping */
3634 memset(&ctxt, 0, sizeof(ctxt));
3635 vsi->info.valid_sections |=
3636 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3637 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3638 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3639 (void)rte_memcpy(&ctxt.info, &vsi->info,
3640 sizeof(struct i40e_aqc_vsi_properties_data));
3641 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3642 I40E_DEFAULT_TCMAP);
3643 if (ret != I40E_SUCCESS) {
3644 PMD_DRV_LOG(ERR, "Failed to configure "
3645 "TC queue mapping");
3646 goto fail_msix_alloc;
3648 ctxt.seid = vsi->seid;
3649 ctxt.pf_num = hw->pf_id;
3650 ctxt.uplink_seid = vsi->uplink_seid;
3653 /* Update VSI parameters */
3654 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3655 if (ret != I40E_SUCCESS) {
3656 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3657 goto fail_msix_alloc;
3660 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3661 sizeof(vsi->info.tc_mapping));
3662 (void)rte_memcpy(&vsi->info.queue_mapping,
3663 &ctxt.info.queue_mapping,
3664 sizeof(vsi->info.queue_mapping));
3665 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3666 vsi->info.valid_sections = 0;
3668 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3672 * Updating default filter settings are necessary to prevent
3673 * reception of tagged packets.
3674 * Some old firmware configurations load a default macvlan
3675 * filter which accepts both tagged and untagged packets.
3676 * The updating is to use a normal filter instead if needed.
3677 * For NVM 4.2.2 or after, the updating is not needed anymore.
3678 * The firmware with correct configurations load the default
3679 * macvlan filter which is expected and cannot be removed.
3681 i40e_update_default_filter_setting(vsi);
3682 i40e_config_qinq(hw, vsi);
3683 } else if (type == I40E_VSI_SRIOV) {
3684 memset(&ctxt, 0, sizeof(ctxt));
3686 * For other VSI, the uplink_seid equals to uplink VSI's
3687 * uplink_seid since they share same VEB
3689 vsi->uplink_seid = uplink_vsi->uplink_seid;
3690 ctxt.pf_num = hw->pf_id;
3691 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3692 ctxt.uplink_seid = vsi->uplink_seid;
3693 ctxt.connection_type = 0x1;
3694 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3697 * Do not configure switch ID to enable VEB switch by
3698 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3699 * if the source mac address of packet sent from VF is not
3700 * listed in the VEB's mac table, the VEB will switch the
3701 * packet back to the VF. Need to enable it when HW issue
3705 /* Configure port/vlan */
3706 ctxt.info.valid_sections |=
3707 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3708 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3709 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3710 I40E_DEFAULT_TCMAP);
3711 if (ret != I40E_SUCCESS) {
3712 PMD_DRV_LOG(ERR, "Failed to configure "
3713 "TC queue mapping");
3714 goto fail_msix_alloc;
3716 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3717 ctxt.info.valid_sections |=
3718 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3720 * Since VSI is not created yet, only configure parameter,
3721 * will add vsi below.
3724 i40e_config_qinq(hw, vsi);
3725 } else if (type == I40E_VSI_VMDQ2) {
3726 memset(&ctxt, 0, sizeof(ctxt));
3728 * For other VSI, the uplink_seid equals to uplink VSI's
3729 * uplink_seid since they share same VEB
3731 vsi->uplink_seid = uplink_vsi->uplink_seid;
3732 ctxt.pf_num = hw->pf_id;
3734 ctxt.uplink_seid = vsi->uplink_seid;
3735 ctxt.connection_type = 0x1;
3736 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3738 ctxt.info.valid_sections |=
3739 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3740 /* user_param carries flag to enable loop back */
3742 ctxt.info.switch_id =
3743 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3744 ctxt.info.switch_id |=
3745 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3748 /* Configure port/vlan */
3749 ctxt.info.valid_sections |=
3750 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3751 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3752 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3753 I40E_DEFAULT_TCMAP);
3754 if (ret != I40E_SUCCESS) {
3755 PMD_DRV_LOG(ERR, "Failed to configure "
3756 "TC queue mapping");
3757 goto fail_msix_alloc;
3759 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3760 ctxt.info.valid_sections |=
3761 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3762 } else if (type == I40E_VSI_FDIR) {
3763 memset(&ctxt, 0, sizeof(ctxt));
3764 vsi->uplink_seid = uplink_vsi->uplink_seid;
3765 ctxt.pf_num = hw->pf_id;
3767 ctxt.uplink_seid = vsi->uplink_seid;
3768 ctxt.connection_type = 0x1; /* regular data port */
3769 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3770 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3771 I40E_DEFAULT_TCMAP);
3772 if (ret != I40E_SUCCESS) {
3773 PMD_DRV_LOG(ERR, "Failed to configure "
3774 "TC queue mapping.");
3775 goto fail_msix_alloc;
3777 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3778 ctxt.info.valid_sections |=
3779 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3781 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3782 goto fail_msix_alloc;
3785 if (vsi->type != I40E_VSI_MAIN) {
3786 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3787 if (ret != I40E_SUCCESS) {
3788 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3789 hw->aq.asq_last_status);
3790 goto fail_msix_alloc;
3792 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3793 vsi->info.valid_sections = 0;
3794 vsi->seid = ctxt.seid;
3795 vsi->vsi_id = ctxt.vsi_number;
3796 vsi->sib_vsi_list.vsi = vsi;
3797 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3798 &vsi->sib_vsi_list, list);
3801 /* MAC/VLAN configuration */
3802 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3803 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3805 ret = i40e_vsi_add_mac(vsi, &filter);
3806 if (ret != I40E_SUCCESS) {
3807 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3808 goto fail_msix_alloc;
3811 /* Get VSI BW information */
3812 i40e_vsi_dump_bw_config(vsi);
3815 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3817 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3823 /* Configure vlan stripping on or off */
3825 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3827 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3828 struct i40e_vsi_context ctxt;
3830 int ret = I40E_SUCCESS;
3832 /* Check if it has been already on or off */
3833 if (vsi->info.valid_sections &
3834 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3836 if ((vsi->info.port_vlan_flags &
3837 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3838 return 0; /* already on */
3840 if ((vsi->info.port_vlan_flags &
3841 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3842 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3843 return 0; /* already off */
3848 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3850 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3851 vsi->info.valid_sections =
3852 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3853 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3854 vsi->info.port_vlan_flags |= vlan_flags;
3855 ctxt.seid = vsi->seid;
3856 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3857 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3859 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3860 on ? "enable" : "disable");
3866 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3868 struct rte_eth_dev_data *data = dev->data;
3871 /* Apply vlan offload setting */
3872 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3874 /* Apply double-vlan setting, not implemented yet */
3876 /* Apply pvid setting */
3877 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3878 data->dev_conf.txmode.hw_vlan_insert_pvid);
3880 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3886 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3888 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3890 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3894 i40e_update_flow_control(struct i40e_hw *hw)
3896 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3897 struct i40e_link_status link_status;
3898 uint32_t rxfc = 0, txfc = 0, reg;
3902 memset(&link_status, 0, sizeof(link_status));
3903 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3904 if (ret != I40E_SUCCESS) {
3905 PMD_DRV_LOG(ERR, "Failed to get link status information");
3906 goto write_reg; /* Disable flow control */
3909 an_info = hw->phy.link_info.an_info;
3910 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3911 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3912 ret = I40E_ERR_NOT_READY;
3913 goto write_reg; /* Disable flow control */
3916 * If link auto negotiation is enabled, flow control needs to
3917 * be configured according to it
3919 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3920 case I40E_LINK_PAUSE_RXTX:
3923 hw->fc.current_mode = I40E_FC_FULL;
3925 case I40E_AQ_LINK_PAUSE_RX:
3927 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3929 case I40E_AQ_LINK_PAUSE_TX:
3931 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3934 hw->fc.current_mode = I40E_FC_NONE;
3939 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3940 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3941 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3942 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3943 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3944 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3951 i40e_pf_setup(struct i40e_pf *pf)
3953 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3954 struct i40e_filter_control_settings settings;
3955 struct i40e_vsi *vsi;
3958 /* Clear all stats counters */
3959 pf->offset_loaded = FALSE;
3960 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3961 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3963 ret = i40e_pf_get_switch_config(pf);
3964 if (ret != I40E_SUCCESS) {
3965 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3968 if (pf->flags & I40E_FLAG_FDIR) {
3969 /* make queue allocated first, let FDIR use queue pair 0*/
3970 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3971 if (ret != I40E_FDIR_QUEUE_ID) {
3972 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3974 pf->flags &= ~I40E_FLAG_FDIR;
3977 /* main VSI setup */
3978 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3980 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3981 return I40E_ERR_NOT_READY;
3985 /* Configure filter control */
3986 memset(&settings, 0, sizeof(settings));
3987 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3988 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3989 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3990 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3992 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3993 hw->func_caps.rss_table_size);
3994 return I40E_ERR_PARAM;
3996 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3997 "size: %u\n", hw->func_caps.rss_table_size);
3998 pf->hash_lut_size = hw->func_caps.rss_table_size;
4000 /* Enable ethtype and macvlan filters */
4001 settings.enable_ethtype = TRUE;
4002 settings.enable_macvlan = TRUE;
4003 ret = i40e_set_filter_control(hw, &settings);
4005 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4008 /* Update flow control according to the auto negotiation */
4009 i40e_update_flow_control(hw);
4011 return I40E_SUCCESS;
4015 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4021 * Set or clear TX Queue Disable flags,
4022 * which is required by hardware.
4024 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4025 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4027 /* Wait until the request is finished */
4028 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4029 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4030 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4031 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4032 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4038 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4039 return I40E_SUCCESS; /* already on, skip next steps */
4041 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4042 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4044 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4045 return I40E_SUCCESS; /* already off, skip next steps */
4046 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4048 /* Write the register */
4049 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4050 /* Check the result */
4051 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4052 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4053 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4055 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4056 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4059 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4060 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4064 /* Check if it is timeout */
4065 if (j >= I40E_CHK_Q_ENA_COUNT) {
4066 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4067 (on ? "enable" : "disable"), q_idx);
4068 return I40E_ERR_TIMEOUT;
4071 return I40E_SUCCESS;
4074 /* Swith on or off the tx queues */
4076 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4078 struct rte_eth_dev_data *dev_data = pf->dev_data;
4079 struct i40e_tx_queue *txq;
4080 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4084 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4085 txq = dev_data->tx_queues[i];
4086 /* Don't operate the queue if not configured or
4087 * if starting only per queue */
4088 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4091 ret = i40e_dev_tx_queue_start(dev, i);
4093 ret = i40e_dev_tx_queue_stop(dev, i);
4094 if ( ret != I40E_SUCCESS)
4098 return I40E_SUCCESS;
4102 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4107 /* Wait until the request is finished */
4108 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4109 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4110 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4111 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4112 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4117 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4118 return I40E_SUCCESS; /* Already on, skip next steps */
4119 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4121 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4122 return I40E_SUCCESS; /* Already off, skip next steps */
4123 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4126 /* Write the register */
4127 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4128 /* Check the result */
4129 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4130 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4131 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4133 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4134 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4137 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4138 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4143 /* Check if it is timeout */
4144 if (j >= I40E_CHK_Q_ENA_COUNT) {
4145 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4146 (on ? "enable" : "disable"), q_idx);
4147 return I40E_ERR_TIMEOUT;
4150 return I40E_SUCCESS;
4152 /* Switch on or off the rx queues */
4154 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4156 struct rte_eth_dev_data *dev_data = pf->dev_data;
4157 struct i40e_rx_queue *rxq;
4158 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4162 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4163 rxq = dev_data->rx_queues[i];
4164 /* Don't operate the queue if not configured or
4165 * if starting only per queue */
4166 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4169 ret = i40e_dev_rx_queue_start(dev, i);
4171 ret = i40e_dev_rx_queue_stop(dev, i);
4172 if (ret != I40E_SUCCESS)
4176 return I40E_SUCCESS;
4179 /* Switch on or off all the rx/tx queues */
4181 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4186 /* enable rx queues before enabling tx queues */
4187 ret = i40e_dev_switch_rx_queues(pf, on);
4189 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4192 ret = i40e_dev_switch_tx_queues(pf, on);
4194 /* Stop tx queues before stopping rx queues */
4195 ret = i40e_dev_switch_tx_queues(pf, on);
4197 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4200 ret = i40e_dev_switch_rx_queues(pf, on);
4206 /* Initialize VSI for TX */
4208 i40e_dev_tx_init(struct i40e_pf *pf)
4210 struct rte_eth_dev_data *data = pf->dev_data;
4212 uint32_t ret = I40E_SUCCESS;
4213 struct i40e_tx_queue *txq;
4215 for (i = 0; i < data->nb_tx_queues; i++) {
4216 txq = data->tx_queues[i];
4217 if (!txq || !txq->q_set)
4219 ret = i40e_tx_queue_init(txq);
4220 if (ret != I40E_SUCCESS)
4223 if (ret == I40E_SUCCESS)
4224 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4230 /* Initialize VSI for RX */
4232 i40e_dev_rx_init(struct i40e_pf *pf)
4234 struct rte_eth_dev_data *data = pf->dev_data;
4235 int ret = I40E_SUCCESS;
4237 struct i40e_rx_queue *rxq;
4239 i40e_pf_config_mq_rx(pf);
4240 for (i = 0; i < data->nb_rx_queues; i++) {
4241 rxq = data->rx_queues[i];
4242 if (!rxq || !rxq->q_set)
4245 ret = i40e_rx_queue_init(rxq);
4246 if (ret != I40E_SUCCESS) {
4247 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4252 if (ret == I40E_SUCCESS)
4253 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4260 i40e_dev_rxtx_init(struct i40e_pf *pf)
4264 err = i40e_dev_tx_init(pf);
4266 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4269 err = i40e_dev_rx_init(pf);
4271 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4279 i40e_vmdq_setup(struct rte_eth_dev *dev)
4281 struct rte_eth_conf *conf = &dev->data->dev_conf;
4282 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4283 int i, err, conf_vsis, j, loop;
4284 struct i40e_vsi *vsi;
4285 struct i40e_vmdq_info *vmdq_info;
4286 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4287 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4290 * Disable interrupt to avoid message from VF. Furthermore, it will
4291 * avoid race condition in VSI creation/destroy.
4293 i40e_pf_disable_irq0(hw);
4295 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4296 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4300 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4301 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4302 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4303 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4304 pf->max_nb_vmdq_vsi);
4308 if (pf->vmdq != NULL) {
4309 PMD_INIT_LOG(INFO, "VMDQ already configured");
4313 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4314 sizeof(*vmdq_info) * conf_vsis, 0);
4316 if (pf->vmdq == NULL) {
4317 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4321 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4323 /* Create VMDQ VSI */
4324 for (i = 0; i < conf_vsis; i++) {
4325 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4326 vmdq_conf->enable_loop_back);
4328 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4332 vmdq_info = &pf->vmdq[i];
4334 vmdq_info->vsi = vsi;
4336 pf->nb_cfg_vmdq_vsi = conf_vsis;
4338 /* Configure Vlan */
4339 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4340 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4341 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4342 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4343 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4344 vmdq_conf->pool_map[i].vlan_id, j);
4346 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4347 vmdq_conf->pool_map[i].vlan_id);
4349 PMD_INIT_LOG(ERR, "Failed to add vlan");
4357 i40e_pf_enable_irq0(hw);
4362 for (i = 0; i < conf_vsis; i++)
4363 if (pf->vmdq[i].vsi == NULL)
4366 i40e_vsi_release(pf->vmdq[i].vsi);
4370 i40e_pf_enable_irq0(hw);
4375 i40e_stat_update_32(struct i40e_hw *hw,
4383 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4387 if (new_data >= *offset)
4388 *stat = (uint64_t)(new_data - *offset);
4390 *stat = (uint64_t)((new_data +
4391 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4395 i40e_stat_update_48(struct i40e_hw *hw,
4404 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4405 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4406 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4411 if (new_data >= *offset)
4412 *stat = new_data - *offset;
4414 *stat = (uint64_t)((new_data +
4415 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4417 *stat &= I40E_48_BIT_MASK;
4422 i40e_pf_disable_irq0(struct i40e_hw *hw)
4424 /* Disable all interrupt types */
4425 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4426 I40E_WRITE_FLUSH(hw);
4431 i40e_pf_enable_irq0(struct i40e_hw *hw)
4433 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4434 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4435 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4436 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4437 I40E_WRITE_FLUSH(hw);
4441 i40e_pf_config_irq0(struct i40e_hw *hw)
4443 /* read pending request and disable first */
4444 i40e_pf_disable_irq0(hw);
4445 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4446 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4447 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4449 /* Link no queues with irq0 */
4450 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4451 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4455 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4457 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4458 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4461 uint32_t index, offset, val;
4466 * Try to find which VF trigger a reset, use absolute VF id to access
4467 * since the reg is global register.
4469 for (i = 0; i < pf->vf_num; i++) {
4470 abs_vf_id = hw->func_caps.vf_base_id + i;
4471 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4472 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4473 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4474 /* VFR event occured */
4475 if (val & (0x1 << offset)) {
4478 /* Clear the event first */
4479 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4481 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4483 * Only notify a VF reset event occured,
4484 * don't trigger another SW reset
4486 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4487 if (ret != I40E_SUCCESS)
4488 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4494 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4496 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497 struct i40e_arq_event_info info;
4498 uint16_t pending, opcode;
4501 info.buf_len = I40E_AQ_BUF_SZ;
4502 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4503 if (!info.msg_buf) {
4504 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4510 ret = i40e_clean_arq_element(hw, &info, &pending);
4512 if (ret != I40E_SUCCESS) {
4513 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4514 "aq_err: %u", hw->aq.asq_last_status);
4517 opcode = rte_le_to_cpu_16(info.desc.opcode);
4520 case i40e_aqc_opc_send_msg_to_pf:
4521 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4522 i40e_pf_host_handle_vf_msg(dev,
4523 rte_le_to_cpu_16(info.desc.retval),
4524 rte_le_to_cpu_32(info.desc.cookie_high),
4525 rte_le_to_cpu_32(info.desc.cookie_low),
4530 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4535 rte_free(info.msg_buf);
4539 * Interrupt handler is registered as the alarm callback for handling LSC
4540 * interrupt in a definite of time, in order to wait the NIC into a stable
4541 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4542 * no need for link down interrupt.
4545 i40e_dev_interrupt_delayed_handler(void *param)
4547 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4551 /* read interrupt causes again */
4552 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4554 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4555 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4556 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4557 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4558 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4559 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4560 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4561 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4562 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4563 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4564 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4566 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4567 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4568 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4569 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4570 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4572 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4573 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4574 i40e_dev_handle_vfr_event(dev);
4576 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4577 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4578 i40e_dev_handle_aq_msg(dev);
4581 /* handle the link up interrupt in an alarm callback */
4582 i40e_dev_link_update(dev, 0);
4583 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4585 i40e_pf_enable_irq0(hw);
4586 rte_intr_enable(&(dev->pci_dev->intr_handle));
4590 * Interrupt handler triggered by NIC for handling
4591 * specific interrupt.
4594 * Pointer to interrupt handle.
4596 * The address of parameter (struct rte_eth_dev *) regsitered before.
4602 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4605 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4606 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4609 /* Disable interrupt */
4610 i40e_pf_disable_irq0(hw);
4612 /* read out interrupt causes */
4613 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4615 /* No interrupt event indicated */
4616 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4617 PMD_DRV_LOG(INFO, "No interrupt event");
4620 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4621 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4622 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4623 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4624 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4625 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4626 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4627 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4628 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4629 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4630 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4631 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4632 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4633 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4634 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4635 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4637 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4638 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4639 i40e_dev_handle_vfr_event(dev);
4641 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4642 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4643 i40e_dev_handle_aq_msg(dev);
4646 /* Link Status Change interrupt */
4647 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4648 #define I40E_US_PER_SECOND 1000000
4649 struct rte_eth_link link;
4651 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4652 memset(&link, 0, sizeof(link));
4653 rte_i40e_dev_atomic_read_link_status(dev, &link);
4654 i40e_dev_link_update(dev, 0);
4657 * For link up interrupt, it needs to wait 1 second to let the
4658 * hardware be a stable state. Otherwise several consecutive
4659 * interrupts can be observed.
4660 * For link down interrupt, no need to wait.
4662 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4663 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4666 _rte_eth_dev_callback_process(dev,
4667 RTE_ETH_EVENT_INTR_LSC);
4671 /* Enable interrupt */
4672 i40e_pf_enable_irq0(hw);
4673 rte_intr_enable(&(dev->pci_dev->intr_handle));
4677 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4678 struct i40e_macvlan_filter *filter,
4681 int ele_num, ele_buff_size;
4682 int num, actual_num, i;
4684 int ret = I40E_SUCCESS;
4685 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4686 struct i40e_aqc_add_macvlan_element_data *req_list;
4688 if (filter == NULL || total == 0)
4689 return I40E_ERR_PARAM;
4690 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4691 ele_buff_size = hw->aq.asq_buf_size;
4693 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4694 if (req_list == NULL) {
4695 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4696 return I40E_ERR_NO_MEMORY;
4701 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4702 memset(req_list, 0, ele_buff_size);
4704 for (i = 0; i < actual_num; i++) {
4705 (void)rte_memcpy(req_list[i].mac_addr,
4706 &filter[num + i].macaddr, ETH_ADDR_LEN);
4707 req_list[i].vlan_tag =
4708 rte_cpu_to_le_16(filter[num + i].vlan_id);
4710 switch (filter[num + i].filter_type) {
4711 case RTE_MAC_PERFECT_MATCH:
4712 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4713 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4715 case RTE_MACVLAN_PERFECT_MATCH:
4716 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4718 case RTE_MAC_HASH_MATCH:
4719 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4720 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4722 case RTE_MACVLAN_HASH_MATCH:
4723 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4726 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4727 ret = I40E_ERR_PARAM;
4731 req_list[i].queue_number = 0;
4733 req_list[i].flags = rte_cpu_to_le_16(flags);
4736 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4738 if (ret != I40E_SUCCESS) {
4739 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4743 } while (num < total);
4751 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4752 struct i40e_macvlan_filter *filter,
4755 int ele_num, ele_buff_size;
4756 int num, actual_num, i;
4758 int ret = I40E_SUCCESS;
4759 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4760 struct i40e_aqc_remove_macvlan_element_data *req_list;
4762 if (filter == NULL || total == 0)
4763 return I40E_ERR_PARAM;
4765 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4766 ele_buff_size = hw->aq.asq_buf_size;
4768 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4769 if (req_list == NULL) {
4770 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4771 return I40E_ERR_NO_MEMORY;
4776 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4777 memset(req_list, 0, ele_buff_size);
4779 for (i = 0; i < actual_num; i++) {
4780 (void)rte_memcpy(req_list[i].mac_addr,
4781 &filter[num + i].macaddr, ETH_ADDR_LEN);
4782 req_list[i].vlan_tag =
4783 rte_cpu_to_le_16(filter[num + i].vlan_id);
4785 switch (filter[num + i].filter_type) {
4786 case RTE_MAC_PERFECT_MATCH:
4787 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4788 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4790 case RTE_MACVLAN_PERFECT_MATCH:
4791 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4793 case RTE_MAC_HASH_MATCH:
4794 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4795 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4797 case RTE_MACVLAN_HASH_MATCH:
4798 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4801 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4802 ret = I40E_ERR_PARAM;
4805 req_list[i].flags = rte_cpu_to_le_16(flags);
4808 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4810 if (ret != I40E_SUCCESS) {
4811 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4815 } while (num < total);
4822 /* Find out specific MAC filter */
4823 static struct i40e_mac_filter *
4824 i40e_find_mac_filter(struct i40e_vsi *vsi,
4825 struct ether_addr *macaddr)
4827 struct i40e_mac_filter *f;
4829 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4830 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4838 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4841 uint32_t vid_idx, vid_bit;
4843 if (vlan_id > ETH_VLAN_ID_MAX)
4846 vid_idx = I40E_VFTA_IDX(vlan_id);
4847 vid_bit = I40E_VFTA_BIT(vlan_id);
4849 if (vsi->vfta[vid_idx] & vid_bit)
4856 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4857 uint16_t vlan_id, bool on)
4859 uint32_t vid_idx, vid_bit;
4861 if (vlan_id > ETH_VLAN_ID_MAX)
4864 vid_idx = I40E_VFTA_IDX(vlan_id);
4865 vid_bit = I40E_VFTA_BIT(vlan_id);
4868 vsi->vfta[vid_idx] |= vid_bit;
4870 vsi->vfta[vid_idx] &= ~vid_bit;
4874 * Find all vlan options for specific mac addr,
4875 * return with actual vlan found.
4878 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4879 struct i40e_macvlan_filter *mv_f,
4880 int num, struct ether_addr *addr)
4886 * Not to use i40e_find_vlan_filter to decrease the loop time,
4887 * although the code looks complex.
4889 if (num < vsi->vlan_num)
4890 return I40E_ERR_PARAM;
4893 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4895 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4896 if (vsi->vfta[j] & (1 << k)) {
4898 PMD_DRV_LOG(ERR, "vlan number "
4900 return I40E_ERR_PARAM;
4902 (void)rte_memcpy(&mv_f[i].macaddr,
4903 addr, ETH_ADDR_LEN);
4905 j * I40E_UINT32_BIT_SIZE + k;
4911 return I40E_SUCCESS;
4915 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4916 struct i40e_macvlan_filter *mv_f,
4921 struct i40e_mac_filter *f;
4923 if (num < vsi->mac_num)
4924 return I40E_ERR_PARAM;
4926 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4928 PMD_DRV_LOG(ERR, "buffer number not match");
4929 return I40E_ERR_PARAM;
4931 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4933 mv_f[i].vlan_id = vlan;
4934 mv_f[i].filter_type = f->mac_info.filter_type;
4938 return I40E_SUCCESS;
4942 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4945 struct i40e_mac_filter *f;
4946 struct i40e_macvlan_filter *mv_f;
4947 int ret = I40E_SUCCESS;
4949 if (vsi == NULL || vsi->mac_num == 0)
4950 return I40E_ERR_PARAM;
4952 /* Case that no vlan is set */
4953 if (vsi->vlan_num == 0)
4956 num = vsi->mac_num * vsi->vlan_num;
4958 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4960 PMD_DRV_LOG(ERR, "failed to allocate memory");
4961 return I40E_ERR_NO_MEMORY;
4965 if (vsi->vlan_num == 0) {
4966 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4967 (void)rte_memcpy(&mv_f[i].macaddr,
4968 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4969 mv_f[i].vlan_id = 0;
4973 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4974 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4975 vsi->vlan_num, &f->mac_info.mac_addr);
4976 if (ret != I40E_SUCCESS)
4982 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4990 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4992 struct i40e_macvlan_filter *mv_f;
4994 int ret = I40E_SUCCESS;
4996 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4997 return I40E_ERR_PARAM;
4999 /* If it's already set, just return */
5000 if (i40e_find_vlan_filter(vsi,vlan))
5001 return I40E_SUCCESS;
5003 mac_num = vsi->mac_num;
5006 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5007 return I40E_ERR_PARAM;
5010 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5013 PMD_DRV_LOG(ERR, "failed to allocate memory");
5014 return I40E_ERR_NO_MEMORY;
5017 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5019 if (ret != I40E_SUCCESS)
5022 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5024 if (ret != I40E_SUCCESS)
5027 i40e_set_vlan_filter(vsi, vlan, 1);
5037 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5039 struct i40e_macvlan_filter *mv_f;
5041 int ret = I40E_SUCCESS;
5044 * Vlan 0 is the generic filter for untagged packets
5045 * and can't be removed.
5047 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5048 return I40E_ERR_PARAM;
5050 /* If can't find it, just return */
5051 if (!i40e_find_vlan_filter(vsi, vlan))
5052 return I40E_ERR_PARAM;
5054 mac_num = vsi->mac_num;
5057 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5058 return I40E_ERR_PARAM;
5061 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5064 PMD_DRV_LOG(ERR, "failed to allocate memory");
5065 return I40E_ERR_NO_MEMORY;
5068 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5070 if (ret != I40E_SUCCESS)
5073 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5075 if (ret != I40E_SUCCESS)
5078 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5079 if (vsi->vlan_num == 1) {
5080 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5081 if (ret != I40E_SUCCESS)
5084 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5085 if (ret != I40E_SUCCESS)
5089 i40e_set_vlan_filter(vsi, vlan, 0);
5099 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5101 struct i40e_mac_filter *f;
5102 struct i40e_macvlan_filter *mv_f;
5103 int i, vlan_num = 0;
5104 int ret = I40E_SUCCESS;
5106 /* If it's add and we've config it, return */
5107 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5109 return I40E_SUCCESS;
5110 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5111 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5114 * If vlan_num is 0, that's the first time to add mac,
5115 * set mask for vlan_id 0.
5117 if (vsi->vlan_num == 0) {
5118 i40e_set_vlan_filter(vsi, 0, 1);
5121 vlan_num = vsi->vlan_num;
5122 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5123 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5126 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5128 PMD_DRV_LOG(ERR, "failed to allocate memory");
5129 return I40E_ERR_NO_MEMORY;
5132 for (i = 0; i < vlan_num; i++) {
5133 mv_f[i].filter_type = mac_filter->filter_type;
5134 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5138 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5139 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5140 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5141 &mac_filter->mac_addr);
5142 if (ret != I40E_SUCCESS)
5146 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5147 if (ret != I40E_SUCCESS)
5150 /* Add the mac addr into mac list */
5151 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5153 PMD_DRV_LOG(ERR, "failed to allocate memory");
5154 ret = I40E_ERR_NO_MEMORY;
5157 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5159 f->mac_info.filter_type = mac_filter->filter_type;
5160 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5171 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5173 struct i40e_mac_filter *f;
5174 struct i40e_macvlan_filter *mv_f;
5176 enum rte_mac_filter_type filter_type;
5177 int ret = I40E_SUCCESS;
5179 /* Can't find it, return an error */
5180 f = i40e_find_mac_filter(vsi, addr);
5182 return I40E_ERR_PARAM;
5184 vlan_num = vsi->vlan_num;
5185 filter_type = f->mac_info.filter_type;
5186 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5187 filter_type == RTE_MACVLAN_HASH_MATCH) {
5188 if (vlan_num == 0) {
5189 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5190 return I40E_ERR_PARAM;
5192 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5193 filter_type == RTE_MAC_HASH_MATCH)
5196 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5198 PMD_DRV_LOG(ERR, "failed to allocate memory");
5199 return I40E_ERR_NO_MEMORY;
5202 for (i = 0; i < vlan_num; i++) {
5203 mv_f[i].filter_type = filter_type;
5204 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5207 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5208 filter_type == RTE_MACVLAN_HASH_MATCH) {
5209 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5210 if (ret != I40E_SUCCESS)
5214 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5215 if (ret != I40E_SUCCESS)
5218 /* Remove the mac addr into mac list */
5219 TAILQ_REMOVE(&vsi->mac_list, f, next);
5229 /* Configure hash enable flags for RSS */
5231 i40e_config_hena(uint64_t flags)
5238 if (flags & ETH_RSS_FRAG_IPV4)
5239 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5240 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5241 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5242 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5243 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5244 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5245 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5246 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5247 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5248 if (flags & ETH_RSS_FRAG_IPV6)
5249 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5250 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5251 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5252 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5253 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5254 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5255 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5256 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5257 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5258 if (flags & ETH_RSS_L2_PAYLOAD)
5259 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5264 /* Parse the hash enable flags */
5266 i40e_parse_hena(uint64_t flags)
5268 uint64_t rss_hf = 0;
5272 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5273 rss_hf |= ETH_RSS_FRAG_IPV4;
5274 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5275 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5276 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5277 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5278 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5279 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5280 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5281 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5282 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5283 rss_hf |= ETH_RSS_FRAG_IPV6;
5284 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5285 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5286 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5287 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5288 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5289 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5290 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5291 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5292 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5293 rss_hf |= ETH_RSS_L2_PAYLOAD;
5300 i40e_pf_disable_rss(struct i40e_pf *pf)
5302 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5305 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5306 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5307 hena &= ~I40E_RSS_HENA_ALL;
5308 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5309 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5310 I40E_WRITE_FLUSH(hw);
5314 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5316 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5320 if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5324 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5325 struct i40e_aqc_get_set_rss_key_data *key_dw =
5326 (struct i40e_aqc_get_set_rss_key_data *)key;
5328 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5330 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5333 uint32_t *hash_key = (uint32_t *)key;
5336 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5337 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5338 I40E_WRITE_FLUSH(hw);
5345 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5347 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5348 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5351 if (!key || !key_len)
5354 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5355 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5356 (struct i40e_aqc_get_set_rss_key_data *)key);
5358 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5362 uint32_t *key_dw = (uint32_t *)key;
5365 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5366 key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5368 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5374 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5376 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5381 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5382 rss_conf->rss_key_len);
5386 rss_hf = rss_conf->rss_hf;
5387 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5388 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5389 hena &= ~I40E_RSS_HENA_ALL;
5390 hena |= i40e_config_hena(rss_hf);
5391 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5392 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5393 I40E_WRITE_FLUSH(hw);
5399 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5400 struct rte_eth_rss_conf *rss_conf)
5402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5404 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5407 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5408 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5409 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5410 if (rss_hf != 0) /* Enable RSS */
5412 return 0; /* Nothing to do */
5415 if (rss_hf == 0) /* Disable RSS */
5418 return i40e_hw_rss_hash_set(pf, rss_conf);
5422 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5423 struct rte_eth_rss_conf *rss_conf)
5425 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5426 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5429 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5430 &rss_conf->rss_key_len);
5432 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5433 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5434 rss_conf->rss_hf = i40e_parse_hena(hena);
5440 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5442 switch (filter_type) {
5443 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5444 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5446 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5447 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5449 case RTE_TUNNEL_FILTER_IMAC_TENID:
5450 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5452 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5453 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5455 case ETH_TUNNEL_FILTER_IMAC:
5456 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5459 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5467 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5468 struct rte_eth_tunnel_filter_conf *tunnel_filter,
5472 uint8_t tun_type = 0;
5474 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5475 struct i40e_vsi *vsi = pf->main_vsi;
5476 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
5477 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
5479 cld_filter = rte_zmalloc("tunnel_filter",
5480 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5483 if (NULL == cld_filter) {
5484 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5487 pfilter = cld_filter;
5489 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5490 sizeof(struct ether_addr));
5491 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5492 sizeof(struct ether_addr));
5494 pfilter->inner_vlan = tunnel_filter->inner_vlan;
5495 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5496 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5497 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5498 &tunnel_filter->ip_addr,
5499 sizeof(pfilter->ipaddr.v4.data));
5501 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5502 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5503 &tunnel_filter->ip_addr,
5504 sizeof(pfilter->ipaddr.v6.data));
5507 /* check tunneled type */
5508 switch (tunnel_filter->tunnel_type) {
5509 case RTE_TUNNEL_TYPE_VXLAN:
5510 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5512 case RTE_TUNNEL_TYPE_NVGRE:
5513 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5516 /* Other tunnel types is not supported. */
5517 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5518 rte_free(cld_filter);
5522 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5525 rte_free(cld_filter);
5529 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5530 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5531 pfilter->tenant_id = tunnel_filter->tenant_id;
5532 pfilter->queue_number = tunnel_filter->queue_id;
5535 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5537 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5540 rte_free(cld_filter);
5545 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5549 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5550 if (pf->vxlan_ports[i] == port)
5558 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5562 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5564 idx = i40e_get_vxlan_port_idx(pf, port);
5566 /* Check if port already exists */
5568 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5572 /* Now check if there is space to add the new port */
5573 idx = i40e_get_vxlan_port_idx(pf, 0);
5575 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5576 "not adding port %d", port);
5580 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5583 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5587 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5590 /* New port: add it and mark its index in the bitmap */
5591 pf->vxlan_ports[idx] = port;
5592 pf->vxlan_bitmap |= (1 << idx);
5594 if (!(pf->flags & I40E_FLAG_VXLAN))
5595 pf->flags |= I40E_FLAG_VXLAN;
5601 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5604 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5606 if (!(pf->flags & I40E_FLAG_VXLAN)) {
5607 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5611 idx = i40e_get_vxlan_port_idx(pf, port);
5614 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5618 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5619 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5623 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5626 pf->vxlan_ports[idx] = 0;
5627 pf->vxlan_bitmap &= ~(1 << idx);
5629 if (!pf->vxlan_bitmap)
5630 pf->flags &= ~I40E_FLAG_VXLAN;
5635 /* Add UDP tunneling port */
5637 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5638 struct rte_eth_udp_tunnel *udp_tunnel)
5641 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5643 if (udp_tunnel == NULL)
5646 switch (udp_tunnel->prot_type) {
5647 case RTE_TUNNEL_TYPE_VXLAN:
5648 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5651 case RTE_TUNNEL_TYPE_GENEVE:
5652 case RTE_TUNNEL_TYPE_TEREDO:
5653 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5658 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5666 /* Remove UDP tunneling port */
5668 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5669 struct rte_eth_udp_tunnel *udp_tunnel)
5672 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5674 if (udp_tunnel == NULL)
5677 switch (udp_tunnel->prot_type) {
5678 case RTE_TUNNEL_TYPE_VXLAN:
5679 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5681 case RTE_TUNNEL_TYPE_GENEVE:
5682 case RTE_TUNNEL_TYPE_TEREDO:
5683 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5687 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5695 /* Calculate the maximum number of contiguous PF queues that are configured */
5697 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5699 struct rte_eth_dev_data *data = pf->dev_data;
5701 struct i40e_rx_queue *rxq;
5704 for (i = 0; i < pf->lan_nb_qps; i++) {
5705 rxq = data->rx_queues[i];
5706 if (rxq && rxq->q_set)
5717 i40e_pf_config_rss(struct i40e_pf *pf)
5719 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5720 struct rte_eth_rss_conf rss_conf;
5721 uint32_t i, lut = 0;
5725 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5726 * It's necessary to calulate the actual PF queues that are configured.
5728 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5729 num = i40e_pf_calc_configured_queues_num(pf);
5730 num = i40e_align_floor(num);
5732 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5734 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5738 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5742 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5745 lut = (lut << 8) | (j & ((0x1 <<
5746 hw->func_caps.rss_table_entry_width) - 1));
5748 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5751 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5752 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5753 i40e_pf_disable_rss(pf);
5756 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5757 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5758 /* Random default keys */
5759 static uint32_t rss_key_default[] = {0x6b793944,
5760 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5761 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5762 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5764 rss_conf.rss_key = (uint8_t *)rss_key_default;
5765 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5769 return i40e_hw_rss_hash_set(pf, &rss_conf);
5773 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5774 struct rte_eth_tunnel_filter_conf *filter)
5776 if (pf == NULL || filter == NULL) {
5777 PMD_DRV_LOG(ERR, "Invalid parameter");
5781 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5782 PMD_DRV_LOG(ERR, "Invalid queue ID");
5786 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5787 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5791 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5792 (is_zero_ether_addr(filter->outer_mac))) {
5793 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5797 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5798 (is_zero_ether_addr(filter->inner_mac))) {
5799 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5807 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5810 struct rte_eth_tunnel_filter_conf *filter;
5811 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5812 int ret = I40E_SUCCESS;
5814 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5816 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5817 return I40E_ERR_PARAM;
5819 switch (filter_op) {
5820 case RTE_ETH_FILTER_NOP:
5821 if (!(pf->flags & I40E_FLAG_VXLAN))
5822 ret = I40E_NOT_SUPPORTED;
5823 case RTE_ETH_FILTER_ADD:
5824 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5826 case RTE_ETH_FILTER_DELETE:
5827 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5830 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5831 ret = I40E_ERR_PARAM;
5839 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5842 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5845 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5846 ret = i40e_pf_config_rss(pf);
5848 i40e_pf_disable_rss(pf);
5853 /* Get the symmetric hash enable configurations per port */
5855 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5857 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5859 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5862 /* Set the symmetric hash enable configurations per port */
5864 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5866 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5869 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5870 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5874 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5876 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5877 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5881 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5883 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5884 I40E_WRITE_FLUSH(hw);
5888 * Get global configurations of hash function type and symmetric hash enable
5889 * per flow type (pctype). Note that global configuration means it affects all
5890 * the ports on the same NIC.
5893 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5894 struct rte_eth_hash_global_conf *g_cfg)
5896 uint32_t reg, mask = I40E_FLOW_TYPES;
5898 enum i40e_filter_pctype pctype;
5900 memset(g_cfg, 0, sizeof(*g_cfg));
5901 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5902 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5903 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5905 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5906 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5907 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5909 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5910 if (!(mask & (1UL << i)))
5912 mask &= ~(1UL << i);
5913 /* Bit set indicats the coresponding flow type is supported */
5914 g_cfg->valid_bit_mask[0] |= (1UL << i);
5915 pctype = i40e_flowtype_to_pctype(i);
5916 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5917 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5918 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5925 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5928 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5930 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5931 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5932 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5933 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5939 * As i40e supports less than 32 flow types, only first 32 bits need to
5942 mask0 = g_cfg->valid_bit_mask[0];
5943 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5945 /* Check if any unsupported flow type configured */
5946 if ((mask0 | i40e_mask) ^ i40e_mask)
5949 if (g_cfg->valid_bit_mask[i])
5957 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5963 * Set global configurations of hash function type and symmetric hash enable
5964 * per flow type (pctype). Note any modifying global configuration will affect
5965 * all the ports on the same NIC.
5968 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5969 struct rte_eth_hash_global_conf *g_cfg)
5974 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5975 enum i40e_filter_pctype pctype;
5977 /* Check the input parameters */
5978 ret = i40e_hash_global_config_check(g_cfg);
5982 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5983 if (!(mask0 & (1UL << i)))
5985 mask0 &= ~(1UL << i);
5986 pctype = i40e_flowtype_to_pctype(i);
5987 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5988 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5989 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5992 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5993 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5995 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5996 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6000 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6001 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6003 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6004 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6008 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6010 /* Use the default, and keep it as it is */
6013 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6016 I40E_WRITE_FLUSH(hw);
6022 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6027 PMD_DRV_LOG(ERR, "Invalid pointer");
6031 switch (info->info_type) {
6032 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6033 i40e_get_symmetric_hash_enable_per_port(hw,
6034 &(info->info.enable));
6036 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6037 ret = i40e_get_hash_filter_global_config(hw,
6038 &(info->info.global_conf));
6041 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6051 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6056 PMD_DRV_LOG(ERR, "Invalid pointer");
6060 switch (info->info_type) {
6061 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6062 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
6064 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6065 ret = i40e_set_hash_filter_global_config(hw,
6066 &(info->info.global_conf));
6069 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6078 /* Operations for hash function */
6080 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
6081 enum rte_filter_op filter_op,
6084 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6087 switch (filter_op) {
6088 case RTE_ETH_FILTER_NOP:
6090 case RTE_ETH_FILTER_GET:
6091 ret = i40e_hash_filter_get(hw,
6092 (struct rte_eth_hash_filter_info *)arg);
6094 case RTE_ETH_FILTER_SET:
6095 ret = i40e_hash_filter_set(hw,
6096 (struct rte_eth_hash_filter_info *)arg);
6099 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
6109 * Configure ethertype filter, which can director packet by filtering
6110 * with mac address and ether_type or only ether_type
6113 i40e_ethertype_filter_set(struct i40e_pf *pf,
6114 struct rte_eth_ethertype_filter *filter,
6117 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6118 struct i40e_control_filter_stats stats;
6122 if (filter->queue >= pf->dev_data->nb_rx_queues) {
6123 PMD_DRV_LOG(ERR, "Invalid queue ID");
6126 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6127 filter->ether_type == ETHER_TYPE_IPv6) {
6128 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6129 " control packet filter.", filter->ether_type);
6132 if (filter->ether_type == ETHER_TYPE_VLAN)
6133 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
6136 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
6137 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
6138 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
6139 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
6140 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
6142 memset(&stats, 0, sizeof(stats));
6143 ret = i40e_aq_add_rem_control_packet_filter(hw,
6144 filter->mac_addr.addr_bytes,
6145 filter->ether_type, flags,
6147 filter->queue, add, &stats, NULL);
6149 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
6150 " mac_etype_used = %u, etype_used = %u,"
6151 " mac_etype_free = %u, etype_free = %u\n",
6152 ret, stats.mac_etype_used, stats.etype_used,
6153 stats.mac_etype_free, stats.etype_free);
6160 * Handle operations for ethertype filter.
6163 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
6164 enum rte_filter_op filter_op,
6167 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6170 if (filter_op == RTE_ETH_FILTER_NOP)
6174 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6179 switch (filter_op) {
6180 case RTE_ETH_FILTER_ADD:
6181 ret = i40e_ethertype_filter_set(pf,
6182 (struct rte_eth_ethertype_filter *)arg,
6185 case RTE_ETH_FILTER_DELETE:
6186 ret = i40e_ethertype_filter_set(pf,
6187 (struct rte_eth_ethertype_filter *)arg,
6191 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6199 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
6200 enum rte_filter_type filter_type,
6201 enum rte_filter_op filter_op,
6209 switch (filter_type) {
6210 case RTE_ETH_FILTER_HASH:
6211 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
6213 case RTE_ETH_FILTER_MACVLAN:
6214 ret = i40e_mac_filter_handle(dev, filter_op, arg);
6216 case RTE_ETH_FILTER_ETHERTYPE:
6217 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
6219 case RTE_ETH_FILTER_TUNNEL:
6220 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
6222 case RTE_ETH_FILTER_FDIR:
6223 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
6226 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6236 * As some registers wouldn't be reset unless a global hardware reset,
6237 * hardware initialization is needed to put those registers into an
6238 * expected initial state.
6241 i40e_hw_init(struct i40e_hw *hw)
6243 /* clear the PF Queue Filter control register */
6244 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
6246 /* Disable symmetric hash per port */
6247 i40e_set_symmetric_hash_enable_per_port(hw, 0);
6250 enum i40e_filter_pctype
6251 i40e_flowtype_to_pctype(uint16_t flow_type)
6253 static const enum i40e_filter_pctype pctype_table[] = {
6254 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
6255 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
6256 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
6257 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
6258 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
6259 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
6260 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
6261 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
6262 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
6263 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
6264 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
6265 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
6266 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
6267 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
6268 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
6269 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
6270 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
6271 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
6272 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
6275 return pctype_table[flow_type];
6279 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
6281 static const uint16_t flowtype_table[] = {
6282 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
6283 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6284 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
6285 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6286 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
6287 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6288 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
6289 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6290 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
6291 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
6292 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6293 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
6294 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6295 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
6296 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6297 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
6298 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6299 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
6300 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
6303 return flowtype_table[pctype];
6307 * On X710, performance number is far from the expectation on recent firmware
6308 * versions; on XL710, performance number is also far from the expectation on
6309 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
6310 * mode is enabled and port MAC address is equal to the packet destination MAC
6311 * address. The fix for this issue may not be integrated in the following
6312 * firmware version. So the workaround in software driver is needed. It needs
6313 * to modify the initial values of 3 internal only registers for both X710 and
6314 * XL710. Note that the values for X710 or XL710 could be different, and the
6315 * workaround can be removed when it is fixed in firmware in the future.
6318 /* For both X710 and XL710 */
6319 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
6320 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
6322 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
6323 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
6326 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
6328 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
6329 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
6332 i40e_configure_registers(struct i40e_hw *hw)
6338 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
6339 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
6340 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
6346 for (i = 0; i < RTE_DIM(reg_table); i++) {
6347 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
6348 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
6350 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
6353 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
6356 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6359 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6363 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6364 reg_table[i].addr, reg);
6365 if (reg == reg_table[i].val)
6368 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6369 reg_table[i].val, NULL);
6371 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6372 "address of 0x%"PRIx32, reg_table[i].val,
6376 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6377 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6381 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
6382 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
6383 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
6384 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6386 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6391 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6392 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6396 /* Configure for double VLAN RX stripping */
6397 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6398 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6399 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6400 ret = i40e_aq_debug_write_register(hw,
6401 I40E_VSI_TSR(vsi->vsi_id),
6404 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6406 return I40E_ERR_CONFIG;
6410 /* Configure for double VLAN TX insertion */
6411 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6412 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6413 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6414 ret = i40e_aq_debug_write_register(hw,
6415 I40E_VSI_L2TAGSTXVALID(
6416 vsi->vsi_id), reg, NULL);
6418 PMD_DRV_LOG(ERR, "Failed to update "
6419 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6420 return I40E_ERR_CONFIG;
6428 * i40e_aq_add_mirror_rule
6429 * @hw: pointer to the hardware structure
6430 * @seid: VEB seid to add mirror rule to
6431 * @dst_id: destination vsi seid
6432 * @entries: Buffer which contains the entities to be mirrored
6433 * @count: number of entities contained in the buffer
6434 * @rule_id:the rule_id of the rule to be added
6436 * Add a mirror rule for a given veb.
6439 static enum i40e_status_code
6440 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6441 uint16_t seid, uint16_t dst_id,
6442 uint16_t rule_type, uint16_t *entries,
6443 uint16_t count, uint16_t *rule_id)
6445 struct i40e_aq_desc desc;
6446 struct i40e_aqc_add_delete_mirror_rule cmd;
6447 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6448 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6451 enum i40e_status_code status;
6453 i40e_fill_default_direct_cmd_desc(&desc,
6454 i40e_aqc_opc_add_mirror_rule);
6455 memset(&cmd, 0, sizeof(cmd));
6457 buff_len = sizeof(uint16_t) * count;
6458 desc.datalen = rte_cpu_to_le_16(buff_len);
6460 desc.flags |= rte_cpu_to_le_16(
6461 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6462 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6463 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6464 cmd.num_entries = rte_cpu_to_le_16(count);
6465 cmd.seid = rte_cpu_to_le_16(seid);
6466 cmd.destination = rte_cpu_to_le_16(dst_id);
6468 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6469 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6470 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6472 " mirror_rules_used = %u, mirror_rules_free = %u,",
6473 hw->aq.asq_last_status, resp->rule_id,
6474 resp->mirror_rules_used, resp->mirror_rules_free);
6475 *rule_id = rte_le_to_cpu_16(resp->rule_id);
6481 * i40e_aq_del_mirror_rule
6482 * @hw: pointer to the hardware structure
6483 * @seid: VEB seid to add mirror rule to
6484 * @entries: Buffer which contains the entities to be mirrored
6485 * @count: number of entities contained in the buffer
6486 * @rule_id:the rule_id of the rule to be delete
6488 * Delete a mirror rule for a given veb.
6491 static enum i40e_status_code
6492 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6493 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6494 uint16_t count, uint16_t rule_id)
6496 struct i40e_aq_desc desc;
6497 struct i40e_aqc_add_delete_mirror_rule cmd;
6498 uint16_t buff_len = 0;
6499 enum i40e_status_code status;
6502 i40e_fill_default_direct_cmd_desc(&desc,
6503 i40e_aqc_opc_delete_mirror_rule);
6504 memset(&cmd, 0, sizeof(cmd));
6505 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6506 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6508 cmd.num_entries = count;
6509 buff_len = sizeof(uint16_t) * count;
6510 desc.datalen = rte_cpu_to_le_16(buff_len);
6511 buff = (void *)entries;
6513 /* rule id is filled in destination field for deleting mirror rule */
6514 cmd.destination = rte_cpu_to_le_16(rule_id);
6516 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6517 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6518 cmd.seid = rte_cpu_to_le_16(seid);
6520 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6521 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6527 * i40e_mirror_rule_set
6528 * @dev: pointer to the hardware structure
6529 * @mirror_conf: mirror rule info
6530 * @sw_id: mirror rule's sw_id
6531 * @on: enable/disable
6533 * set a mirror rule.
6537 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6538 struct rte_eth_mirror_conf *mirror_conf,
6539 uint8_t sw_id, uint8_t on)
6541 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6542 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6543 struct i40e_mirror_rule *it, *mirr_rule = NULL;
6544 struct i40e_mirror_rule *parent = NULL;
6545 uint16_t seid, dst_seid, rule_id;
6549 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6551 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6552 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6553 " without veb or vfs.");
6556 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6557 PMD_DRV_LOG(ERR, "mirror table is full.");
6560 if (mirror_conf->dst_pool > pf->vf_num) {
6561 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6562 mirror_conf->dst_pool);
6566 seid = pf->main_vsi->veb->seid;
6568 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6569 if (sw_id <= it->index) {
6575 if (mirr_rule && sw_id == mirr_rule->index) {
6577 PMD_DRV_LOG(ERR, "mirror rule exists.");
6580 ret = i40e_aq_del_mirror_rule(hw, seid,
6581 mirr_rule->rule_type,
6583 mirr_rule->num_entries, mirr_rule->id);
6585 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6586 " ret = %d, aq_err = %d.",
6587 ret, hw->aq.asq_last_status);
6590 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6591 rte_free(mirr_rule);
6592 pf->nb_mirror_rule--;
6596 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6600 mirr_rule = rte_zmalloc("i40e_mirror_rule",
6601 sizeof(struct i40e_mirror_rule) , 0);
6603 PMD_DRV_LOG(ERR, "failed to allocate memory");
6604 return I40E_ERR_NO_MEMORY;
6606 switch (mirror_conf->rule_type) {
6607 case ETH_MIRROR_VLAN:
6608 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6609 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6610 mirr_rule->entries[j] =
6611 mirror_conf->vlan.vlan_id[i];
6616 PMD_DRV_LOG(ERR, "vlan is not specified.");
6617 rte_free(mirr_rule);
6620 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6622 case ETH_MIRROR_VIRTUAL_POOL_UP:
6623 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6624 /* check if the specified pool bit is out of range */
6625 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6626 PMD_DRV_LOG(ERR, "pool mask is out of range.");
6627 rte_free(mirr_rule);
6630 for (i = 0, j = 0; i < pf->vf_num; i++) {
6631 if (mirror_conf->pool_mask & (1ULL << i)) {
6632 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6636 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6637 /* add pf vsi to entries */
6638 mirr_rule->entries[j] = pf->main_vsi_seid;
6642 PMD_DRV_LOG(ERR, "pool is not specified.");
6643 rte_free(mirr_rule);
6646 /* egress and ingress in aq commands means from switch but not port */
6647 mirr_rule->rule_type =
6648 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6649 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6650 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6652 case ETH_MIRROR_UPLINK_PORT:
6653 /* egress and ingress in aq commands means from switch but not port*/
6654 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6656 case ETH_MIRROR_DOWNLINK_PORT:
6657 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6660 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6661 mirror_conf->rule_type);
6662 rte_free(mirr_rule);
6666 /* If the dst_pool is equal to vf_num, consider it as PF */
6667 if (mirror_conf->dst_pool == pf->vf_num)
6668 dst_seid = pf->main_vsi_seid;
6670 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6672 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6673 mirr_rule->rule_type, mirr_rule->entries,
6676 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6677 " ret = %d, aq_err = %d.",
6678 ret, hw->aq.asq_last_status);
6679 rte_free(mirr_rule);
6683 mirr_rule->index = sw_id;
6684 mirr_rule->num_entries = j;
6685 mirr_rule->id = rule_id;
6686 mirr_rule->dst_vsi_seid = dst_seid;
6689 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6691 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6693 pf->nb_mirror_rule++;
6698 * i40e_mirror_rule_reset
6699 * @dev: pointer to the device
6700 * @sw_id: mirror rule's sw_id
6702 * reset a mirror rule.
6706 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6710 struct i40e_mirror_rule *it, *mirr_rule = NULL;
6714 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6716 seid = pf->main_vsi->veb->seid;
6718 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6719 if (sw_id == it->index) {
6725 ret = i40e_aq_del_mirror_rule(hw, seid,
6726 mirr_rule->rule_type,
6728 mirr_rule->num_entries, mirr_rule->id);
6730 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6731 " status = %d, aq_err = %d.",
6732 ret, hw->aq.asq_last_status);
6735 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6736 rte_free(mirr_rule);
6737 pf->nb_mirror_rule--;
6739 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6746 i40e_timesync_enable(struct rte_eth_dev *dev)
6748 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6749 struct rte_eth_link *link = &dev->data->dev_link;
6750 uint32_t tsync_ctl_l;
6751 uint32_t tsync_ctl_h;
6752 uint32_t tsync_inc_l;
6753 uint32_t tsync_inc_h;
6755 switch (link->link_speed) {
6756 case ETH_LINK_SPEED_40G:
6757 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6758 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6760 case ETH_LINK_SPEED_10G:
6761 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6762 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6764 case ETH_LINK_SPEED_1000:
6765 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6766 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6773 /* Clear timesync registers. */
6774 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6775 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6776 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6777 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6778 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6779 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6780 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6782 /* Set the timesync increment value. */
6783 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6784 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6786 /* Enable timestamping of PTP packets. */
6787 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6788 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6790 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6791 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6792 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6794 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6795 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6801 i40e_timesync_disable(struct rte_eth_dev *dev)
6803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6804 uint32_t tsync_ctl_l;
6805 uint32_t tsync_ctl_h;
6807 /* Disable timestamping of transmitted PTP packets. */
6808 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6809 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6811 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6812 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6814 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6815 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6817 /* Set the timesync increment value. */
6818 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6819 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6825 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6826 struct timespec *timestamp, uint32_t flags)
6828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6829 uint32_t sync_status;
6832 uint32_t index = flags & 0x03;
6834 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6835 if ((sync_status & (1 << index)) == 0)
6838 rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6839 rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6841 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6842 timestamp->tv_nsec = 0;
6848 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6849 struct timespec *timestamp)
6851 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6852 uint32_t sync_status;
6856 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6857 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6860 tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6861 tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6863 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6864 timestamp->tv_nsec = 0;
6870 * i40e_parse_dcb_configure - parse dcb configure from user
6871 * @dev: the device being configured
6872 * @dcb_cfg: pointer of the result of parse
6873 * @*tc_map: bit map of enabled traffic classes
6875 * Returns 0 on success, negative value on failure
6878 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
6879 struct i40e_dcbx_config *dcb_cfg,
6882 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
6883 uint8_t i, tc_bw, bw_lf;
6885 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
6887 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6888 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
6889 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
6893 /* assume each tc has the same bw */
6894 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
6895 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6896 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
6897 /* to ensure the sum of tcbw is equal to 100 */
6898 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
6899 for (i = 0; i < bw_lf; i++)
6900 dcb_cfg->etscfg.tcbwtable[i]++;
6902 /* assume each tc has the same Transmission Selection Algorithm */
6903 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6904 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
6906 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
6907 dcb_cfg->etscfg.prioritytable[i] =
6908 dcb_rx_conf->dcb_tc[i];
6910 /* FW needs one App to configure HW */
6911 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
6912 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
6913 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
6914 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
6916 if (dcb_rx_conf->nb_tcs == 0)
6917 *tc_map = 1; /* tc0 only */
6919 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
6921 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
6922 dcb_cfg->pfc.willing = 0;
6923 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
6924 dcb_cfg->pfc.pfcenable = *tc_map;
6930 * i40e_vsi_get_bw_info - Query VSI BW Information
6931 * @vsi: the VSI being queried
6933 * Returns 0 on success, negative value on failure
6936 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
6938 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
6939 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
6940 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6944 /* Get the VSI level BW configuration */
6945 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
6948 "couldn't get PF vsi bw config, err %s aq_err %s\n",
6949 i40e_stat_str(hw, ret),
6950 i40e_aq_str(hw, hw->aq.asq_last_status));
6954 /* Get the VSI level BW configuration per TC */
6955 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6959 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
6960 i40e_stat_str(hw, ret),
6961 i40e_aq_str(hw, hw->aq.asq_last_status));
6965 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
6966 PMD_INIT_LOG(WARNING,
6967 "Enabled TCs mismatch from querying VSI BW info"
6968 " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
6969 bw_ets_config.tc_valid_bits);
6970 /* Still continuing */
6973 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
6974 vsi->bw_info.bw_max_quanta = bw_config.max_bw;
6975 tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
6976 (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
6977 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6978 vsi->bw_info.bw_ets_share_credits[i] =
6979 bw_ets_config.share_credits[i];
6980 vsi->bw_info.bw_ets_limit_credits[i] =
6981 rte_le_to_cpu_16(bw_ets_config.credits[i]);
6982 /* 3 bits out of 4 for each TC */
6983 vsi->bw_info.bw_ets_max_quanta[i] =
6984 (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
6986 "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
6987 __func__, vsi->seid, i, bw_config.qs_handles[i]);
6994 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
6995 struct i40e_aqc_vsi_properties_data *info,
6996 uint8_t enabled_tcmap)
6998 int ret, i, total_tc = 0;
6999 uint16_t qpnum_per_tc, bsf, qp_idx;
7000 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
7002 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
7003 if (ret != I40E_SUCCESS)
7006 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7007 if (enabled_tcmap & (1 << i))
7012 vsi->enabled_tc = enabled_tcmap;
7014 qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
7015 /* Number of queues per enabled TC */
7016 if (qpnum_per_tc == 0) {
7017 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
7018 return I40E_ERR_INVALID_QP_ID;
7020 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
7022 bsf = rte_bsf32(qpnum_per_tc);
7025 * Configure TC and queue mapping parameters, for enabled TC,
7026 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
7027 * default queue will serve it.
7030 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7031 if (vsi->enabled_tc & (1 << i)) {
7032 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
7033 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
7034 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
7035 qp_idx += qpnum_per_tc;
7037 info->tc_mapping[i] = 0;
7040 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
7041 if (vsi->type == I40E_VSI_SRIOV) {
7042 info->mapping_flags |=
7043 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
7044 for (i = 0; i < vsi->nb_qps; i++)
7045 info->queue_mapping[i] =
7046 rte_cpu_to_le_16(vsi->base_queue + i);
7048 info->mapping_flags |=
7049 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
7050 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
7052 info->valid_sections |=
7053 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
7055 return I40E_SUCCESS;
7059 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
7060 * @vsi: VSI to be configured
7061 * @tc_map: enabled TC bitmap
7063 * Returns 0 on success, negative value on failure
7066 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
7068 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
7069 struct i40e_vsi_context ctxt;
7070 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7074 /* Check if enabled_tc is same as existing or new TCs */
7075 if (vsi->enabled_tc == tc_map)
7078 /* configure tc bandwidth */
7079 memset(&bw_data, 0, sizeof(bw_data));
7080 bw_data.tc_valid_bits = tc_map;
7081 /* Enable ETS TCs with equal BW Share for now across all VSIs */
7082 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7083 if (tc_map & BIT_ULL(i))
7084 bw_data.tc_bw_credits[i] = 1;
7086 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
7088 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
7089 " per TC failed = %d",
7090 hw->aq.asq_last_status);
7093 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
7094 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
7096 /* Update Queue Pairs Mapping for currently enabled UPs */
7097 ctxt.seid = vsi->seid;
7098 ctxt.pf_num = hw->pf_id;
7100 ctxt.uplink_seid = vsi->uplink_seid;
7101 ctxt.info = vsi->info;
7103 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
7107 /* Update the VSI after updating the VSI queue-mapping information */
7108 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7110 PMD_INIT_LOG(ERR, "Failed to configure "
7111 "TC queue mapping = %d",
7112 hw->aq.asq_last_status);
7115 /* update the local VSI info with updated queue map */
7116 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
7117 sizeof(vsi->info.tc_mapping));
7118 (void)rte_memcpy(&vsi->info.queue_mapping,
7119 &ctxt.info.queue_mapping,
7120 sizeof(vsi->info.queue_mapping));
7121 vsi->info.mapping_flags = ctxt.info.mapping_flags;
7122 vsi->info.valid_sections = 0;
7124 /* Update current VSI BW information */
7125 ret = i40e_vsi_get_bw_info(vsi);
7128 "Failed updating vsi bw info, err %s aq_err %s",
7129 i40e_stat_str(hw, ret),
7130 i40e_aq_str(hw, hw->aq.asq_last_status));
7134 vsi->enabled_tc = tc_map;
7141 * i40e_dcb_hw_configure - program the dcb setting to hw
7142 * @pf: pf the configuration is taken on
7143 * @new_cfg: new configuration
7144 * @tc_map: enabled TC bitmap
7146 * Returns 0 on success, negative value on failure
7148 static enum i40e_status_code
7149 i40e_dcb_hw_configure(struct i40e_pf *pf,
7150 struct i40e_dcbx_config *new_cfg,
7153 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7154 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
7155 struct i40e_vsi *main_vsi = pf->main_vsi;
7156 struct i40e_vsi_list *vsi_list;
7160 /* Use the FW API if FW > v4.4*/
7161 if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
7162 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
7163 " to configure DCB");
7164 return I40E_ERR_FIRMWARE_API_VERSION;
7167 /* Check if need reconfiguration */
7168 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
7169 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
7170 return I40E_SUCCESS;
7173 /* Copy the new config to the current config */
7174 *old_cfg = *new_cfg;
7175 old_cfg->etsrec = old_cfg->etscfg;
7176 ret = i40e_set_dcb_config(hw);
7179 "Set DCB Config failed, err %s aq_err %s\n",
7180 i40e_stat_str(hw, ret),
7181 i40e_aq_str(hw, hw->aq.asq_last_status));
7184 /* set receive Arbiter to RR mode and ETS scheme by default */
7185 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
7186 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
7187 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
7188 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
7189 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
7190 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
7191 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
7192 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
7193 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
7194 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
7195 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
7196 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
7197 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
7199 /* get local mib to check whether it is configured correctly */
7201 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
7202 /* Get Local DCB Config */
7203 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
7204 &hw->local_dcbx_config);
7206 /* Update each VSI */
7207 i40e_vsi_config_tc(main_vsi, tc_map);
7208 if (main_vsi->veb) {
7209 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
7210 /* Beside main VSI, only enable default
7213 ret = i40e_vsi_config_tc(vsi_list->vsi,
7214 I40E_DEFAULT_TCMAP);
7216 PMD_INIT_LOG(WARNING,
7217 "Failed configuring TC for VSI seid=%d\n",
7218 vsi_list->vsi->seid);
7222 return I40E_SUCCESS;
7226 * i40e_dcb_init_configure - initial dcb config
7227 * @dev: device being configured
7228 * @sw_dcb: indicate whether dcb is sw configured or hw offload
7230 * Returns 0 on success, negative value on failure
7233 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
7235 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7236 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7239 if ((pf->flags & I40E_FLAG_DCB) == 0) {
7240 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7244 /* DCB initialization:
7245 * Update DCB configuration from the Firmware and configure
7246 * LLDP MIB change event.
7248 if (sw_dcb == TRUE) {
7249 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
7250 if (ret != I40E_SUCCESS)
7251 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
7253 ret = i40e_init_dcb(hw);
7254 /* if sw_dcb, lldp agent is stopped, the return from
7255 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
7258 if (ret != I40E_SUCCESS &&
7259 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
7260 memset(&hw->local_dcbx_config, 0,
7261 sizeof(struct i40e_dcbx_config));
7262 /* set dcb default configuration */
7263 hw->local_dcbx_config.etscfg.willing = 0;
7264 hw->local_dcbx_config.etscfg.maxtcs = 0;
7265 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
7266 hw->local_dcbx_config.etscfg.tsatable[0] =
7268 hw->local_dcbx_config.etsrec =
7269 hw->local_dcbx_config.etscfg;
7270 hw->local_dcbx_config.pfc.willing = 0;
7271 hw->local_dcbx_config.pfc.pfccap =
7272 I40E_MAX_TRAFFIC_CLASS;
7273 /* FW needs one App to configure HW */
7274 hw->local_dcbx_config.numapps = 1;
7275 hw->local_dcbx_config.app[0].selector =
7276 I40E_APP_SEL_ETHTYPE;
7277 hw->local_dcbx_config.app[0].priority = 3;
7278 hw->local_dcbx_config.app[0].protocolid =
7279 I40E_APP_PROTOID_FCOE;
7280 ret = i40e_set_dcb_config(hw);
7282 PMD_INIT_LOG(ERR, "default dcb config fails."
7283 " err = %d, aq_err = %d.", ret,
7284 hw->aq.asq_last_status);
7288 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7289 " aq_err = %d.", ret,
7290 hw->aq.asq_last_status);
7294 ret = i40e_aq_start_lldp(hw, NULL);
7295 if (ret != I40E_SUCCESS)
7296 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
7298 ret = i40e_init_dcb(hw);
7300 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
7301 PMD_INIT_LOG(ERR, "HW doesn't support"
7306 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7307 " aq_err = %d.", ret,
7308 hw->aq.asq_last_status);
7316 * i40e_dcb_setup - setup dcb related config
7317 * @dev: device being configured
7319 * Returns 0 on success, negative value on failure
7322 i40e_dcb_setup(struct rte_eth_dev *dev)
7324 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7325 struct i40e_dcbx_config dcb_cfg;
7329 if ((pf->flags & I40E_FLAG_DCB) == 0) {
7330 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7334 if (pf->vf_num != 0 ||
7335 (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
7336 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
7338 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
7340 PMD_INIT_LOG(ERR, "invalid dcb config");
7343 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
7345 PMD_INIT_LOG(ERR, "dcb sw configure fails");
7352 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
7353 struct rte_eth_dcb_info *dcb_info)
7355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7356 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7357 struct i40e_vsi *vsi = pf->main_vsi;
7358 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
7359 uint16_t bsf, tc_mapping;
7362 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7363 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
7365 dcb_info->nb_tcs = 1;
7366 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7367 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
7368 for (i = 0; i < dcb_info->nb_tcs; i++)
7369 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
7371 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7372 if (vsi->enabled_tc & (1 << i)) {
7373 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
7374 /* only main vsi support multi TCs */
7375 dcb_info->tc_queue.tc_rxq[0][i].base =
7376 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
7377 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
7378 dcb_info->tc_queue.tc_txq[0][i].base =
7379 dcb_info->tc_queue.tc_rxq[0][i].base;
7380 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
7381 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
7382 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
7383 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
7384 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;