1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
30 #include <rte_os_shim.h>
32 #include "i40e_logs.h"
33 #include "base/i40e_prototype.h"
34 #include "base/i40e_adminq_cmd.h"
35 #include "base/i40e_type.h"
36 #include "base/i40e_register.h"
37 #include "base/i40e_dcb.h"
38 #include "i40e_ethdev.h"
39 #include "i40e_rxtx.h"
41 #include "i40e_regs.h"
42 #include "rte_pmd_i40e.h"
43 #include "i40e_hash.h"
45 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
46 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
47 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
49 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
51 #define I40E_CLEAR_PXE_WAIT_MS 200
52 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
53 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
55 /* Maximun number of capability elements */
56 #define I40E_MAX_CAP_ELE_NUM 128
58 /* Wait count and interval */
59 #define I40E_CHK_Q_ENA_COUNT 1000
60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
62 /* Maximun number of VSI */
63 #define I40E_MAX_NUM_VSIS (384UL)
65 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
67 /* Flow control default timer */
68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
70 /* Flow control enable fwd bit */
71 #define I40E_PRTMAC_FWD_CTRL 0x00000001
73 /* Receive Packet Buffer size */
74 #define I40E_RXPBSIZE (968 * 1024)
77 #define I40E_KILOSHIFT 10
79 /* Flow control default high water */
80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
82 /* Flow control default low water */
83 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
85 /* Receive Average Packet Size in Byte*/
86 #define I40E_PACKET_AVERAGE_SIZE 128
88 /* Mask of PF interrupt causes */
89 #define I40E_PFINT_ICR0_ENA_MASK ( \
90 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
92 I40E_PFINT_ICR0_ENA_GRST_MASK | \
93 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
94 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
95 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
96 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
97 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
98 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
100 #define I40E_FLOW_TYPES ( \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
106 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
110 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
111 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
113 /* Additional timesync values. */
114 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
115 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
116 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
117 #define I40E_PRTTSYN_TSYNENA 0x80000000
118 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
119 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
122 * Below are values for writing un-exposed registers suggested
125 /* Destination MAC address */
126 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
127 /* Source MAC address */
128 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
130 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
132 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
133 /* Single VLAN tag in the inner L2 header */
134 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
135 /* Source IPv4 address */
136 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
137 /* Destination IPv4 address */
138 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
139 /* Source IPv4 address for X722 */
140 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
141 /* Destination IPv4 address for X722 */
142 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
143 /* IPv4 Protocol for X722 */
144 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
145 /* IPv4 Time to Live for X722 */
146 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
147 /* IPv4 Type of Service (TOS) */
148 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
150 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
151 /* IPv4 Time to Live */
152 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
153 /* Source IPv6 address */
154 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
155 /* Destination IPv6 address */
156 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
157 /* IPv6 Traffic Class (TC) */
158 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
159 /* IPv6 Next Header */
160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
164 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
165 /* Destination L4 port */
166 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
167 /* SCTP verification tag */
168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
171 /* Source port of tunneling UDP */
172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
173 /* Destination port of tunneling UDP */
174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
175 /* UDP Tunneling ID, NVGRE/GRE key */
176 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
177 /* Last ether type */
178 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
179 /* Tunneling outer destination IPv4 address */
180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
181 /* Tunneling outer destination IPv6 address */
182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
183 /* 1st word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
185 /* 2nd word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
187 /* 3rd word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
189 /* 4th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
191 /* 5th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
193 /* 6th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
195 /* 7th word of flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
197 /* 8th word of flex payload */
198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
199 /* all 8 words flex payload */
200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
201 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
203 #define I40E_TRANSLATE_INSET 0
204 #define I40E_TRANSLATE_REG 1
206 #define I40E_INSET_IPV4_TOS_MASK 0x0000FF00UL
207 #define I40E_INSET_IPV4_TTL_MASK 0x000000FFUL
208 #define I40E_INSET_IPV4_PROTO_MASK 0x0000FF00UL
209 #define I40E_INSET_IPV6_TC_MASK 0x0000F00FUL
210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x0000FF00UL
211 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000000FFUL
213 /* PCI offset for querying capability */
214 #define PCI_DEV_CAP_REG 0xA4
215 /* PCI offset for enabling/disabling Extended Tag */
216 #define PCI_DEV_CTRL_REG 0xA8
217 /* Bit mask of Extended Tag capability */
218 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
219 /* Bit shift of Extended Tag enable/disable */
220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
221 /* Bit mask of Extended Tag enable/disable */
222 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
224 #define I40E_GLQF_PIT_IPV4_START 2
225 #define I40E_GLQF_PIT_IPV4_COUNT 2
226 #define I40E_GLQF_PIT_IPV6_START 4
227 #define I40E_GLQF_PIT_IPV6_COUNT 2
229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
230 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
231 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
234 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
235 I40E_GLQF_PIT_DEST_OFF_SHIFT)
237 #define I40E_GLQF_PIT_FSIZE_GET(a) (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
238 I40E_GLQF_PIT_FSIZE_SHIFT)
240 #define I40E_GLQF_PIT_BUILD(off, mask) (((off) << 16) | (mask))
241 #define I40E_FDIR_FIELD_OFFSET(a) ((a) >> 1)
243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
245 static int i40e_dev_configure(struct rte_eth_dev *dev);
246 static int i40e_dev_start(struct rte_eth_dev *dev);
247 static int i40e_dev_stop(struct rte_eth_dev *dev);
248 static int i40e_dev_close(struct rte_eth_dev *dev);
249 static int i40e_dev_reset(struct rte_eth_dev *dev);
250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
259 struct rte_eth_xstat *xstats, unsigned n);
260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
261 struct rte_eth_xstat_name *xstats_names,
263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
265 char *fw_version, size_t fw_size);
266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
267 struct rte_eth_dev_info *dev_info);
268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
272 enum rte_vlan_type vlan_type,
274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
282 struct rte_eth_fc_conf *fc_conf);
283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
284 struct rte_eth_fc_conf *fc_conf);
285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
286 struct rte_eth_pfc_conf *pfc_conf);
287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
288 struct rte_ether_addr *mac_addr,
291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
293 struct rte_eth_rss_reta_entry64 *reta_conf,
295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
296 struct rte_eth_rss_reta_entry64 *reta_conf,
299 static int i40e_get_cap(struct i40e_hw *hw);
300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
301 static int i40e_pf_setup(struct i40e_pf *pf);
302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
306 bool offset_loaded, uint64_t *offset, uint64_t *stat);
307 static void i40e_stat_update_48(struct i40e_hw *hw,
313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
314 static void i40e_dev_interrupt_handler(void *param);
315 static void i40e_dev_alarm_handler(void *param);
316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
317 uint32_t base, uint32_t num);
318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
324 static int i40e_veb_release(struct i40e_veb *veb);
325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
326 struct i40e_vsi *vsi);
327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
329 struct i40e_macvlan_filter *mv_f,
332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
334 struct rte_eth_rss_conf *rss_conf);
335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
336 struct rte_eth_rss_conf *rss_conf);
337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
338 struct rte_eth_udp_tunnel *udp_tunnel);
339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
340 struct rte_eth_udp_tunnel *udp_tunnel);
341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
343 const struct rte_flow_ops **ops);
344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
347 static void i40e_configure_registers(struct i40e_hw *hw);
348 static void i40e_hw_init(struct rte_eth_dev *dev);
349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
350 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
356 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
357 struct rte_eth_mirror_conf *mirror_conf,
358 uint8_t sw_id, uint8_t on);
359 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
361 static int i40e_timesync_enable(struct rte_eth_dev *dev);
362 static int i40e_timesync_disable(struct rte_eth_dev *dev);
363 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp,
366 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
370 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
372 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
373 struct timespec *timestamp);
374 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
375 const struct timespec *timestamp);
377 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
379 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
382 static int i40e_get_regs(struct rte_eth_dev *dev,
383 struct rte_dev_reg_info *regs);
385 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
387 static int i40e_get_eeprom(struct rte_eth_dev *dev,
388 struct rte_dev_eeprom_info *eeprom);
390 static int i40e_get_module_info(struct rte_eth_dev *dev,
391 struct rte_eth_dev_module_info *modinfo);
392 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
393 struct rte_dev_eeprom_info *info);
395 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
396 struct rte_ether_addr *mac_addr);
398 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
400 static int i40e_ethertype_filter_convert(
401 const struct rte_eth_ethertype_filter *input,
402 struct i40e_ethertype_filter *filter);
403 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
404 struct i40e_ethertype_filter *filter);
406 static int i40e_tunnel_filter_convert(
407 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
408 struct i40e_tunnel_filter *tunnel_filter);
409 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
413 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
414 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
415 static void i40e_filter_restore(struct i40e_pf *pf);
416 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
418 static const char *const valid_keys[] = {
419 ETH_I40E_FLOATING_VEB_ARG,
420 ETH_I40E_FLOATING_VEB_LIST_ARG,
421 ETH_I40E_SUPPORT_MULTI_DRIVER,
422 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
426 static const struct rte_pci_id pci_id_i40e_map[] = {
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
452 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
453 { .vendor_id = 0, /* sentinel */ },
456 static const struct eth_dev_ops i40e_eth_dev_ops = {
457 .dev_configure = i40e_dev_configure,
458 .dev_start = i40e_dev_start,
459 .dev_stop = i40e_dev_stop,
460 .dev_close = i40e_dev_close,
461 .dev_reset = i40e_dev_reset,
462 .promiscuous_enable = i40e_dev_promiscuous_enable,
463 .promiscuous_disable = i40e_dev_promiscuous_disable,
464 .allmulticast_enable = i40e_dev_allmulticast_enable,
465 .allmulticast_disable = i40e_dev_allmulticast_disable,
466 .dev_set_link_up = i40e_dev_set_link_up,
467 .dev_set_link_down = i40e_dev_set_link_down,
468 .link_update = i40e_dev_link_update,
469 .stats_get = i40e_dev_stats_get,
470 .xstats_get = i40e_dev_xstats_get,
471 .xstats_get_names = i40e_dev_xstats_get_names,
472 .stats_reset = i40e_dev_stats_reset,
473 .xstats_reset = i40e_dev_stats_reset,
474 .fw_version_get = i40e_fw_version_get,
475 .dev_infos_get = i40e_dev_info_get,
476 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
477 .vlan_filter_set = i40e_vlan_filter_set,
478 .vlan_tpid_set = i40e_vlan_tpid_set,
479 .vlan_offload_set = i40e_vlan_offload_set,
480 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
481 .vlan_pvid_set = i40e_vlan_pvid_set,
482 .rx_queue_start = i40e_dev_rx_queue_start,
483 .rx_queue_stop = i40e_dev_rx_queue_stop,
484 .tx_queue_start = i40e_dev_tx_queue_start,
485 .tx_queue_stop = i40e_dev_tx_queue_stop,
486 .rx_queue_setup = i40e_dev_rx_queue_setup,
487 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
488 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
489 .rx_queue_release = i40e_dev_rx_queue_release,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .flow_ops_get = i40e_dev_flow_ops_get,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .rx_burst_mode_get = i40e_rx_burst_mode_get,
509 .tx_burst_mode_get = i40e_tx_burst_mode_get,
510 .mirror_rule_set = i40e_mirror_rule_set,
511 .mirror_rule_reset = i40e_mirror_rule_reset,
512 .timesync_enable = i40e_timesync_enable,
513 .timesync_disable = i40e_timesync_disable,
514 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
515 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
516 .get_dcb_info = i40e_dev_get_dcb_info,
517 .timesync_adjust_time = i40e_timesync_adjust_time,
518 .timesync_read_time = i40e_timesync_read_time,
519 .timesync_write_time = i40e_timesync_write_time,
520 .get_reg = i40e_get_regs,
521 .get_eeprom_length = i40e_get_eeprom_length,
522 .get_eeprom = i40e_get_eeprom,
523 .get_module_info = i40e_get_module_info,
524 .get_module_eeprom = i40e_get_module_eeprom,
525 .mac_addr_set = i40e_set_default_mac_addr,
526 .mtu_set = i40e_dev_mtu_set,
527 .tm_ops_get = i40e_tm_ops_get,
528 .tx_done_cleanup = i40e_tx_done_cleanup,
529 .get_monitor_addr = i40e_get_monitor_addr,
532 /* store statistics names and its offset in stats structure */
533 struct rte_i40e_xstats_name_off {
534 char name[RTE_ETH_XSTATS_NAME_SIZE];
538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
539 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
540 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
541 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
542 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
543 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
544 rx_unknown_protocol)},
545 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
546 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
547 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
548 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
552 sizeof(rte_i40e_stats_strings[0]))
554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
555 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
556 tx_dropped_link_down)},
557 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
558 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
560 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
561 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
563 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
567 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
568 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
569 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
570 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
571 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
572 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
584 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
589 mac_short_packet_dropped)},
590 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
593 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
594 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
604 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
606 {"rx_flow_director_atr_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
608 {"rx_flow_director_sb_match_packets",
609 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
610 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
614 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
621 sizeof(rte_i40e_hw_port_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
631 sizeof(rte_i40e_rxq_prio_strings[0]))
633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
634 {"xon_packets", offsetof(struct i40e_hw_port_stats,
636 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
638 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
639 priority_xon_2_xoff)},
642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
643 sizeof(rte_i40e_txq_prio_strings[0]))
646 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
647 struct rte_pci_device *pci_dev)
649 char name[RTE_ETH_NAME_MAX_LEN];
650 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
653 if (pci_dev->device.devargs) {
654 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
660 if (eth_da.nb_representor_ports > 0 &&
661 eth_da.type != RTE_ETH_REPRESENTOR_VF) {
662 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
663 pci_dev->device.devargs->args);
667 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
668 sizeof(struct i40e_adapter),
669 eth_dev_pci_specific_init, pci_dev,
670 eth_i40e_dev_init, NULL);
672 if (retval || eth_da.nb_representor_ports < 1)
675 /* probe VF representor ports */
676 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
677 pci_dev->device.name);
679 if (pf_ethdev == NULL)
682 for (i = 0; i < eth_da.nb_representor_ports; i++) {
683 struct i40e_vf_representor representor = {
684 .vf_id = eth_da.representor_ports[i],
685 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
686 pf_ethdev->data->dev_private)->switch_domain_id,
687 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
688 pf_ethdev->data->dev_private)
691 /* representor port net_bdf_port */
692 snprintf(name, sizeof(name), "net_%s_representor_%d",
693 pci_dev->device.name, eth_da.representor_ports[i]);
695 retval = rte_eth_dev_create(&pci_dev->device, name,
696 sizeof(struct i40e_vf_representor), NULL, NULL,
697 i40e_vf_representor_init, &representor);
700 PMD_DRV_LOG(ERR, "failed to create i40e vf "
701 "representor %s.", name);
707 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
709 struct rte_eth_dev *ethdev;
711 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
715 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
716 return rte_eth_dev_pci_generic_remove(pci_dev,
717 i40e_vf_representor_uninit);
719 return rte_eth_dev_pci_generic_remove(pci_dev,
720 eth_i40e_dev_uninit);
723 static struct rte_pci_driver rte_i40e_pmd = {
724 .id_table = pci_id_i40e_map,
725 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
726 .probe = eth_i40e_pci_probe,
727 .remove = eth_i40e_pci_remove,
731 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
734 uint32_t ori_reg_val;
735 struct rte_eth_dev_data *dev_data =
736 ((struct i40e_adapter *)hw->back)->pf.dev_data;
737 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
739 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
740 i40e_write_rx_ctl(hw, reg_addr, reg_val);
741 if (ori_reg_val != reg_val)
743 "i40e device %s changed global register [0x%08x]."
744 " original: 0x%08x, new: 0x%08x",
745 dev->device->name, reg_addr, ori_reg_val, reg_val);
748 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
749 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
750 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
752 #ifndef I40E_GLQF_ORT
753 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
755 #ifndef I40E_GLQF_PIT
756 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
758 #ifndef I40E_GLQF_L3_MAP
759 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
762 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
765 * Initialize registers for parsing packet type of QinQ
766 * This should be removed from code once proper
767 * configuration API is added to avoid configuration conflicts
768 * between ports of the same device.
770 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
771 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
774 static inline void i40e_config_automask(struct i40e_pf *pf)
776 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
779 /* INTENA flag is not auto-cleared for interrupt */
780 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
781 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
782 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
784 /* If support multi-driver, PF will use INT0. */
785 if (!pf->support_multi_driver)
786 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
788 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
791 static inline void i40e_clear_automask(struct i40e_pf *pf)
793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
796 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
797 val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
798 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
800 if (!pf->support_multi_driver)
801 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
803 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
806 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
809 * Add a ethertype filter to drop all flow control frames transmitted
813 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
815 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
816 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
817 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
818 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
821 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
822 I40E_FLOW_CONTROL_ETHERTYPE, flags,
823 pf->main_vsi_seid, 0,
827 "Failed to add filter to drop flow control frames from VSIs.");
831 floating_veb_list_handler(__rte_unused const char *key,
832 const char *floating_veb_value,
836 unsigned int count = 0;
839 bool *vf_floating_veb = opaque;
841 while (isblank(*floating_veb_value))
842 floating_veb_value++;
844 /* Reset floating VEB configuration for VFs */
845 for (idx = 0; idx < I40E_MAX_VF; idx++)
846 vf_floating_veb[idx] = false;
850 while (isblank(*floating_veb_value))
851 floating_veb_value++;
852 if (*floating_veb_value == '\0')
855 idx = strtoul(floating_veb_value, &end, 10);
856 if (errno || end == NULL)
860 while (isblank(*end))
864 } else if ((*end == ';') || (*end == '\0')) {
866 if (min == I40E_MAX_VF)
868 if (max >= I40E_MAX_VF)
869 max = I40E_MAX_VF - 1;
870 for (idx = min; idx <= max; idx++) {
871 vf_floating_veb[idx] = true;
878 floating_veb_value = end + 1;
879 } while (*end != '\0');
888 config_vf_floating_veb(struct rte_devargs *devargs,
889 uint16_t floating_veb,
890 bool *vf_floating_veb)
892 struct rte_kvargs *kvlist;
894 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
898 /* All the VFs attach to the floating VEB by default
899 * when the floating VEB is enabled.
901 for (i = 0; i < I40E_MAX_VF; i++)
902 vf_floating_veb[i] = true;
907 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
911 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
912 rte_kvargs_free(kvlist);
915 /* When the floating_veb_list parameter exists, all the VFs
916 * will attach to the legacy VEB firstly, then configure VFs
917 * to the floating VEB according to the floating_veb_list.
919 if (rte_kvargs_process(kvlist, floating_veb_list,
920 floating_veb_list_handler,
921 vf_floating_veb) < 0) {
922 rte_kvargs_free(kvlist);
925 rte_kvargs_free(kvlist);
929 i40e_check_floating_handler(__rte_unused const char *key,
931 __rte_unused void *opaque)
933 if (strcmp(value, "1"))
940 is_floating_veb_supported(struct rte_devargs *devargs)
942 struct rte_kvargs *kvlist;
943 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
948 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
952 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
953 rte_kvargs_free(kvlist);
956 /* Floating VEB is enabled when there's key-value:
957 * enable_floating_veb=1
959 if (rte_kvargs_process(kvlist, floating_veb_key,
960 i40e_check_floating_handler, NULL) < 0) {
961 rte_kvargs_free(kvlist);
964 rte_kvargs_free(kvlist);
970 config_floating_veb(struct rte_eth_dev *dev)
972 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
973 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
976 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
978 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
980 is_floating_veb_supported(pci_dev->device.devargs);
981 config_vf_floating_veb(pci_dev->device.devargs,
983 pf->floating_veb_list);
985 pf->floating_veb = false;
989 #define I40E_L2_TAGS_S_TAG_SHIFT 1
990 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
993 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
996 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
997 char ethertype_hash_name[RTE_HASH_NAMESIZE];
1000 struct rte_hash_parameters ethertype_hash_params = {
1001 .name = ethertype_hash_name,
1002 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
1003 .key_len = sizeof(struct i40e_ethertype_filter_input),
1004 .hash_func = rte_hash_crc,
1005 .hash_func_init_val = 0,
1006 .socket_id = rte_socket_id(),
1009 /* Initialize ethertype filter rule list and hash */
1010 TAILQ_INIT(ðertype_rule->ethertype_list);
1011 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1012 "ethertype_%s", dev->device->name);
1013 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
1014 if (!ethertype_rule->hash_table) {
1015 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1018 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1019 sizeof(struct i40e_ethertype_filter *) *
1020 I40E_MAX_ETHERTYPE_FILTER_NUM,
1022 if (!ethertype_rule->hash_map) {
1024 "Failed to allocate memory for ethertype hash map!");
1026 goto err_ethertype_hash_map_alloc;
1031 err_ethertype_hash_map_alloc:
1032 rte_hash_free(ethertype_rule->hash_table);
1038 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1041 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1042 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1045 struct rte_hash_parameters tunnel_hash_params = {
1046 .name = tunnel_hash_name,
1047 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1048 .key_len = sizeof(struct i40e_tunnel_filter_input),
1049 .hash_func = rte_hash_crc,
1050 .hash_func_init_val = 0,
1051 .socket_id = rte_socket_id(),
1054 /* Initialize tunnel filter rule list and hash */
1055 TAILQ_INIT(&tunnel_rule->tunnel_list);
1056 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1057 "tunnel_%s", dev->device->name);
1058 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1059 if (!tunnel_rule->hash_table) {
1060 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1063 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1064 sizeof(struct i40e_tunnel_filter *) *
1065 I40E_MAX_TUNNEL_FILTER_NUM,
1067 if (!tunnel_rule->hash_map) {
1069 "Failed to allocate memory for tunnel hash map!");
1071 goto err_tunnel_hash_map_alloc;
1076 err_tunnel_hash_map_alloc:
1077 rte_hash_free(tunnel_rule->hash_table);
1083 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1085 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1086 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1087 struct i40e_fdir_info *fdir_info = &pf->fdir;
1088 char fdir_hash_name[RTE_HASH_NAMESIZE];
1089 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1090 uint32_t best = hw->func_caps.fd_filters_best_effort;
1091 enum i40e_filter_pctype pctype;
1092 struct rte_bitmap *bmp = NULL;
1098 struct rte_hash_parameters fdir_hash_params = {
1099 .name = fdir_hash_name,
1100 .entries = I40E_MAX_FDIR_FILTER_NUM,
1101 .key_len = sizeof(struct i40e_fdir_input),
1102 .hash_func = rte_hash_crc,
1103 .hash_func_init_val = 0,
1104 .socket_id = rte_socket_id(),
1107 /* Initialize flow director filter rule list and hash */
1108 TAILQ_INIT(&fdir_info->fdir_list);
1109 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1110 "fdir_%s", dev->device->name);
1111 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1112 if (!fdir_info->hash_table) {
1113 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1117 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1118 sizeof(struct i40e_fdir_filter *) *
1119 I40E_MAX_FDIR_FILTER_NUM,
1121 if (!fdir_info->hash_map) {
1123 "Failed to allocate memory for fdir hash map!");
1125 goto err_fdir_hash_map_alloc;
1128 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1129 sizeof(struct i40e_fdir_filter) *
1130 I40E_MAX_FDIR_FILTER_NUM,
1133 if (!fdir_info->fdir_filter_array) {
1135 "Failed to allocate memory for fdir filter array!");
1137 goto err_fdir_filter_array_alloc;
1140 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1141 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
1142 pf->fdir.flow_count[pctype] = 0;
1144 fdir_info->fdir_space_size = alloc + best;
1145 fdir_info->fdir_actual_cnt = 0;
1146 fdir_info->fdir_guarantee_total_space = alloc;
1147 fdir_info->fdir_guarantee_free_space =
1148 fdir_info->fdir_guarantee_total_space;
1150 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1152 fdir_info->fdir_flow_pool.pool =
1153 rte_zmalloc("i40e_fdir_entry",
1154 sizeof(struct i40e_fdir_entry) *
1155 fdir_info->fdir_space_size,
1158 if (!fdir_info->fdir_flow_pool.pool) {
1160 "Failed to allocate memory for bitmap flow!");
1162 goto err_fdir_bitmap_flow_alloc;
1165 for (i = 0; i < fdir_info->fdir_space_size; i++)
1166 fdir_info->fdir_flow_pool.pool[i].idx = i;
1169 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1170 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1173 "Failed to allocate memory for fdir bitmap!");
1175 goto err_fdir_mem_alloc;
1177 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1180 "Failed to initialization fdir bitmap!");
1182 goto err_fdir_bmp_alloc;
1184 for (i = 0; i < fdir_info->fdir_space_size; i++)
1185 rte_bitmap_set(bmp, i);
1187 fdir_info->fdir_flow_pool.bitmap = bmp;
1194 rte_free(fdir_info->fdir_flow_pool.pool);
1195 err_fdir_bitmap_flow_alloc:
1196 rte_free(fdir_info->fdir_filter_array);
1197 err_fdir_filter_array_alloc:
1198 rte_free(fdir_info->hash_map);
1199 err_fdir_hash_map_alloc:
1200 rte_hash_free(fdir_info->hash_table);
1206 i40e_init_customized_info(struct i40e_pf *pf)
1210 /* Initialize customized pctype */
1211 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1212 pf->customized_pctype[i].index = i;
1213 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1214 pf->customized_pctype[i].valid = false;
1217 pf->gtp_support = false;
1218 pf->esp_support = false;
1222 i40e_init_filter_invalidation(struct i40e_pf *pf)
1224 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1225 struct i40e_fdir_info *fdir_info = &pf->fdir;
1226 uint32_t glqf_ctl_reg = 0;
1228 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1229 if (!pf->support_multi_driver) {
1230 fdir_info->fdir_invalprio = 1;
1231 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1232 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1233 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1235 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1236 fdir_info->fdir_invalprio = 1;
1237 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1239 fdir_info->fdir_invalprio = 0;
1240 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1246 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1248 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1250 struct i40e_queue_regions *info = &pf->queue_region;
1253 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1254 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1256 memset(info, 0, sizeof(struct i40e_queue_regions));
1260 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1265 unsigned long support_multi_driver;
1268 pf = (struct i40e_pf *)opaque;
1271 support_multi_driver = strtoul(value, &end, 10);
1272 if (errno != 0 || end == value || *end != 0) {
1273 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1277 if (support_multi_driver == 1 || support_multi_driver == 0)
1278 pf->support_multi_driver = (bool)support_multi_driver;
1280 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1281 "enable global configuration by default."
1282 ETH_I40E_SUPPORT_MULTI_DRIVER);
1287 i40e_support_multi_driver(struct rte_eth_dev *dev)
1289 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1290 struct rte_kvargs *kvlist;
1293 /* Enable global configuration by default */
1294 pf->support_multi_driver = false;
1296 if (!dev->device->devargs)
1299 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1303 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1304 if (!kvargs_count) {
1305 rte_kvargs_free(kvlist);
1309 if (kvargs_count > 1)
1310 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1311 "the first invalid or last valid one is used !",
1312 ETH_I40E_SUPPORT_MULTI_DRIVER);
1314 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1315 i40e_parse_multi_drv_handler, pf) < 0) {
1316 rte_kvargs_free(kvlist);
1320 rte_kvargs_free(kvlist);
1325 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1326 uint32_t reg_addr, uint64_t reg_val,
1327 struct i40e_asq_cmd_details *cmd_details)
1329 uint64_t ori_reg_val;
1330 struct rte_eth_dev_data *dev_data =
1331 ((struct i40e_adapter *)hw->back)->pf.dev_data;
1332 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
1335 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1336 if (ret != I40E_SUCCESS) {
1338 "Fail to debug read from 0x%08x",
1343 if (ori_reg_val != reg_val)
1344 PMD_DRV_LOG(WARNING,
1345 "i40e device %s changed global register [0x%08x]."
1346 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1347 dev->device->name, reg_addr, ori_reg_val, reg_val);
1349 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1353 read_vf_msg_config(__rte_unused const char *key,
1357 struct i40e_vf_msg_cfg *cfg = opaque;
1359 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1360 &cfg->ignore_second) != 3) {
1361 memset(cfg, 0, sizeof(*cfg));
1362 PMD_DRV_LOG(ERR, "format error! example: "
1363 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1368 * If the message validation function been enabled, the 'period'
1369 * and 'ignore_second' must greater than 0.
1371 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1372 memset(cfg, 0, sizeof(*cfg));
1373 PMD_DRV_LOG(ERR, "%s error! the second and third"
1374 " number must be greater than 0!",
1375 ETH_I40E_VF_MSG_CFG);
1383 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1384 struct i40e_vf_msg_cfg *msg_cfg)
1386 struct rte_kvargs *kvlist;
1390 memset(msg_cfg, 0, sizeof(*msg_cfg));
1392 if (!dev->device->devargs)
1395 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1399 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1403 if (kvargs_count > 1) {
1404 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1405 ETH_I40E_VF_MSG_CFG);
1410 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1411 read_vf_msg_config, msg_cfg) < 0)
1415 rte_kvargs_free(kvlist);
1419 #define I40E_ALARM_INTERVAL 50000 /* us */
1422 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1424 struct rte_pci_device *pci_dev;
1425 struct rte_intr_handle *intr_handle;
1426 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct i40e_vsi *vsi;
1431 uint8_t aq_fail = 0;
1433 PMD_INIT_FUNC_TRACE();
1435 dev->dev_ops = &i40e_eth_dev_ops;
1436 dev->rx_queue_count = i40e_dev_rx_queue_count;
1437 dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1438 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1439 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1440 dev->rx_pkt_burst = i40e_recv_pkts;
1441 dev->tx_pkt_burst = i40e_xmit_pkts;
1442 dev->tx_pkt_prepare = i40e_prep_pkts;
1444 /* for secondary processes, we don't initialise any further as primary
1445 * has already done this work. Only check we don't need a different
1447 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1448 i40e_set_rx_function(dev);
1449 i40e_set_tx_function(dev);
1452 i40e_set_default_ptype_table(dev);
1453 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1454 intr_handle = &pci_dev->intr_handle;
1456 rte_eth_copy_pci_info(dev, pci_dev);
1457 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1459 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1460 pf->dev_data = dev->data;
1462 hw->back = I40E_PF_TO_ADAPTER(pf);
1463 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1466 "Hardware is not available, as address is NULL");
1470 hw->vendor_id = pci_dev->id.vendor_id;
1471 hw->device_id = pci_dev->id.device_id;
1472 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1473 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1474 hw->bus.device = pci_dev->addr.devid;
1475 hw->bus.func = pci_dev->addr.function;
1476 hw->adapter_stopped = 0;
1477 hw->adapter_closed = 0;
1479 /* Init switch device pointer */
1480 hw->switch_dev = NULL;
1483 * Switch Tag value should not be identical to either the First Tag
1484 * or Second Tag values. So set something other than common Ethertype
1485 * for internal switching.
1487 hw->switch_tag = 0xffff;
1489 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1490 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1491 PMD_INIT_LOG(ERR, "\nERROR: "
1492 "Firmware recovery mode detected. Limiting functionality.\n"
1493 "Refer to the Intel(R) Ethernet Adapters and Devices "
1494 "User Guide for details on firmware recovery mode.");
1498 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1499 /* Check if need to support multi-driver */
1500 i40e_support_multi_driver(dev);
1502 /* Make sure all is clean before doing PF reset */
1505 /* Reset here to make sure all is clean for each PF */
1506 ret = i40e_pf_reset(hw);
1508 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1512 /* Initialize the shared code (base driver) */
1513 ret = i40e_init_shared_code(hw);
1515 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1519 /* Initialize the parameters for adminq */
1520 i40e_init_adminq_parameter(hw);
1521 ret = i40e_init_adminq(hw);
1522 if (ret != I40E_SUCCESS) {
1523 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1526 /* Firmware of SFP x722 does not support 802.1ad frames ability */
1527 if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1528 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1529 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1531 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1532 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1533 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1534 ((hw->nvm.version >> 12) & 0xf),
1535 ((hw->nvm.version >> 4) & 0xff),
1536 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1538 /* Initialize the hardware */
1541 i40e_config_automask(pf);
1543 i40e_set_default_pctype_table(dev);
1546 * To work around the NVM issue, initialize registers
1547 * for packet type of QinQ by software.
1548 * It should be removed once issues are fixed in NVM.
1550 if (!pf->support_multi_driver)
1551 i40e_GLQF_reg_init(hw);
1553 /* Initialize the input set for filters (hash and fd) to default value */
1554 i40e_filter_input_set_init(pf);
1556 /* initialise the L3_MAP register */
1557 if (!pf->support_multi_driver) {
1558 ret = i40e_aq_debug_write_global_register(hw,
1559 I40E_GLQF_L3_MAP(40),
1562 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1565 "Global register 0x%08x is changed with 0x28",
1566 I40E_GLQF_L3_MAP(40));
1569 /* Need the special FW version to support floating VEB */
1570 config_floating_veb(dev);
1571 /* Clear PXE mode */
1572 i40e_clear_pxe_mode(hw);
1573 i40e_dev_sync_phy_type(hw);
1576 * On X710, performance number is far from the expectation on recent
1577 * firmware versions. The fix for this issue may not be integrated in
1578 * the following firmware version. So the workaround in software driver
1579 * is needed. It needs to modify the initial values of 3 internal only
1580 * registers. Note that the workaround can be removed when it is fixed
1581 * in firmware in the future.
1583 i40e_configure_registers(hw);
1585 /* Get hw capabilities */
1586 ret = i40e_get_cap(hw);
1587 if (ret != I40E_SUCCESS) {
1588 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1589 goto err_get_capabilities;
1592 /* Initialize parameters for PF */
1593 ret = i40e_pf_parameter_init(dev);
1595 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1596 goto err_parameter_init;
1599 /* Initialize the queue management */
1600 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1602 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1603 goto err_qp_pool_init;
1605 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1606 hw->func_caps.num_msix_vectors - 1);
1608 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1609 goto err_msix_pool_init;
1612 /* Initialize lan hmc */
1613 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1614 hw->func_caps.num_rx_qp, 0, 0);
1615 if (ret != I40E_SUCCESS) {
1616 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1617 goto err_init_lan_hmc;
1620 /* Configure lan hmc */
1621 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1622 if (ret != I40E_SUCCESS) {
1623 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1624 goto err_configure_lan_hmc;
1627 /* Get and check the mac address */
1628 i40e_get_mac_addr(hw, hw->mac.addr);
1629 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1630 PMD_INIT_LOG(ERR, "mac address is not valid");
1632 goto err_get_mac_addr;
1634 /* Copy the permanent MAC address */
1635 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1636 (struct rte_ether_addr *)hw->mac.perm_addr);
1638 /* Disable flow control */
1639 hw->fc.requested_mode = I40E_FC_NONE;
1640 i40e_set_fc(hw, &aq_fail, TRUE);
1642 /* Set the global registers with default ether type value */
1643 if (!pf->support_multi_driver) {
1644 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1645 RTE_ETHER_TYPE_VLAN);
1646 if (ret != I40E_SUCCESS) {
1648 "Failed to set the default outer "
1650 goto err_setup_pf_switch;
1654 /* PF setup, which includes VSI setup */
1655 ret = i40e_pf_setup(pf);
1657 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1658 goto err_setup_pf_switch;
1663 /* Disable double vlan by default */
1664 i40e_vsi_config_double_vlan(vsi, FALSE);
1666 /* Disable S-TAG identification when floating_veb is disabled */
1667 if (!pf->floating_veb) {
1668 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1669 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1670 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1671 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1675 if (!vsi->max_macaddrs)
1676 len = RTE_ETHER_ADDR_LEN;
1678 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1680 /* Should be after VSI initialized */
1681 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1682 if (!dev->data->mac_addrs) {
1684 "Failed to allocated memory for storing mac address");
1687 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1688 &dev->data->mac_addrs[0]);
1690 /* Init dcb to sw mode by default */
1691 ret = i40e_dcb_init_configure(dev, TRUE);
1692 if (ret != I40E_SUCCESS) {
1693 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1694 pf->flags &= ~I40E_FLAG_DCB;
1696 /* Update HW struct after DCB configuration */
1699 /* initialize pf host driver to setup SRIOV resource if applicable */
1700 i40e_pf_host_init(dev);
1702 /* register callback func to eal lib */
1703 rte_intr_callback_register(intr_handle,
1704 i40e_dev_interrupt_handler, dev);
1706 /* configure and enable device interrupt */
1707 i40e_pf_config_irq0(hw, TRUE);
1708 i40e_pf_enable_irq0(hw);
1710 /* enable uio intr after callback register */
1711 rte_intr_enable(intr_handle);
1713 /* By default disable flexible payload in global configuration */
1714 if (!pf->support_multi_driver)
1715 i40e_flex_payload_reg_set_default(hw);
1718 * Add an ethertype filter to drop all flow control frames transmitted
1719 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1722 i40e_add_tx_flow_control_drop_filter(pf);
1724 /* Set the max frame size to 0x2600 by default,
1725 * in case other drivers changed the default value.
1727 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1729 /* initialize mirror rule list */
1730 TAILQ_INIT(&pf->mirror_list);
1732 /* initialize RSS rule list */
1733 TAILQ_INIT(&pf->rss_config_list);
1735 /* initialize Traffic Manager configuration */
1736 i40e_tm_conf_init(dev);
1738 /* Initialize customized information */
1739 i40e_init_customized_info(pf);
1741 /* Initialize the filter invalidation configuration */
1742 i40e_init_filter_invalidation(pf);
1744 ret = i40e_init_ethtype_filter_list(dev);
1746 goto err_init_ethtype_filter_list;
1747 ret = i40e_init_tunnel_filter_list(dev);
1749 goto err_init_tunnel_filter_list;
1750 ret = i40e_init_fdir_filter_list(dev);
1752 goto err_init_fdir_filter_list;
1754 /* initialize queue region configuration */
1755 i40e_init_queue_region_conf(dev);
1757 /* reset all stats of the device, including pf and main vsi */
1758 i40e_dev_stats_reset(dev);
1762 err_init_fdir_filter_list:
1763 rte_free(pf->tunnel.hash_table);
1764 rte_free(pf->tunnel.hash_map);
1765 err_init_tunnel_filter_list:
1766 rte_free(pf->ethertype.hash_table);
1767 rte_free(pf->ethertype.hash_map);
1768 err_init_ethtype_filter_list:
1769 rte_free(dev->data->mac_addrs);
1770 dev->data->mac_addrs = NULL;
1772 i40e_vsi_release(pf->main_vsi);
1773 err_setup_pf_switch:
1775 err_configure_lan_hmc:
1776 (void)i40e_shutdown_lan_hmc(hw);
1778 i40e_res_pool_destroy(&pf->msix_pool);
1780 i40e_res_pool_destroy(&pf->qp_pool);
1783 err_get_capabilities:
1784 (void)i40e_shutdown_adminq(hw);
1790 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1792 struct i40e_ethertype_filter *p_ethertype;
1793 struct i40e_ethertype_rule *ethertype_rule;
1795 ethertype_rule = &pf->ethertype;
1796 /* Remove all ethertype filter rules and hash */
1797 if (ethertype_rule->hash_map)
1798 rte_free(ethertype_rule->hash_map);
1799 if (ethertype_rule->hash_table)
1800 rte_hash_free(ethertype_rule->hash_table);
1802 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1803 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1804 p_ethertype, rules);
1805 rte_free(p_ethertype);
1810 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1812 struct i40e_tunnel_filter *p_tunnel;
1813 struct i40e_tunnel_rule *tunnel_rule;
1815 tunnel_rule = &pf->tunnel;
1816 /* Remove all tunnel director rules and hash */
1817 if (tunnel_rule->hash_map)
1818 rte_free(tunnel_rule->hash_map);
1819 if (tunnel_rule->hash_table)
1820 rte_hash_free(tunnel_rule->hash_table);
1822 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1823 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1829 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1831 struct i40e_fdir_filter *p_fdir;
1832 struct i40e_fdir_info *fdir_info;
1834 fdir_info = &pf->fdir;
1836 /* Remove all flow director rules */
1837 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1838 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1842 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1844 struct i40e_fdir_info *fdir_info;
1846 fdir_info = &pf->fdir;
1848 /* flow director memory cleanup */
1849 if (fdir_info->hash_map)
1850 rte_free(fdir_info->hash_map);
1851 if (fdir_info->hash_table)
1852 rte_hash_free(fdir_info->hash_table);
1853 if (fdir_info->fdir_flow_pool.bitmap)
1854 rte_free(fdir_info->fdir_flow_pool.bitmap);
1855 if (fdir_info->fdir_flow_pool.pool)
1856 rte_free(fdir_info->fdir_flow_pool.pool);
1857 if (fdir_info->fdir_filter_array)
1858 rte_free(fdir_info->fdir_filter_array);
1861 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1864 * Disable by default flexible payload
1865 * for corresponding L2/L3/L4 layers.
1867 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1868 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1869 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1873 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1877 PMD_INIT_FUNC_TRACE();
1879 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1882 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884 if (hw->adapter_closed == 0)
1885 i40e_dev_close(dev);
1891 i40e_dev_configure(struct rte_eth_dev *dev)
1893 struct i40e_adapter *ad =
1894 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1895 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1900 ret = i40e_dev_sync_phy_type(hw);
1904 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1905 * bulk allocation or vector Rx preconditions we will reset it.
1907 ad->rx_bulk_alloc_allowed = true;
1908 ad->rx_vec_allowed = true;
1909 ad->tx_simple_allowed = true;
1910 ad->tx_vec_allowed = true;
1912 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1913 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1915 /* Only legacy filter API needs the following fdir config. So when the
1916 * legacy filter API is deprecated, the following codes should also be
1919 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1920 ret = i40e_fdir_setup(pf);
1921 if (ret != I40E_SUCCESS) {
1922 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1925 ret = i40e_fdir_configure(dev);
1927 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1931 i40e_fdir_teardown(pf);
1933 ret = i40e_dev_init_vlan(dev);
1938 * General PMD driver call sequence are NIC init, configure,
1939 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1940 * will try to lookup the VSI that specific queue belongs to if VMDQ
1941 * applicable. So, VMDQ setting has to be done before
1942 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1943 * For RSS setting, it will try to calculate actual configured RX queue
1944 * number, which will be available after rx_queue_setup(). dev_start()
1945 * function is good to place RSS setup.
1947 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1948 ret = i40e_vmdq_setup(dev);
1953 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1954 ret = i40e_dcb_setup(dev);
1956 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1961 TAILQ_INIT(&pf->flow_list);
1966 /* need to release vmdq resource if exists */
1967 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1968 i40e_vsi_release(pf->vmdq[i].vsi);
1969 pf->vmdq[i].vsi = NULL;
1974 /* Need to release fdir resource if exists.
1975 * Only legacy filter API needs the following fdir config. So when the
1976 * legacy filter API is deprecated, the following code should also be
1979 i40e_fdir_teardown(pf);
1984 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1986 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
1987 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1990 uint16_t msix_vect = vsi->msix_intr;
1993 for (i = 0; i < vsi->nb_qps; i++) {
1994 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1995 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1999 if (vsi->type != I40E_VSI_SRIOV) {
2000 if (!rte_intr_allow_others(intr_handle)) {
2001 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2002 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2004 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2007 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2008 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2010 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2015 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2016 vsi->user_param + (msix_vect - 1);
2018 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2019 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2021 I40E_WRITE_FLUSH(hw);
2025 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2026 int base_queue, int nb_queue,
2031 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2032 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2034 /* Bind all RX queues to allocated MSIX interrupt */
2035 for (i = 0; i < nb_queue; i++) {
2036 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2037 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2038 ((base_queue + i + 1) <<
2039 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2040 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2041 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2043 if (i == nb_queue - 1)
2044 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2045 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2048 /* Write first RX queue to Link list register as the head element */
2049 if (vsi->type != I40E_VSI_SRIOV) {
2051 i40e_calc_itr_interval(1, pf->support_multi_driver);
2053 if (msix_vect == I40E_MISC_VEC_ID) {
2054 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2056 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2058 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2060 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2063 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2065 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2067 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2069 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2076 if (msix_vect == I40E_MISC_VEC_ID) {
2078 I40E_VPINT_LNKLST0(vsi->user_param),
2080 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2082 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2084 /* num_msix_vectors_vf needs to minus irq0 */
2085 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2086 vsi->user_param + (msix_vect - 1);
2088 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2090 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2092 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2096 I40E_WRITE_FLUSH(hw);
2100 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2102 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2103 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2104 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2105 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2106 uint16_t msix_vect = vsi->msix_intr;
2107 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2108 uint16_t queue_idx = 0;
2112 for (i = 0; i < vsi->nb_qps; i++) {
2113 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2114 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2117 /* VF bind interrupt */
2118 if (vsi->type == I40E_VSI_SRIOV) {
2119 if (vsi->nb_msix == 0) {
2120 PMD_DRV_LOG(ERR, "No msix resource");
2123 __vsi_queues_bind_intr(vsi, msix_vect,
2124 vsi->base_queue, vsi->nb_qps,
2129 /* PF & VMDq bind interrupt */
2130 if (rte_intr_dp_is_en(intr_handle)) {
2131 if (vsi->type == I40E_VSI_MAIN) {
2134 } else if (vsi->type == I40E_VSI_VMDQ2) {
2135 struct i40e_vsi *main_vsi =
2136 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2137 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2142 for (i = 0; i < vsi->nb_used_qps; i++) {
2143 if (vsi->nb_msix == 0) {
2144 PMD_DRV_LOG(ERR, "No msix resource");
2146 } else if (nb_msix <= 1) {
2147 if (!rte_intr_allow_others(intr_handle))
2148 /* allow to share MISC_VEC_ID */
2149 msix_vect = I40E_MISC_VEC_ID;
2151 /* no enough msix_vect, map all to one */
2152 __vsi_queues_bind_intr(vsi, msix_vect,
2153 vsi->base_queue + i,
2154 vsi->nb_used_qps - i,
2156 for (; !!record && i < vsi->nb_used_qps; i++)
2157 intr_handle->intr_vec[queue_idx + i] =
2161 /* 1:1 queue/msix_vect mapping */
2162 __vsi_queues_bind_intr(vsi, msix_vect,
2163 vsi->base_queue + i, 1,
2166 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2176 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2178 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2179 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2180 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2181 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2182 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2183 uint16_t msix_intr, i;
2185 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2186 for (i = 0; i < vsi->nb_msix; i++) {
2187 msix_intr = vsi->msix_intr + i;
2188 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2189 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2190 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2191 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2194 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2195 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2196 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2197 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2199 I40E_WRITE_FLUSH(hw);
2203 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2205 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2206 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2207 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2208 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2209 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2210 uint16_t msix_intr, i;
2212 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2213 for (i = 0; i < vsi->nb_msix; i++) {
2214 msix_intr = vsi->msix_intr + i;
2215 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2216 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2219 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2220 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2222 I40E_WRITE_FLUSH(hw);
2225 static inline uint8_t
2226 i40e_parse_link_speeds(uint16_t link_speeds)
2228 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2230 if (link_speeds & ETH_LINK_SPEED_40G)
2231 link_speed |= I40E_LINK_SPEED_40GB;
2232 if (link_speeds & ETH_LINK_SPEED_25G)
2233 link_speed |= I40E_LINK_SPEED_25GB;
2234 if (link_speeds & ETH_LINK_SPEED_20G)
2235 link_speed |= I40E_LINK_SPEED_20GB;
2236 if (link_speeds & ETH_LINK_SPEED_10G)
2237 link_speed |= I40E_LINK_SPEED_10GB;
2238 if (link_speeds & ETH_LINK_SPEED_1G)
2239 link_speed |= I40E_LINK_SPEED_1GB;
2240 if (link_speeds & ETH_LINK_SPEED_100M)
2241 link_speed |= I40E_LINK_SPEED_100MB;
2247 i40e_phy_conf_link(struct i40e_hw *hw,
2249 uint8_t force_speed,
2252 enum i40e_status_code status;
2253 struct i40e_aq_get_phy_abilities_resp phy_ab;
2254 struct i40e_aq_set_phy_config phy_conf;
2255 enum i40e_aq_phy_type cnt;
2256 uint8_t avail_speed;
2257 uint32_t phy_type_mask = 0;
2259 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2260 I40E_AQ_PHY_FLAG_PAUSE_RX |
2261 I40E_AQ_PHY_FLAG_PAUSE_RX |
2262 I40E_AQ_PHY_FLAG_LOW_POWER;
2265 /* To get phy capabilities of available speeds. */
2266 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2269 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2273 avail_speed = phy_ab.link_speed;
2275 /* To get the current phy config. */
2276 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2279 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2284 /* If link needs to go up and it is in autoneg mode the speed is OK,
2285 * no need to set up again.
2287 if (is_up && phy_ab.phy_type != 0 &&
2288 abilities & I40E_AQ_PHY_AN_ENABLED &&
2289 phy_ab.link_speed != 0)
2290 return I40E_SUCCESS;
2292 memset(&phy_conf, 0, sizeof(phy_conf));
2294 /* bits 0-2 use the values from get_phy_abilities_resp */
2296 abilities |= phy_ab.abilities & mask;
2298 phy_conf.abilities = abilities;
2300 /* If link needs to go up, but the force speed is not supported,
2301 * Warn users and config the default available speeds.
2303 if (is_up && !(force_speed & avail_speed)) {
2304 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2305 phy_conf.link_speed = avail_speed;
2307 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2310 /* PHY type mask needs to include each type except PHY type extension */
2311 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2312 phy_type_mask |= 1 << cnt;
2314 /* use get_phy_abilities_resp value for the rest */
2315 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2316 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2317 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2318 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2319 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2320 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2321 phy_conf.eee_capability = phy_ab.eee_capability;
2322 phy_conf.eeer = phy_ab.eeer_val;
2323 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2325 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2326 phy_ab.abilities, phy_ab.link_speed);
2327 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2328 phy_conf.abilities, phy_conf.link_speed);
2330 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2334 return I40E_SUCCESS;
2338 i40e_apply_link_speed(struct rte_eth_dev *dev)
2341 uint8_t abilities = 0;
2342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343 struct rte_eth_conf *conf = &dev->data->dev_conf;
2345 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2346 I40E_AQ_PHY_LINK_ENABLED;
2348 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2349 conf->link_speeds = ETH_LINK_SPEED_40G |
2350 ETH_LINK_SPEED_25G |
2351 ETH_LINK_SPEED_20G |
2352 ETH_LINK_SPEED_10G |
2354 ETH_LINK_SPEED_100M;
2356 abilities |= I40E_AQ_PHY_AN_ENABLED;
2358 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2360 speed = i40e_parse_link_speeds(conf->link_speeds);
2362 return i40e_phy_conf_link(hw, abilities, speed, true);
2366 i40e_dev_start(struct rte_eth_dev *dev)
2368 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2369 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2370 struct i40e_vsi *main_vsi = pf->main_vsi;
2372 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2373 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2374 uint32_t intr_vector = 0;
2375 struct i40e_vsi *vsi;
2376 uint16_t nb_rxq, nb_txq;
2378 hw->adapter_stopped = 0;
2380 rte_intr_disable(intr_handle);
2382 if ((rte_intr_cap_multiple(intr_handle) ||
2383 !RTE_ETH_DEV_SRIOV(dev).active) &&
2384 dev->data->dev_conf.intr_conf.rxq != 0) {
2385 intr_vector = dev->data->nb_rx_queues;
2386 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2391 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2392 intr_handle->intr_vec =
2393 rte_zmalloc("intr_vec",
2394 dev->data->nb_rx_queues * sizeof(int),
2396 if (!intr_handle->intr_vec) {
2398 "Failed to allocate %d rx_queues intr_vec",
2399 dev->data->nb_rx_queues);
2404 /* Initialize VSI */
2405 ret = i40e_dev_rxtx_init(pf);
2406 if (ret != I40E_SUCCESS) {
2407 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2411 /* Map queues with MSIX interrupt */
2412 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2413 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2414 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2417 i40e_vsi_enable_queues_intr(main_vsi);
2419 /* Map VMDQ VSI queues with MSIX interrupt */
2420 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2421 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2422 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2423 I40E_ITR_INDEX_DEFAULT);
2426 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2429 /* Enable all queues which have been configured */
2430 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2431 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2436 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2437 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2442 /* Enable receiving broadcast packets */
2443 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2444 if (ret != I40E_SUCCESS)
2445 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2447 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2448 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2450 if (ret != I40E_SUCCESS)
2451 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2454 /* Enable the VLAN promiscuous mode. */
2456 for (i = 0; i < pf->vf_num; i++) {
2457 vsi = pf->vfs[i].vsi;
2458 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2463 /* Enable mac loopback mode */
2464 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2465 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2466 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2467 if (ret != I40E_SUCCESS) {
2468 PMD_DRV_LOG(ERR, "fail to set loopback link");
2473 /* Apply link configure */
2474 ret = i40e_apply_link_speed(dev);
2475 if (I40E_SUCCESS != ret) {
2476 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2480 if (!rte_intr_allow_others(intr_handle)) {
2481 rte_intr_callback_unregister(intr_handle,
2482 i40e_dev_interrupt_handler,
2484 /* configure and enable device interrupt */
2485 i40e_pf_config_irq0(hw, FALSE);
2486 i40e_pf_enable_irq0(hw);
2488 if (dev->data->dev_conf.intr_conf.lsc != 0)
2490 "lsc won't enable because of no intr multiplex");
2492 ret = i40e_aq_set_phy_int_mask(hw,
2493 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2494 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2495 I40E_AQ_EVENT_MEDIA_NA), NULL);
2496 if (ret != I40E_SUCCESS)
2497 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2499 /* Call get_link_info aq commond to enable/disable LSE */
2500 i40e_dev_link_update(dev, 0);
2503 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2504 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2505 i40e_dev_alarm_handler, dev);
2507 /* enable uio intr after callback register */
2508 rte_intr_enable(intr_handle);
2511 i40e_filter_restore(pf);
2513 if (pf->tm_conf.root && !pf->tm_conf.committed)
2514 PMD_DRV_LOG(WARNING,
2515 "please call hierarchy_commit() "
2516 "before starting the port");
2518 return I40E_SUCCESS;
2521 for (i = 0; i < nb_txq; i++)
2522 i40e_dev_tx_queue_stop(dev, i);
2524 for (i = 0; i < nb_rxq; i++)
2525 i40e_dev_rx_queue_stop(dev, i);
2531 i40e_dev_stop(struct rte_eth_dev *dev)
2533 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2534 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535 struct i40e_vsi *main_vsi = pf->main_vsi;
2536 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2537 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2540 if (hw->adapter_stopped == 1)
2543 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2544 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2545 rte_intr_enable(intr_handle);
2548 /* Disable all queues */
2549 for (i = 0; i < dev->data->nb_tx_queues; i++)
2550 i40e_dev_tx_queue_stop(dev, i);
2552 for (i = 0; i < dev->data->nb_rx_queues; i++)
2553 i40e_dev_rx_queue_stop(dev, i);
2555 /* un-map queues with interrupt registers */
2556 i40e_vsi_disable_queues_intr(main_vsi);
2557 i40e_vsi_queues_unbind_intr(main_vsi);
2559 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2560 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2561 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2564 /* Clear all queues and release memory */
2565 i40e_dev_clear_queues(dev);
2568 i40e_dev_set_link_down(dev);
2570 if (!rte_intr_allow_others(intr_handle))
2571 /* resume to the default handler */
2572 rte_intr_callback_register(intr_handle,
2573 i40e_dev_interrupt_handler,
2576 /* Clean datapath event and queue/vec mapping */
2577 rte_intr_efd_disable(intr_handle);
2578 if (intr_handle->intr_vec) {
2579 rte_free(intr_handle->intr_vec);
2580 intr_handle->intr_vec = NULL;
2583 /* reset hierarchy commit */
2584 pf->tm_conf.committed = false;
2586 hw->adapter_stopped = 1;
2587 dev->data->dev_started = 0;
2589 pf->adapter->rss_reta_updated = 0;
2595 i40e_dev_close(struct rte_eth_dev *dev)
2597 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2599 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2600 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2601 struct i40e_mirror_rule *p_mirror;
2602 struct i40e_filter_control_settings settings;
2603 struct rte_flow *p_flow;
2607 uint8_t aq_fail = 0;
2610 PMD_INIT_FUNC_TRACE();
2611 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2614 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2616 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2619 ret = i40e_dev_stop(dev);
2621 /* Remove all mirror rules */
2622 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2623 ret = i40e_aq_del_mirror_rule(hw,
2624 pf->main_vsi->veb->seid,
2625 p_mirror->rule_type,
2627 p_mirror->num_entries,
2630 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2631 "status = %d, aq_err = %d.", ret,
2632 hw->aq.asq_last_status);
2634 /* remove mirror software resource anyway */
2635 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2637 pf->nb_mirror_rule--;
2640 i40e_dev_free_queues(dev);
2642 /* Disable interrupt */
2643 i40e_pf_disable_irq0(hw);
2644 rte_intr_disable(intr_handle);
2647 * Only legacy filter API needs the following fdir config. So when the
2648 * legacy filter API is deprecated, the following code should also be
2651 i40e_fdir_teardown(pf);
2653 /* shutdown and destroy the HMC */
2654 i40e_shutdown_lan_hmc(hw);
2656 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2657 i40e_vsi_release(pf->vmdq[i].vsi);
2658 pf->vmdq[i].vsi = NULL;
2663 /* release all the existing VSIs and VEBs */
2664 i40e_vsi_release(pf->main_vsi);
2666 /* shutdown the adminq */
2667 i40e_aq_queue_shutdown(hw, true);
2668 i40e_shutdown_adminq(hw);
2670 i40e_res_pool_destroy(&pf->qp_pool);
2671 i40e_res_pool_destroy(&pf->msix_pool);
2673 /* Disable flexible payload in global configuration */
2674 if (!pf->support_multi_driver)
2675 i40e_flex_payload_reg_set_default(hw);
2677 /* force a PF reset to clean anything leftover */
2678 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2679 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2680 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2681 I40E_WRITE_FLUSH(hw);
2683 /* Clear PXE mode */
2684 i40e_clear_pxe_mode(hw);
2686 /* Unconfigure filter control */
2687 memset(&settings, 0, sizeof(settings));
2688 ret = i40e_set_filter_control(hw, &settings);
2690 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2693 /* Disable flow control */
2694 hw->fc.requested_mode = I40E_FC_NONE;
2695 i40e_set_fc(hw, &aq_fail, TRUE);
2697 /* uninitialize pf host driver */
2698 i40e_pf_host_uninit(dev);
2701 ret = rte_intr_callback_unregister(intr_handle,
2702 i40e_dev_interrupt_handler, dev);
2703 if (ret >= 0 || ret == -ENOENT) {
2705 } else if (ret != -EAGAIN) {
2707 "intr callback unregister failed: %d",
2710 i40e_msec_delay(500);
2711 } while (retries++ < 5);
2713 i40e_rm_ethtype_filter_list(pf);
2714 i40e_rm_tunnel_filter_list(pf);
2715 i40e_rm_fdir_filter_list(pf);
2717 /* Remove all flows */
2718 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2719 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2720 /* Do not free FDIR flows since they are static allocated */
2721 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2725 /* release the fdir static allocated memory */
2726 i40e_fdir_memory_cleanup(pf);
2728 /* Remove all Traffic Manager configuration */
2729 i40e_tm_conf_uninit(dev);
2731 i40e_clear_automask(pf);
2733 hw->adapter_closed = 1;
2738 * Reset PF device only to re-initialize resources in PMD layer
2741 i40e_dev_reset(struct rte_eth_dev *dev)
2745 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2746 * its VF to make them align with it. The detailed notification
2747 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2748 * To avoid unexpected behavior in VF, currently reset of PF with
2749 * SR-IOV activation is not supported. It might be supported later.
2751 if (dev->data->sriov.active)
2754 ret = eth_i40e_dev_uninit(dev);
2758 ret = eth_i40e_dev_init(dev, NULL);
2764 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2766 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768 struct i40e_vsi *vsi = pf->main_vsi;
2771 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2773 if (status != I40E_SUCCESS) {
2774 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2778 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2780 if (status != I40E_SUCCESS) {
2781 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2782 /* Rollback unicast promiscuous mode */
2783 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2792 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2794 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2795 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796 struct i40e_vsi *vsi = pf->main_vsi;
2799 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2801 if (status != I40E_SUCCESS) {
2802 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2806 /* must remain in all_multicast mode */
2807 if (dev->data->all_multicast == 1)
2810 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2812 if (status != I40E_SUCCESS) {
2813 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2814 /* Rollback unicast promiscuous mode */
2815 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2824 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2826 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828 struct i40e_vsi *vsi = pf->main_vsi;
2831 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2832 if (ret != I40E_SUCCESS) {
2833 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2841 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2844 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845 struct i40e_vsi *vsi = pf->main_vsi;
2848 if (dev->data->promiscuous == 1)
2849 return 0; /* must remain in all_multicast mode */
2851 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2852 vsi->seid, FALSE, NULL);
2853 if (ret != I40E_SUCCESS) {
2854 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2862 * Set device link up.
2865 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2867 /* re-apply link speed setting */
2868 return i40e_apply_link_speed(dev);
2872 * Set device link down.
2875 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2877 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2878 uint8_t abilities = 0;
2879 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2882 return i40e_phy_conf_link(hw, abilities, speed, false);
2885 static __rte_always_inline void
2886 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2888 /* Link status registers and values*/
2889 #define I40E_PRTMAC_LINKSTA 0x001E2420
2890 #define I40E_REG_LINK_UP 0x40000080
2891 #define I40E_PRTMAC_MACC 0x001E24E0
2892 #define I40E_REG_MACC_25GB 0x00020000
2893 #define I40E_REG_SPEED_MASK 0x38000000
2894 #define I40E_REG_SPEED_0 0x00000000
2895 #define I40E_REG_SPEED_1 0x08000000
2896 #define I40E_REG_SPEED_2 0x10000000
2897 #define I40E_REG_SPEED_3 0x18000000
2898 #define I40E_REG_SPEED_4 0x20000000
2899 uint32_t link_speed;
2902 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2903 link_speed = reg_val & I40E_REG_SPEED_MASK;
2904 reg_val &= I40E_REG_LINK_UP;
2905 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2907 if (unlikely(link->link_status == 0))
2910 /* Parse the link status */
2911 switch (link_speed) {
2912 case I40E_REG_SPEED_0:
2913 link->link_speed = ETH_SPEED_NUM_100M;
2915 case I40E_REG_SPEED_1:
2916 link->link_speed = ETH_SPEED_NUM_1G;
2918 case I40E_REG_SPEED_2:
2919 if (hw->mac.type == I40E_MAC_X722)
2920 link->link_speed = ETH_SPEED_NUM_2_5G;
2922 link->link_speed = ETH_SPEED_NUM_10G;
2924 case I40E_REG_SPEED_3:
2925 if (hw->mac.type == I40E_MAC_X722) {
2926 link->link_speed = ETH_SPEED_NUM_5G;
2928 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2930 if (reg_val & I40E_REG_MACC_25GB)
2931 link->link_speed = ETH_SPEED_NUM_25G;
2933 link->link_speed = ETH_SPEED_NUM_40G;
2936 case I40E_REG_SPEED_4:
2937 if (hw->mac.type == I40E_MAC_X722)
2938 link->link_speed = ETH_SPEED_NUM_10G;
2940 link->link_speed = ETH_SPEED_NUM_20G;
2943 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2948 static __rte_always_inline void
2949 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2950 bool enable_lse, int wait_to_complete)
2952 #define CHECK_INTERVAL 100 /* 100ms */
2953 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2954 uint32_t rep_cnt = MAX_REPEAT_TIME;
2955 struct i40e_link_status link_status;
2958 memset(&link_status, 0, sizeof(link_status));
2961 memset(&link_status, 0, sizeof(link_status));
2963 /* Get link status information from hardware */
2964 status = i40e_aq_get_link_info(hw, enable_lse,
2965 &link_status, NULL);
2966 if (unlikely(status != I40E_SUCCESS)) {
2967 link->link_speed = ETH_SPEED_NUM_NONE;
2968 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2969 PMD_DRV_LOG(ERR, "Failed to get link info");
2973 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2974 if (!wait_to_complete || link->link_status)
2977 rte_delay_ms(CHECK_INTERVAL);
2978 } while (--rep_cnt);
2980 /* Parse the link status */
2981 switch (link_status.link_speed) {
2982 case I40E_LINK_SPEED_100MB:
2983 link->link_speed = ETH_SPEED_NUM_100M;
2985 case I40E_LINK_SPEED_1GB:
2986 link->link_speed = ETH_SPEED_NUM_1G;
2988 case I40E_LINK_SPEED_10GB:
2989 link->link_speed = ETH_SPEED_NUM_10G;
2991 case I40E_LINK_SPEED_20GB:
2992 link->link_speed = ETH_SPEED_NUM_20G;
2994 case I40E_LINK_SPEED_25GB:
2995 link->link_speed = ETH_SPEED_NUM_25G;
2997 case I40E_LINK_SPEED_40GB:
2998 link->link_speed = ETH_SPEED_NUM_40G;
3001 if (link->link_status)
3002 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3004 link->link_speed = ETH_SPEED_NUM_NONE;
3010 i40e_dev_link_update(struct rte_eth_dev *dev,
3011 int wait_to_complete)
3013 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3014 struct rte_eth_link link;
3015 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3018 memset(&link, 0, sizeof(link));
3020 /* i40e uses full duplex only */
3021 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3022 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3023 ETH_LINK_SPEED_FIXED);
3025 if (!wait_to_complete && !enable_lse)
3026 update_link_reg(hw, &link);
3028 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3031 rte_eth_linkstatus_get(hw->switch_dev, &link);
3033 ret = rte_eth_linkstatus_set(dev, &link);
3034 i40e_notify_all_vfs_link_status(dev);
3040 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3041 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3042 uint64_t *stat, uint64_t *prev_stat)
3044 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3045 /* enlarge the limitation when statistics counters overflowed */
3046 if (offset_loaded) {
3047 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3048 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3049 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3054 /* Get all the statistics of a VSI */
3056 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3058 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3059 struct i40e_eth_stats *nes = &vsi->eth_stats;
3060 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3061 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3063 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3064 vsi->offset_loaded, &oes->rx_bytes,
3065 &nes->rx_bytes, &vsi->prev_rx_bytes);
3066 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3067 vsi->offset_loaded, &oes->rx_unicast,
3069 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3070 vsi->offset_loaded, &oes->rx_multicast,
3071 &nes->rx_multicast);
3072 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3073 vsi->offset_loaded, &oes->rx_broadcast,
3074 &nes->rx_broadcast);
3075 /* exclude CRC bytes */
3076 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3077 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3079 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3080 &oes->rx_discards, &nes->rx_discards);
3081 /* GLV_REPC not supported */
3082 /* GLV_RMPC not supported */
3083 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3084 &oes->rx_unknown_protocol,
3085 &nes->rx_unknown_protocol);
3086 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3087 vsi->offset_loaded, &oes->tx_bytes,
3088 &nes->tx_bytes, &vsi->prev_tx_bytes);
3089 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3090 vsi->offset_loaded, &oes->tx_unicast,
3092 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3093 vsi->offset_loaded, &oes->tx_multicast,
3094 &nes->tx_multicast);
3095 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3096 vsi->offset_loaded, &oes->tx_broadcast,
3097 &nes->tx_broadcast);
3098 /* GLV_TDPC not supported */
3099 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3100 &oes->tx_errors, &nes->tx_errors);
3101 vsi->offset_loaded = true;
3103 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3105 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3106 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3107 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3108 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3109 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3110 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3111 nes->rx_unknown_protocol);
3112 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3113 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3114 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3115 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3116 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3117 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3118 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3123 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3126 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3127 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3129 /* Get rx/tx bytes of internal transfer packets */
3130 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3131 I40E_GLV_GORCL(hw->port),
3133 &pf->internal_stats_offset.rx_bytes,
3134 &pf->internal_stats.rx_bytes,
3135 &pf->internal_prev_rx_bytes);
3136 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3137 I40E_GLV_GOTCL(hw->port),
3139 &pf->internal_stats_offset.tx_bytes,
3140 &pf->internal_stats.tx_bytes,
3141 &pf->internal_prev_tx_bytes);
3142 /* Get total internal rx packet count */
3143 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3144 I40E_GLV_UPRCL(hw->port),
3146 &pf->internal_stats_offset.rx_unicast,
3147 &pf->internal_stats.rx_unicast);
3148 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3149 I40E_GLV_MPRCL(hw->port),
3151 &pf->internal_stats_offset.rx_multicast,
3152 &pf->internal_stats.rx_multicast);
3153 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3154 I40E_GLV_BPRCL(hw->port),
3156 &pf->internal_stats_offset.rx_broadcast,
3157 &pf->internal_stats.rx_broadcast);
3158 /* Get total internal tx packet count */
3159 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3160 I40E_GLV_UPTCL(hw->port),
3162 &pf->internal_stats_offset.tx_unicast,
3163 &pf->internal_stats.tx_unicast);
3164 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3165 I40E_GLV_MPTCL(hw->port),
3167 &pf->internal_stats_offset.tx_multicast,
3168 &pf->internal_stats.tx_multicast);
3169 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3170 I40E_GLV_BPTCL(hw->port),
3172 &pf->internal_stats_offset.tx_broadcast,
3173 &pf->internal_stats.tx_broadcast);
3175 /* exclude CRC size */
3176 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3177 pf->internal_stats.rx_multicast +
3178 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3180 /* Get statistics of struct i40e_eth_stats */
3181 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3182 I40E_GLPRT_GORCL(hw->port),
3183 pf->offset_loaded, &os->eth.rx_bytes,
3184 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3185 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3186 I40E_GLPRT_UPRCL(hw->port),
3187 pf->offset_loaded, &os->eth.rx_unicast,
3188 &ns->eth.rx_unicast);
3189 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3190 I40E_GLPRT_MPRCL(hw->port),
3191 pf->offset_loaded, &os->eth.rx_multicast,
3192 &ns->eth.rx_multicast);
3193 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3194 I40E_GLPRT_BPRCL(hw->port),
3195 pf->offset_loaded, &os->eth.rx_broadcast,
3196 &ns->eth.rx_broadcast);
3197 /* Workaround: CRC size should not be included in byte statistics,
3198 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3201 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3202 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3204 /* exclude internal rx bytes
3205 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3206 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3208 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3210 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3211 ns->eth.rx_bytes = 0;
3213 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3215 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3216 ns->eth.rx_unicast = 0;
3218 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3220 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3221 ns->eth.rx_multicast = 0;
3223 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3225 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3226 ns->eth.rx_broadcast = 0;
3228 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3230 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3231 pf->offset_loaded, &os->eth.rx_discards,
3232 &ns->eth.rx_discards);
3233 /* GLPRT_REPC not supported */
3234 /* GLPRT_RMPC not supported */
3235 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3237 &os->eth.rx_unknown_protocol,
3238 &ns->eth.rx_unknown_protocol);
3239 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3240 I40E_GLPRT_GOTCL(hw->port),
3241 pf->offset_loaded, &os->eth.tx_bytes,
3242 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3243 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3244 I40E_GLPRT_UPTCL(hw->port),
3245 pf->offset_loaded, &os->eth.tx_unicast,
3246 &ns->eth.tx_unicast);
3247 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3248 I40E_GLPRT_MPTCL(hw->port),
3249 pf->offset_loaded, &os->eth.tx_multicast,
3250 &ns->eth.tx_multicast);
3251 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3252 I40E_GLPRT_BPTCL(hw->port),
3253 pf->offset_loaded, &os->eth.tx_broadcast,
3254 &ns->eth.tx_broadcast);
3255 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3256 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3258 /* exclude internal tx bytes
3259 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3260 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3262 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3264 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3265 ns->eth.tx_bytes = 0;
3267 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3269 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3270 ns->eth.tx_unicast = 0;
3272 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3274 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3275 ns->eth.tx_multicast = 0;
3277 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3279 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3280 ns->eth.tx_broadcast = 0;
3282 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3284 /* GLPRT_TEPC not supported */
3286 /* additional port specific stats */
3287 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3288 pf->offset_loaded, &os->tx_dropped_link_down,
3289 &ns->tx_dropped_link_down);
3290 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3291 pf->offset_loaded, &os->crc_errors,
3293 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3294 pf->offset_loaded, &os->illegal_bytes,
3295 &ns->illegal_bytes);
3296 /* GLPRT_ERRBC not supported */
3297 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3298 pf->offset_loaded, &os->mac_local_faults,
3299 &ns->mac_local_faults);
3300 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3301 pf->offset_loaded, &os->mac_remote_faults,
3302 &ns->mac_remote_faults);
3303 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3304 pf->offset_loaded, &os->rx_length_errors,
3305 &ns->rx_length_errors);
3306 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3307 pf->offset_loaded, &os->link_xon_rx,
3309 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3310 pf->offset_loaded, &os->link_xoff_rx,
3312 for (i = 0; i < 8; i++) {
3313 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3315 &os->priority_xon_rx[i],
3316 &ns->priority_xon_rx[i]);
3317 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3319 &os->priority_xoff_rx[i],
3320 &ns->priority_xoff_rx[i]);
3322 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3323 pf->offset_loaded, &os->link_xon_tx,
3325 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3326 pf->offset_loaded, &os->link_xoff_tx,
3328 for (i = 0; i < 8; i++) {
3329 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3331 &os->priority_xon_tx[i],
3332 &ns->priority_xon_tx[i]);
3333 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3335 &os->priority_xoff_tx[i],
3336 &ns->priority_xoff_tx[i]);
3337 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3339 &os->priority_xon_2_xoff[i],
3340 &ns->priority_xon_2_xoff[i]);
3342 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3343 I40E_GLPRT_PRC64L(hw->port),
3344 pf->offset_loaded, &os->rx_size_64,
3346 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3347 I40E_GLPRT_PRC127L(hw->port),
3348 pf->offset_loaded, &os->rx_size_127,
3350 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3351 I40E_GLPRT_PRC255L(hw->port),
3352 pf->offset_loaded, &os->rx_size_255,
3354 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3355 I40E_GLPRT_PRC511L(hw->port),
3356 pf->offset_loaded, &os->rx_size_511,
3358 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3359 I40E_GLPRT_PRC1023L(hw->port),
3360 pf->offset_loaded, &os->rx_size_1023,
3362 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3363 I40E_GLPRT_PRC1522L(hw->port),
3364 pf->offset_loaded, &os->rx_size_1522,
3366 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3367 I40E_GLPRT_PRC9522L(hw->port),
3368 pf->offset_loaded, &os->rx_size_big,
3370 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3371 pf->offset_loaded, &os->rx_undersize,
3373 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3374 pf->offset_loaded, &os->rx_fragments,
3376 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3377 pf->offset_loaded, &os->rx_oversize,
3379 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3380 pf->offset_loaded, &os->rx_jabber,
3382 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3383 I40E_GLPRT_PTC64L(hw->port),
3384 pf->offset_loaded, &os->tx_size_64,
3386 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3387 I40E_GLPRT_PTC127L(hw->port),
3388 pf->offset_loaded, &os->tx_size_127,
3390 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3391 I40E_GLPRT_PTC255L(hw->port),
3392 pf->offset_loaded, &os->tx_size_255,
3394 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3395 I40E_GLPRT_PTC511L(hw->port),
3396 pf->offset_loaded, &os->tx_size_511,
3398 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3399 I40E_GLPRT_PTC1023L(hw->port),
3400 pf->offset_loaded, &os->tx_size_1023,
3402 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3403 I40E_GLPRT_PTC1522L(hw->port),
3404 pf->offset_loaded, &os->tx_size_1522,
3406 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3407 I40E_GLPRT_PTC9522L(hw->port),
3408 pf->offset_loaded, &os->tx_size_big,
3410 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3412 &os->fd_sb_match, &ns->fd_sb_match);
3413 /* GLPRT_MSPDC not supported */
3414 /* GLPRT_XEC not supported */
3416 pf->offset_loaded = true;
3419 i40e_update_vsi_stats(pf->main_vsi);
3422 /* Get all statistics of a port */
3424 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3426 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3429 struct i40e_vsi *vsi;
3432 /* call read registers - updates values, now write them to struct */
3433 i40e_read_stats_registers(pf, hw);
3435 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3436 pf->main_vsi->eth_stats.rx_multicast +
3437 pf->main_vsi->eth_stats.rx_broadcast -
3438 pf->main_vsi->eth_stats.rx_discards;
3439 stats->opackets = ns->eth.tx_unicast +
3440 ns->eth.tx_multicast +
3441 ns->eth.tx_broadcast;
3442 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3443 stats->obytes = ns->eth.tx_bytes;
3444 stats->oerrors = ns->eth.tx_errors +
3445 pf->main_vsi->eth_stats.tx_errors;
3448 stats->imissed = ns->eth.rx_discards +
3449 pf->main_vsi->eth_stats.rx_discards;
3450 stats->ierrors = ns->crc_errors +
3451 ns->rx_length_errors + ns->rx_undersize +
3452 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3455 for (i = 0; i < pf->vf_num; i++) {
3456 vsi = pf->vfs[i].vsi;
3457 i40e_update_vsi_stats(vsi);
3459 stats->ipackets += (vsi->eth_stats.rx_unicast +
3460 vsi->eth_stats.rx_multicast +
3461 vsi->eth_stats.rx_broadcast -
3462 vsi->eth_stats.rx_discards);
3463 stats->ibytes += vsi->eth_stats.rx_bytes;
3464 stats->oerrors += vsi->eth_stats.tx_errors;
3465 stats->imissed += vsi->eth_stats.rx_discards;
3469 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3470 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3471 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3472 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3473 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3474 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3475 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3476 ns->eth.rx_unknown_protocol);
3477 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3478 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3479 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3480 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3481 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3482 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3484 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3485 ns->tx_dropped_link_down);
3486 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3487 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3489 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3490 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3491 ns->mac_local_faults);
3492 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3493 ns->mac_remote_faults);
3494 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3495 ns->rx_length_errors);
3496 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3497 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3498 for (i = 0; i < 8; i++) {
3499 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3500 i, ns->priority_xon_rx[i]);
3501 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3502 i, ns->priority_xoff_rx[i]);
3504 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3505 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3506 for (i = 0; i < 8; i++) {
3507 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3508 i, ns->priority_xon_tx[i]);
3509 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3510 i, ns->priority_xoff_tx[i]);
3511 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3512 i, ns->priority_xon_2_xoff[i]);
3514 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3515 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3516 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3517 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3518 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3519 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3520 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3521 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3522 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3523 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3524 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3525 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3526 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3527 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3528 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3529 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3530 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3531 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3532 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3533 ns->mac_short_packet_dropped);
3534 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3535 ns->checksum_error);
3536 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3537 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3541 /* Reset the statistics */
3543 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3545 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3546 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548 /* Mark PF and VSI stats to update the offset, aka "reset" */
3549 pf->offset_loaded = false;
3551 pf->main_vsi->offset_loaded = false;
3553 /* read the stats, reading current register values into offset */
3554 i40e_read_stats_registers(pf, hw);
3560 i40e_xstats_calc_num(void)
3562 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3563 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3564 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3567 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3568 struct rte_eth_xstat_name *xstats_names,
3569 __rte_unused unsigned limit)
3574 if (xstats_names == NULL)
3575 return i40e_xstats_calc_num();
3577 /* Note: limit checked in rte_eth_xstats_names() */
3579 /* Get stats from i40e_eth_stats struct */
3580 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3581 strlcpy(xstats_names[count].name,
3582 rte_i40e_stats_strings[i].name,
3583 sizeof(xstats_names[count].name));
3587 /* Get individiual stats from i40e_hw_port struct */
3588 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3589 strlcpy(xstats_names[count].name,
3590 rte_i40e_hw_port_strings[i].name,
3591 sizeof(xstats_names[count].name));
3595 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3596 for (prio = 0; prio < 8; prio++) {
3597 snprintf(xstats_names[count].name,
3598 sizeof(xstats_names[count].name),
3599 "rx_priority%u_%s", prio,
3600 rte_i40e_rxq_prio_strings[i].name);
3605 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3606 for (prio = 0; prio < 8; prio++) {
3607 snprintf(xstats_names[count].name,
3608 sizeof(xstats_names[count].name),
3609 "tx_priority%u_%s", prio,
3610 rte_i40e_txq_prio_strings[i].name);
3618 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3621 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3622 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623 unsigned i, count, prio;
3624 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3626 count = i40e_xstats_calc_num();
3630 i40e_read_stats_registers(pf, hw);
3637 /* Get stats from i40e_eth_stats struct */
3638 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3639 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3640 rte_i40e_stats_strings[i].offset);
3641 xstats[count].id = count;
3645 /* Get individiual stats from i40e_hw_port struct */
3646 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3647 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3648 rte_i40e_hw_port_strings[i].offset);
3649 xstats[count].id = count;
3653 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3654 for (prio = 0; prio < 8; prio++) {
3655 xstats[count].value =
3656 *(uint64_t *)(((char *)hw_stats) +
3657 rte_i40e_rxq_prio_strings[i].offset +
3658 (sizeof(uint64_t) * prio));
3659 xstats[count].id = count;
3664 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3665 for (prio = 0; prio < 8; prio++) {
3666 xstats[count].value =
3667 *(uint64_t *)(((char *)hw_stats) +
3668 rte_i40e_txq_prio_strings[i].offset +
3669 (sizeof(uint64_t) * prio));
3670 xstats[count].id = count;
3679 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3681 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3687 full_ver = hw->nvm.oem_ver;
3688 ver = (u8)(full_ver >> 24);
3689 build = (u16)((full_ver >> 8) & 0xffff);
3690 patch = (u8)(full_ver & 0xff);
3692 ret = snprintf(fw_version, fw_size,
3693 "%d.%d%d 0x%08x %d.%d.%d",
3694 ((hw->nvm.version >> 12) & 0xf),
3695 ((hw->nvm.version >> 4) & 0xff),
3696 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3701 ret += 1; /* add the size of '\0' */
3702 if (fw_size < (size_t)ret)
3709 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3710 * the Rx data path does not hang if the FW LLDP is stopped.
3711 * return true if lldp need to stop
3712 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3715 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3718 char ver_str[64] = {0};
3719 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3721 i40e_fw_version_get(dev, ver_str, 64);
3722 nvm_ver = atof(ver_str);
3723 if ((hw->mac.type == I40E_MAC_X722 ||
3724 hw->mac.type == I40E_MAC_X722_VF) &&
3725 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3727 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3734 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3736 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3737 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 struct i40e_vsi *vsi = pf->main_vsi;
3739 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3741 dev_info->max_rx_queues = vsi->nb_qps;
3742 dev_info->max_tx_queues = vsi->nb_qps;
3743 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3744 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3745 dev_info->max_mac_addrs = vsi->max_macaddrs;
3746 dev_info->max_vfs = pci_dev->max_vfs;
3747 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3748 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3749 dev_info->rx_queue_offload_capa = 0;
3750 dev_info->rx_offload_capa =
3751 DEV_RX_OFFLOAD_VLAN_STRIP |
3752 DEV_RX_OFFLOAD_QINQ_STRIP |
3753 DEV_RX_OFFLOAD_IPV4_CKSUM |
3754 DEV_RX_OFFLOAD_UDP_CKSUM |
3755 DEV_RX_OFFLOAD_TCP_CKSUM |
3756 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3757 DEV_RX_OFFLOAD_KEEP_CRC |
3758 DEV_RX_OFFLOAD_SCATTER |
3759 DEV_RX_OFFLOAD_VLAN_EXTEND |
3760 DEV_RX_OFFLOAD_VLAN_FILTER |
3761 DEV_RX_OFFLOAD_JUMBO_FRAME |
3762 DEV_RX_OFFLOAD_RSS_HASH;
3764 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3765 dev_info->tx_offload_capa =
3766 DEV_TX_OFFLOAD_VLAN_INSERT |
3767 DEV_TX_OFFLOAD_QINQ_INSERT |
3768 DEV_TX_OFFLOAD_IPV4_CKSUM |
3769 DEV_TX_OFFLOAD_UDP_CKSUM |
3770 DEV_TX_OFFLOAD_TCP_CKSUM |
3771 DEV_TX_OFFLOAD_SCTP_CKSUM |
3772 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3773 DEV_TX_OFFLOAD_TCP_TSO |
3774 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3775 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3776 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3777 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3778 DEV_TX_OFFLOAD_MULTI_SEGS |
3779 dev_info->tx_queue_offload_capa;
3780 dev_info->dev_capa =
3781 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3782 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3784 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3786 dev_info->reta_size = pf->hash_lut_size;
3787 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3789 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3791 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3792 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3793 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3795 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3800 dev_info->default_txconf = (struct rte_eth_txconf) {
3802 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3803 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3804 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3806 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3807 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3811 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3812 .nb_max = I40E_MAX_RING_DESC,
3813 .nb_min = I40E_MIN_RING_DESC,
3814 .nb_align = I40E_ALIGN_RING_DESC,
3817 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3818 .nb_max = I40E_MAX_RING_DESC,
3819 .nb_min = I40E_MIN_RING_DESC,
3820 .nb_align = I40E_ALIGN_RING_DESC,
3821 .nb_seg_max = I40E_TX_MAX_SEG,
3822 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3825 if (pf->flags & I40E_FLAG_VMDQ) {
3826 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3827 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3828 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3829 pf->max_nb_vmdq_vsi;
3830 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3831 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3832 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3835 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3837 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3838 dev_info->default_rxportconf.nb_queues = 2;
3839 dev_info->default_txportconf.nb_queues = 2;
3840 if (dev->data->nb_rx_queues == 1)
3841 dev_info->default_rxportconf.ring_size = 2048;
3843 dev_info->default_rxportconf.ring_size = 1024;
3844 if (dev->data->nb_tx_queues == 1)
3845 dev_info->default_txportconf.ring_size = 1024;
3847 dev_info->default_txportconf.ring_size = 512;
3849 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3851 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3852 dev_info->default_rxportconf.nb_queues = 1;
3853 dev_info->default_txportconf.nb_queues = 1;
3854 dev_info->default_rxportconf.ring_size = 256;
3855 dev_info->default_txportconf.ring_size = 256;
3858 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3859 dev_info->default_rxportconf.nb_queues = 1;
3860 dev_info->default_txportconf.nb_queues = 1;
3861 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3862 dev_info->default_rxportconf.ring_size = 512;
3863 dev_info->default_txportconf.ring_size = 256;
3865 dev_info->default_rxportconf.ring_size = 256;
3866 dev_info->default_txportconf.ring_size = 256;
3869 dev_info->default_rxportconf.burst_size = 32;
3870 dev_info->default_txportconf.burst_size = 32;
3876 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3878 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3879 struct i40e_vsi *vsi = pf->main_vsi;
3880 PMD_INIT_FUNC_TRACE();
3883 return i40e_vsi_add_vlan(vsi, vlan_id);
3885 return i40e_vsi_delete_vlan(vsi, vlan_id);
3889 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3890 enum rte_vlan_type vlan_type,
3891 uint16_t tpid, int qinq)
3893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3896 uint16_t reg_id = 3;
3900 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3904 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3906 if (ret != I40E_SUCCESS) {
3908 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3913 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3916 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3917 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3918 if (reg_r == reg_w) {
3919 PMD_DRV_LOG(DEBUG, "No need to write");
3923 ret = i40e_aq_debug_write_global_register(hw,
3924 I40E_GL_SWT_L2TAGCTRL(reg_id),
3926 if (ret != I40E_SUCCESS) {
3928 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3933 "Global register 0x%08x is changed with value 0x%08x",
3934 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3940 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3941 enum rte_vlan_type vlan_type,
3944 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3946 int qinq = dev->data->dev_conf.rxmode.offloads &
3947 DEV_RX_OFFLOAD_VLAN_EXTEND;
3950 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3951 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3952 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3954 "Unsupported vlan type.");
3958 if (pf->support_multi_driver) {
3959 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3963 /* 802.1ad frames ability is added in NVM API 1.7*/
3964 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3966 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3967 hw->first_tag = rte_cpu_to_le_16(tpid);
3968 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3969 hw->second_tag = rte_cpu_to_le_16(tpid);
3971 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3972 hw->second_tag = rte_cpu_to_le_16(tpid);
3974 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3975 if (ret != I40E_SUCCESS) {
3977 "Set switch config failed aq_err: %d",
3978 hw->aq.asq_last_status);
3982 /* If NVM API < 1.7, keep the register setting */
3983 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3989 /* Configure outer vlan stripping on or off in QinQ mode */
3991 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3993 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3994 int ret = I40E_SUCCESS;
3997 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3998 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4002 /* Configure for outer VLAN RX stripping */
4003 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4006 reg |= I40E_VSI_TSR_QINQ_STRIP;
4008 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4010 ret = i40e_aq_debug_write_register(hw,
4011 I40E_VSI_TSR(vsi->vsi_id),
4014 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4016 return I40E_ERR_CONFIG;
4023 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4025 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4026 struct i40e_vsi *vsi = pf->main_vsi;
4027 struct rte_eth_rxmode *rxmode;
4029 rxmode = &dev->data->dev_conf.rxmode;
4030 if (mask & ETH_VLAN_FILTER_MASK) {
4031 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4032 i40e_vsi_config_vlan_filter(vsi, TRUE);
4034 i40e_vsi_config_vlan_filter(vsi, FALSE);
4037 if (mask & ETH_VLAN_STRIP_MASK) {
4038 /* Enable or disable VLAN stripping */
4039 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4040 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4042 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4045 if (mask & ETH_VLAN_EXTEND_MASK) {
4046 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4047 i40e_vsi_config_double_vlan(vsi, TRUE);
4048 /* Set global registers with default ethertype. */
4049 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4050 RTE_ETHER_TYPE_VLAN);
4051 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4052 RTE_ETHER_TYPE_VLAN);
4055 i40e_vsi_config_double_vlan(vsi, FALSE);
4058 if (mask & ETH_QINQ_STRIP_MASK) {
4059 /* Enable or disable outer VLAN stripping */
4060 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4061 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4063 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4070 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4071 __rte_unused uint16_t queue,
4072 __rte_unused int on)
4074 PMD_INIT_FUNC_TRACE();
4078 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4080 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4081 struct i40e_vsi *vsi = pf->main_vsi;
4082 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4083 struct i40e_vsi_vlan_pvid_info info;
4085 memset(&info, 0, sizeof(info));
4088 info.config.pvid = pvid;
4090 info.config.reject.tagged =
4091 data->dev_conf.txmode.hw_vlan_reject_tagged;
4092 info.config.reject.untagged =
4093 data->dev_conf.txmode.hw_vlan_reject_untagged;
4096 return i40e_vsi_vlan_pvid_set(vsi, &info);
4100 i40e_dev_led_on(struct rte_eth_dev *dev)
4102 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103 uint32_t mode = i40e_led_get(hw);
4106 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4112 i40e_dev_led_off(struct rte_eth_dev *dev)
4114 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115 uint32_t mode = i40e_led_get(hw);
4118 i40e_led_set(hw, 0, false);
4124 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4126 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4129 fc_conf->pause_time = pf->fc_conf.pause_time;
4131 /* read out from register, in case they are modified by other port */
4132 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4133 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4134 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4135 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4137 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4138 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4140 /* Return current mode according to actual setting*/
4141 switch (hw->fc.current_mode) {
4143 fc_conf->mode = RTE_FC_FULL;
4145 case I40E_FC_TX_PAUSE:
4146 fc_conf->mode = RTE_FC_TX_PAUSE;
4148 case I40E_FC_RX_PAUSE:
4149 fc_conf->mode = RTE_FC_RX_PAUSE;
4153 fc_conf->mode = RTE_FC_NONE;
4160 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4162 uint32_t mflcn_reg, fctrl_reg, reg;
4163 uint32_t max_high_water;
4164 uint8_t i, aq_failure;
4168 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4169 [RTE_FC_NONE] = I40E_FC_NONE,
4170 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4171 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4172 [RTE_FC_FULL] = I40E_FC_FULL
4175 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4177 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4178 if ((fc_conf->high_water > max_high_water) ||
4179 (fc_conf->high_water < fc_conf->low_water)) {
4181 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4186 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4188 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4190 pf->fc_conf.pause_time = fc_conf->pause_time;
4191 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4192 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4194 PMD_INIT_FUNC_TRACE();
4196 /* All the link flow control related enable/disable register
4197 * configuration is handle by the F/W
4199 err = i40e_set_fc(hw, &aq_failure, true);
4203 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4204 /* Configure flow control refresh threshold,
4205 * the value for stat_tx_pause_refresh_timer[8]
4206 * is used for global pause operation.
4210 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4211 pf->fc_conf.pause_time);
4213 /* configure the timer value included in transmitted pause
4215 * the value for stat_tx_pause_quanta[8] is used for global
4218 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4219 pf->fc_conf.pause_time);
4221 fctrl_reg = I40E_READ_REG(hw,
4222 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4224 if (fc_conf->mac_ctrl_frame_fwd != 0)
4225 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4227 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4229 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4232 /* Configure pause time (2 TCs per register) */
4233 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4234 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4235 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4237 /* Configure flow control refresh threshold value */
4238 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4239 pf->fc_conf.pause_time / 2);
4241 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4243 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4244 *depending on configuration
4246 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4247 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4248 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4250 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4251 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4254 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4257 if (!pf->support_multi_driver) {
4258 /* config water marker both based on the packets and bytes */
4259 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4260 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4261 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4262 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4263 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4264 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4265 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4266 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4268 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4269 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4273 "Water marker configuration is not supported.");
4276 I40E_WRITE_FLUSH(hw);
4282 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4283 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4285 PMD_INIT_FUNC_TRACE();
4290 /* Add a MAC address, and update filters */
4292 i40e_macaddr_add(struct rte_eth_dev *dev,
4293 struct rte_ether_addr *mac_addr,
4294 __rte_unused uint32_t index,
4297 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4298 struct i40e_mac_filter_info mac_filter;
4299 struct i40e_vsi *vsi;
4300 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4303 /* If VMDQ not enabled or configured, return */
4304 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4305 !pf->nb_cfg_vmdq_vsi)) {
4306 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4307 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4312 if (pool > pf->nb_cfg_vmdq_vsi) {
4313 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4314 pool, pf->nb_cfg_vmdq_vsi);
4318 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4319 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4320 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4322 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4327 vsi = pf->vmdq[pool - 1].vsi;
4329 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4330 if (ret != I40E_SUCCESS) {
4331 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4337 /* Remove a MAC address, and update filters */
4339 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4342 struct i40e_vsi *vsi;
4343 struct rte_eth_dev_data *data = dev->data;
4344 struct rte_ether_addr *macaddr;
4349 macaddr = &(data->mac_addrs[index]);
4351 pool_sel = dev->data->mac_pool_sel[index];
4353 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4354 if (pool_sel & (1ULL << i)) {
4358 /* No VMDQ pool enabled or configured */
4359 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4360 (i > pf->nb_cfg_vmdq_vsi)) {
4362 "No VMDQ pool enabled/configured");
4365 vsi = pf->vmdq[i - 1].vsi;
4367 ret = i40e_vsi_delete_mac(vsi, macaddr);
4370 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4378 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4380 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4381 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4388 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4389 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4390 vsi->type != I40E_VSI_SRIOV,
4393 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4397 uint32_t *lut_dw = (uint32_t *)lut;
4398 uint16_t i, lut_size_dw = lut_size / 4;
4400 if (vsi->type == I40E_VSI_SRIOV) {
4401 for (i = 0; i <= lut_size_dw; i++) {
4402 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4403 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4406 for (i = 0; i < lut_size_dw; i++)
4407 lut_dw[i] = I40E_READ_REG(hw,
4416 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4424 pf = I40E_VSI_TO_PF(vsi);
4425 hw = I40E_VSI_TO_HW(vsi);
4427 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4428 enum i40e_status_code status;
4430 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4431 vsi->type != I40E_VSI_SRIOV,
4435 "Failed to update RSS lookup table, error status: %d",
4440 uint32_t *lut_dw = (uint32_t *)lut;
4441 uint16_t i, lut_size_dw = lut_size / 4;
4443 if (vsi->type == I40E_VSI_SRIOV) {
4444 for (i = 0; i < lut_size_dw; i++)
4447 I40E_VFQF_HLUT1(i, vsi->user_param),
4450 for (i = 0; i < lut_size_dw; i++)
4451 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4454 I40E_WRITE_FLUSH(hw);
4461 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4462 struct rte_eth_rss_reta_entry64 *reta_conf,
4465 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4466 uint16_t i, lut_size = pf->hash_lut_size;
4467 uint16_t idx, shift;
4471 if (reta_size != lut_size ||
4472 reta_size > ETH_RSS_RETA_SIZE_512) {
4474 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4475 reta_size, lut_size);
4479 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4481 PMD_DRV_LOG(ERR, "No memory can be allocated");
4484 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4487 for (i = 0; i < reta_size; i++) {
4488 idx = i / RTE_RETA_GROUP_SIZE;
4489 shift = i % RTE_RETA_GROUP_SIZE;
4490 if (reta_conf[idx].mask & (1ULL << shift))
4491 lut[i] = reta_conf[idx].reta[shift];
4493 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4495 pf->adapter->rss_reta_updated = 1;
4504 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4505 struct rte_eth_rss_reta_entry64 *reta_conf,
4508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4509 uint16_t i, lut_size = pf->hash_lut_size;
4510 uint16_t idx, shift;
4514 if (reta_size != lut_size ||
4515 reta_size > ETH_RSS_RETA_SIZE_512) {
4517 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4518 reta_size, lut_size);
4522 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4524 PMD_DRV_LOG(ERR, "No memory can be allocated");
4528 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4531 for (i = 0; i < reta_size; i++) {
4532 idx = i / RTE_RETA_GROUP_SIZE;
4533 shift = i % RTE_RETA_GROUP_SIZE;
4534 if (reta_conf[idx].mask & (1ULL << shift))
4535 reta_conf[idx].reta[shift] = lut[i];
4545 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4546 * @hw: pointer to the HW structure
4547 * @mem: pointer to mem struct to fill out
4548 * @size: size of memory requested
4549 * @alignment: what to align the allocation to
4551 enum i40e_status_code
4552 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4553 struct i40e_dma_mem *mem,
4557 const struct rte_memzone *mz = NULL;
4558 char z_name[RTE_MEMZONE_NAMESIZE];
4561 return I40E_ERR_PARAM;
4563 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4564 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4565 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4567 return I40E_ERR_NO_MEMORY;
4572 mem->zone = (const void *)mz;
4574 "memzone %s allocated with physical address: %"PRIu64,
4577 return I40E_SUCCESS;
4581 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4582 * @hw: pointer to the HW structure
4583 * @mem: ptr to mem struct to free
4585 enum i40e_status_code
4586 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4587 struct i40e_dma_mem *mem)
4590 return I40E_ERR_PARAM;
4593 "memzone %s to be freed with physical address: %"PRIu64,
4594 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4595 rte_memzone_free((const struct rte_memzone *)mem->zone);
4600 return I40E_SUCCESS;
4604 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4605 * @hw: pointer to the HW structure
4606 * @mem: pointer to mem struct to fill out
4607 * @size: size of memory requested
4609 enum i40e_status_code
4610 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4611 struct i40e_virt_mem *mem,
4615 return I40E_ERR_PARAM;
4618 mem->va = rte_zmalloc("i40e", size, 0);
4621 return I40E_SUCCESS;
4623 return I40E_ERR_NO_MEMORY;
4627 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4628 * @hw: pointer to the HW structure
4629 * @mem: pointer to mem struct to free
4631 enum i40e_status_code
4632 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4633 struct i40e_virt_mem *mem)
4636 return I40E_ERR_PARAM;
4641 return I40E_SUCCESS;
4645 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4647 rte_spinlock_init(&sp->spinlock);
4651 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4653 rte_spinlock_lock(&sp->spinlock);
4657 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4659 rte_spinlock_unlock(&sp->spinlock);
4663 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4669 * Get the hardware capabilities, which will be parsed
4670 * and saved into struct i40e_hw.
4673 i40e_get_cap(struct i40e_hw *hw)
4675 struct i40e_aqc_list_capabilities_element_resp *buf;
4676 uint16_t len, size = 0;
4679 /* Calculate a huge enough buff for saving response data temporarily */
4680 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4681 I40E_MAX_CAP_ELE_NUM;
4682 buf = rte_zmalloc("i40e", len, 0);
4684 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4685 return I40E_ERR_NO_MEMORY;
4688 /* Get, parse the capabilities and save it to hw */
4689 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4690 i40e_aqc_opc_list_func_capabilities, NULL);
4691 if (ret != I40E_SUCCESS)
4692 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4694 /* Free the temporary buffer after being used */
4700 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4702 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4710 pf = (struct i40e_pf *)opaque;
4714 num = strtoul(value, &end, 0);
4715 if (errno != 0 || end == value || *end != 0) {
4716 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4717 "kept the value = %hu", value, pf->vf_nb_qp_max);
4721 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4722 pf->vf_nb_qp_max = (uint16_t)num;
4724 /* here return 0 to make next valid same argument work */
4725 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4726 "power of 2 and equal or less than 16 !, Now it is "
4727 "kept the value = %hu", num, pf->vf_nb_qp_max);
4732 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4734 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4735 struct rte_kvargs *kvlist;
4738 /* set default queue number per VF as 4 */
4739 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4741 if (dev->device->devargs == NULL)
4744 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4748 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4749 if (!kvargs_count) {
4750 rte_kvargs_free(kvlist);
4754 if (kvargs_count > 1)
4755 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4756 "the first invalid or last valid one is used !",
4757 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4759 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4760 i40e_pf_parse_vf_queue_number_handler, pf);
4762 rte_kvargs_free(kvlist);
4768 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4771 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4772 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4773 uint16_t qp_count = 0, vsi_count = 0;
4775 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4776 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4780 i40e_pf_config_vf_rxq_number(dev);
4782 /* Add the parameter init for LFC */
4783 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4784 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4785 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4787 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4788 pf->max_num_vsi = hw->func_caps.num_vsis;
4789 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4790 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4792 /* FDir queue/VSI allocation */
4793 pf->fdir_qp_offset = 0;
4794 if (hw->func_caps.fd) {
4795 pf->flags |= I40E_FLAG_FDIR;
4796 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4798 pf->fdir_nb_qps = 0;
4800 qp_count += pf->fdir_nb_qps;
4803 /* LAN queue/VSI allocation */
4804 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4805 if (!hw->func_caps.rss) {
4808 pf->flags |= I40E_FLAG_RSS;
4809 if (hw->mac.type == I40E_MAC_X722)
4810 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4811 pf->lan_nb_qps = pf->lan_nb_qp_max;
4813 qp_count += pf->lan_nb_qps;
4816 /* VF queue/VSI allocation */
4817 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4818 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4819 pf->flags |= I40E_FLAG_SRIOV;
4820 pf->vf_nb_qps = pf->vf_nb_qp_max;
4821 pf->vf_num = pci_dev->max_vfs;
4823 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4824 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4829 qp_count += pf->vf_nb_qps * pf->vf_num;
4830 vsi_count += pf->vf_num;
4832 /* VMDq queue/VSI allocation */
4833 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4834 pf->vmdq_nb_qps = 0;
4835 pf->max_nb_vmdq_vsi = 0;
4836 if (hw->func_caps.vmdq) {
4837 if (qp_count < hw->func_caps.num_tx_qp &&
4838 vsi_count < hw->func_caps.num_vsis) {
4839 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4840 qp_count) / pf->vmdq_nb_qp_max;
4842 /* Limit the maximum number of VMDq vsi to the maximum
4843 * ethdev can support
4845 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4846 hw->func_caps.num_vsis - vsi_count);
4847 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4849 if (pf->max_nb_vmdq_vsi) {
4850 pf->flags |= I40E_FLAG_VMDQ;
4851 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4853 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4854 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4855 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4858 "No enough queues left for VMDq");
4861 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4864 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4865 vsi_count += pf->max_nb_vmdq_vsi;
4867 if (hw->func_caps.dcb)
4868 pf->flags |= I40E_FLAG_DCB;
4870 if (qp_count > hw->func_caps.num_tx_qp) {
4872 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4873 qp_count, hw->func_caps.num_tx_qp);
4876 if (vsi_count > hw->func_caps.num_vsis) {
4878 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4879 vsi_count, hw->func_caps.num_vsis);
4887 i40e_pf_get_switch_config(struct i40e_pf *pf)
4889 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4890 struct i40e_aqc_get_switch_config_resp *switch_config;
4891 struct i40e_aqc_switch_config_element_resp *element;
4892 uint16_t start_seid = 0, num_reported;
4895 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4896 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4897 if (!switch_config) {
4898 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4902 /* Get the switch configurations */
4903 ret = i40e_aq_get_switch_config(hw, switch_config,
4904 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4905 if (ret != I40E_SUCCESS) {
4906 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4909 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4910 if (num_reported != 1) { /* The number should be 1 */
4911 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4915 /* Parse the switch configuration elements */
4916 element = &(switch_config->element[0]);
4917 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4918 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4919 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4921 PMD_DRV_LOG(INFO, "Unknown element type");
4924 rte_free(switch_config);
4930 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4933 struct pool_entry *entry;
4935 if (pool == NULL || num == 0)
4938 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4939 if (entry == NULL) {
4940 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4944 /* queue heap initialize */
4945 pool->num_free = num;
4946 pool->num_alloc = 0;
4948 LIST_INIT(&pool->alloc_list);
4949 LIST_INIT(&pool->free_list);
4951 /* Initialize element */
4955 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4960 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4962 struct pool_entry *entry, *next_entry;
4967 for (entry = LIST_FIRST(&pool->alloc_list);
4968 entry && (next_entry = LIST_NEXT(entry, next), 1);
4969 entry = next_entry) {
4970 LIST_REMOVE(entry, next);
4974 for (entry = LIST_FIRST(&pool->free_list);
4975 entry && (next_entry = LIST_NEXT(entry, next), 1);
4976 entry = next_entry) {
4977 LIST_REMOVE(entry, next);
4982 pool->num_alloc = 0;
4984 LIST_INIT(&pool->alloc_list);
4985 LIST_INIT(&pool->free_list);
4989 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4992 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4993 uint32_t pool_offset;
4998 PMD_DRV_LOG(ERR, "Invalid parameter");
5002 pool_offset = base - pool->base;
5003 /* Lookup in alloc list */
5004 LIST_FOREACH(entry, &pool->alloc_list, next) {
5005 if (entry->base == pool_offset) {
5006 valid_entry = entry;
5007 LIST_REMOVE(entry, next);
5012 /* Not find, return */
5013 if (valid_entry == NULL) {
5014 PMD_DRV_LOG(ERR, "Failed to find entry");
5019 * Found it, move it to free list and try to merge.
5020 * In order to make merge easier, always sort it by qbase.
5021 * Find adjacent prev and last entries.
5024 LIST_FOREACH(entry, &pool->free_list, next) {
5025 if (entry->base > valid_entry->base) {
5033 len = valid_entry->len;
5034 /* Try to merge with next one*/
5036 /* Merge with next one */
5037 if (valid_entry->base + len == next->base) {
5038 next->base = valid_entry->base;
5040 rte_free(valid_entry);
5047 /* Merge with previous one */
5048 if (prev->base + prev->len == valid_entry->base) {
5050 /* If it merge with next one, remove next node */
5052 LIST_REMOVE(valid_entry, next);
5053 rte_free(valid_entry);
5056 rte_free(valid_entry);
5063 /* Not find any entry to merge, insert */
5066 LIST_INSERT_AFTER(prev, valid_entry, next);
5067 else if (next != NULL)
5068 LIST_INSERT_BEFORE(next, valid_entry, next);
5069 else /* It's empty list, insert to head */
5070 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5073 pool->num_free += len;
5074 pool->num_alloc -= len;
5080 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5083 struct pool_entry *entry, *valid_entry;
5085 if (pool == NULL || num == 0) {
5086 PMD_DRV_LOG(ERR, "Invalid parameter");
5090 if (pool->num_free < num) {
5091 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5092 num, pool->num_free);
5097 /* Lookup in free list and find most fit one */
5098 LIST_FOREACH(entry, &pool->free_list, next) {
5099 if (entry->len >= num) {
5101 if (entry->len == num) {
5102 valid_entry = entry;
5105 if (valid_entry == NULL || valid_entry->len > entry->len)
5106 valid_entry = entry;
5110 /* Not find one to satisfy the request, return */
5111 if (valid_entry == NULL) {
5112 PMD_DRV_LOG(ERR, "No valid entry found");
5116 * The entry have equal queue number as requested,
5117 * remove it from alloc_list.
5119 if (valid_entry->len == num) {
5120 LIST_REMOVE(valid_entry, next);
5123 * The entry have more numbers than requested,
5124 * create a new entry for alloc_list and minus its
5125 * queue base and number in free_list.
5127 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5128 if (entry == NULL) {
5130 "Failed to allocate memory for resource pool");
5133 entry->base = valid_entry->base;
5135 valid_entry->base += num;
5136 valid_entry->len -= num;
5137 valid_entry = entry;
5140 /* Insert it into alloc list, not sorted */
5141 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5143 pool->num_free -= valid_entry->len;
5144 pool->num_alloc += valid_entry->len;
5146 return valid_entry->base + pool->base;
5150 * bitmap_is_subset - Check whether src2 is subset of src1
5153 bitmap_is_subset(uint8_t src1, uint8_t src2)
5155 return !((src1 ^ src2) & src2);
5158 static enum i40e_status_code
5159 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5161 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5163 /* If DCB is not supported, only default TC is supported */
5164 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5165 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5166 return I40E_NOT_SUPPORTED;
5169 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5171 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5172 hw->func_caps.enabled_tcmap, enabled_tcmap);
5173 return I40E_NOT_SUPPORTED;
5175 return I40E_SUCCESS;
5179 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5180 struct i40e_vsi_vlan_pvid_info *info)
5183 struct i40e_vsi_context ctxt;
5184 uint8_t vlan_flags = 0;
5187 if (vsi == NULL || info == NULL) {
5188 PMD_DRV_LOG(ERR, "invalid parameters");
5189 return I40E_ERR_PARAM;
5193 vsi->info.pvid = info->config.pvid;
5195 * If insert pvid is enabled, only tagged pkts are
5196 * allowed to be sent out.
5198 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5199 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5202 if (info->config.reject.tagged == 0)
5203 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5205 if (info->config.reject.untagged == 0)
5206 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5208 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5209 I40E_AQ_VSI_PVLAN_MODE_MASK);
5210 vsi->info.port_vlan_flags |= vlan_flags;
5211 vsi->info.valid_sections =
5212 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5213 memset(&ctxt, 0, sizeof(ctxt));
5214 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5215 ctxt.seid = vsi->seid;
5217 hw = I40E_VSI_TO_HW(vsi);
5218 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5219 if (ret != I40E_SUCCESS)
5220 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5226 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5228 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5230 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5232 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5233 if (ret != I40E_SUCCESS)
5237 PMD_DRV_LOG(ERR, "seid not valid");
5241 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5242 tc_bw_data.tc_valid_bits = enabled_tcmap;
5243 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5244 tc_bw_data.tc_bw_credits[i] =
5245 (enabled_tcmap & (1 << i)) ? 1 : 0;
5247 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5248 if (ret != I40E_SUCCESS) {
5249 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5253 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5254 sizeof(vsi->info.qs_handle));
5255 return I40E_SUCCESS;
5258 static enum i40e_status_code
5259 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5260 struct i40e_aqc_vsi_properties_data *info,
5261 uint8_t enabled_tcmap)
5263 enum i40e_status_code ret;
5264 int i, total_tc = 0;
5265 uint16_t qpnum_per_tc, bsf, qp_idx;
5267 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5268 if (ret != I40E_SUCCESS)
5271 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5272 if (enabled_tcmap & (1 << i))
5276 vsi->enabled_tc = enabled_tcmap;
5278 /* Number of queues per enabled TC */
5279 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5280 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5281 bsf = rte_bsf32(qpnum_per_tc);
5283 /* Adjust the queue number to actual queues that can be applied */
5284 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5285 vsi->nb_qps = qpnum_per_tc * total_tc;
5288 * Configure TC and queue mapping parameters, for enabled TC,
5289 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5290 * default queue will serve it.
5293 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5294 if (vsi->enabled_tc & (1 << i)) {
5295 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5296 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5297 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5298 qp_idx += qpnum_per_tc;
5300 info->tc_mapping[i] = 0;
5303 /* Associate queue number with VSI */
5304 if (vsi->type == I40E_VSI_SRIOV) {
5305 info->mapping_flags |=
5306 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5307 for (i = 0; i < vsi->nb_qps; i++)
5308 info->queue_mapping[i] =
5309 rte_cpu_to_le_16(vsi->base_queue + i);
5311 info->mapping_flags |=
5312 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5313 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5315 info->valid_sections |=
5316 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5318 return I40E_SUCCESS;
5322 i40e_veb_release(struct i40e_veb *veb)
5324 struct i40e_vsi *vsi;
5330 if (!TAILQ_EMPTY(&veb->head)) {
5331 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5334 /* associate_vsi field is NULL for floating VEB */
5335 if (veb->associate_vsi != NULL) {
5336 vsi = veb->associate_vsi;
5337 hw = I40E_VSI_TO_HW(vsi);
5339 vsi->uplink_seid = veb->uplink_seid;
5342 veb->associate_pf->main_vsi->floating_veb = NULL;
5343 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5346 i40e_aq_delete_element(hw, veb->seid, NULL);
5348 return I40E_SUCCESS;
5352 static struct i40e_veb *
5353 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5355 struct i40e_veb *veb;
5361 "veb setup failed, associated PF shouldn't null");
5364 hw = I40E_PF_TO_HW(pf);
5366 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5368 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5372 veb->associate_vsi = vsi;
5373 veb->associate_pf = pf;
5374 TAILQ_INIT(&veb->head);
5375 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5377 /* create floating veb if vsi is NULL */
5379 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5380 I40E_DEFAULT_TCMAP, false,
5381 &veb->seid, false, NULL);
5383 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5384 true, &veb->seid, false, NULL);
5387 if (ret != I40E_SUCCESS) {
5388 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5389 hw->aq.asq_last_status);
5392 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5394 /* get statistics index */
5395 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5396 &veb->stats_idx, NULL, NULL, NULL);
5397 if (ret != I40E_SUCCESS) {
5398 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5399 hw->aq.asq_last_status);
5402 /* Get VEB bandwidth, to be implemented */
5403 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5405 vsi->uplink_seid = veb->seid;
5414 i40e_vsi_release(struct i40e_vsi *vsi)
5418 struct i40e_vsi_list *vsi_list;
5421 struct i40e_mac_filter *f;
5422 uint16_t user_param;
5425 return I40E_SUCCESS;
5430 user_param = vsi->user_param;
5432 pf = I40E_VSI_TO_PF(vsi);
5433 hw = I40E_VSI_TO_HW(vsi);
5435 /* VSI has child to attach, release child first */
5437 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5438 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5441 i40e_veb_release(vsi->veb);
5444 if (vsi->floating_veb) {
5445 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5446 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5451 /* Remove all macvlan filters of the VSI */
5452 i40e_vsi_remove_all_macvlan_filter(vsi);
5453 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5456 if (vsi->type != I40E_VSI_MAIN &&
5457 ((vsi->type != I40E_VSI_SRIOV) ||
5458 !pf->floating_veb_list[user_param])) {
5459 /* Remove vsi from parent's sibling list */
5460 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5461 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5462 return I40E_ERR_PARAM;
5464 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5465 &vsi->sib_vsi_list, list);
5467 /* Remove all switch element of the VSI */
5468 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5469 if (ret != I40E_SUCCESS)
5470 PMD_DRV_LOG(ERR, "Failed to delete element");
5473 if ((vsi->type == I40E_VSI_SRIOV) &&
5474 pf->floating_veb_list[user_param]) {
5475 /* Remove vsi from parent's sibling list */
5476 if (vsi->parent_vsi == NULL ||
5477 vsi->parent_vsi->floating_veb == NULL) {
5478 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5479 return I40E_ERR_PARAM;
5481 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5482 &vsi->sib_vsi_list, list);
5484 /* Remove all switch element of the VSI */
5485 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5486 if (ret != I40E_SUCCESS)
5487 PMD_DRV_LOG(ERR, "Failed to delete element");
5490 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5492 if (vsi->type != I40E_VSI_SRIOV)
5493 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5496 return I40E_SUCCESS;
5500 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5502 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5503 struct i40e_aqc_remove_macvlan_element_data def_filter;
5504 struct i40e_mac_filter_info filter;
5507 if (vsi->type != I40E_VSI_MAIN)
5508 return I40E_ERR_CONFIG;
5509 memset(&def_filter, 0, sizeof(def_filter));
5510 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5512 def_filter.vlan_tag = 0;
5513 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5514 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5515 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5516 if (ret != I40E_SUCCESS) {
5517 struct i40e_mac_filter *f;
5518 struct rte_ether_addr *mac;
5521 "Cannot remove the default macvlan filter");
5522 /* It needs to add the permanent mac into mac list */
5523 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5525 PMD_DRV_LOG(ERR, "failed to allocate memory");
5526 return I40E_ERR_NO_MEMORY;
5528 mac = &f->mac_info.mac_addr;
5529 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5531 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5532 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5537 rte_memcpy(&filter.mac_addr,
5538 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5539 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5540 return i40e_vsi_add_mac(vsi, &filter);
5544 * i40e_vsi_get_bw_config - Query VSI BW Information
5545 * @vsi: the VSI to be queried
5547 * Returns 0 on success, negative value on failure
5549 static enum i40e_status_code
5550 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5552 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5553 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5554 struct i40e_hw *hw = &vsi->adapter->hw;
5559 memset(&bw_config, 0, sizeof(bw_config));
5560 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5561 if (ret != I40E_SUCCESS) {
5562 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5563 hw->aq.asq_last_status);
5567 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5568 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5569 &ets_sla_config, NULL);
5570 if (ret != I40E_SUCCESS) {
5572 "VSI failed to get TC bandwdith configuration %u",
5573 hw->aq.asq_last_status);
5577 /* store and print out BW info */
5578 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5579 vsi->bw_info.bw_max = bw_config.max_bw;
5580 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5581 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5582 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5583 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5585 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5586 vsi->bw_info.bw_ets_share_credits[i] =
5587 ets_sla_config.share_credits[i];
5588 vsi->bw_info.bw_ets_credits[i] =
5589 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5590 /* 4 bits per TC, 4th bit is reserved */
5591 vsi->bw_info.bw_ets_max[i] =
5592 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5593 RTE_LEN2MASK(3, uint8_t));
5594 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5595 vsi->bw_info.bw_ets_share_credits[i]);
5596 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5597 vsi->bw_info.bw_ets_credits[i]);
5598 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5599 vsi->bw_info.bw_ets_max[i]);
5602 return I40E_SUCCESS;
5605 /* i40e_enable_pf_lb
5606 * @pf: pointer to the pf structure
5608 * allow loopback on pf
5611 i40e_enable_pf_lb(struct i40e_pf *pf)
5613 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5614 struct i40e_vsi_context ctxt;
5617 /* Use the FW API if FW >= v5.0 */
5618 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5619 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5623 memset(&ctxt, 0, sizeof(ctxt));
5624 ctxt.seid = pf->main_vsi_seid;
5625 ctxt.pf_num = hw->pf_id;
5626 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5628 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5629 ret, hw->aq.asq_last_status);
5632 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5633 ctxt.info.valid_sections =
5634 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5635 ctxt.info.switch_id |=
5636 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5638 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5640 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5641 hw->aq.asq_last_status);
5646 i40e_vsi_setup(struct i40e_pf *pf,
5647 enum i40e_vsi_type type,
5648 struct i40e_vsi *uplink_vsi,
5649 uint16_t user_param)
5651 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5652 struct i40e_vsi *vsi;
5653 struct i40e_mac_filter_info filter;
5655 struct i40e_vsi_context ctxt;
5656 struct rte_ether_addr broadcast =
5657 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5659 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5660 uplink_vsi == NULL) {
5662 "VSI setup failed, VSI link shouldn't be NULL");
5666 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5668 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5673 * 1.type is not MAIN and uplink vsi is not NULL
5674 * If uplink vsi didn't setup VEB, create one first under veb field
5675 * 2.type is SRIOV and the uplink is NULL
5676 * If floating VEB is NULL, create one veb under floating veb field
5679 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5680 uplink_vsi->veb == NULL) {
5681 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5683 if (uplink_vsi->veb == NULL) {
5684 PMD_DRV_LOG(ERR, "VEB setup failed");
5687 /* set ALLOWLOOPBACk on pf, when veb is created */
5688 i40e_enable_pf_lb(pf);
5691 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5692 pf->main_vsi->floating_veb == NULL) {
5693 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5695 if (pf->main_vsi->floating_veb == NULL) {
5696 PMD_DRV_LOG(ERR, "VEB setup failed");
5701 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5703 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5706 TAILQ_INIT(&vsi->mac_list);
5708 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5709 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5710 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5711 vsi->user_param = user_param;
5712 vsi->vlan_anti_spoof_on = 0;
5713 vsi->vlan_filter_on = 0;
5714 /* Allocate queues */
5715 switch (vsi->type) {
5716 case I40E_VSI_MAIN :
5717 vsi->nb_qps = pf->lan_nb_qps;
5719 case I40E_VSI_SRIOV :
5720 vsi->nb_qps = pf->vf_nb_qps;
5722 case I40E_VSI_VMDQ2:
5723 vsi->nb_qps = pf->vmdq_nb_qps;
5726 vsi->nb_qps = pf->fdir_nb_qps;
5732 * The filter status descriptor is reported in rx queue 0,
5733 * while the tx queue for fdir filter programming has no
5734 * such constraints, can be non-zero queues.
5735 * To simplify it, choose FDIR vsi use queue 0 pair.
5736 * To make sure it will use queue 0 pair, queue allocation
5737 * need be done before this function is called
5739 if (type != I40E_VSI_FDIR) {
5740 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5742 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5746 vsi->base_queue = ret;
5748 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5750 /* VF has MSIX interrupt in VF range, don't allocate here */
5751 if (type == I40E_VSI_MAIN) {
5752 if (pf->support_multi_driver) {
5753 /* If support multi-driver, need to use INT0 instead of
5754 * allocating from msix pool. The Msix pool is init from
5755 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5756 * to 1 without calling i40e_res_pool_alloc.
5761 ret = i40e_res_pool_alloc(&pf->msix_pool,
5762 RTE_MIN(vsi->nb_qps,
5763 RTE_MAX_RXTX_INTR_VEC_ID));
5766 "VSI MAIN %d get heap failed %d",
5768 goto fail_queue_alloc;
5770 vsi->msix_intr = ret;
5771 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5772 RTE_MAX_RXTX_INTR_VEC_ID);
5774 } else if (type != I40E_VSI_SRIOV) {
5775 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5777 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5778 if (type != I40E_VSI_FDIR)
5779 goto fail_queue_alloc;
5783 vsi->msix_intr = ret;
5792 if (type == I40E_VSI_MAIN) {
5793 /* For main VSI, no need to add since it's default one */
5794 vsi->uplink_seid = pf->mac_seid;
5795 vsi->seid = pf->main_vsi_seid;
5796 /* Bind queues with specific MSIX interrupt */
5798 * Needs 2 interrupt at least, one for misc cause which will
5799 * enabled from OS side, Another for queues binding the
5800 * interrupt from device side only.
5803 /* Get default VSI parameters from hardware */
5804 memset(&ctxt, 0, sizeof(ctxt));
5805 ctxt.seid = vsi->seid;
5806 ctxt.pf_num = hw->pf_id;
5807 ctxt.uplink_seid = vsi->uplink_seid;
5809 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5810 if (ret != I40E_SUCCESS) {
5811 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5812 goto fail_msix_alloc;
5814 rte_memcpy(&vsi->info, &ctxt.info,
5815 sizeof(struct i40e_aqc_vsi_properties_data));
5816 vsi->vsi_id = ctxt.vsi_number;
5817 vsi->info.valid_sections = 0;
5819 /* Configure tc, enabled TC0 only */
5820 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5822 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5823 goto fail_msix_alloc;
5826 /* TC, queue mapping */
5827 memset(&ctxt, 0, sizeof(ctxt));
5828 vsi->info.valid_sections |=
5829 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5830 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5831 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5832 rte_memcpy(&ctxt.info, &vsi->info,
5833 sizeof(struct i40e_aqc_vsi_properties_data));
5834 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5835 I40E_DEFAULT_TCMAP);
5836 if (ret != I40E_SUCCESS) {
5838 "Failed to configure TC queue mapping");
5839 goto fail_msix_alloc;
5841 ctxt.seid = vsi->seid;
5842 ctxt.pf_num = hw->pf_id;
5843 ctxt.uplink_seid = vsi->uplink_seid;
5846 /* Update VSI parameters */
5847 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5848 if (ret != I40E_SUCCESS) {
5849 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5850 goto fail_msix_alloc;
5853 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5854 sizeof(vsi->info.tc_mapping));
5855 rte_memcpy(&vsi->info.queue_mapping,
5856 &ctxt.info.queue_mapping,
5857 sizeof(vsi->info.queue_mapping));
5858 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5859 vsi->info.valid_sections = 0;
5861 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5865 * Updating default filter settings are necessary to prevent
5866 * reception of tagged packets.
5867 * Some old firmware configurations load a default macvlan
5868 * filter which accepts both tagged and untagged packets.
5869 * The updating is to use a normal filter instead if needed.
5870 * For NVM 4.2.2 or after, the updating is not needed anymore.
5871 * The firmware with correct configurations load the default
5872 * macvlan filter which is expected and cannot be removed.
5874 i40e_update_default_filter_setting(vsi);
5875 i40e_config_qinq(hw, vsi);
5876 } else if (type == I40E_VSI_SRIOV) {
5877 memset(&ctxt, 0, sizeof(ctxt));
5879 * For other VSI, the uplink_seid equals to uplink VSI's
5880 * uplink_seid since they share same VEB
5882 if (uplink_vsi == NULL)
5883 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5885 vsi->uplink_seid = uplink_vsi->uplink_seid;
5886 ctxt.pf_num = hw->pf_id;
5887 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5888 ctxt.uplink_seid = vsi->uplink_seid;
5889 ctxt.connection_type = 0x1;
5890 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5892 /* Use the VEB configuration if FW >= v5.0 */
5893 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5894 /* Configure switch ID */
5895 ctxt.info.valid_sections |=
5896 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5897 ctxt.info.switch_id =
5898 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5901 /* Configure port/vlan */
5902 ctxt.info.valid_sections |=
5903 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5904 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5905 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5906 hw->func_caps.enabled_tcmap);
5907 if (ret != I40E_SUCCESS) {
5909 "Failed to configure TC queue mapping");
5910 goto fail_msix_alloc;
5913 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5914 ctxt.info.valid_sections |=
5915 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5917 * Since VSI is not created yet, only configure parameter,
5918 * will add vsi below.
5921 i40e_config_qinq(hw, vsi);
5922 } else if (type == I40E_VSI_VMDQ2) {
5923 memset(&ctxt, 0, sizeof(ctxt));
5925 * For other VSI, the uplink_seid equals to uplink VSI's
5926 * uplink_seid since they share same VEB
5928 vsi->uplink_seid = uplink_vsi->uplink_seid;
5929 ctxt.pf_num = hw->pf_id;
5931 ctxt.uplink_seid = vsi->uplink_seid;
5932 ctxt.connection_type = 0x1;
5933 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5935 ctxt.info.valid_sections |=
5936 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5937 /* user_param carries flag to enable loop back */
5939 ctxt.info.switch_id =
5940 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5941 ctxt.info.switch_id |=
5942 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5945 /* Configure port/vlan */
5946 ctxt.info.valid_sections |=
5947 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5948 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5949 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5950 I40E_DEFAULT_TCMAP);
5951 if (ret != I40E_SUCCESS) {
5953 "Failed to configure TC queue mapping");
5954 goto fail_msix_alloc;
5956 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5957 ctxt.info.valid_sections |=
5958 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5959 } else if (type == I40E_VSI_FDIR) {
5960 memset(&ctxt, 0, sizeof(ctxt));
5961 vsi->uplink_seid = uplink_vsi->uplink_seid;
5962 ctxt.pf_num = hw->pf_id;
5964 ctxt.uplink_seid = vsi->uplink_seid;
5965 ctxt.connection_type = 0x1; /* regular data port */
5966 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5967 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5968 I40E_DEFAULT_TCMAP);
5969 if (ret != I40E_SUCCESS) {
5971 "Failed to configure TC queue mapping.");
5972 goto fail_msix_alloc;
5974 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5975 ctxt.info.valid_sections |=
5976 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5978 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5979 goto fail_msix_alloc;
5982 if (vsi->type != I40E_VSI_MAIN) {
5983 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5984 if (ret != I40E_SUCCESS) {
5985 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5986 hw->aq.asq_last_status);
5987 goto fail_msix_alloc;
5989 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5990 vsi->info.valid_sections = 0;
5991 vsi->seid = ctxt.seid;
5992 vsi->vsi_id = ctxt.vsi_number;
5993 vsi->sib_vsi_list.vsi = vsi;
5994 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5995 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5996 &vsi->sib_vsi_list, list);
5998 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5999 &vsi->sib_vsi_list, list);
6003 /* MAC/VLAN configuration */
6004 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6005 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
6007 ret = i40e_vsi_add_mac(vsi, &filter);
6008 if (ret != I40E_SUCCESS) {
6009 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6010 goto fail_msix_alloc;
6013 /* Get VSI BW information */
6014 i40e_vsi_get_bw_config(vsi);
6017 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6019 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6025 /* Configure vlan filter on or off */
6027 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6030 struct i40e_mac_filter *f;
6032 struct i40e_mac_filter_info *mac_filter;
6033 enum i40e_mac_filter_type desired_filter;
6034 int ret = I40E_SUCCESS;
6037 /* Filter to match MAC and VLAN */
6038 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6040 /* Filter to match only MAC */
6041 desired_filter = I40E_MAC_PERFECT_MATCH;
6046 mac_filter = rte_zmalloc("mac_filter_info_data",
6047 num * sizeof(*mac_filter), 0);
6048 if (mac_filter == NULL) {
6049 PMD_DRV_LOG(ERR, "failed to allocate memory");
6050 return I40E_ERR_NO_MEMORY;
6055 /* Remove all existing mac */
6056 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6057 mac_filter[i] = f->mac_info;
6058 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6060 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6061 on ? "enable" : "disable");
6067 /* Override with new filter */
6068 for (i = 0; i < num; i++) {
6069 mac_filter[i].filter_type = desired_filter;
6070 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6072 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6073 on ? "enable" : "disable");
6079 rte_free(mac_filter);
6083 /* Configure vlan stripping on or off */
6085 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6087 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6088 struct i40e_vsi_context ctxt;
6090 int ret = I40E_SUCCESS;
6092 /* Check if it has been already on or off */
6093 if (vsi->info.valid_sections &
6094 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6096 if ((vsi->info.port_vlan_flags &
6097 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6098 return 0; /* already on */
6100 if ((vsi->info.port_vlan_flags &
6101 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6102 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6103 return 0; /* already off */
6108 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6110 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6111 vsi->info.valid_sections =
6112 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6113 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6114 vsi->info.port_vlan_flags |= vlan_flags;
6115 ctxt.seid = vsi->seid;
6116 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6117 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6119 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6120 on ? "enable" : "disable");
6126 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6128 struct rte_eth_dev_data *data = dev->data;
6132 /* Apply vlan offload setting */
6133 mask = ETH_VLAN_STRIP_MASK |
6134 ETH_QINQ_STRIP_MASK |
6135 ETH_VLAN_FILTER_MASK |
6136 ETH_VLAN_EXTEND_MASK;
6137 ret = i40e_vlan_offload_set(dev, mask);
6139 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6143 /* Apply pvid setting */
6144 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6145 data->dev_conf.txmode.hw_vlan_insert_pvid);
6147 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6153 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6155 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6157 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6161 i40e_update_flow_control(struct i40e_hw *hw)
6163 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6164 struct i40e_link_status link_status;
6165 uint32_t rxfc = 0, txfc = 0, reg;
6169 memset(&link_status, 0, sizeof(link_status));
6170 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6171 if (ret != I40E_SUCCESS) {
6172 PMD_DRV_LOG(ERR, "Failed to get link status information");
6173 goto write_reg; /* Disable flow control */
6176 an_info = hw->phy.link_info.an_info;
6177 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6178 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6179 ret = I40E_ERR_NOT_READY;
6180 goto write_reg; /* Disable flow control */
6183 * If link auto negotiation is enabled, flow control needs to
6184 * be configured according to it
6186 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6187 case I40E_LINK_PAUSE_RXTX:
6190 hw->fc.current_mode = I40E_FC_FULL;
6192 case I40E_AQ_LINK_PAUSE_RX:
6194 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6196 case I40E_AQ_LINK_PAUSE_TX:
6198 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6201 hw->fc.current_mode = I40E_FC_NONE;
6206 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6207 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6208 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6209 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6210 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6211 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6218 i40e_pf_setup(struct i40e_pf *pf)
6220 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6221 struct i40e_filter_control_settings settings;
6222 struct i40e_vsi *vsi;
6225 /* Clear all stats counters */
6226 pf->offset_loaded = FALSE;
6227 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6228 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6229 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6230 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6232 ret = i40e_pf_get_switch_config(pf);
6233 if (ret != I40E_SUCCESS) {
6234 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6238 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6240 PMD_INIT_LOG(WARNING,
6241 "failed to allocate switch domain for device %d", ret);
6243 if (pf->flags & I40E_FLAG_FDIR) {
6244 /* make queue allocated first, let FDIR use queue pair 0*/
6245 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6246 if (ret != I40E_FDIR_QUEUE_ID) {
6248 "queue allocation fails for FDIR: ret =%d",
6250 pf->flags &= ~I40E_FLAG_FDIR;
6253 /* main VSI setup */
6254 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6256 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6257 return I40E_ERR_NOT_READY;
6261 /* Configure filter control */
6262 memset(&settings, 0, sizeof(settings));
6263 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6264 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6265 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6266 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6268 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6269 hw->func_caps.rss_table_size);
6270 return I40E_ERR_PARAM;
6272 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6273 hw->func_caps.rss_table_size);
6274 pf->hash_lut_size = hw->func_caps.rss_table_size;
6276 /* Enable ethtype and macvlan filters */
6277 settings.enable_ethtype = TRUE;
6278 settings.enable_macvlan = TRUE;
6279 ret = i40e_set_filter_control(hw, &settings);
6281 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6284 /* Update flow control according to the auto negotiation */
6285 i40e_update_flow_control(hw);
6287 return I40E_SUCCESS;
6291 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6297 * Set or clear TX Queue Disable flags,
6298 * which is required by hardware.
6300 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6301 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6303 /* Wait until the request is finished */
6304 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6305 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6306 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6307 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6308 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6314 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6315 return I40E_SUCCESS; /* already on, skip next steps */
6317 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6318 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6320 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6321 return I40E_SUCCESS; /* already off, skip next steps */
6322 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6324 /* Write the register */
6325 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6326 /* Check the result */
6327 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6328 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6329 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6331 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6332 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6335 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6336 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6340 /* Check if it is timeout */
6341 if (j >= I40E_CHK_Q_ENA_COUNT) {
6342 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6343 (on ? "enable" : "disable"), q_idx);
6344 return I40E_ERR_TIMEOUT;
6347 return I40E_SUCCESS;
6351 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6356 /* Wait until the request is finished */
6357 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6358 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6359 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6360 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6361 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6366 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6367 return I40E_SUCCESS; /* Already on, skip next steps */
6368 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6370 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6371 return I40E_SUCCESS; /* Already off, skip next steps */
6372 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6375 /* Write the register */
6376 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6377 /* Check the result */
6378 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6379 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6380 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6382 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6383 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6386 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6387 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6392 /* Check if it is timeout */
6393 if (j >= I40E_CHK_Q_ENA_COUNT) {
6394 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6395 (on ? "enable" : "disable"), q_idx);
6396 return I40E_ERR_TIMEOUT;
6399 return I40E_SUCCESS;
6402 /* Initialize VSI for TX */
6404 i40e_dev_tx_init(struct i40e_pf *pf)
6406 struct rte_eth_dev_data *data = pf->dev_data;
6408 uint32_t ret = I40E_SUCCESS;
6409 struct i40e_tx_queue *txq;
6411 for (i = 0; i < data->nb_tx_queues; i++) {
6412 txq = data->tx_queues[i];
6413 if (!txq || !txq->q_set)
6415 ret = i40e_tx_queue_init(txq);
6416 if (ret != I40E_SUCCESS)
6419 if (ret == I40E_SUCCESS)
6420 i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
6425 /* Initialize VSI for RX */
6427 i40e_dev_rx_init(struct i40e_pf *pf)
6429 struct rte_eth_dev_data *data = pf->dev_data;
6430 int ret = I40E_SUCCESS;
6432 struct i40e_rx_queue *rxq;
6434 i40e_pf_config_rss(pf);
6435 for (i = 0; i < data->nb_rx_queues; i++) {
6436 rxq = data->rx_queues[i];
6437 if (!rxq || !rxq->q_set)
6440 ret = i40e_rx_queue_init(rxq);
6441 if (ret != I40E_SUCCESS) {
6443 "Failed to do RX queue initialization");
6447 if (ret == I40E_SUCCESS)
6448 i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
6454 i40e_dev_rxtx_init(struct i40e_pf *pf)
6458 err = i40e_dev_tx_init(pf);
6460 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6463 err = i40e_dev_rx_init(pf);
6465 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6473 i40e_vmdq_setup(struct rte_eth_dev *dev)
6475 struct rte_eth_conf *conf = &dev->data->dev_conf;
6476 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6477 int i, err, conf_vsis, j, loop;
6478 struct i40e_vsi *vsi;
6479 struct i40e_vmdq_info *vmdq_info;
6480 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6481 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6484 * Disable interrupt to avoid message from VF. Furthermore, it will
6485 * avoid race condition in VSI creation/destroy.
6487 i40e_pf_disable_irq0(hw);
6489 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6490 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6494 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6495 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6496 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6497 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6498 pf->max_nb_vmdq_vsi);
6502 if (pf->vmdq != NULL) {
6503 PMD_INIT_LOG(INFO, "VMDQ already configured");
6507 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6508 sizeof(*vmdq_info) * conf_vsis, 0);
6510 if (pf->vmdq == NULL) {
6511 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6515 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6517 /* Create VMDQ VSI */
6518 for (i = 0; i < conf_vsis; i++) {
6519 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6520 vmdq_conf->enable_loop_back);
6522 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6526 vmdq_info = &pf->vmdq[i];
6528 vmdq_info->vsi = vsi;
6530 pf->nb_cfg_vmdq_vsi = conf_vsis;
6532 /* Configure Vlan */
6533 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6534 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6535 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6536 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6537 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6538 vmdq_conf->pool_map[i].vlan_id, j);
6540 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6541 vmdq_conf->pool_map[i].vlan_id);
6543 PMD_INIT_LOG(ERR, "Failed to add vlan");
6551 i40e_pf_enable_irq0(hw);
6556 for (i = 0; i < conf_vsis; i++)
6557 if (pf->vmdq[i].vsi == NULL)
6560 i40e_vsi_release(pf->vmdq[i].vsi);
6564 i40e_pf_enable_irq0(hw);
6569 i40e_stat_update_32(struct i40e_hw *hw,
6577 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6581 if (new_data >= *offset)
6582 *stat = (uint64_t)(new_data - *offset);
6584 *stat = (uint64_t)((new_data +
6585 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6589 i40e_stat_update_48(struct i40e_hw *hw,
6598 if (hw->device_id == I40E_DEV_ID_QEMU) {
6599 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6600 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6601 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6603 new_data = I40E_READ_REG64(hw, loreg);
6609 if (new_data >= *offset)
6610 *stat = new_data - *offset;
6612 *stat = (uint64_t)((new_data +
6613 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6615 *stat &= I40E_48_BIT_MASK;
6620 i40e_pf_disable_irq0(struct i40e_hw *hw)
6622 /* Disable all interrupt types */
6623 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6624 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6625 I40E_WRITE_FLUSH(hw);
6630 i40e_pf_enable_irq0(struct i40e_hw *hw)
6632 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6633 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6634 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6635 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6636 I40E_WRITE_FLUSH(hw);
6640 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6642 /* read pending request and disable first */
6643 i40e_pf_disable_irq0(hw);
6644 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6645 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6646 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6649 /* Link no queues with irq0 */
6650 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6651 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6655 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6658 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6661 uint32_t index, offset, val;
6666 * Try to find which VF trigger a reset, use absolute VF id to access
6667 * since the reg is global register.
6669 for (i = 0; i < pf->vf_num; i++) {
6670 abs_vf_id = hw->func_caps.vf_base_id + i;
6671 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6672 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6673 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6674 /* VFR event occurred */
6675 if (val & (0x1 << offset)) {
6678 /* Clear the event first */
6679 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6681 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6683 * Only notify a VF reset event occurred,
6684 * don't trigger another SW reset
6686 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6687 if (ret != I40E_SUCCESS)
6688 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6694 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6696 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6699 for (i = 0; i < pf->vf_num; i++)
6700 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6704 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6707 struct i40e_arq_event_info info;
6708 uint16_t pending, opcode;
6711 info.buf_len = I40E_AQ_BUF_SZ;
6712 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6713 if (!info.msg_buf) {
6714 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6720 ret = i40e_clean_arq_element(hw, &info, &pending);
6722 if (ret != I40E_SUCCESS) {
6724 "Failed to read msg from AdminQ, aq_err: %u",
6725 hw->aq.asq_last_status);
6728 opcode = rte_le_to_cpu_16(info.desc.opcode);
6731 case i40e_aqc_opc_send_msg_to_pf:
6732 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6733 i40e_pf_host_handle_vf_msg(dev,
6734 rte_le_to_cpu_16(info.desc.retval),
6735 rte_le_to_cpu_32(info.desc.cookie_high),
6736 rte_le_to_cpu_32(info.desc.cookie_low),
6740 case i40e_aqc_opc_get_link_status:
6741 ret = i40e_dev_link_update(dev, 0);
6743 rte_eth_dev_callback_process(dev,
6744 RTE_ETH_EVENT_INTR_LSC, NULL);
6747 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6752 rte_free(info.msg_buf);
6756 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6758 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6759 #define I40E_MDD_CLEAR16 0xFFFF
6760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6762 bool mdd_detected = false;
6763 struct i40e_pf_vf *vf;
6767 /* find what triggered the MDD event */
6768 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6769 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6770 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6771 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6772 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6773 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6774 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6775 I40E_GL_MDET_TX_EVENT_SHIFT;
6776 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6777 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6778 hw->func_caps.base_queue;
6779 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6780 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6781 event, queue, pf_num, vf_num, dev->data->name);
6782 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6783 mdd_detected = true;
6785 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6786 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6787 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6788 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6789 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6790 I40E_GL_MDET_RX_EVENT_SHIFT;
6791 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6792 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6793 hw->func_caps.base_queue;
6795 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6796 "queue %d of function 0x%02x device %s\n",
6797 event, queue, func, dev->data->name);
6798 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6799 mdd_detected = true;
6803 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6804 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6805 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6806 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6808 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6809 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6810 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6812 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6816 /* see if one of the VFs needs its hand slapped */
6817 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6819 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6820 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6821 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6823 vf->num_mdd_events++;
6824 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6826 i, vf->num_mdd_events);
6829 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6830 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6831 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6833 vf->num_mdd_events++;
6834 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6836 i, vf->num_mdd_events);
6842 * Interrupt handler triggered by NIC for handling
6843 * specific interrupt.
6846 * Pointer to interrupt handle.
6848 * The address of parameter (struct rte_eth_dev *) regsitered before.
6854 i40e_dev_interrupt_handler(void *param)
6856 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860 /* Disable interrupt */
6861 i40e_pf_disable_irq0(hw);
6863 /* read out interrupt causes */
6864 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6866 /* No interrupt event indicated */
6867 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6868 PMD_DRV_LOG(INFO, "No interrupt event");
6871 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6872 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6873 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6874 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6875 i40e_handle_mdd_event(dev);
6877 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6878 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6879 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6880 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6881 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6882 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6883 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6884 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6885 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6886 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6888 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6889 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6890 i40e_dev_handle_vfr_event(dev);
6892 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6893 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6894 i40e_dev_handle_aq_msg(dev);
6898 /* Enable interrupt */
6899 i40e_pf_enable_irq0(hw);
6903 i40e_dev_alarm_handler(void *param)
6905 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6906 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6909 /* Disable interrupt */
6910 i40e_pf_disable_irq0(hw);
6912 /* read out interrupt causes */
6913 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6915 /* No interrupt event indicated */
6916 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6918 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6919 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6920 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6921 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6922 i40e_handle_mdd_event(dev);
6924 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6925 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6926 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6927 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6928 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6929 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6930 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6931 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6932 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6933 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6935 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6936 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6937 i40e_dev_handle_vfr_event(dev);
6939 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6940 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6941 i40e_dev_handle_aq_msg(dev);
6945 /* Enable interrupt */
6946 i40e_pf_enable_irq0(hw);
6947 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6948 i40e_dev_alarm_handler, dev);
6952 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6953 struct i40e_macvlan_filter *filter,
6956 int ele_num, ele_buff_size;
6957 int num, actual_num, i;
6959 int ret = I40E_SUCCESS;
6960 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6961 struct i40e_aqc_add_macvlan_element_data *req_list;
6963 if (filter == NULL || total == 0)
6964 return I40E_ERR_PARAM;
6965 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6966 ele_buff_size = hw->aq.asq_buf_size;
6968 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6969 if (req_list == NULL) {
6970 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6971 return I40E_ERR_NO_MEMORY;
6976 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6977 memset(req_list, 0, ele_buff_size);
6979 for (i = 0; i < actual_num; i++) {
6980 rte_memcpy(req_list[i].mac_addr,
6981 &filter[num + i].macaddr, ETH_ADDR_LEN);
6982 req_list[i].vlan_tag =
6983 rte_cpu_to_le_16(filter[num + i].vlan_id);
6985 switch (filter[num + i].filter_type) {
6986 case I40E_MAC_PERFECT_MATCH:
6987 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6988 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6990 case I40E_MACVLAN_PERFECT_MATCH:
6991 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6993 case I40E_MAC_HASH_MATCH:
6994 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6995 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6997 case I40E_MACVLAN_HASH_MATCH:
6998 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7001 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7002 ret = I40E_ERR_PARAM;
7006 req_list[i].queue_number = 0;
7008 req_list[i].flags = rte_cpu_to_le_16(flags);
7011 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7013 if (ret != I40E_SUCCESS) {
7014 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7018 } while (num < total);
7026 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7027 struct i40e_macvlan_filter *filter,
7030 int ele_num, ele_buff_size;
7031 int num, actual_num, i;
7033 int ret = I40E_SUCCESS;
7034 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7035 struct i40e_aqc_remove_macvlan_element_data *req_list;
7037 if (filter == NULL || total == 0)
7038 return I40E_ERR_PARAM;
7040 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7041 ele_buff_size = hw->aq.asq_buf_size;
7043 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7044 if (req_list == NULL) {
7045 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7046 return I40E_ERR_NO_MEMORY;
7051 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7052 memset(req_list, 0, ele_buff_size);
7054 for (i = 0; i < actual_num; i++) {
7055 rte_memcpy(req_list[i].mac_addr,
7056 &filter[num + i].macaddr, ETH_ADDR_LEN);
7057 req_list[i].vlan_tag =
7058 rte_cpu_to_le_16(filter[num + i].vlan_id);
7060 switch (filter[num + i].filter_type) {
7061 case I40E_MAC_PERFECT_MATCH:
7062 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7063 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7065 case I40E_MACVLAN_PERFECT_MATCH:
7066 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7068 case I40E_MAC_HASH_MATCH:
7069 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7070 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7072 case I40E_MACVLAN_HASH_MATCH:
7073 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7076 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7077 ret = I40E_ERR_PARAM;
7080 req_list[i].flags = rte_cpu_to_le_16(flags);
7083 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7085 if (ret != I40E_SUCCESS) {
7086 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7090 } while (num < total);
7097 /* Find out specific MAC filter */
7098 static struct i40e_mac_filter *
7099 i40e_find_mac_filter(struct i40e_vsi *vsi,
7100 struct rte_ether_addr *macaddr)
7102 struct i40e_mac_filter *f;
7104 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7105 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7113 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7116 uint32_t vid_idx, vid_bit;
7118 if (vlan_id > ETH_VLAN_ID_MAX)
7121 vid_idx = I40E_VFTA_IDX(vlan_id);
7122 vid_bit = I40E_VFTA_BIT(vlan_id);
7124 if (vsi->vfta[vid_idx] & vid_bit)
7131 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7132 uint16_t vlan_id, bool on)
7134 uint32_t vid_idx, vid_bit;
7136 vid_idx = I40E_VFTA_IDX(vlan_id);
7137 vid_bit = I40E_VFTA_BIT(vlan_id);
7140 vsi->vfta[vid_idx] |= vid_bit;
7142 vsi->vfta[vid_idx] &= ~vid_bit;
7146 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7147 uint16_t vlan_id, bool on)
7149 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7150 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7153 if (vlan_id > ETH_VLAN_ID_MAX)
7156 i40e_store_vlan_filter(vsi, vlan_id, on);
7158 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7161 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7164 ret = i40e_aq_add_vlan(hw, vsi->seid,
7165 &vlan_data, 1, NULL);
7166 if (ret != I40E_SUCCESS)
7167 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7169 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7170 &vlan_data, 1, NULL);
7171 if (ret != I40E_SUCCESS)
7173 "Failed to remove vlan filter");
7178 * Find all vlan options for specific mac addr,
7179 * return with actual vlan found.
7182 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7183 struct i40e_macvlan_filter *mv_f,
7184 int num, struct rte_ether_addr *addr)
7190 * Not to use i40e_find_vlan_filter to decrease the loop time,
7191 * although the code looks complex.
7193 if (num < vsi->vlan_num)
7194 return I40E_ERR_PARAM;
7197 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7199 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7200 if (vsi->vfta[j] & (1 << k)) {
7203 "vlan number doesn't match");
7204 return I40E_ERR_PARAM;
7206 rte_memcpy(&mv_f[i].macaddr,
7207 addr, ETH_ADDR_LEN);
7209 j * I40E_UINT32_BIT_SIZE + k;
7215 return I40E_SUCCESS;
7219 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7220 struct i40e_macvlan_filter *mv_f,
7225 struct i40e_mac_filter *f;
7227 if (num < vsi->mac_num)
7228 return I40E_ERR_PARAM;
7230 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7232 PMD_DRV_LOG(ERR, "buffer number not match");
7233 return I40E_ERR_PARAM;
7235 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7237 mv_f[i].vlan_id = vlan;
7238 mv_f[i].filter_type = f->mac_info.filter_type;
7242 return I40E_SUCCESS;
7246 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7249 struct i40e_mac_filter *f;
7250 struct i40e_macvlan_filter *mv_f;
7251 int ret = I40E_SUCCESS;
7253 if (vsi == NULL || vsi->mac_num == 0)
7254 return I40E_ERR_PARAM;
7256 /* Case that no vlan is set */
7257 if (vsi->vlan_num == 0)
7260 num = vsi->mac_num * vsi->vlan_num;
7262 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7264 PMD_DRV_LOG(ERR, "failed to allocate memory");
7265 return I40E_ERR_NO_MEMORY;
7269 if (vsi->vlan_num == 0) {
7270 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7271 rte_memcpy(&mv_f[i].macaddr,
7272 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7273 mv_f[i].filter_type = f->mac_info.filter_type;
7274 mv_f[i].vlan_id = 0;
7278 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7279 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7280 vsi->vlan_num, &f->mac_info.mac_addr);
7281 if (ret != I40E_SUCCESS)
7283 for (j = i; j < i + vsi->vlan_num; j++)
7284 mv_f[j].filter_type = f->mac_info.filter_type;
7289 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7297 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7299 struct i40e_macvlan_filter *mv_f;
7301 int ret = I40E_SUCCESS;
7303 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7304 return I40E_ERR_PARAM;
7306 /* If it's already set, just return */
7307 if (i40e_find_vlan_filter(vsi,vlan))
7308 return I40E_SUCCESS;
7310 mac_num = vsi->mac_num;
7313 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7314 return I40E_ERR_PARAM;
7317 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7320 PMD_DRV_LOG(ERR, "failed to allocate memory");
7321 return I40E_ERR_NO_MEMORY;
7324 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7326 if (ret != I40E_SUCCESS)
7329 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7331 if (ret != I40E_SUCCESS)
7334 i40e_set_vlan_filter(vsi, vlan, 1);
7344 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7346 struct i40e_macvlan_filter *mv_f;
7348 int ret = I40E_SUCCESS;
7351 * Vlan 0 is the generic filter for untagged packets
7352 * and can't be removed.
7354 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7355 return I40E_ERR_PARAM;
7357 /* If can't find it, just return */
7358 if (!i40e_find_vlan_filter(vsi, vlan))
7359 return I40E_ERR_PARAM;
7361 mac_num = vsi->mac_num;
7364 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7365 return I40E_ERR_PARAM;
7368 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7371 PMD_DRV_LOG(ERR, "failed to allocate memory");
7372 return I40E_ERR_NO_MEMORY;
7375 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7377 if (ret != I40E_SUCCESS)
7380 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7382 if (ret != I40E_SUCCESS)
7385 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7386 if (vsi->vlan_num == 1) {
7387 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7388 if (ret != I40E_SUCCESS)
7391 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7392 if (ret != I40E_SUCCESS)
7396 i40e_set_vlan_filter(vsi, vlan, 0);
7406 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7408 struct i40e_mac_filter *f;
7409 struct i40e_macvlan_filter *mv_f;
7410 int i, vlan_num = 0;
7411 int ret = I40E_SUCCESS;
7413 /* If it's add and we've config it, return */
7414 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7416 return I40E_SUCCESS;
7417 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7418 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7421 * If vlan_num is 0, that's the first time to add mac,
7422 * set mask for vlan_id 0.
7424 if (vsi->vlan_num == 0) {
7425 i40e_set_vlan_filter(vsi, 0, 1);
7428 vlan_num = vsi->vlan_num;
7429 } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7430 mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7433 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7435 PMD_DRV_LOG(ERR, "failed to allocate memory");
7436 return I40E_ERR_NO_MEMORY;
7439 for (i = 0; i < vlan_num; i++) {
7440 mv_f[i].filter_type = mac_filter->filter_type;
7441 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7445 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7446 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7447 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7448 &mac_filter->mac_addr);
7449 if (ret != I40E_SUCCESS)
7453 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7454 if (ret != I40E_SUCCESS)
7457 /* Add the mac addr into mac list */
7458 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7460 PMD_DRV_LOG(ERR, "failed to allocate memory");
7461 ret = I40E_ERR_NO_MEMORY;
7464 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7466 f->mac_info.filter_type = mac_filter->filter_type;
7467 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7478 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7480 struct i40e_mac_filter *f;
7481 struct i40e_macvlan_filter *mv_f;
7483 enum i40e_mac_filter_type filter_type;
7484 int ret = I40E_SUCCESS;
7486 /* Can't find it, return an error */
7487 f = i40e_find_mac_filter(vsi, addr);
7489 return I40E_ERR_PARAM;
7491 vlan_num = vsi->vlan_num;
7492 filter_type = f->mac_info.filter_type;
7493 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7494 filter_type == I40E_MACVLAN_HASH_MATCH) {
7495 if (vlan_num == 0) {
7496 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7497 return I40E_ERR_PARAM;
7499 } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7500 filter_type == I40E_MAC_HASH_MATCH)
7503 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7505 PMD_DRV_LOG(ERR, "failed to allocate memory");
7506 return I40E_ERR_NO_MEMORY;
7509 for (i = 0; i < vlan_num; i++) {
7510 mv_f[i].filter_type = filter_type;
7511 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7514 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7515 filter_type == I40E_MACVLAN_HASH_MATCH) {
7516 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7517 if (ret != I40E_SUCCESS)
7521 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7522 if (ret != I40E_SUCCESS)
7525 /* Remove the mac addr into mac list */
7526 TAILQ_REMOVE(&vsi->mac_list, f, next);
7536 /* Configure hash enable flags for RSS */
7538 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7546 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7547 if (flags & (1ULL << i))
7548 hena |= adapter->pctypes_tbl[i];
7554 /* Parse the hash enable flags */
7556 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7558 uint64_t rss_hf = 0;
7564 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7565 if (flags & adapter->pctypes_tbl[i])
7566 rss_hf |= (1ULL << i);
7573 i40e_pf_disable_rss(struct i40e_pf *pf)
7575 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7577 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7578 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7579 I40E_WRITE_FLUSH(hw);
7583 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7585 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7586 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7587 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7588 I40E_VFQF_HKEY_MAX_INDEX :
7589 I40E_PFQF_HKEY_MAX_INDEX;
7591 if (!key || key_len == 0) {
7592 PMD_DRV_LOG(DEBUG, "No key to be configured");
7594 } else if (key_len != (key_idx + 1) *
7596 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7600 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7601 struct i40e_aqc_get_set_rss_key_data *key_dw =
7602 (struct i40e_aqc_get_set_rss_key_data *)key;
7603 enum i40e_status_code status =
7604 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7608 "Failed to configure RSS key via AQ, error status: %d",
7613 uint32_t *hash_key = (uint32_t *)key;
7616 if (vsi->type == I40E_VSI_SRIOV) {
7617 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7620 I40E_VFQF_HKEY1(i, vsi->user_param),
7624 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7625 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7628 I40E_WRITE_FLUSH(hw);
7635 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7637 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7638 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7642 if (!key || !key_len)
7645 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7646 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7647 (struct i40e_aqc_get_set_rss_key_data *)key);
7649 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7653 uint32_t *key_dw = (uint32_t *)key;
7656 if (vsi->type == I40E_VSI_SRIOV) {
7657 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7658 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7659 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7661 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7664 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7665 reg = I40E_PFQF_HKEY(i);
7666 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7668 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7676 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7678 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7682 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7683 rss_conf->rss_key_len);
7687 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7688 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7689 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7690 I40E_WRITE_FLUSH(hw);
7696 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7697 struct rte_eth_rss_conf *rss_conf)
7699 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7700 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7701 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7704 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7705 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7707 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7708 if (rss_hf != 0) /* Enable RSS */
7710 return 0; /* Nothing to do */
7713 if (rss_hf == 0) /* Disable RSS */
7716 return i40e_hw_rss_hash_set(pf, rss_conf);
7720 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7721 struct rte_eth_rss_conf *rss_conf)
7723 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7724 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7731 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7732 &rss_conf->rss_key_len);
7736 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7737 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7738 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7744 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7746 switch (filter_type) {
7747 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7748 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7750 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7751 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7753 case RTE_TUNNEL_FILTER_IMAC_TENID:
7754 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7756 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7757 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7759 case ETH_TUNNEL_FILTER_IMAC:
7760 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7762 case ETH_TUNNEL_FILTER_OIP:
7763 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7765 case ETH_TUNNEL_FILTER_IIP:
7766 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7769 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7776 /* Convert tunnel filter structure */
7778 i40e_tunnel_filter_convert(
7779 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7780 struct i40e_tunnel_filter *tunnel_filter)
7782 rte_ether_addr_copy((struct rte_ether_addr *)
7783 &cld_filter->element.outer_mac,
7784 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7785 rte_ether_addr_copy((struct rte_ether_addr *)
7786 &cld_filter->element.inner_mac,
7787 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7788 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7789 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7790 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7791 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7792 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7794 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7795 tunnel_filter->input.flags = cld_filter->element.flags;
7796 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7797 tunnel_filter->queue = cld_filter->element.queue_number;
7798 rte_memcpy(tunnel_filter->input.general_fields,
7799 cld_filter->general_fields,
7800 sizeof(cld_filter->general_fields));
7805 /* Check if there exists the tunnel filter */
7806 struct i40e_tunnel_filter *
7807 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7808 const struct i40e_tunnel_filter_input *input)
7812 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7816 return tunnel_rule->hash_map[ret];
7819 /* Add a tunnel filter into the SW list */
7821 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7822 struct i40e_tunnel_filter *tunnel_filter)
7824 struct i40e_tunnel_rule *rule = &pf->tunnel;
7827 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7830 "Failed to insert tunnel filter to hash table %d!",
7834 rule->hash_map[ret] = tunnel_filter;
7836 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7841 /* Delete a tunnel filter from the SW list */
7843 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7844 struct i40e_tunnel_filter_input *input)
7846 struct i40e_tunnel_rule *rule = &pf->tunnel;
7847 struct i40e_tunnel_filter *tunnel_filter;
7850 ret = rte_hash_del_key(rule->hash_table, input);
7853 "Failed to delete tunnel filter to hash table %d!",
7857 tunnel_filter = rule->hash_map[ret];
7858 rule->hash_map[ret] = NULL;
7860 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7861 rte_free(tunnel_filter);
7866 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7867 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7868 #define I40E_TR_GENEVE_KEY_MASK 0x8
7869 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7870 #define I40E_TR_GRE_KEY_MASK 0x400
7871 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7872 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7873 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7874 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7875 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7876 #define I40E_DIRECTION_INGRESS_KEY 0x8000
7877 #define I40E_TR_L4_TYPE_TCP 0x2
7878 #define I40E_TR_L4_TYPE_UDP 0x4
7879 #define I40E_TR_L4_TYPE_SCTP 0x8
7882 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7884 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7885 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7886 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7887 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7888 enum i40e_status_code status = I40E_SUCCESS;
7890 if (pf->support_multi_driver) {
7891 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7892 return I40E_NOT_SUPPORTED;
7895 memset(&filter_replace, 0,
7896 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7897 memset(&filter_replace_buf, 0,
7898 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7900 /* create L1 filter */
7901 filter_replace.old_filter_type =
7902 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7903 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7904 filter_replace.tr_bit = 0;
7906 /* Prepare the buffer, 3 entries */
7907 filter_replace_buf.data[0] =
7908 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7909 filter_replace_buf.data[0] |=
7910 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7911 filter_replace_buf.data[2] = 0xFF;
7912 filter_replace_buf.data[3] = 0xFF;
7913 filter_replace_buf.data[4] =
7914 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7915 filter_replace_buf.data[4] |=
7916 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7917 filter_replace_buf.data[7] = 0xF0;
7918 filter_replace_buf.data[8]
7919 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7920 filter_replace_buf.data[8] |=
7921 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7922 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7923 I40E_TR_GENEVE_KEY_MASK |
7924 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7925 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7926 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7927 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7929 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7930 &filter_replace_buf);
7931 if (!status && (filter_replace.old_filter_type !=
7932 filter_replace.new_filter_type))
7933 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7934 " original: 0x%x, new: 0x%x",
7936 filter_replace.old_filter_type,
7937 filter_replace.new_filter_type);
7943 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7945 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7946 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7947 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7948 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7949 enum i40e_status_code status = I40E_SUCCESS;
7951 if (pf->support_multi_driver) {
7952 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7953 return I40E_NOT_SUPPORTED;
7957 memset(&filter_replace, 0,
7958 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7959 memset(&filter_replace_buf, 0,
7960 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7961 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7962 I40E_AQC_MIRROR_CLOUD_FILTER;
7963 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7964 filter_replace.new_filter_type =
7965 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7966 /* Prepare the buffer, 2 entries */
7967 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7968 filter_replace_buf.data[0] |=
7969 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7970 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7971 filter_replace_buf.data[4] |=
7972 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7973 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7974 &filter_replace_buf);
7977 if (filter_replace.old_filter_type !=
7978 filter_replace.new_filter_type)
7979 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7980 " original: 0x%x, new: 0x%x",
7982 filter_replace.old_filter_type,
7983 filter_replace.new_filter_type);
7986 memset(&filter_replace, 0,
7987 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7988 memset(&filter_replace_buf, 0,
7989 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7991 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7992 I40E_AQC_MIRROR_CLOUD_FILTER;
7993 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7994 filter_replace.new_filter_type =
7995 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7996 /* Prepare the buffer, 2 entries */
7997 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7998 filter_replace_buf.data[0] |=
7999 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8000 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8001 filter_replace_buf.data[4] |=
8002 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8004 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8005 &filter_replace_buf);
8006 if (!status && (filter_replace.old_filter_type !=
8007 filter_replace.new_filter_type))
8008 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8009 " original: 0x%x, new: 0x%x",
8011 filter_replace.old_filter_type,
8012 filter_replace.new_filter_type);
8017 static enum i40e_status_code
8018 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8020 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8021 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8022 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8023 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8024 enum i40e_status_code status = I40E_SUCCESS;
8026 if (pf->support_multi_driver) {
8027 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8028 return I40E_NOT_SUPPORTED;
8032 memset(&filter_replace, 0,
8033 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8034 memset(&filter_replace_buf, 0,
8035 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8036 /* create L1 filter */
8037 filter_replace.old_filter_type =
8038 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8039 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8040 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8041 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8042 /* Prepare the buffer, 2 entries */
8043 filter_replace_buf.data[0] =
8044 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8045 filter_replace_buf.data[0] |=
8046 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8047 filter_replace_buf.data[2] = 0xFF;
8048 filter_replace_buf.data[3] = 0xFF;
8049 filter_replace_buf.data[4] =
8050 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8051 filter_replace_buf.data[4] |=
8052 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8053 filter_replace_buf.data[6] = 0xFF;
8054 filter_replace_buf.data[7] = 0xFF;
8055 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8056 &filter_replace_buf);
8059 if (filter_replace.old_filter_type !=
8060 filter_replace.new_filter_type)
8061 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8062 " original: 0x%x, new: 0x%x",
8064 filter_replace.old_filter_type,
8065 filter_replace.new_filter_type);
8068 memset(&filter_replace, 0,
8069 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8070 memset(&filter_replace_buf, 0,
8071 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8072 /* create L1 filter */
8073 filter_replace.old_filter_type =
8074 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8075 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8076 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8077 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8078 /* Prepare the buffer, 2 entries */
8079 filter_replace_buf.data[0] =
8080 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8081 filter_replace_buf.data[0] |=
8082 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8083 filter_replace_buf.data[2] = 0xFF;
8084 filter_replace_buf.data[3] = 0xFF;
8085 filter_replace_buf.data[4] =
8086 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8087 filter_replace_buf.data[4] |=
8088 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8089 filter_replace_buf.data[6] = 0xFF;
8090 filter_replace_buf.data[7] = 0xFF;
8092 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8093 &filter_replace_buf);
8094 if (!status && (filter_replace.old_filter_type !=
8095 filter_replace.new_filter_type))
8096 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8097 " original: 0x%x, new: 0x%x",
8099 filter_replace.old_filter_type,
8100 filter_replace.new_filter_type);
8106 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8108 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8109 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8110 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8111 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8112 enum i40e_status_code status = I40E_SUCCESS;
8114 if (pf->support_multi_driver) {
8115 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8116 return I40E_NOT_SUPPORTED;
8120 memset(&filter_replace, 0,
8121 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8122 memset(&filter_replace_buf, 0,
8123 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8124 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8125 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8126 filter_replace.new_filter_type =
8127 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8128 /* Prepare the buffer, 2 entries */
8129 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8130 filter_replace_buf.data[0] |=
8131 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8132 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8133 filter_replace_buf.data[4] |=
8134 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8135 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8136 &filter_replace_buf);
8139 if (filter_replace.old_filter_type !=
8140 filter_replace.new_filter_type)
8141 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8142 " original: 0x%x, new: 0x%x",
8144 filter_replace.old_filter_type,
8145 filter_replace.new_filter_type);
8148 memset(&filter_replace, 0,
8149 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8150 memset(&filter_replace_buf, 0,
8151 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8152 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8153 filter_replace.old_filter_type =
8154 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8155 filter_replace.new_filter_type =
8156 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8157 /* Prepare the buffer, 2 entries */
8158 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8159 filter_replace_buf.data[0] |=
8160 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8161 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8162 filter_replace_buf.data[4] |=
8163 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8165 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8166 &filter_replace_buf);
8167 if (!status && (filter_replace.old_filter_type !=
8168 filter_replace.new_filter_type))
8169 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8170 " original: 0x%x, new: 0x%x",
8172 filter_replace.old_filter_type,
8173 filter_replace.new_filter_type);
8178 static enum i40e_status_code
8179 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8180 enum i40e_l4_port_type l4_port_type)
8182 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8183 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8184 enum i40e_status_code status = I40E_SUCCESS;
8185 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8186 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8188 if (pf->support_multi_driver) {
8189 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8190 return I40E_NOT_SUPPORTED;
8193 memset(&filter_replace, 0,
8194 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8195 memset(&filter_replace_buf, 0,
8196 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8198 /* create L1 filter */
8199 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8200 filter_replace.old_filter_type =
8201 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8202 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8203 filter_replace_buf.data[8] =
8204 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8206 filter_replace.old_filter_type =
8207 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8208 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8209 filter_replace_buf.data[8] =
8210 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8213 filter_replace.tr_bit = 0;
8214 /* Prepare the buffer, 3 entries */
8215 filter_replace_buf.data[0] =
8216 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8217 filter_replace_buf.data[0] |=
8218 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8219 filter_replace_buf.data[2] = 0x00;
8220 filter_replace_buf.data[3] =
8221 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8222 filter_replace_buf.data[4] =
8223 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8224 filter_replace_buf.data[4] |=
8225 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8226 filter_replace_buf.data[5] = 0x00;
8227 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8228 I40E_TR_L4_TYPE_TCP |
8229 I40E_TR_L4_TYPE_SCTP;
8230 filter_replace_buf.data[7] = 0x00;
8231 filter_replace_buf.data[8] |=
8232 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8233 filter_replace_buf.data[9] = 0x00;
8234 filter_replace_buf.data[10] = 0xFF;
8235 filter_replace_buf.data[11] = 0xFF;
8237 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8238 &filter_replace_buf);
8239 if (!status && filter_replace.old_filter_type !=
8240 filter_replace.new_filter_type)
8241 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8242 " original: 0x%x, new: 0x%x",
8244 filter_replace.old_filter_type,
8245 filter_replace.new_filter_type);
8250 static enum i40e_status_code
8251 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8252 enum i40e_l4_port_type l4_port_type)
8254 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8255 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8256 enum i40e_status_code status = I40E_SUCCESS;
8257 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8258 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8260 if (pf->support_multi_driver) {
8261 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8262 return I40E_NOT_SUPPORTED;
8265 memset(&filter_replace, 0,
8266 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8267 memset(&filter_replace_buf, 0,
8268 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8270 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8271 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8272 filter_replace.new_filter_type =
8273 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8274 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8276 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8277 filter_replace.new_filter_type =
8278 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8279 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8282 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8283 filter_replace.tr_bit = 0;
8284 /* Prepare the buffer, 2 entries */
8285 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8286 filter_replace_buf.data[0] |=
8287 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8288 filter_replace_buf.data[4] |=
8289 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8290 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8291 &filter_replace_buf);
8293 if (!status && filter_replace.old_filter_type !=
8294 filter_replace.new_filter_type)
8295 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8296 " original: 0x%x, new: 0x%x",
8298 filter_replace.old_filter_type,
8299 filter_replace.new_filter_type);
8305 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8306 struct i40e_tunnel_filter_conf *tunnel_filter,
8310 uint32_t ipv4_addr, ipv4_addr_le;
8311 uint8_t i, tun_type = 0;
8312 /* internal variable to convert ipv6 byte order */
8313 uint32_t convert_ipv6[4];
8315 struct i40e_pf_vf *vf = NULL;
8316 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8317 struct i40e_vsi *vsi;
8318 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8319 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8320 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8321 struct i40e_tunnel_filter *tunnel, *node;
8322 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8324 bool big_buffer = 0;
8326 cld_filter = rte_zmalloc("tunnel_filter",
8327 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8330 if (cld_filter == NULL) {
8331 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8334 pfilter = cld_filter;
8336 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8337 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8338 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8339 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8341 pfilter->element.inner_vlan =
8342 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8343 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8344 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8345 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8346 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8347 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8349 sizeof(pfilter->element.ipaddr.v4.data));
8351 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8352 for (i = 0; i < 4; i++) {
8354 rte_cpu_to_le_32(rte_be_to_cpu_32(
8355 tunnel_filter->ip_addr.ipv6_addr[i]));
8357 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8359 sizeof(pfilter->element.ipaddr.v6.data));
8362 /* check tunneled type */
8363 switch (tunnel_filter->tunnel_type) {
8364 case I40E_TUNNEL_TYPE_VXLAN:
8365 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8367 case I40E_TUNNEL_TYPE_NVGRE:
8368 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8370 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8371 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8373 case I40E_TUNNEL_TYPE_MPLSoUDP:
8374 if (!pf->mpls_replace_flag) {
8375 i40e_replace_mpls_l1_filter(pf);
8376 i40e_replace_mpls_cloud_filter(pf);
8377 pf->mpls_replace_flag = 1;
8379 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8380 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8382 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8383 (teid_le & 0xF) << 12;
8384 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8387 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8389 case I40E_TUNNEL_TYPE_MPLSoGRE:
8390 if (!pf->mpls_replace_flag) {
8391 i40e_replace_mpls_l1_filter(pf);
8392 i40e_replace_mpls_cloud_filter(pf);
8393 pf->mpls_replace_flag = 1;
8395 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8396 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8398 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8399 (teid_le & 0xF) << 12;
8400 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8403 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8405 case I40E_TUNNEL_TYPE_GTPC:
8406 if (!pf->gtp_replace_flag) {
8407 i40e_replace_gtp_l1_filter(pf);
8408 i40e_replace_gtp_cloud_filter(pf);
8409 pf->gtp_replace_flag = 1;
8411 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8412 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8413 (teid_le >> 16) & 0xFFFF;
8414 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8416 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8420 case I40E_TUNNEL_TYPE_GTPU:
8421 if (!pf->gtp_replace_flag) {
8422 i40e_replace_gtp_l1_filter(pf);
8423 i40e_replace_gtp_cloud_filter(pf);
8424 pf->gtp_replace_flag = 1;
8426 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8427 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8428 (teid_le >> 16) & 0xFFFF;
8429 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8431 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8435 case I40E_TUNNEL_TYPE_QINQ:
8436 if (!pf->qinq_replace_flag) {
8437 ret = i40e_cloud_filter_qinq_create(pf);
8440 "QinQ tunnel filter already created.");
8441 pf->qinq_replace_flag = 1;
8443 /* Add in the General fields the values of
8444 * the Outer and Inner VLAN
8445 * Big Buffer should be set, see changes in
8446 * i40e_aq_add_cloud_filters
8448 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8449 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8452 case I40E_CLOUD_TYPE_UDP:
8453 case I40E_CLOUD_TYPE_TCP:
8454 case I40E_CLOUD_TYPE_SCTP:
8455 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8456 if (!pf->sport_replace_flag) {
8457 i40e_replace_port_l1_filter(pf,
8458 tunnel_filter->l4_port_type);
8459 i40e_replace_port_cloud_filter(pf,
8460 tunnel_filter->l4_port_type);
8461 pf->sport_replace_flag = 1;
8463 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8464 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8465 I40E_DIRECTION_INGRESS_KEY;
8467 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8468 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8469 I40E_TR_L4_TYPE_UDP;
8470 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8471 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8472 I40E_TR_L4_TYPE_TCP;
8474 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8475 I40E_TR_L4_TYPE_SCTP;
8477 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8478 (teid_le >> 16) & 0xFFFF;
8481 if (!pf->dport_replace_flag) {
8482 i40e_replace_port_l1_filter(pf,
8483 tunnel_filter->l4_port_type);
8484 i40e_replace_port_cloud_filter(pf,
8485 tunnel_filter->l4_port_type);
8486 pf->dport_replace_flag = 1;
8488 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8489 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8490 I40E_DIRECTION_INGRESS_KEY;
8492 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8493 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8494 I40E_TR_L4_TYPE_UDP;
8495 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8496 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8497 I40E_TR_L4_TYPE_TCP;
8499 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8500 I40E_TR_L4_TYPE_SCTP;
8502 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8503 (teid_le >> 16) & 0xFFFF;
8509 /* Other tunnel types is not supported. */
8510 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8511 rte_free(cld_filter);
8515 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8516 pfilter->element.flags =
8517 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8518 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8519 pfilter->element.flags =
8520 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8521 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8522 pfilter->element.flags =
8523 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8524 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8525 pfilter->element.flags =
8526 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8527 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8528 pfilter->element.flags |=
8529 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8530 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8531 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8532 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8533 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8534 pfilter->element.flags |=
8535 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8537 pfilter->element.flags |=
8538 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8540 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8541 &pfilter->element.flags);
8543 rte_free(cld_filter);
8548 pfilter->element.flags |= rte_cpu_to_le_16(
8549 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8550 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8551 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8552 pfilter->element.queue_number =
8553 rte_cpu_to_le_16(tunnel_filter->queue_id);
8555 if (!tunnel_filter->is_to_vf)
8558 if (tunnel_filter->vf_id >= pf->vf_num) {
8559 PMD_DRV_LOG(ERR, "Invalid argument.");
8560 rte_free(cld_filter);
8563 vf = &pf->vfs[tunnel_filter->vf_id];
8567 /* Check if there is the filter in SW list */
8568 memset(&check_filter, 0, sizeof(check_filter));
8569 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8570 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8571 check_filter.vf_id = tunnel_filter->vf_id;
8572 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8574 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8575 rte_free(cld_filter);
8579 if (!add && !node) {
8580 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8581 rte_free(cld_filter);
8587 ret = i40e_aq_add_cloud_filters_bb(hw,
8588 vsi->seid, cld_filter, 1);
8590 ret = i40e_aq_add_cloud_filters(hw,
8591 vsi->seid, &cld_filter->element, 1);
8593 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8594 rte_free(cld_filter);
8597 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8598 if (tunnel == NULL) {
8599 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8600 rte_free(cld_filter);
8604 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8605 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8610 ret = i40e_aq_rem_cloud_filters_bb(
8611 hw, vsi->seid, cld_filter, 1);
8613 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8614 &cld_filter->element, 1);
8616 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8617 rte_free(cld_filter);
8620 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8623 rte_free(cld_filter);
8628 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8632 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8633 if (pf->vxlan_ports[i] == port)
8641 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8644 uint8_t filter_idx = 0;
8645 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8647 idx = i40e_get_vxlan_port_idx(pf, port);
8649 /* Check if port already exists */
8651 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8655 /* Now check if there is space to add the new port */
8656 idx = i40e_get_vxlan_port_idx(pf, 0);
8659 "Maximum number of UDP ports reached, not adding port %d",
8664 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8667 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8671 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8674 /* New port: add it and mark its index in the bitmap */
8675 pf->vxlan_ports[idx] = port;
8676 pf->vxlan_bitmap |= (1 << idx);
8678 if (!(pf->flags & I40E_FLAG_VXLAN))
8679 pf->flags |= I40E_FLAG_VXLAN;
8685 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8688 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8690 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8691 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8695 idx = i40e_get_vxlan_port_idx(pf, port);
8698 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8702 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8703 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8707 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8710 pf->vxlan_ports[idx] = 0;
8711 pf->vxlan_bitmap &= ~(1 << idx);
8713 if (!pf->vxlan_bitmap)
8714 pf->flags &= ~I40E_FLAG_VXLAN;
8719 /* Add UDP tunneling port */
8721 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8722 struct rte_eth_udp_tunnel *udp_tunnel)
8725 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8727 if (udp_tunnel == NULL)
8730 switch (udp_tunnel->prot_type) {
8731 case RTE_TUNNEL_TYPE_VXLAN:
8732 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8733 I40E_AQC_TUNNEL_TYPE_VXLAN);
8735 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8736 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8737 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8739 case RTE_TUNNEL_TYPE_GENEVE:
8740 case RTE_TUNNEL_TYPE_TEREDO:
8741 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8746 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8754 /* Remove UDP tunneling port */
8756 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8757 struct rte_eth_udp_tunnel *udp_tunnel)
8760 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8762 if (udp_tunnel == NULL)
8765 switch (udp_tunnel->prot_type) {
8766 case RTE_TUNNEL_TYPE_VXLAN:
8767 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8768 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8770 case RTE_TUNNEL_TYPE_GENEVE:
8771 case RTE_TUNNEL_TYPE_TEREDO:
8772 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8776 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8784 /* Calculate the maximum number of contiguous PF queues that are configured */
8786 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8788 struct rte_eth_dev_data *data = pf->dev_data;
8790 struct i40e_rx_queue *rxq;
8793 for (i = 0; i < pf->lan_nb_qps; i++) {
8794 rxq = data->rx_queues[i];
8795 if (rxq && rxq->q_set)
8804 /* Reset the global configure of hash function and input sets */
8806 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8808 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8809 uint32_t reg, reg_val;
8812 /* Reset global RSS function sets */
8813 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8814 if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8815 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8816 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8819 for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8823 if (hw->mac.type == I40E_MAC_X722)
8824 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8828 /* Reset pctype insets */
8829 inset = i40e_get_default_input_set(i);
8831 pf->hash_input_set[pctype] = inset;
8832 inset = i40e_translate_input_set_reg(hw->mac.type,
8835 reg = I40E_GLQF_HASH_INSET(0, pctype);
8836 i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8837 reg = I40E_GLQF_HASH_INSET(1, pctype);
8838 i40e_check_write_global_reg(hw, reg,
8839 (uint32_t)(inset >> 32));
8841 /* Clear unused mask registers of the pctype */
8842 for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8843 reg = I40E_GLQF_HASH_MSK(j, pctype);
8844 i40e_check_write_global_reg(hw, reg, 0);
8848 /* Reset pctype symmetric sets */
8849 reg = I40E_GLQF_HSYM(pctype);
8850 reg_val = i40e_read_rx_ctl(hw, reg);
8851 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8852 reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8853 i40e_write_global_rx_ctl(hw, reg, reg_val);
8856 I40E_WRITE_FLUSH(hw);
8860 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8862 struct i40e_hw *hw = &pf->adapter->hw;
8863 uint8_t lut[ETH_RSS_RETA_SIZE_512];
8867 /* If both VMDQ and RSS enabled, not all of PF queues are
8868 * configured. It's necessary to calculate the actual PF
8869 * queues that are configured.
8871 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8872 num = i40e_pf_calc_configured_queues_num(pf);
8874 num = pf->dev_data->nb_rx_queues;
8876 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8880 for (i = 0; i < hw->func_caps.rss_table_size; i++)
8881 lut[i] = (uint8_t)(i % (uint32_t)num);
8883 return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8887 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8889 const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8894 rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8896 pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8897 static uint32_t rss_key_default[] = {0x6b793944,
8898 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8899 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8900 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8902 rss_key = (uint8_t *)rss_key_default;
8905 return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8909 i40e_pf_rss_reset(struct i40e_pf *pf)
8911 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8915 pf->hash_filter_enabled = 0;
8916 i40e_pf_disable_rss(pf);
8917 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8919 if (!pf->support_multi_driver)
8920 i40e_pf_global_rss_reset(pf);
8922 /* Reset RETA table */
8923 if (pf->adapter->rss_reta_updated == 0) {
8924 ret = i40e_pf_reset_rss_reta(pf);
8929 return i40e_pf_reset_rss_key(pf);
8934 i40e_pf_config_rss(struct i40e_pf *pf)
8937 enum rte_eth_rx_mq_mode mq_mode;
8938 uint64_t rss_hf, hena;
8941 ret = i40e_pf_rss_reset(pf);
8943 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8947 rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8948 mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8949 if (!(rss_hf & pf->adapter->flow_types_mask) ||
8950 !(mq_mode & ETH_MQ_RX_RSS_FLAG))
8953 hw = I40E_PF_TO_HW(pf);
8954 hena = i40e_config_hena(pf->adapter, rss_hf);
8955 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8956 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8957 I40E_WRITE_FLUSH(hw);
8962 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8963 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8965 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8967 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8971 if (pf->support_multi_driver) {
8972 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8976 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8977 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8980 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8981 } else if (len == 4) {
8982 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8984 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8989 ret = i40e_aq_debug_write_global_register(hw,
8990 I40E_GL_PRS_FVBM(2),
8994 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8995 "with value 0x%08x",
8996 I40E_GL_PRS_FVBM(2), reg);
9000 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9001 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9006 /* Set the symmetric hash enable configurations per port */
9008 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9010 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9013 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
9016 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9018 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9021 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9023 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9024 I40E_WRITE_FLUSH(hw);
9028 * Valid input sets for hash and flow director filters per PCTYPE
9031 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9032 enum rte_filter_type filter)
9036 static const uint64_t valid_hash_inset_table[] = {
9037 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9038 I40E_INSET_DMAC | I40E_INSET_SMAC |
9039 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9040 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9041 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9042 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9043 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9044 I40E_INSET_FLEX_PAYLOAD,
9045 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9046 I40E_INSET_DMAC | I40E_INSET_SMAC |
9047 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9048 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9049 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9050 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9051 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9052 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9053 I40E_INSET_FLEX_PAYLOAD,
9054 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9055 I40E_INSET_DMAC | I40E_INSET_SMAC |
9056 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9057 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9058 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9059 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9060 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9061 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9062 I40E_INSET_FLEX_PAYLOAD,
9063 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9064 I40E_INSET_DMAC | I40E_INSET_SMAC |
9065 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9066 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9067 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9068 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9069 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9070 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9071 I40E_INSET_FLEX_PAYLOAD,
9072 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9073 I40E_INSET_DMAC | I40E_INSET_SMAC |
9074 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9076 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9077 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9078 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9079 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9080 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9081 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9082 I40E_INSET_DMAC | I40E_INSET_SMAC |
9083 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9084 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9085 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9086 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9087 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9088 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9089 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9090 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9091 I40E_INSET_DMAC | I40E_INSET_SMAC |
9092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9094 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9095 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9096 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9097 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9098 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9099 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9100 I40E_INSET_DMAC | I40E_INSET_SMAC |
9101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9102 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9103 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9104 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9105 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9106 I40E_INSET_FLEX_PAYLOAD,
9107 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9108 I40E_INSET_DMAC | I40E_INSET_SMAC |
9109 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9110 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9111 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9112 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9113 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9114 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9115 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9116 I40E_INSET_DMAC | I40E_INSET_SMAC |
9117 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9118 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9119 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9120 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9121 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9122 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9123 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9124 I40E_INSET_DMAC | I40E_INSET_SMAC |
9125 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9126 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9127 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9128 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9129 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9130 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9131 I40E_INSET_FLEX_PAYLOAD,
9132 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9133 I40E_INSET_DMAC | I40E_INSET_SMAC |
9134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9135 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9136 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9137 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9138 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9139 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9140 I40E_INSET_FLEX_PAYLOAD,
9141 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9142 I40E_INSET_DMAC | I40E_INSET_SMAC |
9143 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9145 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9146 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9147 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9148 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9149 I40E_INSET_FLEX_PAYLOAD,
9150 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9151 I40E_INSET_DMAC | I40E_INSET_SMAC |
9152 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9153 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9154 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9155 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9156 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9157 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9158 I40E_INSET_FLEX_PAYLOAD,
9159 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9160 I40E_INSET_DMAC | I40E_INSET_SMAC |
9161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9162 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9163 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9164 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9165 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9166 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9167 I40E_INSET_FLEX_PAYLOAD,
9168 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9169 I40E_INSET_DMAC | I40E_INSET_SMAC |
9170 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9171 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9172 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9173 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9174 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9175 I40E_INSET_FLEX_PAYLOAD,
9176 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9177 I40E_INSET_DMAC | I40E_INSET_SMAC |
9178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9179 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9180 I40E_INSET_FLEX_PAYLOAD,
9184 * Flow director supports only fields defined in
9185 * union rte_eth_fdir_flow.
9187 static const uint64_t valid_fdir_inset_table[] = {
9188 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9190 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9191 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9192 I40E_INSET_IPV4_TTL,
9193 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9194 I40E_INSET_DMAC | I40E_INSET_SMAC |
9195 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9196 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9197 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9198 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9199 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9200 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9201 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9202 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9203 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9204 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9205 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9206 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9207 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9208 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9209 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9210 I40E_INSET_DMAC | I40E_INSET_SMAC |
9211 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9212 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9213 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9214 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9215 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9216 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9217 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9218 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9219 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9220 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9221 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9222 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9223 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9224 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9226 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9227 I40E_INSET_DMAC | I40E_INSET_SMAC |
9228 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9229 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9230 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9231 I40E_INSET_IPV4_TTL,
9232 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9233 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9234 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9235 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9236 I40E_INSET_IPV6_HOP_LIMIT,
9237 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9238 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9239 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9240 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9241 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9242 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9243 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9244 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9245 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9246 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9247 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9248 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9249 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9250 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9251 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9252 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9253 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9254 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9255 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9256 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9257 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9258 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9259 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9260 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9261 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9262 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9263 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9264 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9265 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9266 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9268 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9269 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9270 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9271 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9272 I40E_INSET_IPV6_HOP_LIMIT,
9273 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9274 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9275 I40E_INSET_LAST_ETHER_TYPE,
9278 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9280 if (filter == RTE_ETH_FILTER_HASH)
9281 valid = valid_hash_inset_table[pctype];
9283 valid = valid_fdir_inset_table[pctype];
9289 * Validate if the input set is allowed for a specific PCTYPE
9292 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9293 enum rte_filter_type filter, uint64_t inset)
9297 valid = i40e_get_valid_input_set(pctype, filter);
9298 if (inset & (~valid))
9304 /* default input set fields combination per pctype */
9306 i40e_get_default_input_set(uint16_t pctype)
9308 static const uint64_t default_inset_table[] = {
9309 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9310 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9311 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9312 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9313 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9314 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9315 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9316 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9317 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9318 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9319 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9320 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9321 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9322 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9323 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9324 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9325 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9326 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9327 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9328 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9330 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9331 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9332 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9333 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9334 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9335 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9336 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9337 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9338 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9339 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9340 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9341 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9342 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9343 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9344 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9345 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9346 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9347 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9348 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9349 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9350 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9351 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9353 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9354 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9355 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9356 I40E_INSET_LAST_ETHER_TYPE,
9359 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9362 return default_inset_table[pctype];
9366 * Translate the input set from bit masks to register aware bit masks
9370 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9380 static const struct inset_map inset_map_common[] = {
9381 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9382 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9383 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9384 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9385 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9386 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9387 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9388 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9389 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9390 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9391 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9392 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9393 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9394 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9395 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9396 {I40E_INSET_TUNNEL_DMAC,
9397 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9398 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9399 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9400 {I40E_INSET_TUNNEL_SRC_PORT,
9401 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9402 {I40E_INSET_TUNNEL_DST_PORT,
9403 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9404 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9405 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9406 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9407 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9408 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9409 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9410 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9411 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9412 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9415 /* some different registers map in x722*/
9416 static const struct inset_map inset_map_diff_x722[] = {
9417 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9418 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9419 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9420 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9423 static const struct inset_map inset_map_diff_not_x722[] = {
9424 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9425 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9426 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9427 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9433 /* Translate input set to register aware inset */
9434 if (type == I40E_MAC_X722) {
9435 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9436 if (input & inset_map_diff_x722[i].inset)
9437 val |= inset_map_diff_x722[i].inset_reg;
9440 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9441 if (input & inset_map_diff_not_x722[i].inset)
9442 val |= inset_map_diff_not_x722[i].inset_reg;
9446 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9447 if (input & inset_map_common[i].inset)
9448 val |= inset_map_common[i].inset_reg;
9455 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9456 uint32_t pit_reg_count, uint32_t hdr_off)
9458 const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9459 uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9460 uint32_t i, reg_val, src_off, count;
9462 for (i = pit_reg_start; i < pit_reg_end; i++) {
9463 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9465 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9466 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9468 if (src_off <= field_off && (src_off + count) > field_off)
9472 if (i >= pit_reg_end) {
9474 "Hardware GLQF_PIT configuration does not support this field mask");
9478 return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9482 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9483 uint32_t *mask, uint8_t nb_elem)
9485 static const uint64_t mask_inset[] = {
9486 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9487 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9489 static const struct {
9493 } inset_mask_offset_map[] = {
9494 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9495 offsetof(struct rte_ipv4_hdr, type_of_service) },
9497 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9498 offsetof(struct rte_ipv4_hdr, next_proto_id) },
9500 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9501 offsetof(struct rte_ipv4_hdr, time_to_live) },
9503 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9504 offsetof(struct rte_ipv6_hdr, vtc_flow) },
9506 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9507 offsetof(struct rte_ipv6_hdr, proto) },
9509 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9510 offsetof(struct rte_ipv6_hdr, hop_limits) },
9520 for (i = 0; i < RTE_DIM(mask_inset); i++) {
9521 /* Clear the inset bit, if no MASK is required,
9522 * for example proto + ttl
9524 if ((mask_inset[i] & inset) == mask_inset[i]) {
9525 inset &= ~mask_inset[i];
9531 for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9532 uint32_t pit_start, pit_count;
9535 if (!(inset_mask_offset_map[i].inset & inset))
9538 if (inset_mask_offset_map[i].inset &
9539 (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9540 I40E_INSET_IPV4_TTL)) {
9541 pit_start = I40E_GLQF_PIT_IPV4_START;
9542 pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9544 pit_start = I40E_GLQF_PIT_IPV6_START;
9545 pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9548 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9549 inset_mask_offset_map[i].offset);
9554 if (idx >= nb_elem) {
9556 "Configuration of inset mask out of range %u",
9561 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9562 inset_mask_offset_map[i].mask);
9570 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9572 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9574 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9576 i40e_write_rx_ctl(hw, addr, val);
9577 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9578 (uint32_t)i40e_read_rx_ctl(hw, addr));
9582 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9584 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9585 struct rte_eth_dev_data *dev_data =
9586 ((struct i40e_adapter *)hw->back)->pf.dev_data;
9587 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
9590 i40e_write_rx_ctl(hw, addr, val);
9591 PMD_DRV_LOG(WARNING,
9592 "i40e device %s changed global register [0x%08x]."
9593 " original: 0x%08x, new: 0x%08x",
9594 dev->device->name, addr, reg,
9595 (uint32_t)i40e_read_rx_ctl(hw, addr));
9600 i40e_filter_input_set_init(struct i40e_pf *pf)
9602 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9603 enum i40e_filter_pctype pctype;
9604 uint64_t input_set, inset_reg;
9605 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9609 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9610 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9611 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9613 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9616 input_set = i40e_get_default_input_set(pctype);
9618 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9619 I40E_INSET_MASK_NUM_REG);
9622 if (pf->support_multi_driver && num > 0) {
9623 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9626 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9629 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9630 (uint32_t)(inset_reg & UINT32_MAX));
9631 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9632 (uint32_t)((inset_reg >>
9633 I40E_32_BIT_WIDTH) & UINT32_MAX));
9634 if (!pf->support_multi_driver) {
9635 i40e_check_write_global_reg(hw,
9636 I40E_GLQF_HASH_INSET(0, pctype),
9637 (uint32_t)(inset_reg & UINT32_MAX));
9638 i40e_check_write_global_reg(hw,
9639 I40E_GLQF_HASH_INSET(1, pctype),
9640 (uint32_t)((inset_reg >>
9641 I40E_32_BIT_WIDTH) & UINT32_MAX));
9643 for (i = 0; i < num; i++) {
9644 i40e_check_write_global_reg(hw,
9645 I40E_GLQF_FD_MSK(i, pctype),
9647 i40e_check_write_global_reg(hw,
9648 I40E_GLQF_HASH_MSK(i, pctype),
9651 /*clear unused mask registers of the pctype */
9652 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9653 i40e_check_write_global_reg(hw,
9654 I40E_GLQF_FD_MSK(i, pctype),
9656 i40e_check_write_global_reg(hw,
9657 I40E_GLQF_HASH_MSK(i, pctype),
9661 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9663 I40E_WRITE_FLUSH(hw);
9665 /* store the default input set */
9666 if (!pf->support_multi_driver)
9667 pf->hash_input_set[pctype] = input_set;
9668 pf->fdir.input_set[pctype] = input_set;
9673 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9674 uint32_t pctype, bool add)
9676 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9677 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9678 uint64_t inset_reg = 0;
9681 if (pf->support_multi_driver) {
9683 "Modify input set is not permitted when multi-driver enabled.");
9687 /* For X722, get translated pctype in fd pctype register */
9688 if (hw->mac.type == I40E_MAC_X722)
9689 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9692 /* get inset value in register */
9693 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9694 inset_reg <<= I40E_32_BIT_WIDTH;
9695 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9696 input_set |= pf->hash_input_set[pctype];
9698 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9699 I40E_INSET_MASK_NUM_REG);
9703 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9705 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9706 (uint32_t)(inset_reg & UINT32_MAX));
9707 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9708 (uint32_t)((inset_reg >>
9709 I40E_32_BIT_WIDTH) & UINT32_MAX));
9711 for (i = 0; i < num; i++)
9712 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9714 /*clear unused mask registers of the pctype */
9715 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9716 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9718 I40E_WRITE_FLUSH(hw);
9720 pf->hash_input_set[pctype] = input_set;
9724 /* Convert ethertype filter structure */
9726 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9727 struct i40e_ethertype_filter *filter)
9729 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9730 RTE_ETHER_ADDR_LEN);
9731 filter->input.ether_type = input->ether_type;
9732 filter->flags = input->flags;
9733 filter->queue = input->queue;
9738 /* Check if there exists the ehtertype filter */
9739 struct i40e_ethertype_filter *
9740 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9741 const struct i40e_ethertype_filter_input *input)
9745 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9749 return ethertype_rule->hash_map[ret];
9752 /* Add ethertype filter in SW list */
9754 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9755 struct i40e_ethertype_filter *filter)
9757 struct i40e_ethertype_rule *rule = &pf->ethertype;
9760 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9763 "Failed to insert ethertype filter"
9764 " to hash table %d!",
9768 rule->hash_map[ret] = filter;
9770 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9775 /* Delete ethertype filter in SW list */
9777 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9778 struct i40e_ethertype_filter_input *input)
9780 struct i40e_ethertype_rule *rule = &pf->ethertype;
9781 struct i40e_ethertype_filter *filter;
9784 ret = rte_hash_del_key(rule->hash_table, input);
9787 "Failed to delete ethertype filter"
9788 " to hash table %d!",
9792 filter = rule->hash_map[ret];
9793 rule->hash_map[ret] = NULL;
9795 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9802 * Configure ethertype filter, which can director packet by filtering
9803 * with mac address and ether_type or only ether_type
9806 i40e_ethertype_filter_set(struct i40e_pf *pf,
9807 struct rte_eth_ethertype_filter *filter,
9810 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9811 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9812 struct i40e_ethertype_filter *ethertype_filter, *node;
9813 struct i40e_ethertype_filter check_filter;
9814 struct i40e_control_filter_stats stats;
9818 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9819 PMD_DRV_LOG(ERR, "Invalid queue ID");
9822 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9823 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9825 "unsupported ether_type(0x%04x) in control packet filter.",
9826 filter->ether_type);
9829 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9830 PMD_DRV_LOG(WARNING,
9831 "filter vlan ether_type in first tag is not supported.");
9833 /* Check if there is the filter in SW list */
9834 memset(&check_filter, 0, sizeof(check_filter));
9835 i40e_ethertype_filter_convert(filter, &check_filter);
9836 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9837 &check_filter.input);
9839 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9843 if (!add && !node) {
9844 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9848 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9849 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9850 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9851 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9852 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9854 memset(&stats, 0, sizeof(stats));
9855 ret = i40e_aq_add_rem_control_packet_filter(hw,
9856 filter->mac_addr.addr_bytes,
9857 filter->ether_type, flags,
9859 filter->queue, add, &stats, NULL);
9862 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9863 ret, stats.mac_etype_used, stats.etype_used,
9864 stats.mac_etype_free, stats.etype_free);
9868 /* Add or delete a filter in SW list */
9870 ethertype_filter = rte_zmalloc("ethertype_filter",
9871 sizeof(*ethertype_filter), 0);
9872 if (ethertype_filter == NULL) {
9873 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9877 rte_memcpy(ethertype_filter, &check_filter,
9878 sizeof(check_filter));
9879 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9881 rte_free(ethertype_filter);
9883 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9890 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9891 const struct rte_flow_ops **ops)
9896 *ops = &i40e_flow_ops;
9901 * Check and enable Extended Tag.
9902 * Enabling Extended Tag is important for 40G performance.
9905 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9907 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9911 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9914 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9918 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9919 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9924 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9927 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9931 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9932 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9935 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9936 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9939 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9946 * As some registers wouldn't be reset unless a global hardware reset,
9947 * hardware initialization is needed to put those registers into an
9948 * expected initial state.
9951 i40e_hw_init(struct rte_eth_dev *dev)
9953 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9955 i40e_enable_extended_tag(dev);
9957 /* clear the PF Queue Filter control register */
9958 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9960 /* Disable symmetric hash per port */
9961 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9965 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9966 * however this function will return only one highest pctype index,
9967 * which is not quite correct. This is known problem of i40e driver
9968 * and needs to be fixed later.
9970 enum i40e_filter_pctype
9971 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9974 uint64_t pctype_mask;
9976 if (flow_type < I40E_FLOW_TYPE_MAX) {
9977 pctype_mask = adapter->pctypes_tbl[flow_type];
9978 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9979 if (pctype_mask & (1ULL << i))
9980 return (enum i40e_filter_pctype)i;
9983 return I40E_FILTER_PCTYPE_INVALID;
9987 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9988 enum i40e_filter_pctype pctype)
9991 uint64_t pctype_mask = 1ULL << pctype;
9993 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9995 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9999 return RTE_ETH_FLOW_UNKNOWN;
10003 * On X710, performance number is far from the expectation on recent firmware
10004 * versions; on XL710, performance number is also far from the expectation on
10005 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10006 * mode is enabled and port MAC address is equal to the packet destination MAC
10007 * address. The fix for this issue may not be integrated in the following
10008 * firmware version. So the workaround in software driver is needed. It needs
10009 * to modify the initial values of 3 internal only registers for both X710 and
10010 * XL710. Note that the values for X710 or XL710 could be different, and the
10011 * workaround can be removed when it is fixed in firmware in the future.
10014 /* For both X710 and XL710 */
10015 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10016 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10017 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10019 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10020 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10023 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10024 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10027 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10029 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10030 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10033 * GL_SWR_PM_UP_THR:
10034 * The value is not impacted from the link speed, its value is set according
10035 * to the total number of ports for a better pipe-monitor configuration.
10038 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10040 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10041 .device_id = (dev), \
10042 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10044 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10045 .device_id = (dev), \
10046 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10048 static const struct {
10049 uint16_t device_id;
10051 } swr_pm_table[] = {
10052 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10053 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10054 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10055 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10056 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10058 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10059 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10060 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10061 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10062 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10063 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10064 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10068 if (value == NULL) {
10069 PMD_DRV_LOG(ERR, "value is NULL");
10073 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10074 if (hw->device_id == swr_pm_table[i].device_id) {
10075 *value = swr_pm_table[i].val;
10077 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10079 hw->device_id, *value);
10088 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10090 enum i40e_status_code status;
10091 struct i40e_aq_get_phy_abilities_resp phy_ab;
10092 int ret = -ENOTSUP;
10095 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10099 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10102 rte_delay_us(100000);
10104 status = i40e_aq_get_phy_capabilities(hw, false,
10105 true, &phy_ab, NULL);
10113 i40e_configure_registers(struct i40e_hw *hw)
10119 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10120 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10121 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10127 for (i = 0; i < RTE_DIM(reg_table); i++) {
10128 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10129 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10131 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10132 else /* For X710/XL710/XXV710 */
10133 if (hw->aq.fw_maj_ver < 6)
10135 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10138 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10141 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10142 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10144 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10145 else /* For X710/XL710/XXV710 */
10147 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10150 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10153 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10154 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10155 "GL_SWR_PM_UP_THR value fixup",
10160 reg_table[i].val = cfg_val;
10163 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10166 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10167 reg_table[i].addr);
10170 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10171 reg_table[i].addr, reg);
10172 if (reg == reg_table[i].val)
10175 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10176 reg_table[i].val, NULL);
10179 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10180 reg_table[i].val, reg_table[i].addr);
10183 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10184 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10188 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10189 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10190 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10192 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10197 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10198 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10202 /* Configure for double VLAN RX stripping */
10203 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10204 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10205 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10206 ret = i40e_aq_debug_write_register(hw,
10207 I40E_VSI_TSR(vsi->vsi_id),
10210 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10212 return I40E_ERR_CONFIG;
10216 /* Configure for double VLAN TX insertion */
10217 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10218 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10219 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10220 ret = i40e_aq_debug_write_register(hw,
10221 I40E_VSI_L2TAGSTXVALID(
10222 vsi->vsi_id), reg, NULL);
10225 "Failed to update VSI_L2TAGSTXVALID[%d]",
10227 return I40E_ERR_CONFIG;
10235 * i40e_aq_add_mirror_rule
10236 * @hw: pointer to the hardware structure
10237 * @seid: VEB seid to add mirror rule to
10238 * @dst_id: destination vsi seid
10239 * @entries: Buffer which contains the entities to be mirrored
10240 * @count: number of entities contained in the buffer
10241 * @rule_id:the rule_id of the rule to be added
10243 * Add a mirror rule for a given veb.
10246 static enum i40e_status_code
10247 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10248 uint16_t seid, uint16_t dst_id,
10249 uint16_t rule_type, uint16_t *entries,
10250 uint16_t count, uint16_t *rule_id)
10252 struct i40e_aq_desc desc;
10253 struct i40e_aqc_add_delete_mirror_rule cmd;
10254 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10255 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10258 enum i40e_status_code status;
10260 i40e_fill_default_direct_cmd_desc(&desc,
10261 i40e_aqc_opc_add_mirror_rule);
10262 memset(&cmd, 0, sizeof(cmd));
10264 buff_len = sizeof(uint16_t) * count;
10265 desc.datalen = rte_cpu_to_le_16(buff_len);
10267 desc.flags |= rte_cpu_to_le_16(
10268 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10269 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10270 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10271 cmd.num_entries = rte_cpu_to_le_16(count);
10272 cmd.seid = rte_cpu_to_le_16(seid);
10273 cmd.destination = rte_cpu_to_le_16(dst_id);
10275 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10276 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10278 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10279 hw->aq.asq_last_status, resp->rule_id,
10280 resp->mirror_rules_used, resp->mirror_rules_free);
10281 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10287 * i40e_aq_del_mirror_rule
10288 * @hw: pointer to the hardware structure
10289 * @seid: VEB seid to add mirror rule to
10290 * @entries: Buffer which contains the entities to be mirrored
10291 * @count: number of entities contained in the buffer
10292 * @rule_id:the rule_id of the rule to be delete
10294 * Delete a mirror rule for a given veb.
10297 static enum i40e_status_code
10298 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10299 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10300 uint16_t count, uint16_t rule_id)
10302 struct i40e_aq_desc desc;
10303 struct i40e_aqc_add_delete_mirror_rule cmd;
10304 uint16_t buff_len = 0;
10305 enum i40e_status_code status;
10308 i40e_fill_default_direct_cmd_desc(&desc,
10309 i40e_aqc_opc_delete_mirror_rule);
10310 memset(&cmd, 0, sizeof(cmd));
10311 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10312 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10314 cmd.num_entries = count;
10315 buff_len = sizeof(uint16_t) * count;
10316 desc.datalen = rte_cpu_to_le_16(buff_len);
10317 buff = (void *)entries;
10319 /* rule id is filled in destination field for deleting mirror rule */
10320 cmd.destination = rte_cpu_to_le_16(rule_id);
10322 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10323 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10324 cmd.seid = rte_cpu_to_le_16(seid);
10326 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10327 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10333 * i40e_mirror_rule_set
10334 * @dev: pointer to the hardware structure
10335 * @mirror_conf: mirror rule info
10336 * @sw_id: mirror rule's sw_id
10337 * @on: enable/disable
10339 * set a mirror rule.
10343 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10344 struct rte_eth_mirror_conf *mirror_conf,
10345 uint8_t sw_id, uint8_t on)
10347 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10348 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10349 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10350 struct i40e_mirror_rule *parent = NULL;
10351 uint16_t seid, dst_seid, rule_id;
10355 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10357 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10359 "mirror rule can not be configured without veb or vfs.");
10362 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10363 PMD_DRV_LOG(ERR, "mirror table is full.");
10366 if (mirror_conf->dst_pool > pf->vf_num) {
10367 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10368 mirror_conf->dst_pool);
10372 seid = pf->main_vsi->veb->seid;
10374 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10375 if (sw_id <= it->index) {
10381 if (mirr_rule && sw_id == mirr_rule->index) {
10383 PMD_DRV_LOG(ERR, "mirror rule exists.");
10386 ret = i40e_aq_del_mirror_rule(hw, seid,
10387 mirr_rule->rule_type,
10388 mirr_rule->entries,
10389 mirr_rule->num_entries, mirr_rule->id);
10392 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10393 ret, hw->aq.asq_last_status);
10396 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10397 rte_free(mirr_rule);
10398 pf->nb_mirror_rule--;
10402 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10406 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10407 sizeof(struct i40e_mirror_rule) , 0);
10409 PMD_DRV_LOG(ERR, "failed to allocate memory");
10410 return I40E_ERR_NO_MEMORY;
10412 switch (mirror_conf->rule_type) {
10413 case ETH_MIRROR_VLAN:
10414 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10415 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10416 mirr_rule->entries[j] =
10417 mirror_conf->vlan.vlan_id[i];
10422 PMD_DRV_LOG(ERR, "vlan is not specified.");
10423 rte_free(mirr_rule);
10426 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10428 case ETH_MIRROR_VIRTUAL_POOL_UP:
10429 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10430 /* check if the specified pool bit is out of range */
10431 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10432 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10433 rte_free(mirr_rule);
10436 for (i = 0, j = 0; i < pf->vf_num; i++) {
10437 if (mirror_conf->pool_mask & (1ULL << i)) {
10438 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10442 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10443 /* add pf vsi to entries */
10444 mirr_rule->entries[j] = pf->main_vsi_seid;
10448 PMD_DRV_LOG(ERR, "pool is not specified.");
10449 rte_free(mirr_rule);
10452 /* egress and ingress in aq commands means from switch but not port */
10453 mirr_rule->rule_type =
10454 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10455 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10456 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10458 case ETH_MIRROR_UPLINK_PORT:
10459 /* egress and ingress in aq commands means from switch but not port*/
10460 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10462 case ETH_MIRROR_DOWNLINK_PORT:
10463 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10466 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10467 mirror_conf->rule_type);
10468 rte_free(mirr_rule);
10472 /* If the dst_pool is equal to vf_num, consider it as PF */
10473 if (mirror_conf->dst_pool == pf->vf_num)
10474 dst_seid = pf->main_vsi_seid;
10476 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10478 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10479 mirr_rule->rule_type, mirr_rule->entries,
10483 "failed to add mirror rule: ret = %d, aq_err = %d.",
10484 ret, hw->aq.asq_last_status);
10485 rte_free(mirr_rule);
10489 mirr_rule->index = sw_id;
10490 mirr_rule->num_entries = j;
10491 mirr_rule->id = rule_id;
10492 mirr_rule->dst_vsi_seid = dst_seid;
10495 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10497 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10499 pf->nb_mirror_rule++;
10504 * i40e_mirror_rule_reset
10505 * @dev: pointer to the device
10506 * @sw_id: mirror rule's sw_id
10508 * reset a mirror rule.
10512 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10514 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10516 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10520 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10522 seid = pf->main_vsi->veb->seid;
10524 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10525 if (sw_id == it->index) {
10531 ret = i40e_aq_del_mirror_rule(hw, seid,
10532 mirr_rule->rule_type,
10533 mirr_rule->entries,
10534 mirr_rule->num_entries, mirr_rule->id);
10537 "failed to remove mirror rule: status = %d, aq_err = %d.",
10538 ret, hw->aq.asq_last_status);
10541 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10542 rte_free(mirr_rule);
10543 pf->nb_mirror_rule--;
10545 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10552 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10555 uint64_t systim_cycles;
10557 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10558 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10561 return systim_cycles;
10565 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10568 uint64_t rx_tstamp;
10570 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10571 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10578 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10580 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10581 uint64_t tx_tstamp;
10583 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10584 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10591 i40e_start_timecounters(struct rte_eth_dev *dev)
10593 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10594 struct i40e_adapter *adapter = dev->data->dev_private;
10595 struct rte_eth_link link;
10596 uint32_t tsync_inc_l;
10597 uint32_t tsync_inc_h;
10599 /* Get current link speed. */
10600 i40e_dev_link_update(dev, 1);
10601 rte_eth_linkstatus_get(dev, &link);
10603 switch (link.link_speed) {
10604 case ETH_SPEED_NUM_40G:
10605 case ETH_SPEED_NUM_25G:
10606 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10607 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10609 case ETH_SPEED_NUM_10G:
10610 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10611 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10613 case ETH_SPEED_NUM_1G:
10614 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10615 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10622 /* Set the timesync increment value. */
10623 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10624 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10626 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10627 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10628 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10630 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10631 adapter->systime_tc.cc_shift = 0;
10632 adapter->systime_tc.nsec_mask = 0;
10634 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10635 adapter->rx_tstamp_tc.cc_shift = 0;
10636 adapter->rx_tstamp_tc.nsec_mask = 0;
10638 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10639 adapter->tx_tstamp_tc.cc_shift = 0;
10640 adapter->tx_tstamp_tc.nsec_mask = 0;
10644 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10646 struct i40e_adapter *adapter = dev->data->dev_private;
10648 adapter->systime_tc.nsec += delta;
10649 adapter->rx_tstamp_tc.nsec += delta;
10650 adapter->tx_tstamp_tc.nsec += delta;
10656 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10659 struct i40e_adapter *adapter = dev->data->dev_private;
10661 ns = rte_timespec_to_ns(ts);
10663 /* Set the timecounters to a new value. */
10664 adapter->systime_tc.nsec = ns;
10665 adapter->rx_tstamp_tc.nsec = ns;
10666 adapter->tx_tstamp_tc.nsec = ns;
10672 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10674 uint64_t ns, systime_cycles;
10675 struct i40e_adapter *adapter = dev->data->dev_private;
10677 systime_cycles = i40e_read_systime_cyclecounter(dev);
10678 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10679 *ts = rte_ns_to_timespec(ns);
10685 i40e_timesync_enable(struct rte_eth_dev *dev)
10687 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10688 uint32_t tsync_ctl_l;
10689 uint32_t tsync_ctl_h;
10691 /* Stop the timesync system time. */
10692 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10693 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10694 /* Reset the timesync system time value. */
10695 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10696 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10698 i40e_start_timecounters(dev);
10700 /* Clear timesync registers. */
10701 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10702 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10703 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10704 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10705 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10706 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10708 /* Enable timestamping of PTP packets. */
10709 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10710 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10712 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10713 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10714 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10716 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10717 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10723 i40e_timesync_disable(struct rte_eth_dev *dev)
10725 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10726 uint32_t tsync_ctl_l;
10727 uint32_t tsync_ctl_h;
10729 /* Disable timestamping of transmitted PTP packets. */
10730 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10731 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10733 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10734 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10736 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10737 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10739 /* Reset the timesync increment value. */
10740 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10741 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10747 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10748 struct timespec *timestamp, uint32_t flags)
10750 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10751 struct i40e_adapter *adapter = dev->data->dev_private;
10752 uint32_t sync_status;
10753 uint32_t index = flags & 0x03;
10754 uint64_t rx_tstamp_cycles;
10757 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10758 if ((sync_status & (1 << index)) == 0)
10761 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10762 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10763 *timestamp = rte_ns_to_timespec(ns);
10769 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10770 struct timespec *timestamp)
10772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10773 struct i40e_adapter *adapter = dev->data->dev_private;
10774 uint32_t sync_status;
10775 uint64_t tx_tstamp_cycles;
10778 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10779 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10782 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10783 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10784 *timestamp = rte_ns_to_timespec(ns);
10790 * i40e_parse_dcb_configure - parse dcb configure from user
10791 * @dev: the device being configured
10792 * @dcb_cfg: pointer of the result of parse
10793 * @*tc_map: bit map of enabled traffic classes
10795 * Returns 0 on success, negative value on failure
10798 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10799 struct i40e_dcbx_config *dcb_cfg,
10802 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10803 uint8_t i, tc_bw, bw_lf;
10805 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10807 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10808 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10809 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10813 /* assume each tc has the same bw */
10814 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10815 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10816 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10817 /* to ensure the sum of tcbw is equal to 100 */
10818 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10819 for (i = 0; i < bw_lf; i++)
10820 dcb_cfg->etscfg.tcbwtable[i]++;
10822 /* assume each tc has the same Transmission Selection Algorithm */
10823 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10824 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10826 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10827 dcb_cfg->etscfg.prioritytable[i] =
10828 dcb_rx_conf->dcb_tc[i];
10830 /* FW needs one App to configure HW */
10831 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10832 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10833 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10834 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10836 if (dcb_rx_conf->nb_tcs == 0)
10837 *tc_map = 1; /* tc0 only */
10839 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10841 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10842 dcb_cfg->pfc.willing = 0;
10843 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10844 dcb_cfg->pfc.pfcenable = *tc_map;
10850 static enum i40e_status_code
10851 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10852 struct i40e_aqc_vsi_properties_data *info,
10853 uint8_t enabled_tcmap)
10855 enum i40e_status_code ret;
10856 int i, total_tc = 0;
10857 uint16_t qpnum_per_tc, bsf, qp_idx;
10858 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10859 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10860 uint16_t used_queues;
10862 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10863 if (ret != I40E_SUCCESS)
10866 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10867 if (enabled_tcmap & (1 << i))
10872 vsi->enabled_tc = enabled_tcmap;
10874 /* different VSI has different queues assigned */
10875 if (vsi->type == I40E_VSI_MAIN)
10876 used_queues = dev_data->nb_rx_queues -
10877 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10878 else if (vsi->type == I40E_VSI_VMDQ2)
10879 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10881 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10882 return I40E_ERR_NO_AVAILABLE_VSI;
10885 qpnum_per_tc = used_queues / total_tc;
10886 /* Number of queues per enabled TC */
10887 if (qpnum_per_tc == 0) {
10888 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10889 return I40E_ERR_INVALID_QP_ID;
10891 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10892 I40E_MAX_Q_PER_TC);
10893 bsf = rte_bsf32(qpnum_per_tc);
10896 * Configure TC and queue mapping parameters, for enabled TC,
10897 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10898 * default queue will serve it.
10901 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10902 if (vsi->enabled_tc & (1 << i)) {
10903 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10904 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10905 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10906 qp_idx += qpnum_per_tc;
10908 info->tc_mapping[i] = 0;
10911 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10912 if (vsi->type == I40E_VSI_SRIOV) {
10913 info->mapping_flags |=
10914 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10915 for (i = 0; i < vsi->nb_qps; i++)
10916 info->queue_mapping[i] =
10917 rte_cpu_to_le_16(vsi->base_queue + i);
10919 info->mapping_flags |=
10920 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10921 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10923 info->valid_sections |=
10924 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10926 return I40E_SUCCESS;
10930 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10931 * @veb: VEB to be configured
10932 * @tc_map: enabled TC bitmap
10934 * Returns 0 on success, negative value on failure
10936 static enum i40e_status_code
10937 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10939 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10940 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10941 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10942 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10943 enum i40e_status_code ret = I40E_SUCCESS;
10947 /* Check if enabled_tc is same as existing or new TCs */
10948 if (veb->enabled_tc == tc_map)
10951 /* configure tc bandwidth */
10952 memset(&veb_bw, 0, sizeof(veb_bw));
10953 veb_bw.tc_valid_bits = tc_map;
10954 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10955 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10956 if (tc_map & BIT_ULL(i))
10957 veb_bw.tc_bw_share_credits[i] = 1;
10959 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10963 "AQ command Config switch_comp BW allocation per TC failed = %d",
10964 hw->aq.asq_last_status);
10968 memset(&ets_query, 0, sizeof(ets_query));
10969 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10971 if (ret != I40E_SUCCESS) {
10973 "Failed to get switch_comp ETS configuration %u",
10974 hw->aq.asq_last_status);
10977 memset(&bw_query, 0, sizeof(bw_query));
10978 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10980 if (ret != I40E_SUCCESS) {
10982 "Failed to get switch_comp bandwidth configuration %u",
10983 hw->aq.asq_last_status);
10987 /* store and print out BW info */
10988 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10989 veb->bw_info.bw_max = ets_query.tc_bw_max;
10990 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10991 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10992 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10993 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10994 I40E_16_BIT_WIDTH);
10995 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10996 veb->bw_info.bw_ets_share_credits[i] =
10997 bw_query.tc_bw_share_credits[i];
10998 veb->bw_info.bw_ets_credits[i] =
10999 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11000 /* 4 bits per TC, 4th bit is reserved */
11001 veb->bw_info.bw_ets_max[i] =
11002 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11003 RTE_LEN2MASK(3, uint8_t));
11004 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11005 veb->bw_info.bw_ets_share_credits[i]);
11006 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11007 veb->bw_info.bw_ets_credits[i]);
11008 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11009 veb->bw_info.bw_ets_max[i]);
11012 veb->enabled_tc = tc_map;
11019 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11020 * @vsi: VSI to be configured
11021 * @tc_map: enabled TC bitmap
11023 * Returns 0 on success, negative value on failure
11025 static enum i40e_status_code
11026 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11028 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11029 struct i40e_vsi_context ctxt;
11030 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11031 enum i40e_status_code ret = I40E_SUCCESS;
11034 /* Check if enabled_tc is same as existing or new TCs */
11035 if (vsi->enabled_tc == tc_map)
11038 /* configure tc bandwidth */
11039 memset(&bw_data, 0, sizeof(bw_data));
11040 bw_data.tc_valid_bits = tc_map;
11041 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11042 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11043 if (tc_map & BIT_ULL(i))
11044 bw_data.tc_bw_credits[i] = 1;
11046 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11049 "AQ command Config VSI BW allocation per TC failed = %d",
11050 hw->aq.asq_last_status);
11053 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11054 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11056 /* Update Queue Pairs Mapping for currently enabled UPs */
11057 ctxt.seid = vsi->seid;
11058 ctxt.pf_num = hw->pf_id;
11060 ctxt.uplink_seid = vsi->uplink_seid;
11061 ctxt.info = vsi->info;
11063 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11067 /* Update the VSI after updating the VSI queue-mapping information */
11068 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11070 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11071 hw->aq.asq_last_status);
11074 /* update the local VSI info with updated queue map */
11075 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11076 sizeof(vsi->info.tc_mapping));
11077 rte_memcpy(&vsi->info.queue_mapping,
11078 &ctxt.info.queue_mapping,
11079 sizeof(vsi->info.queue_mapping));
11080 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11081 vsi->info.valid_sections = 0;
11083 /* query and update current VSI BW information */
11084 ret = i40e_vsi_get_bw_config(vsi);
11087 "Failed updating vsi bw info, err %s aq_err %s",
11088 i40e_stat_str(hw, ret),
11089 i40e_aq_str(hw, hw->aq.asq_last_status));
11093 vsi->enabled_tc = tc_map;
11100 * i40e_dcb_hw_configure - program the dcb setting to hw
11101 * @pf: pf the configuration is taken on
11102 * @new_cfg: new configuration
11103 * @tc_map: enabled TC bitmap
11105 * Returns 0 on success, negative value on failure
11107 static enum i40e_status_code
11108 i40e_dcb_hw_configure(struct i40e_pf *pf,
11109 struct i40e_dcbx_config *new_cfg,
11112 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11113 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11114 struct i40e_vsi *main_vsi = pf->main_vsi;
11115 struct i40e_vsi_list *vsi_list;
11116 enum i40e_status_code ret;
11120 /* Use the FW API if FW > v4.4*/
11121 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11122 (hw->aq.fw_maj_ver >= 5))) {
11124 "FW < v4.4, can not use FW LLDP API to configure DCB");
11125 return I40E_ERR_FIRMWARE_API_VERSION;
11128 /* Check if need reconfiguration */
11129 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11130 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11131 return I40E_SUCCESS;
11134 /* Copy the new config to the current config */
11135 *old_cfg = *new_cfg;
11136 old_cfg->etsrec = old_cfg->etscfg;
11137 ret = i40e_set_dcb_config(hw);
11139 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11140 i40e_stat_str(hw, ret),
11141 i40e_aq_str(hw, hw->aq.asq_last_status));
11144 /* set receive Arbiter to RR mode and ETS scheme by default */
11145 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11146 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11147 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11148 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11149 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11150 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11151 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11152 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11153 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11154 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11155 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11156 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11157 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11159 /* get local mib to check whether it is configured correctly */
11161 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11162 /* Get Local DCB Config */
11163 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11164 &hw->local_dcbx_config);
11166 /* if Veb is created, need to update TC of it at first */
11167 if (main_vsi->veb) {
11168 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11170 PMD_INIT_LOG(WARNING,
11171 "Failed configuring TC for VEB seid=%d",
11172 main_vsi->veb->seid);
11174 /* Update each VSI */
11175 i40e_vsi_config_tc(main_vsi, tc_map);
11176 if (main_vsi->veb) {
11177 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11178 /* Beside main VSI and VMDQ VSIs, only enable default
11179 * TC for other VSIs
11181 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11182 ret = i40e_vsi_config_tc(vsi_list->vsi,
11185 ret = i40e_vsi_config_tc(vsi_list->vsi,
11186 I40E_DEFAULT_TCMAP);
11188 PMD_INIT_LOG(WARNING,
11189 "Failed configuring TC for VSI seid=%d",
11190 vsi_list->vsi->seid);
11194 return I40E_SUCCESS;
11198 * i40e_dcb_init_configure - initial dcb config
11199 * @dev: device being configured
11200 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11202 * Returns 0 on success, negative value on failure
11205 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11207 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11208 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11211 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11212 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11216 /* DCB initialization:
11217 * Update DCB configuration from the Firmware and configure
11218 * LLDP MIB change event.
11220 if (sw_dcb == TRUE) {
11221 /* Stopping lldp is necessary for DPDK, but it will cause
11222 * DCB init failed. For i40e_init_dcb(), the prerequisite
11223 * for successful initialization of DCB is that LLDP is
11224 * enabled. So it is needed to start lldp before DCB init
11225 * and stop it after initialization.
11227 ret = i40e_aq_start_lldp(hw, true, NULL);
11228 if (ret != I40E_SUCCESS)
11229 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11231 ret = i40e_init_dcb(hw, true);
11232 /* If lldp agent is stopped, the return value from
11233 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11234 * adminq status. Otherwise, it should return success.
11236 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11237 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11238 memset(&hw->local_dcbx_config, 0,
11239 sizeof(struct i40e_dcbx_config));
11240 /* set dcb default configuration */
11241 hw->local_dcbx_config.etscfg.willing = 0;
11242 hw->local_dcbx_config.etscfg.maxtcs = 0;
11243 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11244 hw->local_dcbx_config.etscfg.tsatable[0] =
11246 /* all UPs mapping to TC0 */
11247 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11248 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11249 hw->local_dcbx_config.etsrec =
11250 hw->local_dcbx_config.etscfg;
11251 hw->local_dcbx_config.pfc.willing = 0;
11252 hw->local_dcbx_config.pfc.pfccap =
11253 I40E_MAX_TRAFFIC_CLASS;
11254 /* FW needs one App to configure HW */
11255 hw->local_dcbx_config.numapps = 1;
11256 hw->local_dcbx_config.app[0].selector =
11257 I40E_APP_SEL_ETHTYPE;
11258 hw->local_dcbx_config.app[0].priority = 3;
11259 hw->local_dcbx_config.app[0].protocolid =
11260 I40E_APP_PROTOID_FCOE;
11261 ret = i40e_set_dcb_config(hw);
11264 "default dcb config fails. err = %d, aq_err = %d.",
11265 ret, hw->aq.asq_last_status);
11270 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11271 ret, hw->aq.asq_last_status);
11275 if (i40e_need_stop_lldp(dev)) {
11276 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11277 if (ret != I40E_SUCCESS)
11278 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11281 ret = i40e_aq_start_lldp(hw, true, NULL);
11282 if (ret != I40E_SUCCESS)
11283 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11285 ret = i40e_init_dcb(hw, true);
11287 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11289 "HW doesn't support DCBX offload.");
11294 "DCBX configuration failed, err = %d, aq_err = %d.",
11295 ret, hw->aq.asq_last_status);
11303 * i40e_dcb_setup - setup dcb related config
11304 * @dev: device being configured
11306 * Returns 0 on success, negative value on failure
11309 i40e_dcb_setup(struct rte_eth_dev *dev)
11311 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11312 struct i40e_dcbx_config dcb_cfg;
11313 uint8_t tc_map = 0;
11316 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11317 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11321 if (pf->vf_num != 0)
11322 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11324 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11326 PMD_INIT_LOG(ERR, "invalid dcb config");
11329 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11331 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11339 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11340 struct rte_eth_dcb_info *dcb_info)
11342 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11344 struct i40e_vsi *vsi = pf->main_vsi;
11345 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11346 uint16_t bsf, tc_mapping;
11349 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11350 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11352 dcb_info->nb_tcs = 1;
11353 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11354 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11355 for (i = 0; i < dcb_info->nb_tcs; i++)
11356 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11358 /* get queue mapping if vmdq is disabled */
11359 if (!pf->nb_cfg_vmdq_vsi) {
11360 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11361 if (!(vsi->enabled_tc & (1 << i)))
11363 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11364 dcb_info->tc_queue.tc_rxq[j][i].base =
11365 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11366 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11367 dcb_info->tc_queue.tc_txq[j][i].base =
11368 dcb_info->tc_queue.tc_rxq[j][i].base;
11369 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11370 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11371 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11372 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11373 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11378 /* get queue mapping if vmdq is enabled */
11380 vsi = pf->vmdq[j].vsi;
11381 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11382 if (!(vsi->enabled_tc & (1 << i)))
11384 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11385 dcb_info->tc_queue.tc_rxq[j][i].base =
11386 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11387 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11388 dcb_info->tc_queue.tc_txq[j][i].base =
11389 dcb_info->tc_queue.tc_rxq[j][i].base;
11390 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11391 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11392 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11393 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11394 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11397 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11402 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11404 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11405 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11406 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11407 uint16_t msix_intr;
11409 msix_intr = intr_handle->intr_vec[queue_id];
11410 if (msix_intr == I40E_MISC_VEC_ID)
11411 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11412 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11413 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11414 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11417 I40E_PFINT_DYN_CTLN(msix_intr -
11418 I40E_RX_VEC_START),
11419 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11420 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11421 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11423 I40E_WRITE_FLUSH(hw);
11424 rte_intr_ack(&pci_dev->intr_handle);
11430 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11432 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11433 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11434 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11435 uint16_t msix_intr;
11437 msix_intr = intr_handle->intr_vec[queue_id];
11438 if (msix_intr == I40E_MISC_VEC_ID)
11439 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11440 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11443 I40E_PFINT_DYN_CTLN(msix_intr -
11444 I40E_RX_VEC_START),
11445 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11446 I40E_WRITE_FLUSH(hw);
11452 * This function is used to check if the register is valid.
11453 * Below is the valid registers list for X722 only:
11457 * 0x208e00--0x209000
11458 * 0x20be00--0x20c000
11459 * 0x263c00--0x264000
11460 * 0x265c00--0x266000
11462 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11464 if ((type != I40E_MAC_X722) &&
11465 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11466 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11467 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11468 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11469 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11470 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11471 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11477 static int i40e_get_regs(struct rte_eth_dev *dev,
11478 struct rte_dev_reg_info *regs)
11480 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11481 uint32_t *ptr_data = regs->data;
11482 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11483 const struct i40e_reg_info *reg_info;
11485 if (ptr_data == NULL) {
11486 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11487 regs->width = sizeof(uint32_t);
11491 /* The first few registers have to be read using AQ operations */
11493 while (i40e_regs_adminq[reg_idx].name) {
11494 reg_info = &i40e_regs_adminq[reg_idx++];
11495 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11497 arr_idx2 <= reg_info->count2;
11499 reg_offset = arr_idx * reg_info->stride1 +
11500 arr_idx2 * reg_info->stride2;
11501 reg_offset += reg_info->base_addr;
11502 ptr_data[reg_offset >> 2] =
11503 i40e_read_rx_ctl(hw, reg_offset);
11507 /* The remaining registers can be read using primitives */
11509 while (i40e_regs_others[reg_idx].name) {
11510 reg_info = &i40e_regs_others[reg_idx++];
11511 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11513 arr_idx2 <= reg_info->count2;
11515 reg_offset = arr_idx * reg_info->stride1 +
11516 arr_idx2 * reg_info->stride2;
11517 reg_offset += reg_info->base_addr;
11518 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11519 ptr_data[reg_offset >> 2] = 0;
11521 ptr_data[reg_offset >> 2] =
11522 I40E_READ_REG(hw, reg_offset);
11529 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11531 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11533 /* Convert word count to byte count */
11534 return hw->nvm.sr_size << 1;
11537 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11538 struct rte_dev_eeprom_info *eeprom)
11540 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11541 uint16_t *data = eeprom->data;
11542 uint16_t offset, length, cnt_words;
11545 offset = eeprom->offset >> 1;
11546 length = eeprom->length >> 1;
11547 cnt_words = length;
11549 if (offset > hw->nvm.sr_size ||
11550 offset + length > hw->nvm.sr_size) {
11551 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11555 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11557 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11558 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11559 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11566 static int i40e_get_module_info(struct rte_eth_dev *dev,
11567 struct rte_eth_dev_module_info *modinfo)
11569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11570 uint32_t sff8472_comp = 0;
11571 uint32_t sff8472_swap = 0;
11572 uint32_t sff8636_rev = 0;
11573 i40e_status status;
11576 /* Check if firmware supports reading module EEPROM. */
11577 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11579 "Module EEPROM memory read not supported. "
11580 "Please update the NVM image.\n");
11584 status = i40e_update_link_info(hw);
11588 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11590 "Cannot read module EEPROM memory. "
11591 "No module connected.\n");
11595 type = hw->phy.link_info.module_type[0];
11598 case I40E_MODULE_TYPE_SFP:
11599 status = i40e_aq_get_phy_register(hw,
11600 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11601 I40E_I2C_EEPROM_DEV_ADDR, 1,
11602 I40E_MODULE_SFF_8472_COMP,
11603 &sff8472_comp, NULL);
11607 status = i40e_aq_get_phy_register(hw,
11608 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11609 I40E_I2C_EEPROM_DEV_ADDR, 1,
11610 I40E_MODULE_SFF_8472_SWAP,
11611 &sff8472_swap, NULL);
11615 /* Check if the module requires address swap to access
11616 * the other EEPROM memory page.
11618 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11619 PMD_DRV_LOG(WARNING,
11620 "Module address swap to access "
11621 "page 0xA2 is not supported.\n");
11622 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11623 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11624 } else if (sff8472_comp == 0x00) {
11625 /* Module is not SFF-8472 compliant */
11626 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11627 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11629 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11630 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11633 case I40E_MODULE_TYPE_QSFP_PLUS:
11634 /* Read from memory page 0. */
11635 status = i40e_aq_get_phy_register(hw,
11636 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11638 I40E_MODULE_REVISION_ADDR,
11639 &sff8636_rev, NULL);
11642 /* Determine revision compliance byte */
11643 if (sff8636_rev > 0x02) {
11644 /* Module is SFF-8636 compliant */
11645 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11646 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11648 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11649 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11652 case I40E_MODULE_TYPE_QSFP28:
11653 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11654 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11657 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11663 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11664 struct rte_dev_eeprom_info *info)
11666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11667 bool is_sfp = false;
11668 i40e_status status;
11670 uint32_t value = 0;
11673 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11677 for (i = 0; i < info->length; i++) {
11678 u32 offset = i + info->offset;
11679 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11681 /* Check if we need to access the other memory page */
11683 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11684 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11685 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11688 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11689 /* Compute memory page number and offset. */
11690 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11694 status = i40e_aq_get_phy_register(hw,
11695 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11696 addr, 1, offset, &value, NULL);
11699 data[i] = (uint8_t)value;
11704 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11705 struct rte_ether_addr *mac_addr)
11707 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11709 struct i40e_vsi *vsi = pf->main_vsi;
11710 struct i40e_mac_filter_info mac_filter;
11711 struct i40e_mac_filter *f;
11714 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11715 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11719 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11720 if (rte_is_same_ether_addr(&pf->dev_addr,
11721 &f->mac_info.mac_addr))
11726 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11730 mac_filter = f->mac_info;
11731 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11732 if (ret != I40E_SUCCESS) {
11733 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11736 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11737 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11738 if (ret != I40E_SUCCESS) {
11739 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11742 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11744 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11745 mac_addr->addr_bytes, NULL);
11746 if (ret != I40E_SUCCESS) {
11747 PMD_DRV_LOG(ERR, "Failed to change mac");
11755 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11757 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11758 struct rte_eth_dev_data *dev_data = pf->dev_data;
11759 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11762 /* check if mtu is within the allowed range */
11763 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11766 /* mtu setting is forbidden if port is start */
11767 if (dev_data->dev_started) {
11768 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11769 dev_data->port_id);
11773 if (frame_size > I40E_ETH_MAX_LEN)
11774 dev_data->dev_conf.rxmode.offloads |=
11775 DEV_RX_OFFLOAD_JUMBO_FRAME;
11777 dev_data->dev_conf.rxmode.offloads &=
11778 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11780 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11785 /* Restore ethertype filter */
11787 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11789 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11790 struct i40e_ethertype_filter_list
11791 *ethertype_list = &pf->ethertype.ethertype_list;
11792 struct i40e_ethertype_filter *f;
11793 struct i40e_control_filter_stats stats;
11796 TAILQ_FOREACH(f, ethertype_list, rules) {
11798 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11799 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11800 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11801 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11802 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11804 memset(&stats, 0, sizeof(stats));
11805 i40e_aq_add_rem_control_packet_filter(hw,
11806 f->input.mac_addr.addr_bytes,
11807 f->input.ether_type,
11808 flags, pf->main_vsi->seid,
11809 f->queue, 1, &stats, NULL);
11811 PMD_DRV_LOG(INFO, "Ethertype filter:"
11812 " mac_etype_used = %u, etype_used = %u,"
11813 " mac_etype_free = %u, etype_free = %u",
11814 stats.mac_etype_used, stats.etype_used,
11815 stats.mac_etype_free, stats.etype_free);
11818 /* Restore tunnel filter */
11820 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11822 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11823 struct i40e_vsi *vsi;
11824 struct i40e_pf_vf *vf;
11825 struct i40e_tunnel_filter_list
11826 *tunnel_list = &pf->tunnel.tunnel_list;
11827 struct i40e_tunnel_filter *f;
11828 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11829 bool big_buffer = 0;
11831 TAILQ_FOREACH(f, tunnel_list, rules) {
11833 vsi = pf->main_vsi;
11835 vf = &pf->vfs[f->vf_id];
11838 memset(&cld_filter, 0, sizeof(cld_filter));
11839 rte_ether_addr_copy((struct rte_ether_addr *)
11840 &f->input.outer_mac,
11841 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11842 rte_ether_addr_copy((struct rte_ether_addr *)
11843 &f->input.inner_mac,
11844 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11845 cld_filter.element.inner_vlan = f->input.inner_vlan;
11846 cld_filter.element.flags = f->input.flags;
11847 cld_filter.element.tenant_id = f->input.tenant_id;
11848 cld_filter.element.queue_number = f->queue;
11849 rte_memcpy(cld_filter.general_fields,
11850 f->input.general_fields,
11851 sizeof(f->input.general_fields));
11853 if (((f->input.flags &
11854 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11855 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11857 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11858 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11860 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11861 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11865 i40e_aq_add_cloud_filters_bb(hw,
11866 vsi->seid, &cld_filter, 1);
11868 i40e_aq_add_cloud_filters(hw, vsi->seid,
11869 &cld_filter.element, 1);
11874 i40e_filter_restore(struct i40e_pf *pf)
11876 i40e_ethertype_filter_restore(pf);
11877 i40e_tunnel_filter_restore(pf);
11878 i40e_fdir_filter_restore(pf);
11879 (void)i40e_hash_filter_restore(pf);
11883 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11885 if (strcmp(dev->device->driver->name, drv->driver.name))
11892 is_i40e_supported(struct rte_eth_dev *dev)
11894 return is_device_supported(dev, &rte_i40e_pmd);
11897 struct i40e_customized_pctype*
11898 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11902 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11903 if (pf->customized_pctype[i].index == index)
11904 return &pf->customized_pctype[i];
11910 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11911 uint32_t pkg_size, uint32_t proto_num,
11912 struct rte_pmd_i40e_proto_info *proto,
11913 enum rte_pmd_i40e_package_op op)
11915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11916 uint32_t pctype_num;
11917 struct rte_pmd_i40e_ptype_info *pctype;
11918 uint32_t buff_size;
11919 struct i40e_customized_pctype *new_pctype = NULL;
11921 uint8_t pctype_value;
11926 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11927 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11928 PMD_DRV_LOG(ERR, "Unsupported operation.");
11932 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11933 (uint8_t *)&pctype_num, sizeof(pctype_num),
11934 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11936 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11940 PMD_DRV_LOG(INFO, "No new pctype added");
11944 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11945 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11947 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11950 /* get information about new pctype list */
11951 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11952 (uint8_t *)pctype, buff_size,
11953 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11955 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11960 /* Update customized pctype. */
11961 for (i = 0; i < pctype_num; i++) {
11962 pctype_value = pctype[i].ptype_id;
11963 memset(name, 0, sizeof(name));
11964 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11965 proto_id = pctype[i].protocols[j];
11966 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11968 for (n = 0; n < proto_num; n++) {
11969 if (proto[n].proto_id != proto_id)
11971 strlcat(name, proto[n].name, sizeof(name));
11972 strlcat(name, "_", sizeof(name));
11976 name[strlen(name) - 1] = '\0';
11977 PMD_DRV_LOG(INFO, "name = %s\n", name);
11978 if (!strcmp(name, "GTPC"))
11980 i40e_find_customized_pctype(pf,
11981 I40E_CUSTOMIZED_GTPC);
11982 else if (!strcmp(name, "GTPU_IPV4"))
11984 i40e_find_customized_pctype(pf,
11985 I40E_CUSTOMIZED_GTPU_IPV4);
11986 else if (!strcmp(name, "GTPU_IPV6"))
11988 i40e_find_customized_pctype(pf,
11989 I40E_CUSTOMIZED_GTPU_IPV6);
11990 else if (!strcmp(name, "GTPU"))
11992 i40e_find_customized_pctype(pf,
11993 I40E_CUSTOMIZED_GTPU);
11994 else if (!strcmp(name, "IPV4_L2TPV3"))
11996 i40e_find_customized_pctype(pf,
11997 I40E_CUSTOMIZED_IPV4_L2TPV3);
11998 else if (!strcmp(name, "IPV6_L2TPV3"))
12000 i40e_find_customized_pctype(pf,
12001 I40E_CUSTOMIZED_IPV6_L2TPV3);
12002 else if (!strcmp(name, "IPV4_ESP"))
12004 i40e_find_customized_pctype(pf,
12005 I40E_CUSTOMIZED_ESP_IPV4);
12006 else if (!strcmp(name, "IPV6_ESP"))
12008 i40e_find_customized_pctype(pf,
12009 I40E_CUSTOMIZED_ESP_IPV6);
12010 else if (!strcmp(name, "IPV4_UDP_ESP"))
12012 i40e_find_customized_pctype(pf,
12013 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12014 else if (!strcmp(name, "IPV6_UDP_ESP"))
12016 i40e_find_customized_pctype(pf,
12017 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12018 else if (!strcmp(name, "IPV4_AH"))
12020 i40e_find_customized_pctype(pf,
12021 I40E_CUSTOMIZED_AH_IPV4);
12022 else if (!strcmp(name, "IPV6_AH"))
12024 i40e_find_customized_pctype(pf,
12025 I40E_CUSTOMIZED_AH_IPV6);
12027 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12028 new_pctype->pctype = pctype_value;
12029 new_pctype->valid = true;
12031 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12032 new_pctype->valid = false;
12042 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12043 uint32_t pkg_size, uint32_t proto_num,
12044 struct rte_pmd_i40e_proto_info *proto,
12045 enum rte_pmd_i40e_package_op op)
12047 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12048 uint16_t port_id = dev->data->port_id;
12049 uint32_t ptype_num;
12050 struct rte_pmd_i40e_ptype_info *ptype;
12051 uint32_t buff_size;
12053 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12058 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12059 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12060 PMD_DRV_LOG(ERR, "Unsupported operation.");
12064 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12065 rte_pmd_i40e_ptype_mapping_reset(port_id);
12069 /* get information about new ptype num */
12070 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12071 (uint8_t *)&ptype_num, sizeof(ptype_num),
12072 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12074 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12078 PMD_DRV_LOG(INFO, "No new ptype added");
12082 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12083 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12085 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12089 /* get information about new ptype list */
12090 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12091 (uint8_t *)ptype, buff_size,
12092 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12094 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12099 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12100 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12101 if (!ptype_mapping) {
12102 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12107 /* Update ptype mapping table. */
12108 for (i = 0; i < ptype_num; i++) {
12109 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12110 ptype_mapping[i].sw_ptype = 0;
12112 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12113 proto_id = ptype[i].protocols[j];
12114 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12116 for (n = 0; n < proto_num; n++) {
12117 if (proto[n].proto_id != proto_id)
12119 memset(name, 0, sizeof(name));
12120 strcpy(name, proto[n].name);
12121 PMD_DRV_LOG(INFO, "name = %s\n", name);
12122 if (!strncasecmp(name, "PPPOE", 5))
12123 ptype_mapping[i].sw_ptype |=
12124 RTE_PTYPE_L2_ETHER_PPPOE;
12125 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12127 ptype_mapping[i].sw_ptype |=
12128 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12129 ptype_mapping[i].sw_ptype |=
12131 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12133 ptype_mapping[i].sw_ptype |=
12134 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12135 ptype_mapping[i].sw_ptype |=
12136 RTE_PTYPE_INNER_L4_FRAG;
12137 } else if (!strncasecmp(name, "OIPV4", 5)) {
12138 ptype_mapping[i].sw_ptype |=
12139 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12141 } else if (!strncasecmp(name, "IPV4", 4) &&
12143 ptype_mapping[i].sw_ptype |=
12144 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12145 else if (!strncasecmp(name, "IPV4", 4) &&
12147 ptype_mapping[i].sw_ptype |=
12148 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12149 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12151 ptype_mapping[i].sw_ptype |=
12152 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12153 ptype_mapping[i].sw_ptype |=
12155 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12157 ptype_mapping[i].sw_ptype |=
12158 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12159 ptype_mapping[i].sw_ptype |=
12160 RTE_PTYPE_INNER_L4_FRAG;
12161 } else if (!strncasecmp(name, "OIPV6", 5)) {
12162 ptype_mapping[i].sw_ptype |=
12163 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12165 } else if (!strncasecmp(name, "IPV6", 4) &&
12167 ptype_mapping[i].sw_ptype |=
12168 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12169 else if (!strncasecmp(name, "IPV6", 4) &&
12171 ptype_mapping[i].sw_ptype |=
12172 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12173 else if (!strncasecmp(name, "UDP", 3) &&
12175 ptype_mapping[i].sw_ptype |=
12177 else if (!strncasecmp(name, "UDP", 3) &&
12179 ptype_mapping[i].sw_ptype |=
12180 RTE_PTYPE_INNER_L4_UDP;
12181 else if (!strncasecmp(name, "TCP", 3) &&
12183 ptype_mapping[i].sw_ptype |=
12185 else if (!strncasecmp(name, "TCP", 3) &&
12187 ptype_mapping[i].sw_ptype |=
12188 RTE_PTYPE_INNER_L4_TCP;
12189 else if (!strncasecmp(name, "SCTP", 4) &&
12191 ptype_mapping[i].sw_ptype |=
12193 else if (!strncasecmp(name, "SCTP", 4) &&
12195 ptype_mapping[i].sw_ptype |=
12196 RTE_PTYPE_INNER_L4_SCTP;
12197 else if ((!strncasecmp(name, "ICMP", 4) ||
12198 !strncasecmp(name, "ICMPV6", 6)) &&
12200 ptype_mapping[i].sw_ptype |=
12202 else if ((!strncasecmp(name, "ICMP", 4) ||
12203 !strncasecmp(name, "ICMPV6", 6)) &&
12205 ptype_mapping[i].sw_ptype |=
12206 RTE_PTYPE_INNER_L4_ICMP;
12207 else if (!strncasecmp(name, "GTPC", 4)) {
12208 ptype_mapping[i].sw_ptype |=
12209 RTE_PTYPE_TUNNEL_GTPC;
12211 } else if (!strncasecmp(name, "GTPU", 4)) {
12212 ptype_mapping[i].sw_ptype |=
12213 RTE_PTYPE_TUNNEL_GTPU;
12215 } else if (!strncasecmp(name, "ESP", 3)) {
12216 ptype_mapping[i].sw_ptype |=
12217 RTE_PTYPE_TUNNEL_ESP;
12219 } else if (!strncasecmp(name, "GRENAT", 6)) {
12220 ptype_mapping[i].sw_ptype |=
12221 RTE_PTYPE_TUNNEL_GRENAT;
12223 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12224 !strncasecmp(name, "L2TPV2", 6) ||
12225 !strncasecmp(name, "L2TPV3", 6)) {
12226 ptype_mapping[i].sw_ptype |=
12227 RTE_PTYPE_TUNNEL_L2TP;
12236 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12239 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12241 rte_free(ptype_mapping);
12247 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12248 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12250 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12251 uint32_t proto_num;
12252 struct rte_pmd_i40e_proto_info *proto;
12253 uint32_t buff_size;
12257 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12258 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12259 PMD_DRV_LOG(ERR, "Unsupported operation.");
12263 /* get information about protocol number */
12264 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12265 (uint8_t *)&proto_num, sizeof(proto_num),
12266 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12268 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12272 PMD_DRV_LOG(INFO, "No new protocol added");
12276 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12277 proto = rte_zmalloc("new_proto", buff_size, 0);
12279 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12283 /* get information about protocol list */
12284 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12285 (uint8_t *)proto, buff_size,
12286 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12288 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12293 /* Check if GTP is supported. */
12294 for (i = 0; i < proto_num; i++) {
12295 if (!strncmp(proto[i].name, "GTP", 3)) {
12296 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12297 pf->gtp_support = true;
12299 pf->gtp_support = false;
12304 /* Check if ESP is supported. */
12305 for (i = 0; i < proto_num; i++) {
12306 if (!strncmp(proto[i].name, "ESP", 3)) {
12307 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12308 pf->esp_support = true;
12310 pf->esp_support = false;
12315 /* Update customized pctype info */
12316 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12317 proto_num, proto, op);
12319 PMD_DRV_LOG(INFO, "No pctype is updated.");
12321 /* Update customized ptype info */
12322 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12323 proto_num, proto, op);
12325 PMD_DRV_LOG(INFO, "No ptype is updated.");
12330 /* Create a QinQ cloud filter
12332 * The Fortville NIC has limited resources for tunnel filters,
12333 * so we can only reuse existing filters.
12335 * In step 1 we define which Field Vector fields can be used for
12337 * As we do not have the inner tag defined as a field,
12338 * we have to define it first, by reusing one of L1 entries.
12340 * In step 2 we are replacing one of existing filter types with
12341 * a new one for QinQ.
12342 * As we reusing L1 and replacing L2, some of the default filter
12343 * types will disappear,which depends on L1 and L2 entries we reuse.
12345 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12347 * 1. Create L1 filter of outer vlan (12b) which will be in use
12348 * later when we define the cloud filter.
12349 * a. Valid_flags.replace_cloud = 0
12350 * b. Old_filter = 10 (Stag_Inner_Vlan)
12351 * c. New_filter = 0x10
12352 * d. TR bit = 0xff (optional, not used here)
12353 * e. Buffer – 2 entries:
12354 * i. Byte 0 = 8 (outer vlan FV index).
12356 * Byte 2-3 = 0x0fff
12357 * ii. Byte 0 = 37 (inner vlan FV index).
12359 * Byte 2-3 = 0x0fff
12362 * 2. Create cloud filter using two L1 filters entries: stag and
12363 * new filter(outer vlan+ inner vlan)
12364 * a. Valid_flags.replace_cloud = 1
12365 * b. Old_filter = 1 (instead of outer IP)
12366 * c. New_filter = 0x10
12367 * d. Buffer – 2 entries:
12368 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12369 * Byte 1-3 = 0 (rsv)
12370 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12371 * Byte 9-11 = 0 (rsv)
12374 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12376 int ret = -ENOTSUP;
12377 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12378 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12379 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12380 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
12382 if (pf->support_multi_driver) {
12383 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12388 memset(&filter_replace, 0,
12389 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12390 memset(&filter_replace_buf, 0,
12391 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12393 /* create L1 filter */
12394 filter_replace.old_filter_type =
12395 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12396 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12397 filter_replace.tr_bit = 0;
12399 /* Prepare the buffer, 2 entries */
12400 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12401 filter_replace_buf.data[0] |=
12402 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12403 /* Field Vector 12b mask */
12404 filter_replace_buf.data[2] = 0xff;
12405 filter_replace_buf.data[3] = 0x0f;
12406 filter_replace_buf.data[4] =
12407 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12408 filter_replace_buf.data[4] |=
12409 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12410 /* Field Vector 12b mask */
12411 filter_replace_buf.data[6] = 0xff;
12412 filter_replace_buf.data[7] = 0x0f;
12413 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12414 &filter_replace_buf);
12415 if (ret != I40E_SUCCESS)
12418 if (filter_replace.old_filter_type !=
12419 filter_replace.new_filter_type)
12420 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12421 " original: 0x%x, new: 0x%x",
12423 filter_replace.old_filter_type,
12424 filter_replace.new_filter_type);
12426 /* Apply the second L2 cloud filter */
12427 memset(&filter_replace, 0,
12428 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12429 memset(&filter_replace_buf, 0,
12430 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12432 /* create L2 filter, input for L2 filter will be L1 filter */
12433 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12434 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12435 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12437 /* Prepare the buffer, 2 entries */
12438 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12439 filter_replace_buf.data[0] |=
12440 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12441 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12442 filter_replace_buf.data[4] |=
12443 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12444 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12445 &filter_replace_buf);
12446 if (!ret && (filter_replace.old_filter_type !=
12447 filter_replace.new_filter_type))
12448 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12449 " original: 0x%x, new: 0x%x",
12451 filter_replace.old_filter_type,
12452 filter_replace.new_filter_type);
12457 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12458 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12459 #ifdef RTE_ETHDEV_DEBUG_RX
12460 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12462 #ifdef RTE_ETHDEV_DEBUG_TX
12463 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12466 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12467 ETH_I40E_FLOATING_VEB_ARG "=1"
12468 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12469 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12470 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");