4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int i40e_dev_configure(struct rte_eth_dev *dev);
249 static int i40e_dev_start(struct rte_eth_dev *dev);
250 static void i40e_dev_stop(struct rte_eth_dev *dev);
251 static void i40e_dev_close(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
261 struct rte_eth_xstat *xstats, unsigned n);
262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
263 struct rte_eth_xstat_name *xstats_names,
265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
271 char *fw_version, size_t fw_size);
272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
273 struct rte_eth_dev_info *dev_info);
274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
278 enum rte_vlan_type vlan_type,
280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
288 struct rte_eth_fc_conf *fc_conf);
289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_pfc_conf *pfc_conf);
293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
305 static int i40e_get_cap(struct i40e_hw *hw);
306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
307 static int i40e_pf_setup(struct i40e_pf *pf);
308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
313 bool offset_loaded, uint64_t *offset, uint64_t *stat);
314 static void i40e_stat_update_48(struct i40e_hw *hw,
320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
339 struct ether_addr *addr);
340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
341 struct i40e_macvlan_filter *mv_f,
344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
348 struct rte_eth_rss_conf *rss_conf);
349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
352 struct rte_eth_udp_tunnel *udp_tunnel);
353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
358 enum rte_filter_type filter_type,
359 enum rte_filter_op filter_op,
361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
362 struct rte_eth_dcb_info *dcb_info);
363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
364 static void i40e_configure_registers(struct i40e_hw *hw);
365 static void i40e_hw_init(struct rte_eth_dev *dev);
366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
368 struct rte_eth_mirror_conf *mirror_conf,
369 uint8_t sw_id, uint8_t on);
370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp,
377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp);
379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
384 struct timespec *timestamp);
385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
386 const struct timespec *timestamp);
388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
393 static int i40e_get_regs(struct rte_eth_dev *dev,
394 struct rte_dev_reg_info *regs);
396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
399 struct rte_dev_eeprom_info *eeprom);
401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
402 struct ether_addr *mac_addr);
404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
406 static int i40e_ethertype_filter_convert(
407 const struct rte_eth_ethertype_filter *input,
408 struct i40e_ethertype_filter *filter);
409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
410 struct i40e_ethertype_filter *filter);
412 static int i40e_tunnel_filter_convert(
413 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
414 struct i40e_tunnel_filter *tunnel_filter);
415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
416 struct i40e_tunnel_filter *tunnel_filter);
418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
420 static void i40e_filter_restore(struct i40e_pf *pf);
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .promiscuous_enable = i40e_dev_promiscuous_enable,
452 .promiscuous_disable = i40e_dev_promiscuous_disable,
453 .allmulticast_enable = i40e_dev_allmulticast_enable,
454 .allmulticast_disable = i40e_dev_allmulticast_disable,
455 .dev_set_link_up = i40e_dev_set_link_up,
456 .dev_set_link_down = i40e_dev_set_link_down,
457 .link_update = i40e_dev_link_update,
458 .stats_get = i40e_dev_stats_get,
459 .xstats_get = i40e_dev_xstats_get,
460 .xstats_get_names = i40e_dev_xstats_get_names,
461 .stats_reset = i40e_dev_stats_reset,
462 .xstats_reset = i40e_dev_stats_reset,
463 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
464 .fw_version_get = i40e_fw_version_get,
465 .dev_infos_get = i40e_dev_info_get,
466 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
467 .vlan_filter_set = i40e_vlan_filter_set,
468 .vlan_tpid_set = i40e_vlan_tpid_set,
469 .vlan_offload_set = i40e_vlan_offload_set,
470 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
471 .vlan_pvid_set = i40e_vlan_pvid_set,
472 .rx_queue_start = i40e_dev_rx_queue_start,
473 .rx_queue_stop = i40e_dev_rx_queue_stop,
474 .tx_queue_start = i40e_dev_tx_queue_start,
475 .tx_queue_stop = i40e_dev_tx_queue_stop,
476 .rx_queue_setup = i40e_dev_rx_queue_setup,
477 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
478 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
479 .rx_queue_release = i40e_dev_rx_queue_release,
480 .rx_queue_count = i40e_dev_rx_queue_count,
481 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
482 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
483 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
484 .tx_queue_setup = i40e_dev_tx_queue_setup,
485 .tx_queue_release = i40e_dev_tx_queue_release,
486 .dev_led_on = i40e_dev_led_on,
487 .dev_led_off = i40e_dev_led_off,
488 .flow_ctrl_get = i40e_flow_ctrl_get,
489 .flow_ctrl_set = i40e_flow_ctrl_set,
490 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
491 .mac_addr_add = i40e_macaddr_add,
492 .mac_addr_remove = i40e_macaddr_remove,
493 .reta_update = i40e_dev_rss_reta_update,
494 .reta_query = i40e_dev_rss_reta_query,
495 .rss_hash_update = i40e_dev_rss_hash_update,
496 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
497 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
498 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
499 .filter_ctrl = i40e_dev_filter_ctrl,
500 .rxq_info_get = i40e_rxq_info_get,
501 .txq_info_get = i40e_txq_info_get,
502 .mirror_rule_set = i40e_mirror_rule_set,
503 .mirror_rule_reset = i40e_mirror_rule_reset,
504 .timesync_enable = i40e_timesync_enable,
505 .timesync_disable = i40e_timesync_disable,
506 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
507 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
508 .get_dcb_info = i40e_dev_get_dcb_info,
509 .timesync_adjust_time = i40e_timesync_adjust_time,
510 .timesync_read_time = i40e_timesync_read_time,
511 .timesync_write_time = i40e_timesync_write_time,
512 .get_reg = i40e_get_regs,
513 .get_eeprom_length = i40e_get_eeprom_length,
514 .get_eeprom = i40e_get_eeprom,
515 .mac_addr_set = i40e_set_default_mac_addr,
516 .mtu_set = i40e_dev_mtu_set,
519 /* store statistics names and its offset in stats structure */
520 struct rte_i40e_xstats_name_off {
521 char name[RTE_ETH_XSTATS_NAME_SIZE];
525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
526 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
527 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
528 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
529 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
530 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
531 rx_unknown_protocol)},
532 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
533 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
534 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
535 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
539 sizeof(rte_i40e_stats_strings[0]))
541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
542 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
543 tx_dropped_link_down)},
544 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
545 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
548 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
550 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
554 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
555 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
556 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
557 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
558 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
559 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
575 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
576 mac_short_packet_dropped)},
577 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
580 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
581 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_flow_director_atr_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
595 {"rx_flow_director_sb_match_packets",
596 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
597 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
601 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
603 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
608 sizeof(rte_i40e_hw_port_strings[0]))
610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
611 {"xon_packets", offsetof(struct i40e_hw_port_stats,
613 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
618 sizeof(rte_i40e_rxq_prio_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
625 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
626 priority_xon_2_xoff)},
629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
630 sizeof(rte_i40e_txq_prio_strings[0]))
632 static struct eth_driver rte_i40e_pmd = {
634 .id_table = pci_id_i40e_map,
635 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
636 .probe = rte_eth_dev_pci_probe,
637 .remove = rte_eth_dev_pci_remove,
639 .eth_dev_init = eth_i40e_dev_init,
640 .eth_dev_uninit = eth_i40e_dev_uninit,
641 .dev_private_size = sizeof(struct i40e_adapter),
645 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
646 struct rte_eth_link *link)
648 struct rte_eth_link *dst = link;
649 struct rte_eth_link *src = &(dev->data->dev_link);
651 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
652 *(uint64_t *)src) == 0)
659 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
660 struct rte_eth_link *link)
662 struct rte_eth_link *dst = &(dev->data->dev_link);
663 struct rte_eth_link *src = link;
665 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
666 *(uint64_t *)src) == 0)
672 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
673 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
674 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
676 #ifndef I40E_GLQF_ORT
677 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
679 #ifndef I40E_GLQF_PIT
680 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
683 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
686 * Initialize registers for flexible payload, which should be set by NVM.
687 * This should be removed from code once it is fixed in NVM.
689 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
690 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
691 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
692 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
693 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
694 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
695 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
696 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
697 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
698 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
699 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
700 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
702 /* Initialize registers for parsing packet type of QinQ */
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
704 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
707 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
710 * Add a ethertype filter to drop all flow control frames transmitted
714 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
716 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
717 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
718 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
719 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
722 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
723 I40E_FLOW_CONTROL_ETHERTYPE, flags,
724 pf->main_vsi_seid, 0,
728 "Failed to add filter to drop flow control frames from VSIs.");
732 floating_veb_list_handler(__rte_unused const char *key,
733 const char *floating_veb_value,
737 unsigned int count = 0;
740 bool *vf_floating_veb = opaque;
742 while (isblank(*floating_veb_value))
743 floating_veb_value++;
745 /* Reset floating VEB configuration for VFs */
746 for (idx = 0; idx < I40E_MAX_VF; idx++)
747 vf_floating_veb[idx] = false;
751 while (isblank(*floating_veb_value))
752 floating_veb_value++;
753 if (*floating_veb_value == '\0')
756 idx = strtoul(floating_veb_value, &end, 10);
757 if (errno || end == NULL)
759 while (isblank(*end))
763 } else if ((*end == ';') || (*end == '\0')) {
765 if (min == I40E_MAX_VF)
767 if (max >= I40E_MAX_VF)
768 max = I40E_MAX_VF - 1;
769 for (idx = min; idx <= max; idx++) {
770 vf_floating_veb[idx] = true;
777 floating_veb_value = end + 1;
778 } while (*end != '\0');
787 config_vf_floating_veb(struct rte_devargs *devargs,
788 uint16_t floating_veb,
789 bool *vf_floating_veb)
791 struct rte_kvargs *kvlist;
793 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
797 /* All the VFs attach to the floating VEB by default
798 * when the floating VEB is enabled.
800 for (i = 0; i < I40E_MAX_VF; i++)
801 vf_floating_veb[i] = true;
806 kvlist = rte_kvargs_parse(devargs->args, NULL);
810 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
811 rte_kvargs_free(kvlist);
814 /* When the floating_veb_list parameter exists, all the VFs
815 * will attach to the legacy VEB firstly, then configure VFs
816 * to the floating VEB according to the floating_veb_list.
818 if (rte_kvargs_process(kvlist, floating_veb_list,
819 floating_veb_list_handler,
820 vf_floating_veb) < 0) {
821 rte_kvargs_free(kvlist);
824 rte_kvargs_free(kvlist);
828 i40e_check_floating_handler(__rte_unused const char *key,
830 __rte_unused void *opaque)
832 if (strcmp(value, "1"))
839 is_floating_veb_supported(struct rte_devargs *devargs)
841 struct rte_kvargs *kvlist;
842 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
847 kvlist = rte_kvargs_parse(devargs->args, NULL);
851 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
852 rte_kvargs_free(kvlist);
855 /* Floating VEB is enabled when there's key-value:
856 * enable_floating_veb=1
858 if (rte_kvargs_process(kvlist, floating_veb_key,
859 i40e_check_floating_handler, NULL) < 0) {
860 rte_kvargs_free(kvlist);
863 rte_kvargs_free(kvlist);
869 config_floating_veb(struct rte_eth_dev *dev)
871 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
872 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
873 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
877 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
879 is_floating_veb_supported(pci_dev->device.devargs);
880 config_vf_floating_veb(pci_dev->device.devargs,
882 pf->floating_veb_list);
884 pf->floating_veb = false;
888 #define I40E_L2_TAGS_S_TAG_SHIFT 1
889 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
892 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
894 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
895 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
896 char ethertype_hash_name[RTE_HASH_NAMESIZE];
899 struct rte_hash_parameters ethertype_hash_params = {
900 .name = ethertype_hash_name,
901 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
902 .key_len = sizeof(struct i40e_ethertype_filter_input),
903 .hash_func = rte_hash_crc,
904 .hash_func_init_val = 0,
905 .socket_id = rte_socket_id(),
908 /* Initialize ethertype filter rule list and hash */
909 TAILQ_INIT(ðertype_rule->ethertype_list);
910 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
911 "ethertype_%s", dev->data->name);
912 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
913 if (!ethertype_rule->hash_table) {
914 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
917 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
918 sizeof(struct i40e_ethertype_filter *) *
919 I40E_MAX_ETHERTYPE_FILTER_NUM,
921 if (!ethertype_rule->hash_map) {
923 "Failed to allocate memory for ethertype hash map!");
925 goto err_ethertype_hash_map_alloc;
930 err_ethertype_hash_map_alloc:
931 rte_hash_free(ethertype_rule->hash_table);
937 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
940 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
941 char tunnel_hash_name[RTE_HASH_NAMESIZE];
944 struct rte_hash_parameters tunnel_hash_params = {
945 .name = tunnel_hash_name,
946 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
947 .key_len = sizeof(struct i40e_tunnel_filter_input),
948 .hash_func = rte_hash_crc,
949 .hash_func_init_val = 0,
950 .socket_id = rte_socket_id(),
953 /* Initialize tunnel filter rule list and hash */
954 TAILQ_INIT(&tunnel_rule->tunnel_list);
955 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
956 "tunnel_%s", dev->data->name);
957 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
958 if (!tunnel_rule->hash_table) {
959 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
962 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
963 sizeof(struct i40e_tunnel_filter *) *
964 I40E_MAX_TUNNEL_FILTER_NUM,
966 if (!tunnel_rule->hash_map) {
968 "Failed to allocate memory for tunnel hash map!");
970 goto err_tunnel_hash_map_alloc;
975 err_tunnel_hash_map_alloc:
976 rte_hash_free(tunnel_rule->hash_table);
982 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
984 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
985 struct i40e_fdir_info *fdir_info = &pf->fdir;
986 char fdir_hash_name[RTE_HASH_NAMESIZE];
989 struct rte_hash_parameters fdir_hash_params = {
990 .name = fdir_hash_name,
991 .entries = I40E_MAX_FDIR_FILTER_NUM,
992 .key_len = sizeof(struct rte_eth_fdir_input),
993 .hash_func = rte_hash_crc,
994 .hash_func_init_val = 0,
995 .socket_id = rte_socket_id(),
998 /* Initialize flow director filter rule list and hash */
999 TAILQ_INIT(&fdir_info->fdir_list);
1000 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1001 "fdir_%s", dev->data->name);
1002 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1003 if (!fdir_info->hash_table) {
1004 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1007 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1008 sizeof(struct i40e_fdir_filter *) *
1009 I40E_MAX_FDIR_FILTER_NUM,
1011 if (!fdir_info->hash_map) {
1013 "Failed to allocate memory for fdir hash map!");
1015 goto err_fdir_hash_map_alloc;
1019 err_fdir_hash_map_alloc:
1020 rte_hash_free(fdir_info->hash_table);
1026 eth_i40e_dev_init(struct rte_eth_dev *dev)
1028 struct rte_pci_device *pci_dev;
1029 struct rte_intr_handle *intr_handle;
1030 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032 struct i40e_vsi *vsi;
1035 uint8_t aq_fail = 0;
1037 PMD_INIT_FUNC_TRACE();
1039 dev->dev_ops = &i40e_eth_dev_ops;
1040 dev->rx_pkt_burst = i40e_recv_pkts;
1041 dev->tx_pkt_burst = i40e_xmit_pkts;
1042 dev->tx_pkt_prepare = i40e_prep_pkts;
1044 /* for secondary processes, we don't initialise any further as primary
1045 * has already done this work. Only check we don't need a different
1047 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1048 i40e_set_rx_function(dev);
1049 i40e_set_tx_function(dev);
1052 pci_dev = I40E_DEV_TO_PCI(dev);
1053 intr_handle = &pci_dev->intr_handle;
1055 rte_eth_copy_pci_info(dev, pci_dev);
1056 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1058 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1059 pf->adapter->eth_dev = dev;
1060 pf->dev_data = dev->data;
1062 hw->back = I40E_PF_TO_ADAPTER(pf);
1063 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1066 "Hardware is not available, as address is NULL");
1070 hw->vendor_id = pci_dev->id.vendor_id;
1071 hw->device_id = pci_dev->id.device_id;
1072 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1073 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1074 hw->bus.device = pci_dev->addr.devid;
1075 hw->bus.func = pci_dev->addr.function;
1076 hw->adapter_stopped = 0;
1078 /* Make sure all is clean before doing PF reset */
1081 /* Initialize the hardware */
1084 /* Reset here to make sure all is clean for each PF */
1085 ret = i40e_pf_reset(hw);
1087 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1091 /* Initialize the shared code (base driver) */
1092 ret = i40e_init_shared_code(hw);
1094 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1099 * To work around the NVM issue, initialize registers
1100 * for flexible payload and packet type of QinQ by
1101 * software. It should be removed once issues are fixed
1104 i40e_GLQF_reg_init(hw);
1106 /* Initialize the input set for filters (hash and fd) to default value */
1107 i40e_filter_input_set_init(pf);
1109 /* Initialize the parameters for adminq */
1110 i40e_init_adminq_parameter(hw);
1111 ret = i40e_init_adminq(hw);
1112 if (ret != I40E_SUCCESS) {
1113 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1116 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1117 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1118 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1119 ((hw->nvm.version >> 12) & 0xf),
1120 ((hw->nvm.version >> 4) & 0xff),
1121 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1123 /* Need the special FW version to support floating VEB */
1124 config_floating_veb(dev);
1125 /* Clear PXE mode */
1126 i40e_clear_pxe_mode(hw);
1127 ret = i40e_dev_sync_phy_type(hw);
1129 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1130 goto err_sync_phy_type;
1133 * On X710, performance number is far from the expectation on recent
1134 * firmware versions. The fix for this issue may not be integrated in
1135 * the following firmware version. So the workaround in software driver
1136 * is needed. It needs to modify the initial values of 3 internal only
1137 * registers. Note that the workaround can be removed when it is fixed
1138 * in firmware in the future.
1140 i40e_configure_registers(hw);
1142 /* Get hw capabilities */
1143 ret = i40e_get_cap(hw);
1144 if (ret != I40E_SUCCESS) {
1145 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1146 goto err_get_capabilities;
1149 /* Initialize parameters for PF */
1150 ret = i40e_pf_parameter_init(dev);
1152 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1153 goto err_parameter_init;
1156 /* Initialize the queue management */
1157 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1159 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1160 goto err_qp_pool_init;
1162 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1163 hw->func_caps.num_msix_vectors - 1);
1165 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1166 goto err_msix_pool_init;
1169 /* Initialize lan hmc */
1170 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1171 hw->func_caps.num_rx_qp, 0, 0);
1172 if (ret != I40E_SUCCESS) {
1173 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1174 goto err_init_lan_hmc;
1177 /* Configure lan hmc */
1178 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1179 if (ret != I40E_SUCCESS) {
1180 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1181 goto err_configure_lan_hmc;
1184 /* Get and check the mac address */
1185 i40e_get_mac_addr(hw, hw->mac.addr);
1186 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1187 PMD_INIT_LOG(ERR, "mac address is not valid");
1189 goto err_get_mac_addr;
1191 /* Copy the permanent MAC address */
1192 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1193 (struct ether_addr *) hw->mac.perm_addr);
1195 /* Disable flow control */
1196 hw->fc.requested_mode = I40E_FC_NONE;
1197 i40e_set_fc(hw, &aq_fail, TRUE);
1199 /* Set the global registers with default ether type value */
1200 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1201 if (ret != I40E_SUCCESS) {
1203 "Failed to set the default outer VLAN ether type");
1204 goto err_setup_pf_switch;
1207 /* PF setup, which includes VSI setup */
1208 ret = i40e_pf_setup(pf);
1210 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1211 goto err_setup_pf_switch;
1214 /* reset all stats of the device, including pf and main vsi */
1215 i40e_dev_stats_reset(dev);
1219 /* Disable double vlan by default */
1220 i40e_vsi_config_double_vlan(vsi, FALSE);
1222 /* Disable S-TAG identification when floating_veb is disabled */
1223 if (!pf->floating_veb) {
1224 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1225 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1226 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1227 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1231 if (!vsi->max_macaddrs)
1232 len = ETHER_ADDR_LEN;
1234 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1236 /* Should be after VSI initialized */
1237 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1238 if (!dev->data->mac_addrs) {
1240 "Failed to allocated memory for storing mac address");
1243 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1244 &dev->data->mac_addrs[0]);
1246 /* Init dcb to sw mode by default */
1247 ret = i40e_dcb_init_configure(dev, TRUE);
1248 if (ret != I40E_SUCCESS) {
1249 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1250 pf->flags &= ~I40E_FLAG_DCB;
1252 /* Update HW struct after DCB configuration */
1255 /* initialize pf host driver to setup SRIOV resource if applicable */
1256 i40e_pf_host_init(dev);
1258 /* register callback func to eal lib */
1259 rte_intr_callback_register(intr_handle,
1260 i40e_dev_interrupt_handler, dev);
1262 /* configure and enable device interrupt */
1263 i40e_pf_config_irq0(hw, TRUE);
1264 i40e_pf_enable_irq0(hw);
1266 /* enable uio intr after callback register */
1267 rte_intr_enable(intr_handle);
1269 * Add an ethertype filter to drop all flow control frames transmitted
1270 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1273 i40e_add_tx_flow_control_drop_filter(pf);
1275 /* Set the max frame size to 0x2600 by default,
1276 * in case other drivers changed the default value.
1278 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1280 /* initialize mirror rule list */
1281 TAILQ_INIT(&pf->mirror_list);
1283 ret = i40e_init_ethtype_filter_list(dev);
1285 goto err_init_ethtype_filter_list;
1286 ret = i40e_init_tunnel_filter_list(dev);
1288 goto err_init_tunnel_filter_list;
1289 ret = i40e_init_fdir_filter_list(dev);
1291 goto err_init_fdir_filter_list;
1295 err_init_fdir_filter_list:
1296 rte_free(pf->tunnel.hash_table);
1297 rte_free(pf->tunnel.hash_map);
1298 err_init_tunnel_filter_list:
1299 rte_free(pf->ethertype.hash_table);
1300 rte_free(pf->ethertype.hash_map);
1301 err_init_ethtype_filter_list:
1302 rte_free(dev->data->mac_addrs);
1304 i40e_vsi_release(pf->main_vsi);
1305 err_setup_pf_switch:
1307 err_configure_lan_hmc:
1308 (void)i40e_shutdown_lan_hmc(hw);
1310 i40e_res_pool_destroy(&pf->msix_pool);
1312 i40e_res_pool_destroy(&pf->qp_pool);
1315 err_get_capabilities:
1317 (void)i40e_shutdown_adminq(hw);
1323 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1325 struct i40e_ethertype_filter *p_ethertype;
1326 struct i40e_ethertype_rule *ethertype_rule;
1328 ethertype_rule = &pf->ethertype;
1329 /* Remove all ethertype filter rules and hash */
1330 if (ethertype_rule->hash_map)
1331 rte_free(ethertype_rule->hash_map);
1332 if (ethertype_rule->hash_table)
1333 rte_hash_free(ethertype_rule->hash_table);
1335 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1336 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1337 p_ethertype, rules);
1338 rte_free(p_ethertype);
1343 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1345 struct i40e_tunnel_filter *p_tunnel;
1346 struct i40e_tunnel_rule *tunnel_rule;
1348 tunnel_rule = &pf->tunnel;
1349 /* Remove all tunnel director rules and hash */
1350 if (tunnel_rule->hash_map)
1351 rte_free(tunnel_rule->hash_map);
1352 if (tunnel_rule->hash_table)
1353 rte_hash_free(tunnel_rule->hash_table);
1355 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1356 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1362 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1364 struct i40e_fdir_filter *p_fdir;
1365 struct i40e_fdir_info *fdir_info;
1367 fdir_info = &pf->fdir;
1368 /* Remove all flow director rules and hash */
1369 if (fdir_info->hash_map)
1370 rte_free(fdir_info->hash_map);
1371 if (fdir_info->hash_table)
1372 rte_hash_free(fdir_info->hash_table);
1374 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1375 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1381 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1384 struct rte_pci_device *pci_dev;
1385 struct rte_intr_handle *intr_handle;
1387 struct i40e_filter_control_settings settings;
1388 struct rte_flow *p_flow;
1390 uint8_t aq_fail = 0;
1392 PMD_INIT_FUNC_TRACE();
1394 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1397 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1398 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1399 pci_dev = I40E_DEV_TO_PCI(dev);
1400 intr_handle = &pci_dev->intr_handle;
1402 if (hw->adapter_stopped == 0)
1403 i40e_dev_close(dev);
1405 dev->dev_ops = NULL;
1406 dev->rx_pkt_burst = NULL;
1407 dev->tx_pkt_burst = NULL;
1409 /* Clear PXE mode */
1410 i40e_clear_pxe_mode(hw);
1412 /* Unconfigure filter control */
1413 memset(&settings, 0, sizeof(settings));
1414 ret = i40e_set_filter_control(hw, &settings);
1416 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1419 /* Disable flow control */
1420 hw->fc.requested_mode = I40E_FC_NONE;
1421 i40e_set_fc(hw, &aq_fail, TRUE);
1423 /* uninitialize pf host driver */
1424 i40e_pf_host_uninit(dev);
1426 rte_free(dev->data->mac_addrs);
1427 dev->data->mac_addrs = NULL;
1429 /* disable uio intr before callback unregister */
1430 rte_intr_disable(intr_handle);
1432 /* register callback func to eal lib */
1433 rte_intr_callback_unregister(intr_handle,
1434 i40e_dev_interrupt_handler, dev);
1436 i40e_rm_ethtype_filter_list(pf);
1437 i40e_rm_tunnel_filter_list(pf);
1438 i40e_rm_fdir_filter_list(pf);
1440 /* Remove all flows */
1441 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1442 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1450 i40e_dev_configure(struct rte_eth_dev *dev)
1452 struct i40e_adapter *ad =
1453 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1454 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1455 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1458 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1459 * bulk allocation or vector Rx preconditions we will reset it.
1461 ad->rx_bulk_alloc_allowed = true;
1462 ad->rx_vec_allowed = true;
1463 ad->tx_simple_allowed = true;
1464 ad->tx_vec_allowed = true;
1466 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1467 ret = i40e_fdir_setup(pf);
1468 if (ret != I40E_SUCCESS) {
1469 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1472 ret = i40e_fdir_configure(dev);
1474 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1478 i40e_fdir_teardown(pf);
1480 ret = i40e_dev_init_vlan(dev);
1485 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1486 * RSS setting have different requirements.
1487 * General PMD driver call sequence are NIC init, configure,
1488 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1489 * will try to lookup the VSI that specific queue belongs to if VMDQ
1490 * applicable. So, VMDQ setting has to be done before
1491 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1492 * For RSS setting, it will try to calculate actual configured RX queue
1493 * number, which will be available after rx_queue_setup(). dev_start()
1494 * function is good to place RSS setup.
1496 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1497 ret = i40e_vmdq_setup(dev);
1502 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1503 ret = i40e_dcb_setup(dev);
1505 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1510 TAILQ_INIT(&pf->flow_list);
1515 /* need to release vmdq resource if exists */
1516 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1517 i40e_vsi_release(pf->vmdq[i].vsi);
1518 pf->vmdq[i].vsi = NULL;
1523 /* need to release fdir resource if exists */
1524 i40e_fdir_teardown(pf);
1529 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1531 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1532 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1533 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1534 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1535 uint16_t msix_vect = vsi->msix_intr;
1538 for (i = 0; i < vsi->nb_qps; i++) {
1539 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1540 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1544 if (vsi->type != I40E_VSI_SRIOV) {
1545 if (!rte_intr_allow_others(intr_handle)) {
1546 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1547 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1549 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1552 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1553 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1555 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1560 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1561 vsi->user_param + (msix_vect - 1);
1563 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1564 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1566 I40E_WRITE_FLUSH(hw);
1570 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1571 int base_queue, int nb_queue)
1575 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1577 /* Bind all RX queues to allocated MSIX interrupt */
1578 for (i = 0; i < nb_queue; i++) {
1579 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1580 I40E_QINT_RQCTL_ITR_INDX_MASK |
1581 ((base_queue + i + 1) <<
1582 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1583 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1584 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1586 if (i == nb_queue - 1)
1587 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1588 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1591 /* Write first RX queue to Link list register as the head element */
1592 if (vsi->type != I40E_VSI_SRIOV) {
1594 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1596 if (msix_vect == I40E_MISC_VEC_ID) {
1597 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1599 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1601 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1603 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1606 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1608 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1610 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1612 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1619 if (msix_vect == I40E_MISC_VEC_ID) {
1621 I40E_VPINT_LNKLST0(vsi->user_param),
1623 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1625 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1627 /* num_msix_vectors_vf needs to minus irq0 */
1628 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1629 vsi->user_param + (msix_vect - 1);
1631 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1633 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1639 I40E_WRITE_FLUSH(hw);
1643 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1645 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1646 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1647 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1648 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1649 uint16_t msix_vect = vsi->msix_intr;
1650 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1651 uint16_t queue_idx = 0;
1656 for (i = 0; i < vsi->nb_qps; i++) {
1657 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1658 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1661 /* INTENA flag is not auto-cleared for interrupt */
1662 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1663 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1664 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1665 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1666 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1668 /* VF bind interrupt */
1669 if (vsi->type == I40E_VSI_SRIOV) {
1670 __vsi_queues_bind_intr(vsi, msix_vect,
1671 vsi->base_queue, vsi->nb_qps);
1675 /* PF & VMDq bind interrupt */
1676 if (rte_intr_dp_is_en(intr_handle)) {
1677 if (vsi->type == I40E_VSI_MAIN) {
1680 } else if (vsi->type == I40E_VSI_VMDQ2) {
1681 struct i40e_vsi *main_vsi =
1682 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1683 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1688 for (i = 0; i < vsi->nb_used_qps; i++) {
1690 if (!rte_intr_allow_others(intr_handle))
1691 /* allow to share MISC_VEC_ID */
1692 msix_vect = I40E_MISC_VEC_ID;
1694 /* no enough msix_vect, map all to one */
1695 __vsi_queues_bind_intr(vsi, msix_vect,
1696 vsi->base_queue + i,
1697 vsi->nb_used_qps - i);
1698 for (; !!record && i < vsi->nb_used_qps; i++)
1699 intr_handle->intr_vec[queue_idx + i] =
1703 /* 1:1 queue/msix_vect mapping */
1704 __vsi_queues_bind_intr(vsi, msix_vect,
1705 vsi->base_queue + i, 1);
1707 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1715 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1717 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1718 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1719 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1720 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1721 uint16_t interval = i40e_calc_itr_interval(\
1722 RTE_LIBRTE_I40E_ITR_INTERVAL);
1723 uint16_t msix_intr, i;
1725 if (rte_intr_allow_others(intr_handle))
1726 for (i = 0; i < vsi->nb_msix; i++) {
1727 msix_intr = vsi->msix_intr + i;
1728 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1729 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1730 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1731 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1733 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1736 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1737 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1738 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1739 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1741 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1743 I40E_WRITE_FLUSH(hw);
1747 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1749 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1750 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1751 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1753 uint16_t msix_intr, i;
1755 if (rte_intr_allow_others(intr_handle))
1756 for (i = 0; i < vsi->nb_msix; i++) {
1757 msix_intr = vsi->msix_intr + i;
1758 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1762 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1764 I40E_WRITE_FLUSH(hw);
1767 static inline uint8_t
1768 i40e_parse_link_speeds(uint16_t link_speeds)
1770 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1772 if (link_speeds & ETH_LINK_SPEED_40G)
1773 link_speed |= I40E_LINK_SPEED_40GB;
1774 if (link_speeds & ETH_LINK_SPEED_25G)
1775 link_speed |= I40E_LINK_SPEED_25GB;
1776 if (link_speeds & ETH_LINK_SPEED_20G)
1777 link_speed |= I40E_LINK_SPEED_20GB;
1778 if (link_speeds & ETH_LINK_SPEED_10G)
1779 link_speed |= I40E_LINK_SPEED_10GB;
1780 if (link_speeds & ETH_LINK_SPEED_1G)
1781 link_speed |= I40E_LINK_SPEED_1GB;
1782 if (link_speeds & ETH_LINK_SPEED_100M)
1783 link_speed |= I40E_LINK_SPEED_100MB;
1789 i40e_phy_conf_link(struct i40e_hw *hw,
1791 uint8_t force_speed)
1793 enum i40e_status_code status;
1794 struct i40e_aq_get_phy_abilities_resp phy_ab;
1795 struct i40e_aq_set_phy_config phy_conf;
1796 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1797 I40E_AQ_PHY_FLAG_PAUSE_RX |
1798 I40E_AQ_PHY_FLAG_PAUSE_RX |
1799 I40E_AQ_PHY_FLAG_LOW_POWER;
1800 const uint8_t advt = I40E_LINK_SPEED_40GB |
1801 I40E_LINK_SPEED_25GB |
1802 I40E_LINK_SPEED_10GB |
1803 I40E_LINK_SPEED_1GB |
1804 I40E_LINK_SPEED_100MB;
1808 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1813 memset(&phy_conf, 0, sizeof(phy_conf));
1815 /* bits 0-2 use the values from get_phy_abilities_resp */
1817 abilities |= phy_ab.abilities & mask;
1819 /* update ablities and speed */
1820 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1821 phy_conf.link_speed = advt;
1823 phy_conf.link_speed = force_speed;
1825 phy_conf.abilities = abilities;
1827 /* use get_phy_abilities_resp value for the rest */
1828 phy_conf.phy_type = phy_ab.phy_type;
1829 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1830 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1831 phy_conf.eee_capability = phy_ab.eee_capability;
1832 phy_conf.eeer = phy_ab.eeer_val;
1833 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1835 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1836 phy_ab.abilities, phy_ab.link_speed);
1837 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1838 phy_conf.abilities, phy_conf.link_speed);
1840 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1844 return I40E_SUCCESS;
1848 i40e_apply_link_speed(struct rte_eth_dev *dev)
1851 uint8_t abilities = 0;
1852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 struct rte_eth_conf *conf = &dev->data->dev_conf;
1855 speed = i40e_parse_link_speeds(conf->link_speeds);
1856 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1857 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1858 abilities |= I40E_AQ_PHY_AN_ENABLED;
1859 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1861 /* Skip changing speed on 40G interfaces, FW does not support */
1862 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1863 speed = I40E_LINK_SPEED_UNKNOWN;
1864 abilities |= I40E_AQ_PHY_AN_ENABLED;
1867 return i40e_phy_conf_link(hw, abilities, speed);
1871 i40e_dev_start(struct rte_eth_dev *dev)
1873 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1875 struct i40e_vsi *main_vsi = pf->main_vsi;
1877 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1878 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1879 uint32_t intr_vector = 0;
1880 struct i40e_vsi *vsi;
1882 hw->adapter_stopped = 0;
1884 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1885 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1886 dev->data->port_id);
1890 rte_intr_disable(intr_handle);
1892 if ((rte_intr_cap_multiple(intr_handle) ||
1893 !RTE_ETH_DEV_SRIOV(dev).active) &&
1894 dev->data->dev_conf.intr_conf.rxq != 0) {
1895 intr_vector = dev->data->nb_rx_queues;
1896 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1901 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1902 intr_handle->intr_vec =
1903 rte_zmalloc("intr_vec",
1904 dev->data->nb_rx_queues * sizeof(int),
1906 if (!intr_handle->intr_vec) {
1908 "Failed to allocate %d rx_queues intr_vec",
1909 dev->data->nb_rx_queues);
1914 /* Initialize VSI */
1915 ret = i40e_dev_rxtx_init(pf);
1916 if (ret != I40E_SUCCESS) {
1917 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1921 /* Map queues with MSIX interrupt */
1922 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1923 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1924 i40e_vsi_queues_bind_intr(main_vsi);
1925 i40e_vsi_enable_queues_intr(main_vsi);
1927 /* Map VMDQ VSI queues with MSIX interrupt */
1928 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1929 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1930 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1931 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1934 /* enable FDIR MSIX interrupt */
1935 if (pf->fdir.fdir_vsi) {
1936 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1937 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1940 /* Enable all queues which have been configured */
1941 ret = i40e_dev_switch_queues(pf, TRUE);
1942 if (ret != I40E_SUCCESS) {
1943 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1947 /* Enable receiving broadcast packets */
1948 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1949 if (ret != I40E_SUCCESS)
1950 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1952 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1953 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1955 if (ret != I40E_SUCCESS)
1956 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1959 /* Enable the VLAN promiscuous mode. */
1961 for (i = 0; i < pf->vf_num; i++) {
1962 vsi = pf->vfs[i].vsi;
1963 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1968 /* Apply link configure */
1969 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1970 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1971 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1972 ETH_LINK_SPEED_40G)) {
1973 PMD_DRV_LOG(ERR, "Invalid link setting");
1976 ret = i40e_apply_link_speed(dev);
1977 if (I40E_SUCCESS != ret) {
1978 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1982 if (!rte_intr_allow_others(intr_handle)) {
1983 rte_intr_callback_unregister(intr_handle,
1984 i40e_dev_interrupt_handler,
1986 /* configure and enable device interrupt */
1987 i40e_pf_config_irq0(hw, FALSE);
1988 i40e_pf_enable_irq0(hw);
1990 if (dev->data->dev_conf.intr_conf.lsc != 0)
1992 "lsc won't enable because of no intr multiplex");
1993 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1994 ret = i40e_aq_set_phy_int_mask(hw,
1995 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1996 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1997 I40E_AQ_EVENT_MEDIA_NA), NULL);
1998 if (ret != I40E_SUCCESS)
1999 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2001 /* Call get_link_info aq commond to enable LSE */
2002 i40e_dev_link_update(dev, 0);
2005 /* enable uio intr after callback register */
2006 rte_intr_enable(intr_handle);
2008 i40e_filter_restore(pf);
2010 return I40E_SUCCESS;
2013 i40e_dev_switch_queues(pf, FALSE);
2014 i40e_dev_clear_queues(dev);
2020 i40e_dev_stop(struct rte_eth_dev *dev)
2022 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2023 struct i40e_vsi *main_vsi = pf->main_vsi;
2024 struct i40e_mirror_rule *p_mirror;
2025 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2026 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2029 /* Disable all queues */
2030 i40e_dev_switch_queues(pf, FALSE);
2032 /* un-map queues with interrupt registers */
2033 i40e_vsi_disable_queues_intr(main_vsi);
2034 i40e_vsi_queues_unbind_intr(main_vsi);
2036 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2037 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2038 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2041 if (pf->fdir.fdir_vsi) {
2042 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2043 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2045 /* Clear all queues and release memory */
2046 i40e_dev_clear_queues(dev);
2049 i40e_dev_set_link_down(dev);
2051 /* Remove all mirror rules */
2052 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2053 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2056 pf->nb_mirror_rule = 0;
2058 if (!rte_intr_allow_others(intr_handle))
2059 /* resume to the default handler */
2060 rte_intr_callback_register(intr_handle,
2061 i40e_dev_interrupt_handler,
2064 /* Clean datapath event and queue/vec mapping */
2065 rte_intr_efd_disable(intr_handle);
2066 if (intr_handle->intr_vec) {
2067 rte_free(intr_handle->intr_vec);
2068 intr_handle->intr_vec = NULL;
2073 i40e_dev_close(struct rte_eth_dev *dev)
2075 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2076 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2078 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082 PMD_INIT_FUNC_TRACE();
2085 hw->adapter_stopped = 1;
2086 i40e_dev_free_queues(dev);
2088 /* Disable interrupt */
2089 i40e_pf_disable_irq0(hw);
2090 rte_intr_disable(intr_handle);
2092 /* shutdown and destroy the HMC */
2093 i40e_shutdown_lan_hmc(hw);
2095 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2096 i40e_vsi_release(pf->vmdq[i].vsi);
2097 pf->vmdq[i].vsi = NULL;
2102 /* release all the existing VSIs and VEBs */
2103 i40e_fdir_teardown(pf);
2104 i40e_vsi_release(pf->main_vsi);
2106 /* shutdown the adminq */
2107 i40e_aq_queue_shutdown(hw, true);
2108 i40e_shutdown_adminq(hw);
2110 i40e_res_pool_destroy(&pf->qp_pool);
2111 i40e_res_pool_destroy(&pf->msix_pool);
2113 /* force a PF reset to clean anything leftover */
2114 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2115 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2116 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2117 I40E_WRITE_FLUSH(hw);
2121 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2123 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2124 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125 struct i40e_vsi *vsi = pf->main_vsi;
2128 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2130 if (status != I40E_SUCCESS)
2131 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2133 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2135 if (status != I40E_SUCCESS)
2136 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2141 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2143 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2144 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 struct i40e_vsi *vsi = pf->main_vsi;
2148 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2150 if (status != I40E_SUCCESS)
2151 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2153 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2155 if (status != I40E_SUCCESS)
2156 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2160 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2162 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2163 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 struct i40e_vsi *vsi = pf->main_vsi;
2167 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2168 if (ret != I40E_SUCCESS)
2169 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2173 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2175 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2176 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 struct i40e_vsi *vsi = pf->main_vsi;
2180 if (dev->data->promiscuous == 1)
2181 return; /* must remain in all_multicast mode */
2183 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2184 vsi->seid, FALSE, NULL);
2185 if (ret != I40E_SUCCESS)
2186 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2190 * Set device link up.
2193 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2195 /* re-apply link speed setting */
2196 return i40e_apply_link_speed(dev);
2200 * Set device link down.
2203 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2205 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2206 uint8_t abilities = 0;
2207 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2210 return i40e_phy_conf_link(hw, abilities, speed);
2214 i40e_dev_link_update(struct rte_eth_dev *dev,
2215 int wait_to_complete)
2217 #define CHECK_INTERVAL 100 /* 100ms */
2218 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2219 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220 struct i40e_link_status link_status;
2221 struct rte_eth_link link, old;
2223 unsigned rep_cnt = MAX_REPEAT_TIME;
2224 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2226 memset(&link, 0, sizeof(link));
2227 memset(&old, 0, sizeof(old));
2228 memset(&link_status, 0, sizeof(link_status));
2229 rte_i40e_dev_atomic_read_link_status(dev, &old);
2232 /* Get link status information from hardware */
2233 status = i40e_aq_get_link_info(hw, enable_lse,
2234 &link_status, NULL);
2235 if (status != I40E_SUCCESS) {
2236 link.link_speed = ETH_SPEED_NUM_100M;
2237 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2238 PMD_DRV_LOG(ERR, "Failed to get link info");
2242 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2243 if (!wait_to_complete || link.link_status)
2246 rte_delay_ms(CHECK_INTERVAL);
2247 } while (--rep_cnt);
2249 if (!link.link_status)
2252 /* i40e uses full duplex only */
2253 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2255 /* Parse the link status */
2256 switch (link_status.link_speed) {
2257 case I40E_LINK_SPEED_100MB:
2258 link.link_speed = ETH_SPEED_NUM_100M;
2260 case I40E_LINK_SPEED_1GB:
2261 link.link_speed = ETH_SPEED_NUM_1G;
2263 case I40E_LINK_SPEED_10GB:
2264 link.link_speed = ETH_SPEED_NUM_10G;
2266 case I40E_LINK_SPEED_20GB:
2267 link.link_speed = ETH_SPEED_NUM_20G;
2269 case I40E_LINK_SPEED_25GB:
2270 link.link_speed = ETH_SPEED_NUM_25G;
2272 case I40E_LINK_SPEED_40GB:
2273 link.link_speed = ETH_SPEED_NUM_40G;
2276 link.link_speed = ETH_SPEED_NUM_100M;
2280 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2281 ETH_LINK_SPEED_FIXED);
2284 rte_i40e_dev_atomic_write_link_status(dev, &link);
2285 if (link.link_status == old.link_status)
2291 /* Get all the statistics of a VSI */
2293 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2295 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2296 struct i40e_eth_stats *nes = &vsi->eth_stats;
2297 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2298 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2300 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2301 vsi->offset_loaded, &oes->rx_bytes,
2303 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2304 vsi->offset_loaded, &oes->rx_unicast,
2306 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2307 vsi->offset_loaded, &oes->rx_multicast,
2308 &nes->rx_multicast);
2309 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2310 vsi->offset_loaded, &oes->rx_broadcast,
2311 &nes->rx_broadcast);
2312 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2313 &oes->rx_discards, &nes->rx_discards);
2314 /* GLV_REPC not supported */
2315 /* GLV_RMPC not supported */
2316 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2317 &oes->rx_unknown_protocol,
2318 &nes->rx_unknown_protocol);
2319 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2320 vsi->offset_loaded, &oes->tx_bytes,
2322 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2323 vsi->offset_loaded, &oes->tx_unicast,
2325 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2326 vsi->offset_loaded, &oes->tx_multicast,
2327 &nes->tx_multicast);
2328 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2329 vsi->offset_loaded, &oes->tx_broadcast,
2330 &nes->tx_broadcast);
2331 /* GLV_TDPC not supported */
2332 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2333 &oes->tx_errors, &nes->tx_errors);
2334 vsi->offset_loaded = true;
2336 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2338 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2339 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2340 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2341 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2342 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2343 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2344 nes->rx_unknown_protocol);
2345 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2346 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2347 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2348 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2349 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2350 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2351 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2356 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2359 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2360 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2362 /* Get statistics of struct i40e_eth_stats */
2363 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2364 I40E_GLPRT_GORCL(hw->port),
2365 pf->offset_loaded, &os->eth.rx_bytes,
2367 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2368 I40E_GLPRT_UPRCL(hw->port),
2369 pf->offset_loaded, &os->eth.rx_unicast,
2370 &ns->eth.rx_unicast);
2371 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2372 I40E_GLPRT_MPRCL(hw->port),
2373 pf->offset_loaded, &os->eth.rx_multicast,
2374 &ns->eth.rx_multicast);
2375 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2376 I40E_GLPRT_BPRCL(hw->port),
2377 pf->offset_loaded, &os->eth.rx_broadcast,
2378 &ns->eth.rx_broadcast);
2379 /* Workaround: CRC size should not be included in byte statistics,
2380 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2382 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2383 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2385 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2386 pf->offset_loaded, &os->eth.rx_discards,
2387 &ns->eth.rx_discards);
2388 /* GLPRT_REPC not supported */
2389 /* GLPRT_RMPC not supported */
2390 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2392 &os->eth.rx_unknown_protocol,
2393 &ns->eth.rx_unknown_protocol);
2394 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2395 I40E_GLPRT_GOTCL(hw->port),
2396 pf->offset_loaded, &os->eth.tx_bytes,
2398 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2399 I40E_GLPRT_UPTCL(hw->port),
2400 pf->offset_loaded, &os->eth.tx_unicast,
2401 &ns->eth.tx_unicast);
2402 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2403 I40E_GLPRT_MPTCL(hw->port),
2404 pf->offset_loaded, &os->eth.tx_multicast,
2405 &ns->eth.tx_multicast);
2406 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2407 I40E_GLPRT_BPTCL(hw->port),
2408 pf->offset_loaded, &os->eth.tx_broadcast,
2409 &ns->eth.tx_broadcast);
2410 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2411 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2412 /* GLPRT_TEPC not supported */
2414 /* additional port specific stats */
2415 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2416 pf->offset_loaded, &os->tx_dropped_link_down,
2417 &ns->tx_dropped_link_down);
2418 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2419 pf->offset_loaded, &os->crc_errors,
2421 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2422 pf->offset_loaded, &os->illegal_bytes,
2423 &ns->illegal_bytes);
2424 /* GLPRT_ERRBC not supported */
2425 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2426 pf->offset_loaded, &os->mac_local_faults,
2427 &ns->mac_local_faults);
2428 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2429 pf->offset_loaded, &os->mac_remote_faults,
2430 &ns->mac_remote_faults);
2431 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2432 pf->offset_loaded, &os->rx_length_errors,
2433 &ns->rx_length_errors);
2434 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2435 pf->offset_loaded, &os->link_xon_rx,
2437 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2438 pf->offset_loaded, &os->link_xoff_rx,
2440 for (i = 0; i < 8; i++) {
2441 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2443 &os->priority_xon_rx[i],
2444 &ns->priority_xon_rx[i]);
2445 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2447 &os->priority_xoff_rx[i],
2448 &ns->priority_xoff_rx[i]);
2450 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2451 pf->offset_loaded, &os->link_xon_tx,
2453 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2454 pf->offset_loaded, &os->link_xoff_tx,
2456 for (i = 0; i < 8; i++) {
2457 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2459 &os->priority_xon_tx[i],
2460 &ns->priority_xon_tx[i]);
2461 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2463 &os->priority_xoff_tx[i],
2464 &ns->priority_xoff_tx[i]);
2465 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2467 &os->priority_xon_2_xoff[i],
2468 &ns->priority_xon_2_xoff[i]);
2470 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2471 I40E_GLPRT_PRC64L(hw->port),
2472 pf->offset_loaded, &os->rx_size_64,
2474 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2475 I40E_GLPRT_PRC127L(hw->port),
2476 pf->offset_loaded, &os->rx_size_127,
2478 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2479 I40E_GLPRT_PRC255L(hw->port),
2480 pf->offset_loaded, &os->rx_size_255,
2482 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2483 I40E_GLPRT_PRC511L(hw->port),
2484 pf->offset_loaded, &os->rx_size_511,
2486 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2487 I40E_GLPRT_PRC1023L(hw->port),
2488 pf->offset_loaded, &os->rx_size_1023,
2490 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2491 I40E_GLPRT_PRC1522L(hw->port),
2492 pf->offset_loaded, &os->rx_size_1522,
2494 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2495 I40E_GLPRT_PRC9522L(hw->port),
2496 pf->offset_loaded, &os->rx_size_big,
2498 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2499 pf->offset_loaded, &os->rx_undersize,
2501 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2502 pf->offset_loaded, &os->rx_fragments,
2504 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2505 pf->offset_loaded, &os->rx_oversize,
2507 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2508 pf->offset_loaded, &os->rx_jabber,
2510 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2511 I40E_GLPRT_PTC64L(hw->port),
2512 pf->offset_loaded, &os->tx_size_64,
2514 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2515 I40E_GLPRT_PTC127L(hw->port),
2516 pf->offset_loaded, &os->tx_size_127,
2518 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2519 I40E_GLPRT_PTC255L(hw->port),
2520 pf->offset_loaded, &os->tx_size_255,
2522 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2523 I40E_GLPRT_PTC511L(hw->port),
2524 pf->offset_loaded, &os->tx_size_511,
2526 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2527 I40E_GLPRT_PTC1023L(hw->port),
2528 pf->offset_loaded, &os->tx_size_1023,
2530 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2531 I40E_GLPRT_PTC1522L(hw->port),
2532 pf->offset_loaded, &os->tx_size_1522,
2534 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2535 I40E_GLPRT_PTC9522L(hw->port),
2536 pf->offset_loaded, &os->tx_size_big,
2538 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2540 &os->fd_sb_match, &ns->fd_sb_match);
2541 /* GLPRT_MSPDC not supported */
2542 /* GLPRT_XEC not supported */
2544 pf->offset_loaded = true;
2547 i40e_update_vsi_stats(pf->main_vsi);
2550 /* Get all statistics of a port */
2552 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2554 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2555 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2559 /* call read registers - updates values, now write them to struct */
2560 i40e_read_stats_registers(pf, hw);
2562 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2563 pf->main_vsi->eth_stats.rx_multicast +
2564 pf->main_vsi->eth_stats.rx_broadcast -
2565 pf->main_vsi->eth_stats.rx_discards;
2566 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2567 pf->main_vsi->eth_stats.tx_multicast +
2568 pf->main_vsi->eth_stats.tx_broadcast;
2569 stats->ibytes = ns->eth.rx_bytes;
2570 stats->obytes = ns->eth.tx_bytes;
2571 stats->oerrors = ns->eth.tx_errors +
2572 pf->main_vsi->eth_stats.tx_errors;
2575 stats->imissed = ns->eth.rx_discards +
2576 pf->main_vsi->eth_stats.rx_discards;
2577 stats->ierrors = ns->crc_errors +
2578 ns->rx_length_errors + ns->rx_undersize +
2579 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2581 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2582 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2583 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2584 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2585 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2586 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2587 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2588 ns->eth.rx_unknown_protocol);
2589 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2590 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2591 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2592 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2593 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2594 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2596 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2597 ns->tx_dropped_link_down);
2598 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2599 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2601 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2602 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2603 ns->mac_local_faults);
2604 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2605 ns->mac_remote_faults);
2606 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2607 ns->rx_length_errors);
2608 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2609 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2610 for (i = 0; i < 8; i++) {
2611 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2612 i, ns->priority_xon_rx[i]);
2613 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2614 i, ns->priority_xoff_rx[i]);
2616 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2617 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2618 for (i = 0; i < 8; i++) {
2619 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2620 i, ns->priority_xon_tx[i]);
2621 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2622 i, ns->priority_xoff_tx[i]);
2623 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2624 i, ns->priority_xon_2_xoff[i]);
2626 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2627 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2628 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2629 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2630 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2631 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2632 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2633 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2634 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2635 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2636 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2637 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2638 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2639 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2640 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2641 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2642 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2643 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2644 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2645 ns->mac_short_packet_dropped);
2646 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2647 ns->checksum_error);
2648 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2649 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2652 /* Reset the statistics */
2654 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2656 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659 /* Mark PF and VSI stats to update the offset, aka "reset" */
2660 pf->offset_loaded = false;
2662 pf->main_vsi->offset_loaded = false;
2664 /* read the stats, reading current register values into offset */
2665 i40e_read_stats_registers(pf, hw);
2669 i40e_xstats_calc_num(void)
2671 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2672 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2673 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2676 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2677 struct rte_eth_xstat_name *xstats_names,
2678 __rte_unused unsigned limit)
2683 if (xstats_names == NULL)
2684 return i40e_xstats_calc_num();
2686 /* Note: limit checked in rte_eth_xstats_names() */
2688 /* Get stats from i40e_eth_stats struct */
2689 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2690 snprintf(xstats_names[count].name,
2691 sizeof(xstats_names[count].name),
2692 "%s", rte_i40e_stats_strings[i].name);
2696 /* Get individiual stats from i40e_hw_port struct */
2697 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2698 snprintf(xstats_names[count].name,
2699 sizeof(xstats_names[count].name),
2700 "%s", rte_i40e_hw_port_strings[i].name);
2704 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2705 for (prio = 0; prio < 8; prio++) {
2706 snprintf(xstats_names[count].name,
2707 sizeof(xstats_names[count].name),
2708 "rx_priority%u_%s", prio,
2709 rte_i40e_rxq_prio_strings[i].name);
2714 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2715 for (prio = 0; prio < 8; prio++) {
2716 snprintf(xstats_names[count].name,
2717 sizeof(xstats_names[count].name),
2718 "tx_priority%u_%s", prio,
2719 rte_i40e_txq_prio_strings[i].name);
2727 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732 unsigned i, count, prio;
2733 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2735 count = i40e_xstats_calc_num();
2739 i40e_read_stats_registers(pf, hw);
2746 /* Get stats from i40e_eth_stats struct */
2747 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2748 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2749 rte_i40e_stats_strings[i].offset);
2750 xstats[count].id = count;
2754 /* Get individiual stats from i40e_hw_port struct */
2755 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2756 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2757 rte_i40e_hw_port_strings[i].offset);
2758 xstats[count].id = count;
2762 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2763 for (prio = 0; prio < 8; prio++) {
2764 xstats[count].value =
2765 *(uint64_t *)(((char *)hw_stats) +
2766 rte_i40e_rxq_prio_strings[i].offset +
2767 (sizeof(uint64_t) * prio));
2768 xstats[count].id = count;
2773 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2774 for (prio = 0; prio < 8; prio++) {
2775 xstats[count].value =
2776 *(uint64_t *)(((char *)hw_stats) +
2777 rte_i40e_txq_prio_strings[i].offset +
2778 (sizeof(uint64_t) * prio));
2779 xstats[count].id = count;
2788 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2789 __rte_unused uint16_t queue_id,
2790 __rte_unused uint8_t stat_idx,
2791 __rte_unused uint8_t is_rx)
2793 PMD_INIT_FUNC_TRACE();
2799 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2801 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 full_ver = hw->nvm.oem_ver;
2808 ver = (u8)(full_ver >> 24);
2809 build = (u16)((full_ver >> 8) & 0xffff);
2810 patch = (u8)(full_ver & 0xff);
2812 ret = snprintf(fw_version, fw_size,
2813 "%d.%d%d 0x%08x %d.%d.%d",
2814 ((hw->nvm.version >> 12) & 0xf),
2815 ((hw->nvm.version >> 4) & 0xff),
2816 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2819 ret += 1; /* add the size of '\0' */
2820 if (fw_size < (u32)ret)
2827 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2829 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2830 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831 struct i40e_vsi *vsi = pf->main_vsi;
2832 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2834 dev_info->pci_dev = pci_dev;
2835 dev_info->max_rx_queues = vsi->nb_qps;
2836 dev_info->max_tx_queues = vsi->nb_qps;
2837 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2838 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2839 dev_info->max_mac_addrs = vsi->max_macaddrs;
2840 dev_info->max_vfs = pci_dev->max_vfs;
2841 dev_info->rx_offload_capa =
2842 DEV_RX_OFFLOAD_VLAN_STRIP |
2843 DEV_RX_OFFLOAD_QINQ_STRIP |
2844 DEV_RX_OFFLOAD_IPV4_CKSUM |
2845 DEV_RX_OFFLOAD_UDP_CKSUM |
2846 DEV_RX_OFFLOAD_TCP_CKSUM;
2847 dev_info->tx_offload_capa =
2848 DEV_TX_OFFLOAD_VLAN_INSERT |
2849 DEV_TX_OFFLOAD_QINQ_INSERT |
2850 DEV_TX_OFFLOAD_IPV4_CKSUM |
2851 DEV_TX_OFFLOAD_UDP_CKSUM |
2852 DEV_TX_OFFLOAD_TCP_CKSUM |
2853 DEV_TX_OFFLOAD_SCTP_CKSUM |
2854 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2855 DEV_TX_OFFLOAD_TCP_TSO |
2856 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2857 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2858 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2859 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2860 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2862 dev_info->reta_size = pf->hash_lut_size;
2863 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2865 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2867 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2868 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2869 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2871 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2875 dev_info->default_txconf = (struct rte_eth_txconf) {
2877 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2878 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2879 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2881 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2882 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2883 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2884 ETH_TXQ_FLAGS_NOOFFLOADS,
2887 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2888 .nb_max = I40E_MAX_RING_DESC,
2889 .nb_min = I40E_MIN_RING_DESC,
2890 .nb_align = I40E_ALIGN_RING_DESC,
2893 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2894 .nb_max = I40E_MAX_RING_DESC,
2895 .nb_min = I40E_MIN_RING_DESC,
2896 .nb_align = I40E_ALIGN_RING_DESC,
2897 .nb_seg_max = I40E_TX_MAX_SEG,
2898 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2901 if (pf->flags & I40E_FLAG_VMDQ) {
2902 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2903 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2904 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2905 pf->max_nb_vmdq_vsi;
2906 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2907 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2908 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2911 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2913 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2914 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2916 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2919 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2923 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2925 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2926 struct i40e_vsi *vsi = pf->main_vsi;
2927 PMD_INIT_FUNC_TRACE();
2930 return i40e_vsi_add_vlan(vsi, vlan_id);
2932 return i40e_vsi_delete_vlan(vsi, vlan_id);
2936 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2937 enum rte_vlan_type vlan_type,
2940 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941 uint64_t reg_r = 0, reg_w = 0;
2942 uint16_t reg_id = 0;
2944 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2946 switch (vlan_type) {
2947 case ETH_VLAN_TYPE_OUTER:
2953 case ETH_VLAN_TYPE_INNER:
2959 "Unsupported vlan type in single vlan.");
2965 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2968 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2970 if (ret != I40E_SUCCESS) {
2972 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2978 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2981 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2982 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2983 if (reg_r == reg_w) {
2985 PMD_DRV_LOG(DEBUG, "No need to write");
2989 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2991 if (ret != I40E_SUCCESS) {
2994 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2999 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3006 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3009 struct i40e_vsi *vsi = pf->main_vsi;
3011 if (mask & ETH_VLAN_FILTER_MASK) {
3012 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3013 i40e_vsi_config_vlan_filter(vsi, TRUE);
3015 i40e_vsi_config_vlan_filter(vsi, FALSE);
3018 if (mask & ETH_VLAN_STRIP_MASK) {
3019 /* Enable or disable VLAN stripping */
3020 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3021 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3023 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3026 if (mask & ETH_VLAN_EXTEND_MASK) {
3027 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3028 i40e_vsi_config_double_vlan(vsi, TRUE);
3029 /* Set global registers with default ether type value */
3030 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3032 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3036 i40e_vsi_config_double_vlan(vsi, FALSE);
3041 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3042 __rte_unused uint16_t queue,
3043 __rte_unused int on)
3045 PMD_INIT_FUNC_TRACE();
3049 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3051 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3052 struct i40e_vsi *vsi = pf->main_vsi;
3053 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3054 struct i40e_vsi_vlan_pvid_info info;
3056 memset(&info, 0, sizeof(info));
3059 info.config.pvid = pvid;
3061 info.config.reject.tagged =
3062 data->dev_conf.txmode.hw_vlan_reject_tagged;
3063 info.config.reject.untagged =
3064 data->dev_conf.txmode.hw_vlan_reject_untagged;
3067 return i40e_vsi_vlan_pvid_set(vsi, &info);
3071 i40e_dev_led_on(struct rte_eth_dev *dev)
3073 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074 uint32_t mode = i40e_led_get(hw);
3077 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3083 i40e_dev_led_off(struct rte_eth_dev *dev)
3085 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086 uint32_t mode = i40e_led_get(hw);
3089 i40e_led_set(hw, 0, false);
3095 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3097 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3100 fc_conf->pause_time = pf->fc_conf.pause_time;
3101 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3102 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3104 /* Return current mode according to actual setting*/
3105 switch (hw->fc.current_mode) {
3107 fc_conf->mode = RTE_FC_FULL;
3109 case I40E_FC_TX_PAUSE:
3110 fc_conf->mode = RTE_FC_TX_PAUSE;
3112 case I40E_FC_RX_PAUSE:
3113 fc_conf->mode = RTE_FC_RX_PAUSE;
3117 fc_conf->mode = RTE_FC_NONE;
3124 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3126 uint32_t mflcn_reg, fctrl_reg, reg;
3127 uint32_t max_high_water;
3128 uint8_t i, aq_failure;
3132 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3133 [RTE_FC_NONE] = I40E_FC_NONE,
3134 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3135 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3136 [RTE_FC_FULL] = I40E_FC_FULL
3139 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3141 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3142 if ((fc_conf->high_water > max_high_water) ||
3143 (fc_conf->high_water < fc_conf->low_water)) {
3145 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3150 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3151 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3152 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3154 pf->fc_conf.pause_time = fc_conf->pause_time;
3155 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3156 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3158 PMD_INIT_FUNC_TRACE();
3160 /* All the link flow control related enable/disable register
3161 * configuration is handle by the F/W
3163 err = i40e_set_fc(hw, &aq_failure, true);
3167 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3168 /* Configure flow control refresh threshold,
3169 * the value for stat_tx_pause_refresh_timer[8]
3170 * is used for global pause operation.
3174 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3175 pf->fc_conf.pause_time);
3177 /* configure the timer value included in transmitted pause
3179 * the value for stat_tx_pause_quanta[8] is used for global
3182 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3183 pf->fc_conf.pause_time);
3185 fctrl_reg = I40E_READ_REG(hw,
3186 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3188 if (fc_conf->mac_ctrl_frame_fwd != 0)
3189 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3191 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3193 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3196 /* Configure pause time (2 TCs per register) */
3197 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3198 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3199 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3201 /* Configure flow control refresh threshold value */
3202 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3203 pf->fc_conf.pause_time / 2);
3205 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3207 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3208 *depending on configuration
3210 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3211 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3212 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3214 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3215 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3218 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3221 /* config the water marker both based on the packets and bytes */
3222 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3223 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3224 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3225 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3226 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3227 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3228 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3229 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3231 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3232 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3235 I40E_WRITE_FLUSH(hw);
3241 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3242 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3244 PMD_INIT_FUNC_TRACE();
3249 /* Add a MAC address, and update filters */
3251 i40e_macaddr_add(struct rte_eth_dev *dev,
3252 struct ether_addr *mac_addr,
3253 __rte_unused uint32_t index,
3256 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3257 struct i40e_mac_filter_info mac_filter;
3258 struct i40e_vsi *vsi;
3261 /* If VMDQ not enabled or configured, return */
3262 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3263 !pf->nb_cfg_vmdq_vsi)) {
3264 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3265 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3270 if (pool > pf->nb_cfg_vmdq_vsi) {
3271 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3272 pool, pf->nb_cfg_vmdq_vsi);
3276 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3277 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3278 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3280 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3285 vsi = pf->vmdq[pool - 1].vsi;
3287 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3288 if (ret != I40E_SUCCESS) {
3289 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3294 /* Remove a MAC address, and update filters */
3296 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3298 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3299 struct i40e_vsi *vsi;
3300 struct rte_eth_dev_data *data = dev->data;
3301 struct ether_addr *macaddr;
3306 macaddr = &(data->mac_addrs[index]);
3308 pool_sel = dev->data->mac_pool_sel[index];
3310 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3311 if (pool_sel & (1ULL << i)) {
3315 /* No VMDQ pool enabled or configured */
3316 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3317 (i > pf->nb_cfg_vmdq_vsi)) {
3319 "No VMDQ pool enabled/configured");
3322 vsi = pf->vmdq[i - 1].vsi;
3324 ret = i40e_vsi_delete_mac(vsi, macaddr);
3327 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3334 /* Set perfect match or hash match of MAC and VLAN for a VF */
3336 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3337 struct rte_eth_mac_filter *filter,
3341 struct i40e_mac_filter_info mac_filter;
3342 struct ether_addr old_mac;
3343 struct ether_addr *new_mac;
3344 struct i40e_pf_vf *vf = NULL;
3349 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3352 hw = I40E_PF_TO_HW(pf);
3354 if (filter == NULL) {
3355 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3359 new_mac = &filter->mac_addr;
3361 if (is_zero_ether_addr(new_mac)) {
3362 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3366 vf_id = filter->dst_id;
3368 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3369 PMD_DRV_LOG(ERR, "Invalid argument.");
3372 vf = &pf->vfs[vf_id];
3374 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3375 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3380 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3381 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3383 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3386 mac_filter.filter_type = filter->filter_type;
3387 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3388 if (ret != I40E_SUCCESS) {
3389 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3392 ether_addr_copy(new_mac, &pf->dev_addr);
3394 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3396 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3397 if (ret != I40E_SUCCESS) {
3398 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3402 /* Clear device address as it has been removed */
3403 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3404 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3410 /* MAC filter handle */
3412 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3415 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3416 struct rte_eth_mac_filter *filter;
3417 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3418 int ret = I40E_NOT_SUPPORTED;
3420 filter = (struct rte_eth_mac_filter *)(arg);
3422 switch (filter_op) {
3423 case RTE_ETH_FILTER_NOP:
3426 case RTE_ETH_FILTER_ADD:
3427 i40e_pf_disable_irq0(hw);
3429 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3430 i40e_pf_enable_irq0(hw);
3432 case RTE_ETH_FILTER_DELETE:
3433 i40e_pf_disable_irq0(hw);
3435 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3436 i40e_pf_enable_irq0(hw);
3439 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3440 ret = I40E_ERR_PARAM;
3448 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3450 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3451 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3457 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3458 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3461 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3465 uint32_t *lut_dw = (uint32_t *)lut;
3466 uint16_t i, lut_size_dw = lut_size / 4;
3468 for (i = 0; i < lut_size_dw; i++)
3469 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3476 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3485 pf = I40E_VSI_TO_PF(vsi);
3486 hw = I40E_VSI_TO_HW(vsi);
3488 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3489 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3492 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3496 uint32_t *lut_dw = (uint32_t *)lut;
3497 uint16_t i, lut_size_dw = lut_size / 4;
3499 for (i = 0; i < lut_size_dw; i++)
3500 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3501 I40E_WRITE_FLUSH(hw);
3508 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3509 struct rte_eth_rss_reta_entry64 *reta_conf,
3512 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3513 uint16_t i, lut_size = pf->hash_lut_size;
3514 uint16_t idx, shift;
3518 if (reta_size != lut_size ||
3519 reta_size > ETH_RSS_RETA_SIZE_512) {
3521 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3522 reta_size, lut_size);
3526 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3528 PMD_DRV_LOG(ERR, "No memory can be allocated");
3531 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3534 for (i = 0; i < reta_size; i++) {
3535 idx = i / RTE_RETA_GROUP_SIZE;
3536 shift = i % RTE_RETA_GROUP_SIZE;
3537 if (reta_conf[idx].mask & (1ULL << shift))
3538 lut[i] = reta_conf[idx].reta[shift];
3540 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3549 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3550 struct rte_eth_rss_reta_entry64 *reta_conf,
3553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3554 uint16_t i, lut_size = pf->hash_lut_size;
3555 uint16_t idx, shift;
3559 if (reta_size != lut_size ||
3560 reta_size > ETH_RSS_RETA_SIZE_512) {
3562 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3563 reta_size, lut_size);
3567 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3569 PMD_DRV_LOG(ERR, "No memory can be allocated");
3573 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3576 for (i = 0; i < reta_size; i++) {
3577 idx = i / RTE_RETA_GROUP_SIZE;
3578 shift = i % RTE_RETA_GROUP_SIZE;
3579 if (reta_conf[idx].mask & (1ULL << shift))
3580 reta_conf[idx].reta[shift] = lut[i];
3590 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3591 * @hw: pointer to the HW structure
3592 * @mem: pointer to mem struct to fill out
3593 * @size: size of memory requested
3594 * @alignment: what to align the allocation to
3596 enum i40e_status_code
3597 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3598 struct i40e_dma_mem *mem,
3602 const struct rte_memzone *mz = NULL;
3603 char z_name[RTE_MEMZONE_NAMESIZE];
3606 return I40E_ERR_PARAM;
3608 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3609 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3610 alignment, RTE_PGSIZE_2M);
3612 return I40E_ERR_NO_MEMORY;
3616 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3617 mem->zone = (const void *)mz;
3619 "memzone %s allocated with physical address: %"PRIu64,
3622 return I40E_SUCCESS;
3626 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3627 * @hw: pointer to the HW structure
3628 * @mem: ptr to mem struct to free
3630 enum i40e_status_code
3631 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3632 struct i40e_dma_mem *mem)
3635 return I40E_ERR_PARAM;
3638 "memzone %s to be freed with physical address: %"PRIu64,
3639 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3640 rte_memzone_free((const struct rte_memzone *)mem->zone);
3645 return I40E_SUCCESS;
3649 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3650 * @hw: pointer to the HW structure
3651 * @mem: pointer to mem struct to fill out
3652 * @size: size of memory requested
3654 enum i40e_status_code
3655 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3656 struct i40e_virt_mem *mem,
3660 return I40E_ERR_PARAM;
3663 mem->va = rte_zmalloc("i40e", size, 0);
3666 return I40E_SUCCESS;
3668 return I40E_ERR_NO_MEMORY;
3672 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3673 * @hw: pointer to the HW structure
3674 * @mem: pointer to mem struct to free
3676 enum i40e_status_code
3677 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3678 struct i40e_virt_mem *mem)
3681 return I40E_ERR_PARAM;
3686 return I40E_SUCCESS;
3690 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3692 rte_spinlock_init(&sp->spinlock);
3696 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3698 rte_spinlock_lock(&sp->spinlock);
3702 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3704 rte_spinlock_unlock(&sp->spinlock);
3708 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3714 * Get the hardware capabilities, which will be parsed
3715 * and saved into struct i40e_hw.
3718 i40e_get_cap(struct i40e_hw *hw)
3720 struct i40e_aqc_list_capabilities_element_resp *buf;
3721 uint16_t len, size = 0;
3724 /* Calculate a huge enough buff for saving response data temporarily */
3725 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3726 I40E_MAX_CAP_ELE_NUM;
3727 buf = rte_zmalloc("i40e", len, 0);
3729 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3730 return I40E_ERR_NO_MEMORY;
3733 /* Get, parse the capabilities and save it to hw */
3734 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3735 i40e_aqc_opc_list_func_capabilities, NULL);
3736 if (ret != I40E_SUCCESS)
3737 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3739 /* Free the temporary buffer after being used */
3746 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3748 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3749 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3750 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3751 uint16_t qp_count = 0, vsi_count = 0;
3753 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3754 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3757 /* Add the parameter init for LFC */
3758 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3759 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3760 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3762 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3763 pf->max_num_vsi = hw->func_caps.num_vsis;
3764 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3765 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3766 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3768 /* FDir queue/VSI allocation */
3769 pf->fdir_qp_offset = 0;
3770 if (hw->func_caps.fd) {
3771 pf->flags |= I40E_FLAG_FDIR;
3772 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3774 pf->fdir_nb_qps = 0;
3776 qp_count += pf->fdir_nb_qps;
3779 /* LAN queue/VSI allocation */
3780 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3781 if (!hw->func_caps.rss) {
3784 pf->flags |= I40E_FLAG_RSS;
3785 if (hw->mac.type == I40E_MAC_X722)
3786 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3787 pf->lan_nb_qps = pf->lan_nb_qp_max;
3789 qp_count += pf->lan_nb_qps;
3792 /* VF queue/VSI allocation */
3793 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3794 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3795 pf->flags |= I40E_FLAG_SRIOV;
3796 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3797 pf->vf_num = pci_dev->max_vfs;
3799 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3800 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3805 qp_count += pf->vf_nb_qps * pf->vf_num;
3806 vsi_count += pf->vf_num;
3808 /* VMDq queue/VSI allocation */
3809 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3810 pf->vmdq_nb_qps = 0;
3811 pf->max_nb_vmdq_vsi = 0;
3812 if (hw->func_caps.vmdq) {
3813 if (qp_count < hw->func_caps.num_tx_qp &&
3814 vsi_count < hw->func_caps.num_vsis) {
3815 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3816 qp_count) / pf->vmdq_nb_qp_max;
3818 /* Limit the maximum number of VMDq vsi to the maximum
3819 * ethdev can support
3821 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3822 hw->func_caps.num_vsis - vsi_count);
3823 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3825 if (pf->max_nb_vmdq_vsi) {
3826 pf->flags |= I40E_FLAG_VMDQ;
3827 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3829 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3830 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3831 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3834 "No enough queues left for VMDq");
3837 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3840 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3841 vsi_count += pf->max_nb_vmdq_vsi;
3843 if (hw->func_caps.dcb)
3844 pf->flags |= I40E_FLAG_DCB;
3846 if (qp_count > hw->func_caps.num_tx_qp) {
3848 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3849 qp_count, hw->func_caps.num_tx_qp);
3852 if (vsi_count > hw->func_caps.num_vsis) {
3854 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3855 vsi_count, hw->func_caps.num_vsis);
3863 i40e_pf_get_switch_config(struct i40e_pf *pf)
3865 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3866 struct i40e_aqc_get_switch_config_resp *switch_config;
3867 struct i40e_aqc_switch_config_element_resp *element;
3868 uint16_t start_seid = 0, num_reported;
3871 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3872 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3873 if (!switch_config) {
3874 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3878 /* Get the switch configurations */
3879 ret = i40e_aq_get_switch_config(hw, switch_config,
3880 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3881 if (ret != I40E_SUCCESS) {
3882 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3885 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3886 if (num_reported != 1) { /* The number should be 1 */
3887 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3891 /* Parse the switch configuration elements */
3892 element = &(switch_config->element[0]);
3893 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3894 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3895 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3897 PMD_DRV_LOG(INFO, "Unknown element type");
3900 rte_free(switch_config);
3906 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3909 struct pool_entry *entry;
3911 if (pool == NULL || num == 0)
3914 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3915 if (entry == NULL) {
3916 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3920 /* queue heap initialize */
3921 pool->num_free = num;
3922 pool->num_alloc = 0;
3924 LIST_INIT(&pool->alloc_list);
3925 LIST_INIT(&pool->free_list);
3927 /* Initialize element */
3931 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3936 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3938 struct pool_entry *entry, *next_entry;
3943 for (entry = LIST_FIRST(&pool->alloc_list);
3944 entry && (next_entry = LIST_NEXT(entry, next), 1);
3945 entry = next_entry) {
3946 LIST_REMOVE(entry, next);
3950 for (entry = LIST_FIRST(&pool->free_list);
3951 entry && (next_entry = LIST_NEXT(entry, next), 1);
3952 entry = next_entry) {
3953 LIST_REMOVE(entry, next);
3958 pool->num_alloc = 0;
3960 LIST_INIT(&pool->alloc_list);
3961 LIST_INIT(&pool->free_list);
3965 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3968 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3969 uint32_t pool_offset;
3973 PMD_DRV_LOG(ERR, "Invalid parameter");
3977 pool_offset = base - pool->base;
3978 /* Lookup in alloc list */
3979 LIST_FOREACH(entry, &pool->alloc_list, next) {
3980 if (entry->base == pool_offset) {
3981 valid_entry = entry;
3982 LIST_REMOVE(entry, next);
3987 /* Not find, return */
3988 if (valid_entry == NULL) {
3989 PMD_DRV_LOG(ERR, "Failed to find entry");
3994 * Found it, move it to free list and try to merge.
3995 * In order to make merge easier, always sort it by qbase.
3996 * Find adjacent prev and last entries.
3999 LIST_FOREACH(entry, &pool->free_list, next) {
4000 if (entry->base > valid_entry->base) {
4008 /* Try to merge with next one*/
4010 /* Merge with next one */
4011 if (valid_entry->base + valid_entry->len == next->base) {
4012 next->base = valid_entry->base;
4013 next->len += valid_entry->len;
4014 rte_free(valid_entry);
4021 /* Merge with previous one */
4022 if (prev->base + prev->len == valid_entry->base) {
4023 prev->len += valid_entry->len;
4024 /* If it merge with next one, remove next node */
4026 LIST_REMOVE(valid_entry, next);
4027 rte_free(valid_entry);
4029 rte_free(valid_entry);
4035 /* Not find any entry to merge, insert */
4038 LIST_INSERT_AFTER(prev, valid_entry, next);
4039 else if (next != NULL)
4040 LIST_INSERT_BEFORE(next, valid_entry, next);
4041 else /* It's empty list, insert to head */
4042 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4045 pool->num_free += valid_entry->len;
4046 pool->num_alloc -= valid_entry->len;
4052 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4055 struct pool_entry *entry, *valid_entry;
4057 if (pool == NULL || num == 0) {
4058 PMD_DRV_LOG(ERR, "Invalid parameter");
4062 if (pool->num_free < num) {
4063 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4064 num, pool->num_free);
4069 /* Lookup in free list and find most fit one */
4070 LIST_FOREACH(entry, &pool->free_list, next) {
4071 if (entry->len >= num) {
4073 if (entry->len == num) {
4074 valid_entry = entry;
4077 if (valid_entry == NULL || valid_entry->len > entry->len)
4078 valid_entry = entry;
4082 /* Not find one to satisfy the request, return */
4083 if (valid_entry == NULL) {
4084 PMD_DRV_LOG(ERR, "No valid entry found");
4088 * The entry have equal queue number as requested,
4089 * remove it from alloc_list.
4091 if (valid_entry->len == num) {
4092 LIST_REMOVE(valid_entry, next);
4095 * The entry have more numbers than requested,
4096 * create a new entry for alloc_list and minus its
4097 * queue base and number in free_list.
4099 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4100 if (entry == NULL) {
4102 "Failed to allocate memory for resource pool");
4105 entry->base = valid_entry->base;
4107 valid_entry->base += num;
4108 valid_entry->len -= num;
4109 valid_entry = entry;
4112 /* Insert it into alloc list, not sorted */
4113 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4115 pool->num_free -= valid_entry->len;
4116 pool->num_alloc += valid_entry->len;
4118 return valid_entry->base + pool->base;
4122 * bitmap_is_subset - Check whether src2 is subset of src1
4125 bitmap_is_subset(uint8_t src1, uint8_t src2)
4127 return !((src1 ^ src2) & src2);
4130 static enum i40e_status_code
4131 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4133 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4135 /* If DCB is not supported, only default TC is supported */
4136 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4137 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4138 return I40E_NOT_SUPPORTED;
4141 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4143 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4144 hw->func_caps.enabled_tcmap, enabled_tcmap);
4145 return I40E_NOT_SUPPORTED;
4147 return I40E_SUCCESS;
4151 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4152 struct i40e_vsi_vlan_pvid_info *info)
4155 struct i40e_vsi_context ctxt;
4156 uint8_t vlan_flags = 0;
4159 if (vsi == NULL || info == NULL) {
4160 PMD_DRV_LOG(ERR, "invalid parameters");
4161 return I40E_ERR_PARAM;
4165 vsi->info.pvid = info->config.pvid;
4167 * If insert pvid is enabled, only tagged pkts are
4168 * allowed to be sent out.
4170 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4171 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4174 if (info->config.reject.tagged == 0)
4175 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4177 if (info->config.reject.untagged == 0)
4178 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4180 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4181 I40E_AQ_VSI_PVLAN_MODE_MASK);
4182 vsi->info.port_vlan_flags |= vlan_flags;
4183 vsi->info.valid_sections =
4184 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4185 memset(&ctxt, 0, sizeof(ctxt));
4186 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4187 ctxt.seid = vsi->seid;
4189 hw = I40E_VSI_TO_HW(vsi);
4190 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4191 if (ret != I40E_SUCCESS)
4192 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4198 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4200 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4202 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4204 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4205 if (ret != I40E_SUCCESS)
4209 PMD_DRV_LOG(ERR, "seid not valid");
4213 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4214 tc_bw_data.tc_valid_bits = enabled_tcmap;
4215 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4216 tc_bw_data.tc_bw_credits[i] =
4217 (enabled_tcmap & (1 << i)) ? 1 : 0;
4219 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4220 if (ret != I40E_SUCCESS) {
4221 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4225 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4226 sizeof(vsi->info.qs_handle));
4227 return I40E_SUCCESS;
4230 static enum i40e_status_code
4231 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4232 struct i40e_aqc_vsi_properties_data *info,
4233 uint8_t enabled_tcmap)
4235 enum i40e_status_code ret;
4236 int i, total_tc = 0;
4237 uint16_t qpnum_per_tc, bsf, qp_idx;
4239 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4240 if (ret != I40E_SUCCESS)
4243 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4244 if (enabled_tcmap & (1 << i))
4246 vsi->enabled_tc = enabled_tcmap;
4248 /* Number of queues per enabled TC */
4249 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4250 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4251 bsf = rte_bsf32(qpnum_per_tc);
4253 /* Adjust the queue number to actual queues that can be applied */
4254 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4255 vsi->nb_qps = qpnum_per_tc * total_tc;
4258 * Configure TC and queue mapping parameters, for enabled TC,
4259 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4260 * default queue will serve it.
4263 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4264 if (vsi->enabled_tc & (1 << i)) {
4265 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4266 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4267 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4268 qp_idx += qpnum_per_tc;
4270 info->tc_mapping[i] = 0;
4273 /* Associate queue number with VSI */
4274 if (vsi->type == I40E_VSI_SRIOV) {
4275 info->mapping_flags |=
4276 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4277 for (i = 0; i < vsi->nb_qps; i++)
4278 info->queue_mapping[i] =
4279 rte_cpu_to_le_16(vsi->base_queue + i);
4281 info->mapping_flags |=
4282 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4283 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4285 info->valid_sections |=
4286 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4288 return I40E_SUCCESS;
4292 i40e_veb_release(struct i40e_veb *veb)
4294 struct i40e_vsi *vsi;
4300 if (!TAILQ_EMPTY(&veb->head)) {
4301 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4304 /* associate_vsi field is NULL for floating VEB */
4305 if (veb->associate_vsi != NULL) {
4306 vsi = veb->associate_vsi;
4307 hw = I40E_VSI_TO_HW(vsi);
4309 vsi->uplink_seid = veb->uplink_seid;
4312 veb->associate_pf->main_vsi->floating_veb = NULL;
4313 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4316 i40e_aq_delete_element(hw, veb->seid, NULL);
4318 return I40E_SUCCESS;
4322 static struct i40e_veb *
4323 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4325 struct i40e_veb *veb;
4331 "veb setup failed, associated PF shouldn't null");
4334 hw = I40E_PF_TO_HW(pf);
4336 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4338 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4342 veb->associate_vsi = vsi;
4343 veb->associate_pf = pf;
4344 TAILQ_INIT(&veb->head);
4345 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4347 /* create floating veb if vsi is NULL */
4349 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4350 I40E_DEFAULT_TCMAP, false,
4351 &veb->seid, false, NULL);
4353 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4354 true, &veb->seid, false, NULL);
4357 if (ret != I40E_SUCCESS) {
4358 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4359 hw->aq.asq_last_status);
4362 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4364 /* get statistics index */
4365 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4366 &veb->stats_idx, NULL, NULL, NULL);
4367 if (ret != I40E_SUCCESS) {
4368 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4369 hw->aq.asq_last_status);
4372 /* Get VEB bandwidth, to be implemented */
4373 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4375 vsi->uplink_seid = veb->seid;
4384 i40e_vsi_release(struct i40e_vsi *vsi)
4388 struct i40e_vsi_list *vsi_list;
4391 struct i40e_mac_filter *f;
4392 uint16_t user_param;
4395 return I40E_SUCCESS;
4400 user_param = vsi->user_param;
4402 pf = I40E_VSI_TO_PF(vsi);
4403 hw = I40E_VSI_TO_HW(vsi);
4405 /* VSI has child to attach, release child first */
4407 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4408 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4411 i40e_veb_release(vsi->veb);
4414 if (vsi->floating_veb) {
4415 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4416 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4421 /* Remove all macvlan filters of the VSI */
4422 i40e_vsi_remove_all_macvlan_filter(vsi);
4423 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4426 if (vsi->type != I40E_VSI_MAIN &&
4427 ((vsi->type != I40E_VSI_SRIOV) ||
4428 !pf->floating_veb_list[user_param])) {
4429 /* Remove vsi from parent's sibling list */
4430 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4431 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4432 return I40E_ERR_PARAM;
4434 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4435 &vsi->sib_vsi_list, list);
4437 /* Remove all switch element of the VSI */
4438 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4439 if (ret != I40E_SUCCESS)
4440 PMD_DRV_LOG(ERR, "Failed to delete element");
4443 if ((vsi->type == I40E_VSI_SRIOV) &&
4444 pf->floating_veb_list[user_param]) {
4445 /* Remove vsi from parent's sibling list */
4446 if (vsi->parent_vsi == NULL ||
4447 vsi->parent_vsi->floating_veb == NULL) {
4448 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4449 return I40E_ERR_PARAM;
4451 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4452 &vsi->sib_vsi_list, list);
4454 /* Remove all switch element of the VSI */
4455 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4456 if (ret != I40E_SUCCESS)
4457 PMD_DRV_LOG(ERR, "Failed to delete element");
4460 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4462 if (vsi->type != I40E_VSI_SRIOV)
4463 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4466 return I40E_SUCCESS;
4470 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4472 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4473 struct i40e_aqc_remove_macvlan_element_data def_filter;
4474 struct i40e_mac_filter_info filter;
4477 if (vsi->type != I40E_VSI_MAIN)
4478 return I40E_ERR_CONFIG;
4479 memset(&def_filter, 0, sizeof(def_filter));
4480 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4482 def_filter.vlan_tag = 0;
4483 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4484 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4485 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4486 if (ret != I40E_SUCCESS) {
4487 struct i40e_mac_filter *f;
4488 struct ether_addr *mac;
4490 PMD_DRV_LOG(WARNING,
4491 "Cannot remove the default macvlan filter");
4492 /* It needs to add the permanent mac into mac list */
4493 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4495 PMD_DRV_LOG(ERR, "failed to allocate memory");
4496 return I40E_ERR_NO_MEMORY;
4498 mac = &f->mac_info.mac_addr;
4499 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4501 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4502 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4507 (void)rte_memcpy(&filter.mac_addr,
4508 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4509 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4510 return i40e_vsi_add_mac(vsi, &filter);
4514 * i40e_vsi_get_bw_config - Query VSI BW Information
4515 * @vsi: the VSI to be queried
4517 * Returns 0 on success, negative value on failure
4519 static enum i40e_status_code
4520 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4522 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4523 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4524 struct i40e_hw *hw = &vsi->adapter->hw;
4529 memset(&bw_config, 0, sizeof(bw_config));
4530 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4531 if (ret != I40E_SUCCESS) {
4532 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4533 hw->aq.asq_last_status);
4537 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4538 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4539 &ets_sla_config, NULL);
4540 if (ret != I40E_SUCCESS) {
4542 "VSI failed to get TC bandwdith configuration %u",
4543 hw->aq.asq_last_status);
4547 /* store and print out BW info */
4548 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4549 vsi->bw_info.bw_max = bw_config.max_bw;
4550 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4551 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4552 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4553 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4555 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4556 vsi->bw_info.bw_ets_share_credits[i] =
4557 ets_sla_config.share_credits[i];
4558 vsi->bw_info.bw_ets_credits[i] =
4559 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4560 /* 4 bits per TC, 4th bit is reserved */
4561 vsi->bw_info.bw_ets_max[i] =
4562 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4563 RTE_LEN2MASK(3, uint8_t));
4564 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4565 vsi->bw_info.bw_ets_share_credits[i]);
4566 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4567 vsi->bw_info.bw_ets_credits[i]);
4568 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4569 vsi->bw_info.bw_ets_max[i]);
4572 return I40E_SUCCESS;
4575 /* i40e_enable_pf_lb
4576 * @pf: pointer to the pf structure
4578 * allow loopback on pf
4581 i40e_enable_pf_lb(struct i40e_pf *pf)
4583 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4584 struct i40e_vsi_context ctxt;
4587 /* Use the FW API if FW >= v5.0 */
4588 if (hw->aq.fw_maj_ver < 5) {
4589 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4593 memset(&ctxt, 0, sizeof(ctxt));
4594 ctxt.seid = pf->main_vsi_seid;
4595 ctxt.pf_num = hw->pf_id;
4596 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4598 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4599 ret, hw->aq.asq_last_status);
4602 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4603 ctxt.info.valid_sections =
4604 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4605 ctxt.info.switch_id |=
4606 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4608 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4610 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4611 hw->aq.asq_last_status);
4616 i40e_vsi_setup(struct i40e_pf *pf,
4617 enum i40e_vsi_type type,
4618 struct i40e_vsi *uplink_vsi,
4619 uint16_t user_param)
4621 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4622 struct i40e_vsi *vsi;
4623 struct i40e_mac_filter_info filter;
4625 struct i40e_vsi_context ctxt;
4626 struct ether_addr broadcast =
4627 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4629 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4630 uplink_vsi == NULL) {
4632 "VSI setup failed, VSI link shouldn't be NULL");
4636 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4638 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4643 * 1.type is not MAIN and uplink vsi is not NULL
4644 * If uplink vsi didn't setup VEB, create one first under veb field
4645 * 2.type is SRIOV and the uplink is NULL
4646 * If floating VEB is NULL, create one veb under floating veb field
4649 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4650 uplink_vsi->veb == NULL) {
4651 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4653 if (uplink_vsi->veb == NULL) {
4654 PMD_DRV_LOG(ERR, "VEB setup failed");
4657 /* set ALLOWLOOPBACk on pf, when veb is created */
4658 i40e_enable_pf_lb(pf);
4661 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4662 pf->main_vsi->floating_veb == NULL) {
4663 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4665 if (pf->main_vsi->floating_veb == NULL) {
4666 PMD_DRV_LOG(ERR, "VEB setup failed");
4671 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4673 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4676 TAILQ_INIT(&vsi->mac_list);
4678 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4679 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4680 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4681 vsi->user_param = user_param;
4682 vsi->vlan_anti_spoof_on = 0;
4683 vsi->vlan_filter_on = 0;
4684 /* Allocate queues */
4685 switch (vsi->type) {
4686 case I40E_VSI_MAIN :
4687 vsi->nb_qps = pf->lan_nb_qps;
4689 case I40E_VSI_SRIOV :
4690 vsi->nb_qps = pf->vf_nb_qps;
4692 case I40E_VSI_VMDQ2:
4693 vsi->nb_qps = pf->vmdq_nb_qps;
4696 vsi->nb_qps = pf->fdir_nb_qps;
4702 * The filter status descriptor is reported in rx queue 0,
4703 * while the tx queue for fdir filter programming has no
4704 * such constraints, can be non-zero queues.
4705 * To simplify it, choose FDIR vsi use queue 0 pair.
4706 * To make sure it will use queue 0 pair, queue allocation
4707 * need be done before this function is called
4709 if (type != I40E_VSI_FDIR) {
4710 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4712 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4716 vsi->base_queue = ret;
4718 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4720 /* VF has MSIX interrupt in VF range, don't allocate here */
4721 if (type == I40E_VSI_MAIN) {
4722 ret = i40e_res_pool_alloc(&pf->msix_pool,
4723 RTE_MIN(vsi->nb_qps,
4724 RTE_MAX_RXTX_INTR_VEC_ID));
4726 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4728 goto fail_queue_alloc;
4730 vsi->msix_intr = ret;
4731 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4732 } else if (type != I40E_VSI_SRIOV) {
4733 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4735 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4736 goto fail_queue_alloc;
4738 vsi->msix_intr = ret;
4746 if (type == I40E_VSI_MAIN) {
4747 /* For main VSI, no need to add since it's default one */
4748 vsi->uplink_seid = pf->mac_seid;
4749 vsi->seid = pf->main_vsi_seid;
4750 /* Bind queues with specific MSIX interrupt */
4752 * Needs 2 interrupt at least, one for misc cause which will
4753 * enabled from OS side, Another for queues binding the
4754 * interrupt from device side only.
4757 /* Get default VSI parameters from hardware */
4758 memset(&ctxt, 0, sizeof(ctxt));
4759 ctxt.seid = vsi->seid;
4760 ctxt.pf_num = hw->pf_id;
4761 ctxt.uplink_seid = vsi->uplink_seid;
4763 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4764 if (ret != I40E_SUCCESS) {
4765 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4766 goto fail_msix_alloc;
4768 (void)rte_memcpy(&vsi->info, &ctxt.info,
4769 sizeof(struct i40e_aqc_vsi_properties_data));
4770 vsi->vsi_id = ctxt.vsi_number;
4771 vsi->info.valid_sections = 0;
4773 /* Configure tc, enabled TC0 only */
4774 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4776 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4777 goto fail_msix_alloc;
4780 /* TC, queue mapping */
4781 memset(&ctxt, 0, sizeof(ctxt));
4782 vsi->info.valid_sections |=
4783 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4784 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4785 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4786 (void)rte_memcpy(&ctxt.info, &vsi->info,
4787 sizeof(struct i40e_aqc_vsi_properties_data));
4788 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4789 I40E_DEFAULT_TCMAP);
4790 if (ret != I40E_SUCCESS) {
4792 "Failed to configure TC queue mapping");
4793 goto fail_msix_alloc;
4795 ctxt.seid = vsi->seid;
4796 ctxt.pf_num = hw->pf_id;
4797 ctxt.uplink_seid = vsi->uplink_seid;
4800 /* Update VSI parameters */
4801 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4802 if (ret != I40E_SUCCESS) {
4803 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4804 goto fail_msix_alloc;
4807 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4808 sizeof(vsi->info.tc_mapping));
4809 (void)rte_memcpy(&vsi->info.queue_mapping,
4810 &ctxt.info.queue_mapping,
4811 sizeof(vsi->info.queue_mapping));
4812 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4813 vsi->info.valid_sections = 0;
4815 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4819 * Updating default filter settings are necessary to prevent
4820 * reception of tagged packets.
4821 * Some old firmware configurations load a default macvlan
4822 * filter which accepts both tagged and untagged packets.
4823 * The updating is to use a normal filter instead if needed.
4824 * For NVM 4.2.2 or after, the updating is not needed anymore.
4825 * The firmware with correct configurations load the default
4826 * macvlan filter which is expected and cannot be removed.
4828 i40e_update_default_filter_setting(vsi);
4829 i40e_config_qinq(hw, vsi);
4830 } else if (type == I40E_VSI_SRIOV) {
4831 memset(&ctxt, 0, sizeof(ctxt));
4833 * For other VSI, the uplink_seid equals to uplink VSI's
4834 * uplink_seid since they share same VEB
4836 if (uplink_vsi == NULL)
4837 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4839 vsi->uplink_seid = uplink_vsi->uplink_seid;
4840 ctxt.pf_num = hw->pf_id;
4841 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4842 ctxt.uplink_seid = vsi->uplink_seid;
4843 ctxt.connection_type = 0x1;
4844 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4846 /* Use the VEB configuration if FW >= v5.0 */
4847 if (hw->aq.fw_maj_ver >= 5) {
4848 /* Configure switch ID */
4849 ctxt.info.valid_sections |=
4850 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4851 ctxt.info.switch_id =
4852 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4855 /* Configure port/vlan */
4856 ctxt.info.valid_sections |=
4857 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4858 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4859 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4860 hw->func_caps.enabled_tcmap);
4861 if (ret != I40E_SUCCESS) {
4863 "Failed to configure TC queue mapping");
4864 goto fail_msix_alloc;
4867 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4868 ctxt.info.valid_sections |=
4869 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4871 * Since VSI is not created yet, only configure parameter,
4872 * will add vsi below.
4875 i40e_config_qinq(hw, vsi);
4876 } else if (type == I40E_VSI_VMDQ2) {
4877 memset(&ctxt, 0, sizeof(ctxt));
4879 * For other VSI, the uplink_seid equals to uplink VSI's
4880 * uplink_seid since they share same VEB
4882 vsi->uplink_seid = uplink_vsi->uplink_seid;
4883 ctxt.pf_num = hw->pf_id;
4885 ctxt.uplink_seid = vsi->uplink_seid;
4886 ctxt.connection_type = 0x1;
4887 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4889 ctxt.info.valid_sections |=
4890 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4891 /* user_param carries flag to enable loop back */
4893 ctxt.info.switch_id =
4894 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4895 ctxt.info.switch_id |=
4896 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4899 /* Configure port/vlan */
4900 ctxt.info.valid_sections |=
4901 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4902 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4903 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4904 I40E_DEFAULT_TCMAP);
4905 if (ret != I40E_SUCCESS) {
4907 "Failed to configure TC queue mapping");
4908 goto fail_msix_alloc;
4910 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4911 ctxt.info.valid_sections |=
4912 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4913 } else if (type == I40E_VSI_FDIR) {
4914 memset(&ctxt, 0, sizeof(ctxt));
4915 vsi->uplink_seid = uplink_vsi->uplink_seid;
4916 ctxt.pf_num = hw->pf_id;
4918 ctxt.uplink_seid = vsi->uplink_seid;
4919 ctxt.connection_type = 0x1; /* regular data port */
4920 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4921 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4922 I40E_DEFAULT_TCMAP);
4923 if (ret != I40E_SUCCESS) {
4925 "Failed to configure TC queue mapping.");
4926 goto fail_msix_alloc;
4928 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4929 ctxt.info.valid_sections |=
4930 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4932 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4933 goto fail_msix_alloc;
4936 if (vsi->type != I40E_VSI_MAIN) {
4937 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4938 if (ret != I40E_SUCCESS) {
4939 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4940 hw->aq.asq_last_status);
4941 goto fail_msix_alloc;
4943 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4944 vsi->info.valid_sections = 0;
4945 vsi->seid = ctxt.seid;
4946 vsi->vsi_id = ctxt.vsi_number;
4947 vsi->sib_vsi_list.vsi = vsi;
4948 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4949 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4950 &vsi->sib_vsi_list, list);
4952 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4953 &vsi->sib_vsi_list, list);
4957 /* MAC/VLAN configuration */
4958 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4959 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4961 ret = i40e_vsi_add_mac(vsi, &filter);
4962 if (ret != I40E_SUCCESS) {
4963 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4964 goto fail_msix_alloc;
4967 /* Get VSI BW information */
4968 i40e_vsi_get_bw_config(vsi);
4971 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4973 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4979 /* Configure vlan filter on or off */
4981 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4984 struct i40e_mac_filter *f;
4986 struct i40e_mac_filter_info *mac_filter;
4987 enum rte_mac_filter_type desired_filter;
4988 int ret = I40E_SUCCESS;
4991 /* Filter to match MAC and VLAN */
4992 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4994 /* Filter to match only MAC */
4995 desired_filter = RTE_MAC_PERFECT_MATCH;
5000 mac_filter = rte_zmalloc("mac_filter_info_data",
5001 num * sizeof(*mac_filter), 0);
5002 if (mac_filter == NULL) {
5003 PMD_DRV_LOG(ERR, "failed to allocate memory");
5004 return I40E_ERR_NO_MEMORY;
5009 /* Remove all existing mac */
5010 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5011 mac_filter[i] = f->mac_info;
5012 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5014 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5015 on ? "enable" : "disable");
5021 /* Override with new filter */
5022 for (i = 0; i < num; i++) {
5023 mac_filter[i].filter_type = desired_filter;
5024 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5026 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5027 on ? "enable" : "disable");
5033 rte_free(mac_filter);
5037 /* Configure vlan stripping on or off */
5039 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5041 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5042 struct i40e_vsi_context ctxt;
5044 int ret = I40E_SUCCESS;
5046 /* Check if it has been already on or off */
5047 if (vsi->info.valid_sections &
5048 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5050 if ((vsi->info.port_vlan_flags &
5051 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5052 return 0; /* already on */
5054 if ((vsi->info.port_vlan_flags &
5055 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5056 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5057 return 0; /* already off */
5062 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5064 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5065 vsi->info.valid_sections =
5066 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5067 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5068 vsi->info.port_vlan_flags |= vlan_flags;
5069 ctxt.seid = vsi->seid;
5070 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5071 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5073 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5074 on ? "enable" : "disable");
5080 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5082 struct rte_eth_dev_data *data = dev->data;
5086 /* Apply vlan offload setting */
5087 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5088 i40e_vlan_offload_set(dev, mask);
5090 /* Apply double-vlan setting, not implemented yet */
5092 /* Apply pvid setting */
5093 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5094 data->dev_conf.txmode.hw_vlan_insert_pvid);
5096 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5102 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5104 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5106 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5110 i40e_update_flow_control(struct i40e_hw *hw)
5112 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5113 struct i40e_link_status link_status;
5114 uint32_t rxfc = 0, txfc = 0, reg;
5118 memset(&link_status, 0, sizeof(link_status));
5119 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5120 if (ret != I40E_SUCCESS) {
5121 PMD_DRV_LOG(ERR, "Failed to get link status information");
5122 goto write_reg; /* Disable flow control */
5125 an_info = hw->phy.link_info.an_info;
5126 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5127 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5128 ret = I40E_ERR_NOT_READY;
5129 goto write_reg; /* Disable flow control */
5132 * If link auto negotiation is enabled, flow control needs to
5133 * be configured according to it
5135 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5136 case I40E_LINK_PAUSE_RXTX:
5139 hw->fc.current_mode = I40E_FC_FULL;
5141 case I40E_AQ_LINK_PAUSE_RX:
5143 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5145 case I40E_AQ_LINK_PAUSE_TX:
5147 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5150 hw->fc.current_mode = I40E_FC_NONE;
5155 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5156 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5157 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5158 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5159 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5160 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5167 i40e_pf_setup(struct i40e_pf *pf)
5169 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5170 struct i40e_filter_control_settings settings;
5171 struct i40e_vsi *vsi;
5174 /* Clear all stats counters */
5175 pf->offset_loaded = FALSE;
5176 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5177 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5179 ret = i40e_pf_get_switch_config(pf);
5180 if (ret != I40E_SUCCESS) {
5181 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5184 if (pf->flags & I40E_FLAG_FDIR) {
5185 /* make queue allocated first, let FDIR use queue pair 0*/
5186 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5187 if (ret != I40E_FDIR_QUEUE_ID) {
5189 "queue allocation fails for FDIR: ret =%d",
5191 pf->flags &= ~I40E_FLAG_FDIR;
5194 /* main VSI setup */
5195 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5197 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5198 return I40E_ERR_NOT_READY;
5202 /* Configure filter control */
5203 memset(&settings, 0, sizeof(settings));
5204 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5205 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5206 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5207 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5209 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5210 hw->func_caps.rss_table_size);
5211 return I40E_ERR_PARAM;
5213 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5214 hw->func_caps.rss_table_size);
5215 pf->hash_lut_size = hw->func_caps.rss_table_size;
5217 /* Enable ethtype and macvlan filters */
5218 settings.enable_ethtype = TRUE;
5219 settings.enable_macvlan = TRUE;
5220 ret = i40e_set_filter_control(hw, &settings);
5222 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5225 /* Update flow control according to the auto negotiation */
5226 i40e_update_flow_control(hw);
5228 return I40E_SUCCESS;
5232 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5238 * Set or clear TX Queue Disable flags,
5239 * which is required by hardware.
5241 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5242 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5244 /* Wait until the request is finished */
5245 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5246 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5247 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5248 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5249 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5255 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5256 return I40E_SUCCESS; /* already on, skip next steps */
5258 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5259 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5261 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5262 return I40E_SUCCESS; /* already off, skip next steps */
5263 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5265 /* Write the register */
5266 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5267 /* Check the result */
5268 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5269 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5270 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5272 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5273 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5276 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5277 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5281 /* Check if it is timeout */
5282 if (j >= I40E_CHK_Q_ENA_COUNT) {
5283 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5284 (on ? "enable" : "disable"), q_idx);
5285 return I40E_ERR_TIMEOUT;
5288 return I40E_SUCCESS;
5291 /* Swith on or off the tx queues */
5293 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5295 struct rte_eth_dev_data *dev_data = pf->dev_data;
5296 struct i40e_tx_queue *txq;
5297 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5301 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5302 txq = dev_data->tx_queues[i];
5303 /* Don't operate the queue if not configured or
5304 * if starting only per queue */
5305 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5308 ret = i40e_dev_tx_queue_start(dev, i);
5310 ret = i40e_dev_tx_queue_stop(dev, i);
5311 if ( ret != I40E_SUCCESS)
5315 return I40E_SUCCESS;
5319 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5324 /* Wait until the request is finished */
5325 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5326 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5327 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5328 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5329 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5334 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5335 return I40E_SUCCESS; /* Already on, skip next steps */
5336 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5338 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5339 return I40E_SUCCESS; /* Already off, skip next steps */
5340 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5343 /* Write the register */
5344 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5345 /* Check the result */
5346 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5347 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5348 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5350 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5351 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5354 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5355 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5360 /* Check if it is timeout */
5361 if (j >= I40E_CHK_Q_ENA_COUNT) {
5362 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5363 (on ? "enable" : "disable"), q_idx);
5364 return I40E_ERR_TIMEOUT;
5367 return I40E_SUCCESS;
5369 /* Switch on or off the rx queues */
5371 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5373 struct rte_eth_dev_data *dev_data = pf->dev_data;
5374 struct i40e_rx_queue *rxq;
5375 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5379 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5380 rxq = dev_data->rx_queues[i];
5381 /* Don't operate the queue if not configured or
5382 * if starting only per queue */
5383 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5386 ret = i40e_dev_rx_queue_start(dev, i);
5388 ret = i40e_dev_rx_queue_stop(dev, i);
5389 if (ret != I40E_SUCCESS)
5393 return I40E_SUCCESS;
5396 /* Switch on or off all the rx/tx queues */
5398 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5403 /* enable rx queues before enabling tx queues */
5404 ret = i40e_dev_switch_rx_queues(pf, on);
5406 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5409 ret = i40e_dev_switch_tx_queues(pf, on);
5411 /* Stop tx queues before stopping rx queues */
5412 ret = i40e_dev_switch_tx_queues(pf, on);
5414 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5417 ret = i40e_dev_switch_rx_queues(pf, on);
5423 /* Initialize VSI for TX */
5425 i40e_dev_tx_init(struct i40e_pf *pf)
5427 struct rte_eth_dev_data *data = pf->dev_data;
5429 uint32_t ret = I40E_SUCCESS;
5430 struct i40e_tx_queue *txq;
5432 for (i = 0; i < data->nb_tx_queues; i++) {
5433 txq = data->tx_queues[i];
5434 if (!txq || !txq->q_set)
5436 ret = i40e_tx_queue_init(txq);
5437 if (ret != I40E_SUCCESS)
5440 if (ret == I40E_SUCCESS)
5441 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5447 /* Initialize VSI for RX */
5449 i40e_dev_rx_init(struct i40e_pf *pf)
5451 struct rte_eth_dev_data *data = pf->dev_data;
5452 int ret = I40E_SUCCESS;
5454 struct i40e_rx_queue *rxq;
5456 i40e_pf_config_mq_rx(pf);
5457 for (i = 0; i < data->nb_rx_queues; i++) {
5458 rxq = data->rx_queues[i];
5459 if (!rxq || !rxq->q_set)
5462 ret = i40e_rx_queue_init(rxq);
5463 if (ret != I40E_SUCCESS) {
5465 "Failed to do RX queue initialization");
5469 if (ret == I40E_SUCCESS)
5470 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5477 i40e_dev_rxtx_init(struct i40e_pf *pf)
5481 err = i40e_dev_tx_init(pf);
5483 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5486 err = i40e_dev_rx_init(pf);
5488 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5496 i40e_vmdq_setup(struct rte_eth_dev *dev)
5498 struct rte_eth_conf *conf = &dev->data->dev_conf;
5499 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5500 int i, err, conf_vsis, j, loop;
5501 struct i40e_vsi *vsi;
5502 struct i40e_vmdq_info *vmdq_info;
5503 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5504 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5507 * Disable interrupt to avoid message from VF. Furthermore, it will
5508 * avoid race condition in VSI creation/destroy.
5510 i40e_pf_disable_irq0(hw);
5512 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5513 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5517 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5518 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5519 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5520 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5521 pf->max_nb_vmdq_vsi);
5525 if (pf->vmdq != NULL) {
5526 PMD_INIT_LOG(INFO, "VMDQ already configured");
5530 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5531 sizeof(*vmdq_info) * conf_vsis, 0);
5533 if (pf->vmdq == NULL) {
5534 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5538 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5540 /* Create VMDQ VSI */
5541 for (i = 0; i < conf_vsis; i++) {
5542 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5543 vmdq_conf->enable_loop_back);
5545 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5549 vmdq_info = &pf->vmdq[i];
5551 vmdq_info->vsi = vsi;
5553 pf->nb_cfg_vmdq_vsi = conf_vsis;
5555 /* Configure Vlan */
5556 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5557 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5558 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5559 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5560 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5561 vmdq_conf->pool_map[i].vlan_id, j);
5563 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5564 vmdq_conf->pool_map[i].vlan_id);
5566 PMD_INIT_LOG(ERR, "Failed to add vlan");
5574 i40e_pf_enable_irq0(hw);
5579 for (i = 0; i < conf_vsis; i++)
5580 if (pf->vmdq[i].vsi == NULL)
5583 i40e_vsi_release(pf->vmdq[i].vsi);
5587 i40e_pf_enable_irq0(hw);
5592 i40e_stat_update_32(struct i40e_hw *hw,
5600 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5604 if (new_data >= *offset)
5605 *stat = (uint64_t)(new_data - *offset);
5607 *stat = (uint64_t)((new_data +
5608 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5612 i40e_stat_update_48(struct i40e_hw *hw,
5621 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5622 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5623 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5628 if (new_data >= *offset)
5629 *stat = new_data - *offset;
5631 *stat = (uint64_t)((new_data +
5632 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5634 *stat &= I40E_48_BIT_MASK;
5639 i40e_pf_disable_irq0(struct i40e_hw *hw)
5641 /* Disable all interrupt types */
5642 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5643 I40E_WRITE_FLUSH(hw);
5648 i40e_pf_enable_irq0(struct i40e_hw *hw)
5650 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5651 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5652 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5653 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5654 I40E_WRITE_FLUSH(hw);
5658 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5660 /* read pending request and disable first */
5661 i40e_pf_disable_irq0(hw);
5662 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5663 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5664 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5667 /* Link no queues with irq0 */
5668 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5669 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5673 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5676 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5679 uint32_t index, offset, val;
5684 * Try to find which VF trigger a reset, use absolute VF id to access
5685 * since the reg is global register.
5687 for (i = 0; i < pf->vf_num; i++) {
5688 abs_vf_id = hw->func_caps.vf_base_id + i;
5689 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5690 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5691 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5692 /* VFR event occured */
5693 if (val & (0x1 << offset)) {
5696 /* Clear the event first */
5697 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5699 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5701 * Only notify a VF reset event occured,
5702 * don't trigger another SW reset
5704 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5705 if (ret != I40E_SUCCESS)
5706 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5712 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5714 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5715 struct i40e_virtchnl_pf_event event;
5718 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5719 event.event_data.link_event.link_status =
5720 dev->data->dev_link.link_status;
5721 event.event_data.link_event.link_speed =
5722 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5724 for (i = 0; i < pf->vf_num; i++)
5725 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5726 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5730 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5732 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5733 struct i40e_arq_event_info info;
5734 uint16_t pending, opcode;
5737 info.buf_len = I40E_AQ_BUF_SZ;
5738 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5739 if (!info.msg_buf) {
5740 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5746 ret = i40e_clean_arq_element(hw, &info, &pending);
5748 if (ret != I40E_SUCCESS) {
5750 "Failed to read msg from AdminQ, aq_err: %u",
5751 hw->aq.asq_last_status);
5754 opcode = rte_le_to_cpu_16(info.desc.opcode);
5757 case i40e_aqc_opc_send_msg_to_pf:
5758 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5759 i40e_pf_host_handle_vf_msg(dev,
5760 rte_le_to_cpu_16(info.desc.retval),
5761 rte_le_to_cpu_32(info.desc.cookie_high),
5762 rte_le_to_cpu_32(info.desc.cookie_low),
5766 case i40e_aqc_opc_get_link_status:
5767 ret = i40e_dev_link_update(dev, 0);
5769 i40e_notify_all_vfs_link_status(dev);
5770 _rte_eth_dev_callback_process(dev,
5771 RTE_ETH_EVENT_INTR_LSC, NULL);
5775 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5780 rte_free(info.msg_buf);
5784 * Interrupt handler triggered by NIC for handling
5785 * specific interrupt.
5788 * Pointer to interrupt handle.
5790 * The address of parameter (struct rte_eth_dev *) regsitered before.
5796 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5799 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5800 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803 /* Disable interrupt */
5804 i40e_pf_disable_irq0(hw);
5806 /* read out interrupt causes */
5807 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5809 /* No interrupt event indicated */
5810 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5811 PMD_DRV_LOG(INFO, "No interrupt event");
5814 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5815 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5816 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5817 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5818 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5819 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5820 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5821 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5822 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5823 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5824 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5825 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5826 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5827 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5828 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5829 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5831 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5832 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5833 i40e_dev_handle_vfr_event(dev);
5835 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5836 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5837 i40e_dev_handle_aq_msg(dev);
5841 /* Enable interrupt */
5842 i40e_pf_enable_irq0(hw);
5843 rte_intr_enable(intr_handle);
5847 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5848 struct i40e_macvlan_filter *filter,
5851 int ele_num, ele_buff_size;
5852 int num, actual_num, i;
5854 int ret = I40E_SUCCESS;
5855 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5856 struct i40e_aqc_add_macvlan_element_data *req_list;
5858 if (filter == NULL || total == 0)
5859 return I40E_ERR_PARAM;
5860 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5861 ele_buff_size = hw->aq.asq_buf_size;
5863 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5864 if (req_list == NULL) {
5865 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5866 return I40E_ERR_NO_MEMORY;
5871 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5872 memset(req_list, 0, ele_buff_size);
5874 for (i = 0; i < actual_num; i++) {
5875 (void)rte_memcpy(req_list[i].mac_addr,
5876 &filter[num + i].macaddr, ETH_ADDR_LEN);
5877 req_list[i].vlan_tag =
5878 rte_cpu_to_le_16(filter[num + i].vlan_id);
5880 switch (filter[num + i].filter_type) {
5881 case RTE_MAC_PERFECT_MATCH:
5882 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5883 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5885 case RTE_MACVLAN_PERFECT_MATCH:
5886 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5888 case RTE_MAC_HASH_MATCH:
5889 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5890 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5892 case RTE_MACVLAN_HASH_MATCH:
5893 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5896 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5897 ret = I40E_ERR_PARAM;
5901 req_list[i].queue_number = 0;
5903 req_list[i].flags = rte_cpu_to_le_16(flags);
5906 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5908 if (ret != I40E_SUCCESS) {
5909 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5913 } while (num < total);
5921 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5922 struct i40e_macvlan_filter *filter,
5925 int ele_num, ele_buff_size;
5926 int num, actual_num, i;
5928 int ret = I40E_SUCCESS;
5929 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5930 struct i40e_aqc_remove_macvlan_element_data *req_list;
5932 if (filter == NULL || total == 0)
5933 return I40E_ERR_PARAM;
5935 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5936 ele_buff_size = hw->aq.asq_buf_size;
5938 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5939 if (req_list == NULL) {
5940 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5941 return I40E_ERR_NO_MEMORY;
5946 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5947 memset(req_list, 0, ele_buff_size);
5949 for (i = 0; i < actual_num; i++) {
5950 (void)rte_memcpy(req_list[i].mac_addr,
5951 &filter[num + i].macaddr, ETH_ADDR_LEN);
5952 req_list[i].vlan_tag =
5953 rte_cpu_to_le_16(filter[num + i].vlan_id);
5955 switch (filter[num + i].filter_type) {
5956 case RTE_MAC_PERFECT_MATCH:
5957 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5958 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5960 case RTE_MACVLAN_PERFECT_MATCH:
5961 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5963 case RTE_MAC_HASH_MATCH:
5964 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5965 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5967 case RTE_MACVLAN_HASH_MATCH:
5968 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5971 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5972 ret = I40E_ERR_PARAM;
5975 req_list[i].flags = rte_cpu_to_le_16(flags);
5978 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5980 if (ret != I40E_SUCCESS) {
5981 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5985 } while (num < total);
5992 /* Find out specific MAC filter */
5993 static struct i40e_mac_filter *
5994 i40e_find_mac_filter(struct i40e_vsi *vsi,
5995 struct ether_addr *macaddr)
5997 struct i40e_mac_filter *f;
5999 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6000 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6008 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6011 uint32_t vid_idx, vid_bit;
6013 if (vlan_id > ETH_VLAN_ID_MAX)
6016 vid_idx = I40E_VFTA_IDX(vlan_id);
6017 vid_bit = I40E_VFTA_BIT(vlan_id);
6019 if (vsi->vfta[vid_idx] & vid_bit)
6026 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6027 uint16_t vlan_id, bool on)
6029 uint32_t vid_idx, vid_bit;
6031 vid_idx = I40E_VFTA_IDX(vlan_id);
6032 vid_bit = I40E_VFTA_BIT(vlan_id);
6035 vsi->vfta[vid_idx] |= vid_bit;
6037 vsi->vfta[vid_idx] &= ~vid_bit;
6041 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6042 uint16_t vlan_id, bool on)
6044 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6045 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6048 if (vlan_id > ETH_VLAN_ID_MAX)
6051 i40e_store_vlan_filter(vsi, vlan_id, on);
6053 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6056 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6059 ret = i40e_aq_add_vlan(hw, vsi->seid,
6060 &vlan_data, 1, NULL);
6061 if (ret != I40E_SUCCESS)
6062 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6064 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6065 &vlan_data, 1, NULL);
6066 if (ret != I40E_SUCCESS)
6068 "Failed to remove vlan filter");
6073 * Find all vlan options for specific mac addr,
6074 * return with actual vlan found.
6077 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6078 struct i40e_macvlan_filter *mv_f,
6079 int num, struct ether_addr *addr)
6085 * Not to use i40e_find_vlan_filter to decrease the loop time,
6086 * although the code looks complex.
6088 if (num < vsi->vlan_num)
6089 return I40E_ERR_PARAM;
6092 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6094 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6095 if (vsi->vfta[j] & (1 << k)) {
6098 "vlan number doesn't match");
6099 return I40E_ERR_PARAM;
6101 (void)rte_memcpy(&mv_f[i].macaddr,
6102 addr, ETH_ADDR_LEN);
6104 j * I40E_UINT32_BIT_SIZE + k;
6110 return I40E_SUCCESS;
6114 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6115 struct i40e_macvlan_filter *mv_f,
6120 struct i40e_mac_filter *f;
6122 if (num < vsi->mac_num)
6123 return I40E_ERR_PARAM;
6125 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6127 PMD_DRV_LOG(ERR, "buffer number not match");
6128 return I40E_ERR_PARAM;
6130 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6132 mv_f[i].vlan_id = vlan;
6133 mv_f[i].filter_type = f->mac_info.filter_type;
6137 return I40E_SUCCESS;
6141 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6144 struct i40e_mac_filter *f;
6145 struct i40e_macvlan_filter *mv_f;
6146 int ret = I40E_SUCCESS;
6148 if (vsi == NULL || vsi->mac_num == 0)
6149 return I40E_ERR_PARAM;
6151 /* Case that no vlan is set */
6152 if (vsi->vlan_num == 0)
6155 num = vsi->mac_num * vsi->vlan_num;
6157 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6159 PMD_DRV_LOG(ERR, "failed to allocate memory");
6160 return I40E_ERR_NO_MEMORY;
6164 if (vsi->vlan_num == 0) {
6165 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6166 (void)rte_memcpy(&mv_f[i].macaddr,
6167 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6168 mv_f[i].filter_type = f->mac_info.filter_type;
6169 mv_f[i].vlan_id = 0;
6173 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6174 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6175 vsi->vlan_num, &f->mac_info.mac_addr);
6176 if (ret != I40E_SUCCESS)
6178 for (j = i; j < i + vsi->vlan_num; j++)
6179 mv_f[j].filter_type = f->mac_info.filter_type;
6184 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6192 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6194 struct i40e_macvlan_filter *mv_f;
6196 int ret = I40E_SUCCESS;
6198 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6199 return I40E_ERR_PARAM;
6201 /* If it's already set, just return */
6202 if (i40e_find_vlan_filter(vsi,vlan))
6203 return I40E_SUCCESS;
6205 mac_num = vsi->mac_num;
6208 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6209 return I40E_ERR_PARAM;
6212 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6215 PMD_DRV_LOG(ERR, "failed to allocate memory");
6216 return I40E_ERR_NO_MEMORY;
6219 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6221 if (ret != I40E_SUCCESS)
6224 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6226 if (ret != I40E_SUCCESS)
6229 i40e_set_vlan_filter(vsi, vlan, 1);
6239 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6241 struct i40e_macvlan_filter *mv_f;
6243 int ret = I40E_SUCCESS;
6246 * Vlan 0 is the generic filter for untagged packets
6247 * and can't be removed.
6249 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6250 return I40E_ERR_PARAM;
6252 /* If can't find it, just return */
6253 if (!i40e_find_vlan_filter(vsi, vlan))
6254 return I40E_ERR_PARAM;
6256 mac_num = vsi->mac_num;
6259 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6260 return I40E_ERR_PARAM;
6263 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6266 PMD_DRV_LOG(ERR, "failed to allocate memory");
6267 return I40E_ERR_NO_MEMORY;
6270 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6272 if (ret != I40E_SUCCESS)
6275 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6277 if (ret != I40E_SUCCESS)
6280 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6281 if (vsi->vlan_num == 1) {
6282 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6283 if (ret != I40E_SUCCESS)
6286 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6287 if (ret != I40E_SUCCESS)
6291 i40e_set_vlan_filter(vsi, vlan, 0);
6301 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6303 struct i40e_mac_filter *f;
6304 struct i40e_macvlan_filter *mv_f;
6305 int i, vlan_num = 0;
6306 int ret = I40E_SUCCESS;
6308 /* If it's add and we've config it, return */
6309 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6311 return I40E_SUCCESS;
6312 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6313 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6316 * If vlan_num is 0, that's the first time to add mac,
6317 * set mask for vlan_id 0.
6319 if (vsi->vlan_num == 0) {
6320 i40e_set_vlan_filter(vsi, 0, 1);
6323 vlan_num = vsi->vlan_num;
6324 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6325 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6328 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6330 PMD_DRV_LOG(ERR, "failed to allocate memory");
6331 return I40E_ERR_NO_MEMORY;
6334 for (i = 0; i < vlan_num; i++) {
6335 mv_f[i].filter_type = mac_filter->filter_type;
6336 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6340 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6341 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6342 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6343 &mac_filter->mac_addr);
6344 if (ret != I40E_SUCCESS)
6348 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6349 if (ret != I40E_SUCCESS)
6352 /* Add the mac addr into mac list */
6353 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6355 PMD_DRV_LOG(ERR, "failed to allocate memory");
6356 ret = I40E_ERR_NO_MEMORY;
6359 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6361 f->mac_info.filter_type = mac_filter->filter_type;
6362 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6373 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6375 struct i40e_mac_filter *f;
6376 struct i40e_macvlan_filter *mv_f;
6378 enum rte_mac_filter_type filter_type;
6379 int ret = I40E_SUCCESS;
6381 /* Can't find it, return an error */
6382 f = i40e_find_mac_filter(vsi, addr);
6384 return I40E_ERR_PARAM;
6386 vlan_num = vsi->vlan_num;
6387 filter_type = f->mac_info.filter_type;
6388 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6389 filter_type == RTE_MACVLAN_HASH_MATCH) {
6390 if (vlan_num == 0) {
6391 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6392 return I40E_ERR_PARAM;
6394 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6395 filter_type == RTE_MAC_HASH_MATCH)
6398 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6400 PMD_DRV_LOG(ERR, "failed to allocate memory");
6401 return I40E_ERR_NO_MEMORY;
6404 for (i = 0; i < vlan_num; i++) {
6405 mv_f[i].filter_type = filter_type;
6406 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6409 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6410 filter_type == RTE_MACVLAN_HASH_MATCH) {
6411 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6412 if (ret != I40E_SUCCESS)
6416 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6417 if (ret != I40E_SUCCESS)
6420 /* Remove the mac addr into mac list */
6421 TAILQ_REMOVE(&vsi->mac_list, f, next);
6431 /* Configure hash enable flags for RSS */
6433 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6440 if (flags & ETH_RSS_FRAG_IPV4)
6441 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6442 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6443 if (type == I40E_MAC_X722) {
6444 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6445 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6447 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6449 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6450 if (type == I40E_MAC_X722) {
6451 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6452 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6453 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6455 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6457 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6458 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6459 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6460 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6461 if (flags & ETH_RSS_FRAG_IPV6)
6462 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6463 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6464 if (type == I40E_MAC_X722) {
6465 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6466 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6468 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6470 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6471 if (type == I40E_MAC_X722) {
6472 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6473 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6474 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6476 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6478 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6479 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6480 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6481 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6482 if (flags & ETH_RSS_L2_PAYLOAD)
6483 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6488 /* Parse the hash enable flags */
6490 i40e_parse_hena(uint64_t flags)
6492 uint64_t rss_hf = 0;
6496 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6497 rss_hf |= ETH_RSS_FRAG_IPV4;
6498 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6499 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6500 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6501 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6502 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6503 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6504 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6505 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6506 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6507 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6508 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6509 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6510 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6511 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6512 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6513 rss_hf |= ETH_RSS_FRAG_IPV6;
6514 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6515 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6516 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6517 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6518 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6519 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6520 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6521 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6522 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6523 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6524 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6525 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6526 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6527 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6528 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6529 rss_hf |= ETH_RSS_L2_PAYLOAD;
6536 i40e_pf_disable_rss(struct i40e_pf *pf)
6538 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6541 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6542 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6543 if (hw->mac.type == I40E_MAC_X722)
6544 hena &= ~I40E_RSS_HENA_ALL_X722;
6546 hena &= ~I40E_RSS_HENA_ALL;
6547 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6548 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6549 I40E_WRITE_FLUSH(hw);
6553 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6555 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6556 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6559 if (!key || key_len == 0) {
6560 PMD_DRV_LOG(DEBUG, "No key to be configured");
6562 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6564 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6568 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6569 struct i40e_aqc_get_set_rss_key_data *key_dw =
6570 (struct i40e_aqc_get_set_rss_key_data *)key;
6572 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6574 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6576 uint32_t *hash_key = (uint32_t *)key;
6579 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6580 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6581 I40E_WRITE_FLUSH(hw);
6588 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6590 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6591 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6594 if (!key || !key_len)
6597 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6598 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6599 (struct i40e_aqc_get_set_rss_key_data *)key);
6601 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6605 uint32_t *key_dw = (uint32_t *)key;
6608 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6609 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6611 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6617 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6619 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6624 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6625 rss_conf->rss_key_len);
6629 rss_hf = rss_conf->rss_hf;
6630 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6631 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6632 if (hw->mac.type == I40E_MAC_X722)
6633 hena &= ~I40E_RSS_HENA_ALL_X722;
6635 hena &= ~I40E_RSS_HENA_ALL;
6636 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6637 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6638 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6639 I40E_WRITE_FLUSH(hw);
6645 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6646 struct rte_eth_rss_conf *rss_conf)
6648 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6649 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6650 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6653 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6654 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6655 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6656 ? I40E_RSS_HENA_ALL_X722
6657 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6658 if (rss_hf != 0) /* Enable RSS */
6660 return 0; /* Nothing to do */
6663 if (rss_hf == 0) /* Disable RSS */
6666 return i40e_hw_rss_hash_set(pf, rss_conf);
6670 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6671 struct rte_eth_rss_conf *rss_conf)
6673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6674 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6678 &rss_conf->rss_key_len);
6680 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6681 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6682 rss_conf->rss_hf = i40e_parse_hena(hena);
6688 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6690 switch (filter_type) {
6691 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6692 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6694 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6695 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6697 case RTE_TUNNEL_FILTER_IMAC_TENID:
6698 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6700 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6701 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6703 case ETH_TUNNEL_FILTER_IMAC:
6704 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6706 case ETH_TUNNEL_FILTER_OIP:
6707 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6709 case ETH_TUNNEL_FILTER_IIP:
6710 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6713 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6720 /* Convert tunnel filter structure */
6722 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6724 struct i40e_tunnel_filter *tunnel_filter)
6726 ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6727 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6728 ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6729 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6730 tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6731 if ((rte_le_to_cpu_16(cld_filter->flags) &
6732 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6733 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6734 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6736 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6737 tunnel_filter->input.flags = cld_filter->flags;
6738 tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6739 tunnel_filter->queue = cld_filter->queue_number;
6744 /* Check if there exists the tunnel filter */
6745 struct i40e_tunnel_filter *
6746 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6747 const struct i40e_tunnel_filter_input *input)
6751 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6755 return tunnel_rule->hash_map[ret];
6758 /* Add a tunnel filter into the SW list */
6760 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6761 struct i40e_tunnel_filter *tunnel_filter)
6763 struct i40e_tunnel_rule *rule = &pf->tunnel;
6766 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6769 "Failed to insert tunnel filter to hash table %d!",
6773 rule->hash_map[ret] = tunnel_filter;
6775 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6780 /* Delete a tunnel filter from the SW list */
6782 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6783 struct i40e_tunnel_filter_input *input)
6785 struct i40e_tunnel_rule *rule = &pf->tunnel;
6786 struct i40e_tunnel_filter *tunnel_filter;
6789 ret = rte_hash_del_key(rule->hash_table, input);
6792 "Failed to delete tunnel filter to hash table %d!",
6796 tunnel_filter = rule->hash_map[ret];
6797 rule->hash_map[ret] = NULL;
6799 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6800 rte_free(tunnel_filter);
6806 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6807 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6812 uint8_t i, tun_type = 0;
6813 /* internal varialbe to convert ipv6 byte order */
6814 uint32_t convert_ipv6[4];
6816 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6817 struct i40e_vsi *vsi = pf->main_vsi;
6818 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6819 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6820 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6821 struct i40e_tunnel_filter *tunnel, *node;
6822 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6824 cld_filter = rte_zmalloc("tunnel_filter",
6825 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6828 if (NULL == cld_filter) {
6829 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6832 pfilter = cld_filter;
6834 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6835 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6837 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6838 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6839 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6840 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6841 rte_memcpy(&pfilter->ipaddr.v4.data,
6842 &rte_cpu_to_le_32(ipv4_addr),
6843 sizeof(pfilter->ipaddr.v4.data));
6845 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6846 for (i = 0; i < 4; i++) {
6848 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6850 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6851 sizeof(pfilter->ipaddr.v6.data));
6854 /* check tunneled type */
6855 switch (tunnel_filter->tunnel_type) {
6856 case RTE_TUNNEL_TYPE_VXLAN:
6857 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6859 case RTE_TUNNEL_TYPE_NVGRE:
6860 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6862 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6863 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6866 /* Other tunnel types is not supported. */
6867 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6868 rte_free(cld_filter);
6872 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6875 rte_free(cld_filter);
6879 pfilter->flags |= rte_cpu_to_le_16(
6880 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6881 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6882 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6883 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6885 /* Check if there is the filter in SW list */
6886 memset(&check_filter, 0, sizeof(check_filter));
6887 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6888 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6890 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6894 if (!add && !node) {
6895 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6900 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6902 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6905 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6906 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6907 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6909 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6912 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6915 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6918 rte_free(cld_filter);
6923 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6927 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6928 if (pf->vxlan_ports[i] == port)
6936 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6940 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6942 idx = i40e_get_vxlan_port_idx(pf, port);
6944 /* Check if port already exists */
6946 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6950 /* Now check if there is space to add the new port */
6951 idx = i40e_get_vxlan_port_idx(pf, 0);
6954 "Maximum number of UDP ports reached, not adding port %d",
6959 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6962 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6966 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6969 /* New port: add it and mark its index in the bitmap */
6970 pf->vxlan_ports[idx] = port;
6971 pf->vxlan_bitmap |= (1 << idx);
6973 if (!(pf->flags & I40E_FLAG_VXLAN))
6974 pf->flags |= I40E_FLAG_VXLAN;
6980 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6983 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6985 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6986 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6990 idx = i40e_get_vxlan_port_idx(pf, port);
6993 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6997 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6998 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7002 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7005 pf->vxlan_ports[idx] = 0;
7006 pf->vxlan_bitmap &= ~(1 << idx);
7008 if (!pf->vxlan_bitmap)
7009 pf->flags &= ~I40E_FLAG_VXLAN;
7014 /* Add UDP tunneling port */
7016 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7017 struct rte_eth_udp_tunnel *udp_tunnel)
7020 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7022 if (udp_tunnel == NULL)
7025 switch (udp_tunnel->prot_type) {
7026 case RTE_TUNNEL_TYPE_VXLAN:
7027 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7030 case RTE_TUNNEL_TYPE_GENEVE:
7031 case RTE_TUNNEL_TYPE_TEREDO:
7032 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7037 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7045 /* Remove UDP tunneling port */
7047 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7048 struct rte_eth_udp_tunnel *udp_tunnel)
7051 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7053 if (udp_tunnel == NULL)
7056 switch (udp_tunnel->prot_type) {
7057 case RTE_TUNNEL_TYPE_VXLAN:
7058 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7060 case RTE_TUNNEL_TYPE_GENEVE:
7061 case RTE_TUNNEL_TYPE_TEREDO:
7062 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7066 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7074 /* Calculate the maximum number of contiguous PF queues that are configured */
7076 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7078 struct rte_eth_dev_data *data = pf->dev_data;
7080 struct i40e_rx_queue *rxq;
7083 for (i = 0; i < pf->lan_nb_qps; i++) {
7084 rxq = data->rx_queues[i];
7085 if (rxq && rxq->q_set)
7096 i40e_pf_config_rss(struct i40e_pf *pf)
7098 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7099 struct rte_eth_rss_conf rss_conf;
7100 uint32_t i, lut = 0;
7104 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7105 * It's necessary to calulate the actual PF queues that are configured.
7107 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7108 num = i40e_pf_calc_configured_queues_num(pf);
7110 num = pf->dev_data->nb_rx_queues;
7112 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7113 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7117 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7121 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7124 lut = (lut << 8) | (j & ((0x1 <<
7125 hw->func_caps.rss_table_entry_width) - 1));
7127 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7130 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7131 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7132 i40e_pf_disable_rss(pf);
7135 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7136 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7137 /* Random default keys */
7138 static uint32_t rss_key_default[] = {0x6b793944,
7139 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7140 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7141 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7143 rss_conf.rss_key = (uint8_t *)rss_key_default;
7144 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7148 return i40e_hw_rss_hash_set(pf, &rss_conf);
7152 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7153 struct rte_eth_tunnel_filter_conf *filter)
7155 if (pf == NULL || filter == NULL) {
7156 PMD_DRV_LOG(ERR, "Invalid parameter");
7160 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7161 PMD_DRV_LOG(ERR, "Invalid queue ID");
7165 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7166 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7170 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7171 (is_zero_ether_addr(&filter->outer_mac))) {
7172 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7176 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7177 (is_zero_ether_addr(&filter->inner_mac))) {
7178 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7185 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7186 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7188 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7193 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7194 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7197 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7198 } else if (len == 4) {
7199 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7201 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7206 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7213 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7214 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7220 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7227 switch (cfg->cfg_type) {
7228 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7229 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7232 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7240 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7241 enum rte_filter_op filter_op,
7244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7245 int ret = I40E_ERR_PARAM;
7247 switch (filter_op) {
7248 case RTE_ETH_FILTER_SET:
7249 ret = i40e_dev_global_config_set(hw,
7250 (struct rte_eth_global_cfg *)arg);
7253 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7261 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7262 enum rte_filter_op filter_op,
7265 struct rte_eth_tunnel_filter_conf *filter;
7266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7267 int ret = I40E_SUCCESS;
7269 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7271 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7272 return I40E_ERR_PARAM;
7274 switch (filter_op) {
7275 case RTE_ETH_FILTER_NOP:
7276 if (!(pf->flags & I40E_FLAG_VXLAN))
7277 ret = I40E_NOT_SUPPORTED;
7279 case RTE_ETH_FILTER_ADD:
7280 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7282 case RTE_ETH_FILTER_DELETE:
7283 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7286 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7287 ret = I40E_ERR_PARAM;
7295 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7298 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7301 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7302 ret = i40e_pf_config_rss(pf);
7304 i40e_pf_disable_rss(pf);
7309 /* Get the symmetric hash enable configurations per port */
7311 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7313 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7315 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7318 /* Set the symmetric hash enable configurations per port */
7320 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7322 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7325 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7327 "Symmetric hash has already been enabled");
7330 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7332 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7334 "Symmetric hash has already been disabled");
7337 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7339 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7340 I40E_WRITE_FLUSH(hw);
7344 * Get global configurations of hash function type and symmetric hash enable
7345 * per flow type (pctype). Note that global configuration means it affects all
7346 * the ports on the same NIC.
7349 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7350 struct rte_eth_hash_global_conf *g_cfg)
7352 uint32_t reg, mask = I40E_FLOW_TYPES;
7354 enum i40e_filter_pctype pctype;
7356 memset(g_cfg, 0, sizeof(*g_cfg));
7357 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7358 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7359 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7361 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7362 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7363 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7365 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7366 if (!(mask & (1UL << i)))
7368 mask &= ~(1UL << i);
7369 /* Bit set indicats the coresponding flow type is supported */
7370 g_cfg->valid_bit_mask[0] |= (1UL << i);
7371 /* if flowtype is invalid, continue */
7372 if (!I40E_VALID_FLOW(i))
7374 pctype = i40e_flowtype_to_pctype(i);
7375 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7376 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7377 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7384 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7387 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7389 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7390 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7391 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7392 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7398 * As i40e supports less than 32 flow types, only first 32 bits need to
7401 mask0 = g_cfg->valid_bit_mask[0];
7402 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7404 /* Check if any unsupported flow type configured */
7405 if ((mask0 | i40e_mask) ^ i40e_mask)
7408 if (g_cfg->valid_bit_mask[i])
7416 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7422 * Set global configurations of hash function type and symmetric hash enable
7423 * per flow type (pctype). Note any modifying global configuration will affect
7424 * all the ports on the same NIC.
7427 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7428 struct rte_eth_hash_global_conf *g_cfg)
7433 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7434 enum i40e_filter_pctype pctype;
7436 /* Check the input parameters */
7437 ret = i40e_hash_global_config_check(g_cfg);
7441 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7442 if (!(mask0 & (1UL << i)))
7444 mask0 &= ~(1UL << i);
7445 /* if flowtype is invalid, continue */
7446 if (!I40E_VALID_FLOW(i))
7448 pctype = i40e_flowtype_to_pctype(i);
7449 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7450 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7451 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7454 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7455 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7457 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7459 "Hash function already set to Toeplitz");
7462 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7463 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7465 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7467 "Hash function already set to Simple XOR");
7470 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7472 /* Use the default, and keep it as it is */
7475 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7478 I40E_WRITE_FLUSH(hw);
7484 * Valid input sets for hash and flow director filters per PCTYPE
7487 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7488 enum rte_filter_type filter)
7492 static const uint64_t valid_hash_inset_table[] = {
7493 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7494 I40E_INSET_DMAC | I40E_INSET_SMAC |
7495 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7496 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7497 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7498 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7499 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7500 I40E_INSET_FLEX_PAYLOAD,
7501 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7502 I40E_INSET_DMAC | I40E_INSET_SMAC |
7503 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7504 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7505 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7506 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7507 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7508 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7509 I40E_INSET_FLEX_PAYLOAD,
7510 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7511 I40E_INSET_DMAC | I40E_INSET_SMAC |
7512 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7513 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7514 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7515 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7516 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7517 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7518 I40E_INSET_FLEX_PAYLOAD,
7519 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7520 I40E_INSET_DMAC | I40E_INSET_SMAC |
7521 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7522 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7523 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7524 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7525 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7526 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7527 I40E_INSET_FLEX_PAYLOAD,
7528 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7529 I40E_INSET_DMAC | I40E_INSET_SMAC |
7530 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7531 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7532 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7533 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7534 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7535 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7536 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7537 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7538 I40E_INSET_DMAC | I40E_INSET_SMAC |
7539 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7540 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7541 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7542 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7543 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7544 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7545 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7546 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7547 I40E_INSET_DMAC | I40E_INSET_SMAC |
7548 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7549 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7550 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7551 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7552 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7553 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7554 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7555 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7556 I40E_INSET_DMAC | I40E_INSET_SMAC |
7557 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7558 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7559 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7560 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7561 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7562 I40E_INSET_FLEX_PAYLOAD,
7563 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7564 I40E_INSET_DMAC | I40E_INSET_SMAC |
7565 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7566 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7567 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7568 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7569 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7570 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7571 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7572 I40E_INSET_DMAC | I40E_INSET_SMAC |
7573 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7574 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7575 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7576 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7577 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7578 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7579 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7580 I40E_INSET_DMAC | I40E_INSET_SMAC |
7581 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7582 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7583 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7584 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7585 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7586 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7587 I40E_INSET_FLEX_PAYLOAD,
7588 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7589 I40E_INSET_DMAC | I40E_INSET_SMAC |
7590 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7591 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7592 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7593 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7594 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7595 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7596 I40E_INSET_FLEX_PAYLOAD,
7597 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7598 I40E_INSET_DMAC | I40E_INSET_SMAC |
7599 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7600 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7601 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7602 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7603 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7604 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7605 I40E_INSET_FLEX_PAYLOAD,
7606 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7607 I40E_INSET_DMAC | I40E_INSET_SMAC |
7608 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7609 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7610 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7611 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7612 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7613 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7614 I40E_INSET_FLEX_PAYLOAD,
7615 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7616 I40E_INSET_DMAC | I40E_INSET_SMAC |
7617 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7618 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7619 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7620 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7621 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7622 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7623 I40E_INSET_FLEX_PAYLOAD,
7624 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7625 I40E_INSET_DMAC | I40E_INSET_SMAC |
7626 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7627 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7628 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7629 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7630 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7631 I40E_INSET_FLEX_PAYLOAD,
7632 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7633 I40E_INSET_DMAC | I40E_INSET_SMAC |
7634 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7635 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7636 I40E_INSET_FLEX_PAYLOAD,
7640 * Flow director supports only fields defined in
7641 * union rte_eth_fdir_flow.
7643 static const uint64_t valid_fdir_inset_table[] = {
7644 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7645 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7646 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7647 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7648 I40E_INSET_IPV4_TTL,
7649 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7650 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7651 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7652 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7653 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7654 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7655 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7656 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7657 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7658 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7659 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7660 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7661 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7662 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7663 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7664 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7665 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7666 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7667 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7668 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7669 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7670 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7671 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7672 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7673 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7674 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7675 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7676 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7677 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7678 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7680 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7681 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7682 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7683 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7684 I40E_INSET_IPV4_TTL,
7685 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7686 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7687 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7688 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7689 I40E_INSET_IPV6_HOP_LIMIT,
7690 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7691 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7692 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7693 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7694 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7695 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7696 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7697 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7698 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7699 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7700 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7701 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7702 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7703 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7704 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7705 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7706 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7707 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7708 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7709 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7710 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7711 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7712 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7713 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7714 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7715 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7716 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7717 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7718 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7719 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7721 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7722 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7723 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7724 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7725 I40E_INSET_IPV6_HOP_LIMIT,
7726 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7727 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7728 I40E_INSET_LAST_ETHER_TYPE,
7731 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7733 if (filter == RTE_ETH_FILTER_HASH)
7734 valid = valid_hash_inset_table[pctype];
7736 valid = valid_fdir_inset_table[pctype];
7742 * Validate if the input set is allowed for a specific PCTYPE
7745 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7746 enum rte_filter_type filter, uint64_t inset)
7750 valid = i40e_get_valid_input_set(pctype, filter);
7751 if (inset & (~valid))
7757 /* default input set fields combination per pctype */
7759 i40e_get_default_input_set(uint16_t pctype)
7761 static const uint64_t default_inset_table[] = {
7762 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7763 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7764 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7765 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7766 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7767 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7768 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7769 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7770 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7771 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7772 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7773 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7774 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7775 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7776 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7777 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7778 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7780 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7781 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7783 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7784 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7785 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7786 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7787 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7788 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7789 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7790 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7791 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7792 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7793 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7794 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7795 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7796 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7797 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7798 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7799 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7800 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7801 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7802 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7803 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7804 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7806 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7807 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7808 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7809 I40E_INSET_LAST_ETHER_TYPE,
7812 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7815 return default_inset_table[pctype];
7819 * Parse the input set from index to logical bit masks
7822 i40e_parse_input_set(uint64_t *inset,
7823 enum i40e_filter_pctype pctype,
7824 enum rte_eth_input_set_field *field,
7830 static const struct {
7831 enum rte_eth_input_set_field field;
7833 } inset_convert_table[] = {
7834 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7835 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7836 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7837 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7838 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7839 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7840 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7841 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7842 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7843 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7844 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7845 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7846 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7847 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7848 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7849 I40E_INSET_IPV6_NEXT_HDR},
7850 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7851 I40E_INSET_IPV6_HOP_LIMIT},
7852 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7853 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7854 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7855 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7856 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7857 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7858 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7859 I40E_INSET_SCTP_VT},
7860 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7861 I40E_INSET_TUNNEL_DMAC},
7862 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7863 I40E_INSET_VLAN_TUNNEL},
7864 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7865 I40E_INSET_TUNNEL_ID},
7866 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7867 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7868 I40E_INSET_FLEX_PAYLOAD_W1},
7869 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7870 I40E_INSET_FLEX_PAYLOAD_W2},
7871 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7872 I40E_INSET_FLEX_PAYLOAD_W3},
7873 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7874 I40E_INSET_FLEX_PAYLOAD_W4},
7875 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7876 I40E_INSET_FLEX_PAYLOAD_W5},
7877 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7878 I40E_INSET_FLEX_PAYLOAD_W6},
7879 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7880 I40E_INSET_FLEX_PAYLOAD_W7},
7881 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7882 I40E_INSET_FLEX_PAYLOAD_W8},
7885 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7888 /* Only one item allowed for default or all */
7890 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7891 *inset = i40e_get_default_input_set(pctype);
7893 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7894 *inset = I40E_INSET_NONE;
7899 for (i = 0, *inset = 0; i < size; i++) {
7900 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7901 if (field[i] == inset_convert_table[j].field) {
7902 *inset |= inset_convert_table[j].inset;
7907 /* It contains unsupported input set, return immediately */
7908 if (j == RTE_DIM(inset_convert_table))
7916 * Translate the input set from bit masks to register aware bit masks
7920 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7930 static const struct inset_map inset_map_common[] = {
7931 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7932 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7933 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7934 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7935 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7936 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7937 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7938 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7939 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7940 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7941 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7942 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7943 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7944 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7945 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7946 {I40E_INSET_TUNNEL_DMAC,
7947 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7948 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7949 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7950 {I40E_INSET_TUNNEL_SRC_PORT,
7951 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7952 {I40E_INSET_TUNNEL_DST_PORT,
7953 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7954 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7955 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7956 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7957 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7958 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7959 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7960 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7961 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7962 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7965 /* some different registers map in x722*/
7966 static const struct inset_map inset_map_diff_x722[] = {
7967 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7968 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7969 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7970 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7973 static const struct inset_map inset_map_diff_not_x722[] = {
7974 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7975 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7976 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7977 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7983 /* Translate input set to register aware inset */
7984 if (type == I40E_MAC_X722) {
7985 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7986 if (input & inset_map_diff_x722[i].inset)
7987 val |= inset_map_diff_x722[i].inset_reg;
7990 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7991 if (input & inset_map_diff_not_x722[i].inset)
7992 val |= inset_map_diff_not_x722[i].inset_reg;
7996 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7997 if (input & inset_map_common[i].inset)
7998 val |= inset_map_common[i].inset_reg;
8005 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8008 uint64_t inset_need_mask = inset;
8010 static const struct {
8013 } inset_mask_map[] = {
8014 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8015 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8016 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8017 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8018 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8019 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8020 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8021 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8024 if (!inset || !mask || !nb_elem)
8027 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8028 /* Clear the inset bit, if no MASK is required,
8029 * for example proto + ttl
8031 if ((inset & inset_mask_map[i].inset) ==
8032 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8033 inset_need_mask &= ~inset_mask_map[i].inset;
8034 if (!inset_need_mask)
8037 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8038 if ((inset_need_mask & inset_mask_map[i].inset) ==
8039 inset_mask_map[i].inset) {
8040 if (idx >= nb_elem) {
8041 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8044 mask[idx] = inset_mask_map[i].mask;
8053 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8055 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8057 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8059 i40e_write_rx_ctl(hw, addr, val);
8060 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8061 (uint32_t)i40e_read_rx_ctl(hw, addr));
8065 i40e_filter_input_set_init(struct i40e_pf *pf)
8067 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8068 enum i40e_filter_pctype pctype;
8069 uint64_t input_set, inset_reg;
8070 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8073 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8074 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8075 if (hw->mac.type == I40E_MAC_X722) {
8076 if (!I40E_VALID_PCTYPE_X722(pctype))
8079 if (!I40E_VALID_PCTYPE(pctype))
8083 input_set = i40e_get_default_input_set(pctype);
8085 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8086 I40E_INSET_MASK_NUM_REG);
8089 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8092 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8093 (uint32_t)(inset_reg & UINT32_MAX));
8094 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8095 (uint32_t)((inset_reg >>
8096 I40E_32_BIT_WIDTH) & UINT32_MAX));
8097 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8098 (uint32_t)(inset_reg & UINT32_MAX));
8099 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8100 (uint32_t)((inset_reg >>
8101 I40E_32_BIT_WIDTH) & UINT32_MAX));
8103 for (i = 0; i < num; i++) {
8104 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8106 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8109 /*clear unused mask registers of the pctype */
8110 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8111 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8113 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8116 I40E_WRITE_FLUSH(hw);
8118 /* store the default input set */
8119 pf->hash_input_set[pctype] = input_set;
8120 pf->fdir.input_set[pctype] = input_set;
8125 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8126 struct rte_eth_input_set_conf *conf)
8128 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8129 enum i40e_filter_pctype pctype;
8130 uint64_t input_set, inset_reg = 0;
8131 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8135 PMD_DRV_LOG(ERR, "Invalid pointer");
8138 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8139 conf->op != RTE_ETH_INPUT_SET_ADD) {
8140 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8144 if (!I40E_VALID_FLOW(conf->flow_type)) {
8145 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8149 if (hw->mac.type == I40E_MAC_X722) {
8150 /* get translated pctype value in fd pctype register */
8151 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8152 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8155 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8157 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8160 PMD_DRV_LOG(ERR, "Failed to parse input set");
8163 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8165 PMD_DRV_LOG(ERR, "Invalid input set");
8168 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8169 /* get inset value in register */
8170 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8171 inset_reg <<= I40E_32_BIT_WIDTH;
8172 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8173 input_set |= pf->hash_input_set[pctype];
8175 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8176 I40E_INSET_MASK_NUM_REG);
8180 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8182 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8183 (uint32_t)(inset_reg & UINT32_MAX));
8184 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8185 (uint32_t)((inset_reg >>
8186 I40E_32_BIT_WIDTH) & UINT32_MAX));
8188 for (i = 0; i < num; i++)
8189 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8191 /*clear unused mask registers of the pctype */
8192 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8193 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8195 I40E_WRITE_FLUSH(hw);
8197 pf->hash_input_set[pctype] = input_set;
8202 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8203 struct rte_eth_input_set_conf *conf)
8205 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8206 enum i40e_filter_pctype pctype;
8207 uint64_t input_set, inset_reg = 0;
8208 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8212 PMD_DRV_LOG(ERR, "Invalid pointer");
8215 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8216 conf->op != RTE_ETH_INPUT_SET_ADD) {
8217 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8221 if (!I40E_VALID_FLOW(conf->flow_type)) {
8222 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8226 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8228 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8231 PMD_DRV_LOG(ERR, "Failed to parse input set");
8234 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8236 PMD_DRV_LOG(ERR, "Invalid input set");
8240 /* get inset value in register */
8241 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8242 inset_reg <<= I40E_32_BIT_WIDTH;
8243 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8245 /* Can not change the inset reg for flex payload for fdir,
8246 * it is done by writing I40E_PRTQF_FD_FLXINSET
8247 * in i40e_set_flex_mask_on_pctype.
8249 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8250 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8252 input_set |= pf->fdir.input_set[pctype];
8253 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8254 I40E_INSET_MASK_NUM_REG);
8258 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8260 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8261 (uint32_t)(inset_reg & UINT32_MAX));
8262 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8263 (uint32_t)((inset_reg >>
8264 I40E_32_BIT_WIDTH) & UINT32_MAX));
8266 for (i = 0; i < num; i++)
8267 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8269 /*clear unused mask registers of the pctype */
8270 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8271 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8273 I40E_WRITE_FLUSH(hw);
8275 pf->fdir.input_set[pctype] = input_set;
8280 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8285 PMD_DRV_LOG(ERR, "Invalid pointer");
8289 switch (info->info_type) {
8290 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8291 i40e_get_symmetric_hash_enable_per_port(hw,
8292 &(info->info.enable));
8294 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8295 ret = i40e_get_hash_filter_global_config(hw,
8296 &(info->info.global_conf));
8299 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8309 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8314 PMD_DRV_LOG(ERR, "Invalid pointer");
8318 switch (info->info_type) {
8319 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8320 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8322 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8323 ret = i40e_set_hash_filter_global_config(hw,
8324 &(info->info.global_conf));
8326 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8327 ret = i40e_hash_filter_inset_select(hw,
8328 &(info->info.input_set_conf));
8332 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8341 /* Operations for hash function */
8343 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8344 enum rte_filter_op filter_op,
8347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8350 switch (filter_op) {
8351 case RTE_ETH_FILTER_NOP:
8353 case RTE_ETH_FILTER_GET:
8354 ret = i40e_hash_filter_get(hw,
8355 (struct rte_eth_hash_filter_info *)arg);
8357 case RTE_ETH_FILTER_SET:
8358 ret = i40e_hash_filter_set(hw,
8359 (struct rte_eth_hash_filter_info *)arg);
8362 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8371 /* Convert ethertype filter structure */
8373 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8374 struct i40e_ethertype_filter *filter)
8376 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8377 filter->input.ether_type = input->ether_type;
8378 filter->flags = input->flags;
8379 filter->queue = input->queue;
8384 /* Check if there exists the ehtertype filter */
8385 struct i40e_ethertype_filter *
8386 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8387 const struct i40e_ethertype_filter_input *input)
8391 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8395 return ethertype_rule->hash_map[ret];
8398 /* Add ethertype filter in SW list */
8400 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8401 struct i40e_ethertype_filter *filter)
8403 struct i40e_ethertype_rule *rule = &pf->ethertype;
8406 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8409 "Failed to insert ethertype filter"
8410 " to hash table %d!",
8414 rule->hash_map[ret] = filter;
8416 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8421 /* Delete ethertype filter in SW list */
8423 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8424 struct i40e_ethertype_filter_input *input)
8426 struct i40e_ethertype_rule *rule = &pf->ethertype;
8427 struct i40e_ethertype_filter *filter;
8430 ret = rte_hash_del_key(rule->hash_table, input);
8433 "Failed to delete ethertype filter"
8434 " to hash table %d!",
8438 filter = rule->hash_map[ret];
8439 rule->hash_map[ret] = NULL;
8441 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8448 * Configure ethertype filter, which can director packet by filtering
8449 * with mac address and ether_type or only ether_type
8452 i40e_ethertype_filter_set(struct i40e_pf *pf,
8453 struct rte_eth_ethertype_filter *filter,
8456 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8457 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8458 struct i40e_ethertype_filter *ethertype_filter, *node;
8459 struct i40e_ethertype_filter check_filter;
8460 struct i40e_control_filter_stats stats;
8464 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8465 PMD_DRV_LOG(ERR, "Invalid queue ID");
8468 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8469 filter->ether_type == ETHER_TYPE_IPv6) {
8471 "unsupported ether_type(0x%04x) in control packet filter.",
8472 filter->ether_type);
8475 if (filter->ether_type == ETHER_TYPE_VLAN)
8476 PMD_DRV_LOG(WARNING,
8477 "filter vlan ether_type in first tag is not supported.");
8479 /* Check if there is the filter in SW list */
8480 memset(&check_filter, 0, sizeof(check_filter));
8481 i40e_ethertype_filter_convert(filter, &check_filter);
8482 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8483 &check_filter.input);
8485 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8489 if (!add && !node) {
8490 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8494 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8495 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8496 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8497 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8498 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8500 memset(&stats, 0, sizeof(stats));
8501 ret = i40e_aq_add_rem_control_packet_filter(hw,
8502 filter->mac_addr.addr_bytes,
8503 filter->ether_type, flags,
8505 filter->queue, add, &stats, NULL);
8508 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8509 ret, stats.mac_etype_used, stats.etype_used,
8510 stats.mac_etype_free, stats.etype_free);
8514 /* Add or delete a filter in SW list */
8516 ethertype_filter = rte_zmalloc("ethertype_filter",
8517 sizeof(*ethertype_filter), 0);
8518 rte_memcpy(ethertype_filter, &check_filter,
8519 sizeof(check_filter));
8520 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8522 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8529 * Handle operations for ethertype filter.
8532 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8533 enum rte_filter_op filter_op,
8536 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8539 if (filter_op == RTE_ETH_FILTER_NOP)
8543 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8548 switch (filter_op) {
8549 case RTE_ETH_FILTER_ADD:
8550 ret = i40e_ethertype_filter_set(pf,
8551 (struct rte_eth_ethertype_filter *)arg,
8554 case RTE_ETH_FILTER_DELETE:
8555 ret = i40e_ethertype_filter_set(pf,
8556 (struct rte_eth_ethertype_filter *)arg,
8560 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8568 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8569 enum rte_filter_type filter_type,
8570 enum rte_filter_op filter_op,
8578 switch (filter_type) {
8579 case RTE_ETH_FILTER_NONE:
8580 /* For global configuration */
8581 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8583 case RTE_ETH_FILTER_HASH:
8584 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8586 case RTE_ETH_FILTER_MACVLAN:
8587 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8589 case RTE_ETH_FILTER_ETHERTYPE:
8590 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8592 case RTE_ETH_FILTER_TUNNEL:
8593 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8595 case RTE_ETH_FILTER_FDIR:
8596 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8598 case RTE_ETH_FILTER_GENERIC:
8599 if (filter_op != RTE_ETH_FILTER_GET)
8601 *(const void **)arg = &i40e_flow_ops;
8604 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8614 * Check and enable Extended Tag.
8615 * Enabling Extended Tag is important for 40G performance.
8618 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8620 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8624 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8627 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8631 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8632 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8637 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8640 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8644 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8645 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8648 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8649 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8652 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8659 * As some registers wouldn't be reset unless a global hardware reset,
8660 * hardware initialization is needed to put those registers into an
8661 * expected initial state.
8664 i40e_hw_init(struct rte_eth_dev *dev)
8666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8668 i40e_enable_extended_tag(dev);
8670 /* clear the PF Queue Filter control register */
8671 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8673 /* Disable symmetric hash per port */
8674 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8677 enum i40e_filter_pctype
8678 i40e_flowtype_to_pctype(uint16_t flow_type)
8680 static const enum i40e_filter_pctype pctype_table[] = {
8681 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8682 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8683 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8684 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8685 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8686 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8687 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8688 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8689 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8690 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8691 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8692 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8693 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8694 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8695 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8696 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8697 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8698 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8699 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8702 return pctype_table[flow_type];
8706 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8708 static const uint16_t flowtype_table[] = {
8709 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8710 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8711 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8712 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8713 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8714 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8715 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8716 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8717 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8718 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8719 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8720 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8721 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8722 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8723 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8724 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8725 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8726 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8727 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8728 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8729 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8730 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8731 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8732 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8733 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8734 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8735 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8736 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8737 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8738 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8739 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8742 return flowtype_table[pctype];
8746 * On X710, performance number is far from the expectation on recent firmware
8747 * versions; on XL710, performance number is also far from the expectation on
8748 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8749 * mode is enabled and port MAC address is equal to the packet destination MAC
8750 * address. The fix for this issue may not be integrated in the following
8751 * firmware version. So the workaround in software driver is needed. It needs
8752 * to modify the initial values of 3 internal only registers for both X710 and
8753 * XL710. Note that the values for X710 or XL710 could be different, and the
8754 * workaround can be removed when it is fixed in firmware in the future.
8757 /* For both X710 and XL710 */
8758 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8759 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8761 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8762 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8765 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8766 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8769 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8771 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8772 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8775 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8777 enum i40e_status_code status;
8778 struct i40e_aq_get_phy_abilities_resp phy_ab;
8781 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8791 i40e_configure_registers(struct i40e_hw *hw)
8797 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8798 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8799 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8805 for (i = 0; i < RTE_DIM(reg_table); i++) {
8806 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8807 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8809 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8810 else /* For X710/XL710/XXV710 */
8812 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8815 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8816 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8818 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8819 else /* For X710/XL710/XXV710 */
8821 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8824 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8825 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8826 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8828 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8831 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8834 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8837 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8841 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8842 reg_table[i].addr, reg);
8843 if (reg == reg_table[i].val)
8846 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8847 reg_table[i].val, NULL);
8850 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8851 reg_table[i].val, reg_table[i].addr);
8854 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8855 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8859 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8860 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8861 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8862 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8864 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8869 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8870 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8874 /* Configure for double VLAN RX stripping */
8875 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8876 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8877 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8878 ret = i40e_aq_debug_write_register(hw,
8879 I40E_VSI_TSR(vsi->vsi_id),
8882 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8884 return I40E_ERR_CONFIG;
8888 /* Configure for double VLAN TX insertion */
8889 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8890 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8891 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8892 ret = i40e_aq_debug_write_register(hw,
8893 I40E_VSI_L2TAGSTXVALID(
8894 vsi->vsi_id), reg, NULL);
8897 "Failed to update VSI_L2TAGSTXVALID[%d]",
8899 return I40E_ERR_CONFIG;
8907 * i40e_aq_add_mirror_rule
8908 * @hw: pointer to the hardware structure
8909 * @seid: VEB seid to add mirror rule to
8910 * @dst_id: destination vsi seid
8911 * @entries: Buffer which contains the entities to be mirrored
8912 * @count: number of entities contained in the buffer
8913 * @rule_id:the rule_id of the rule to be added
8915 * Add a mirror rule for a given veb.
8918 static enum i40e_status_code
8919 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8920 uint16_t seid, uint16_t dst_id,
8921 uint16_t rule_type, uint16_t *entries,
8922 uint16_t count, uint16_t *rule_id)
8924 struct i40e_aq_desc desc;
8925 struct i40e_aqc_add_delete_mirror_rule cmd;
8926 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8927 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8930 enum i40e_status_code status;
8932 i40e_fill_default_direct_cmd_desc(&desc,
8933 i40e_aqc_opc_add_mirror_rule);
8934 memset(&cmd, 0, sizeof(cmd));
8936 buff_len = sizeof(uint16_t) * count;
8937 desc.datalen = rte_cpu_to_le_16(buff_len);
8939 desc.flags |= rte_cpu_to_le_16(
8940 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8941 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8942 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8943 cmd.num_entries = rte_cpu_to_le_16(count);
8944 cmd.seid = rte_cpu_to_le_16(seid);
8945 cmd.destination = rte_cpu_to_le_16(dst_id);
8947 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8948 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8950 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8951 hw->aq.asq_last_status, resp->rule_id,
8952 resp->mirror_rules_used, resp->mirror_rules_free);
8953 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8959 * i40e_aq_del_mirror_rule
8960 * @hw: pointer to the hardware structure
8961 * @seid: VEB seid to add mirror rule to
8962 * @entries: Buffer which contains the entities to be mirrored
8963 * @count: number of entities contained in the buffer
8964 * @rule_id:the rule_id of the rule to be delete
8966 * Delete a mirror rule for a given veb.
8969 static enum i40e_status_code
8970 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8971 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8972 uint16_t count, uint16_t rule_id)
8974 struct i40e_aq_desc desc;
8975 struct i40e_aqc_add_delete_mirror_rule cmd;
8976 uint16_t buff_len = 0;
8977 enum i40e_status_code status;
8980 i40e_fill_default_direct_cmd_desc(&desc,
8981 i40e_aqc_opc_delete_mirror_rule);
8982 memset(&cmd, 0, sizeof(cmd));
8983 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8984 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8986 cmd.num_entries = count;
8987 buff_len = sizeof(uint16_t) * count;
8988 desc.datalen = rte_cpu_to_le_16(buff_len);
8989 buff = (void *)entries;
8991 /* rule id is filled in destination field for deleting mirror rule */
8992 cmd.destination = rte_cpu_to_le_16(rule_id);
8994 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8995 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8996 cmd.seid = rte_cpu_to_le_16(seid);
8998 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8999 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9005 * i40e_mirror_rule_set
9006 * @dev: pointer to the hardware structure
9007 * @mirror_conf: mirror rule info
9008 * @sw_id: mirror rule's sw_id
9009 * @on: enable/disable
9011 * set a mirror rule.
9015 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9016 struct rte_eth_mirror_conf *mirror_conf,
9017 uint8_t sw_id, uint8_t on)
9019 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9020 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9021 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9022 struct i40e_mirror_rule *parent = NULL;
9023 uint16_t seid, dst_seid, rule_id;
9027 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9029 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9031 "mirror rule can not be configured without veb or vfs.");
9034 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9035 PMD_DRV_LOG(ERR, "mirror table is full.");
9038 if (mirror_conf->dst_pool > pf->vf_num) {
9039 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9040 mirror_conf->dst_pool);
9044 seid = pf->main_vsi->veb->seid;
9046 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9047 if (sw_id <= it->index) {
9053 if (mirr_rule && sw_id == mirr_rule->index) {
9055 PMD_DRV_LOG(ERR, "mirror rule exists.");
9058 ret = i40e_aq_del_mirror_rule(hw, seid,
9059 mirr_rule->rule_type,
9061 mirr_rule->num_entries, mirr_rule->id);
9064 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9065 ret, hw->aq.asq_last_status);
9068 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9069 rte_free(mirr_rule);
9070 pf->nb_mirror_rule--;
9074 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9078 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9079 sizeof(struct i40e_mirror_rule) , 0);
9081 PMD_DRV_LOG(ERR, "failed to allocate memory");
9082 return I40E_ERR_NO_MEMORY;
9084 switch (mirror_conf->rule_type) {
9085 case ETH_MIRROR_VLAN:
9086 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9087 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9088 mirr_rule->entries[j] =
9089 mirror_conf->vlan.vlan_id[i];
9094 PMD_DRV_LOG(ERR, "vlan is not specified.");
9095 rte_free(mirr_rule);
9098 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9100 case ETH_MIRROR_VIRTUAL_POOL_UP:
9101 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9102 /* check if the specified pool bit is out of range */
9103 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9104 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9105 rte_free(mirr_rule);
9108 for (i = 0, j = 0; i < pf->vf_num; i++) {
9109 if (mirror_conf->pool_mask & (1ULL << i)) {
9110 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9114 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9115 /* add pf vsi to entries */
9116 mirr_rule->entries[j] = pf->main_vsi_seid;
9120 PMD_DRV_LOG(ERR, "pool is not specified.");
9121 rte_free(mirr_rule);
9124 /* egress and ingress in aq commands means from switch but not port */
9125 mirr_rule->rule_type =
9126 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9127 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9128 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9130 case ETH_MIRROR_UPLINK_PORT:
9131 /* egress and ingress in aq commands means from switch but not port*/
9132 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9134 case ETH_MIRROR_DOWNLINK_PORT:
9135 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9138 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9139 mirror_conf->rule_type);
9140 rte_free(mirr_rule);
9144 /* If the dst_pool is equal to vf_num, consider it as PF */
9145 if (mirror_conf->dst_pool == pf->vf_num)
9146 dst_seid = pf->main_vsi_seid;
9148 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9150 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9151 mirr_rule->rule_type, mirr_rule->entries,
9155 "failed to add mirror rule: ret = %d, aq_err = %d.",
9156 ret, hw->aq.asq_last_status);
9157 rte_free(mirr_rule);
9161 mirr_rule->index = sw_id;
9162 mirr_rule->num_entries = j;
9163 mirr_rule->id = rule_id;
9164 mirr_rule->dst_vsi_seid = dst_seid;
9167 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9169 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9171 pf->nb_mirror_rule++;
9176 * i40e_mirror_rule_reset
9177 * @dev: pointer to the device
9178 * @sw_id: mirror rule's sw_id
9180 * reset a mirror rule.
9184 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9186 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9188 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9192 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9194 seid = pf->main_vsi->veb->seid;
9196 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9197 if (sw_id == it->index) {
9203 ret = i40e_aq_del_mirror_rule(hw, seid,
9204 mirr_rule->rule_type,
9206 mirr_rule->num_entries, mirr_rule->id);
9209 "failed to remove mirror rule: status = %d, aq_err = %d.",
9210 ret, hw->aq.asq_last_status);
9213 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9214 rte_free(mirr_rule);
9215 pf->nb_mirror_rule--;
9217 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9224 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9227 uint64_t systim_cycles;
9229 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9230 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9233 return systim_cycles;
9237 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9239 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9242 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9243 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9250 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9252 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9255 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9256 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9263 i40e_start_timecounters(struct rte_eth_dev *dev)
9265 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9266 struct i40e_adapter *adapter =
9267 (struct i40e_adapter *)dev->data->dev_private;
9268 struct rte_eth_link link;
9269 uint32_t tsync_inc_l;
9270 uint32_t tsync_inc_h;
9272 /* Get current link speed. */
9273 memset(&link, 0, sizeof(link));
9274 i40e_dev_link_update(dev, 1);
9275 rte_i40e_dev_atomic_read_link_status(dev, &link);
9277 switch (link.link_speed) {
9278 case ETH_SPEED_NUM_40G:
9279 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9280 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9282 case ETH_SPEED_NUM_10G:
9283 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9284 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9286 case ETH_SPEED_NUM_1G:
9287 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9288 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9295 /* Set the timesync increment value. */
9296 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9297 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9299 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9300 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9301 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9303 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9304 adapter->systime_tc.cc_shift = 0;
9305 adapter->systime_tc.nsec_mask = 0;
9307 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9308 adapter->rx_tstamp_tc.cc_shift = 0;
9309 adapter->rx_tstamp_tc.nsec_mask = 0;
9311 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9312 adapter->tx_tstamp_tc.cc_shift = 0;
9313 adapter->tx_tstamp_tc.nsec_mask = 0;
9317 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9319 struct i40e_adapter *adapter =
9320 (struct i40e_adapter *)dev->data->dev_private;
9322 adapter->systime_tc.nsec += delta;
9323 adapter->rx_tstamp_tc.nsec += delta;
9324 adapter->tx_tstamp_tc.nsec += delta;
9330 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9333 struct i40e_adapter *adapter =
9334 (struct i40e_adapter *)dev->data->dev_private;
9336 ns = rte_timespec_to_ns(ts);
9338 /* Set the timecounters to a new value. */
9339 adapter->systime_tc.nsec = ns;
9340 adapter->rx_tstamp_tc.nsec = ns;
9341 adapter->tx_tstamp_tc.nsec = ns;
9347 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9349 uint64_t ns, systime_cycles;
9350 struct i40e_adapter *adapter =
9351 (struct i40e_adapter *)dev->data->dev_private;
9353 systime_cycles = i40e_read_systime_cyclecounter(dev);
9354 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9355 *ts = rte_ns_to_timespec(ns);
9361 i40e_timesync_enable(struct rte_eth_dev *dev)
9363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9364 uint32_t tsync_ctl_l;
9365 uint32_t tsync_ctl_h;
9367 /* Stop the timesync system time. */
9368 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9369 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9370 /* Reset the timesync system time value. */
9371 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9372 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9374 i40e_start_timecounters(dev);
9376 /* Clear timesync registers. */
9377 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9378 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9379 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9380 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9381 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9382 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9384 /* Enable timestamping of PTP packets. */
9385 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9386 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9388 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9389 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9390 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9392 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9393 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9399 i40e_timesync_disable(struct rte_eth_dev *dev)
9401 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9402 uint32_t tsync_ctl_l;
9403 uint32_t tsync_ctl_h;
9405 /* Disable timestamping of transmitted PTP packets. */
9406 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9407 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9409 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9410 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9412 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9413 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9415 /* Reset the timesync increment value. */
9416 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9417 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9423 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9424 struct timespec *timestamp, uint32_t flags)
9426 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9427 struct i40e_adapter *adapter =
9428 (struct i40e_adapter *)dev->data->dev_private;
9430 uint32_t sync_status;
9431 uint32_t index = flags & 0x03;
9432 uint64_t rx_tstamp_cycles;
9435 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9436 if ((sync_status & (1 << index)) == 0)
9439 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9440 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9441 *timestamp = rte_ns_to_timespec(ns);
9447 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9448 struct timespec *timestamp)
9450 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9451 struct i40e_adapter *adapter =
9452 (struct i40e_adapter *)dev->data->dev_private;
9454 uint32_t sync_status;
9455 uint64_t tx_tstamp_cycles;
9458 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9459 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9462 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9463 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9464 *timestamp = rte_ns_to_timespec(ns);
9470 * i40e_parse_dcb_configure - parse dcb configure from user
9471 * @dev: the device being configured
9472 * @dcb_cfg: pointer of the result of parse
9473 * @*tc_map: bit map of enabled traffic classes
9475 * Returns 0 on success, negative value on failure
9478 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9479 struct i40e_dcbx_config *dcb_cfg,
9482 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9483 uint8_t i, tc_bw, bw_lf;
9485 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9487 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9488 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9489 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9493 /* assume each tc has the same bw */
9494 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9495 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9496 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9497 /* to ensure the sum of tcbw is equal to 100 */
9498 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9499 for (i = 0; i < bw_lf; i++)
9500 dcb_cfg->etscfg.tcbwtable[i]++;
9502 /* assume each tc has the same Transmission Selection Algorithm */
9503 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9504 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9506 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9507 dcb_cfg->etscfg.prioritytable[i] =
9508 dcb_rx_conf->dcb_tc[i];
9510 /* FW needs one App to configure HW */
9511 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9512 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9513 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9514 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9516 if (dcb_rx_conf->nb_tcs == 0)
9517 *tc_map = 1; /* tc0 only */
9519 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9521 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9522 dcb_cfg->pfc.willing = 0;
9523 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9524 dcb_cfg->pfc.pfcenable = *tc_map;
9530 static enum i40e_status_code
9531 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9532 struct i40e_aqc_vsi_properties_data *info,
9533 uint8_t enabled_tcmap)
9535 enum i40e_status_code ret;
9536 int i, total_tc = 0;
9537 uint16_t qpnum_per_tc, bsf, qp_idx;
9538 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9539 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9540 uint16_t used_queues;
9542 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9543 if (ret != I40E_SUCCESS)
9546 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9547 if (enabled_tcmap & (1 << i))
9552 vsi->enabled_tc = enabled_tcmap;
9554 /* different VSI has different queues assigned */
9555 if (vsi->type == I40E_VSI_MAIN)
9556 used_queues = dev_data->nb_rx_queues -
9557 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9558 else if (vsi->type == I40E_VSI_VMDQ2)
9559 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9561 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9562 return I40E_ERR_NO_AVAILABLE_VSI;
9565 qpnum_per_tc = used_queues / total_tc;
9566 /* Number of queues per enabled TC */
9567 if (qpnum_per_tc == 0) {
9568 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9569 return I40E_ERR_INVALID_QP_ID;
9571 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9573 bsf = rte_bsf32(qpnum_per_tc);
9576 * Configure TC and queue mapping parameters, for enabled TC,
9577 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9578 * default queue will serve it.
9581 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9582 if (vsi->enabled_tc & (1 << i)) {
9583 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9584 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9585 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9586 qp_idx += qpnum_per_tc;
9588 info->tc_mapping[i] = 0;
9591 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9592 if (vsi->type == I40E_VSI_SRIOV) {
9593 info->mapping_flags |=
9594 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9595 for (i = 0; i < vsi->nb_qps; i++)
9596 info->queue_mapping[i] =
9597 rte_cpu_to_le_16(vsi->base_queue + i);
9599 info->mapping_flags |=
9600 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9601 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9603 info->valid_sections |=
9604 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9606 return I40E_SUCCESS;
9610 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9611 * @veb: VEB to be configured
9612 * @tc_map: enabled TC bitmap
9614 * Returns 0 on success, negative value on failure
9616 static enum i40e_status_code
9617 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9619 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9620 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9621 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9622 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9623 enum i40e_status_code ret = I40E_SUCCESS;
9627 /* Check if enabled_tc is same as existing or new TCs */
9628 if (veb->enabled_tc == tc_map)
9631 /* configure tc bandwidth */
9632 memset(&veb_bw, 0, sizeof(veb_bw));
9633 veb_bw.tc_valid_bits = tc_map;
9634 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9635 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9636 if (tc_map & BIT_ULL(i))
9637 veb_bw.tc_bw_share_credits[i] = 1;
9639 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9643 "AQ command Config switch_comp BW allocation per TC failed = %d",
9644 hw->aq.asq_last_status);
9648 memset(&ets_query, 0, sizeof(ets_query));
9649 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9651 if (ret != I40E_SUCCESS) {
9653 "Failed to get switch_comp ETS configuration %u",
9654 hw->aq.asq_last_status);
9657 memset(&bw_query, 0, sizeof(bw_query));
9658 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9660 if (ret != I40E_SUCCESS) {
9662 "Failed to get switch_comp bandwidth configuration %u",
9663 hw->aq.asq_last_status);
9667 /* store and print out BW info */
9668 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9669 veb->bw_info.bw_max = ets_query.tc_bw_max;
9670 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9671 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9672 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9673 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9675 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9676 veb->bw_info.bw_ets_share_credits[i] =
9677 bw_query.tc_bw_share_credits[i];
9678 veb->bw_info.bw_ets_credits[i] =
9679 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9680 /* 4 bits per TC, 4th bit is reserved */
9681 veb->bw_info.bw_ets_max[i] =
9682 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9683 RTE_LEN2MASK(3, uint8_t));
9684 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9685 veb->bw_info.bw_ets_share_credits[i]);
9686 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9687 veb->bw_info.bw_ets_credits[i]);
9688 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9689 veb->bw_info.bw_ets_max[i]);
9692 veb->enabled_tc = tc_map;
9699 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9700 * @vsi: VSI to be configured
9701 * @tc_map: enabled TC bitmap
9703 * Returns 0 on success, negative value on failure
9705 static enum i40e_status_code
9706 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9708 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9709 struct i40e_vsi_context ctxt;
9710 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9711 enum i40e_status_code ret = I40E_SUCCESS;
9714 /* Check if enabled_tc is same as existing or new TCs */
9715 if (vsi->enabled_tc == tc_map)
9718 /* configure tc bandwidth */
9719 memset(&bw_data, 0, sizeof(bw_data));
9720 bw_data.tc_valid_bits = tc_map;
9721 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9722 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9723 if (tc_map & BIT_ULL(i))
9724 bw_data.tc_bw_credits[i] = 1;
9726 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9729 "AQ command Config VSI BW allocation per TC failed = %d",
9730 hw->aq.asq_last_status);
9733 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9734 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9736 /* Update Queue Pairs Mapping for currently enabled UPs */
9737 ctxt.seid = vsi->seid;
9738 ctxt.pf_num = hw->pf_id;
9740 ctxt.uplink_seid = vsi->uplink_seid;
9741 ctxt.info = vsi->info;
9743 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9747 /* Update the VSI after updating the VSI queue-mapping information */
9748 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9750 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9751 hw->aq.asq_last_status);
9754 /* update the local VSI info with updated queue map */
9755 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9756 sizeof(vsi->info.tc_mapping));
9757 (void)rte_memcpy(&vsi->info.queue_mapping,
9758 &ctxt.info.queue_mapping,
9759 sizeof(vsi->info.queue_mapping));
9760 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9761 vsi->info.valid_sections = 0;
9763 /* query and update current VSI BW information */
9764 ret = i40e_vsi_get_bw_config(vsi);
9767 "Failed updating vsi bw info, err %s aq_err %s",
9768 i40e_stat_str(hw, ret),
9769 i40e_aq_str(hw, hw->aq.asq_last_status));
9773 vsi->enabled_tc = tc_map;
9780 * i40e_dcb_hw_configure - program the dcb setting to hw
9781 * @pf: pf the configuration is taken on
9782 * @new_cfg: new configuration
9783 * @tc_map: enabled TC bitmap
9785 * Returns 0 on success, negative value on failure
9787 static enum i40e_status_code
9788 i40e_dcb_hw_configure(struct i40e_pf *pf,
9789 struct i40e_dcbx_config *new_cfg,
9792 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9793 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9794 struct i40e_vsi *main_vsi = pf->main_vsi;
9795 struct i40e_vsi_list *vsi_list;
9796 enum i40e_status_code ret;
9800 /* Use the FW API if FW > v4.4*/
9801 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9802 (hw->aq.fw_maj_ver >= 5))) {
9804 "FW < v4.4, can not use FW LLDP API to configure DCB");
9805 return I40E_ERR_FIRMWARE_API_VERSION;
9808 /* Check if need reconfiguration */
9809 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9810 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9811 return I40E_SUCCESS;
9814 /* Copy the new config to the current config */
9815 *old_cfg = *new_cfg;
9816 old_cfg->etsrec = old_cfg->etscfg;
9817 ret = i40e_set_dcb_config(hw);
9819 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9820 i40e_stat_str(hw, ret),
9821 i40e_aq_str(hw, hw->aq.asq_last_status));
9824 /* set receive Arbiter to RR mode and ETS scheme by default */
9825 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9826 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9827 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9828 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9829 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9830 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9831 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9832 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9833 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9834 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9835 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9836 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9837 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9839 /* get local mib to check whether it is configured correctly */
9841 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9842 /* Get Local DCB Config */
9843 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9844 &hw->local_dcbx_config);
9846 /* if Veb is created, need to update TC of it at first */
9847 if (main_vsi->veb) {
9848 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9850 PMD_INIT_LOG(WARNING,
9851 "Failed configuring TC for VEB seid=%d",
9852 main_vsi->veb->seid);
9854 /* Update each VSI */
9855 i40e_vsi_config_tc(main_vsi, tc_map);
9856 if (main_vsi->veb) {
9857 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9858 /* Beside main VSI and VMDQ VSIs, only enable default
9861 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9862 ret = i40e_vsi_config_tc(vsi_list->vsi,
9865 ret = i40e_vsi_config_tc(vsi_list->vsi,
9866 I40E_DEFAULT_TCMAP);
9868 PMD_INIT_LOG(WARNING,
9869 "Failed configuring TC for VSI seid=%d",
9870 vsi_list->vsi->seid);
9874 return I40E_SUCCESS;
9878 * i40e_dcb_init_configure - initial dcb config
9879 * @dev: device being configured
9880 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9882 * Returns 0 on success, negative value on failure
9885 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9887 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9891 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9892 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9896 /* DCB initialization:
9897 * Update DCB configuration from the Firmware and configure
9898 * LLDP MIB change event.
9900 if (sw_dcb == TRUE) {
9901 ret = i40e_init_dcb(hw);
9902 /* If lldp agent is stopped, the return value from
9903 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9904 * adminq status. Otherwise, it should return success.
9906 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9907 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9908 memset(&hw->local_dcbx_config, 0,
9909 sizeof(struct i40e_dcbx_config));
9910 /* set dcb default configuration */
9911 hw->local_dcbx_config.etscfg.willing = 0;
9912 hw->local_dcbx_config.etscfg.maxtcs = 0;
9913 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9914 hw->local_dcbx_config.etscfg.tsatable[0] =
9916 /* all UPs mapping to TC0 */
9917 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9918 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
9919 hw->local_dcbx_config.etsrec =
9920 hw->local_dcbx_config.etscfg;
9921 hw->local_dcbx_config.pfc.willing = 0;
9922 hw->local_dcbx_config.pfc.pfccap =
9923 I40E_MAX_TRAFFIC_CLASS;
9924 hw->local_dcbx_config.pfc.pfcenable =
9926 /* FW needs one App to configure HW */
9927 hw->local_dcbx_config.numapps = 1;
9928 hw->local_dcbx_config.app[0].selector =
9929 I40E_APP_SEL_ETHTYPE;
9930 hw->local_dcbx_config.app[0].priority = 3;
9931 hw->local_dcbx_config.app[0].protocolid =
9932 I40E_APP_PROTOID_FCOE;
9933 ret = i40e_set_dcb_config(hw);
9936 "default dcb config fails. err = %d, aq_err = %d.",
9937 ret, hw->aq.asq_last_status);
9942 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9943 ret, hw->aq.asq_last_status);
9947 ret = i40e_aq_start_lldp(hw, NULL);
9948 if (ret != I40E_SUCCESS)
9949 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9951 ret = i40e_init_dcb(hw);
9953 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9955 "HW doesn't support DCBX offload.");
9960 "DCBX configuration failed, err = %d, aq_err = %d.",
9961 ret, hw->aq.asq_last_status);
9969 * i40e_dcb_setup - setup dcb related config
9970 * @dev: device being configured
9972 * Returns 0 on success, negative value on failure
9975 i40e_dcb_setup(struct rte_eth_dev *dev)
9977 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9978 struct i40e_dcbx_config dcb_cfg;
9982 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9983 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9987 if (pf->vf_num != 0)
9988 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9990 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9992 PMD_INIT_LOG(ERR, "invalid dcb config");
9995 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9997 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10005 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10006 struct rte_eth_dcb_info *dcb_info)
10008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10010 struct i40e_vsi *vsi = pf->main_vsi;
10011 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10012 uint16_t bsf, tc_mapping;
10015 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10016 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10018 dcb_info->nb_tcs = 1;
10019 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10020 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10021 for (i = 0; i < dcb_info->nb_tcs; i++)
10022 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10024 /* get queue mapping if vmdq is disabled */
10025 if (!pf->nb_cfg_vmdq_vsi) {
10026 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10027 if (!(vsi->enabled_tc & (1 << i)))
10029 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10030 dcb_info->tc_queue.tc_rxq[j][i].base =
10031 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10032 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10033 dcb_info->tc_queue.tc_txq[j][i].base =
10034 dcb_info->tc_queue.tc_rxq[j][i].base;
10035 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10036 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10037 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10038 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10039 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10044 /* get queue mapping if vmdq is enabled */
10046 vsi = pf->vmdq[j].vsi;
10047 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10048 if (!(vsi->enabled_tc & (1 << i)))
10050 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10051 dcb_info->tc_queue.tc_rxq[j][i].base =
10052 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10053 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10054 dcb_info->tc_queue.tc_txq[j][i].base =
10055 dcb_info->tc_queue.tc_rxq[j][i].base;
10056 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10057 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10058 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10059 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10060 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10063 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10068 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10070 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10071 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10072 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10073 uint16_t interval =
10074 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10075 uint16_t msix_intr;
10077 msix_intr = intr_handle->intr_vec[queue_id];
10078 if (msix_intr == I40E_MISC_VEC_ID)
10079 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10080 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10081 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10082 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10084 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10087 I40E_PFINT_DYN_CTLN(msix_intr -
10088 I40E_RX_VEC_START),
10089 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10090 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10091 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10093 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10095 I40E_WRITE_FLUSH(hw);
10096 rte_intr_enable(&pci_dev->intr_handle);
10102 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10104 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10105 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10107 uint16_t msix_intr;
10109 msix_intr = intr_handle->intr_vec[queue_id];
10110 if (msix_intr == I40E_MISC_VEC_ID)
10111 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10114 I40E_PFINT_DYN_CTLN(msix_intr -
10115 I40E_RX_VEC_START),
10117 I40E_WRITE_FLUSH(hw);
10122 static int i40e_get_regs(struct rte_eth_dev *dev,
10123 struct rte_dev_reg_info *regs)
10125 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10126 uint32_t *ptr_data = regs->data;
10127 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10128 const struct i40e_reg_info *reg_info;
10130 if (ptr_data == NULL) {
10131 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10132 regs->width = sizeof(uint32_t);
10136 /* The first few registers have to be read using AQ operations */
10138 while (i40e_regs_adminq[reg_idx].name) {
10139 reg_info = &i40e_regs_adminq[reg_idx++];
10140 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10142 arr_idx2 <= reg_info->count2;
10144 reg_offset = arr_idx * reg_info->stride1 +
10145 arr_idx2 * reg_info->stride2;
10146 reg_offset += reg_info->base_addr;
10147 ptr_data[reg_offset >> 2] =
10148 i40e_read_rx_ctl(hw, reg_offset);
10152 /* The remaining registers can be read using primitives */
10154 while (i40e_regs_others[reg_idx].name) {
10155 reg_info = &i40e_regs_others[reg_idx++];
10156 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10158 arr_idx2 <= reg_info->count2;
10160 reg_offset = arr_idx * reg_info->stride1 +
10161 arr_idx2 * reg_info->stride2;
10162 reg_offset += reg_info->base_addr;
10163 ptr_data[reg_offset >> 2] =
10164 I40E_READ_REG(hw, reg_offset);
10171 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10173 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10175 /* Convert word count to byte count */
10176 return hw->nvm.sr_size << 1;
10179 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10180 struct rte_dev_eeprom_info *eeprom)
10182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10183 uint16_t *data = eeprom->data;
10184 uint16_t offset, length, cnt_words;
10187 offset = eeprom->offset >> 1;
10188 length = eeprom->length >> 1;
10189 cnt_words = length;
10191 if (offset > hw->nvm.sr_size ||
10192 offset + length > hw->nvm.sr_size) {
10193 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10197 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10199 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10200 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10201 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10208 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10209 struct ether_addr *mac_addr)
10211 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10213 if (!is_valid_assigned_ether_addr(mac_addr)) {
10214 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10218 /* Flags: 0x3 updates port address */
10219 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10223 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10225 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10226 struct rte_eth_dev_data *dev_data = pf->dev_data;
10227 uint32_t frame_size = mtu + ETHER_HDR_LEN
10228 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10231 /* check if mtu is within the allowed range */
10232 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10235 /* mtu setting is forbidden if port is start */
10236 if (dev_data->dev_started) {
10237 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10238 dev_data->port_id);
10242 if (frame_size > ETHER_MAX_LEN)
10243 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10245 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10247 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10252 /* Restore ethertype filter */
10254 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10256 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10257 struct i40e_ethertype_filter_list
10258 *ethertype_list = &pf->ethertype.ethertype_list;
10259 struct i40e_ethertype_filter *f;
10260 struct i40e_control_filter_stats stats;
10263 TAILQ_FOREACH(f, ethertype_list, rules) {
10265 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10266 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10267 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10268 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10269 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10271 memset(&stats, 0, sizeof(stats));
10272 i40e_aq_add_rem_control_packet_filter(hw,
10273 f->input.mac_addr.addr_bytes,
10274 f->input.ether_type,
10275 flags, pf->main_vsi->seid,
10276 f->queue, 1, &stats, NULL);
10278 PMD_DRV_LOG(INFO, "Ethertype filter:"
10279 " mac_etype_used = %u, etype_used = %u,"
10280 " mac_etype_free = %u, etype_free = %u",
10281 stats.mac_etype_used, stats.etype_used,
10282 stats.mac_etype_free, stats.etype_free);
10285 /* Restore tunnel filter */
10287 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10289 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10290 struct i40e_vsi *vsi = pf->main_vsi;
10291 struct i40e_tunnel_filter_list
10292 *tunnel_list = &pf->tunnel.tunnel_list;
10293 struct i40e_tunnel_filter *f;
10294 struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10296 TAILQ_FOREACH(f, tunnel_list, rules) {
10297 memset(&cld_filter, 0, sizeof(cld_filter));
10298 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10299 cld_filter.queue_number = f->queue;
10300 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10305 i40e_filter_restore(struct i40e_pf *pf)
10307 i40e_ethertype_filter_restore(pf);
10308 i40e_tunnel_filter_restore(pf);
10309 i40e_fdir_filter_restore(pf);
10313 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10315 if (strcmp(dev->driver->pci_drv.driver.name,
10316 drv->pci_drv.driver.name))
10323 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10325 struct rte_eth_dev *dev;
10326 struct i40e_pf *pf;
10328 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10330 dev = &rte_eth_devices[port];
10332 if (!is_device_supported(dev, &rte_i40e_pmd))
10335 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10337 if (vf >= pf->vf_num || !pf->vfs) {
10338 PMD_DRV_LOG(ERR, "Invalid argument.");
10342 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10348 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10350 struct rte_eth_dev *dev;
10351 struct i40e_pf *pf;
10352 struct i40e_vsi *vsi;
10353 struct i40e_hw *hw;
10354 struct i40e_vsi_context ctxt;
10357 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10359 dev = &rte_eth_devices[port];
10361 if (!is_device_supported(dev, &rte_i40e_pmd))
10364 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10366 if (vf_id >= pf->vf_num || !pf->vfs) {
10367 PMD_DRV_LOG(ERR, "Invalid argument.");
10371 vsi = pf->vfs[vf_id].vsi;
10373 PMD_DRV_LOG(ERR, "Invalid VSI.");
10377 /* Check if it has been already on or off */
10378 if (vsi->info.valid_sections &
10379 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10381 if ((vsi->info.sec_flags &
10382 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10383 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10384 return 0; /* already on */
10386 if ((vsi->info.sec_flags &
10387 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10388 return 0; /* already off */
10392 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10394 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10396 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10398 memset(&ctxt, 0, sizeof(ctxt));
10399 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10400 ctxt.seid = vsi->seid;
10402 hw = I40E_VSI_TO_HW(vsi);
10403 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10404 if (ret != I40E_SUCCESS) {
10406 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10413 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10417 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10418 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10421 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10425 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10426 if (!(vsi->vfta[j] & (1 << k)))
10429 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10433 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10435 ret = i40e_aq_add_vlan(hw, vsi->seid,
10436 &vlan_data, 1, NULL);
10438 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10439 &vlan_data, 1, NULL);
10440 if (ret != I40E_SUCCESS) {
10442 "Failed to add/rm vlan filter");
10448 return I40E_SUCCESS;
10452 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10454 struct rte_eth_dev *dev;
10455 struct i40e_pf *pf;
10456 struct i40e_vsi *vsi;
10457 struct i40e_hw *hw;
10458 struct i40e_vsi_context ctxt;
10461 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10463 dev = &rte_eth_devices[port];
10465 if (!is_device_supported(dev, &rte_i40e_pmd))
10468 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10470 if (vf_id >= pf->vf_num || !pf->vfs) {
10471 PMD_DRV_LOG(ERR, "Invalid argument.");
10475 vsi = pf->vfs[vf_id].vsi;
10477 PMD_DRV_LOG(ERR, "Invalid VSI.");
10481 /* Check if it has been already on or off */
10482 if (vsi->vlan_anti_spoof_on == on)
10483 return 0; /* already on or off */
10485 vsi->vlan_anti_spoof_on = on;
10486 if (!vsi->vlan_filter_on) {
10487 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10489 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10494 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10496 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10498 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10500 memset(&ctxt, 0, sizeof(ctxt));
10501 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10502 ctxt.seid = vsi->seid;
10504 hw = I40E_VSI_TO_HW(vsi);
10505 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10506 if (ret != I40E_SUCCESS) {
10508 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10515 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10517 struct i40e_mac_filter *f;
10518 struct i40e_macvlan_filter *mv_f;
10520 enum rte_mac_filter_type filter_type;
10521 int ret = I40E_SUCCESS;
10524 /* remove all the MACs */
10525 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10526 vlan_num = vsi->vlan_num;
10527 filter_type = f->mac_info.filter_type;
10528 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10529 filter_type == RTE_MACVLAN_HASH_MATCH) {
10530 if (vlan_num == 0) {
10531 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10532 return I40E_ERR_PARAM;
10534 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10535 filter_type == RTE_MAC_HASH_MATCH)
10538 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10540 PMD_DRV_LOG(ERR, "failed to allocate memory");
10541 return I40E_ERR_NO_MEMORY;
10544 for (i = 0; i < vlan_num; i++) {
10545 mv_f[i].filter_type = filter_type;
10546 (void)rte_memcpy(&mv_f[i].macaddr,
10547 &f->mac_info.mac_addr,
10550 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10551 filter_type == RTE_MACVLAN_HASH_MATCH) {
10552 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10553 &f->mac_info.mac_addr);
10554 if (ret != I40E_SUCCESS) {
10560 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10561 if (ret != I40E_SUCCESS) {
10567 ret = I40E_SUCCESS;
10574 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10576 struct i40e_mac_filter *f;
10577 struct i40e_macvlan_filter *mv_f;
10578 int i, vlan_num = 0;
10579 int ret = I40E_SUCCESS;
10582 /* restore all the MACs */
10583 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10584 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10585 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10587 * If vlan_num is 0, that's the first time to add mac,
10588 * set mask for vlan_id 0.
10590 if (vsi->vlan_num == 0) {
10591 i40e_set_vlan_filter(vsi, 0, 1);
10594 vlan_num = vsi->vlan_num;
10595 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10596 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10599 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10601 PMD_DRV_LOG(ERR, "failed to allocate memory");
10602 return I40E_ERR_NO_MEMORY;
10605 for (i = 0; i < vlan_num; i++) {
10606 mv_f[i].filter_type = f->mac_info.filter_type;
10607 (void)rte_memcpy(&mv_f[i].macaddr,
10608 &f->mac_info.mac_addr,
10612 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10613 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10614 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10615 &f->mac_info.mac_addr);
10616 if (ret != I40E_SUCCESS) {
10622 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10623 if (ret != I40E_SUCCESS) {
10629 ret = I40E_SUCCESS;
10636 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10638 struct i40e_vsi_context ctxt;
10639 struct i40e_hw *hw;
10645 hw = I40E_VSI_TO_HW(vsi);
10647 /* Use the FW API if FW >= v5.0 */
10648 if (hw->aq.fw_maj_ver < 5) {
10649 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10653 /* Check if it has been already on or off */
10654 if (vsi->info.valid_sections &
10655 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10657 if ((vsi->info.switch_id &
10658 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10659 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10660 return 0; /* already on */
10662 if ((vsi->info.switch_id &
10663 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10664 return 0; /* already off */
10668 /* remove all the MAC and VLAN first */
10669 ret = i40e_vsi_rm_mac_filter(vsi);
10671 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10674 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
10675 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10677 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10682 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10684 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10686 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10688 memset(&ctxt, 0, sizeof(ctxt));
10689 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10690 ctxt.seid = vsi->seid;
10692 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10693 if (ret != I40E_SUCCESS) {
10694 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10698 /* add all the MAC and VLAN back */
10699 ret = i40e_vsi_restore_mac_filter(vsi);
10702 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
10703 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10712 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10714 struct rte_eth_dev *dev;
10715 struct i40e_pf *pf;
10716 struct i40e_pf_vf *vf;
10717 struct i40e_vsi *vsi;
10721 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10723 dev = &rte_eth_devices[port];
10725 if (!is_device_supported(dev, &rte_i40e_pmd))
10728 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10730 /* setup PF TX loopback */
10731 vsi = pf->main_vsi;
10732 ret = i40e_vsi_set_tx_loopback(vsi, on);
10736 /* setup TX loopback for all the VFs */
10738 /* if no VF, do nothing. */
10742 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10743 vf = &pf->vfs[vf_id];
10746 ret = i40e_vsi_set_tx_loopback(vsi, on);
10755 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10757 struct rte_eth_dev *dev;
10758 struct i40e_pf *pf;
10759 struct i40e_vsi *vsi;
10760 struct i40e_hw *hw;
10763 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10765 dev = &rte_eth_devices[port];
10767 if (!is_device_supported(dev, &rte_i40e_pmd))
10770 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10772 if (vf_id >= pf->vf_num || !pf->vfs) {
10773 PMD_DRV_LOG(ERR, "Invalid argument.");
10777 vsi = pf->vfs[vf_id].vsi;
10779 PMD_DRV_LOG(ERR, "Invalid VSI.");
10783 hw = I40E_VSI_TO_HW(vsi);
10785 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10787 if (ret != I40E_SUCCESS) {
10789 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10796 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10798 struct rte_eth_dev *dev;
10799 struct i40e_pf *pf;
10800 struct i40e_vsi *vsi;
10801 struct i40e_hw *hw;
10804 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10806 dev = &rte_eth_devices[port];
10808 if (!is_device_supported(dev, &rte_i40e_pmd))
10811 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10813 if (vf_id >= pf->vf_num || !pf->vfs) {
10814 PMD_DRV_LOG(ERR, "Invalid argument.");
10818 vsi = pf->vfs[vf_id].vsi;
10820 PMD_DRV_LOG(ERR, "Invalid VSI.");
10824 hw = I40E_VSI_TO_HW(vsi);
10826 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10828 if (ret != I40E_SUCCESS) {
10830 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10837 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10838 struct ether_addr *mac_addr)
10840 struct i40e_mac_filter *f;
10841 struct rte_eth_dev *dev;
10842 struct i40e_pf_vf *vf;
10843 struct i40e_vsi *vsi;
10844 struct i40e_pf *pf;
10847 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10850 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10852 dev = &rte_eth_devices[port];
10854 if (!is_device_supported(dev, &rte_i40e_pmd))
10857 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10859 if (vf_id >= pf->vf_num || !pf->vfs)
10862 vf = &pf->vfs[vf_id];
10865 PMD_DRV_LOG(ERR, "Invalid VSI.");
10869 ether_addr_copy(mac_addr, &vf->mac_addr);
10871 /* Remove all existing mac */
10872 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10873 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10878 /* Set vlan strip on/off for specific VF from host */
10880 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10882 struct rte_eth_dev *dev;
10883 struct i40e_pf *pf;
10884 struct i40e_vsi *vsi;
10887 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10889 dev = &rte_eth_devices[port];
10891 if (!is_device_supported(dev, &rte_i40e_pmd))
10894 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10896 if (vf_id >= pf->vf_num || !pf->vfs) {
10897 PMD_DRV_LOG(ERR, "Invalid argument.");
10901 vsi = pf->vfs[vf_id].vsi;
10906 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10907 if (ret != I40E_SUCCESS) {
10909 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10915 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10918 struct rte_eth_dev *dev;
10919 struct i40e_pf *pf;
10920 struct i40e_hw *hw;
10921 struct i40e_vsi *vsi;
10922 struct i40e_vsi_context ctxt;
10925 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10927 if (vlan_id > ETHER_MAX_VLAN_ID) {
10928 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10932 dev = &rte_eth_devices[port];
10934 if (!is_device_supported(dev, &rte_i40e_pmd))
10937 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10938 hw = I40E_PF_TO_HW(pf);
10941 * return -ENODEV if SRIOV not enabled, VF number not configured
10942 * or no queue assigned.
10944 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10945 pf->vf_nb_qps == 0)
10948 if (vf_id >= pf->vf_num || !pf->vfs) {
10949 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10953 vsi = pf->vfs[vf_id].vsi;
10955 PMD_DRV_LOG(ERR, "Invalid VSI.");
10959 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10960 vsi->info.pvid = vlan_id;
10962 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10964 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10966 memset(&ctxt, 0, sizeof(ctxt));
10967 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10968 ctxt.seid = vsi->seid;
10970 hw = I40E_VSI_TO_HW(vsi);
10971 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10972 if (ret != I40E_SUCCESS) {
10974 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10980 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10983 struct rte_eth_dev *dev;
10984 struct i40e_pf *pf;
10985 struct i40e_vsi *vsi;
10986 struct i40e_hw *hw;
10987 struct i40e_mac_filter_info filter;
10988 struct ether_addr broadcast = {
10989 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
10992 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10995 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10999 dev = &rte_eth_devices[port];
11001 if (!is_device_supported(dev, &rte_i40e_pmd))
11004 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11005 hw = I40E_PF_TO_HW(pf);
11007 if (vf_id >= pf->vf_num || !pf->vfs) {
11008 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11013 * return -ENODEV if SRIOV not enabled, VF number not configured
11014 * or no queue assigned.
11016 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11017 pf->vf_nb_qps == 0) {
11018 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11022 vsi = pf->vfs[vf_id].vsi;
11024 PMD_DRV_LOG(ERR, "Invalid VSI.");
11029 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11030 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11031 ret = i40e_vsi_add_mac(vsi, &filter);
11033 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11036 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11038 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11046 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11048 struct rte_eth_dev *dev;
11049 struct i40e_pf *pf;
11050 struct i40e_hw *hw;
11051 struct i40e_vsi *vsi;
11052 struct i40e_vsi_context ctxt;
11055 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11058 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11062 dev = &rte_eth_devices[port];
11064 if (!is_device_supported(dev, &rte_i40e_pmd))
11067 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11068 hw = I40E_PF_TO_HW(pf);
11071 * return -ENODEV if SRIOV not enabled, VF number not configured
11072 * or no queue assigned.
11074 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11075 pf->vf_nb_qps == 0) {
11076 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11080 if (vf_id >= pf->vf_num || !pf->vfs) {
11081 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11085 vsi = pf->vfs[vf_id].vsi;
11087 PMD_DRV_LOG(ERR, "Invalid VSI.");
11091 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11093 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11094 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11096 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11097 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11100 memset(&ctxt, 0, sizeof(ctxt));
11101 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11102 ctxt.seid = vsi->seid;
11104 hw = I40E_VSI_TO_HW(vsi);
11105 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11106 if (ret != I40E_SUCCESS) {
11108 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11114 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11115 uint64_t vf_mask, uint8_t on)
11117 struct rte_eth_dev *dev;
11118 struct i40e_pf *pf;
11119 struct i40e_hw *hw;
11120 struct i40e_vsi *vsi;
11122 int ret = I40E_SUCCESS;
11124 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11126 dev = &rte_eth_devices[port];
11128 if (!is_device_supported(dev, &rte_i40e_pmd))
11131 if (vlan_id > ETHER_MAX_VLAN_ID) {
11132 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11136 if (vf_mask == 0) {
11137 PMD_DRV_LOG(ERR, "No VF.");
11142 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11146 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11147 hw = I40E_PF_TO_HW(pf);
11150 * return -ENODEV if SRIOV not enabled, VF number not configured
11151 * or no queue assigned.
11153 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11154 pf->vf_nb_qps == 0) {
11155 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11159 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11160 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11161 vsi = pf->vfs[vf_idx].vsi;
11163 if (!vsi->vlan_filter_on) {
11164 vsi->vlan_filter_on = true;
11165 if (!vsi->vlan_anti_spoof_on)
11166 i40e_add_rm_all_vlan_filter(
11169 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
11171 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11173 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11178 if (ret != I40E_SUCCESS) {
11180 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11187 rte_pmd_i40e_get_vf_stats(uint8_t port,
11189 struct rte_eth_stats *stats)
11191 struct rte_eth_dev *dev;
11192 struct i40e_pf *pf;
11193 struct i40e_vsi *vsi;
11195 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11197 dev = &rte_eth_devices[port];
11199 if (!is_device_supported(dev, &rte_i40e_pmd))
11202 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11204 if (vf_id >= pf->vf_num || !pf->vfs) {
11205 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11209 vsi = pf->vfs[vf_id].vsi;
11211 PMD_DRV_LOG(ERR, "Invalid VSI.");
11215 i40e_update_vsi_stats(vsi);
11217 stats->ipackets = vsi->eth_stats.rx_unicast +
11218 vsi->eth_stats.rx_multicast +
11219 vsi->eth_stats.rx_broadcast;
11220 stats->opackets = vsi->eth_stats.tx_unicast +
11221 vsi->eth_stats.tx_multicast +
11222 vsi->eth_stats.tx_broadcast;
11223 stats->ibytes = vsi->eth_stats.rx_bytes;
11224 stats->obytes = vsi->eth_stats.tx_bytes;
11225 stats->ierrors = vsi->eth_stats.rx_discards;
11226 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11232 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11235 struct rte_eth_dev *dev;
11236 struct i40e_pf *pf;
11237 struct i40e_vsi *vsi;
11239 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11241 dev = &rte_eth_devices[port];
11243 if (!is_device_supported(dev, &rte_i40e_pmd))
11246 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11248 if (vf_id >= pf->vf_num || !pf->vfs) {
11249 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11253 vsi = pf->vfs[vf_id].vsi;
11255 PMD_DRV_LOG(ERR, "Invalid VSI.");
11259 vsi->offset_loaded = false;
11260 i40e_update_vsi_stats(vsi);