4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_adminq_cmd.h"
57 #include "base/i40e_type.h"
58 #include "i40e_ethdev.h"
59 #include "i40e_rxtx.h"
62 /* Maximun number of MAC addresses */
63 #define I40E_NUM_MACADDR_MAX 64
64 #define I40E_CLEAR_PXE_WAIT_MS 200
66 /* Maximun number of capability elements */
67 #define I40E_MAX_CAP_ELE_NUM 128
69 /* Wait count and inteval */
70 #define I40E_CHK_Q_ENA_COUNT 1000
71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
73 /* Maximun number of VSI */
74 #define I40E_MAX_NUM_VSIS (384UL)
76 /* Default queue interrupt throttling time in microseconds */
77 #define I40E_ITR_INDEX_DEFAULT 0
78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
79 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
110 static int i40e_dev_configure(struct rte_eth_dev *dev);
111 static int i40e_dev_start(struct rte_eth_dev *dev);
112 static void i40e_dev_stop(struct rte_eth_dev *dev);
113 static void i40e_dev_close(struct rte_eth_dev *dev);
114 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
115 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
116 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
117 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
118 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
119 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
120 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
121 struct rte_eth_stats *stats);
122 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
123 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
127 static void i40e_dev_info_get(struct rte_eth_dev *dev,
128 struct rte_eth_dev_info *dev_info);
129 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
132 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
133 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
134 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
137 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
138 static int i40e_dev_led_on(struct rte_eth_dev *dev);
139 static int i40e_dev_led_off(struct rte_eth_dev *dev);
140 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
141 struct rte_eth_fc_conf *fc_conf);
142 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
143 struct rte_eth_pfc_conf *pfc_conf);
144 static void i40e_macaddr_add(struct rte_eth_dev *dev,
145 struct ether_addr *mac_addr,
148 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
149 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
150 struct rte_eth_rss_reta_entry64 *reta_conf,
152 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
153 struct rte_eth_rss_reta_entry64 *reta_conf,
156 static int i40e_get_cap(struct i40e_hw *hw);
157 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
158 static int i40e_pf_setup(struct i40e_pf *pf);
159 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
160 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
161 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
162 bool offset_loaded, uint64_t *offset, uint64_t *stat);
163 static void i40e_stat_update_48(struct i40e_hw *hw,
169 static void i40e_pf_config_irq0(struct i40e_hw *hw);
170 static void i40e_dev_interrupt_handler(
171 __rte_unused struct rte_intr_handle *handle, void *param);
172 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
173 uint32_t base, uint32_t num);
174 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
175 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
177 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
179 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
180 static int i40e_veb_release(struct i40e_veb *veb);
181 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
182 struct i40e_vsi *vsi);
183 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
184 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
185 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
186 struct i40e_macvlan_filter *mv_f,
188 struct ether_addr *addr);
189 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
190 struct i40e_macvlan_filter *mv_f,
193 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
194 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
195 struct rte_eth_rss_conf *rss_conf);
196 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
197 struct rte_eth_rss_conf *rss_conf);
198 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
199 struct rte_eth_udp_tunnel *udp_tunnel);
200 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
201 struct rte_eth_udp_tunnel *udp_tunnel);
202 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
203 struct rte_eth_ethertype_filter *filter,
205 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
206 enum rte_filter_op filter_op,
208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
209 enum rte_filter_type filter_type,
210 enum rte_filter_op filter_op,
212 static void i40e_configure_registers(struct i40e_hw *hw);
213 static void i40e_hw_init(struct i40e_hw *hw);
214 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
216 static const struct rte_pci_id pci_id_i40e_map[] = {
217 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
218 #include "rte_pci_dev_ids.h"
219 { .vendor_id = 0, /* sentinel */ },
222 static const struct eth_dev_ops i40e_eth_dev_ops = {
223 .dev_configure = i40e_dev_configure,
224 .dev_start = i40e_dev_start,
225 .dev_stop = i40e_dev_stop,
226 .dev_close = i40e_dev_close,
227 .promiscuous_enable = i40e_dev_promiscuous_enable,
228 .promiscuous_disable = i40e_dev_promiscuous_disable,
229 .allmulticast_enable = i40e_dev_allmulticast_enable,
230 .allmulticast_disable = i40e_dev_allmulticast_disable,
231 .dev_set_link_up = i40e_dev_set_link_up,
232 .dev_set_link_down = i40e_dev_set_link_down,
233 .link_update = i40e_dev_link_update,
234 .stats_get = i40e_dev_stats_get,
235 .stats_reset = i40e_dev_stats_reset,
236 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
237 .dev_infos_get = i40e_dev_info_get,
238 .vlan_filter_set = i40e_vlan_filter_set,
239 .vlan_tpid_set = i40e_vlan_tpid_set,
240 .vlan_offload_set = i40e_vlan_offload_set,
241 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
242 .vlan_pvid_set = i40e_vlan_pvid_set,
243 .rx_queue_start = i40e_dev_rx_queue_start,
244 .rx_queue_stop = i40e_dev_rx_queue_stop,
245 .tx_queue_start = i40e_dev_tx_queue_start,
246 .tx_queue_stop = i40e_dev_tx_queue_stop,
247 .rx_queue_setup = i40e_dev_rx_queue_setup,
248 .rx_queue_release = i40e_dev_rx_queue_release,
249 .rx_queue_count = i40e_dev_rx_queue_count,
250 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
251 .tx_queue_setup = i40e_dev_tx_queue_setup,
252 .tx_queue_release = i40e_dev_tx_queue_release,
253 .dev_led_on = i40e_dev_led_on,
254 .dev_led_off = i40e_dev_led_off,
255 .flow_ctrl_set = i40e_flow_ctrl_set,
256 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
257 .mac_addr_add = i40e_macaddr_add,
258 .mac_addr_remove = i40e_macaddr_remove,
259 .reta_update = i40e_dev_rss_reta_update,
260 .reta_query = i40e_dev_rss_reta_query,
261 .rss_hash_update = i40e_dev_rss_hash_update,
262 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
263 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
264 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
265 .filter_ctrl = i40e_dev_filter_ctrl,
268 static struct eth_driver rte_i40e_pmd = {
270 .name = "rte_i40e_pmd",
271 .id_table = pci_id_i40e_map,
272 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
274 .eth_dev_init = eth_i40e_dev_init,
275 .dev_private_size = sizeof(struct i40e_adapter),
279 i40e_align_floor(int n)
283 return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
287 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
288 struct rte_eth_link *link)
290 struct rte_eth_link *dst = link;
291 struct rte_eth_link *src = &(dev->data->dev_link);
293 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
294 *(uint64_t *)src) == 0)
301 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
302 struct rte_eth_link *link)
304 struct rte_eth_link *dst = &(dev->data->dev_link);
305 struct rte_eth_link *src = link;
307 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
308 *(uint64_t *)src) == 0)
315 * Driver initialization routine.
316 * Invoked once at EAL init time.
317 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
320 rte_i40e_pmd_init(const char *name __rte_unused,
321 const char *params __rte_unused)
323 PMD_INIT_FUNC_TRACE();
324 rte_eth_driver_register(&rte_i40e_pmd);
329 static struct rte_driver rte_i40e_driver = {
331 .init = rte_i40e_pmd_init,
334 PMD_REGISTER_DRIVER(rte_i40e_driver);
337 * Initialize registers for flexible payload, which should be set by NVM.
338 * This should be removed from code once it is fixed in NVM.
340 #ifndef I40E_GLQF_ORT
341 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
343 #ifndef I40E_GLQF_PIT
344 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
347 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
349 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
350 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
351 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
352 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
353 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
354 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
355 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
356 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
357 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
358 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
360 /* GLQF_PIT Registers */
361 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
362 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
366 eth_i40e_dev_init(struct rte_eth_dev *dev)
368 struct rte_pci_device *pci_dev;
369 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
370 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
371 struct i40e_vsi *vsi;
376 PMD_INIT_FUNC_TRACE();
378 dev->dev_ops = &i40e_eth_dev_ops;
379 dev->rx_pkt_burst = i40e_recv_pkts;
380 dev->tx_pkt_burst = i40e_xmit_pkts;
382 /* for secondary processes, we don't initialise any further as primary
383 * has already done this work. Only check we don't need a different
385 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
386 if (dev->data->scattered_rx)
387 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
390 pci_dev = dev->pci_dev;
391 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
392 pf->adapter->eth_dev = dev;
393 pf->dev_data = dev->data;
395 hw->back = I40E_PF_TO_ADAPTER(pf);
396 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
398 PMD_INIT_LOG(ERR, "Hardware is not available, "
399 "as address is NULL");
403 hw->vendor_id = pci_dev->id.vendor_id;
404 hw->device_id = pci_dev->id.device_id;
405 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
406 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
407 hw->bus.device = pci_dev->addr.devid;
408 hw->bus.func = pci_dev->addr.function;
410 /* Make sure all is clean before doing PF reset */
413 /* Initialize the hardware */
416 /* Reset here to make sure all is clean for each PF */
417 ret = i40e_pf_reset(hw);
419 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
423 /* Initialize the shared code (base driver) */
424 ret = i40e_init_shared_code(hw);
426 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
431 * To work around the NVM issue,initialize registers
432 * for flexible payload by software.
433 * It should be removed once issues are fixed in NVM.
435 i40e_flex_payload_reg_init(hw);
437 /* Initialize the parameters for adminq */
438 i40e_init_adminq_parameter(hw);
439 ret = i40e_init_adminq(hw);
440 if (ret != I40E_SUCCESS) {
441 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
444 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
445 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
446 hw->aq.api_maj_ver, hw->aq.api_min_ver,
447 ((hw->nvm.version >> 12) & 0xf),
448 ((hw->nvm.version >> 4) & 0xff),
449 (hw->nvm.version & 0xf), hw->nvm.eetrack);
452 ret = i40e_aq_stop_lldp(hw, true, NULL);
453 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
454 PMD_INIT_LOG(INFO, "Failed to stop lldp");
457 i40e_clear_pxe_mode(hw);
460 * On X710, performance number is far from the expectation on recent
461 * firmware versions. The fix for this issue may not be integrated in
462 * the following firmware version. So the workaround in software driver
463 * is needed. It needs to modify the initial values of 3 internal only
464 * registers. Note that the workaround can be removed when it is fixed
465 * in firmware in the future.
467 i40e_configure_registers(hw);
469 /* Get hw capabilities */
470 ret = i40e_get_cap(hw);
471 if (ret != I40E_SUCCESS) {
472 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
473 goto err_get_capabilities;
476 /* Initialize parameters for PF */
477 ret = i40e_pf_parameter_init(dev);
479 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
480 goto err_parameter_init;
483 /* Initialize the queue management */
484 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
486 PMD_INIT_LOG(ERR, "Failed to init queue pool");
487 goto err_qp_pool_init;
489 ret = i40e_res_pool_init(&pf->msix_pool, 1,
490 hw->func_caps.num_msix_vectors - 1);
492 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
493 goto err_msix_pool_init;
496 /* Initialize lan hmc */
497 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
498 hw->func_caps.num_rx_qp, 0, 0);
499 if (ret != I40E_SUCCESS) {
500 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
501 goto err_init_lan_hmc;
504 /* Configure lan hmc */
505 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
506 if (ret != I40E_SUCCESS) {
507 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
508 goto err_configure_lan_hmc;
511 /* Get and check the mac address */
512 i40e_get_mac_addr(hw, hw->mac.addr);
513 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
514 PMD_INIT_LOG(ERR, "mac address is not valid");
516 goto err_get_mac_addr;
518 /* Copy the permanent MAC address */
519 ether_addr_copy((struct ether_addr *) hw->mac.addr,
520 (struct ether_addr *) hw->mac.perm_addr);
522 /* Disable flow control */
523 hw->fc.requested_mode = I40E_FC_NONE;
524 i40e_set_fc(hw, &aq_fail, TRUE);
526 /* PF setup, which includes VSI setup */
527 ret = i40e_pf_setup(pf);
529 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
530 goto err_setup_pf_switch;
535 /* Disable double vlan by default */
536 i40e_vsi_config_double_vlan(vsi, FALSE);
538 if (!vsi->max_macaddrs)
539 len = ETHER_ADDR_LEN;
541 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
543 /* Should be after VSI initialized */
544 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
545 if (!dev->data->mac_addrs) {
546 PMD_INIT_LOG(ERR, "Failed to allocated memory "
547 "for storing mac address");
550 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
551 &dev->data->mac_addrs[0]);
553 /* initialize pf host driver to setup SRIOV resource if applicable */
554 i40e_pf_host_init(dev);
556 /* register callback func to eal lib */
557 rte_intr_callback_register(&(pci_dev->intr_handle),
558 i40e_dev_interrupt_handler, (void *)dev);
560 /* configure and enable device interrupt */
561 i40e_pf_config_irq0(hw);
562 i40e_pf_enable_irq0(hw);
564 /* enable uio intr after callback register */
565 rte_intr_enable(&(pci_dev->intr_handle));
570 i40e_vsi_release(pf->main_vsi);
573 err_configure_lan_hmc:
574 (void)i40e_shutdown_lan_hmc(hw);
576 i40e_res_pool_destroy(&pf->msix_pool);
578 i40e_res_pool_destroy(&pf->qp_pool);
581 err_get_capabilities:
582 (void)i40e_shutdown_adminq(hw);
588 i40e_dev_configure(struct rte_eth_dev *dev)
590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
591 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
594 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
595 ret = i40e_fdir_setup(pf);
596 if (ret != I40E_SUCCESS) {
597 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
600 ret = i40e_fdir_configure(dev);
602 PMD_DRV_LOG(ERR, "failed to configure fdir.");
606 i40e_fdir_teardown(pf);
608 ret = i40e_dev_init_vlan(dev);
613 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
614 * RSS setting have different requirements.
615 * General PMD driver call sequence are NIC init, configure,
616 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
617 * will try to lookup the VSI that specific queue belongs to if VMDQ
618 * applicable. So, VMDQ setting has to be done before
619 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
620 * For RSS setting, it will try to calculate actual configured RX queue
621 * number, which will be available after rx_queue_setup(). dev_start()
622 * function is good to place RSS setup.
624 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
625 ret = i40e_vmdq_setup(dev);
631 i40e_fdir_teardown(pf);
636 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
638 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
639 uint16_t msix_vect = vsi->msix_intr;
642 for (i = 0; i < vsi->nb_qps; i++) {
643 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
644 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
648 if (vsi->type != I40E_VSI_SRIOV) {
649 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
650 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
654 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
655 vsi->user_param + (msix_vect - 1);
657 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
659 I40E_WRITE_FLUSH(hw);
662 static inline uint16_t
663 i40e_calc_itr_interval(int16_t interval)
665 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
666 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
668 /* Convert to hardware count, as writing each 1 represents 2 us */
673 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
676 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
677 uint16_t msix_vect = vsi->msix_intr;
680 for (i = 0; i < vsi->nb_qps; i++)
681 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
683 /* Bind all RX queues to allocated MSIX interrupt */
684 for (i = 0; i < vsi->nb_qps; i++) {
685 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
686 I40E_QINT_RQCTL_ITR_INDX_MASK |
687 ((vsi->base_queue + i + 1) <<
688 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
689 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
690 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
692 if (i == vsi->nb_qps - 1)
693 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
694 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
697 /* Write first RX queue to Link list register as the head element */
698 if (vsi->type != I40E_VSI_SRIOV) {
700 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
702 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
704 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
705 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
707 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
708 msix_vect - 1), interval);
710 #ifndef I40E_GLINT_CTL
711 #define I40E_GLINT_CTL 0x0003F800
712 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
714 /* Disable auto-mask on enabling of all none-zero interrupt */
715 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
716 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
720 /* num_msix_vectors_vf needs to minus irq0 */
721 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
722 vsi->user_param + (msix_vect - 1);
724 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
725 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
726 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
729 I40E_WRITE_FLUSH(hw);
733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
735 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
736 uint16_t interval = i40e_calc_itr_interval(\
737 RTE_LIBRTE_I40E_ITR_INTERVAL);
739 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
740 I40E_PFINT_DYN_CTLN_INTENA_MASK |
741 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
742 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
743 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
747 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
749 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
751 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
754 static inline uint8_t
755 i40e_parse_link_speed(uint16_t eth_link_speed)
757 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
759 switch (eth_link_speed) {
760 case ETH_LINK_SPEED_40G:
761 link_speed = I40E_LINK_SPEED_40GB;
763 case ETH_LINK_SPEED_20G:
764 link_speed = I40E_LINK_SPEED_20GB;
766 case ETH_LINK_SPEED_10G:
767 link_speed = I40E_LINK_SPEED_10GB;
769 case ETH_LINK_SPEED_1000:
770 link_speed = I40E_LINK_SPEED_1GB;
772 case ETH_LINK_SPEED_100:
773 link_speed = I40E_LINK_SPEED_100MB;
781 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
783 enum i40e_status_code status;
784 struct i40e_aq_get_phy_abilities_resp phy_ab;
785 struct i40e_aq_set_phy_config phy_conf;
786 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
787 I40E_AQ_PHY_FLAG_PAUSE_RX |
788 I40E_AQ_PHY_FLAG_LOW_POWER;
789 const uint8_t advt = I40E_LINK_SPEED_40GB |
790 I40E_LINK_SPEED_10GB |
791 I40E_LINK_SPEED_1GB |
792 I40E_LINK_SPEED_100MB;
795 /* Skip it on 40G interfaces, as a workaround for the link issue */
796 if (i40e_is_40G_device(hw->device_id))
799 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
804 memset(&phy_conf, 0, sizeof(phy_conf));
806 /* bits 0-2 use the values from get_phy_abilities_resp */
808 abilities |= phy_ab.abilities & mask;
810 /* update ablities and speed */
811 if (abilities & I40E_AQ_PHY_AN_ENABLED)
812 phy_conf.link_speed = advt;
814 phy_conf.link_speed = force_speed;
816 phy_conf.abilities = abilities;
818 /* use get_phy_abilities_resp value for the rest */
819 phy_conf.phy_type = phy_ab.phy_type;
820 phy_conf.eee_capability = phy_ab.eee_capability;
821 phy_conf.eeer = phy_ab.eeer_val;
822 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
824 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
825 phy_ab.abilities, phy_ab.link_speed);
826 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
827 phy_conf.abilities, phy_conf.link_speed);
829 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
837 i40e_apply_link_speed(struct rte_eth_dev *dev)
840 uint8_t abilities = 0;
841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
842 struct rte_eth_conf *conf = &dev->data->dev_conf;
844 speed = i40e_parse_link_speed(conf->link_speed);
845 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
846 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
847 abilities |= I40E_AQ_PHY_AN_ENABLED;
849 abilities |= I40E_AQ_PHY_LINK_ENABLED;
851 return i40e_phy_conf_link(hw, abilities, speed);
855 i40e_dev_start(struct rte_eth_dev *dev)
857 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
859 struct i40e_vsi *main_vsi = pf->main_vsi;
862 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
863 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
864 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
865 dev->data->dev_conf.link_duplex,
871 ret = i40e_dev_rxtx_init(pf);
872 if (ret != I40E_SUCCESS) {
873 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
877 /* Map queues with MSIX interrupt */
878 i40e_vsi_queues_bind_intr(main_vsi);
879 i40e_vsi_enable_queues_intr(main_vsi);
881 /* Map VMDQ VSI queues with MSIX interrupt */
882 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
883 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
884 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
887 /* enable FDIR MSIX interrupt */
888 if (pf->fdir.fdir_vsi) {
889 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
890 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
893 /* Enable all queues which have been configured */
894 ret = i40e_dev_switch_queues(pf, TRUE);
895 if (ret != I40E_SUCCESS) {
896 PMD_DRV_LOG(ERR, "Failed to enable VSI");
900 /* Enable receiving broadcast packets */
901 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
902 if (ret != I40E_SUCCESS)
903 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
905 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
906 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
908 if (ret != I40E_SUCCESS)
909 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
912 /* Apply link configure */
913 ret = i40e_apply_link_speed(dev);
914 if (I40E_SUCCESS != ret) {
915 PMD_DRV_LOG(ERR, "Fail to apply link setting");
922 i40e_dev_switch_queues(pf, FALSE);
923 i40e_dev_clear_queues(dev);
929 i40e_dev_stop(struct rte_eth_dev *dev)
931 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
932 struct i40e_vsi *main_vsi = pf->main_vsi;
935 /* Disable all queues */
936 i40e_dev_switch_queues(pf, FALSE);
938 /* un-map queues with interrupt registers */
939 i40e_vsi_disable_queues_intr(main_vsi);
940 i40e_vsi_queues_unbind_intr(main_vsi);
942 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
943 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
944 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
947 if (pf->fdir.fdir_vsi) {
948 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
949 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
951 /* Clear all queues and release memory */
952 i40e_dev_clear_queues(dev);
955 i40e_dev_set_link_down(dev);
960 i40e_dev_close(struct rte_eth_dev *dev)
962 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
966 PMD_INIT_FUNC_TRACE();
970 /* Disable interrupt */
971 i40e_pf_disable_irq0(hw);
972 rte_intr_disable(&(dev->pci_dev->intr_handle));
974 /* shutdown and destroy the HMC */
975 i40e_shutdown_lan_hmc(hw);
977 /* release all the existing VSIs and VEBs */
978 i40e_fdir_teardown(pf);
979 i40e_vsi_release(pf->main_vsi);
981 /* shutdown the adminq */
982 i40e_aq_queue_shutdown(hw, true);
983 i40e_shutdown_adminq(hw);
985 i40e_res_pool_destroy(&pf->qp_pool);
986 i40e_res_pool_destroy(&pf->msix_pool);
988 /* force a PF reset to clean anything leftover */
989 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
990 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
991 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
992 I40E_WRITE_FLUSH(hw);
996 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
999 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1000 struct i40e_vsi *vsi = pf->main_vsi;
1003 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1005 if (status != I40E_SUCCESS)
1006 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1008 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1010 if (status != I40E_SUCCESS)
1011 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1016 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1018 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1019 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020 struct i40e_vsi *vsi = pf->main_vsi;
1023 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1025 if (status != I40E_SUCCESS)
1026 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1028 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1030 if (status != I40E_SUCCESS)
1031 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1035 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1037 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 struct i40e_vsi *vsi = pf->main_vsi;
1042 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1043 if (ret != I40E_SUCCESS)
1044 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1048 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1051 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052 struct i40e_vsi *vsi = pf->main_vsi;
1055 if (dev->data->promiscuous == 1)
1056 return; /* must remain in all_multicast mode */
1058 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1059 vsi->seid, FALSE, NULL);
1060 if (ret != I40E_SUCCESS)
1061 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1065 * Set device link up.
1068 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1070 /* re-apply link speed setting */
1071 return i40e_apply_link_speed(dev);
1075 * Set device link down.
1078 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1080 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1081 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1082 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084 return i40e_phy_conf_link(hw, abilities, speed);
1088 i40e_dev_link_update(struct rte_eth_dev *dev,
1089 int wait_to_complete)
1091 #define CHECK_INTERVAL 100 /* 100ms */
1092 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1093 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1094 struct i40e_link_status link_status;
1095 struct rte_eth_link link, old;
1097 unsigned rep_cnt = MAX_REPEAT_TIME;
1099 memset(&link, 0, sizeof(link));
1100 memset(&old, 0, sizeof(old));
1101 memset(&link_status, 0, sizeof(link_status));
1102 rte_i40e_dev_atomic_read_link_status(dev, &old);
1105 /* Get link status information from hardware */
1106 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1107 if (status != I40E_SUCCESS) {
1108 link.link_speed = ETH_LINK_SPEED_100;
1109 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1110 PMD_DRV_LOG(ERR, "Failed to get link info");
1114 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1115 if (!wait_to_complete)
1118 rte_delay_ms(CHECK_INTERVAL);
1119 } while (!link.link_status && rep_cnt--);
1121 if (!link.link_status)
1124 /* i40e uses full duplex only */
1125 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1127 /* Parse the link status */
1128 switch (link_status.link_speed) {
1129 case I40E_LINK_SPEED_100MB:
1130 link.link_speed = ETH_LINK_SPEED_100;
1132 case I40E_LINK_SPEED_1GB:
1133 link.link_speed = ETH_LINK_SPEED_1000;
1135 case I40E_LINK_SPEED_10GB:
1136 link.link_speed = ETH_LINK_SPEED_10G;
1138 case I40E_LINK_SPEED_20GB:
1139 link.link_speed = ETH_LINK_SPEED_20G;
1141 case I40E_LINK_SPEED_40GB:
1142 link.link_speed = ETH_LINK_SPEED_40G;
1145 link.link_speed = ETH_LINK_SPEED_100;
1150 rte_i40e_dev_atomic_write_link_status(dev, &link);
1151 if (link.link_status == old.link_status)
1157 /* Get all the statistics of a VSI */
1159 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1161 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1162 struct i40e_eth_stats *nes = &vsi->eth_stats;
1163 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1164 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1166 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1167 vsi->offset_loaded, &oes->rx_bytes,
1169 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1170 vsi->offset_loaded, &oes->rx_unicast,
1172 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1173 vsi->offset_loaded, &oes->rx_multicast,
1174 &nes->rx_multicast);
1175 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1176 vsi->offset_loaded, &oes->rx_broadcast,
1177 &nes->rx_broadcast);
1178 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1179 &oes->rx_discards, &nes->rx_discards);
1180 /* GLV_REPC not supported */
1181 /* GLV_RMPC not supported */
1182 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1183 &oes->rx_unknown_protocol,
1184 &nes->rx_unknown_protocol);
1185 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1186 vsi->offset_loaded, &oes->tx_bytes,
1188 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1189 vsi->offset_loaded, &oes->tx_unicast,
1191 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1192 vsi->offset_loaded, &oes->tx_multicast,
1193 &nes->tx_multicast);
1194 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1195 vsi->offset_loaded, &oes->tx_broadcast,
1196 &nes->tx_broadcast);
1197 /* GLV_TDPC not supported */
1198 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1199 &oes->tx_errors, &nes->tx_errors);
1200 vsi->offset_loaded = true;
1202 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1204 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1205 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1206 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1207 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1208 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1209 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1210 nes->rx_unknown_protocol);
1211 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1212 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1213 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1214 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1215 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1216 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1217 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1221 /* Get all statistics of a port */
1223 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1226 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1227 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1229 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1231 /* Get statistics of struct i40e_eth_stats */
1232 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1233 I40E_GLPRT_GORCL(hw->port),
1234 pf->offset_loaded, &os->eth.rx_bytes,
1236 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1237 I40E_GLPRT_UPRCL(hw->port),
1238 pf->offset_loaded, &os->eth.rx_unicast,
1239 &ns->eth.rx_unicast);
1240 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1241 I40E_GLPRT_MPRCL(hw->port),
1242 pf->offset_loaded, &os->eth.rx_multicast,
1243 &ns->eth.rx_multicast);
1244 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1245 I40E_GLPRT_BPRCL(hw->port),
1246 pf->offset_loaded, &os->eth.rx_broadcast,
1247 &ns->eth.rx_broadcast);
1248 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1249 pf->offset_loaded, &os->eth.rx_discards,
1250 &ns->eth.rx_discards);
1251 /* GLPRT_REPC not supported */
1252 /* GLPRT_RMPC not supported */
1253 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1255 &os->eth.rx_unknown_protocol,
1256 &ns->eth.rx_unknown_protocol);
1257 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1258 I40E_GLPRT_GOTCL(hw->port),
1259 pf->offset_loaded, &os->eth.tx_bytes,
1261 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1262 I40E_GLPRT_UPTCL(hw->port),
1263 pf->offset_loaded, &os->eth.tx_unicast,
1264 &ns->eth.tx_unicast);
1265 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1266 I40E_GLPRT_MPTCL(hw->port),
1267 pf->offset_loaded, &os->eth.tx_multicast,
1268 &ns->eth.tx_multicast);
1269 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1270 I40E_GLPRT_BPTCL(hw->port),
1271 pf->offset_loaded, &os->eth.tx_broadcast,
1272 &ns->eth.tx_broadcast);
1273 /* GLPRT_TEPC not supported */
1275 /* additional port specific stats */
1276 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1277 pf->offset_loaded, &os->tx_dropped_link_down,
1278 &ns->tx_dropped_link_down);
1279 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1280 pf->offset_loaded, &os->crc_errors,
1282 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1283 pf->offset_loaded, &os->illegal_bytes,
1284 &ns->illegal_bytes);
1285 /* GLPRT_ERRBC not supported */
1286 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1287 pf->offset_loaded, &os->mac_local_faults,
1288 &ns->mac_local_faults);
1289 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1290 pf->offset_loaded, &os->mac_remote_faults,
1291 &ns->mac_remote_faults);
1292 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1293 pf->offset_loaded, &os->rx_length_errors,
1294 &ns->rx_length_errors);
1295 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1296 pf->offset_loaded, &os->link_xon_rx,
1298 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1299 pf->offset_loaded, &os->link_xoff_rx,
1301 for (i = 0; i < 8; i++) {
1302 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1304 &os->priority_xon_rx[i],
1305 &ns->priority_xon_rx[i]);
1306 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1308 &os->priority_xoff_rx[i],
1309 &ns->priority_xoff_rx[i]);
1311 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1312 pf->offset_loaded, &os->link_xon_tx,
1314 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1315 pf->offset_loaded, &os->link_xoff_tx,
1317 for (i = 0; i < 8; i++) {
1318 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1320 &os->priority_xon_tx[i],
1321 &ns->priority_xon_tx[i]);
1322 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1324 &os->priority_xoff_tx[i],
1325 &ns->priority_xoff_tx[i]);
1326 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1328 &os->priority_xon_2_xoff[i],
1329 &ns->priority_xon_2_xoff[i]);
1331 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1332 I40E_GLPRT_PRC64L(hw->port),
1333 pf->offset_loaded, &os->rx_size_64,
1335 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1336 I40E_GLPRT_PRC127L(hw->port),
1337 pf->offset_loaded, &os->rx_size_127,
1339 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1340 I40E_GLPRT_PRC255L(hw->port),
1341 pf->offset_loaded, &os->rx_size_255,
1343 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1344 I40E_GLPRT_PRC511L(hw->port),
1345 pf->offset_loaded, &os->rx_size_511,
1347 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1348 I40E_GLPRT_PRC1023L(hw->port),
1349 pf->offset_loaded, &os->rx_size_1023,
1351 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1352 I40E_GLPRT_PRC1522L(hw->port),
1353 pf->offset_loaded, &os->rx_size_1522,
1355 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1356 I40E_GLPRT_PRC9522L(hw->port),
1357 pf->offset_loaded, &os->rx_size_big,
1359 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1360 pf->offset_loaded, &os->rx_undersize,
1362 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1363 pf->offset_loaded, &os->rx_fragments,
1365 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1366 pf->offset_loaded, &os->rx_oversize,
1368 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1369 pf->offset_loaded, &os->rx_jabber,
1371 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1372 I40E_GLPRT_PTC64L(hw->port),
1373 pf->offset_loaded, &os->tx_size_64,
1375 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1376 I40E_GLPRT_PTC127L(hw->port),
1377 pf->offset_loaded, &os->tx_size_127,
1379 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1380 I40E_GLPRT_PTC255L(hw->port),
1381 pf->offset_loaded, &os->tx_size_255,
1383 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1384 I40E_GLPRT_PTC511L(hw->port),
1385 pf->offset_loaded, &os->tx_size_511,
1387 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1388 I40E_GLPRT_PTC1023L(hw->port),
1389 pf->offset_loaded, &os->tx_size_1023,
1391 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1392 I40E_GLPRT_PTC1522L(hw->port),
1393 pf->offset_loaded, &os->tx_size_1522,
1395 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1396 I40E_GLPRT_PTC9522L(hw->port),
1397 pf->offset_loaded, &os->tx_size_big,
1399 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1401 &os->fd_sb_match, &ns->fd_sb_match);
1402 /* GLPRT_MSPDC not supported */
1403 /* GLPRT_XEC not supported */
1405 pf->offset_loaded = true;
1408 i40e_update_vsi_stats(pf->main_vsi);
1410 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1411 ns->eth.rx_broadcast;
1412 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1413 ns->eth.tx_broadcast;
1414 stats->ibytes = ns->eth.rx_bytes;
1415 stats->obytes = ns->eth.tx_bytes;
1416 stats->oerrors = ns->eth.tx_errors;
1417 stats->imcasts = ns->eth.rx_multicast;
1418 stats->fdirmatch = ns->fd_sb_match;
1421 stats->ibadcrc = ns->crc_errors;
1422 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1423 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1424 stats->imissed = ns->eth.rx_discards;
1425 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1427 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1428 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
1429 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
1430 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
1431 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
1432 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
1433 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1434 ns->eth.rx_unknown_protocol);
1435 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
1436 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
1437 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
1438 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
1439 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
1440 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
1442 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
1443 ns->tx_dropped_link_down);
1444 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
1445 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
1447 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
1448 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
1449 ns->mac_local_faults);
1450 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
1451 ns->mac_remote_faults);
1452 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
1453 ns->rx_length_errors);
1454 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
1455 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
1456 for (i = 0; i < 8; i++) {
1457 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
1458 i, ns->priority_xon_rx[i]);
1459 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
1460 i, ns->priority_xoff_rx[i]);
1462 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
1463 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
1464 for (i = 0; i < 8; i++) {
1465 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
1466 i, ns->priority_xon_tx[i]);
1467 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
1468 i, ns->priority_xoff_tx[i]);
1469 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
1470 i, ns->priority_xon_2_xoff[i]);
1472 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
1473 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
1474 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
1475 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
1476 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
1477 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
1478 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
1479 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
1480 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
1481 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
1482 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
1483 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
1484 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
1485 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
1486 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
1487 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
1488 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
1489 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
1490 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1491 ns->mac_short_packet_dropped);
1492 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
1493 ns->checksum_error);
1494 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
1495 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1498 /* Reset the statistics */
1500 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1502 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1504 /* It results in reloading the start point of each counter */
1505 pf->offset_loaded = false;
1509 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1510 __rte_unused uint16_t queue_id,
1511 __rte_unused uint8_t stat_idx,
1512 __rte_unused uint8_t is_rx)
1514 PMD_INIT_FUNC_TRACE();
1520 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1522 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1523 struct i40e_vsi *vsi = pf->main_vsi;
1525 dev_info->max_rx_queues = vsi->nb_qps;
1526 dev_info->max_tx_queues = vsi->nb_qps;
1527 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1528 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1529 dev_info->max_mac_addrs = vsi->max_macaddrs;
1530 dev_info->max_vfs = dev->pci_dev->max_vfs;
1531 dev_info->rx_offload_capa =
1532 DEV_RX_OFFLOAD_VLAN_STRIP |
1533 DEV_RX_OFFLOAD_QINQ_STRIP |
1534 DEV_RX_OFFLOAD_IPV4_CKSUM |
1535 DEV_RX_OFFLOAD_UDP_CKSUM |
1536 DEV_RX_OFFLOAD_TCP_CKSUM;
1537 dev_info->tx_offload_capa =
1538 DEV_TX_OFFLOAD_VLAN_INSERT |
1539 DEV_TX_OFFLOAD_QINQ_INSERT |
1540 DEV_TX_OFFLOAD_IPV4_CKSUM |
1541 DEV_TX_OFFLOAD_UDP_CKSUM |
1542 DEV_TX_OFFLOAD_TCP_CKSUM |
1543 DEV_TX_OFFLOAD_SCTP_CKSUM |
1544 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1545 DEV_TX_OFFLOAD_TCP_TSO;
1546 dev_info->reta_size = pf->hash_lut_size;
1547 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1549 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1551 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1552 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1553 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1555 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1559 dev_info->default_txconf = (struct rte_eth_txconf) {
1561 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1562 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1563 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1565 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1566 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1567 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1568 ETH_TXQ_FLAGS_NOOFFLOADS,
1571 if (pf->flags & I40E_FLAG_VMDQ) {
1572 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1573 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1574 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1575 pf->max_nb_vmdq_vsi;
1576 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1577 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1578 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1583 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1585 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1586 struct i40e_vsi *vsi = pf->main_vsi;
1587 PMD_INIT_FUNC_TRACE();
1590 return i40e_vsi_add_vlan(vsi, vlan_id);
1592 return i40e_vsi_delete_vlan(vsi, vlan_id);
1596 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1597 __rte_unused uint16_t tpid)
1599 PMD_INIT_FUNC_TRACE();
1603 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1605 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1606 struct i40e_vsi *vsi = pf->main_vsi;
1608 if (mask & ETH_VLAN_STRIP_MASK) {
1609 /* Enable or disable VLAN stripping */
1610 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1611 i40e_vsi_config_vlan_stripping(vsi, TRUE);
1613 i40e_vsi_config_vlan_stripping(vsi, FALSE);
1616 if (mask & ETH_VLAN_EXTEND_MASK) {
1617 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1618 i40e_vsi_config_double_vlan(vsi, TRUE);
1620 i40e_vsi_config_double_vlan(vsi, FALSE);
1625 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1626 __rte_unused uint16_t queue,
1627 __rte_unused int on)
1629 PMD_INIT_FUNC_TRACE();
1633 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1635 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1636 struct i40e_vsi *vsi = pf->main_vsi;
1637 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1638 struct i40e_vsi_vlan_pvid_info info;
1640 memset(&info, 0, sizeof(info));
1643 info.config.pvid = pvid;
1645 info.config.reject.tagged =
1646 data->dev_conf.txmode.hw_vlan_reject_tagged;
1647 info.config.reject.untagged =
1648 data->dev_conf.txmode.hw_vlan_reject_untagged;
1651 return i40e_vsi_vlan_pvid_set(vsi, &info);
1655 i40e_dev_led_on(struct rte_eth_dev *dev)
1657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658 uint32_t mode = i40e_led_get(hw);
1661 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1667 i40e_dev_led_off(struct rte_eth_dev *dev)
1669 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670 uint32_t mode = i40e_led_get(hw);
1673 i40e_led_set(hw, 0, false);
1679 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1680 __rte_unused struct rte_eth_fc_conf *fc_conf)
1682 PMD_INIT_FUNC_TRACE();
1688 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1689 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1691 PMD_INIT_FUNC_TRACE();
1696 /* Add a MAC address, and update filters */
1698 i40e_macaddr_add(struct rte_eth_dev *dev,
1699 struct ether_addr *mac_addr,
1700 __rte_unused uint32_t index,
1703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1704 struct i40e_mac_filter_info mac_filter;
1705 struct i40e_vsi *vsi;
1708 /* If VMDQ not enabled or configured, return */
1709 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1710 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1711 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1716 if (pool > pf->nb_cfg_vmdq_vsi) {
1717 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1718 pool, pf->nb_cfg_vmdq_vsi);
1722 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1723 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1728 vsi = pf->vmdq[pool - 1].vsi;
1730 ret = i40e_vsi_add_mac(vsi, &mac_filter);
1731 if (ret != I40E_SUCCESS) {
1732 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1737 /* Remove a MAC address, and update filters */
1739 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1741 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1742 struct i40e_vsi *vsi;
1743 struct rte_eth_dev_data *data = dev->data;
1744 struct ether_addr *macaddr;
1749 macaddr = &(data->mac_addrs[index]);
1751 pool_sel = dev->data->mac_pool_sel[index];
1753 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1754 if (pool_sel & (1ULL << i)) {
1758 /* No VMDQ pool enabled or configured */
1759 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1760 (i > pf->nb_cfg_vmdq_vsi)) {
1761 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1765 vsi = pf->vmdq[i - 1].vsi;
1767 ret = i40e_vsi_delete_mac(vsi, macaddr);
1770 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1777 /* Set perfect match or hash match of MAC and VLAN for a VF */
1779 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1780 struct rte_eth_mac_filter *filter,
1784 struct i40e_mac_filter_info mac_filter;
1785 struct ether_addr old_mac;
1786 struct ether_addr *new_mac;
1787 struct i40e_pf_vf *vf = NULL;
1792 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1795 hw = I40E_PF_TO_HW(pf);
1797 if (filter == NULL) {
1798 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1802 new_mac = &filter->mac_addr;
1804 if (is_zero_ether_addr(new_mac)) {
1805 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1809 vf_id = filter->dst_id;
1811 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1812 PMD_DRV_LOG(ERR, "Invalid argument.");
1815 vf = &pf->vfs[vf_id];
1817 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1818 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1823 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1824 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1826 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1829 mac_filter.filter_type = filter->filter_type;
1830 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1831 if (ret != I40E_SUCCESS) {
1832 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1835 ether_addr_copy(new_mac, &pf->dev_addr);
1837 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1839 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1840 if (ret != I40E_SUCCESS) {
1841 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1845 /* Clear device address as it has been removed */
1846 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1847 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1853 /* MAC filter handle */
1855 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1858 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1859 struct rte_eth_mac_filter *filter;
1860 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1861 int ret = I40E_NOT_SUPPORTED;
1863 filter = (struct rte_eth_mac_filter *)(arg);
1865 switch (filter_op) {
1866 case RTE_ETH_FILTER_NOP:
1869 case RTE_ETH_FILTER_ADD:
1870 i40e_pf_disable_irq0(hw);
1872 ret = i40e_vf_mac_filter_set(pf, filter, 1);
1873 i40e_pf_enable_irq0(hw);
1875 case RTE_ETH_FILTER_DELETE:
1876 i40e_pf_disable_irq0(hw);
1878 ret = i40e_vf_mac_filter_set(pf, filter, 0);
1879 i40e_pf_enable_irq0(hw);
1882 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1883 ret = I40E_ERR_PARAM;
1891 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1892 struct rte_eth_rss_reta_entry64 *reta_conf,
1895 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898 uint16_t i, j, lut_size = pf->hash_lut_size;
1899 uint16_t idx, shift;
1902 if (reta_size != lut_size ||
1903 reta_size > ETH_RSS_RETA_SIZE_512) {
1904 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1905 "(%d) doesn't match the number hardware can supported "
1906 "(%d)\n", reta_size, lut_size);
1910 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1911 idx = i / RTE_RETA_GROUP_SIZE;
1912 shift = i % RTE_RETA_GROUP_SIZE;
1913 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1917 if (mask == I40E_4_BIT_MASK)
1920 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1921 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1922 if (mask & (0x1 << j))
1923 lut |= reta_conf[idx].reta[shift + j] <<
1926 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1928 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1935 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1936 struct rte_eth_rss_reta_entry64 *reta_conf,
1939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 uint16_t i, j, lut_size = pf->hash_lut_size;
1943 uint16_t idx, shift;
1946 if (reta_size != lut_size ||
1947 reta_size > ETH_RSS_RETA_SIZE_512) {
1948 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1949 "(%d) doesn't match the number hardware can supported "
1950 "(%d)\n", reta_size, lut_size);
1954 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1955 idx = i / RTE_RETA_GROUP_SIZE;
1956 shift = i % RTE_RETA_GROUP_SIZE;
1957 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1962 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1963 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1964 if (mask & (0x1 << j))
1965 reta_conf[idx].reta[shift + j] = ((lut >>
1966 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1974 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1975 * @hw: pointer to the HW structure
1976 * @mem: pointer to mem struct to fill out
1977 * @size: size of memory requested
1978 * @alignment: what to align the allocation to
1980 enum i40e_status_code
1981 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1982 struct i40e_dma_mem *mem,
1986 static uint64_t id = 0;
1987 const struct rte_memzone *mz = NULL;
1988 char z_name[RTE_MEMZONE_NAMESIZE];
1991 return I40E_ERR_PARAM;
1994 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
1995 #ifdef RTE_LIBRTE_XEN_DOM0
1996 mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
1999 mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2002 return I40E_ERR_NO_MEMORY;
2007 #ifdef RTE_LIBRTE_XEN_DOM0
2008 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2010 mem->pa = mz->phys_addr;
2013 return I40E_SUCCESS;
2017 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2018 * @hw: pointer to the HW structure
2019 * @mem: ptr to mem struct to free
2021 enum i40e_status_code
2022 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2023 struct i40e_dma_mem *mem)
2025 if (!mem || !mem->va)
2026 return I40E_ERR_PARAM;
2031 return I40E_SUCCESS;
2035 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2036 * @hw: pointer to the HW structure
2037 * @mem: pointer to mem struct to fill out
2038 * @size: size of memory requested
2040 enum i40e_status_code
2041 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2042 struct i40e_virt_mem *mem,
2046 return I40E_ERR_PARAM;
2049 mem->va = rte_zmalloc("i40e", size, 0);
2052 return I40E_SUCCESS;
2054 return I40E_ERR_NO_MEMORY;
2058 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2059 * @hw: pointer to the HW structure
2060 * @mem: pointer to mem struct to free
2062 enum i40e_status_code
2063 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2064 struct i40e_virt_mem *mem)
2067 return I40E_ERR_PARAM;
2072 return I40E_SUCCESS;
2076 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2078 rte_spinlock_init(&sp->spinlock);
2082 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2084 rte_spinlock_lock(&sp->spinlock);
2088 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2090 rte_spinlock_unlock(&sp->spinlock);
2094 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2100 * Get the hardware capabilities, which will be parsed
2101 * and saved into struct i40e_hw.
2104 i40e_get_cap(struct i40e_hw *hw)
2106 struct i40e_aqc_list_capabilities_element_resp *buf;
2107 uint16_t len, size = 0;
2110 /* Calculate a huge enough buff for saving response data temporarily */
2111 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2112 I40E_MAX_CAP_ELE_NUM;
2113 buf = rte_zmalloc("i40e", len, 0);
2115 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2116 return I40E_ERR_NO_MEMORY;
2119 /* Get, parse the capabilities and save it to hw */
2120 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2121 i40e_aqc_opc_list_func_capabilities, NULL);
2122 if (ret != I40E_SUCCESS)
2123 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2125 /* Free the temporary buffer after being used */
2132 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2134 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2135 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2136 uint16_t sum_queues = 0, sum_vsis, left_queues;
2138 /* First check if FW support SRIOV */
2139 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2140 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2144 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2145 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2146 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2147 /* Allocate queues for pf */
2148 if (hw->func_caps.rss) {
2149 pf->flags |= I40E_FLAG_RSS;
2150 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2151 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2152 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2155 sum_queues = pf->lan_nb_qps;
2156 /* Default VSI is not counted in */
2158 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2160 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2161 pf->flags |= I40E_FLAG_SRIOV;
2162 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2163 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2164 PMD_INIT_LOG(ERR, "Config VF number %u, "
2165 "max supported %u.",
2166 dev->pci_dev->max_vfs,
2167 hw->func_caps.num_vfs);
2170 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2171 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2172 "max support %u queues.",
2173 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2176 pf->vf_num = dev->pci_dev->max_vfs;
2177 sum_queues += pf->vf_nb_qps * pf->vf_num;
2178 sum_vsis += pf->vf_num;
2179 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2180 pf->vf_num, pf->vf_nb_qps);
2184 if (hw->func_caps.vmdq) {
2185 pf->flags |= I40E_FLAG_VMDQ;
2186 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2187 pf->max_nb_vmdq_vsi = 1;
2189 * If VMDQ available, assume a single VSI can be created. Will adjust
2192 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2193 sum_vsis += pf->max_nb_vmdq_vsi;
2195 pf->vmdq_nb_qps = 0;
2196 pf->max_nb_vmdq_vsi = 0;
2198 pf->nb_cfg_vmdq_vsi = 0;
2200 if (hw->func_caps.fd) {
2201 pf->flags |= I40E_FLAG_FDIR;
2202 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2204 * Each flow director consumes one VSI and one queue,
2205 * but can't calculate out predictably here.
2209 if (sum_vsis > pf->max_num_vsi ||
2210 sum_queues > hw->func_caps.num_rx_qp) {
2211 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2212 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2213 pf->max_num_vsi, sum_vsis);
2214 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2215 hw->func_caps.num_rx_qp, sum_queues);
2219 /* Adjust VMDQ setting to support as many VMs as possible */
2220 if (pf->flags & I40E_FLAG_VMDQ) {
2221 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2223 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2224 pf->max_num_vsi - sum_vsis);
2226 /* Limit the max VMDQ number that rte_ether that can support */
2227 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2230 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2231 pf->max_nb_vmdq_vsi);
2232 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2235 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2237 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2238 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2239 sum_vsis, hw->func_caps.num_msix_vectors);
2242 return I40E_SUCCESS;
2246 i40e_pf_get_switch_config(struct i40e_pf *pf)
2248 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2249 struct i40e_aqc_get_switch_config_resp *switch_config;
2250 struct i40e_aqc_switch_config_element_resp *element;
2251 uint16_t start_seid = 0, num_reported;
2254 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2255 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2256 if (!switch_config) {
2257 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2261 /* Get the switch configurations */
2262 ret = i40e_aq_get_switch_config(hw, switch_config,
2263 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2264 if (ret != I40E_SUCCESS) {
2265 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2268 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2269 if (num_reported != 1) { /* The number should be 1 */
2270 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2274 /* Parse the switch configuration elements */
2275 element = &(switch_config->element[0]);
2276 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2277 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2278 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2280 PMD_DRV_LOG(INFO, "Unknown element type");
2283 rte_free(switch_config);
2289 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2292 struct pool_entry *entry;
2294 if (pool == NULL || num == 0)
2297 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2298 if (entry == NULL) {
2299 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2303 /* queue heap initialize */
2304 pool->num_free = num;
2305 pool->num_alloc = 0;
2307 LIST_INIT(&pool->alloc_list);
2308 LIST_INIT(&pool->free_list);
2310 /* Initialize element */
2314 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2319 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2321 struct pool_entry *entry;
2326 LIST_FOREACH(entry, &pool->alloc_list, next) {
2327 LIST_REMOVE(entry, next);
2331 LIST_FOREACH(entry, &pool->free_list, next) {
2332 LIST_REMOVE(entry, next);
2337 pool->num_alloc = 0;
2339 LIST_INIT(&pool->alloc_list);
2340 LIST_INIT(&pool->free_list);
2344 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2347 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2348 uint32_t pool_offset;
2352 PMD_DRV_LOG(ERR, "Invalid parameter");
2356 pool_offset = base - pool->base;
2357 /* Lookup in alloc list */
2358 LIST_FOREACH(entry, &pool->alloc_list, next) {
2359 if (entry->base == pool_offset) {
2360 valid_entry = entry;
2361 LIST_REMOVE(entry, next);
2366 /* Not find, return */
2367 if (valid_entry == NULL) {
2368 PMD_DRV_LOG(ERR, "Failed to find entry");
2373 * Found it, move it to free list and try to merge.
2374 * In order to make merge easier, always sort it by qbase.
2375 * Find adjacent prev and last entries.
2378 LIST_FOREACH(entry, &pool->free_list, next) {
2379 if (entry->base > valid_entry->base) {
2387 /* Try to merge with next one*/
2389 /* Merge with next one */
2390 if (valid_entry->base + valid_entry->len == next->base) {
2391 next->base = valid_entry->base;
2392 next->len += valid_entry->len;
2393 rte_free(valid_entry);
2400 /* Merge with previous one */
2401 if (prev->base + prev->len == valid_entry->base) {
2402 prev->len += valid_entry->len;
2403 /* If it merge with next one, remove next node */
2405 LIST_REMOVE(valid_entry, next);
2406 rte_free(valid_entry);
2408 rte_free(valid_entry);
2414 /* Not find any entry to merge, insert */
2417 LIST_INSERT_AFTER(prev, valid_entry, next);
2418 else if (next != NULL)
2419 LIST_INSERT_BEFORE(next, valid_entry, next);
2420 else /* It's empty list, insert to head */
2421 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2424 pool->num_free += valid_entry->len;
2425 pool->num_alloc -= valid_entry->len;
2431 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2434 struct pool_entry *entry, *valid_entry;
2436 if (pool == NULL || num == 0) {
2437 PMD_DRV_LOG(ERR, "Invalid parameter");
2441 if (pool->num_free < num) {
2442 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2443 num, pool->num_free);
2448 /* Lookup in free list and find most fit one */
2449 LIST_FOREACH(entry, &pool->free_list, next) {
2450 if (entry->len >= num) {
2452 if (entry->len == num) {
2453 valid_entry = entry;
2456 if (valid_entry == NULL || valid_entry->len > entry->len)
2457 valid_entry = entry;
2461 /* Not find one to satisfy the request, return */
2462 if (valid_entry == NULL) {
2463 PMD_DRV_LOG(ERR, "No valid entry found");
2467 * The entry have equal queue number as requested,
2468 * remove it from alloc_list.
2470 if (valid_entry->len == num) {
2471 LIST_REMOVE(valid_entry, next);
2474 * The entry have more numbers than requested,
2475 * create a new entry for alloc_list and minus its
2476 * queue base and number in free_list.
2478 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2479 if (entry == NULL) {
2480 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2484 entry->base = valid_entry->base;
2486 valid_entry->base += num;
2487 valid_entry->len -= num;
2488 valid_entry = entry;
2491 /* Insert it into alloc list, not sorted */
2492 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2494 pool->num_free -= valid_entry->len;
2495 pool->num_alloc += valid_entry->len;
2497 return (valid_entry->base + pool->base);
2501 * bitmap_is_subset - Check whether src2 is subset of src1
2504 bitmap_is_subset(uint8_t src1, uint8_t src2)
2506 return !((src1 ^ src2) & src2);
2510 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2512 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2514 /* If DCB is not supported, only default TC is supported */
2515 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2516 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2520 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2521 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2522 "HW support 0x%x", hw->func_caps.enabled_tcmap,
2526 return I40E_SUCCESS;
2530 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2531 struct i40e_vsi_vlan_pvid_info *info)
2534 struct i40e_vsi_context ctxt;
2535 uint8_t vlan_flags = 0;
2538 if (vsi == NULL || info == NULL) {
2539 PMD_DRV_LOG(ERR, "invalid parameters");
2540 return I40E_ERR_PARAM;
2544 vsi->info.pvid = info->config.pvid;
2546 * If insert pvid is enabled, only tagged pkts are
2547 * allowed to be sent out.
2549 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2550 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2553 if (info->config.reject.tagged == 0)
2554 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2556 if (info->config.reject.untagged == 0)
2557 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2559 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2560 I40E_AQ_VSI_PVLAN_MODE_MASK);
2561 vsi->info.port_vlan_flags |= vlan_flags;
2562 vsi->info.valid_sections =
2563 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2564 memset(&ctxt, 0, sizeof(ctxt));
2565 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2566 ctxt.seid = vsi->seid;
2568 hw = I40E_VSI_TO_HW(vsi);
2569 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2570 if (ret != I40E_SUCCESS)
2571 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2577 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2579 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2581 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2583 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2584 if (ret != I40E_SUCCESS)
2588 PMD_DRV_LOG(ERR, "seid not valid");
2592 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2593 tc_bw_data.tc_valid_bits = enabled_tcmap;
2594 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2595 tc_bw_data.tc_bw_credits[i] =
2596 (enabled_tcmap & (1 << i)) ? 1 : 0;
2598 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2599 if (ret != I40E_SUCCESS) {
2600 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2604 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2605 sizeof(vsi->info.qs_handle));
2606 return I40E_SUCCESS;
2610 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2611 struct i40e_aqc_vsi_properties_data *info,
2612 uint8_t enabled_tcmap)
2614 int ret, total_tc = 0, i;
2615 uint16_t qpnum_per_tc, bsf, qp_idx;
2617 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2618 if (ret != I40E_SUCCESS)
2621 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2622 if (enabled_tcmap & (1 << i))
2624 vsi->enabled_tc = enabled_tcmap;
2626 /* Number of queues per enabled TC */
2627 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2628 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2629 bsf = rte_bsf32(qpnum_per_tc);
2631 /* Adjust the queue number to actual queues that can be applied */
2632 vsi->nb_qps = qpnum_per_tc * total_tc;
2635 * Configure TC and queue mapping parameters, for enabled TC,
2636 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2637 * default queue will serve it.
2640 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2641 if (vsi->enabled_tc & (1 << i)) {
2642 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2643 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2644 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2645 qp_idx += qpnum_per_tc;
2647 info->tc_mapping[i] = 0;
2650 /* Associate queue number with VSI */
2651 if (vsi->type == I40E_VSI_SRIOV) {
2652 info->mapping_flags |=
2653 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2654 for (i = 0; i < vsi->nb_qps; i++)
2655 info->queue_mapping[i] =
2656 rte_cpu_to_le_16(vsi->base_queue + i);
2658 info->mapping_flags |=
2659 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2660 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2662 info->valid_sections |=
2663 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2665 return I40E_SUCCESS;
2669 i40e_veb_release(struct i40e_veb *veb)
2671 struct i40e_vsi *vsi;
2674 if (veb == NULL || veb->associate_vsi == NULL)
2677 if (!TAILQ_EMPTY(&veb->head)) {
2678 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2682 vsi = veb->associate_vsi;
2683 hw = I40E_VSI_TO_HW(vsi);
2685 vsi->uplink_seid = veb->uplink_seid;
2686 i40e_aq_delete_element(hw, veb->seid, NULL);
2689 return I40E_SUCCESS;
2693 static struct i40e_veb *
2694 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2696 struct i40e_veb *veb;
2700 if (NULL == pf || vsi == NULL) {
2701 PMD_DRV_LOG(ERR, "veb setup failed, "
2702 "associated VSI shouldn't null");
2705 hw = I40E_PF_TO_HW(pf);
2707 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2709 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2713 veb->associate_vsi = vsi;
2714 TAILQ_INIT(&veb->head);
2715 veb->uplink_seid = vsi->uplink_seid;
2717 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2718 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2720 if (ret != I40E_SUCCESS) {
2721 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2722 hw->aq.asq_last_status);
2726 /* get statistics index */
2727 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2728 &veb->stats_idx, NULL, NULL, NULL);
2729 if (ret != I40E_SUCCESS) {
2730 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2731 hw->aq.asq_last_status);
2735 /* Get VEB bandwidth, to be implemented */
2736 /* Now associated vsi binding to the VEB, set uplink to this VEB */
2737 vsi->uplink_seid = veb->seid;
2746 i40e_vsi_release(struct i40e_vsi *vsi)
2750 struct i40e_vsi_list *vsi_list;
2752 struct i40e_mac_filter *f;
2755 return I40E_SUCCESS;
2757 pf = I40E_VSI_TO_PF(vsi);
2758 hw = I40E_VSI_TO_HW(vsi);
2760 /* VSI has child to attach, release child first */
2762 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2763 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2765 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2767 i40e_veb_release(vsi->veb);
2770 /* Remove all macvlan filters of the VSI */
2771 i40e_vsi_remove_all_macvlan_filter(vsi);
2772 TAILQ_FOREACH(f, &vsi->mac_list, next)
2775 if (vsi->type != I40E_VSI_MAIN) {
2776 /* Remove vsi from parent's sibling list */
2777 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2778 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2779 return I40E_ERR_PARAM;
2781 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2782 &vsi->sib_vsi_list, list);
2784 /* Remove all switch element of the VSI */
2785 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2786 if (ret != I40E_SUCCESS)
2787 PMD_DRV_LOG(ERR, "Failed to delete element");
2789 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2791 if (vsi->type != I40E_VSI_SRIOV)
2792 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2795 return I40E_SUCCESS;
2799 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2801 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2802 struct i40e_aqc_remove_macvlan_element_data def_filter;
2803 struct i40e_mac_filter_info filter;
2806 if (vsi->type != I40E_VSI_MAIN)
2807 return I40E_ERR_CONFIG;
2808 memset(&def_filter, 0, sizeof(def_filter));
2809 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2811 def_filter.vlan_tag = 0;
2812 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2813 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2814 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2815 if (ret != I40E_SUCCESS) {
2816 struct i40e_mac_filter *f;
2817 struct ether_addr *mac;
2819 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2821 /* It needs to add the permanent mac into mac list */
2822 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2824 PMD_DRV_LOG(ERR, "failed to allocate memory");
2825 return I40E_ERR_NO_MEMORY;
2827 mac = &f->mac_info.mac_addr;
2828 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2830 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2831 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2836 (void)rte_memcpy(&filter.mac_addr,
2837 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2838 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2839 return i40e_vsi_add_mac(vsi, &filter);
2843 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2845 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2846 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2847 struct i40e_hw *hw = &vsi->adapter->hw;
2851 memset(&bw_config, 0, sizeof(bw_config));
2852 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2853 if (ret != I40E_SUCCESS) {
2854 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2855 hw->aq.asq_last_status);
2859 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2860 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2861 &ets_sla_config, NULL);
2862 if (ret != I40E_SUCCESS) {
2863 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2864 "configuration %u", hw->aq.asq_last_status);
2868 /* Not store the info yet, just print out */
2869 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2870 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2871 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2872 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2873 ets_sla_config.share_credits[i]);
2874 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2875 rte_le_to_cpu_16(ets_sla_config.credits[i]));
2876 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2877 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2886 i40e_vsi_setup(struct i40e_pf *pf,
2887 enum i40e_vsi_type type,
2888 struct i40e_vsi *uplink_vsi,
2889 uint16_t user_param)
2891 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2892 struct i40e_vsi *vsi;
2893 struct i40e_mac_filter_info filter;
2895 struct i40e_vsi_context ctxt;
2896 struct ether_addr broadcast =
2897 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2899 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2900 PMD_DRV_LOG(ERR, "VSI setup failed, "
2901 "VSI link shouldn't be NULL");
2905 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2906 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2907 "uplink VSI should be NULL");
2911 /* If uplink vsi didn't setup VEB, create one first */
2912 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2913 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2915 if (NULL == uplink_vsi->veb) {
2916 PMD_DRV_LOG(ERR, "VEB setup failed");
2921 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2923 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2926 TAILQ_INIT(&vsi->mac_list);
2928 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2929 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2930 vsi->parent_vsi = uplink_vsi;
2931 vsi->user_param = user_param;
2932 /* Allocate queues */
2933 switch (vsi->type) {
2934 case I40E_VSI_MAIN :
2935 vsi->nb_qps = pf->lan_nb_qps;
2937 case I40E_VSI_SRIOV :
2938 vsi->nb_qps = pf->vf_nb_qps;
2940 case I40E_VSI_VMDQ2:
2941 vsi->nb_qps = pf->vmdq_nb_qps;
2944 vsi->nb_qps = pf->fdir_nb_qps;
2950 * The filter status descriptor is reported in rx queue 0,
2951 * while the tx queue for fdir filter programming has no
2952 * such constraints, can be non-zero queues.
2953 * To simplify it, choose FDIR vsi use queue 0 pair.
2954 * To make sure it will use queue 0 pair, queue allocation
2955 * need be done before this function is called
2957 if (type != I40E_VSI_FDIR) {
2958 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2960 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2964 vsi->base_queue = ret;
2966 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2968 /* VF has MSIX interrupt in VF range, don't allocate here */
2969 if (type != I40E_VSI_SRIOV) {
2970 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2972 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2973 goto fail_queue_alloc;
2975 vsi->msix_intr = ret;
2979 if (type == I40E_VSI_MAIN) {
2980 /* For main VSI, no need to add since it's default one */
2981 vsi->uplink_seid = pf->mac_seid;
2982 vsi->seid = pf->main_vsi_seid;
2983 /* Bind queues with specific MSIX interrupt */
2985 * Needs 2 interrupt at least, one for misc cause which will
2986 * enabled from OS side, Another for queues binding the
2987 * interrupt from device side only.
2990 /* Get default VSI parameters from hardware */
2991 memset(&ctxt, 0, sizeof(ctxt));
2992 ctxt.seid = vsi->seid;
2993 ctxt.pf_num = hw->pf_id;
2994 ctxt.uplink_seid = vsi->uplink_seid;
2996 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
2997 if (ret != I40E_SUCCESS) {
2998 PMD_DRV_LOG(ERR, "Failed to get VSI params");
2999 goto fail_msix_alloc;
3001 (void)rte_memcpy(&vsi->info, &ctxt.info,
3002 sizeof(struct i40e_aqc_vsi_properties_data));
3003 vsi->vsi_id = ctxt.vsi_number;
3004 vsi->info.valid_sections = 0;
3006 /* Configure tc, enabled TC0 only */
3007 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3009 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3010 goto fail_msix_alloc;
3013 /* TC, queue mapping */
3014 memset(&ctxt, 0, sizeof(ctxt));
3015 vsi->info.valid_sections |=
3016 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3017 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3018 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3019 (void)rte_memcpy(&ctxt.info, &vsi->info,
3020 sizeof(struct i40e_aqc_vsi_properties_data));
3021 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3022 I40E_DEFAULT_TCMAP);
3023 if (ret != I40E_SUCCESS) {
3024 PMD_DRV_LOG(ERR, "Failed to configure "
3025 "TC queue mapping");
3026 goto fail_msix_alloc;
3028 ctxt.seid = vsi->seid;
3029 ctxt.pf_num = hw->pf_id;
3030 ctxt.uplink_seid = vsi->uplink_seid;
3033 /* Update VSI parameters */
3034 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3035 if (ret != I40E_SUCCESS) {
3036 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3037 goto fail_msix_alloc;
3040 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3041 sizeof(vsi->info.tc_mapping));
3042 (void)rte_memcpy(&vsi->info.queue_mapping,
3043 &ctxt.info.queue_mapping,
3044 sizeof(vsi->info.queue_mapping));
3045 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3046 vsi->info.valid_sections = 0;
3048 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3052 * Updating default filter settings are necessary to prevent
3053 * reception of tagged packets.
3054 * Some old firmware configurations load a default macvlan
3055 * filter which accepts both tagged and untagged packets.
3056 * The updating is to use a normal filter instead if needed.
3057 * For NVM 4.2.2 or after, the updating is not needed anymore.
3058 * The firmware with correct configurations load the default
3059 * macvlan filter which is expected and cannot be removed.
3061 i40e_update_default_filter_setting(vsi);
3062 i40e_config_qinq(hw, vsi);
3063 } else if (type == I40E_VSI_SRIOV) {
3064 memset(&ctxt, 0, sizeof(ctxt));
3066 * For other VSI, the uplink_seid equals to uplink VSI's
3067 * uplink_seid since they share same VEB
3069 vsi->uplink_seid = uplink_vsi->uplink_seid;
3070 ctxt.pf_num = hw->pf_id;
3071 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3072 ctxt.uplink_seid = vsi->uplink_seid;
3073 ctxt.connection_type = 0x1;
3074 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3077 * Do not configure switch ID to enable VEB switch by
3078 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3079 * if the source mac address of packet sent from VF is not
3080 * listed in the VEB's mac table, the VEB will switch the
3081 * packet back to the VF. Need to enable it when HW issue
3085 /* Configure port/vlan */
3086 ctxt.info.valid_sections |=
3087 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3088 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3089 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3090 I40E_DEFAULT_TCMAP);
3091 if (ret != I40E_SUCCESS) {
3092 PMD_DRV_LOG(ERR, "Failed to configure "
3093 "TC queue mapping");
3094 goto fail_msix_alloc;
3096 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3097 ctxt.info.valid_sections |=
3098 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3100 * Since VSI is not created yet, only configure parameter,
3101 * will add vsi below.
3104 i40e_config_qinq(hw, vsi);
3105 } else if (type == I40E_VSI_VMDQ2) {
3106 memset(&ctxt, 0, sizeof(ctxt));
3108 * For other VSI, the uplink_seid equals to uplink VSI's
3109 * uplink_seid since they share same VEB
3111 vsi->uplink_seid = uplink_vsi->uplink_seid;
3112 ctxt.pf_num = hw->pf_id;
3114 ctxt.uplink_seid = vsi->uplink_seid;
3115 ctxt.connection_type = 0x1;
3116 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3118 ctxt.info.valid_sections |=
3119 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3120 /* user_param carries flag to enable loop back */
3122 ctxt.info.switch_id =
3123 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3124 ctxt.info.switch_id |=
3125 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3128 /* Configure port/vlan */
3129 ctxt.info.valid_sections |=
3130 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3131 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3132 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3133 I40E_DEFAULT_TCMAP);
3134 if (ret != I40E_SUCCESS) {
3135 PMD_DRV_LOG(ERR, "Failed to configure "
3136 "TC queue mapping");
3137 goto fail_msix_alloc;
3139 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3140 ctxt.info.valid_sections |=
3141 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3142 } else if (type == I40E_VSI_FDIR) {
3143 memset(&ctxt, 0, sizeof(ctxt));
3144 vsi->uplink_seid = uplink_vsi->uplink_seid;
3145 ctxt.pf_num = hw->pf_id;
3147 ctxt.uplink_seid = vsi->uplink_seid;
3148 ctxt.connection_type = 0x1; /* regular data port */
3149 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3150 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3151 I40E_DEFAULT_TCMAP);
3152 if (ret != I40E_SUCCESS) {
3153 PMD_DRV_LOG(ERR, "Failed to configure "
3154 "TC queue mapping.");
3155 goto fail_msix_alloc;
3157 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3158 ctxt.info.valid_sections |=
3159 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3161 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3162 goto fail_msix_alloc;
3165 if (vsi->type != I40E_VSI_MAIN) {
3166 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3167 if (ret != I40E_SUCCESS) {
3168 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3169 hw->aq.asq_last_status);
3170 goto fail_msix_alloc;
3172 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3173 vsi->info.valid_sections = 0;
3174 vsi->seid = ctxt.seid;
3175 vsi->vsi_id = ctxt.vsi_number;
3176 vsi->sib_vsi_list.vsi = vsi;
3177 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3178 &vsi->sib_vsi_list, list);
3181 /* MAC/VLAN configuration */
3182 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3183 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3185 ret = i40e_vsi_add_mac(vsi, &filter);
3186 if (ret != I40E_SUCCESS) {
3187 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3188 goto fail_msix_alloc;
3191 /* Get VSI BW information */
3192 i40e_vsi_dump_bw_config(vsi);
3195 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3197 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3203 /* Configure vlan stripping on or off */
3205 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3207 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3208 struct i40e_vsi_context ctxt;
3210 int ret = I40E_SUCCESS;
3212 /* Check if it has been already on or off */
3213 if (vsi->info.valid_sections &
3214 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3216 if ((vsi->info.port_vlan_flags &
3217 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3218 return 0; /* already on */
3220 if ((vsi->info.port_vlan_flags &
3221 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3222 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3223 return 0; /* already off */
3228 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3230 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3231 vsi->info.valid_sections =
3232 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3233 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3234 vsi->info.port_vlan_flags |= vlan_flags;
3235 ctxt.seid = vsi->seid;
3236 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3237 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3239 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3240 on ? "enable" : "disable");
3246 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3248 struct rte_eth_dev_data *data = dev->data;
3251 /* Apply vlan offload setting */
3252 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3254 /* Apply double-vlan setting, not implemented yet */
3256 /* Apply pvid setting */
3257 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3258 data->dev_conf.txmode.hw_vlan_insert_pvid);
3260 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3266 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3268 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3270 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3274 i40e_update_flow_control(struct i40e_hw *hw)
3276 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3277 struct i40e_link_status link_status;
3278 uint32_t rxfc = 0, txfc = 0, reg;
3282 memset(&link_status, 0, sizeof(link_status));
3283 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3284 if (ret != I40E_SUCCESS) {
3285 PMD_DRV_LOG(ERR, "Failed to get link status information");
3286 goto write_reg; /* Disable flow control */
3289 an_info = hw->phy.link_info.an_info;
3290 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3291 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3292 ret = I40E_ERR_NOT_READY;
3293 goto write_reg; /* Disable flow control */
3296 * If link auto negotiation is enabled, flow control needs to
3297 * be configured according to it
3299 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3300 case I40E_LINK_PAUSE_RXTX:
3303 hw->fc.current_mode = I40E_FC_FULL;
3305 case I40E_AQ_LINK_PAUSE_RX:
3307 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3309 case I40E_AQ_LINK_PAUSE_TX:
3311 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3314 hw->fc.current_mode = I40E_FC_NONE;
3319 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3320 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3321 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3322 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3323 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3324 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3331 i40e_pf_setup(struct i40e_pf *pf)
3333 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3334 struct i40e_filter_control_settings settings;
3335 struct i40e_vsi *vsi;
3338 /* Clear all stats counters */
3339 pf->offset_loaded = FALSE;
3340 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3341 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3343 ret = i40e_pf_get_switch_config(pf);
3344 if (ret != I40E_SUCCESS) {
3345 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3348 if (pf->flags & I40E_FLAG_FDIR) {
3349 /* make queue allocated first, let FDIR use queue pair 0*/
3350 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3351 if (ret != I40E_FDIR_QUEUE_ID) {
3352 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3354 pf->flags &= ~I40E_FLAG_FDIR;
3357 /* main VSI setup */
3358 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3360 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3361 return I40E_ERR_NOT_READY;
3365 /* Configure filter control */
3366 memset(&settings, 0, sizeof(settings));
3367 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3368 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3369 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3370 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3372 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3373 hw->func_caps.rss_table_size);
3374 return I40E_ERR_PARAM;
3376 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3377 "size: %u\n", hw->func_caps.rss_table_size);
3378 pf->hash_lut_size = hw->func_caps.rss_table_size;
3380 /* Enable ethtype and macvlan filters */
3381 settings.enable_ethtype = TRUE;
3382 settings.enable_macvlan = TRUE;
3383 ret = i40e_set_filter_control(hw, &settings);
3385 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3388 /* Update flow control according to the auto negotiation */
3389 i40e_update_flow_control(hw);
3391 return I40E_SUCCESS;
3395 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3401 * Set or clear TX Queue Disable flags,
3402 * which is required by hardware.
3404 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3405 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3407 /* Wait until the request is finished */
3408 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3409 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3410 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3411 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3412 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3418 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3419 return I40E_SUCCESS; /* already on, skip next steps */
3421 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3422 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3424 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3425 return I40E_SUCCESS; /* already off, skip next steps */
3426 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3428 /* Write the register */
3429 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3430 /* Check the result */
3431 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3432 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3433 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3435 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3436 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3439 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3440 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3444 /* Check if it is timeout */
3445 if (j >= I40E_CHK_Q_ENA_COUNT) {
3446 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3447 (on ? "enable" : "disable"), q_idx);
3448 return I40E_ERR_TIMEOUT;
3451 return I40E_SUCCESS;
3454 /* Swith on or off the tx queues */
3456 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3458 struct rte_eth_dev_data *dev_data = pf->dev_data;
3459 struct i40e_tx_queue *txq;
3460 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3464 for (i = 0; i < dev_data->nb_tx_queues; i++) {
3465 txq = dev_data->tx_queues[i];
3466 /* Don't operate the queue if not configured or
3467 * if starting only per queue */
3468 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3471 ret = i40e_dev_tx_queue_start(dev, i);
3473 ret = i40e_dev_tx_queue_stop(dev, i);
3474 if ( ret != I40E_SUCCESS)
3478 return I40E_SUCCESS;
3482 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3487 /* Wait until the request is finished */
3488 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3489 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3490 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3491 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3492 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3497 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3498 return I40E_SUCCESS; /* Already on, skip next steps */
3499 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3501 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3502 return I40E_SUCCESS; /* Already off, skip next steps */
3503 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3506 /* Write the register */
3507 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3508 /* Check the result */
3509 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3510 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3511 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3513 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3514 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3517 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3518 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3523 /* Check if it is timeout */
3524 if (j >= I40E_CHK_Q_ENA_COUNT) {
3525 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3526 (on ? "enable" : "disable"), q_idx);
3527 return I40E_ERR_TIMEOUT;
3530 return I40E_SUCCESS;
3532 /* Switch on or off the rx queues */
3534 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3536 struct rte_eth_dev_data *dev_data = pf->dev_data;
3537 struct i40e_rx_queue *rxq;
3538 struct rte_eth_dev *dev = pf->adapter->eth_dev;
3542 for (i = 0; i < dev_data->nb_rx_queues; i++) {
3543 rxq = dev_data->rx_queues[i];
3544 /* Don't operate the queue if not configured or
3545 * if starting only per queue */
3546 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3549 ret = i40e_dev_rx_queue_start(dev, i);
3551 ret = i40e_dev_rx_queue_stop(dev, i);
3552 if (ret != I40E_SUCCESS)
3556 return I40E_SUCCESS;
3559 /* Switch on or off all the rx/tx queues */
3561 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3566 /* enable rx queues before enabling tx queues */
3567 ret = i40e_dev_switch_rx_queues(pf, on);
3569 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3572 ret = i40e_dev_switch_tx_queues(pf, on);
3574 /* Stop tx queues before stopping rx queues */
3575 ret = i40e_dev_switch_tx_queues(pf, on);
3577 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3580 ret = i40e_dev_switch_rx_queues(pf, on);
3586 /* Initialize VSI for TX */
3588 i40e_dev_tx_init(struct i40e_pf *pf)
3590 struct rte_eth_dev_data *data = pf->dev_data;
3592 uint32_t ret = I40E_SUCCESS;
3593 struct i40e_tx_queue *txq;
3595 for (i = 0; i < data->nb_tx_queues; i++) {
3596 txq = data->tx_queues[i];
3597 if (!txq || !txq->q_set)
3599 ret = i40e_tx_queue_init(txq);
3600 if (ret != I40E_SUCCESS)
3607 /* Initialize VSI for RX */
3609 i40e_dev_rx_init(struct i40e_pf *pf)
3611 struct rte_eth_dev_data *data = pf->dev_data;
3612 int ret = I40E_SUCCESS;
3614 struct i40e_rx_queue *rxq;
3616 i40e_pf_config_mq_rx(pf);
3617 for (i = 0; i < data->nb_rx_queues; i++) {
3618 rxq = data->rx_queues[i];
3619 if (!rxq || !rxq->q_set)
3622 ret = i40e_rx_queue_init(rxq);
3623 if (ret != I40E_SUCCESS) {
3624 PMD_DRV_LOG(ERR, "Failed to do RX queue "
3634 i40e_dev_rxtx_init(struct i40e_pf *pf)
3638 err = i40e_dev_tx_init(pf);
3640 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3643 err = i40e_dev_rx_init(pf);
3645 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3653 i40e_vmdq_setup(struct rte_eth_dev *dev)
3655 struct rte_eth_conf *conf = &dev->data->dev_conf;
3656 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3657 int i, err, conf_vsis, j, loop;
3658 struct i40e_vsi *vsi;
3659 struct i40e_vmdq_info *vmdq_info;
3660 struct rte_eth_vmdq_rx_conf *vmdq_conf;
3661 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3664 * Disable interrupt to avoid message from VF. Furthermore, it will
3665 * avoid race condition in VSI creation/destroy.
3667 i40e_pf_disable_irq0(hw);
3669 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3670 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3674 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3675 if (conf_vsis > pf->max_nb_vmdq_vsi) {
3676 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3677 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3678 pf->max_nb_vmdq_vsi);
3682 if (pf->vmdq != NULL) {
3683 PMD_INIT_LOG(INFO, "VMDQ already configured");
3687 pf->vmdq = rte_zmalloc("vmdq_info_struct",
3688 sizeof(*vmdq_info) * conf_vsis, 0);
3690 if (pf->vmdq == NULL) {
3691 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3695 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3697 /* Create VMDQ VSI */
3698 for (i = 0; i < conf_vsis; i++) {
3699 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3700 vmdq_conf->enable_loop_back);
3702 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3706 vmdq_info = &pf->vmdq[i];
3708 vmdq_info->vsi = vsi;
3710 pf->nb_cfg_vmdq_vsi = conf_vsis;
3712 /* Configure Vlan */
3713 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3714 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3715 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3716 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3717 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3718 vmdq_conf->pool_map[i].vlan_id, j);
3720 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3721 vmdq_conf->pool_map[i].vlan_id);
3723 PMD_INIT_LOG(ERR, "Failed to add vlan");
3731 i40e_pf_enable_irq0(hw);
3736 for (i = 0; i < conf_vsis; i++)
3737 if (pf->vmdq[i].vsi == NULL)
3740 i40e_vsi_release(pf->vmdq[i].vsi);
3744 i40e_pf_enable_irq0(hw);
3749 i40e_stat_update_32(struct i40e_hw *hw,
3757 new_data = (uint64_t)I40E_READ_REG(hw, reg);
3761 if (new_data >= *offset)
3762 *stat = (uint64_t)(new_data - *offset);
3764 *stat = (uint64_t)((new_data +
3765 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3769 i40e_stat_update_48(struct i40e_hw *hw,
3778 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3779 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3780 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3785 if (new_data >= *offset)
3786 *stat = new_data - *offset;
3788 *stat = (uint64_t)((new_data +
3789 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3791 *stat &= I40E_48_BIT_MASK;
3796 i40e_pf_disable_irq0(struct i40e_hw *hw)
3798 /* Disable all interrupt types */
3799 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3800 I40E_WRITE_FLUSH(hw);
3805 i40e_pf_enable_irq0(struct i40e_hw *hw)
3807 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3808 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3809 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3810 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3811 I40E_WRITE_FLUSH(hw);
3815 i40e_pf_config_irq0(struct i40e_hw *hw)
3817 /* read pending request and disable first */
3818 i40e_pf_disable_irq0(hw);
3819 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3820 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3821 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3823 /* Link no queues with irq0 */
3824 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3825 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3829 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3835 uint32_t index, offset, val;
3840 * Try to find which VF trigger a reset, use absolute VF id to access
3841 * since the reg is global register.
3843 for (i = 0; i < pf->vf_num; i++) {
3844 abs_vf_id = hw->func_caps.vf_base_id + i;
3845 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3846 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3847 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3848 /* VFR event occured */
3849 if (val & (0x1 << offset)) {
3852 /* Clear the event first */
3853 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3855 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3857 * Only notify a VF reset event occured,
3858 * don't trigger another SW reset
3860 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3861 if (ret != I40E_SUCCESS)
3862 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3868 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3871 struct i40e_arq_event_info info;
3872 uint16_t pending, opcode;
3875 info.buf_len = I40E_AQ_BUF_SZ;
3876 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3877 if (!info.msg_buf) {
3878 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3884 ret = i40e_clean_arq_element(hw, &info, &pending);
3886 if (ret != I40E_SUCCESS) {
3887 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3888 "aq_err: %u", hw->aq.asq_last_status);
3891 opcode = rte_le_to_cpu_16(info.desc.opcode);
3894 case i40e_aqc_opc_send_msg_to_pf:
3895 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3896 i40e_pf_host_handle_vf_msg(dev,
3897 rte_le_to_cpu_16(info.desc.retval),
3898 rte_le_to_cpu_32(info.desc.cookie_high),
3899 rte_le_to_cpu_32(info.desc.cookie_low),
3904 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3909 rte_free(info.msg_buf);
3913 * Interrupt handler is registered as the alarm callback for handling LSC
3914 * interrupt in a definite of time, in order to wait the NIC into a stable
3915 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3916 * no need for link down interrupt.
3919 i40e_dev_interrupt_delayed_handler(void *param)
3921 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3925 /* read interrupt causes again */
3926 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3928 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3929 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3930 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3931 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3932 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3933 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3934 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3935 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3936 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3937 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3938 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3940 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3941 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3942 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3943 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3944 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3946 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3947 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3948 i40e_dev_handle_vfr_event(dev);
3950 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3951 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3952 i40e_dev_handle_aq_msg(dev);
3955 /* handle the link up interrupt in an alarm callback */
3956 i40e_dev_link_update(dev, 0);
3957 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3959 i40e_pf_enable_irq0(hw);
3960 rte_intr_enable(&(dev->pci_dev->intr_handle));
3964 * Interrupt handler triggered by NIC for handling
3965 * specific interrupt.
3968 * Pointer to interrupt handle.
3970 * The address of parameter (struct rte_eth_dev *) regsitered before.
3976 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3979 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3980 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3983 /* Disable interrupt */
3984 i40e_pf_disable_irq0(hw);
3986 /* read out interrupt causes */
3987 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3989 /* No interrupt event indicated */
3990 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
3991 PMD_DRV_LOG(INFO, "No interrupt event");
3994 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3995 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3996 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
3997 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3998 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
3999 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4000 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4001 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4002 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4003 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4004 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4005 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4006 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4007 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4008 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4009 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4011 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4012 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4013 i40e_dev_handle_vfr_event(dev);
4015 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4016 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4017 i40e_dev_handle_aq_msg(dev);
4020 /* Link Status Change interrupt */
4021 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4022 #define I40E_US_PER_SECOND 1000000
4023 struct rte_eth_link link;
4025 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4026 memset(&link, 0, sizeof(link));
4027 rte_i40e_dev_atomic_read_link_status(dev, &link);
4028 i40e_dev_link_update(dev, 0);
4031 * For link up interrupt, it needs to wait 1 second to let the
4032 * hardware be a stable state. Otherwise several consecutive
4033 * interrupts can be observed.
4034 * For link down interrupt, no need to wait.
4036 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4037 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4040 _rte_eth_dev_callback_process(dev,
4041 RTE_ETH_EVENT_INTR_LSC);
4045 /* Enable interrupt */
4046 i40e_pf_enable_irq0(hw);
4047 rte_intr_enable(&(dev->pci_dev->intr_handle));
4051 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4052 struct i40e_macvlan_filter *filter,
4055 int ele_num, ele_buff_size;
4056 int num, actual_num, i;
4058 int ret = I40E_SUCCESS;
4059 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4060 struct i40e_aqc_add_macvlan_element_data *req_list;
4062 if (filter == NULL || total == 0)
4063 return I40E_ERR_PARAM;
4064 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4065 ele_buff_size = hw->aq.asq_buf_size;
4067 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4068 if (req_list == NULL) {
4069 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4070 return I40E_ERR_NO_MEMORY;
4075 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4076 memset(req_list, 0, ele_buff_size);
4078 for (i = 0; i < actual_num; i++) {
4079 (void)rte_memcpy(req_list[i].mac_addr,
4080 &filter[num + i].macaddr, ETH_ADDR_LEN);
4081 req_list[i].vlan_tag =
4082 rte_cpu_to_le_16(filter[num + i].vlan_id);
4084 switch (filter[num + i].filter_type) {
4085 case RTE_MAC_PERFECT_MATCH:
4086 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4087 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4089 case RTE_MACVLAN_PERFECT_MATCH:
4090 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4092 case RTE_MAC_HASH_MATCH:
4093 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4094 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4096 case RTE_MACVLAN_HASH_MATCH:
4097 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4100 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4101 ret = I40E_ERR_PARAM;
4105 req_list[i].queue_number = 0;
4107 req_list[i].flags = rte_cpu_to_le_16(flags);
4110 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4112 if (ret != I40E_SUCCESS) {
4113 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4117 } while (num < total);
4125 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4126 struct i40e_macvlan_filter *filter,
4129 int ele_num, ele_buff_size;
4130 int num, actual_num, i;
4132 int ret = I40E_SUCCESS;
4133 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4134 struct i40e_aqc_remove_macvlan_element_data *req_list;
4136 if (filter == NULL || total == 0)
4137 return I40E_ERR_PARAM;
4139 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4140 ele_buff_size = hw->aq.asq_buf_size;
4142 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4143 if (req_list == NULL) {
4144 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4145 return I40E_ERR_NO_MEMORY;
4150 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4151 memset(req_list, 0, ele_buff_size);
4153 for (i = 0; i < actual_num; i++) {
4154 (void)rte_memcpy(req_list[i].mac_addr,
4155 &filter[num + i].macaddr, ETH_ADDR_LEN);
4156 req_list[i].vlan_tag =
4157 rte_cpu_to_le_16(filter[num + i].vlan_id);
4159 switch (filter[num + i].filter_type) {
4160 case RTE_MAC_PERFECT_MATCH:
4161 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4162 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4164 case RTE_MACVLAN_PERFECT_MATCH:
4165 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4167 case RTE_MAC_HASH_MATCH:
4168 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4169 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4171 case RTE_MACVLAN_HASH_MATCH:
4172 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4175 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4176 ret = I40E_ERR_PARAM;
4179 req_list[i].flags = rte_cpu_to_le_16(flags);
4182 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4184 if (ret != I40E_SUCCESS) {
4185 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4189 } while (num < total);
4196 /* Find out specific MAC filter */
4197 static struct i40e_mac_filter *
4198 i40e_find_mac_filter(struct i40e_vsi *vsi,
4199 struct ether_addr *macaddr)
4201 struct i40e_mac_filter *f;
4203 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4204 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4212 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4215 uint32_t vid_idx, vid_bit;
4217 if (vlan_id > ETH_VLAN_ID_MAX)
4220 vid_idx = I40E_VFTA_IDX(vlan_id);
4221 vid_bit = I40E_VFTA_BIT(vlan_id);
4223 if (vsi->vfta[vid_idx] & vid_bit)
4230 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4231 uint16_t vlan_id, bool on)
4233 uint32_t vid_idx, vid_bit;
4235 if (vlan_id > ETH_VLAN_ID_MAX)
4238 vid_idx = I40E_VFTA_IDX(vlan_id);
4239 vid_bit = I40E_VFTA_BIT(vlan_id);
4242 vsi->vfta[vid_idx] |= vid_bit;
4244 vsi->vfta[vid_idx] &= ~vid_bit;
4248 * Find all vlan options for specific mac addr,
4249 * return with actual vlan found.
4252 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4253 struct i40e_macvlan_filter *mv_f,
4254 int num, struct ether_addr *addr)
4260 * Not to use i40e_find_vlan_filter to decrease the loop time,
4261 * although the code looks complex.
4263 if (num < vsi->vlan_num)
4264 return I40E_ERR_PARAM;
4267 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4269 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4270 if (vsi->vfta[j] & (1 << k)) {
4272 PMD_DRV_LOG(ERR, "vlan number "
4274 return I40E_ERR_PARAM;
4276 (void)rte_memcpy(&mv_f[i].macaddr,
4277 addr, ETH_ADDR_LEN);
4279 j * I40E_UINT32_BIT_SIZE + k;
4285 return I40E_SUCCESS;
4289 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4290 struct i40e_macvlan_filter *mv_f,
4295 struct i40e_mac_filter *f;
4297 if (num < vsi->mac_num)
4298 return I40E_ERR_PARAM;
4300 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4302 PMD_DRV_LOG(ERR, "buffer number not match");
4303 return I40E_ERR_PARAM;
4305 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4307 mv_f[i].vlan_id = vlan;
4308 mv_f[i].filter_type = f->mac_info.filter_type;
4312 return I40E_SUCCESS;
4316 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4319 struct i40e_mac_filter *f;
4320 struct i40e_macvlan_filter *mv_f;
4321 int ret = I40E_SUCCESS;
4323 if (vsi == NULL || vsi->mac_num == 0)
4324 return I40E_ERR_PARAM;
4326 /* Case that no vlan is set */
4327 if (vsi->vlan_num == 0)
4330 num = vsi->mac_num * vsi->vlan_num;
4332 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4334 PMD_DRV_LOG(ERR, "failed to allocate memory");
4335 return I40E_ERR_NO_MEMORY;
4339 if (vsi->vlan_num == 0) {
4340 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4341 (void)rte_memcpy(&mv_f[i].macaddr,
4342 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4343 mv_f[i].vlan_id = 0;
4347 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4348 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4349 vsi->vlan_num, &f->mac_info.mac_addr);
4350 if (ret != I40E_SUCCESS)
4356 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4364 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4366 struct i40e_macvlan_filter *mv_f;
4368 int ret = I40E_SUCCESS;
4370 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4371 return I40E_ERR_PARAM;
4373 /* If it's already set, just return */
4374 if (i40e_find_vlan_filter(vsi,vlan))
4375 return I40E_SUCCESS;
4377 mac_num = vsi->mac_num;
4380 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4381 return I40E_ERR_PARAM;
4384 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4387 PMD_DRV_LOG(ERR, "failed to allocate memory");
4388 return I40E_ERR_NO_MEMORY;
4391 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4393 if (ret != I40E_SUCCESS)
4396 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4398 if (ret != I40E_SUCCESS)
4401 i40e_set_vlan_filter(vsi, vlan, 1);
4411 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4413 struct i40e_macvlan_filter *mv_f;
4415 int ret = I40E_SUCCESS;
4418 * Vlan 0 is the generic filter for untagged packets
4419 * and can't be removed.
4421 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4422 return I40E_ERR_PARAM;
4424 /* If can't find it, just return */
4425 if (!i40e_find_vlan_filter(vsi, vlan))
4426 return I40E_ERR_PARAM;
4428 mac_num = vsi->mac_num;
4431 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4432 return I40E_ERR_PARAM;
4435 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4438 PMD_DRV_LOG(ERR, "failed to allocate memory");
4439 return I40E_ERR_NO_MEMORY;
4442 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4444 if (ret != I40E_SUCCESS)
4447 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4449 if (ret != I40E_SUCCESS)
4452 /* This is last vlan to remove, replace all mac filter with vlan 0 */
4453 if (vsi->vlan_num == 1) {
4454 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4455 if (ret != I40E_SUCCESS)
4458 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4459 if (ret != I40E_SUCCESS)
4463 i40e_set_vlan_filter(vsi, vlan, 0);
4473 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4475 struct i40e_mac_filter *f;
4476 struct i40e_macvlan_filter *mv_f;
4477 int i, vlan_num = 0;
4478 int ret = I40E_SUCCESS;
4480 /* If it's add and we've config it, return */
4481 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4483 return I40E_SUCCESS;
4484 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4485 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4488 * If vlan_num is 0, that's the first time to add mac,
4489 * set mask for vlan_id 0.
4491 if (vsi->vlan_num == 0) {
4492 i40e_set_vlan_filter(vsi, 0, 1);
4495 vlan_num = vsi->vlan_num;
4496 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4497 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4500 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4502 PMD_DRV_LOG(ERR, "failed to allocate memory");
4503 return I40E_ERR_NO_MEMORY;
4506 for (i = 0; i < vlan_num; i++) {
4507 mv_f[i].filter_type = mac_filter->filter_type;
4508 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4512 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4513 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4514 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4515 &mac_filter->mac_addr);
4516 if (ret != I40E_SUCCESS)
4520 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4521 if (ret != I40E_SUCCESS)
4524 /* Add the mac addr into mac list */
4525 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4527 PMD_DRV_LOG(ERR, "failed to allocate memory");
4528 ret = I40E_ERR_NO_MEMORY;
4531 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4533 f->mac_info.filter_type = mac_filter->filter_type;
4534 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4545 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4547 struct i40e_mac_filter *f;
4548 struct i40e_macvlan_filter *mv_f;
4550 enum rte_mac_filter_type filter_type;
4551 int ret = I40E_SUCCESS;
4553 /* Can't find it, return an error */
4554 f = i40e_find_mac_filter(vsi, addr);
4556 return I40E_ERR_PARAM;
4558 vlan_num = vsi->vlan_num;
4559 filter_type = f->mac_info.filter_type;
4560 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4561 filter_type == RTE_MACVLAN_HASH_MATCH) {
4562 if (vlan_num == 0) {
4563 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4564 return I40E_ERR_PARAM;
4566 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4567 filter_type == RTE_MAC_HASH_MATCH)
4570 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4572 PMD_DRV_LOG(ERR, "failed to allocate memory");
4573 return I40E_ERR_NO_MEMORY;
4576 for (i = 0; i < vlan_num; i++) {
4577 mv_f[i].filter_type = filter_type;
4578 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4581 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4582 filter_type == RTE_MACVLAN_HASH_MATCH) {
4583 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4584 if (ret != I40E_SUCCESS)
4588 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4589 if (ret != I40E_SUCCESS)
4592 /* Remove the mac addr into mac list */
4593 TAILQ_REMOVE(&vsi->mac_list, f, next);
4603 /* Configure hash enable flags for RSS */
4605 i40e_config_hena(uint64_t flags)
4612 if (flags & ETH_RSS_FRAG_IPV4)
4613 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4614 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4615 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4616 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4617 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4618 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4619 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4620 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4621 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4622 if (flags & ETH_RSS_FRAG_IPV6)
4623 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4624 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4625 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4626 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4627 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4628 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4629 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4630 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4631 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4632 if (flags & ETH_RSS_L2_PAYLOAD)
4633 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4638 /* Parse the hash enable flags */
4640 i40e_parse_hena(uint64_t flags)
4642 uint64_t rss_hf = 0;
4646 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4647 rss_hf |= ETH_RSS_FRAG_IPV4;
4648 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4649 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4650 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4651 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4652 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4653 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4654 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4655 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4656 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4657 rss_hf |= ETH_RSS_FRAG_IPV6;
4658 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4659 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4660 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4661 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4662 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4663 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4664 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4665 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4666 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4667 rss_hf |= ETH_RSS_L2_PAYLOAD;
4674 i40e_pf_disable_rss(struct i40e_pf *pf)
4676 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4679 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4680 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4681 hena &= ~I40E_RSS_HENA_ALL;
4682 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4683 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4684 I40E_WRITE_FLUSH(hw);
4688 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4691 uint8_t hash_key_len;
4696 hash_key = (uint32_t *)(rss_conf->rss_key);
4697 hash_key_len = rss_conf->rss_key_len;
4698 if (hash_key != NULL && hash_key_len >=
4699 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4700 /* Fill in RSS hash key */
4701 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4702 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4705 rss_hf = rss_conf->rss_hf;
4706 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4707 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4708 hena &= ~I40E_RSS_HENA_ALL;
4709 hena |= i40e_config_hena(rss_hf);
4710 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4711 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4712 I40E_WRITE_FLUSH(hw);
4718 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4719 struct rte_eth_rss_conf *rss_conf)
4721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4725 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4726 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4727 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4728 if (rss_hf != 0) /* Enable RSS */
4730 return 0; /* Nothing to do */
4733 if (rss_hf == 0) /* Disable RSS */
4736 return i40e_hw_rss_hash_set(hw, rss_conf);
4740 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4741 struct rte_eth_rss_conf *rss_conf)
4743 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4748 if (hash_key != NULL) {
4749 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4750 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4751 rss_conf->rss_key_len = i * sizeof(uint32_t);
4753 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4754 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4755 rss_conf->rss_hf = i40e_parse_hena(hena);
4761 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4763 switch (filter_type) {
4764 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4765 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4767 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4768 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4770 case RTE_TUNNEL_FILTER_IMAC_TENID:
4771 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4773 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4774 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4776 case ETH_TUNNEL_FILTER_IMAC:
4777 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4780 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4788 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4789 struct rte_eth_tunnel_filter_conf *tunnel_filter,
4793 uint8_t tun_type = 0;
4795 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4796 struct i40e_vsi *vsi = pf->main_vsi;
4797 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
4798 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
4800 cld_filter = rte_zmalloc("tunnel_filter",
4801 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4804 if (NULL == cld_filter) {
4805 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4808 pfilter = cld_filter;
4810 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4811 sizeof(struct ether_addr));
4812 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4813 sizeof(struct ether_addr));
4815 pfilter->inner_vlan = tunnel_filter->inner_vlan;
4816 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4817 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4818 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4819 &tunnel_filter->ip_addr,
4820 sizeof(pfilter->ipaddr.v4.data));
4822 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4823 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4824 &tunnel_filter->ip_addr,
4825 sizeof(pfilter->ipaddr.v6.data));
4828 /* check tunneled type */
4829 switch (tunnel_filter->tunnel_type) {
4830 case RTE_TUNNEL_TYPE_VXLAN:
4831 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4833 case RTE_TUNNEL_TYPE_NVGRE:
4834 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4837 /* Other tunnel types is not supported. */
4838 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4839 rte_free(cld_filter);
4843 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4846 rte_free(cld_filter);
4850 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4851 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4852 pfilter->tenant_id = tunnel_filter->tenant_id;
4853 pfilter->queue_number = tunnel_filter->queue_id;
4856 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4858 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4861 rte_free(cld_filter);
4866 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4870 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4871 if (pf->vxlan_ports[i] == port)
4879 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4883 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4885 idx = i40e_get_vxlan_port_idx(pf, port);
4887 /* Check if port already exists */
4889 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4893 /* Now check if there is space to add the new port */
4894 idx = i40e_get_vxlan_port_idx(pf, 0);
4896 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4897 "not adding port %d", port);
4901 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4904 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4908 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4911 /* New port: add it and mark its index in the bitmap */
4912 pf->vxlan_ports[idx] = port;
4913 pf->vxlan_bitmap |= (1 << idx);
4915 if (!(pf->flags & I40E_FLAG_VXLAN))
4916 pf->flags |= I40E_FLAG_VXLAN;
4922 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4925 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4927 if (!(pf->flags & I40E_FLAG_VXLAN)) {
4928 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4932 idx = i40e_get_vxlan_port_idx(pf, port);
4935 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4939 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4940 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4944 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4947 pf->vxlan_ports[idx] = 0;
4948 pf->vxlan_bitmap &= ~(1 << idx);
4950 if (!pf->vxlan_bitmap)
4951 pf->flags &= ~I40E_FLAG_VXLAN;
4956 /* Add UDP tunneling port */
4958 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4959 struct rte_eth_udp_tunnel *udp_tunnel)
4962 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4964 if (udp_tunnel == NULL)
4967 switch (udp_tunnel->prot_type) {
4968 case RTE_TUNNEL_TYPE_VXLAN:
4969 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4972 case RTE_TUNNEL_TYPE_GENEVE:
4973 case RTE_TUNNEL_TYPE_TEREDO:
4974 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4979 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4987 /* Remove UDP tunneling port */
4989 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
4990 struct rte_eth_udp_tunnel *udp_tunnel)
4993 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4995 if (udp_tunnel == NULL)
4998 switch (udp_tunnel->prot_type) {
4999 case RTE_TUNNEL_TYPE_VXLAN:
5000 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5002 case RTE_TUNNEL_TYPE_GENEVE:
5003 case RTE_TUNNEL_TYPE_TEREDO:
5004 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5008 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5016 /* Calculate the maximum number of contiguous PF queues that are configured */
5018 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5020 struct rte_eth_dev_data *data = pf->dev_data;
5022 struct i40e_rx_queue *rxq;
5025 for (i = 0; i < pf->lan_nb_qps; i++) {
5026 rxq = data->rx_queues[i];
5027 if (rxq && rxq->q_set)
5038 i40e_pf_config_rss(struct i40e_pf *pf)
5040 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5041 struct rte_eth_rss_conf rss_conf;
5042 uint32_t i, lut = 0;
5046 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5047 * It's necessary to calulate the actual PF queues that are configured.
5049 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5050 num = i40e_pf_calc_configured_queues_num(pf);
5051 num = i40e_align_floor(num);
5053 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5055 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5059 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5063 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5066 lut = (lut << 8) | (j & ((0x1 <<
5067 hw->func_caps.rss_table_entry_width) - 1));
5069 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5072 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5073 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5074 i40e_pf_disable_rss(pf);
5077 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5078 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5079 /* Random default keys */
5080 static uint32_t rss_key_default[] = {0x6b793944,
5081 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5082 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5083 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5085 rss_conf.rss_key = (uint8_t *)rss_key_default;
5086 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5090 return i40e_hw_rss_hash_set(hw, &rss_conf);
5094 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5095 struct rte_eth_tunnel_filter_conf *filter)
5097 if (pf == NULL || filter == NULL) {
5098 PMD_DRV_LOG(ERR, "Invalid parameter");
5102 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5103 PMD_DRV_LOG(ERR, "Invalid queue ID");
5107 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5108 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5112 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5113 (is_zero_ether_addr(filter->outer_mac))) {
5114 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5118 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5119 (is_zero_ether_addr(filter->inner_mac))) {
5120 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5128 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5131 struct rte_eth_tunnel_filter_conf *filter;
5132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5133 int ret = I40E_SUCCESS;
5135 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5137 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5138 return I40E_ERR_PARAM;
5140 switch (filter_op) {
5141 case RTE_ETH_FILTER_NOP:
5142 if (!(pf->flags & I40E_FLAG_VXLAN))
5143 ret = I40E_NOT_SUPPORTED;
5144 case RTE_ETH_FILTER_ADD:
5145 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5147 case RTE_ETH_FILTER_DELETE:
5148 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5151 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5152 ret = I40E_ERR_PARAM;
5160 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5163 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5165 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5166 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5171 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5172 ret = i40e_pf_config_rss(pf);
5174 i40e_pf_disable_rss(pf);
5179 /* Get the symmetric hash enable configurations per port */
5181 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5183 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5185 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5188 /* Set the symmetric hash enable configurations per port */
5190 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5192 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5195 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5196 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5200 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5202 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5203 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5207 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5209 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5210 I40E_WRITE_FLUSH(hw);
5214 * Get global configurations of hash function type and symmetric hash enable
5215 * per flow type (pctype). Note that global configuration means it affects all
5216 * the ports on the same NIC.
5219 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5220 struct rte_eth_hash_global_conf *g_cfg)
5222 uint32_t reg, mask = I40E_FLOW_TYPES;
5224 enum i40e_filter_pctype pctype;
5226 memset(g_cfg, 0, sizeof(*g_cfg));
5227 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5228 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5229 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5231 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5232 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5233 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5235 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5236 if (!(mask & (1UL << i)))
5238 mask &= ~(1UL << i);
5239 /* Bit set indicats the coresponding flow type is supported */
5240 g_cfg->valid_bit_mask[0] |= (1UL << i);
5241 pctype = i40e_flowtype_to_pctype(i);
5242 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5243 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5244 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5251 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5254 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5256 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5257 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5258 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5259 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5265 * As i40e supports less than 32 flow types, only first 32 bits need to
5268 mask0 = g_cfg->valid_bit_mask[0];
5269 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5271 /* Check if any unsupported flow type configured */
5272 if ((mask0 | i40e_mask) ^ i40e_mask)
5275 if (g_cfg->valid_bit_mask[i])
5283 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5289 * Set global configurations of hash function type and symmetric hash enable
5290 * per flow type (pctype). Note any modifying global configuration will affect
5291 * all the ports on the same NIC.
5294 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5295 struct rte_eth_hash_global_conf *g_cfg)
5300 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5301 enum i40e_filter_pctype pctype;
5303 /* Check the input parameters */
5304 ret = i40e_hash_global_config_check(g_cfg);
5308 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5309 if (!(mask0 & (1UL << i)))
5311 mask0 &= ~(1UL << i);
5312 pctype = i40e_flowtype_to_pctype(i);
5313 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5314 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5315 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5318 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5319 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5321 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5322 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5326 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5327 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5329 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5330 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5334 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5336 /* Use the default, and keep it as it is */
5339 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5342 I40E_WRITE_FLUSH(hw);
5348 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5353 PMD_DRV_LOG(ERR, "Invalid pointer");
5357 switch (info->info_type) {
5358 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5359 i40e_get_symmetric_hash_enable_per_port(hw,
5360 &(info->info.enable));
5362 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5363 ret = i40e_get_hash_filter_global_config(hw,
5364 &(info->info.global_conf));
5367 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5377 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5382 PMD_DRV_LOG(ERR, "Invalid pointer");
5386 switch (info->info_type) {
5387 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5388 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5390 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5391 ret = i40e_set_hash_filter_global_config(hw,
5392 &(info->info.global_conf));
5395 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5404 /* Operations for hash function */
5406 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5407 enum rte_filter_op filter_op,
5410 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413 switch (filter_op) {
5414 case RTE_ETH_FILTER_NOP:
5416 case RTE_ETH_FILTER_GET:
5417 ret = i40e_hash_filter_get(hw,
5418 (struct rte_eth_hash_filter_info *)arg);
5420 case RTE_ETH_FILTER_SET:
5421 ret = i40e_hash_filter_set(hw,
5422 (struct rte_eth_hash_filter_info *)arg);
5425 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5435 * Configure ethertype filter, which can director packet by filtering
5436 * with mac address and ether_type or only ether_type
5439 i40e_ethertype_filter_set(struct i40e_pf *pf,
5440 struct rte_eth_ethertype_filter *filter,
5443 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5444 struct i40e_control_filter_stats stats;
5448 if (filter->queue >= pf->dev_data->nb_rx_queues) {
5449 PMD_DRV_LOG(ERR, "Invalid queue ID");
5452 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5453 filter->ether_type == ETHER_TYPE_IPv6) {
5454 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5455 " control packet filter.", filter->ether_type);
5458 if (filter->ether_type == ETHER_TYPE_VLAN)
5459 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5462 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5463 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5464 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5465 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5466 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5468 memset(&stats, 0, sizeof(stats));
5469 ret = i40e_aq_add_rem_control_packet_filter(hw,
5470 filter->mac_addr.addr_bytes,
5471 filter->ether_type, flags,
5473 filter->queue, add, &stats, NULL);
5475 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5476 " mac_etype_used = %u, etype_used = %u,"
5477 " mac_etype_free = %u, etype_free = %u\n",
5478 ret, stats.mac_etype_used, stats.etype_used,
5479 stats.mac_etype_free, stats.etype_free);
5486 * Handle operations for ethertype filter.
5489 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5490 enum rte_filter_op filter_op,
5493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5496 if (filter_op == RTE_ETH_FILTER_NOP)
5500 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5505 switch (filter_op) {
5506 case RTE_ETH_FILTER_ADD:
5507 ret = i40e_ethertype_filter_set(pf,
5508 (struct rte_eth_ethertype_filter *)arg,
5511 case RTE_ETH_FILTER_DELETE:
5512 ret = i40e_ethertype_filter_set(pf,
5513 (struct rte_eth_ethertype_filter *)arg,
5517 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5525 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5526 enum rte_filter_type filter_type,
5527 enum rte_filter_op filter_op,
5535 switch (filter_type) {
5536 case RTE_ETH_FILTER_HASH:
5537 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5539 case RTE_ETH_FILTER_MACVLAN:
5540 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5542 case RTE_ETH_FILTER_ETHERTYPE:
5543 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5545 case RTE_ETH_FILTER_TUNNEL:
5546 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5548 case RTE_ETH_FILTER_FDIR:
5549 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5552 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5562 * As some registers wouldn't be reset unless a global hardware reset,
5563 * hardware initialization is needed to put those registers into an
5564 * expected initial state.
5567 i40e_hw_init(struct i40e_hw *hw)
5569 /* clear the PF Queue Filter control register */
5570 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5572 /* Disable symmetric hash per port */
5573 i40e_set_symmetric_hash_enable_per_port(hw, 0);
5576 enum i40e_filter_pctype
5577 i40e_flowtype_to_pctype(uint16_t flow_type)
5579 static const enum i40e_filter_pctype pctype_table[] = {
5580 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5581 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5582 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5583 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5584 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5585 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5586 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5587 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5588 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5589 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5590 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5591 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5592 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5593 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5594 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5595 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5596 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5597 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5598 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5601 return pctype_table[flow_type];
5605 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5607 static const uint16_t flowtype_table[] = {
5608 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5609 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5610 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5611 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5612 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5613 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5614 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5615 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5616 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5617 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5618 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5619 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5620 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5621 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5622 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5623 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5624 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5625 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5626 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5629 return flowtype_table[pctype];
5633 * On X710, performance number is far from the expectation on recent firmware
5634 * versions; on XL710, performance number is also far from the expectation on
5635 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5636 * mode is enabled and port MAC address is equal to the packet destination MAC
5637 * address. The fix for this issue may not be integrated in the following
5638 * firmware version. So the workaround in software driver is needed. It needs
5639 * to modify the initial values of 3 internal only registers for both X710 and
5640 * XL710. Note that the values for X710 or XL710 could be different, and the
5641 * workaround can be removed when it is fixed in firmware in the future.
5644 /* For both X710 and XL710 */
5645 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5646 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
5648 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5649 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
5652 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
5654 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
5655 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
5658 i40e_configure_registers(struct i40e_hw *hw)
5664 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5665 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5666 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5672 for (i = 0; i < RTE_DIM(reg_table); i++) {
5673 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5674 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5676 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5679 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5682 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5685 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5689 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5690 reg_table[i].addr, reg);
5691 if (reg == reg_table[i].val)
5694 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5695 reg_table[i].val, NULL);
5697 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5698 "address of 0x%"PRIx32, reg_table[i].val,
5702 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5703 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5707 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
5708 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
5709 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
5710 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5712 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5717 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5718 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5722 /* Configure for double VLAN RX stripping */
5723 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5724 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5725 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5726 ret = i40e_aq_debug_write_register(hw,
5727 I40E_VSI_TSR(vsi->vsi_id),
5730 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5732 return I40E_ERR_CONFIG;
5736 /* Configure for double VLAN TX insertion */
5737 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5738 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5739 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5740 ret = i40e_aq_debug_write_register(hw,
5741 I40E_VSI_L2TAGSTXVALID(
5742 vsi->vsi_id), reg, NULL);
5744 PMD_DRV_LOG(ERR, "Failed to update "
5745 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5746 return I40E_ERR_CONFIG;