1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
50 #define I40E_CLEAR_PXE_WAIT_MS 200
51 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
52 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
54 /* Maximun number of capability elements */
55 #define I40E_MAX_CAP_ELE_NUM 128
57 /* Wait count and interval */
58 #define I40E_CHK_Q_ENA_COUNT 1000
59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
61 /* Maximun number of VSI */
62 #define I40E_MAX_NUM_VSIS (384UL)
64 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
66 /* Flow control default timer */
67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
69 /* Flow control enable fwd bit */
70 #define I40E_PRTMAC_FWD_CTRL 0x00000001
72 /* Receive Packet Buffer size */
73 #define I40E_RXPBSIZE (968 * 1024)
76 #define I40E_KILOSHIFT 10
78 /* Flow control default high water */
79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Flow control default low water */
82 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
84 /* Receive Average Packet Size in Byte*/
85 #define I40E_PACKET_AVERAGE_SIZE 128
87 /* Mask of PF interrupt causes */
88 #define I40E_PFINT_ICR0_ENA_MASK ( \
89 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
90 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_GRST_MASK | \
92 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
93 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
94 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
95 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
96 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
97 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
99 #define I40E_FLOW_TYPES ( \
100 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
105 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
110 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
112 /* Additional timesync values. */
113 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
114 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
115 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
116 #define I40E_PRTTSYN_TSYNENA 0x80000000
117 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
118 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
121 * Below are values for writing un-exposed registers suggested
124 /* Destination MAC address */
125 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
126 /* Source MAC address */
127 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
129 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
131 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
132 /* Single VLAN tag in the inner L2 header */
133 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
134 /* Source IPv4 address */
135 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
136 /* Destination IPv4 address */
137 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
138 /* Source IPv4 address for X722 */
139 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
140 /* Destination IPv4 address for X722 */
141 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
142 /* IPv4 Protocol for X722 */
143 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
144 /* IPv4 Time to Live for X722 */
145 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
146 /* IPv4 Type of Service (TOS) */
147 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
149 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
150 /* IPv4 Time to Live */
151 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
152 /* Source IPv6 address */
153 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
154 /* Destination IPv6 address */
155 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
156 /* IPv6 Traffic Class (TC) */
157 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
158 /* IPv6 Next Header */
159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
163 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
164 /* Destination L4 port */
165 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
166 /* SCTP verification tag */
167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
170 /* Source port of tunneling UDP */
171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
172 /* Destination port of tunneling UDP */
173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
174 /* UDP Tunneling ID, NVGRE/GRE key */
175 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
176 /* Last ether type */
177 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
178 /* Tunneling outer destination IPv4 address */
179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
180 /* Tunneling outer destination IPv6 address */
181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
182 /* 1st word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
184 /* 2nd word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
186 /* 3rd word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
188 /* 4th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
190 /* 5th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
192 /* 6th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
194 /* 7th word of flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
196 /* 8th word of flex payload */
197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
198 /* all 8 words flex payload */
199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
200 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
202 #define I40E_TRANSLATE_INSET 0
203 #define I40E_TRANSLATE_REG 1
205 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
206 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
207 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
208 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
210 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
212 /* PCI offset for querying capability */
213 #define PCI_DEV_CAP_REG 0xA4
214 /* PCI offset for enabling/disabling Extended Tag */
215 #define PCI_DEV_CTRL_REG 0xA8
216 /* Bit mask of Extended Tag capability */
217 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
218 /* Bit shift of Extended Tag enable/disable */
219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
220 /* Bit mask of Extended Tag enable/disable */
221 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
225 static int i40e_dev_configure(struct rte_eth_dev *dev);
226 static int i40e_dev_start(struct rte_eth_dev *dev);
227 static void i40e_dev_stop(struct rte_eth_dev *dev);
228 static void i40e_dev_close(struct rte_eth_dev *dev);
229 static int i40e_dev_reset(struct rte_eth_dev *dev);
230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
237 struct rte_eth_stats *stats);
238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
239 struct rte_eth_xstat *xstats, unsigned n);
240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
241 struct rte_eth_xstat_name *xstats_names,
243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
245 char *fw_version, size_t fw_size);
246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
247 struct rte_eth_dev_info *dev_info);
248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
252 enum rte_vlan_type vlan_type,
254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_fc_conf *fc_conf);
265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
266 struct rte_eth_pfc_conf *pfc_conf);
267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
268 struct rte_ether_addr *mac_addr,
271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
276 struct rte_eth_rss_reta_entry64 *reta_conf,
279 static int i40e_get_cap(struct i40e_hw *hw);
280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
281 static int i40e_pf_setup(struct i40e_pf *pf);
282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
286 bool offset_loaded, uint64_t *offset, uint64_t *stat);
287 static void i40e_stat_update_48(struct i40e_hw *hw,
293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
294 static void i40e_dev_interrupt_handler(void *param);
295 static void i40e_dev_alarm_handler(void *param);
296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
297 uint32_t base, uint32_t num);
298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
304 static int i40e_veb_release(struct i40e_veb *veb);
305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
306 struct i40e_vsi *vsi);
307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
309 struct i40e_macvlan_filter *mv_f,
312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
322 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
326 enum rte_filter_type filter_type,
327 enum rte_filter_op filter_op,
329 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
331 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
332 static void i40e_configure_registers(struct i40e_hw *hw);
333 static void i40e_hw_init(struct rte_eth_dev *dev);
334 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
335 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
341 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
342 struct rte_eth_mirror_conf *mirror_conf,
343 uint8_t sw_id, uint8_t on);
344 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
346 static int i40e_timesync_enable(struct rte_eth_dev *dev);
347 static int i40e_timesync_disable(struct rte_eth_dev *dev);
348 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp,
351 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
352 struct timespec *timestamp);
353 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
355 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
357 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
360 const struct timespec *timestamp);
362 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
364 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
367 static int i40e_get_regs(struct rte_eth_dev *dev,
368 struct rte_dev_reg_info *regs);
370 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
372 static int i40e_get_eeprom(struct rte_eth_dev *dev,
373 struct rte_dev_eeprom_info *eeprom);
375 static int i40e_get_module_info(struct rte_eth_dev *dev,
376 struct rte_eth_dev_module_info *modinfo);
377 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
378 struct rte_dev_eeprom_info *info);
380 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
381 struct rte_ether_addr *mac_addr);
383 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
385 static int i40e_ethertype_filter_convert(
386 const struct rte_eth_ethertype_filter *input,
387 struct i40e_ethertype_filter *filter);
388 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
389 struct i40e_ethertype_filter *filter);
391 static int i40e_tunnel_filter_convert(
392 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
398 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
399 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
400 static void i40e_filter_restore(struct i40e_pf *pf);
401 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
402 static int i40e_pf_config_rss(struct i40e_pf *pf);
404 static const char *const valid_keys[] = {
405 ETH_I40E_FLOATING_VEB_ARG,
406 ETH_I40E_FLOATING_VEB_LIST_ARG,
407 ETH_I40E_SUPPORT_MULTI_DRIVER,
408 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
409 ETH_I40E_USE_LATEST_VEC,
413 static const struct rte_pci_id pci_id_i40e_map[] = {
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
440 { .vendor_id = 0, /* sentinel */ },
443 static const struct eth_dev_ops i40e_eth_dev_ops = {
444 .dev_configure = i40e_dev_configure,
445 .dev_start = i40e_dev_start,
446 .dev_stop = i40e_dev_stop,
447 .dev_close = i40e_dev_close,
448 .dev_reset = i40e_dev_reset,
449 .promiscuous_enable = i40e_dev_promiscuous_enable,
450 .promiscuous_disable = i40e_dev_promiscuous_disable,
451 .allmulticast_enable = i40e_dev_allmulticast_enable,
452 .allmulticast_disable = i40e_dev_allmulticast_disable,
453 .dev_set_link_up = i40e_dev_set_link_up,
454 .dev_set_link_down = i40e_dev_set_link_down,
455 .link_update = i40e_dev_link_update,
456 .stats_get = i40e_dev_stats_get,
457 .xstats_get = i40e_dev_xstats_get,
458 .xstats_get_names = i40e_dev_xstats_get_names,
459 .stats_reset = i40e_dev_stats_reset,
460 .xstats_reset = i40e_dev_stats_reset,
461 .fw_version_get = i40e_fw_version_get,
462 .dev_infos_get = i40e_dev_info_get,
463 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
464 .vlan_filter_set = i40e_vlan_filter_set,
465 .vlan_tpid_set = i40e_vlan_tpid_set,
466 .vlan_offload_set = i40e_vlan_offload_set,
467 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
468 .vlan_pvid_set = i40e_vlan_pvid_set,
469 .rx_queue_start = i40e_dev_rx_queue_start,
470 .rx_queue_stop = i40e_dev_rx_queue_stop,
471 .tx_queue_start = i40e_dev_tx_queue_start,
472 .tx_queue_stop = i40e_dev_tx_queue_stop,
473 .rx_queue_setup = i40e_dev_rx_queue_setup,
474 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
475 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
476 .rx_queue_release = i40e_dev_rx_queue_release,
477 .tx_queue_setup = i40e_dev_tx_queue_setup,
478 .tx_queue_release = i40e_dev_tx_queue_release,
479 .dev_led_on = i40e_dev_led_on,
480 .dev_led_off = i40e_dev_led_off,
481 .flow_ctrl_get = i40e_flow_ctrl_get,
482 .flow_ctrl_set = i40e_flow_ctrl_set,
483 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
484 .mac_addr_add = i40e_macaddr_add,
485 .mac_addr_remove = i40e_macaddr_remove,
486 .reta_update = i40e_dev_rss_reta_update,
487 .reta_query = i40e_dev_rss_reta_query,
488 .rss_hash_update = i40e_dev_rss_hash_update,
489 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
490 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
491 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
492 .filter_ctrl = i40e_dev_filter_ctrl,
493 .rxq_info_get = i40e_rxq_info_get,
494 .txq_info_get = i40e_txq_info_get,
495 .rx_burst_mode_get = i40e_rx_burst_mode_get,
496 .tx_burst_mode_get = i40e_tx_burst_mode_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
515 .tx_done_cleanup = i40e_tx_done_cleanup,
518 /* store statistics names and its offset in stats structure */
519 struct rte_i40e_xstats_name_off {
520 char name[RTE_ETH_XSTATS_NAME_SIZE];
524 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
525 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
526 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
527 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
528 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
529 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
530 rx_unknown_protocol)},
531 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
532 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
533 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
534 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
537 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
538 sizeof(rte_i40e_stats_strings[0]))
540 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
541 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
542 tx_dropped_link_down)},
543 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
544 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
546 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
547 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
549 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
551 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
553 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
554 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
555 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
556 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
557 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
558 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
572 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
575 mac_short_packet_dropped)},
576 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
578 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
579 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
580 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
592 {"rx_flow_director_atr_match_packets",
593 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
594 {"rx_flow_director_sb_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
596 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
598 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
602 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
606 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
607 sizeof(rte_i40e_hw_port_strings[0]))
609 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
610 {"xon_packets", offsetof(struct i40e_hw_port_stats,
612 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
616 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
617 sizeof(rte_i40e_rxq_prio_strings[0]))
619 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
620 {"xon_packets", offsetof(struct i40e_hw_port_stats,
622 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
624 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
625 priority_xon_2_xoff)},
628 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
629 sizeof(rte_i40e_txq_prio_strings[0]))
632 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
633 struct rte_pci_device *pci_dev)
635 char name[RTE_ETH_NAME_MAX_LEN];
636 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
639 if (pci_dev->device.devargs) {
640 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
646 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
647 sizeof(struct i40e_adapter),
648 eth_dev_pci_specific_init, pci_dev,
649 eth_i40e_dev_init, NULL);
651 if (retval || eth_da.nb_representor_ports < 1)
654 /* probe VF representor ports */
655 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
656 pci_dev->device.name);
658 if (pf_ethdev == NULL)
661 for (i = 0; i < eth_da.nb_representor_ports; i++) {
662 struct i40e_vf_representor representor = {
663 .vf_id = eth_da.representor_ports[i],
664 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
665 pf_ethdev->data->dev_private)->switch_domain_id,
666 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
667 pf_ethdev->data->dev_private)
670 /* representor port net_bdf_port */
671 snprintf(name, sizeof(name), "net_%s_representor_%d",
672 pci_dev->device.name, eth_da.representor_ports[i]);
674 retval = rte_eth_dev_create(&pci_dev->device, name,
675 sizeof(struct i40e_vf_representor), NULL, NULL,
676 i40e_vf_representor_init, &representor);
679 PMD_DRV_LOG(ERR, "failed to create i40e vf "
680 "representor %s.", name);
686 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
688 struct rte_eth_dev *ethdev;
690 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_pci_generic_remove(pci_dev,
696 i40e_vf_representor_uninit);
698 return rte_eth_dev_pci_generic_remove(pci_dev,
699 eth_i40e_dev_uninit);
702 static struct rte_pci_driver rte_i40e_pmd = {
703 .id_table = pci_id_i40e_map,
704 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
705 .probe = eth_i40e_pci_probe,
706 .remove = eth_i40e_pci_remove,
710 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
713 uint32_t ori_reg_val;
714 struct rte_eth_dev *dev;
716 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
717 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
718 i40e_write_rx_ctl(hw, reg_addr, reg_val);
719 if (ori_reg_val != reg_val)
721 "i40e device %s changed global register [0x%08x]."
722 " original: 0x%08x, new: 0x%08x",
723 dev->device->name, reg_addr, ori_reg_val, reg_val);
726 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
727 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
728 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
730 #ifndef I40E_GLQF_ORT
731 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
733 #ifndef I40E_GLQF_PIT
734 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
736 #ifndef I40E_GLQF_L3_MAP
737 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
740 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
743 * Initialize registers for parsing packet type of QinQ
744 * This should be removed from code once proper
745 * configuration API is added to avoid configuration conflicts
746 * between ports of the same device.
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
749 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
752 static inline void i40e_config_automask(struct i40e_pf *pf)
754 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
757 /* INTENA flag is not auto-cleared for interrupt */
758 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
759 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
760 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
762 /* If support multi-driver, PF will use INT0. */
763 if (!pf->support_multi_driver)
764 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
766 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
769 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
772 * Add a ethertype filter to drop all flow control frames transmitted
776 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
778 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
779 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
781 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
784 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
785 I40E_FLOW_CONTROL_ETHERTYPE, flags,
786 pf->main_vsi_seid, 0,
790 "Failed to add filter to drop flow control frames from VSIs.");
794 floating_veb_list_handler(__rte_unused const char *key,
795 const char *floating_veb_value,
799 unsigned int count = 0;
802 bool *vf_floating_veb = opaque;
804 while (isblank(*floating_veb_value))
805 floating_veb_value++;
807 /* Reset floating VEB configuration for VFs */
808 for (idx = 0; idx < I40E_MAX_VF; idx++)
809 vf_floating_veb[idx] = false;
813 while (isblank(*floating_veb_value))
814 floating_veb_value++;
815 if (*floating_veb_value == '\0')
818 idx = strtoul(floating_veb_value, &end, 10);
819 if (errno || end == NULL)
821 while (isblank(*end))
825 } else if ((*end == ';') || (*end == '\0')) {
827 if (min == I40E_MAX_VF)
829 if (max >= I40E_MAX_VF)
830 max = I40E_MAX_VF - 1;
831 for (idx = min; idx <= max; idx++) {
832 vf_floating_veb[idx] = true;
839 floating_veb_value = end + 1;
840 } while (*end != '\0');
849 config_vf_floating_veb(struct rte_devargs *devargs,
850 uint16_t floating_veb,
851 bool *vf_floating_veb)
853 struct rte_kvargs *kvlist;
855 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
859 /* All the VFs attach to the floating VEB by default
860 * when the floating VEB is enabled.
862 for (i = 0; i < I40E_MAX_VF; i++)
863 vf_floating_veb[i] = true;
868 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
872 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
873 rte_kvargs_free(kvlist);
876 /* When the floating_veb_list parameter exists, all the VFs
877 * will attach to the legacy VEB firstly, then configure VFs
878 * to the floating VEB according to the floating_veb_list.
880 if (rte_kvargs_process(kvlist, floating_veb_list,
881 floating_veb_list_handler,
882 vf_floating_veb) < 0) {
883 rte_kvargs_free(kvlist);
886 rte_kvargs_free(kvlist);
890 i40e_check_floating_handler(__rte_unused const char *key,
892 __rte_unused void *opaque)
894 if (strcmp(value, "1"))
901 is_floating_veb_supported(struct rte_devargs *devargs)
903 struct rte_kvargs *kvlist;
904 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
909 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
913 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
914 rte_kvargs_free(kvlist);
917 /* Floating VEB is enabled when there's key-value:
918 * enable_floating_veb=1
920 if (rte_kvargs_process(kvlist, floating_veb_key,
921 i40e_check_floating_handler, NULL) < 0) {
922 rte_kvargs_free(kvlist);
925 rte_kvargs_free(kvlist);
931 config_floating_veb(struct rte_eth_dev *dev)
933 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
934 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
937 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
939 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
941 is_floating_veb_supported(pci_dev->device.devargs);
942 config_vf_floating_veb(pci_dev->device.devargs,
944 pf->floating_veb_list);
946 pf->floating_veb = false;
950 #define I40E_L2_TAGS_S_TAG_SHIFT 1
951 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
954 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
956 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
957 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
958 char ethertype_hash_name[RTE_HASH_NAMESIZE];
961 struct rte_hash_parameters ethertype_hash_params = {
962 .name = ethertype_hash_name,
963 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
964 .key_len = sizeof(struct i40e_ethertype_filter_input),
965 .hash_func = rte_hash_crc,
966 .hash_func_init_val = 0,
967 .socket_id = rte_socket_id(),
970 /* Initialize ethertype filter rule list and hash */
971 TAILQ_INIT(ðertype_rule->ethertype_list);
972 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
973 "ethertype_%s", dev->device->name);
974 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
975 if (!ethertype_rule->hash_table) {
976 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
979 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
980 sizeof(struct i40e_ethertype_filter *) *
981 I40E_MAX_ETHERTYPE_FILTER_NUM,
983 if (!ethertype_rule->hash_map) {
985 "Failed to allocate memory for ethertype hash map!");
987 goto err_ethertype_hash_map_alloc;
992 err_ethertype_hash_map_alloc:
993 rte_hash_free(ethertype_rule->hash_table);
999 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1003 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1006 struct rte_hash_parameters tunnel_hash_params = {
1007 .name = tunnel_hash_name,
1008 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1009 .key_len = sizeof(struct i40e_tunnel_filter_input),
1010 .hash_func = rte_hash_crc,
1011 .hash_func_init_val = 0,
1012 .socket_id = rte_socket_id(),
1015 /* Initialize tunnel filter rule list and hash */
1016 TAILQ_INIT(&tunnel_rule->tunnel_list);
1017 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1018 "tunnel_%s", dev->device->name);
1019 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1020 if (!tunnel_rule->hash_table) {
1021 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1024 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1025 sizeof(struct i40e_tunnel_filter *) *
1026 I40E_MAX_TUNNEL_FILTER_NUM,
1028 if (!tunnel_rule->hash_map) {
1030 "Failed to allocate memory for tunnel hash map!");
1032 goto err_tunnel_hash_map_alloc;
1037 err_tunnel_hash_map_alloc:
1038 rte_hash_free(tunnel_rule->hash_table);
1044 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1048 struct i40e_fdir_info *fdir_info = &pf->fdir;
1049 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1051 uint32_t best = hw->func_caps.fd_filters_best_effort;
1052 struct rte_bitmap *bmp = NULL;
1058 struct rte_hash_parameters fdir_hash_params = {
1059 .name = fdir_hash_name,
1060 .entries = I40E_MAX_FDIR_FILTER_NUM,
1061 .key_len = sizeof(struct i40e_fdir_input),
1062 .hash_func = rte_hash_crc,
1063 .hash_func_init_val = 0,
1064 .socket_id = rte_socket_id(),
1067 /* Initialize flow director filter rule list and hash */
1068 TAILQ_INIT(&fdir_info->fdir_list);
1069 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1070 "fdir_%s", dev->device->name);
1071 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1072 if (!fdir_info->hash_table) {
1073 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1077 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078 sizeof(struct i40e_fdir_filter *) *
1079 I40E_MAX_FDIR_FILTER_NUM,
1081 if (!fdir_info->hash_map) {
1083 "Failed to allocate memory for fdir hash map!");
1085 goto err_fdir_hash_map_alloc;
1088 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1089 sizeof(struct i40e_fdir_filter) *
1090 I40E_MAX_FDIR_FILTER_NUM,
1093 if (!fdir_info->fdir_filter_array) {
1095 "Failed to allocate memory for fdir filter array!");
1097 goto err_fdir_filter_array_alloc;
1100 fdir_info->fdir_space_size = alloc + best;
1101 fdir_info->fdir_actual_cnt = 0;
1102 fdir_info->fdir_guarantee_total_space = alloc;
1103 fdir_info->fdir_guarantee_free_space =
1104 fdir_info->fdir_guarantee_total_space;
1106 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1108 fdir_info->fdir_flow_pool.pool =
1109 rte_zmalloc("i40e_fdir_entry",
1110 sizeof(struct i40e_fdir_entry) *
1111 fdir_info->fdir_space_size,
1114 if (!fdir_info->fdir_flow_pool.pool) {
1116 "Failed to allocate memory for bitmap flow!");
1118 goto err_fdir_bitmap_flow_alloc;
1121 for (i = 0; i < fdir_info->fdir_space_size; i++)
1122 fdir_info->fdir_flow_pool.pool[i].idx = i;
1125 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1126 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1129 "Failed to allocate memory for fdir bitmap!");
1131 goto err_fdir_mem_alloc;
1133 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1136 "Failed to initialization fdir bitmap!");
1138 goto err_fdir_bmp_alloc;
1140 for (i = 0; i < fdir_info->fdir_space_size; i++)
1141 rte_bitmap_set(bmp, i);
1143 fdir_info->fdir_flow_pool.bitmap = bmp;
1150 rte_free(fdir_info->fdir_flow_pool.pool);
1151 err_fdir_bitmap_flow_alloc:
1152 rte_free(fdir_info->fdir_filter_array);
1153 err_fdir_filter_array_alloc:
1154 rte_free(fdir_info->hash_map);
1155 err_fdir_hash_map_alloc:
1156 rte_hash_free(fdir_info->hash_table);
1162 i40e_init_customized_info(struct i40e_pf *pf)
1166 /* Initialize customized pctype */
1167 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1168 pf->customized_pctype[i].index = i;
1169 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1170 pf->customized_pctype[i].valid = false;
1173 pf->gtp_support = false;
1174 pf->esp_support = false;
1178 i40e_init_filter_invalidation(struct i40e_pf *pf)
1180 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1181 struct i40e_fdir_info *fdir_info = &pf->fdir;
1182 uint32_t glqf_ctl_reg = 0;
1184 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1185 if (!pf->support_multi_driver) {
1186 fdir_info->fdir_invalprio = 1;
1187 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1188 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1189 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1191 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1192 fdir_info->fdir_invalprio = 1;
1193 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1195 fdir_info->fdir_invalprio = 0;
1196 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1202 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1204 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206 struct i40e_queue_regions *info = &pf->queue_region;
1209 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1210 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1212 memset(info, 0, sizeof(struct i40e_queue_regions));
1216 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1221 unsigned long support_multi_driver;
1224 pf = (struct i40e_pf *)opaque;
1227 support_multi_driver = strtoul(value, &end, 10);
1228 if (errno != 0 || end == value || *end != 0) {
1229 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1233 if (support_multi_driver == 1 || support_multi_driver == 0)
1234 pf->support_multi_driver = (bool)support_multi_driver;
1236 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1237 "enable global configuration by default."
1238 ETH_I40E_SUPPORT_MULTI_DRIVER);
1243 i40e_support_multi_driver(struct rte_eth_dev *dev)
1245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1246 struct rte_kvargs *kvlist;
1249 /* Enable global configuration by default */
1250 pf->support_multi_driver = false;
1252 if (!dev->device->devargs)
1255 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1259 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1260 if (!kvargs_count) {
1261 rte_kvargs_free(kvlist);
1265 if (kvargs_count > 1)
1266 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1267 "the first invalid or last valid one is used !",
1268 ETH_I40E_SUPPORT_MULTI_DRIVER);
1270 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1271 i40e_parse_multi_drv_handler, pf) < 0) {
1272 rte_kvargs_free(kvlist);
1276 rte_kvargs_free(kvlist);
1281 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1282 uint32_t reg_addr, uint64_t reg_val,
1283 struct i40e_asq_cmd_details *cmd_details)
1285 uint64_t ori_reg_val;
1286 struct rte_eth_dev *dev;
1289 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1290 if (ret != I40E_SUCCESS) {
1292 "Fail to debug read from 0x%08x",
1296 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1298 if (ori_reg_val != reg_val)
1299 PMD_DRV_LOG(WARNING,
1300 "i40e device %s changed global register [0x%08x]."
1301 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1302 dev->device->name, reg_addr, ori_reg_val, reg_val);
1304 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1308 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1312 struct i40e_adapter *ad = opaque;
1315 use_latest_vec = atoi(value);
1317 if (use_latest_vec != 0 && use_latest_vec != 1)
1318 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1320 ad->use_latest_vec = (uint8_t)use_latest_vec;
1326 i40e_use_latest_vec(struct rte_eth_dev *dev)
1328 struct i40e_adapter *ad =
1329 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1330 struct rte_kvargs *kvlist;
1333 ad->use_latest_vec = false;
1335 if (!dev->device->devargs)
1338 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1342 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1343 if (!kvargs_count) {
1344 rte_kvargs_free(kvlist);
1348 if (kvargs_count > 1)
1349 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1350 "the first invalid or last valid one is used !",
1351 ETH_I40E_USE_LATEST_VEC);
1353 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1354 i40e_parse_latest_vec_handler, ad) < 0) {
1355 rte_kvargs_free(kvlist);
1359 rte_kvargs_free(kvlist);
1364 read_vf_msg_config(__rte_unused const char *key,
1368 struct i40e_vf_msg_cfg *cfg = opaque;
1370 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1371 &cfg->ignore_second) != 3) {
1372 memset(cfg, 0, sizeof(*cfg));
1373 PMD_DRV_LOG(ERR, "format error! example: "
1374 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1379 * If the message validation function been enabled, the 'period'
1380 * and 'ignore_second' must greater than 0.
1382 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1383 memset(cfg, 0, sizeof(*cfg));
1384 PMD_DRV_LOG(ERR, "%s error! the second and third"
1385 " number must be greater than 0!",
1386 ETH_I40E_VF_MSG_CFG);
1394 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1395 struct i40e_vf_msg_cfg *msg_cfg)
1397 struct rte_kvargs *kvlist;
1401 memset(msg_cfg, 0, sizeof(*msg_cfg));
1403 if (!dev->device->devargs)
1406 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1410 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1414 if (kvargs_count > 1) {
1415 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1416 ETH_I40E_VF_MSG_CFG);
1421 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1422 read_vf_msg_config, msg_cfg) < 0)
1426 rte_kvargs_free(kvlist);
1430 #define I40E_ALARM_INTERVAL 50000 /* us */
1433 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1435 struct rte_pci_device *pci_dev;
1436 struct rte_intr_handle *intr_handle;
1437 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439 struct i40e_vsi *vsi;
1442 uint8_t aq_fail = 0;
1444 PMD_INIT_FUNC_TRACE();
1446 dev->dev_ops = &i40e_eth_dev_ops;
1447 dev->rx_queue_count = i40e_dev_rx_queue_count;
1448 dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1449 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1450 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1451 dev->rx_pkt_burst = i40e_recv_pkts;
1452 dev->tx_pkt_burst = i40e_xmit_pkts;
1453 dev->tx_pkt_prepare = i40e_prep_pkts;
1455 /* for secondary processes, we don't initialise any further as primary
1456 * has already done this work. Only check we don't need a different
1458 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459 i40e_set_rx_function(dev);
1460 i40e_set_tx_function(dev);
1463 i40e_set_default_ptype_table(dev);
1464 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465 intr_handle = &pci_dev->intr_handle;
1467 rte_eth_copy_pci_info(dev, pci_dev);
1469 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1470 pf->adapter->eth_dev = dev;
1471 pf->dev_data = dev->data;
1473 hw->back = I40E_PF_TO_ADAPTER(pf);
1474 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1477 "Hardware is not available, as address is NULL");
1481 hw->vendor_id = pci_dev->id.vendor_id;
1482 hw->device_id = pci_dev->id.device_id;
1483 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1484 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1485 hw->bus.device = pci_dev->addr.devid;
1486 hw->bus.func = pci_dev->addr.function;
1487 hw->adapter_stopped = 0;
1488 hw->adapter_closed = 0;
1490 /* Init switch device pointer */
1491 hw->switch_dev = NULL;
1494 * Switch Tag value should not be identical to either the First Tag
1495 * or Second Tag values. So set something other than common Ethertype
1496 * for internal switching.
1498 hw->switch_tag = 0xffff;
1500 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1501 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1502 PMD_INIT_LOG(ERR, "\nERROR: "
1503 "Firmware recovery mode detected. Limiting functionality.\n"
1504 "Refer to the Intel(R) Ethernet Adapters and Devices "
1505 "User Guide for details on firmware recovery mode.");
1509 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1510 /* Check if need to support multi-driver */
1511 i40e_support_multi_driver(dev);
1512 /* Check if users want the latest supported vec path */
1513 i40e_use_latest_vec(dev);
1515 /* Make sure all is clean before doing PF reset */
1518 /* Reset here to make sure all is clean for each PF */
1519 ret = i40e_pf_reset(hw);
1521 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1525 /* Initialize the shared code (base driver) */
1526 ret = i40e_init_shared_code(hw);
1528 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1532 /* Initialize the parameters for adminq */
1533 i40e_init_adminq_parameter(hw);
1534 ret = i40e_init_adminq(hw);
1535 if (ret != I40E_SUCCESS) {
1536 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1539 /* Firmware of SFP x722 does not support adminq option */
1540 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1541 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1543 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1544 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1545 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1546 ((hw->nvm.version >> 12) & 0xf),
1547 ((hw->nvm.version >> 4) & 0xff),
1548 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1550 /* Initialize the hardware */
1553 i40e_config_automask(pf);
1555 i40e_set_default_pctype_table(dev);
1558 * To work around the NVM issue, initialize registers
1559 * for packet type of QinQ by software.
1560 * It should be removed once issues are fixed in NVM.
1562 if (!pf->support_multi_driver)
1563 i40e_GLQF_reg_init(hw);
1565 /* Initialize the input set for filters (hash and fd) to default value */
1566 i40e_filter_input_set_init(pf);
1568 /* initialise the L3_MAP register */
1569 if (!pf->support_multi_driver) {
1570 ret = i40e_aq_debug_write_global_register(hw,
1571 I40E_GLQF_L3_MAP(40),
1574 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1577 "Global register 0x%08x is changed with 0x28",
1578 I40E_GLQF_L3_MAP(40));
1581 /* Need the special FW version to support floating VEB */
1582 config_floating_veb(dev);
1583 /* Clear PXE mode */
1584 i40e_clear_pxe_mode(hw);
1585 i40e_dev_sync_phy_type(hw);
1588 * On X710, performance number is far from the expectation on recent
1589 * firmware versions. The fix for this issue may not be integrated in
1590 * the following firmware version. So the workaround in software driver
1591 * is needed. It needs to modify the initial values of 3 internal only
1592 * registers. Note that the workaround can be removed when it is fixed
1593 * in firmware in the future.
1595 i40e_configure_registers(hw);
1597 /* Get hw capabilities */
1598 ret = i40e_get_cap(hw);
1599 if (ret != I40E_SUCCESS) {
1600 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1601 goto err_get_capabilities;
1604 /* Initialize parameters for PF */
1605 ret = i40e_pf_parameter_init(dev);
1607 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1608 goto err_parameter_init;
1611 /* Initialize the queue management */
1612 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1614 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1615 goto err_qp_pool_init;
1617 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1618 hw->func_caps.num_msix_vectors - 1);
1620 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1621 goto err_msix_pool_init;
1624 /* Initialize lan hmc */
1625 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1626 hw->func_caps.num_rx_qp, 0, 0);
1627 if (ret != I40E_SUCCESS) {
1628 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1629 goto err_init_lan_hmc;
1632 /* Configure lan hmc */
1633 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1634 if (ret != I40E_SUCCESS) {
1635 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1636 goto err_configure_lan_hmc;
1639 /* Get and check the mac address */
1640 i40e_get_mac_addr(hw, hw->mac.addr);
1641 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1642 PMD_INIT_LOG(ERR, "mac address is not valid");
1644 goto err_get_mac_addr;
1646 /* Copy the permanent MAC address */
1647 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1648 (struct rte_ether_addr *)hw->mac.perm_addr);
1650 /* Disable flow control */
1651 hw->fc.requested_mode = I40E_FC_NONE;
1652 i40e_set_fc(hw, &aq_fail, TRUE);
1654 /* Set the global registers with default ether type value */
1655 if (!pf->support_multi_driver) {
1656 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1657 RTE_ETHER_TYPE_VLAN);
1658 if (ret != I40E_SUCCESS) {
1660 "Failed to set the default outer "
1662 goto err_setup_pf_switch;
1666 /* PF setup, which includes VSI setup */
1667 ret = i40e_pf_setup(pf);
1669 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1670 goto err_setup_pf_switch;
1675 /* Disable double vlan by default */
1676 i40e_vsi_config_double_vlan(vsi, FALSE);
1678 /* Disable S-TAG identification when floating_veb is disabled */
1679 if (!pf->floating_veb) {
1680 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1681 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1682 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1683 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1687 if (!vsi->max_macaddrs)
1688 len = RTE_ETHER_ADDR_LEN;
1690 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1692 /* Should be after VSI initialized */
1693 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1694 if (!dev->data->mac_addrs) {
1696 "Failed to allocated memory for storing mac address");
1699 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1700 &dev->data->mac_addrs[0]);
1702 /* Pass the information to the rte_eth_dev_close() that it should also
1703 * release the private port resources.
1705 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1707 /* Init dcb to sw mode by default */
1708 ret = i40e_dcb_init_configure(dev, TRUE);
1709 if (ret != I40E_SUCCESS) {
1710 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1711 pf->flags &= ~I40E_FLAG_DCB;
1713 /* Update HW struct after DCB configuration */
1716 /* initialize pf host driver to setup SRIOV resource if applicable */
1717 i40e_pf_host_init(dev);
1719 /* register callback func to eal lib */
1720 rte_intr_callback_register(intr_handle,
1721 i40e_dev_interrupt_handler, dev);
1723 /* configure and enable device interrupt */
1724 i40e_pf_config_irq0(hw, TRUE);
1725 i40e_pf_enable_irq0(hw);
1727 /* enable uio intr after callback register */
1728 rte_intr_enable(intr_handle);
1730 /* By default disable flexible payload in global configuration */
1731 if (!pf->support_multi_driver)
1732 i40e_flex_payload_reg_set_default(hw);
1735 * Add an ethertype filter to drop all flow control frames transmitted
1736 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1739 i40e_add_tx_flow_control_drop_filter(pf);
1741 /* Set the max frame size to 0x2600 by default,
1742 * in case other drivers changed the default value.
1744 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1746 /* initialize mirror rule list */
1747 TAILQ_INIT(&pf->mirror_list);
1749 /* initialize RSS rule list */
1750 TAILQ_INIT(&pf->rss_config_list);
1752 /* initialize Traffic Manager configuration */
1753 i40e_tm_conf_init(dev);
1755 /* Initialize customized information */
1756 i40e_init_customized_info(pf);
1758 /* Initialize the filter invalidation configuration */
1759 i40e_init_filter_invalidation(pf);
1761 ret = i40e_init_ethtype_filter_list(dev);
1763 goto err_init_ethtype_filter_list;
1764 ret = i40e_init_tunnel_filter_list(dev);
1766 goto err_init_tunnel_filter_list;
1767 ret = i40e_init_fdir_filter_list(dev);
1769 goto err_init_fdir_filter_list;
1771 /* initialize queue region configuration */
1772 i40e_init_queue_region_conf(dev);
1774 /* initialize RSS configuration from rte_flow */
1775 memset(&pf->rss_info, 0,
1776 sizeof(struct i40e_rte_flow_rss_conf));
1778 /* reset all stats of the device, including pf and main vsi */
1779 i40e_dev_stats_reset(dev);
1783 err_init_fdir_filter_list:
1784 rte_free(pf->tunnel.hash_table);
1785 rte_free(pf->tunnel.hash_map);
1786 err_init_tunnel_filter_list:
1787 rte_free(pf->ethertype.hash_table);
1788 rte_free(pf->ethertype.hash_map);
1789 err_init_ethtype_filter_list:
1790 rte_free(dev->data->mac_addrs);
1791 dev->data->mac_addrs = NULL;
1793 i40e_vsi_release(pf->main_vsi);
1794 err_setup_pf_switch:
1796 err_configure_lan_hmc:
1797 (void)i40e_shutdown_lan_hmc(hw);
1799 i40e_res_pool_destroy(&pf->msix_pool);
1801 i40e_res_pool_destroy(&pf->qp_pool);
1804 err_get_capabilities:
1805 (void)i40e_shutdown_adminq(hw);
1811 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1813 struct i40e_ethertype_filter *p_ethertype;
1814 struct i40e_ethertype_rule *ethertype_rule;
1816 ethertype_rule = &pf->ethertype;
1817 /* Remove all ethertype filter rules and hash */
1818 if (ethertype_rule->hash_map)
1819 rte_free(ethertype_rule->hash_map);
1820 if (ethertype_rule->hash_table)
1821 rte_hash_free(ethertype_rule->hash_table);
1823 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1824 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1825 p_ethertype, rules);
1826 rte_free(p_ethertype);
1831 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1833 struct i40e_tunnel_filter *p_tunnel;
1834 struct i40e_tunnel_rule *tunnel_rule;
1836 tunnel_rule = &pf->tunnel;
1837 /* Remove all tunnel director rules and hash */
1838 if (tunnel_rule->hash_map)
1839 rte_free(tunnel_rule->hash_map);
1840 if (tunnel_rule->hash_table)
1841 rte_hash_free(tunnel_rule->hash_table);
1843 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1844 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1850 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1852 struct i40e_fdir_filter *p_fdir;
1853 struct i40e_fdir_info *fdir_info;
1855 fdir_info = &pf->fdir;
1857 /* Remove all flow director rules */
1858 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1859 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1863 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1865 struct i40e_fdir_info *fdir_info;
1867 fdir_info = &pf->fdir;
1869 /* flow director memory cleanup */
1870 if (fdir_info->hash_map)
1871 rte_free(fdir_info->hash_map);
1872 if (fdir_info->hash_table)
1873 rte_hash_free(fdir_info->hash_table);
1874 if (fdir_info->fdir_flow_pool.bitmap)
1875 rte_free(fdir_info->fdir_flow_pool.bitmap);
1876 if (fdir_info->fdir_flow_pool.pool)
1877 rte_free(fdir_info->fdir_flow_pool.pool);
1878 if (fdir_info->fdir_filter_array)
1879 rte_free(fdir_info->fdir_filter_array);
1882 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1885 * Disable by default flexible payload
1886 * for corresponding L2/L3/L4 layers.
1888 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1889 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1890 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1894 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1898 PMD_INIT_FUNC_TRACE();
1900 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1903 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905 if (hw->adapter_closed == 0)
1906 i40e_dev_close(dev);
1912 i40e_dev_configure(struct rte_eth_dev *dev)
1914 struct i40e_adapter *ad =
1915 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1916 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1921 ret = i40e_dev_sync_phy_type(hw);
1925 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1926 * bulk allocation or vector Rx preconditions we will reset it.
1928 ad->rx_bulk_alloc_allowed = true;
1929 ad->rx_vec_allowed = true;
1930 ad->tx_simple_allowed = true;
1931 ad->tx_vec_allowed = true;
1933 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1934 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1936 /* Only legacy filter API needs the following fdir config. So when the
1937 * legacy filter API is deprecated, the following codes should also be
1940 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1941 ret = i40e_fdir_setup(pf);
1942 if (ret != I40E_SUCCESS) {
1943 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1946 ret = i40e_fdir_configure(dev);
1948 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1952 i40e_fdir_teardown(pf);
1954 ret = i40e_dev_init_vlan(dev);
1959 * General PMD driver call sequence are NIC init, configure,
1960 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961 * will try to lookup the VSI that specific queue belongs to if VMDQ
1962 * applicable. So, VMDQ setting has to be done before
1963 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1964 * For RSS setting, it will try to calculate actual configured RX queue
1965 * number, which will be available after rx_queue_setup(). dev_start()
1966 * function is good to place RSS setup.
1968 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969 ret = i40e_vmdq_setup(dev);
1974 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975 ret = i40e_dcb_setup(dev);
1977 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1982 TAILQ_INIT(&pf->flow_list);
1987 /* need to release vmdq resource if exists */
1988 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989 i40e_vsi_release(pf->vmdq[i].vsi);
1990 pf->vmdq[i].vsi = NULL;
1995 /* Need to release fdir resource if exists.
1996 * Only legacy filter API needs the following fdir config. So when the
1997 * legacy filter API is deprecated, the following code should also be
2000 i40e_fdir_teardown(pf);
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2007 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011 uint16_t msix_vect = vsi->msix_intr;
2014 for (i = 0; i < vsi->nb_qps; i++) {
2015 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2020 if (vsi->type != I40E_VSI_SRIOV) {
2021 if (!rte_intr_allow_others(intr_handle)) {
2022 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2025 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2028 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2031 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2036 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037 vsi->user_param + (msix_vect - 1);
2039 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2042 I40E_WRITE_FLUSH(hw);
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047 int base_queue, int nb_queue,
2052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2055 /* Bind all RX queues to allocated MSIX interrupt */
2056 for (i = 0; i < nb_queue; i++) {
2057 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059 ((base_queue + i + 1) <<
2060 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2064 if (i == nb_queue - 1)
2065 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2069 /* Write first RX queue to Link list register as the head element */
2070 if (vsi->type != I40E_VSI_SRIOV) {
2072 i40e_calc_itr_interval(1, pf->support_multi_driver);
2074 if (msix_vect == I40E_MISC_VEC_ID) {
2075 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2077 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2079 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2081 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2084 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2086 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2088 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2090 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2097 if (msix_vect == I40E_MISC_VEC_ID) {
2099 I40E_VPINT_LNKLST0(vsi->user_param),
2101 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2103 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2105 /* num_msix_vectors_vf needs to minus irq0 */
2106 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107 vsi->user_param + (msix_vect - 1);
2109 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2111 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2113 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2117 I40E_WRITE_FLUSH(hw);
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2123 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127 uint16_t msix_vect = vsi->msix_intr;
2128 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129 uint16_t queue_idx = 0;
2133 for (i = 0; i < vsi->nb_qps; i++) {
2134 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2138 /* VF bind interrupt */
2139 if (vsi->type == I40E_VSI_SRIOV) {
2140 if (vsi->nb_msix == 0) {
2141 PMD_DRV_LOG(ERR, "No msix resource");
2144 __vsi_queues_bind_intr(vsi, msix_vect,
2145 vsi->base_queue, vsi->nb_qps,
2150 /* PF & VMDq bind interrupt */
2151 if (rte_intr_dp_is_en(intr_handle)) {
2152 if (vsi->type == I40E_VSI_MAIN) {
2155 } else if (vsi->type == I40E_VSI_VMDQ2) {
2156 struct i40e_vsi *main_vsi =
2157 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2158 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2163 for (i = 0; i < vsi->nb_used_qps; i++) {
2164 if (vsi->nb_msix == 0) {
2165 PMD_DRV_LOG(ERR, "No msix resource");
2167 } else if (nb_msix <= 1) {
2168 if (!rte_intr_allow_others(intr_handle))
2169 /* allow to share MISC_VEC_ID */
2170 msix_vect = I40E_MISC_VEC_ID;
2172 /* no enough msix_vect, map all to one */
2173 __vsi_queues_bind_intr(vsi, msix_vect,
2174 vsi->base_queue + i,
2175 vsi->nb_used_qps - i,
2177 for (; !!record && i < vsi->nb_used_qps; i++)
2178 intr_handle->intr_vec[queue_idx + i] =
2182 /* 1:1 queue/msix_vect mapping */
2183 __vsi_queues_bind_intr(vsi, msix_vect,
2184 vsi->base_queue + i, 1,
2187 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2197 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2199 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2200 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2204 uint16_t msix_intr, i;
2206 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2207 for (i = 0; i < vsi->nb_msix; i++) {
2208 msix_intr = vsi->msix_intr + i;
2209 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2210 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2211 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2212 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2215 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2216 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2217 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2218 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2220 I40E_WRITE_FLUSH(hw);
2224 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2226 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2227 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2229 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2230 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2231 uint16_t msix_intr, i;
2233 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2234 for (i = 0; i < vsi->nb_msix; i++) {
2235 msix_intr = vsi->msix_intr + i;
2236 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2237 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2240 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2241 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2243 I40E_WRITE_FLUSH(hw);
2246 static inline uint8_t
2247 i40e_parse_link_speeds(uint16_t link_speeds)
2249 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2251 if (link_speeds & ETH_LINK_SPEED_40G)
2252 link_speed |= I40E_LINK_SPEED_40GB;
2253 if (link_speeds & ETH_LINK_SPEED_25G)
2254 link_speed |= I40E_LINK_SPEED_25GB;
2255 if (link_speeds & ETH_LINK_SPEED_20G)
2256 link_speed |= I40E_LINK_SPEED_20GB;
2257 if (link_speeds & ETH_LINK_SPEED_10G)
2258 link_speed |= I40E_LINK_SPEED_10GB;
2259 if (link_speeds & ETH_LINK_SPEED_1G)
2260 link_speed |= I40E_LINK_SPEED_1GB;
2261 if (link_speeds & ETH_LINK_SPEED_100M)
2262 link_speed |= I40E_LINK_SPEED_100MB;
2268 i40e_phy_conf_link(struct i40e_hw *hw,
2270 uint8_t force_speed,
2273 enum i40e_status_code status;
2274 struct i40e_aq_get_phy_abilities_resp phy_ab;
2275 struct i40e_aq_set_phy_config phy_conf;
2276 enum i40e_aq_phy_type cnt;
2277 uint8_t avail_speed;
2278 uint32_t phy_type_mask = 0;
2280 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2281 I40E_AQ_PHY_FLAG_PAUSE_RX |
2282 I40E_AQ_PHY_FLAG_PAUSE_RX |
2283 I40E_AQ_PHY_FLAG_LOW_POWER;
2286 /* To get phy capabilities of available speeds. */
2287 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2290 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2294 avail_speed = phy_ab.link_speed;
2296 /* To get the current phy config. */
2297 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2300 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2305 /* If link needs to go up and it is in autoneg mode the speed is OK,
2306 * no need to set up again.
2308 if (is_up && phy_ab.phy_type != 0 &&
2309 abilities & I40E_AQ_PHY_AN_ENABLED &&
2310 phy_ab.link_speed != 0)
2311 return I40E_SUCCESS;
2313 memset(&phy_conf, 0, sizeof(phy_conf));
2315 /* bits 0-2 use the values from get_phy_abilities_resp */
2317 abilities |= phy_ab.abilities & mask;
2319 phy_conf.abilities = abilities;
2321 /* If link needs to go up, but the force speed is not supported,
2322 * Warn users and config the default available speeds.
2324 if (is_up && !(force_speed & avail_speed)) {
2325 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2326 phy_conf.link_speed = avail_speed;
2328 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2331 /* PHY type mask needs to include each type except PHY type extension */
2332 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2333 phy_type_mask |= 1 << cnt;
2335 /* use get_phy_abilities_resp value for the rest */
2336 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2337 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2338 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2339 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2340 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2341 phy_conf.eee_capability = phy_ab.eee_capability;
2342 phy_conf.eeer = phy_ab.eeer_val;
2343 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2345 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2346 phy_ab.abilities, phy_ab.link_speed);
2347 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2348 phy_conf.abilities, phy_conf.link_speed);
2350 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2354 return I40E_SUCCESS;
2358 i40e_apply_link_speed(struct rte_eth_dev *dev)
2361 uint8_t abilities = 0;
2362 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363 struct rte_eth_conf *conf = &dev->data->dev_conf;
2365 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2366 I40E_AQ_PHY_LINK_ENABLED;
2368 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2369 conf->link_speeds = ETH_LINK_SPEED_40G |
2370 ETH_LINK_SPEED_25G |
2371 ETH_LINK_SPEED_20G |
2372 ETH_LINK_SPEED_10G |
2374 ETH_LINK_SPEED_100M;
2376 abilities |= I40E_AQ_PHY_AN_ENABLED;
2378 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2380 speed = i40e_parse_link_speeds(conf->link_speeds);
2382 return i40e_phy_conf_link(hw, abilities, speed, true);
2386 i40e_dev_start(struct rte_eth_dev *dev)
2388 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390 struct i40e_vsi *main_vsi = pf->main_vsi;
2392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2393 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394 uint32_t intr_vector = 0;
2395 struct i40e_vsi *vsi;
2396 uint16_t nb_rxq, nb_txq;
2398 hw->adapter_stopped = 0;
2400 rte_intr_disable(intr_handle);
2402 if ((rte_intr_cap_multiple(intr_handle) ||
2403 !RTE_ETH_DEV_SRIOV(dev).active) &&
2404 dev->data->dev_conf.intr_conf.rxq != 0) {
2405 intr_vector = dev->data->nb_rx_queues;
2406 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2411 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2412 intr_handle->intr_vec =
2413 rte_zmalloc("intr_vec",
2414 dev->data->nb_rx_queues * sizeof(int),
2416 if (!intr_handle->intr_vec) {
2418 "Failed to allocate %d rx_queues intr_vec",
2419 dev->data->nb_rx_queues);
2424 /* Initialize VSI */
2425 ret = i40e_dev_rxtx_init(pf);
2426 if (ret != I40E_SUCCESS) {
2427 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2431 /* Map queues with MSIX interrupt */
2432 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2433 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2434 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2437 i40e_vsi_enable_queues_intr(main_vsi);
2439 /* Map VMDQ VSI queues with MSIX interrupt */
2440 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2441 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2442 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2443 I40E_ITR_INDEX_DEFAULT);
2446 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2449 /* Enable all queues which have been configured */
2450 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2451 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2456 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2457 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2462 /* Enable receiving broadcast packets */
2463 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2464 if (ret != I40E_SUCCESS)
2465 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2467 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2468 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2470 if (ret != I40E_SUCCESS)
2471 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2474 /* Enable the VLAN promiscuous mode. */
2476 for (i = 0; i < pf->vf_num; i++) {
2477 vsi = pf->vfs[i].vsi;
2478 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2483 /* Enable mac loopback mode */
2484 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2485 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2486 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2487 if (ret != I40E_SUCCESS) {
2488 PMD_DRV_LOG(ERR, "fail to set loopback link");
2493 /* Apply link configure */
2494 ret = i40e_apply_link_speed(dev);
2495 if (I40E_SUCCESS != ret) {
2496 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2500 if (!rte_intr_allow_others(intr_handle)) {
2501 rte_intr_callback_unregister(intr_handle,
2502 i40e_dev_interrupt_handler,
2504 /* configure and enable device interrupt */
2505 i40e_pf_config_irq0(hw, FALSE);
2506 i40e_pf_enable_irq0(hw);
2508 if (dev->data->dev_conf.intr_conf.lsc != 0)
2510 "lsc won't enable because of no intr multiplex");
2512 ret = i40e_aq_set_phy_int_mask(hw,
2513 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2514 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2515 I40E_AQ_EVENT_MEDIA_NA), NULL);
2516 if (ret != I40E_SUCCESS)
2517 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2519 /* Call get_link_info aq commond to enable/disable LSE */
2520 i40e_dev_link_update(dev, 0);
2523 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2524 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2525 i40e_dev_alarm_handler, dev);
2527 /* enable uio intr after callback register */
2528 rte_intr_enable(intr_handle);
2531 i40e_filter_restore(pf);
2533 if (pf->tm_conf.root && !pf->tm_conf.committed)
2534 PMD_DRV_LOG(WARNING,
2535 "please call hierarchy_commit() "
2536 "before starting the port");
2538 return I40E_SUCCESS;
2541 for (i = 0; i < nb_txq; i++)
2542 i40e_dev_tx_queue_stop(dev, i);
2544 for (i = 0; i < nb_rxq; i++)
2545 i40e_dev_rx_queue_stop(dev, i);
2551 i40e_dev_stop(struct rte_eth_dev *dev)
2553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555 struct i40e_vsi *main_vsi = pf->main_vsi;
2556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2557 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2560 if (hw->adapter_stopped == 1)
2563 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2564 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2565 rte_intr_enable(intr_handle);
2568 /* Disable all queues */
2569 for (i = 0; i < dev->data->nb_tx_queues; i++)
2570 i40e_dev_tx_queue_stop(dev, i);
2572 for (i = 0; i < dev->data->nb_rx_queues; i++)
2573 i40e_dev_rx_queue_stop(dev, i);
2575 /* un-map queues with interrupt registers */
2576 i40e_vsi_disable_queues_intr(main_vsi);
2577 i40e_vsi_queues_unbind_intr(main_vsi);
2579 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2580 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2581 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2584 /* Clear all queues and release memory */
2585 i40e_dev_clear_queues(dev);
2588 i40e_dev_set_link_down(dev);
2590 if (!rte_intr_allow_others(intr_handle))
2591 /* resume to the default handler */
2592 rte_intr_callback_register(intr_handle,
2593 i40e_dev_interrupt_handler,
2596 /* Clean datapath event and queue/vec mapping */
2597 rte_intr_efd_disable(intr_handle);
2598 if (intr_handle->intr_vec) {
2599 rte_free(intr_handle->intr_vec);
2600 intr_handle->intr_vec = NULL;
2603 /* reset hierarchy commit */
2604 pf->tm_conf.committed = false;
2606 hw->adapter_stopped = 1;
2608 pf->adapter->rss_reta_updated = 0;
2612 i40e_dev_close(struct rte_eth_dev *dev)
2614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2617 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618 struct i40e_mirror_rule *p_mirror;
2619 struct i40e_filter_control_settings settings;
2620 struct rte_flow *p_flow;
2624 uint8_t aq_fail = 0;
2627 PMD_INIT_FUNC_TRACE();
2629 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2631 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2636 /* Remove all mirror rules */
2637 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2638 ret = i40e_aq_del_mirror_rule(hw,
2639 pf->main_vsi->veb->seid,
2640 p_mirror->rule_type,
2642 p_mirror->num_entries,
2645 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2646 "status = %d, aq_err = %d.", ret,
2647 hw->aq.asq_last_status);
2649 /* remove mirror software resource anyway */
2650 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2652 pf->nb_mirror_rule--;
2655 i40e_dev_free_queues(dev);
2657 /* Disable interrupt */
2658 i40e_pf_disable_irq0(hw);
2659 rte_intr_disable(intr_handle);
2662 * Only legacy filter API needs the following fdir config. So when the
2663 * legacy filter API is deprecated, the following code should also be
2666 i40e_fdir_teardown(pf);
2668 /* shutdown and destroy the HMC */
2669 i40e_shutdown_lan_hmc(hw);
2671 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2672 i40e_vsi_release(pf->vmdq[i].vsi);
2673 pf->vmdq[i].vsi = NULL;
2678 /* release all the existing VSIs and VEBs */
2679 i40e_vsi_release(pf->main_vsi);
2681 /* shutdown the adminq */
2682 i40e_aq_queue_shutdown(hw, true);
2683 i40e_shutdown_adminq(hw);
2685 i40e_res_pool_destroy(&pf->qp_pool);
2686 i40e_res_pool_destroy(&pf->msix_pool);
2688 /* Disable flexible payload in global configuration */
2689 if (!pf->support_multi_driver)
2690 i40e_flex_payload_reg_set_default(hw);
2692 /* force a PF reset to clean anything leftover */
2693 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2694 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2695 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2696 I40E_WRITE_FLUSH(hw);
2698 dev->dev_ops = NULL;
2699 dev->rx_pkt_burst = NULL;
2700 dev->tx_pkt_burst = NULL;
2702 /* Clear PXE mode */
2703 i40e_clear_pxe_mode(hw);
2705 /* Unconfigure filter control */
2706 memset(&settings, 0, sizeof(settings));
2707 ret = i40e_set_filter_control(hw, &settings);
2709 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2712 /* Disable flow control */
2713 hw->fc.requested_mode = I40E_FC_NONE;
2714 i40e_set_fc(hw, &aq_fail, TRUE);
2716 /* uninitialize pf host driver */
2717 i40e_pf_host_uninit(dev);
2720 ret = rte_intr_callback_unregister(intr_handle,
2721 i40e_dev_interrupt_handler, dev);
2722 if (ret >= 0 || ret == -ENOENT) {
2724 } else if (ret != -EAGAIN) {
2726 "intr callback unregister failed: %d",
2729 i40e_msec_delay(500);
2730 } while (retries++ < 5);
2732 i40e_rm_ethtype_filter_list(pf);
2733 i40e_rm_tunnel_filter_list(pf);
2734 i40e_rm_fdir_filter_list(pf);
2736 /* Remove all flows */
2737 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2738 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2739 /* Do not free FDIR flows since they are static allocated */
2740 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2744 /* release the fdir static allocated memory */
2745 i40e_fdir_memory_cleanup(pf);
2747 /* Remove all Traffic Manager configuration */
2748 i40e_tm_conf_uninit(dev);
2750 hw->adapter_closed = 1;
2754 * Reset PF device only to re-initialize resources in PMD layer
2757 i40e_dev_reset(struct rte_eth_dev *dev)
2761 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2762 * its VF to make them align with it. The detailed notification
2763 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2764 * To avoid unexpected behavior in VF, currently reset of PF with
2765 * SR-IOV activation is not supported. It might be supported later.
2767 if (dev->data->sriov.active)
2770 ret = eth_i40e_dev_uninit(dev);
2774 ret = eth_i40e_dev_init(dev, NULL);
2780 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 struct i40e_vsi *vsi = pf->main_vsi;
2787 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2789 if (status != I40E_SUCCESS) {
2790 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2794 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2796 if (status != I40E_SUCCESS) {
2797 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2798 /* Rollback unicast promiscuous mode */
2799 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2808 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 struct i40e_vsi *vsi = pf->main_vsi;
2815 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2817 if (status != I40E_SUCCESS) {
2818 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2822 /* must remain in all_multicast mode */
2823 if (dev->data->all_multicast == 1)
2826 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2828 if (status != I40E_SUCCESS) {
2829 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2830 /* Rollback unicast promiscuous mode */
2831 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2840 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2842 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844 struct i40e_vsi *vsi = pf->main_vsi;
2847 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2848 if (ret != I40E_SUCCESS) {
2849 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2857 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2859 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 struct i40e_vsi *vsi = pf->main_vsi;
2864 if (dev->data->promiscuous == 1)
2865 return 0; /* must remain in all_multicast mode */
2867 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2868 vsi->seid, FALSE, NULL);
2869 if (ret != I40E_SUCCESS) {
2870 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2878 * Set device link up.
2881 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2883 /* re-apply link speed setting */
2884 return i40e_apply_link_speed(dev);
2888 * Set device link down.
2891 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2893 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2894 uint8_t abilities = 0;
2895 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2898 return i40e_phy_conf_link(hw, abilities, speed, false);
2901 static __rte_always_inline void
2902 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2904 /* Link status registers and values*/
2905 #define I40E_PRTMAC_LINKSTA 0x001E2420
2906 #define I40E_REG_LINK_UP 0x40000080
2907 #define I40E_PRTMAC_MACC 0x001E24E0
2908 #define I40E_REG_MACC_25GB 0x00020000
2909 #define I40E_REG_SPEED_MASK 0x38000000
2910 #define I40E_REG_SPEED_0 0x00000000
2911 #define I40E_REG_SPEED_1 0x08000000
2912 #define I40E_REG_SPEED_2 0x10000000
2913 #define I40E_REG_SPEED_3 0x18000000
2914 #define I40E_REG_SPEED_4 0x20000000
2915 uint32_t link_speed;
2918 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2919 link_speed = reg_val & I40E_REG_SPEED_MASK;
2920 reg_val &= I40E_REG_LINK_UP;
2921 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2923 if (unlikely(link->link_status == 0))
2926 /* Parse the link status */
2927 switch (link_speed) {
2928 case I40E_REG_SPEED_0:
2929 link->link_speed = ETH_SPEED_NUM_100M;
2931 case I40E_REG_SPEED_1:
2932 link->link_speed = ETH_SPEED_NUM_1G;
2934 case I40E_REG_SPEED_2:
2935 if (hw->mac.type == I40E_MAC_X722)
2936 link->link_speed = ETH_SPEED_NUM_2_5G;
2938 link->link_speed = ETH_SPEED_NUM_10G;
2940 case I40E_REG_SPEED_3:
2941 if (hw->mac.type == I40E_MAC_X722) {
2942 link->link_speed = ETH_SPEED_NUM_5G;
2944 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2946 if (reg_val & I40E_REG_MACC_25GB)
2947 link->link_speed = ETH_SPEED_NUM_25G;
2949 link->link_speed = ETH_SPEED_NUM_40G;
2952 case I40E_REG_SPEED_4:
2953 if (hw->mac.type == I40E_MAC_X722)
2954 link->link_speed = ETH_SPEED_NUM_10G;
2956 link->link_speed = ETH_SPEED_NUM_20G;
2959 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2964 static __rte_always_inline void
2965 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2966 bool enable_lse, int wait_to_complete)
2968 #define CHECK_INTERVAL 100 /* 100ms */
2969 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2970 uint32_t rep_cnt = MAX_REPEAT_TIME;
2971 struct i40e_link_status link_status;
2974 memset(&link_status, 0, sizeof(link_status));
2977 memset(&link_status, 0, sizeof(link_status));
2979 /* Get link status information from hardware */
2980 status = i40e_aq_get_link_info(hw, enable_lse,
2981 &link_status, NULL);
2982 if (unlikely(status != I40E_SUCCESS)) {
2983 link->link_speed = ETH_SPEED_NUM_NONE;
2984 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2985 PMD_DRV_LOG(ERR, "Failed to get link info");
2989 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2990 if (!wait_to_complete || link->link_status)
2993 rte_delay_ms(CHECK_INTERVAL);
2994 } while (--rep_cnt);
2996 /* Parse the link status */
2997 switch (link_status.link_speed) {
2998 case I40E_LINK_SPEED_100MB:
2999 link->link_speed = ETH_SPEED_NUM_100M;
3001 case I40E_LINK_SPEED_1GB:
3002 link->link_speed = ETH_SPEED_NUM_1G;
3004 case I40E_LINK_SPEED_10GB:
3005 link->link_speed = ETH_SPEED_NUM_10G;
3007 case I40E_LINK_SPEED_20GB:
3008 link->link_speed = ETH_SPEED_NUM_20G;
3010 case I40E_LINK_SPEED_25GB:
3011 link->link_speed = ETH_SPEED_NUM_25G;
3013 case I40E_LINK_SPEED_40GB:
3014 link->link_speed = ETH_SPEED_NUM_40G;
3017 if (link->link_status)
3018 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3020 link->link_speed = ETH_SPEED_NUM_NONE;
3026 i40e_dev_link_update(struct rte_eth_dev *dev,
3027 int wait_to_complete)
3029 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030 struct rte_eth_link link;
3031 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3034 memset(&link, 0, sizeof(link));
3036 /* i40e uses full duplex only */
3037 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3038 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3039 ETH_LINK_SPEED_FIXED);
3041 if (!wait_to_complete && !enable_lse)
3042 update_link_reg(hw, &link);
3044 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3047 rte_eth_linkstatus_get(hw->switch_dev, &link);
3049 ret = rte_eth_linkstatus_set(dev, &link);
3050 i40e_notify_all_vfs_link_status(dev);
3056 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3057 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3058 uint64_t *stat, uint64_t *prev_stat)
3060 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3061 /* enlarge the limitation when statistics counters overflowed */
3062 if (offset_loaded) {
3063 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3064 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3065 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3070 /* Get all the statistics of a VSI */
3072 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3074 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3075 struct i40e_eth_stats *nes = &vsi->eth_stats;
3076 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3077 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3079 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3080 vsi->offset_loaded, &oes->rx_bytes,
3081 &nes->rx_bytes, &vsi->prev_rx_bytes);
3082 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3083 vsi->offset_loaded, &oes->rx_unicast,
3085 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3086 vsi->offset_loaded, &oes->rx_multicast,
3087 &nes->rx_multicast);
3088 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3089 vsi->offset_loaded, &oes->rx_broadcast,
3090 &nes->rx_broadcast);
3091 /* exclude CRC bytes */
3092 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3093 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3095 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3096 &oes->rx_discards, &nes->rx_discards);
3097 /* GLV_REPC not supported */
3098 /* GLV_RMPC not supported */
3099 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3100 &oes->rx_unknown_protocol,
3101 &nes->rx_unknown_protocol);
3102 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3103 vsi->offset_loaded, &oes->tx_bytes,
3104 &nes->tx_bytes, &vsi->prev_tx_bytes);
3105 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3106 vsi->offset_loaded, &oes->tx_unicast,
3108 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3109 vsi->offset_loaded, &oes->tx_multicast,
3110 &nes->tx_multicast);
3111 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3112 vsi->offset_loaded, &oes->tx_broadcast,
3113 &nes->tx_broadcast);
3114 /* GLV_TDPC not supported */
3115 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3116 &oes->tx_errors, &nes->tx_errors);
3117 vsi->offset_loaded = true;
3119 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3121 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3122 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3123 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3124 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3125 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3126 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3127 nes->rx_unknown_protocol);
3128 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3129 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3130 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3131 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3132 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3133 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3134 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3139 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3142 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3143 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3145 /* Get rx/tx bytes of internal transfer packets */
3146 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3147 I40E_GLV_GORCL(hw->port),
3149 &pf->internal_stats_offset.rx_bytes,
3150 &pf->internal_stats.rx_bytes,
3151 &pf->internal_prev_rx_bytes);
3152 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3153 I40E_GLV_GOTCL(hw->port),
3155 &pf->internal_stats_offset.tx_bytes,
3156 &pf->internal_stats.tx_bytes,
3157 &pf->internal_prev_tx_bytes);
3158 /* Get total internal rx packet count */
3159 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3160 I40E_GLV_UPRCL(hw->port),
3162 &pf->internal_stats_offset.rx_unicast,
3163 &pf->internal_stats.rx_unicast);
3164 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3165 I40E_GLV_MPRCL(hw->port),
3167 &pf->internal_stats_offset.rx_multicast,
3168 &pf->internal_stats.rx_multicast);
3169 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3170 I40E_GLV_BPRCL(hw->port),
3172 &pf->internal_stats_offset.rx_broadcast,
3173 &pf->internal_stats.rx_broadcast);
3174 /* Get total internal tx packet count */
3175 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3176 I40E_GLV_UPTCL(hw->port),
3178 &pf->internal_stats_offset.tx_unicast,
3179 &pf->internal_stats.tx_unicast);
3180 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3181 I40E_GLV_MPTCL(hw->port),
3183 &pf->internal_stats_offset.tx_multicast,
3184 &pf->internal_stats.tx_multicast);
3185 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3186 I40E_GLV_BPTCL(hw->port),
3188 &pf->internal_stats_offset.tx_broadcast,
3189 &pf->internal_stats.tx_broadcast);
3191 /* exclude CRC size */
3192 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3193 pf->internal_stats.rx_multicast +
3194 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3196 /* Get statistics of struct i40e_eth_stats */
3197 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3198 I40E_GLPRT_GORCL(hw->port),
3199 pf->offset_loaded, &os->eth.rx_bytes,
3200 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3201 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3202 I40E_GLPRT_UPRCL(hw->port),
3203 pf->offset_loaded, &os->eth.rx_unicast,
3204 &ns->eth.rx_unicast);
3205 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3206 I40E_GLPRT_MPRCL(hw->port),
3207 pf->offset_loaded, &os->eth.rx_multicast,
3208 &ns->eth.rx_multicast);
3209 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3210 I40E_GLPRT_BPRCL(hw->port),
3211 pf->offset_loaded, &os->eth.rx_broadcast,
3212 &ns->eth.rx_broadcast);
3213 /* Workaround: CRC size should not be included in byte statistics,
3214 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3217 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3218 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3220 /* exclude internal rx bytes
3221 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3222 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3224 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3226 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3227 ns->eth.rx_bytes = 0;
3229 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3231 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3232 ns->eth.rx_unicast = 0;
3234 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3236 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3237 ns->eth.rx_multicast = 0;
3239 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3241 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3242 ns->eth.rx_broadcast = 0;
3244 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3246 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3247 pf->offset_loaded, &os->eth.rx_discards,
3248 &ns->eth.rx_discards);
3249 /* GLPRT_REPC not supported */
3250 /* GLPRT_RMPC not supported */
3251 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3253 &os->eth.rx_unknown_protocol,
3254 &ns->eth.rx_unknown_protocol);
3255 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3256 I40E_GLPRT_GOTCL(hw->port),
3257 pf->offset_loaded, &os->eth.tx_bytes,
3258 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3259 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3260 I40E_GLPRT_UPTCL(hw->port),
3261 pf->offset_loaded, &os->eth.tx_unicast,
3262 &ns->eth.tx_unicast);
3263 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3264 I40E_GLPRT_MPTCL(hw->port),
3265 pf->offset_loaded, &os->eth.tx_multicast,
3266 &ns->eth.tx_multicast);
3267 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3268 I40E_GLPRT_BPTCL(hw->port),
3269 pf->offset_loaded, &os->eth.tx_broadcast,
3270 &ns->eth.tx_broadcast);
3271 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3272 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3274 /* exclude internal tx bytes
3275 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3276 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3278 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3280 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3281 ns->eth.tx_bytes = 0;
3283 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3285 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3286 ns->eth.tx_unicast = 0;
3288 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3290 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3291 ns->eth.tx_multicast = 0;
3293 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3295 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3296 ns->eth.tx_broadcast = 0;
3298 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3300 /* GLPRT_TEPC not supported */
3302 /* additional port specific stats */
3303 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3304 pf->offset_loaded, &os->tx_dropped_link_down,
3305 &ns->tx_dropped_link_down);
3306 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3307 pf->offset_loaded, &os->crc_errors,
3309 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3310 pf->offset_loaded, &os->illegal_bytes,
3311 &ns->illegal_bytes);
3312 /* GLPRT_ERRBC not supported */
3313 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3314 pf->offset_loaded, &os->mac_local_faults,
3315 &ns->mac_local_faults);
3316 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3317 pf->offset_loaded, &os->mac_remote_faults,
3318 &ns->mac_remote_faults);
3319 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3320 pf->offset_loaded, &os->rx_length_errors,
3321 &ns->rx_length_errors);
3322 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3323 pf->offset_loaded, &os->link_xon_rx,
3325 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3326 pf->offset_loaded, &os->link_xoff_rx,
3328 for (i = 0; i < 8; i++) {
3329 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3331 &os->priority_xon_rx[i],
3332 &ns->priority_xon_rx[i]);
3333 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3335 &os->priority_xoff_rx[i],
3336 &ns->priority_xoff_rx[i]);
3338 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3339 pf->offset_loaded, &os->link_xon_tx,
3341 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3342 pf->offset_loaded, &os->link_xoff_tx,
3344 for (i = 0; i < 8; i++) {
3345 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3347 &os->priority_xon_tx[i],
3348 &ns->priority_xon_tx[i]);
3349 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3351 &os->priority_xoff_tx[i],
3352 &ns->priority_xoff_tx[i]);
3353 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3355 &os->priority_xon_2_xoff[i],
3356 &ns->priority_xon_2_xoff[i]);
3358 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3359 I40E_GLPRT_PRC64L(hw->port),
3360 pf->offset_loaded, &os->rx_size_64,
3362 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3363 I40E_GLPRT_PRC127L(hw->port),
3364 pf->offset_loaded, &os->rx_size_127,
3366 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3367 I40E_GLPRT_PRC255L(hw->port),
3368 pf->offset_loaded, &os->rx_size_255,
3370 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3371 I40E_GLPRT_PRC511L(hw->port),
3372 pf->offset_loaded, &os->rx_size_511,
3374 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3375 I40E_GLPRT_PRC1023L(hw->port),
3376 pf->offset_loaded, &os->rx_size_1023,
3378 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3379 I40E_GLPRT_PRC1522L(hw->port),
3380 pf->offset_loaded, &os->rx_size_1522,
3382 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3383 I40E_GLPRT_PRC9522L(hw->port),
3384 pf->offset_loaded, &os->rx_size_big,
3386 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3387 pf->offset_loaded, &os->rx_undersize,
3389 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3390 pf->offset_loaded, &os->rx_fragments,
3392 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3393 pf->offset_loaded, &os->rx_oversize,
3395 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3396 pf->offset_loaded, &os->rx_jabber,
3398 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3399 I40E_GLPRT_PTC64L(hw->port),
3400 pf->offset_loaded, &os->tx_size_64,
3402 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3403 I40E_GLPRT_PTC127L(hw->port),
3404 pf->offset_loaded, &os->tx_size_127,
3406 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3407 I40E_GLPRT_PTC255L(hw->port),
3408 pf->offset_loaded, &os->tx_size_255,
3410 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3411 I40E_GLPRT_PTC511L(hw->port),
3412 pf->offset_loaded, &os->tx_size_511,
3414 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3415 I40E_GLPRT_PTC1023L(hw->port),
3416 pf->offset_loaded, &os->tx_size_1023,
3418 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3419 I40E_GLPRT_PTC1522L(hw->port),
3420 pf->offset_loaded, &os->tx_size_1522,
3422 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3423 I40E_GLPRT_PTC9522L(hw->port),
3424 pf->offset_loaded, &os->tx_size_big,
3426 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3428 &os->fd_sb_match, &ns->fd_sb_match);
3429 /* GLPRT_MSPDC not supported */
3430 /* GLPRT_XEC not supported */
3432 pf->offset_loaded = true;
3435 i40e_update_vsi_stats(pf->main_vsi);
3438 /* Get all statistics of a port */
3440 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3442 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3443 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3445 struct i40e_vsi *vsi;
3448 /* call read registers - updates values, now write them to struct */
3449 i40e_read_stats_registers(pf, hw);
3451 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3452 pf->main_vsi->eth_stats.rx_multicast +
3453 pf->main_vsi->eth_stats.rx_broadcast -
3454 pf->main_vsi->eth_stats.rx_discards;
3455 stats->opackets = ns->eth.tx_unicast +
3456 ns->eth.tx_multicast +
3457 ns->eth.tx_broadcast;
3458 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3459 stats->obytes = ns->eth.tx_bytes;
3460 stats->oerrors = ns->eth.tx_errors +
3461 pf->main_vsi->eth_stats.tx_errors;
3464 stats->imissed = ns->eth.rx_discards +
3465 pf->main_vsi->eth_stats.rx_discards;
3466 stats->ierrors = ns->crc_errors +
3467 ns->rx_length_errors + ns->rx_undersize +
3468 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3471 for (i = 0; i < pf->vf_num; i++) {
3472 vsi = pf->vfs[i].vsi;
3473 i40e_update_vsi_stats(vsi);
3475 stats->ipackets += (vsi->eth_stats.rx_unicast +
3476 vsi->eth_stats.rx_multicast +
3477 vsi->eth_stats.rx_broadcast -
3478 vsi->eth_stats.rx_discards);
3479 stats->ibytes += vsi->eth_stats.rx_bytes;
3480 stats->oerrors += vsi->eth_stats.tx_errors;
3481 stats->imissed += vsi->eth_stats.rx_discards;
3485 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3486 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3487 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3488 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3489 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3490 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3491 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3492 ns->eth.rx_unknown_protocol);
3493 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3494 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3495 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3496 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3497 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3498 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3500 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3501 ns->tx_dropped_link_down);
3502 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3503 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3505 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3506 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3507 ns->mac_local_faults);
3508 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3509 ns->mac_remote_faults);
3510 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3511 ns->rx_length_errors);
3512 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3513 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3514 for (i = 0; i < 8; i++) {
3515 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3516 i, ns->priority_xon_rx[i]);
3517 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3518 i, ns->priority_xoff_rx[i]);
3520 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3521 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3522 for (i = 0; i < 8; i++) {
3523 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3524 i, ns->priority_xon_tx[i]);
3525 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3526 i, ns->priority_xoff_tx[i]);
3527 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3528 i, ns->priority_xon_2_xoff[i]);
3530 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3531 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3532 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3533 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3534 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3535 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3536 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3537 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3538 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3539 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3540 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3541 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3542 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3543 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3544 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3545 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3546 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3547 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3548 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3549 ns->mac_short_packet_dropped);
3550 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3551 ns->checksum_error);
3552 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3553 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3557 /* Reset the statistics */
3559 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3561 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3562 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564 /* Mark PF and VSI stats to update the offset, aka "reset" */
3565 pf->offset_loaded = false;
3567 pf->main_vsi->offset_loaded = false;
3569 /* read the stats, reading current register values into offset */
3570 i40e_read_stats_registers(pf, hw);
3576 i40e_xstats_calc_num(void)
3578 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3579 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3580 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3583 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3584 struct rte_eth_xstat_name *xstats_names,
3585 __rte_unused unsigned limit)
3590 if (xstats_names == NULL)
3591 return i40e_xstats_calc_num();
3593 /* Note: limit checked in rte_eth_xstats_names() */
3595 /* Get stats from i40e_eth_stats struct */
3596 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3597 strlcpy(xstats_names[count].name,
3598 rte_i40e_stats_strings[i].name,
3599 sizeof(xstats_names[count].name));
3603 /* Get individiual stats from i40e_hw_port struct */
3604 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3605 strlcpy(xstats_names[count].name,
3606 rte_i40e_hw_port_strings[i].name,
3607 sizeof(xstats_names[count].name));
3611 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3612 for (prio = 0; prio < 8; prio++) {
3613 snprintf(xstats_names[count].name,
3614 sizeof(xstats_names[count].name),
3615 "rx_priority%u_%s", prio,
3616 rte_i40e_rxq_prio_strings[i].name);
3621 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3622 for (prio = 0; prio < 8; prio++) {
3623 snprintf(xstats_names[count].name,
3624 sizeof(xstats_names[count].name),
3625 "tx_priority%u_%s", prio,
3626 rte_i40e_txq_prio_strings[i].name);
3634 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3637 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639 unsigned i, count, prio;
3640 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3642 count = i40e_xstats_calc_num();
3646 i40e_read_stats_registers(pf, hw);
3653 /* Get stats from i40e_eth_stats struct */
3654 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3655 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3656 rte_i40e_stats_strings[i].offset);
3657 xstats[count].id = count;
3661 /* Get individiual stats from i40e_hw_port struct */
3662 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3663 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3664 rte_i40e_hw_port_strings[i].offset);
3665 xstats[count].id = count;
3669 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3670 for (prio = 0; prio < 8; prio++) {
3671 xstats[count].value =
3672 *(uint64_t *)(((char *)hw_stats) +
3673 rte_i40e_rxq_prio_strings[i].offset +
3674 (sizeof(uint64_t) * prio));
3675 xstats[count].id = count;
3680 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3681 for (prio = 0; prio < 8; prio++) {
3682 xstats[count].value =
3683 *(uint64_t *)(((char *)hw_stats) +
3684 rte_i40e_txq_prio_strings[i].offset +
3685 (sizeof(uint64_t) * prio));
3686 xstats[count].id = count;
3695 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3697 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3703 full_ver = hw->nvm.oem_ver;
3704 ver = (u8)(full_ver >> 24);
3705 build = (u16)((full_ver >> 8) & 0xffff);
3706 patch = (u8)(full_ver & 0xff);
3708 ret = snprintf(fw_version, fw_size,
3709 "%d.%d%d 0x%08x %d.%d.%d",
3710 ((hw->nvm.version >> 12) & 0xf),
3711 ((hw->nvm.version >> 4) & 0xff),
3712 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3715 ret += 1; /* add the size of '\0' */
3716 if (fw_size < (u32)ret)
3723 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3724 * the Rx data path does not hang if the FW LLDP is stopped.
3725 * return true if lldp need to stop
3726 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3729 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3732 char ver_str[64] = {0};
3733 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3735 i40e_fw_version_get(dev, ver_str, 64);
3736 nvm_ver = atof(ver_str);
3737 if ((hw->mac.type == I40E_MAC_X722 ||
3738 hw->mac.type == I40E_MAC_X722_VF) &&
3739 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3741 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3748 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3751 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3752 struct i40e_vsi *vsi = pf->main_vsi;
3753 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3755 dev_info->max_rx_queues = vsi->nb_qps;
3756 dev_info->max_tx_queues = vsi->nb_qps;
3757 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3758 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3759 dev_info->max_mac_addrs = vsi->max_macaddrs;
3760 dev_info->max_vfs = pci_dev->max_vfs;
3761 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3762 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3763 dev_info->rx_queue_offload_capa = 0;
3764 dev_info->rx_offload_capa =
3765 DEV_RX_OFFLOAD_VLAN_STRIP |
3766 DEV_RX_OFFLOAD_QINQ_STRIP |
3767 DEV_RX_OFFLOAD_IPV4_CKSUM |
3768 DEV_RX_OFFLOAD_UDP_CKSUM |
3769 DEV_RX_OFFLOAD_TCP_CKSUM |
3770 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3771 DEV_RX_OFFLOAD_KEEP_CRC |
3772 DEV_RX_OFFLOAD_SCATTER |
3773 DEV_RX_OFFLOAD_VLAN_EXTEND |
3774 DEV_RX_OFFLOAD_VLAN_FILTER |
3775 DEV_RX_OFFLOAD_JUMBO_FRAME |
3776 DEV_RX_OFFLOAD_RSS_HASH;
3778 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3779 dev_info->tx_offload_capa =
3780 DEV_TX_OFFLOAD_VLAN_INSERT |
3781 DEV_TX_OFFLOAD_QINQ_INSERT |
3782 DEV_TX_OFFLOAD_IPV4_CKSUM |
3783 DEV_TX_OFFLOAD_UDP_CKSUM |
3784 DEV_TX_OFFLOAD_TCP_CKSUM |
3785 DEV_TX_OFFLOAD_SCTP_CKSUM |
3786 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3787 DEV_TX_OFFLOAD_TCP_TSO |
3788 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3789 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3790 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3791 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3792 DEV_TX_OFFLOAD_MULTI_SEGS |
3793 dev_info->tx_queue_offload_capa;
3794 dev_info->dev_capa =
3795 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3796 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3798 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3800 dev_info->reta_size = pf->hash_lut_size;
3801 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3803 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3805 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3806 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3807 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3809 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3814 dev_info->default_txconf = (struct rte_eth_txconf) {
3816 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3817 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3818 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3820 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3821 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3825 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3826 .nb_max = I40E_MAX_RING_DESC,
3827 .nb_min = I40E_MIN_RING_DESC,
3828 .nb_align = I40E_ALIGN_RING_DESC,
3831 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3832 .nb_max = I40E_MAX_RING_DESC,
3833 .nb_min = I40E_MIN_RING_DESC,
3834 .nb_align = I40E_ALIGN_RING_DESC,
3835 .nb_seg_max = I40E_TX_MAX_SEG,
3836 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3839 if (pf->flags & I40E_FLAG_VMDQ) {
3840 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3841 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3842 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3843 pf->max_nb_vmdq_vsi;
3844 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3845 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3846 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3849 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3851 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3852 dev_info->default_rxportconf.nb_queues = 2;
3853 dev_info->default_txportconf.nb_queues = 2;
3854 if (dev->data->nb_rx_queues == 1)
3855 dev_info->default_rxportconf.ring_size = 2048;
3857 dev_info->default_rxportconf.ring_size = 1024;
3858 if (dev->data->nb_tx_queues == 1)
3859 dev_info->default_txportconf.ring_size = 1024;
3861 dev_info->default_txportconf.ring_size = 512;
3863 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3865 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3866 dev_info->default_rxportconf.nb_queues = 1;
3867 dev_info->default_txportconf.nb_queues = 1;
3868 dev_info->default_rxportconf.ring_size = 256;
3869 dev_info->default_txportconf.ring_size = 256;
3872 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3873 dev_info->default_rxportconf.nb_queues = 1;
3874 dev_info->default_txportconf.nb_queues = 1;
3875 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3876 dev_info->default_rxportconf.ring_size = 512;
3877 dev_info->default_txportconf.ring_size = 256;
3879 dev_info->default_rxportconf.ring_size = 256;
3880 dev_info->default_txportconf.ring_size = 256;
3883 dev_info->default_rxportconf.burst_size = 32;
3884 dev_info->default_txportconf.burst_size = 32;
3890 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3893 struct i40e_vsi *vsi = pf->main_vsi;
3894 PMD_INIT_FUNC_TRACE();
3897 return i40e_vsi_add_vlan(vsi, vlan_id);
3899 return i40e_vsi_delete_vlan(vsi, vlan_id);
3903 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3904 enum rte_vlan_type vlan_type,
3905 uint16_t tpid, int qinq)
3907 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910 uint16_t reg_id = 3;
3914 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3918 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3920 if (ret != I40E_SUCCESS) {
3922 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3927 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3930 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3931 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3932 if (reg_r == reg_w) {
3933 PMD_DRV_LOG(DEBUG, "No need to write");
3937 ret = i40e_aq_debug_write_global_register(hw,
3938 I40E_GL_SWT_L2TAGCTRL(reg_id),
3940 if (ret != I40E_SUCCESS) {
3942 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3947 "Global register 0x%08x is changed with value 0x%08x",
3948 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3954 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3955 enum rte_vlan_type vlan_type,
3958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3960 int qinq = dev->data->dev_conf.rxmode.offloads &
3961 DEV_RX_OFFLOAD_VLAN_EXTEND;
3964 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3965 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3966 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3968 "Unsupported vlan type.");
3972 if (pf->support_multi_driver) {
3973 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3977 /* 802.1ad frames ability is added in NVM API 1.7*/
3978 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3980 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3981 hw->first_tag = rte_cpu_to_le_16(tpid);
3982 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3983 hw->second_tag = rte_cpu_to_le_16(tpid);
3985 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3986 hw->second_tag = rte_cpu_to_le_16(tpid);
3988 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3989 if (ret != I40E_SUCCESS) {
3991 "Set switch config failed aq_err: %d",
3992 hw->aq.asq_last_status);
3996 /* If NVM API < 1.7, keep the register setting */
3997 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
4003 /* Configure outer vlan stripping on or off in QinQ mode */
4005 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
4007 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4008 int ret = I40E_SUCCESS;
4011 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
4012 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4016 /* Configure for outer VLAN RX stripping */
4017 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4020 reg |= I40E_VSI_TSR_QINQ_STRIP;
4022 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4024 ret = i40e_aq_debug_write_register(hw,
4025 I40E_VSI_TSR(vsi->vsi_id),
4028 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4030 return I40E_ERR_CONFIG;
4037 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4039 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4040 struct i40e_vsi *vsi = pf->main_vsi;
4041 struct rte_eth_rxmode *rxmode;
4043 rxmode = &dev->data->dev_conf.rxmode;
4044 if (mask & ETH_VLAN_FILTER_MASK) {
4045 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4046 i40e_vsi_config_vlan_filter(vsi, TRUE);
4048 i40e_vsi_config_vlan_filter(vsi, FALSE);
4051 if (mask & ETH_VLAN_STRIP_MASK) {
4052 /* Enable or disable VLAN stripping */
4053 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4054 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4056 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4059 if (mask & ETH_VLAN_EXTEND_MASK) {
4060 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4061 i40e_vsi_config_double_vlan(vsi, TRUE);
4062 /* Set global registers with default ethertype. */
4063 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4064 RTE_ETHER_TYPE_VLAN);
4065 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4066 RTE_ETHER_TYPE_VLAN);
4069 i40e_vsi_config_double_vlan(vsi, FALSE);
4072 if (mask & ETH_QINQ_STRIP_MASK) {
4073 /* Enable or disable outer VLAN stripping */
4074 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4075 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4077 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4084 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4085 __rte_unused uint16_t queue,
4086 __rte_unused int on)
4088 PMD_INIT_FUNC_TRACE();
4092 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4094 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4095 struct i40e_vsi *vsi = pf->main_vsi;
4096 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4097 struct i40e_vsi_vlan_pvid_info info;
4099 memset(&info, 0, sizeof(info));
4102 info.config.pvid = pvid;
4104 info.config.reject.tagged =
4105 data->dev_conf.txmode.hw_vlan_reject_tagged;
4106 info.config.reject.untagged =
4107 data->dev_conf.txmode.hw_vlan_reject_untagged;
4110 return i40e_vsi_vlan_pvid_set(vsi, &info);
4114 i40e_dev_led_on(struct rte_eth_dev *dev)
4116 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117 uint32_t mode = i40e_led_get(hw);
4120 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4126 i40e_dev_led_off(struct rte_eth_dev *dev)
4128 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129 uint32_t mode = i40e_led_get(hw);
4132 i40e_led_set(hw, 0, false);
4138 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4140 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4143 fc_conf->pause_time = pf->fc_conf.pause_time;
4145 /* read out from register, in case they are modified by other port */
4146 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4147 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4148 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4149 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4151 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4152 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4154 /* Return current mode according to actual setting*/
4155 switch (hw->fc.current_mode) {
4157 fc_conf->mode = RTE_FC_FULL;
4159 case I40E_FC_TX_PAUSE:
4160 fc_conf->mode = RTE_FC_TX_PAUSE;
4162 case I40E_FC_RX_PAUSE:
4163 fc_conf->mode = RTE_FC_RX_PAUSE;
4167 fc_conf->mode = RTE_FC_NONE;
4174 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4176 uint32_t mflcn_reg, fctrl_reg, reg;
4177 uint32_t max_high_water;
4178 uint8_t i, aq_failure;
4182 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4183 [RTE_FC_NONE] = I40E_FC_NONE,
4184 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4185 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4186 [RTE_FC_FULL] = I40E_FC_FULL
4189 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4191 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4192 if ((fc_conf->high_water > max_high_water) ||
4193 (fc_conf->high_water < fc_conf->low_water)) {
4195 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4200 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4202 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4204 pf->fc_conf.pause_time = fc_conf->pause_time;
4205 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4206 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4208 PMD_INIT_FUNC_TRACE();
4210 /* All the link flow control related enable/disable register
4211 * configuration is handle by the F/W
4213 err = i40e_set_fc(hw, &aq_failure, true);
4217 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4218 /* Configure flow control refresh threshold,
4219 * the value for stat_tx_pause_refresh_timer[8]
4220 * is used for global pause operation.
4224 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4225 pf->fc_conf.pause_time);
4227 /* configure the timer value included in transmitted pause
4229 * the value for stat_tx_pause_quanta[8] is used for global
4232 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4233 pf->fc_conf.pause_time);
4235 fctrl_reg = I40E_READ_REG(hw,
4236 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4238 if (fc_conf->mac_ctrl_frame_fwd != 0)
4239 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4241 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4243 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4246 /* Configure pause time (2 TCs per register) */
4247 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4248 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4249 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4251 /* Configure flow control refresh threshold value */
4252 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4253 pf->fc_conf.pause_time / 2);
4255 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4257 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4258 *depending on configuration
4260 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4261 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4262 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4264 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4265 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4268 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4271 if (!pf->support_multi_driver) {
4272 /* config water marker both based on the packets and bytes */
4273 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4274 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4275 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4276 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4277 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4278 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4279 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4280 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4282 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4283 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4287 "Water marker configuration is not supported.");
4290 I40E_WRITE_FLUSH(hw);
4296 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4297 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4299 PMD_INIT_FUNC_TRACE();
4304 /* Add a MAC address, and update filters */
4306 i40e_macaddr_add(struct rte_eth_dev *dev,
4307 struct rte_ether_addr *mac_addr,
4308 __rte_unused uint32_t index,
4311 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4312 struct i40e_mac_filter_info mac_filter;
4313 struct i40e_vsi *vsi;
4314 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4317 /* If VMDQ not enabled or configured, return */
4318 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4319 !pf->nb_cfg_vmdq_vsi)) {
4320 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4321 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4326 if (pool > pf->nb_cfg_vmdq_vsi) {
4327 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4328 pool, pf->nb_cfg_vmdq_vsi);
4332 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4333 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4334 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4336 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4341 vsi = pf->vmdq[pool - 1].vsi;
4343 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4344 if (ret != I40E_SUCCESS) {
4345 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4351 /* Remove a MAC address, and update filters */
4353 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4356 struct i40e_vsi *vsi;
4357 struct rte_eth_dev_data *data = dev->data;
4358 struct rte_ether_addr *macaddr;
4363 macaddr = &(data->mac_addrs[index]);
4365 pool_sel = dev->data->mac_pool_sel[index];
4367 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4368 if (pool_sel & (1ULL << i)) {
4372 /* No VMDQ pool enabled or configured */
4373 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4374 (i > pf->nb_cfg_vmdq_vsi)) {
4376 "No VMDQ pool enabled/configured");
4379 vsi = pf->vmdq[i - 1].vsi;
4381 ret = i40e_vsi_delete_mac(vsi, macaddr);
4384 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4391 /* Set perfect match or hash match of MAC and VLAN for a VF */
4393 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4394 struct rte_eth_mac_filter *filter,
4398 struct i40e_mac_filter_info mac_filter;
4399 struct rte_ether_addr old_mac;
4400 struct rte_ether_addr *new_mac;
4401 struct i40e_pf_vf *vf = NULL;
4406 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4409 hw = I40E_PF_TO_HW(pf);
4411 if (filter == NULL) {
4412 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4416 new_mac = &filter->mac_addr;
4418 if (rte_is_zero_ether_addr(new_mac)) {
4419 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4423 vf_id = filter->dst_id;
4425 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4426 PMD_DRV_LOG(ERR, "Invalid argument.");
4429 vf = &pf->vfs[vf_id];
4431 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4432 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4437 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4438 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4439 RTE_ETHER_ADDR_LEN);
4440 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4441 RTE_ETHER_ADDR_LEN);
4443 mac_filter.filter_type = filter->filter_type;
4444 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4445 if (ret != I40E_SUCCESS) {
4446 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4449 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4451 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4452 RTE_ETHER_ADDR_LEN);
4453 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4454 if (ret != I40E_SUCCESS) {
4455 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4459 /* Clear device address as it has been removed */
4460 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4461 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4467 /* MAC filter handle */
4469 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4473 struct rte_eth_mac_filter *filter;
4474 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4475 int ret = I40E_NOT_SUPPORTED;
4477 filter = (struct rte_eth_mac_filter *)(arg);
4479 switch (filter_op) {
4480 case RTE_ETH_FILTER_NOP:
4483 case RTE_ETH_FILTER_ADD:
4484 i40e_pf_disable_irq0(hw);
4486 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4487 i40e_pf_enable_irq0(hw);
4489 case RTE_ETH_FILTER_DELETE:
4490 i40e_pf_disable_irq0(hw);
4492 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4493 i40e_pf_enable_irq0(hw);
4496 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4497 ret = I40E_ERR_PARAM;
4505 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4507 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4508 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4515 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4516 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4517 vsi->type != I40E_VSI_SRIOV,
4520 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4524 uint32_t *lut_dw = (uint32_t *)lut;
4525 uint16_t i, lut_size_dw = lut_size / 4;
4527 if (vsi->type == I40E_VSI_SRIOV) {
4528 for (i = 0; i <= lut_size_dw; i++) {
4529 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4530 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4533 for (i = 0; i < lut_size_dw; i++)
4534 lut_dw[i] = I40E_READ_REG(hw,
4543 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4552 pf = I40E_VSI_TO_PF(vsi);
4553 hw = I40E_VSI_TO_HW(vsi);
4555 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4556 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4557 vsi->type != I40E_VSI_SRIOV,
4560 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4564 uint32_t *lut_dw = (uint32_t *)lut;
4565 uint16_t i, lut_size_dw = lut_size / 4;
4567 if (vsi->type == I40E_VSI_SRIOV) {
4568 for (i = 0; i < lut_size_dw; i++)
4571 I40E_VFQF_HLUT1(i, vsi->user_param),
4574 for (i = 0; i < lut_size_dw; i++)
4575 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4578 I40E_WRITE_FLUSH(hw);
4585 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4586 struct rte_eth_rss_reta_entry64 *reta_conf,
4589 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4590 uint16_t i, lut_size = pf->hash_lut_size;
4591 uint16_t idx, shift;
4595 if (reta_size != lut_size ||
4596 reta_size > ETH_RSS_RETA_SIZE_512) {
4598 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4599 reta_size, lut_size);
4603 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4605 PMD_DRV_LOG(ERR, "No memory can be allocated");
4608 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4611 for (i = 0; i < reta_size; i++) {
4612 idx = i / RTE_RETA_GROUP_SIZE;
4613 shift = i % RTE_RETA_GROUP_SIZE;
4614 if (reta_conf[idx].mask & (1ULL << shift))
4615 lut[i] = reta_conf[idx].reta[shift];
4617 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4619 pf->adapter->rss_reta_updated = 1;
4628 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4629 struct rte_eth_rss_reta_entry64 *reta_conf,
4632 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4633 uint16_t i, lut_size = pf->hash_lut_size;
4634 uint16_t idx, shift;
4638 if (reta_size != lut_size ||
4639 reta_size > ETH_RSS_RETA_SIZE_512) {
4641 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4642 reta_size, lut_size);
4646 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4648 PMD_DRV_LOG(ERR, "No memory can be allocated");
4652 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4655 for (i = 0; i < reta_size; i++) {
4656 idx = i / RTE_RETA_GROUP_SIZE;
4657 shift = i % RTE_RETA_GROUP_SIZE;
4658 if (reta_conf[idx].mask & (1ULL << shift))
4659 reta_conf[idx].reta[shift] = lut[i];
4669 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4670 * @hw: pointer to the HW structure
4671 * @mem: pointer to mem struct to fill out
4672 * @size: size of memory requested
4673 * @alignment: what to align the allocation to
4675 enum i40e_status_code
4676 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4677 struct i40e_dma_mem *mem,
4681 const struct rte_memzone *mz = NULL;
4682 char z_name[RTE_MEMZONE_NAMESIZE];
4685 return I40E_ERR_PARAM;
4687 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4688 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4689 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4691 return I40E_ERR_NO_MEMORY;
4696 mem->zone = (const void *)mz;
4698 "memzone %s allocated with physical address: %"PRIu64,
4701 return I40E_SUCCESS;
4705 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4706 * @hw: pointer to the HW structure
4707 * @mem: ptr to mem struct to free
4709 enum i40e_status_code
4710 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4711 struct i40e_dma_mem *mem)
4714 return I40E_ERR_PARAM;
4717 "memzone %s to be freed with physical address: %"PRIu64,
4718 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4719 rte_memzone_free((const struct rte_memzone *)mem->zone);
4724 return I40E_SUCCESS;
4728 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4729 * @hw: pointer to the HW structure
4730 * @mem: pointer to mem struct to fill out
4731 * @size: size of memory requested
4733 enum i40e_status_code
4734 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4735 struct i40e_virt_mem *mem,
4739 return I40E_ERR_PARAM;
4742 mem->va = rte_zmalloc("i40e", size, 0);
4745 return I40E_SUCCESS;
4747 return I40E_ERR_NO_MEMORY;
4751 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4752 * @hw: pointer to the HW structure
4753 * @mem: pointer to mem struct to free
4755 enum i40e_status_code
4756 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4757 struct i40e_virt_mem *mem)
4760 return I40E_ERR_PARAM;
4765 return I40E_SUCCESS;
4769 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4771 rte_spinlock_init(&sp->spinlock);
4775 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4777 rte_spinlock_lock(&sp->spinlock);
4781 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4783 rte_spinlock_unlock(&sp->spinlock);
4787 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4793 * Get the hardware capabilities, which will be parsed
4794 * and saved into struct i40e_hw.
4797 i40e_get_cap(struct i40e_hw *hw)
4799 struct i40e_aqc_list_capabilities_element_resp *buf;
4800 uint16_t len, size = 0;
4803 /* Calculate a huge enough buff for saving response data temporarily */
4804 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4805 I40E_MAX_CAP_ELE_NUM;
4806 buf = rte_zmalloc("i40e", len, 0);
4808 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4809 return I40E_ERR_NO_MEMORY;
4812 /* Get, parse the capabilities and save it to hw */
4813 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4814 i40e_aqc_opc_list_func_capabilities, NULL);
4815 if (ret != I40E_SUCCESS)
4816 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4818 /* Free the temporary buffer after being used */
4824 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4826 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4834 pf = (struct i40e_pf *)opaque;
4838 num = strtoul(value, &end, 0);
4839 if (errno != 0 || end == value || *end != 0) {
4840 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4841 "kept the value = %hu", value, pf->vf_nb_qp_max);
4845 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4846 pf->vf_nb_qp_max = (uint16_t)num;
4848 /* here return 0 to make next valid same argument work */
4849 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4850 "power of 2 and equal or less than 16 !, Now it is "
4851 "kept the value = %hu", num, pf->vf_nb_qp_max);
4856 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4858 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4859 struct rte_kvargs *kvlist;
4862 /* set default queue number per VF as 4 */
4863 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4865 if (dev->device->devargs == NULL)
4868 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4872 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4873 if (!kvargs_count) {
4874 rte_kvargs_free(kvlist);
4878 if (kvargs_count > 1)
4879 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4880 "the first invalid or last valid one is used !",
4881 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4883 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4884 i40e_pf_parse_vf_queue_number_handler, pf);
4886 rte_kvargs_free(kvlist);
4892 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4894 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4895 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4896 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4897 uint16_t qp_count = 0, vsi_count = 0;
4899 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4900 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4904 i40e_pf_config_vf_rxq_number(dev);
4906 /* Add the parameter init for LFC */
4907 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4908 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4909 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4911 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4912 pf->max_num_vsi = hw->func_caps.num_vsis;
4913 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4914 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4916 /* FDir queue/VSI allocation */
4917 pf->fdir_qp_offset = 0;
4918 if (hw->func_caps.fd) {
4919 pf->flags |= I40E_FLAG_FDIR;
4920 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4922 pf->fdir_nb_qps = 0;
4924 qp_count += pf->fdir_nb_qps;
4927 /* LAN queue/VSI allocation */
4928 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4929 if (!hw->func_caps.rss) {
4932 pf->flags |= I40E_FLAG_RSS;
4933 if (hw->mac.type == I40E_MAC_X722)
4934 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4935 pf->lan_nb_qps = pf->lan_nb_qp_max;
4937 qp_count += pf->lan_nb_qps;
4940 /* VF queue/VSI allocation */
4941 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4942 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4943 pf->flags |= I40E_FLAG_SRIOV;
4944 pf->vf_nb_qps = pf->vf_nb_qp_max;
4945 pf->vf_num = pci_dev->max_vfs;
4947 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4948 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4953 qp_count += pf->vf_nb_qps * pf->vf_num;
4954 vsi_count += pf->vf_num;
4956 /* VMDq queue/VSI allocation */
4957 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4958 pf->vmdq_nb_qps = 0;
4959 pf->max_nb_vmdq_vsi = 0;
4960 if (hw->func_caps.vmdq) {
4961 if (qp_count < hw->func_caps.num_tx_qp &&
4962 vsi_count < hw->func_caps.num_vsis) {
4963 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4964 qp_count) / pf->vmdq_nb_qp_max;
4966 /* Limit the maximum number of VMDq vsi to the maximum
4967 * ethdev can support
4969 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4970 hw->func_caps.num_vsis - vsi_count);
4971 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4973 if (pf->max_nb_vmdq_vsi) {
4974 pf->flags |= I40E_FLAG_VMDQ;
4975 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4977 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4978 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4979 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4982 "No enough queues left for VMDq");
4985 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4988 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4989 vsi_count += pf->max_nb_vmdq_vsi;
4991 if (hw->func_caps.dcb)
4992 pf->flags |= I40E_FLAG_DCB;
4994 if (qp_count > hw->func_caps.num_tx_qp) {
4996 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4997 qp_count, hw->func_caps.num_tx_qp);
5000 if (vsi_count > hw->func_caps.num_vsis) {
5002 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
5003 vsi_count, hw->func_caps.num_vsis);
5011 i40e_pf_get_switch_config(struct i40e_pf *pf)
5013 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5014 struct i40e_aqc_get_switch_config_resp *switch_config;
5015 struct i40e_aqc_switch_config_element_resp *element;
5016 uint16_t start_seid = 0, num_reported;
5019 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
5020 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
5021 if (!switch_config) {
5022 PMD_DRV_LOG(ERR, "Failed to allocated memory");
5026 /* Get the switch configurations */
5027 ret = i40e_aq_get_switch_config(hw, switch_config,
5028 I40E_AQ_LARGE_BUF, &start_seid, NULL);
5029 if (ret != I40E_SUCCESS) {
5030 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
5033 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
5034 if (num_reported != 1) { /* The number should be 1 */
5035 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
5039 /* Parse the switch configuration elements */
5040 element = &(switch_config->element[0]);
5041 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
5042 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
5043 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
5045 PMD_DRV_LOG(INFO, "Unknown element type");
5048 rte_free(switch_config);
5054 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
5057 struct pool_entry *entry;
5059 if (pool == NULL || num == 0)
5062 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5063 if (entry == NULL) {
5064 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5068 /* queue heap initialize */
5069 pool->num_free = num;
5070 pool->num_alloc = 0;
5072 LIST_INIT(&pool->alloc_list);
5073 LIST_INIT(&pool->free_list);
5075 /* Initialize element */
5079 LIST_INSERT_HEAD(&pool->free_list, entry, next);
5084 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5086 struct pool_entry *entry, *next_entry;
5091 for (entry = LIST_FIRST(&pool->alloc_list);
5092 entry && (next_entry = LIST_NEXT(entry, next), 1);
5093 entry = next_entry) {
5094 LIST_REMOVE(entry, next);
5098 for (entry = LIST_FIRST(&pool->free_list);
5099 entry && (next_entry = LIST_NEXT(entry, next), 1);
5100 entry = next_entry) {
5101 LIST_REMOVE(entry, next);
5106 pool->num_alloc = 0;
5108 LIST_INIT(&pool->alloc_list);
5109 LIST_INIT(&pool->free_list);
5113 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5116 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5117 uint32_t pool_offset;
5122 PMD_DRV_LOG(ERR, "Invalid parameter");
5126 pool_offset = base - pool->base;
5127 /* Lookup in alloc list */
5128 LIST_FOREACH(entry, &pool->alloc_list, next) {
5129 if (entry->base == pool_offset) {
5130 valid_entry = entry;
5131 LIST_REMOVE(entry, next);
5136 /* Not find, return */
5137 if (valid_entry == NULL) {
5138 PMD_DRV_LOG(ERR, "Failed to find entry");
5143 * Found it, move it to free list and try to merge.
5144 * In order to make merge easier, always sort it by qbase.
5145 * Find adjacent prev and last entries.
5148 LIST_FOREACH(entry, &pool->free_list, next) {
5149 if (entry->base > valid_entry->base) {
5157 len = valid_entry->len;
5158 /* Try to merge with next one*/
5160 /* Merge with next one */
5161 if (valid_entry->base + len == next->base) {
5162 next->base = valid_entry->base;
5164 rte_free(valid_entry);
5171 /* Merge with previous one */
5172 if (prev->base + prev->len == valid_entry->base) {
5174 /* If it merge with next one, remove next node */
5176 LIST_REMOVE(valid_entry, next);
5177 rte_free(valid_entry);
5180 rte_free(valid_entry);
5187 /* Not find any entry to merge, insert */
5190 LIST_INSERT_AFTER(prev, valid_entry, next);
5191 else if (next != NULL)
5192 LIST_INSERT_BEFORE(next, valid_entry, next);
5193 else /* It's empty list, insert to head */
5194 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5197 pool->num_free += len;
5198 pool->num_alloc -= len;
5204 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5207 struct pool_entry *entry, *valid_entry;
5209 if (pool == NULL || num == 0) {
5210 PMD_DRV_LOG(ERR, "Invalid parameter");
5214 if (pool->num_free < num) {
5215 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5216 num, pool->num_free);
5221 /* Lookup in free list and find most fit one */
5222 LIST_FOREACH(entry, &pool->free_list, next) {
5223 if (entry->len >= num) {
5225 if (entry->len == num) {
5226 valid_entry = entry;
5229 if (valid_entry == NULL || valid_entry->len > entry->len)
5230 valid_entry = entry;
5234 /* Not find one to satisfy the request, return */
5235 if (valid_entry == NULL) {
5236 PMD_DRV_LOG(ERR, "No valid entry found");
5240 * The entry have equal queue number as requested,
5241 * remove it from alloc_list.
5243 if (valid_entry->len == num) {
5244 LIST_REMOVE(valid_entry, next);
5247 * The entry have more numbers than requested,
5248 * create a new entry for alloc_list and minus its
5249 * queue base and number in free_list.
5251 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5252 if (entry == NULL) {
5254 "Failed to allocate memory for resource pool");
5257 entry->base = valid_entry->base;
5259 valid_entry->base += num;
5260 valid_entry->len -= num;
5261 valid_entry = entry;
5264 /* Insert it into alloc list, not sorted */
5265 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5267 pool->num_free -= valid_entry->len;
5268 pool->num_alloc += valid_entry->len;
5270 return valid_entry->base + pool->base;
5274 * bitmap_is_subset - Check whether src2 is subset of src1
5277 bitmap_is_subset(uint8_t src1, uint8_t src2)
5279 return !((src1 ^ src2) & src2);
5282 static enum i40e_status_code
5283 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5285 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5287 /* If DCB is not supported, only default TC is supported */
5288 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5289 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5290 return I40E_NOT_SUPPORTED;
5293 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5295 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5296 hw->func_caps.enabled_tcmap, enabled_tcmap);
5297 return I40E_NOT_SUPPORTED;
5299 return I40E_SUCCESS;
5303 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5304 struct i40e_vsi_vlan_pvid_info *info)
5307 struct i40e_vsi_context ctxt;
5308 uint8_t vlan_flags = 0;
5311 if (vsi == NULL || info == NULL) {
5312 PMD_DRV_LOG(ERR, "invalid parameters");
5313 return I40E_ERR_PARAM;
5317 vsi->info.pvid = info->config.pvid;
5319 * If insert pvid is enabled, only tagged pkts are
5320 * allowed to be sent out.
5322 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5323 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5326 if (info->config.reject.tagged == 0)
5327 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5329 if (info->config.reject.untagged == 0)
5330 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5332 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5333 I40E_AQ_VSI_PVLAN_MODE_MASK);
5334 vsi->info.port_vlan_flags |= vlan_flags;
5335 vsi->info.valid_sections =
5336 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5337 memset(&ctxt, 0, sizeof(ctxt));
5338 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5339 ctxt.seid = vsi->seid;
5341 hw = I40E_VSI_TO_HW(vsi);
5342 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5343 if (ret != I40E_SUCCESS)
5344 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5350 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5352 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5354 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5356 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5357 if (ret != I40E_SUCCESS)
5361 PMD_DRV_LOG(ERR, "seid not valid");
5365 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5366 tc_bw_data.tc_valid_bits = enabled_tcmap;
5367 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5368 tc_bw_data.tc_bw_credits[i] =
5369 (enabled_tcmap & (1 << i)) ? 1 : 0;
5371 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5372 if (ret != I40E_SUCCESS) {
5373 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5377 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5378 sizeof(vsi->info.qs_handle));
5379 return I40E_SUCCESS;
5382 static enum i40e_status_code
5383 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5384 struct i40e_aqc_vsi_properties_data *info,
5385 uint8_t enabled_tcmap)
5387 enum i40e_status_code ret;
5388 int i, total_tc = 0;
5389 uint16_t qpnum_per_tc, bsf, qp_idx;
5391 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5392 if (ret != I40E_SUCCESS)
5395 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5396 if (enabled_tcmap & (1 << i))
5400 vsi->enabled_tc = enabled_tcmap;
5402 /* Number of queues per enabled TC */
5403 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5404 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5405 bsf = rte_bsf32(qpnum_per_tc);
5407 /* Adjust the queue number to actual queues that can be applied */
5408 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5409 vsi->nb_qps = qpnum_per_tc * total_tc;
5412 * Configure TC and queue mapping parameters, for enabled TC,
5413 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5414 * default queue will serve it.
5417 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5418 if (vsi->enabled_tc & (1 << i)) {
5419 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5420 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5421 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5422 qp_idx += qpnum_per_tc;
5424 info->tc_mapping[i] = 0;
5427 /* Associate queue number with VSI */
5428 if (vsi->type == I40E_VSI_SRIOV) {
5429 info->mapping_flags |=
5430 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5431 for (i = 0; i < vsi->nb_qps; i++)
5432 info->queue_mapping[i] =
5433 rte_cpu_to_le_16(vsi->base_queue + i);
5435 info->mapping_flags |=
5436 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5437 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5439 info->valid_sections |=
5440 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5442 return I40E_SUCCESS;
5446 i40e_veb_release(struct i40e_veb *veb)
5448 struct i40e_vsi *vsi;
5454 if (!TAILQ_EMPTY(&veb->head)) {
5455 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5458 /* associate_vsi field is NULL for floating VEB */
5459 if (veb->associate_vsi != NULL) {
5460 vsi = veb->associate_vsi;
5461 hw = I40E_VSI_TO_HW(vsi);
5463 vsi->uplink_seid = veb->uplink_seid;
5466 veb->associate_pf->main_vsi->floating_veb = NULL;
5467 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5470 i40e_aq_delete_element(hw, veb->seid, NULL);
5472 return I40E_SUCCESS;
5476 static struct i40e_veb *
5477 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5479 struct i40e_veb *veb;
5485 "veb setup failed, associated PF shouldn't null");
5488 hw = I40E_PF_TO_HW(pf);
5490 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5492 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5496 veb->associate_vsi = vsi;
5497 veb->associate_pf = pf;
5498 TAILQ_INIT(&veb->head);
5499 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5501 /* create floating veb if vsi is NULL */
5503 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5504 I40E_DEFAULT_TCMAP, false,
5505 &veb->seid, false, NULL);
5507 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5508 true, &veb->seid, false, NULL);
5511 if (ret != I40E_SUCCESS) {
5512 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5513 hw->aq.asq_last_status);
5516 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5518 /* get statistics index */
5519 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5520 &veb->stats_idx, NULL, NULL, NULL);
5521 if (ret != I40E_SUCCESS) {
5522 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5523 hw->aq.asq_last_status);
5526 /* Get VEB bandwidth, to be implemented */
5527 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5529 vsi->uplink_seid = veb->seid;
5538 i40e_vsi_release(struct i40e_vsi *vsi)
5542 struct i40e_vsi_list *vsi_list;
5545 struct i40e_mac_filter *f;
5546 uint16_t user_param;
5549 return I40E_SUCCESS;
5554 user_param = vsi->user_param;
5556 pf = I40E_VSI_TO_PF(vsi);
5557 hw = I40E_VSI_TO_HW(vsi);
5559 /* VSI has child to attach, release child first */
5561 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5562 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5565 i40e_veb_release(vsi->veb);
5568 if (vsi->floating_veb) {
5569 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5570 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5575 /* Remove all macvlan filters of the VSI */
5576 i40e_vsi_remove_all_macvlan_filter(vsi);
5577 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5580 if (vsi->type != I40E_VSI_MAIN &&
5581 ((vsi->type != I40E_VSI_SRIOV) ||
5582 !pf->floating_veb_list[user_param])) {
5583 /* Remove vsi from parent's sibling list */
5584 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5585 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5586 return I40E_ERR_PARAM;
5588 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5589 &vsi->sib_vsi_list, list);
5591 /* Remove all switch element of the VSI */
5592 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5593 if (ret != I40E_SUCCESS)
5594 PMD_DRV_LOG(ERR, "Failed to delete element");
5597 if ((vsi->type == I40E_VSI_SRIOV) &&
5598 pf->floating_veb_list[user_param]) {
5599 /* Remove vsi from parent's sibling list */
5600 if (vsi->parent_vsi == NULL ||
5601 vsi->parent_vsi->floating_veb == NULL) {
5602 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5603 return I40E_ERR_PARAM;
5605 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5606 &vsi->sib_vsi_list, list);
5608 /* Remove all switch element of the VSI */
5609 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5610 if (ret != I40E_SUCCESS)
5611 PMD_DRV_LOG(ERR, "Failed to delete element");
5614 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5616 if (vsi->type != I40E_VSI_SRIOV)
5617 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5620 return I40E_SUCCESS;
5624 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5626 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5627 struct i40e_aqc_remove_macvlan_element_data def_filter;
5628 struct i40e_mac_filter_info filter;
5631 if (vsi->type != I40E_VSI_MAIN)
5632 return I40E_ERR_CONFIG;
5633 memset(&def_filter, 0, sizeof(def_filter));
5634 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5636 def_filter.vlan_tag = 0;
5637 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5638 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5639 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5640 if (ret != I40E_SUCCESS) {
5641 struct i40e_mac_filter *f;
5642 struct rte_ether_addr *mac;
5645 "Cannot remove the default macvlan filter");
5646 /* It needs to add the permanent mac into mac list */
5647 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5649 PMD_DRV_LOG(ERR, "failed to allocate memory");
5650 return I40E_ERR_NO_MEMORY;
5652 mac = &f->mac_info.mac_addr;
5653 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5655 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5656 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5661 rte_memcpy(&filter.mac_addr,
5662 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5663 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5664 return i40e_vsi_add_mac(vsi, &filter);
5668 * i40e_vsi_get_bw_config - Query VSI BW Information
5669 * @vsi: the VSI to be queried
5671 * Returns 0 on success, negative value on failure
5673 static enum i40e_status_code
5674 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5676 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5677 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5678 struct i40e_hw *hw = &vsi->adapter->hw;
5683 memset(&bw_config, 0, sizeof(bw_config));
5684 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5685 if (ret != I40E_SUCCESS) {
5686 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5687 hw->aq.asq_last_status);
5691 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5692 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5693 &ets_sla_config, NULL);
5694 if (ret != I40E_SUCCESS) {
5696 "VSI failed to get TC bandwdith configuration %u",
5697 hw->aq.asq_last_status);
5701 /* store and print out BW info */
5702 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5703 vsi->bw_info.bw_max = bw_config.max_bw;
5704 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5705 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5706 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5707 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5709 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5710 vsi->bw_info.bw_ets_share_credits[i] =
5711 ets_sla_config.share_credits[i];
5712 vsi->bw_info.bw_ets_credits[i] =
5713 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5714 /* 4 bits per TC, 4th bit is reserved */
5715 vsi->bw_info.bw_ets_max[i] =
5716 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5717 RTE_LEN2MASK(3, uint8_t));
5718 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5719 vsi->bw_info.bw_ets_share_credits[i]);
5720 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5721 vsi->bw_info.bw_ets_credits[i]);
5722 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5723 vsi->bw_info.bw_ets_max[i]);
5726 return I40E_SUCCESS;
5729 /* i40e_enable_pf_lb
5730 * @pf: pointer to the pf structure
5732 * allow loopback on pf
5735 i40e_enable_pf_lb(struct i40e_pf *pf)
5737 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5738 struct i40e_vsi_context ctxt;
5741 /* Use the FW API if FW >= v5.0 */
5742 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5743 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5747 memset(&ctxt, 0, sizeof(ctxt));
5748 ctxt.seid = pf->main_vsi_seid;
5749 ctxt.pf_num = hw->pf_id;
5750 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5752 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5753 ret, hw->aq.asq_last_status);
5756 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5757 ctxt.info.valid_sections =
5758 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5759 ctxt.info.switch_id |=
5760 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5762 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5764 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5765 hw->aq.asq_last_status);
5770 i40e_vsi_setup(struct i40e_pf *pf,
5771 enum i40e_vsi_type type,
5772 struct i40e_vsi *uplink_vsi,
5773 uint16_t user_param)
5775 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5776 struct i40e_vsi *vsi;
5777 struct i40e_mac_filter_info filter;
5779 struct i40e_vsi_context ctxt;
5780 struct rte_ether_addr broadcast =
5781 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5783 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5784 uplink_vsi == NULL) {
5786 "VSI setup failed, VSI link shouldn't be NULL");
5790 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5792 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5797 * 1.type is not MAIN and uplink vsi is not NULL
5798 * If uplink vsi didn't setup VEB, create one first under veb field
5799 * 2.type is SRIOV and the uplink is NULL
5800 * If floating VEB is NULL, create one veb under floating veb field
5803 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5804 uplink_vsi->veb == NULL) {
5805 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5807 if (uplink_vsi->veb == NULL) {
5808 PMD_DRV_LOG(ERR, "VEB setup failed");
5811 /* set ALLOWLOOPBACk on pf, when veb is created */
5812 i40e_enable_pf_lb(pf);
5815 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5816 pf->main_vsi->floating_veb == NULL) {
5817 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5819 if (pf->main_vsi->floating_veb == NULL) {
5820 PMD_DRV_LOG(ERR, "VEB setup failed");
5825 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5827 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5830 TAILQ_INIT(&vsi->mac_list);
5832 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5833 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5834 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5835 vsi->user_param = user_param;
5836 vsi->vlan_anti_spoof_on = 0;
5837 vsi->vlan_filter_on = 0;
5838 /* Allocate queues */
5839 switch (vsi->type) {
5840 case I40E_VSI_MAIN :
5841 vsi->nb_qps = pf->lan_nb_qps;
5843 case I40E_VSI_SRIOV :
5844 vsi->nb_qps = pf->vf_nb_qps;
5846 case I40E_VSI_VMDQ2:
5847 vsi->nb_qps = pf->vmdq_nb_qps;
5850 vsi->nb_qps = pf->fdir_nb_qps;
5856 * The filter status descriptor is reported in rx queue 0,
5857 * while the tx queue for fdir filter programming has no
5858 * such constraints, can be non-zero queues.
5859 * To simplify it, choose FDIR vsi use queue 0 pair.
5860 * To make sure it will use queue 0 pair, queue allocation
5861 * need be done before this function is called
5863 if (type != I40E_VSI_FDIR) {
5864 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5866 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5870 vsi->base_queue = ret;
5872 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5874 /* VF has MSIX interrupt in VF range, don't allocate here */
5875 if (type == I40E_VSI_MAIN) {
5876 if (pf->support_multi_driver) {
5877 /* If support multi-driver, need to use INT0 instead of
5878 * allocating from msix pool. The Msix pool is init from
5879 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5880 * to 1 without calling i40e_res_pool_alloc.
5885 ret = i40e_res_pool_alloc(&pf->msix_pool,
5886 RTE_MIN(vsi->nb_qps,
5887 RTE_MAX_RXTX_INTR_VEC_ID));
5890 "VSI MAIN %d get heap failed %d",
5892 goto fail_queue_alloc;
5894 vsi->msix_intr = ret;
5895 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5896 RTE_MAX_RXTX_INTR_VEC_ID);
5898 } else if (type != I40E_VSI_SRIOV) {
5899 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5901 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5902 if (type != I40E_VSI_FDIR)
5903 goto fail_queue_alloc;
5907 vsi->msix_intr = ret;
5916 if (type == I40E_VSI_MAIN) {
5917 /* For main VSI, no need to add since it's default one */
5918 vsi->uplink_seid = pf->mac_seid;
5919 vsi->seid = pf->main_vsi_seid;
5920 /* Bind queues with specific MSIX interrupt */
5922 * Needs 2 interrupt at least, one for misc cause which will
5923 * enabled from OS side, Another for queues binding the
5924 * interrupt from device side only.
5927 /* Get default VSI parameters from hardware */
5928 memset(&ctxt, 0, sizeof(ctxt));
5929 ctxt.seid = vsi->seid;
5930 ctxt.pf_num = hw->pf_id;
5931 ctxt.uplink_seid = vsi->uplink_seid;
5933 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5934 if (ret != I40E_SUCCESS) {
5935 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5936 goto fail_msix_alloc;
5938 rte_memcpy(&vsi->info, &ctxt.info,
5939 sizeof(struct i40e_aqc_vsi_properties_data));
5940 vsi->vsi_id = ctxt.vsi_number;
5941 vsi->info.valid_sections = 0;
5943 /* Configure tc, enabled TC0 only */
5944 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5946 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5947 goto fail_msix_alloc;
5950 /* TC, queue mapping */
5951 memset(&ctxt, 0, sizeof(ctxt));
5952 vsi->info.valid_sections |=
5953 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5954 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5955 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5956 rte_memcpy(&ctxt.info, &vsi->info,
5957 sizeof(struct i40e_aqc_vsi_properties_data));
5958 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5959 I40E_DEFAULT_TCMAP);
5960 if (ret != I40E_SUCCESS) {
5962 "Failed to configure TC queue mapping");
5963 goto fail_msix_alloc;
5965 ctxt.seid = vsi->seid;
5966 ctxt.pf_num = hw->pf_id;
5967 ctxt.uplink_seid = vsi->uplink_seid;
5970 /* Update VSI parameters */
5971 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5972 if (ret != I40E_SUCCESS) {
5973 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5974 goto fail_msix_alloc;
5977 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5978 sizeof(vsi->info.tc_mapping));
5979 rte_memcpy(&vsi->info.queue_mapping,
5980 &ctxt.info.queue_mapping,
5981 sizeof(vsi->info.queue_mapping));
5982 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5983 vsi->info.valid_sections = 0;
5985 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5989 * Updating default filter settings are necessary to prevent
5990 * reception of tagged packets.
5991 * Some old firmware configurations load a default macvlan
5992 * filter which accepts both tagged and untagged packets.
5993 * The updating is to use a normal filter instead if needed.
5994 * For NVM 4.2.2 or after, the updating is not needed anymore.
5995 * The firmware with correct configurations load the default
5996 * macvlan filter which is expected and cannot be removed.
5998 i40e_update_default_filter_setting(vsi);
5999 i40e_config_qinq(hw, vsi);
6000 } else if (type == I40E_VSI_SRIOV) {
6001 memset(&ctxt, 0, sizeof(ctxt));
6003 * For other VSI, the uplink_seid equals to uplink VSI's
6004 * uplink_seid since they share same VEB
6006 if (uplink_vsi == NULL)
6007 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
6009 vsi->uplink_seid = uplink_vsi->uplink_seid;
6010 ctxt.pf_num = hw->pf_id;
6011 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
6012 ctxt.uplink_seid = vsi->uplink_seid;
6013 ctxt.connection_type = 0x1;
6014 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6016 /* Use the VEB configuration if FW >= v5.0 */
6017 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
6018 /* Configure switch ID */
6019 ctxt.info.valid_sections |=
6020 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6021 ctxt.info.switch_id =
6022 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6025 /* Configure port/vlan */
6026 ctxt.info.valid_sections |=
6027 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6028 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6029 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6030 hw->func_caps.enabled_tcmap);
6031 if (ret != I40E_SUCCESS) {
6033 "Failed to configure TC queue mapping");
6034 goto fail_msix_alloc;
6037 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
6038 ctxt.info.valid_sections |=
6039 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6041 * Since VSI is not created yet, only configure parameter,
6042 * will add vsi below.
6045 i40e_config_qinq(hw, vsi);
6046 } else if (type == I40E_VSI_VMDQ2) {
6047 memset(&ctxt, 0, sizeof(ctxt));
6049 * For other VSI, the uplink_seid equals to uplink VSI's
6050 * uplink_seid since they share same VEB
6052 vsi->uplink_seid = uplink_vsi->uplink_seid;
6053 ctxt.pf_num = hw->pf_id;
6055 ctxt.uplink_seid = vsi->uplink_seid;
6056 ctxt.connection_type = 0x1;
6057 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6059 ctxt.info.valid_sections |=
6060 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6061 /* user_param carries flag to enable loop back */
6063 ctxt.info.switch_id =
6064 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6065 ctxt.info.switch_id |=
6066 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6069 /* Configure port/vlan */
6070 ctxt.info.valid_sections |=
6071 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6072 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6073 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6074 I40E_DEFAULT_TCMAP);
6075 if (ret != I40E_SUCCESS) {
6077 "Failed to configure TC queue mapping");
6078 goto fail_msix_alloc;
6080 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6081 ctxt.info.valid_sections |=
6082 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6083 } else if (type == I40E_VSI_FDIR) {
6084 memset(&ctxt, 0, sizeof(ctxt));
6085 vsi->uplink_seid = uplink_vsi->uplink_seid;
6086 ctxt.pf_num = hw->pf_id;
6088 ctxt.uplink_seid = vsi->uplink_seid;
6089 ctxt.connection_type = 0x1; /* regular data port */
6090 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6091 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6092 I40E_DEFAULT_TCMAP);
6093 if (ret != I40E_SUCCESS) {
6095 "Failed to configure TC queue mapping.");
6096 goto fail_msix_alloc;
6098 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6099 ctxt.info.valid_sections |=
6100 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6102 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6103 goto fail_msix_alloc;
6106 if (vsi->type != I40E_VSI_MAIN) {
6107 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6108 if (ret != I40E_SUCCESS) {
6109 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6110 hw->aq.asq_last_status);
6111 goto fail_msix_alloc;
6113 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6114 vsi->info.valid_sections = 0;
6115 vsi->seid = ctxt.seid;
6116 vsi->vsi_id = ctxt.vsi_number;
6117 vsi->sib_vsi_list.vsi = vsi;
6118 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6119 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6120 &vsi->sib_vsi_list, list);
6122 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6123 &vsi->sib_vsi_list, list);
6127 /* MAC/VLAN configuration */
6128 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6129 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6131 ret = i40e_vsi_add_mac(vsi, &filter);
6132 if (ret != I40E_SUCCESS) {
6133 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6134 goto fail_msix_alloc;
6137 /* Get VSI BW information */
6138 i40e_vsi_get_bw_config(vsi);
6141 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6143 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6149 /* Configure vlan filter on or off */
6151 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6154 struct i40e_mac_filter *f;
6156 struct i40e_mac_filter_info *mac_filter;
6157 enum rte_mac_filter_type desired_filter;
6158 int ret = I40E_SUCCESS;
6161 /* Filter to match MAC and VLAN */
6162 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6164 /* Filter to match only MAC */
6165 desired_filter = RTE_MAC_PERFECT_MATCH;
6170 mac_filter = rte_zmalloc("mac_filter_info_data",
6171 num * sizeof(*mac_filter), 0);
6172 if (mac_filter == NULL) {
6173 PMD_DRV_LOG(ERR, "failed to allocate memory");
6174 return I40E_ERR_NO_MEMORY;
6179 /* Remove all existing mac */
6180 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6181 mac_filter[i] = f->mac_info;
6182 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6184 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6185 on ? "enable" : "disable");
6191 /* Override with new filter */
6192 for (i = 0; i < num; i++) {
6193 mac_filter[i].filter_type = desired_filter;
6194 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6196 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6197 on ? "enable" : "disable");
6203 rte_free(mac_filter);
6207 /* Configure vlan stripping on or off */
6209 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6211 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6212 struct i40e_vsi_context ctxt;
6214 int ret = I40E_SUCCESS;
6216 /* Check if it has been already on or off */
6217 if (vsi->info.valid_sections &
6218 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6220 if ((vsi->info.port_vlan_flags &
6221 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6222 return 0; /* already on */
6224 if ((vsi->info.port_vlan_flags &
6225 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6226 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6227 return 0; /* already off */
6232 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6234 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6235 vsi->info.valid_sections =
6236 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6237 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6238 vsi->info.port_vlan_flags |= vlan_flags;
6239 ctxt.seid = vsi->seid;
6240 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6241 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6243 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6244 on ? "enable" : "disable");
6250 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6252 struct rte_eth_dev_data *data = dev->data;
6256 /* Apply vlan offload setting */
6257 mask = ETH_VLAN_STRIP_MASK |
6258 ETH_QINQ_STRIP_MASK |
6259 ETH_VLAN_FILTER_MASK |
6260 ETH_VLAN_EXTEND_MASK;
6261 ret = i40e_vlan_offload_set(dev, mask);
6263 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6267 /* Apply pvid setting */
6268 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6269 data->dev_conf.txmode.hw_vlan_insert_pvid);
6271 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6277 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6279 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6281 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6285 i40e_update_flow_control(struct i40e_hw *hw)
6287 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6288 struct i40e_link_status link_status;
6289 uint32_t rxfc = 0, txfc = 0, reg;
6293 memset(&link_status, 0, sizeof(link_status));
6294 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6295 if (ret != I40E_SUCCESS) {
6296 PMD_DRV_LOG(ERR, "Failed to get link status information");
6297 goto write_reg; /* Disable flow control */
6300 an_info = hw->phy.link_info.an_info;
6301 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6302 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6303 ret = I40E_ERR_NOT_READY;
6304 goto write_reg; /* Disable flow control */
6307 * If link auto negotiation is enabled, flow control needs to
6308 * be configured according to it
6310 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6311 case I40E_LINK_PAUSE_RXTX:
6314 hw->fc.current_mode = I40E_FC_FULL;
6316 case I40E_AQ_LINK_PAUSE_RX:
6318 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6320 case I40E_AQ_LINK_PAUSE_TX:
6322 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6325 hw->fc.current_mode = I40E_FC_NONE;
6330 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6331 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6332 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6333 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6334 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6335 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6342 i40e_pf_setup(struct i40e_pf *pf)
6344 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6345 struct i40e_filter_control_settings settings;
6346 struct i40e_vsi *vsi;
6349 /* Clear all stats counters */
6350 pf->offset_loaded = FALSE;
6351 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6352 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6353 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6354 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6356 ret = i40e_pf_get_switch_config(pf);
6357 if (ret != I40E_SUCCESS) {
6358 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6362 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6364 PMD_INIT_LOG(WARNING,
6365 "failed to allocate switch domain for device %d", ret);
6367 if (pf->flags & I40E_FLAG_FDIR) {
6368 /* make queue allocated first, let FDIR use queue pair 0*/
6369 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6370 if (ret != I40E_FDIR_QUEUE_ID) {
6372 "queue allocation fails for FDIR: ret =%d",
6374 pf->flags &= ~I40E_FLAG_FDIR;
6377 /* main VSI setup */
6378 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6380 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6381 return I40E_ERR_NOT_READY;
6385 /* Configure filter control */
6386 memset(&settings, 0, sizeof(settings));
6387 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6388 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6389 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6390 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6392 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6393 hw->func_caps.rss_table_size);
6394 return I40E_ERR_PARAM;
6396 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6397 hw->func_caps.rss_table_size);
6398 pf->hash_lut_size = hw->func_caps.rss_table_size;
6400 /* Enable ethtype and macvlan filters */
6401 settings.enable_ethtype = TRUE;
6402 settings.enable_macvlan = TRUE;
6403 ret = i40e_set_filter_control(hw, &settings);
6405 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6408 /* Update flow control according to the auto negotiation */
6409 i40e_update_flow_control(hw);
6411 return I40E_SUCCESS;
6415 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6421 * Set or clear TX Queue Disable flags,
6422 * which is required by hardware.
6424 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6425 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6427 /* Wait until the request is finished */
6428 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6429 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6430 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6431 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6432 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6438 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6439 return I40E_SUCCESS; /* already on, skip next steps */
6441 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6442 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6444 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6445 return I40E_SUCCESS; /* already off, skip next steps */
6446 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6448 /* Write the register */
6449 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6450 /* Check the result */
6451 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6452 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6453 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6455 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6456 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6459 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6460 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6464 /* Check if it is timeout */
6465 if (j >= I40E_CHK_Q_ENA_COUNT) {
6466 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6467 (on ? "enable" : "disable"), q_idx);
6468 return I40E_ERR_TIMEOUT;
6471 return I40E_SUCCESS;
6475 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6480 /* Wait until the request is finished */
6481 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6482 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6483 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6484 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6485 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6490 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6491 return I40E_SUCCESS; /* Already on, skip next steps */
6492 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6494 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6495 return I40E_SUCCESS; /* Already off, skip next steps */
6496 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6499 /* Write the register */
6500 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6501 /* Check the result */
6502 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6503 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6504 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6506 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6507 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6510 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6511 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6516 /* Check if it is timeout */
6517 if (j >= I40E_CHK_Q_ENA_COUNT) {
6518 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6519 (on ? "enable" : "disable"), q_idx);
6520 return I40E_ERR_TIMEOUT;
6523 return I40E_SUCCESS;
6526 /* Initialize VSI for TX */
6528 i40e_dev_tx_init(struct i40e_pf *pf)
6530 struct rte_eth_dev_data *data = pf->dev_data;
6532 uint32_t ret = I40E_SUCCESS;
6533 struct i40e_tx_queue *txq;
6535 for (i = 0; i < data->nb_tx_queues; i++) {
6536 txq = data->tx_queues[i];
6537 if (!txq || !txq->q_set)
6539 ret = i40e_tx_queue_init(txq);
6540 if (ret != I40E_SUCCESS)
6543 if (ret == I40E_SUCCESS)
6544 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6550 /* Initialize VSI for RX */
6552 i40e_dev_rx_init(struct i40e_pf *pf)
6554 struct rte_eth_dev_data *data = pf->dev_data;
6555 int ret = I40E_SUCCESS;
6557 struct i40e_rx_queue *rxq;
6559 i40e_pf_config_rss(pf);
6560 for (i = 0; i < data->nb_rx_queues; i++) {
6561 rxq = data->rx_queues[i];
6562 if (!rxq || !rxq->q_set)
6565 ret = i40e_rx_queue_init(rxq);
6566 if (ret != I40E_SUCCESS) {
6568 "Failed to do RX queue initialization");
6572 if (ret == I40E_SUCCESS)
6573 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6580 i40e_dev_rxtx_init(struct i40e_pf *pf)
6584 err = i40e_dev_tx_init(pf);
6586 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6589 err = i40e_dev_rx_init(pf);
6591 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6599 i40e_vmdq_setup(struct rte_eth_dev *dev)
6601 struct rte_eth_conf *conf = &dev->data->dev_conf;
6602 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6603 int i, err, conf_vsis, j, loop;
6604 struct i40e_vsi *vsi;
6605 struct i40e_vmdq_info *vmdq_info;
6606 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6607 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6610 * Disable interrupt to avoid message from VF. Furthermore, it will
6611 * avoid race condition in VSI creation/destroy.
6613 i40e_pf_disable_irq0(hw);
6615 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6616 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6620 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6621 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6622 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6623 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6624 pf->max_nb_vmdq_vsi);
6628 if (pf->vmdq != NULL) {
6629 PMD_INIT_LOG(INFO, "VMDQ already configured");
6633 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6634 sizeof(*vmdq_info) * conf_vsis, 0);
6636 if (pf->vmdq == NULL) {
6637 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6641 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6643 /* Create VMDQ VSI */
6644 for (i = 0; i < conf_vsis; i++) {
6645 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6646 vmdq_conf->enable_loop_back);
6648 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6652 vmdq_info = &pf->vmdq[i];
6654 vmdq_info->vsi = vsi;
6656 pf->nb_cfg_vmdq_vsi = conf_vsis;
6658 /* Configure Vlan */
6659 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6660 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6661 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6662 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6663 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6664 vmdq_conf->pool_map[i].vlan_id, j);
6666 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6667 vmdq_conf->pool_map[i].vlan_id);
6669 PMD_INIT_LOG(ERR, "Failed to add vlan");
6677 i40e_pf_enable_irq0(hw);
6682 for (i = 0; i < conf_vsis; i++)
6683 if (pf->vmdq[i].vsi == NULL)
6686 i40e_vsi_release(pf->vmdq[i].vsi);
6690 i40e_pf_enable_irq0(hw);
6695 i40e_stat_update_32(struct i40e_hw *hw,
6703 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6707 if (new_data >= *offset)
6708 *stat = (uint64_t)(new_data - *offset);
6710 *stat = (uint64_t)((new_data +
6711 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6715 i40e_stat_update_48(struct i40e_hw *hw,
6724 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6725 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6726 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6731 if (new_data >= *offset)
6732 *stat = new_data - *offset;
6734 *stat = (uint64_t)((new_data +
6735 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6737 *stat &= I40E_48_BIT_MASK;
6742 i40e_pf_disable_irq0(struct i40e_hw *hw)
6744 /* Disable all interrupt types */
6745 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6746 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6747 I40E_WRITE_FLUSH(hw);
6752 i40e_pf_enable_irq0(struct i40e_hw *hw)
6754 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6755 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6756 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6757 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6758 I40E_WRITE_FLUSH(hw);
6762 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6764 /* read pending request and disable first */
6765 i40e_pf_disable_irq0(hw);
6766 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6767 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6768 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6771 /* Link no queues with irq0 */
6772 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6773 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6777 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6779 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6783 uint32_t index, offset, val;
6788 * Try to find which VF trigger a reset, use absolute VF id to access
6789 * since the reg is global register.
6791 for (i = 0; i < pf->vf_num; i++) {
6792 abs_vf_id = hw->func_caps.vf_base_id + i;
6793 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6794 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6795 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6796 /* VFR event occurred */
6797 if (val & (0x1 << offset)) {
6800 /* Clear the event first */
6801 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6803 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6805 * Only notify a VF reset event occurred,
6806 * don't trigger another SW reset
6808 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6809 if (ret != I40E_SUCCESS)
6810 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6816 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6818 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6821 for (i = 0; i < pf->vf_num; i++)
6822 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6826 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6829 struct i40e_arq_event_info info;
6830 uint16_t pending, opcode;
6833 info.buf_len = I40E_AQ_BUF_SZ;
6834 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6835 if (!info.msg_buf) {
6836 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6842 ret = i40e_clean_arq_element(hw, &info, &pending);
6844 if (ret != I40E_SUCCESS) {
6846 "Failed to read msg from AdminQ, aq_err: %u",
6847 hw->aq.asq_last_status);
6850 opcode = rte_le_to_cpu_16(info.desc.opcode);
6853 case i40e_aqc_opc_send_msg_to_pf:
6854 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6855 i40e_pf_host_handle_vf_msg(dev,
6856 rte_le_to_cpu_16(info.desc.retval),
6857 rte_le_to_cpu_32(info.desc.cookie_high),
6858 rte_le_to_cpu_32(info.desc.cookie_low),
6862 case i40e_aqc_opc_get_link_status:
6863 ret = i40e_dev_link_update(dev, 0);
6865 rte_eth_dev_callback_process(dev,
6866 RTE_ETH_EVENT_INTR_LSC, NULL);
6869 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6874 rte_free(info.msg_buf);
6878 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6880 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6881 #define I40E_MDD_CLEAR16 0xFFFF
6882 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6884 bool mdd_detected = false;
6885 struct i40e_pf_vf *vf;
6889 /* find what triggered the MDD event */
6890 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6891 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6892 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6893 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6894 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6895 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6896 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6897 I40E_GL_MDET_TX_EVENT_SHIFT;
6898 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6899 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6900 hw->func_caps.base_queue;
6901 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6902 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6903 event, queue, pf_num, vf_num, dev->data->name);
6904 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6905 mdd_detected = true;
6907 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6908 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6909 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6910 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6911 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6912 I40E_GL_MDET_RX_EVENT_SHIFT;
6913 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6914 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6915 hw->func_caps.base_queue;
6917 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6918 "queue %d of function 0x%02x device %s\n",
6919 event, queue, func, dev->data->name);
6920 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6921 mdd_detected = true;
6925 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6926 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6927 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6928 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6930 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6931 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6932 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6934 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6938 /* see if one of the VFs needs its hand slapped */
6939 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6941 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6942 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6943 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6945 vf->num_mdd_events++;
6946 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6948 i, vf->num_mdd_events);
6951 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6952 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6953 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6955 vf->num_mdd_events++;
6956 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6958 i, vf->num_mdd_events);
6964 * Interrupt handler triggered by NIC for handling
6965 * specific interrupt.
6968 * Pointer to interrupt handle.
6970 * The address of parameter (struct rte_eth_dev *) regsitered before.
6976 i40e_dev_interrupt_handler(void *param)
6978 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6979 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6982 /* Disable interrupt */
6983 i40e_pf_disable_irq0(hw);
6985 /* read out interrupt causes */
6986 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6988 /* No interrupt event indicated */
6989 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6990 PMD_DRV_LOG(INFO, "No interrupt event");
6993 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6994 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6995 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6996 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6997 i40e_handle_mdd_event(dev);
6999 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7000 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7001 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7002 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7003 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7004 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7005 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7006 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7007 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7008 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7010 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7011 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7012 i40e_dev_handle_vfr_event(dev);
7014 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7015 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7016 i40e_dev_handle_aq_msg(dev);
7020 /* Enable interrupt */
7021 i40e_pf_enable_irq0(hw);
7025 i40e_dev_alarm_handler(void *param)
7027 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7028 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7031 /* Disable interrupt */
7032 i40e_pf_disable_irq0(hw);
7034 /* read out interrupt causes */
7035 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
7037 /* No interrupt event indicated */
7038 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
7040 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
7041 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
7042 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
7043 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
7044 i40e_handle_mdd_event(dev);
7046 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7047 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7048 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7049 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7050 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7051 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7052 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7053 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7054 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7055 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7057 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7058 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7059 i40e_dev_handle_vfr_event(dev);
7061 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7062 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7063 i40e_dev_handle_aq_msg(dev);
7067 /* Enable interrupt */
7068 i40e_pf_enable_irq0(hw);
7069 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7070 i40e_dev_alarm_handler, dev);
7074 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7075 struct i40e_macvlan_filter *filter,
7078 int ele_num, ele_buff_size;
7079 int num, actual_num, i;
7081 int ret = I40E_SUCCESS;
7082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7083 struct i40e_aqc_add_macvlan_element_data *req_list;
7085 if (filter == NULL || total == 0)
7086 return I40E_ERR_PARAM;
7087 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7088 ele_buff_size = hw->aq.asq_buf_size;
7090 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7091 if (req_list == NULL) {
7092 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7093 return I40E_ERR_NO_MEMORY;
7098 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7099 memset(req_list, 0, ele_buff_size);
7101 for (i = 0; i < actual_num; i++) {
7102 rte_memcpy(req_list[i].mac_addr,
7103 &filter[num + i].macaddr, ETH_ADDR_LEN);
7104 req_list[i].vlan_tag =
7105 rte_cpu_to_le_16(filter[num + i].vlan_id);
7107 switch (filter[num + i].filter_type) {
7108 case RTE_MAC_PERFECT_MATCH:
7109 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7110 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7112 case RTE_MACVLAN_PERFECT_MATCH:
7113 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7115 case RTE_MAC_HASH_MATCH:
7116 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7117 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7119 case RTE_MACVLAN_HASH_MATCH:
7120 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7123 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7124 ret = I40E_ERR_PARAM;
7128 req_list[i].queue_number = 0;
7130 req_list[i].flags = rte_cpu_to_le_16(flags);
7133 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7135 if (ret != I40E_SUCCESS) {
7136 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7140 } while (num < total);
7148 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7149 struct i40e_macvlan_filter *filter,
7152 int ele_num, ele_buff_size;
7153 int num, actual_num, i;
7155 int ret = I40E_SUCCESS;
7156 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7157 struct i40e_aqc_remove_macvlan_element_data *req_list;
7159 if (filter == NULL || total == 0)
7160 return I40E_ERR_PARAM;
7162 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7163 ele_buff_size = hw->aq.asq_buf_size;
7165 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7166 if (req_list == NULL) {
7167 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7168 return I40E_ERR_NO_MEMORY;
7173 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7174 memset(req_list, 0, ele_buff_size);
7176 for (i = 0; i < actual_num; i++) {
7177 rte_memcpy(req_list[i].mac_addr,
7178 &filter[num + i].macaddr, ETH_ADDR_LEN);
7179 req_list[i].vlan_tag =
7180 rte_cpu_to_le_16(filter[num + i].vlan_id);
7182 switch (filter[num + i].filter_type) {
7183 case RTE_MAC_PERFECT_MATCH:
7184 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7185 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7187 case RTE_MACVLAN_PERFECT_MATCH:
7188 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7190 case RTE_MAC_HASH_MATCH:
7191 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7192 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7194 case RTE_MACVLAN_HASH_MATCH:
7195 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7198 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7199 ret = I40E_ERR_PARAM;
7202 req_list[i].flags = rte_cpu_to_le_16(flags);
7205 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7207 if (ret != I40E_SUCCESS) {
7208 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7212 } while (num < total);
7219 /* Find out specific MAC filter */
7220 static struct i40e_mac_filter *
7221 i40e_find_mac_filter(struct i40e_vsi *vsi,
7222 struct rte_ether_addr *macaddr)
7224 struct i40e_mac_filter *f;
7226 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7227 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7235 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7238 uint32_t vid_idx, vid_bit;
7240 if (vlan_id > ETH_VLAN_ID_MAX)
7243 vid_idx = I40E_VFTA_IDX(vlan_id);
7244 vid_bit = I40E_VFTA_BIT(vlan_id);
7246 if (vsi->vfta[vid_idx] & vid_bit)
7253 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7254 uint16_t vlan_id, bool on)
7256 uint32_t vid_idx, vid_bit;
7258 vid_idx = I40E_VFTA_IDX(vlan_id);
7259 vid_bit = I40E_VFTA_BIT(vlan_id);
7262 vsi->vfta[vid_idx] |= vid_bit;
7264 vsi->vfta[vid_idx] &= ~vid_bit;
7268 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7269 uint16_t vlan_id, bool on)
7271 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7272 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7275 if (vlan_id > ETH_VLAN_ID_MAX)
7278 i40e_store_vlan_filter(vsi, vlan_id, on);
7280 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7283 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7286 ret = i40e_aq_add_vlan(hw, vsi->seid,
7287 &vlan_data, 1, NULL);
7288 if (ret != I40E_SUCCESS)
7289 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7291 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7292 &vlan_data, 1, NULL);
7293 if (ret != I40E_SUCCESS)
7295 "Failed to remove vlan filter");
7300 * Find all vlan options for specific mac addr,
7301 * return with actual vlan found.
7304 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7305 struct i40e_macvlan_filter *mv_f,
7306 int num, struct rte_ether_addr *addr)
7312 * Not to use i40e_find_vlan_filter to decrease the loop time,
7313 * although the code looks complex.
7315 if (num < vsi->vlan_num)
7316 return I40E_ERR_PARAM;
7319 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7321 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7322 if (vsi->vfta[j] & (1 << k)) {
7325 "vlan number doesn't match");
7326 return I40E_ERR_PARAM;
7328 rte_memcpy(&mv_f[i].macaddr,
7329 addr, ETH_ADDR_LEN);
7331 j * I40E_UINT32_BIT_SIZE + k;
7337 return I40E_SUCCESS;
7341 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7342 struct i40e_macvlan_filter *mv_f,
7347 struct i40e_mac_filter *f;
7349 if (num < vsi->mac_num)
7350 return I40E_ERR_PARAM;
7352 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7354 PMD_DRV_LOG(ERR, "buffer number not match");
7355 return I40E_ERR_PARAM;
7357 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7359 mv_f[i].vlan_id = vlan;
7360 mv_f[i].filter_type = f->mac_info.filter_type;
7364 return I40E_SUCCESS;
7368 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7371 struct i40e_mac_filter *f;
7372 struct i40e_macvlan_filter *mv_f;
7373 int ret = I40E_SUCCESS;
7375 if (vsi == NULL || vsi->mac_num == 0)
7376 return I40E_ERR_PARAM;
7378 /* Case that no vlan is set */
7379 if (vsi->vlan_num == 0)
7382 num = vsi->mac_num * vsi->vlan_num;
7384 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7386 PMD_DRV_LOG(ERR, "failed to allocate memory");
7387 return I40E_ERR_NO_MEMORY;
7391 if (vsi->vlan_num == 0) {
7392 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7393 rte_memcpy(&mv_f[i].macaddr,
7394 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7395 mv_f[i].filter_type = f->mac_info.filter_type;
7396 mv_f[i].vlan_id = 0;
7400 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7401 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7402 vsi->vlan_num, &f->mac_info.mac_addr);
7403 if (ret != I40E_SUCCESS)
7405 for (j = i; j < i + vsi->vlan_num; j++)
7406 mv_f[j].filter_type = f->mac_info.filter_type;
7411 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7419 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7421 struct i40e_macvlan_filter *mv_f;
7423 int ret = I40E_SUCCESS;
7425 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7426 return I40E_ERR_PARAM;
7428 /* If it's already set, just return */
7429 if (i40e_find_vlan_filter(vsi,vlan))
7430 return I40E_SUCCESS;
7432 mac_num = vsi->mac_num;
7435 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7436 return I40E_ERR_PARAM;
7439 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7442 PMD_DRV_LOG(ERR, "failed to allocate memory");
7443 return I40E_ERR_NO_MEMORY;
7446 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7448 if (ret != I40E_SUCCESS)
7451 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7453 if (ret != I40E_SUCCESS)
7456 i40e_set_vlan_filter(vsi, vlan, 1);
7466 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7468 struct i40e_macvlan_filter *mv_f;
7470 int ret = I40E_SUCCESS;
7473 * Vlan 0 is the generic filter for untagged packets
7474 * and can't be removed.
7476 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7477 return I40E_ERR_PARAM;
7479 /* If can't find it, just return */
7480 if (!i40e_find_vlan_filter(vsi, vlan))
7481 return I40E_ERR_PARAM;
7483 mac_num = vsi->mac_num;
7486 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7487 return I40E_ERR_PARAM;
7490 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7493 PMD_DRV_LOG(ERR, "failed to allocate memory");
7494 return I40E_ERR_NO_MEMORY;
7497 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7499 if (ret != I40E_SUCCESS)
7502 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7504 if (ret != I40E_SUCCESS)
7507 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7508 if (vsi->vlan_num == 1) {
7509 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7510 if (ret != I40E_SUCCESS)
7513 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7514 if (ret != I40E_SUCCESS)
7518 i40e_set_vlan_filter(vsi, vlan, 0);
7528 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7530 struct i40e_mac_filter *f;
7531 struct i40e_macvlan_filter *mv_f;
7532 int i, vlan_num = 0;
7533 int ret = I40E_SUCCESS;
7535 /* If it's add and we've config it, return */
7536 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7538 return I40E_SUCCESS;
7539 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7540 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7543 * If vlan_num is 0, that's the first time to add mac,
7544 * set mask for vlan_id 0.
7546 if (vsi->vlan_num == 0) {
7547 i40e_set_vlan_filter(vsi, 0, 1);
7550 vlan_num = vsi->vlan_num;
7551 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7552 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7555 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7557 PMD_DRV_LOG(ERR, "failed to allocate memory");
7558 return I40E_ERR_NO_MEMORY;
7561 for (i = 0; i < vlan_num; i++) {
7562 mv_f[i].filter_type = mac_filter->filter_type;
7563 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7567 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7568 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7569 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7570 &mac_filter->mac_addr);
7571 if (ret != I40E_SUCCESS)
7575 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7576 if (ret != I40E_SUCCESS)
7579 /* Add the mac addr into mac list */
7580 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7582 PMD_DRV_LOG(ERR, "failed to allocate memory");
7583 ret = I40E_ERR_NO_MEMORY;
7586 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7588 f->mac_info.filter_type = mac_filter->filter_type;
7589 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7600 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7602 struct i40e_mac_filter *f;
7603 struct i40e_macvlan_filter *mv_f;
7605 enum rte_mac_filter_type filter_type;
7606 int ret = I40E_SUCCESS;
7608 /* Can't find it, return an error */
7609 f = i40e_find_mac_filter(vsi, addr);
7611 return I40E_ERR_PARAM;
7613 vlan_num = vsi->vlan_num;
7614 filter_type = f->mac_info.filter_type;
7615 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7616 filter_type == RTE_MACVLAN_HASH_MATCH) {
7617 if (vlan_num == 0) {
7618 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7619 return I40E_ERR_PARAM;
7621 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7622 filter_type == RTE_MAC_HASH_MATCH)
7625 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7627 PMD_DRV_LOG(ERR, "failed to allocate memory");
7628 return I40E_ERR_NO_MEMORY;
7631 for (i = 0; i < vlan_num; i++) {
7632 mv_f[i].filter_type = filter_type;
7633 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7636 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7637 filter_type == RTE_MACVLAN_HASH_MATCH) {
7638 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7639 if (ret != I40E_SUCCESS)
7643 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7644 if (ret != I40E_SUCCESS)
7647 /* Remove the mac addr into mac list */
7648 TAILQ_REMOVE(&vsi->mac_list, f, next);
7658 /* Configure hash enable flags for RSS */
7660 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7668 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7669 if (flags & (1ULL << i))
7670 hena |= adapter->pctypes_tbl[i];
7676 /* Parse the hash enable flags */
7678 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7680 uint64_t rss_hf = 0;
7686 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7687 if (flags & adapter->pctypes_tbl[i])
7688 rss_hf |= (1ULL << i);
7695 i40e_pf_disable_rss(struct i40e_pf *pf)
7697 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7699 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7700 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7701 I40E_WRITE_FLUSH(hw);
7705 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7707 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7708 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7709 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7710 I40E_VFQF_HKEY_MAX_INDEX :
7711 I40E_PFQF_HKEY_MAX_INDEX;
7714 if (!key || key_len == 0) {
7715 PMD_DRV_LOG(DEBUG, "No key to be configured");
7717 } else if (key_len != (key_idx + 1) *
7719 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7723 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7724 struct i40e_aqc_get_set_rss_key_data *key_dw =
7725 (struct i40e_aqc_get_set_rss_key_data *)key;
7727 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7729 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7731 uint32_t *hash_key = (uint32_t *)key;
7734 if (vsi->type == I40E_VSI_SRIOV) {
7735 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7738 I40E_VFQF_HKEY1(i, vsi->user_param),
7742 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7743 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7746 I40E_WRITE_FLUSH(hw);
7753 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7755 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7756 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7760 if (!key || !key_len)
7763 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7764 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7765 (struct i40e_aqc_get_set_rss_key_data *)key);
7767 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7771 uint32_t *key_dw = (uint32_t *)key;
7774 if (vsi->type == I40E_VSI_SRIOV) {
7775 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7776 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7777 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7779 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7782 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7783 reg = I40E_PFQF_HKEY(i);
7784 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7786 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7794 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7796 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7800 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7801 rss_conf->rss_key_len);
7805 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7806 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7807 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7808 I40E_WRITE_FLUSH(hw);
7814 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7815 struct rte_eth_rss_conf *rss_conf)
7817 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7819 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7822 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7823 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7825 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7826 if (rss_hf != 0) /* Enable RSS */
7828 return 0; /* Nothing to do */
7831 if (rss_hf == 0) /* Disable RSS */
7834 return i40e_hw_rss_hash_set(pf, rss_conf);
7838 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7839 struct rte_eth_rss_conf *rss_conf)
7841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7849 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7850 &rss_conf->rss_key_len);
7854 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7855 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7856 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7862 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7864 switch (filter_type) {
7865 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7866 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7868 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7869 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7871 case RTE_TUNNEL_FILTER_IMAC_TENID:
7872 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7874 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7875 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7877 case ETH_TUNNEL_FILTER_IMAC:
7878 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7880 case ETH_TUNNEL_FILTER_OIP:
7881 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7883 case ETH_TUNNEL_FILTER_IIP:
7884 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7887 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7894 /* Convert tunnel filter structure */
7896 i40e_tunnel_filter_convert(
7897 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7898 struct i40e_tunnel_filter *tunnel_filter)
7900 rte_ether_addr_copy((struct rte_ether_addr *)
7901 &cld_filter->element.outer_mac,
7902 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7903 rte_ether_addr_copy((struct rte_ether_addr *)
7904 &cld_filter->element.inner_mac,
7905 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7906 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7907 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7908 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7909 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7910 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7912 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7913 tunnel_filter->input.flags = cld_filter->element.flags;
7914 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7915 tunnel_filter->queue = cld_filter->element.queue_number;
7916 rte_memcpy(tunnel_filter->input.general_fields,
7917 cld_filter->general_fields,
7918 sizeof(cld_filter->general_fields));
7923 /* Check if there exists the tunnel filter */
7924 struct i40e_tunnel_filter *
7925 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7926 const struct i40e_tunnel_filter_input *input)
7930 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7934 return tunnel_rule->hash_map[ret];
7937 /* Add a tunnel filter into the SW list */
7939 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7940 struct i40e_tunnel_filter *tunnel_filter)
7942 struct i40e_tunnel_rule *rule = &pf->tunnel;
7945 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7948 "Failed to insert tunnel filter to hash table %d!",
7952 rule->hash_map[ret] = tunnel_filter;
7954 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7959 /* Delete a tunnel filter from the SW list */
7961 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7962 struct i40e_tunnel_filter_input *input)
7964 struct i40e_tunnel_rule *rule = &pf->tunnel;
7965 struct i40e_tunnel_filter *tunnel_filter;
7968 ret = rte_hash_del_key(rule->hash_table, input);
7971 "Failed to delete tunnel filter to hash table %d!",
7975 tunnel_filter = rule->hash_map[ret];
7976 rule->hash_map[ret] = NULL;
7978 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7979 rte_free(tunnel_filter);
7985 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7986 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7990 uint32_t ipv4_addr, ipv4_addr_le;
7991 uint8_t i, tun_type = 0;
7992 /* internal varialbe to convert ipv6 byte order */
7993 uint32_t convert_ipv6[4];
7995 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7996 struct i40e_vsi *vsi = pf->main_vsi;
7997 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7998 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7999 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8000 struct i40e_tunnel_filter *tunnel, *node;
8001 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8003 cld_filter = rte_zmalloc("tunnel_filter",
8004 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8007 if (NULL == cld_filter) {
8008 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8011 pfilter = cld_filter;
8013 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8014 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8015 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8016 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8018 pfilter->element.inner_vlan =
8019 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8020 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
8021 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8022 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8023 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8024 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8026 sizeof(pfilter->element.ipaddr.v4.data));
8028 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8029 for (i = 0; i < 4; i++) {
8031 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
8033 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8035 sizeof(pfilter->element.ipaddr.v6.data));
8038 /* check tunneled type */
8039 switch (tunnel_filter->tunnel_type) {
8040 case RTE_TUNNEL_TYPE_VXLAN:
8041 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8043 case RTE_TUNNEL_TYPE_NVGRE:
8044 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8046 case RTE_TUNNEL_TYPE_IP_IN_GRE:
8047 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8049 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8050 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
8053 /* Other tunnel types is not supported. */
8054 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8055 rte_free(cld_filter);
8059 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8060 &pfilter->element.flags);
8062 rte_free(cld_filter);
8066 pfilter->element.flags |= rte_cpu_to_le_16(
8067 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8068 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8069 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8070 pfilter->element.queue_number =
8071 rte_cpu_to_le_16(tunnel_filter->queue_id);
8073 /* Check if there is the filter in SW list */
8074 memset(&check_filter, 0, sizeof(check_filter));
8075 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8076 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8078 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8079 rte_free(cld_filter);
8083 if (!add && !node) {
8084 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8085 rte_free(cld_filter);
8090 ret = i40e_aq_add_cloud_filters(hw,
8091 vsi->seid, &cld_filter->element, 1);
8093 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8094 rte_free(cld_filter);
8097 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8098 if (tunnel == NULL) {
8099 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8100 rte_free(cld_filter);
8104 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8105 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8109 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8110 &cld_filter->element, 1);
8112 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8113 rte_free(cld_filter);
8116 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8119 rte_free(cld_filter);
8123 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8124 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
8125 #define I40E_TR_GENEVE_KEY_MASK 0x8
8126 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
8127 #define I40E_TR_GRE_KEY_MASK 0x400
8128 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
8129 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
8130 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8131 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8132 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8133 #define I40E_DIRECTION_INGRESS_KEY 0x8000
8134 #define I40E_TR_L4_TYPE_TCP 0x2
8135 #define I40E_TR_L4_TYPE_UDP 0x4
8136 #define I40E_TR_L4_TYPE_SCTP 0x8
8139 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8141 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8142 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8143 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8144 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8145 enum i40e_status_code status = I40E_SUCCESS;
8147 if (pf->support_multi_driver) {
8148 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8149 return I40E_NOT_SUPPORTED;
8152 memset(&filter_replace, 0,
8153 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8154 memset(&filter_replace_buf, 0,
8155 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8157 /* create L1 filter */
8158 filter_replace.old_filter_type =
8159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8160 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8161 filter_replace.tr_bit = 0;
8163 /* Prepare the buffer, 3 entries */
8164 filter_replace_buf.data[0] =
8165 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8166 filter_replace_buf.data[0] |=
8167 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8168 filter_replace_buf.data[2] = 0xFF;
8169 filter_replace_buf.data[3] = 0xFF;
8170 filter_replace_buf.data[4] =
8171 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8172 filter_replace_buf.data[4] |=
8173 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8174 filter_replace_buf.data[7] = 0xF0;
8175 filter_replace_buf.data[8]
8176 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8177 filter_replace_buf.data[8] |=
8178 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8179 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8180 I40E_TR_GENEVE_KEY_MASK |
8181 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8182 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8183 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8184 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8186 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8187 &filter_replace_buf);
8188 if (!status && (filter_replace.old_filter_type !=
8189 filter_replace.new_filter_type))
8190 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8191 " original: 0x%x, new: 0x%x",
8193 filter_replace.old_filter_type,
8194 filter_replace.new_filter_type);
8200 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8202 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8203 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8204 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8205 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8206 enum i40e_status_code status = I40E_SUCCESS;
8208 if (pf->support_multi_driver) {
8209 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8210 return I40E_NOT_SUPPORTED;
8214 memset(&filter_replace, 0,
8215 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8216 memset(&filter_replace_buf, 0,
8217 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8218 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8219 I40E_AQC_MIRROR_CLOUD_FILTER;
8220 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8221 filter_replace.new_filter_type =
8222 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8223 /* Prepare the buffer, 2 entries */
8224 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8225 filter_replace_buf.data[0] |=
8226 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8227 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8228 filter_replace_buf.data[4] |=
8229 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8230 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8231 &filter_replace_buf);
8234 if (filter_replace.old_filter_type !=
8235 filter_replace.new_filter_type)
8236 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8237 " original: 0x%x, new: 0x%x",
8239 filter_replace.old_filter_type,
8240 filter_replace.new_filter_type);
8243 memset(&filter_replace, 0,
8244 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8245 memset(&filter_replace_buf, 0,
8246 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8248 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8249 I40E_AQC_MIRROR_CLOUD_FILTER;
8250 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8251 filter_replace.new_filter_type =
8252 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8253 /* Prepare the buffer, 2 entries */
8254 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8255 filter_replace_buf.data[0] |=
8256 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8257 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8258 filter_replace_buf.data[4] |=
8259 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8261 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8262 &filter_replace_buf);
8263 if (!status && (filter_replace.old_filter_type !=
8264 filter_replace.new_filter_type))
8265 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8266 " original: 0x%x, new: 0x%x",
8268 filter_replace.old_filter_type,
8269 filter_replace.new_filter_type);
8274 static enum i40e_status_code
8275 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8277 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8278 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8279 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8280 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8281 enum i40e_status_code status = I40E_SUCCESS;
8283 if (pf->support_multi_driver) {
8284 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8285 return I40E_NOT_SUPPORTED;
8289 memset(&filter_replace, 0,
8290 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8291 memset(&filter_replace_buf, 0,
8292 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8293 /* create L1 filter */
8294 filter_replace.old_filter_type =
8295 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8296 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8297 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8298 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8299 /* Prepare the buffer, 2 entries */
8300 filter_replace_buf.data[0] =
8301 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8302 filter_replace_buf.data[0] |=
8303 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8304 filter_replace_buf.data[2] = 0xFF;
8305 filter_replace_buf.data[3] = 0xFF;
8306 filter_replace_buf.data[4] =
8307 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8308 filter_replace_buf.data[4] |=
8309 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8310 filter_replace_buf.data[6] = 0xFF;
8311 filter_replace_buf.data[7] = 0xFF;
8312 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8313 &filter_replace_buf);
8316 if (filter_replace.old_filter_type !=
8317 filter_replace.new_filter_type)
8318 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8319 " original: 0x%x, new: 0x%x",
8321 filter_replace.old_filter_type,
8322 filter_replace.new_filter_type);
8325 memset(&filter_replace, 0,
8326 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8327 memset(&filter_replace_buf, 0,
8328 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8329 /* create L1 filter */
8330 filter_replace.old_filter_type =
8331 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8332 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8333 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8334 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8335 /* Prepare the buffer, 2 entries */
8336 filter_replace_buf.data[0] =
8337 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8338 filter_replace_buf.data[0] |=
8339 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8340 filter_replace_buf.data[2] = 0xFF;
8341 filter_replace_buf.data[3] = 0xFF;
8342 filter_replace_buf.data[4] =
8343 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8344 filter_replace_buf.data[4] |=
8345 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8346 filter_replace_buf.data[6] = 0xFF;
8347 filter_replace_buf.data[7] = 0xFF;
8349 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8350 &filter_replace_buf);
8351 if (!status && (filter_replace.old_filter_type !=
8352 filter_replace.new_filter_type))
8353 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8354 " original: 0x%x, new: 0x%x",
8356 filter_replace.old_filter_type,
8357 filter_replace.new_filter_type);
8363 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8365 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8366 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8367 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8368 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8369 enum i40e_status_code status = I40E_SUCCESS;
8371 if (pf->support_multi_driver) {
8372 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8373 return I40E_NOT_SUPPORTED;
8377 memset(&filter_replace, 0,
8378 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8379 memset(&filter_replace_buf, 0,
8380 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8381 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8382 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8383 filter_replace.new_filter_type =
8384 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8385 /* Prepare the buffer, 2 entries */
8386 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8387 filter_replace_buf.data[0] |=
8388 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8389 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8390 filter_replace_buf.data[4] |=
8391 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8392 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8393 &filter_replace_buf);
8396 if (filter_replace.old_filter_type !=
8397 filter_replace.new_filter_type)
8398 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8399 " original: 0x%x, new: 0x%x",
8401 filter_replace.old_filter_type,
8402 filter_replace.new_filter_type);
8405 memset(&filter_replace, 0,
8406 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8407 memset(&filter_replace_buf, 0,
8408 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8409 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8410 filter_replace.old_filter_type =
8411 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8412 filter_replace.new_filter_type =
8413 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8414 /* Prepare the buffer, 2 entries */
8415 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8416 filter_replace_buf.data[0] |=
8417 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8418 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8419 filter_replace_buf.data[4] |=
8420 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8422 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8423 &filter_replace_buf);
8424 if (!status && (filter_replace.old_filter_type !=
8425 filter_replace.new_filter_type))
8426 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8427 " original: 0x%x, new: 0x%x",
8429 filter_replace.old_filter_type,
8430 filter_replace.new_filter_type);
8435 static enum i40e_status_code
8436 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8437 enum i40e_l4_port_type l4_port_type)
8439 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8440 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8441 enum i40e_status_code status = I40E_SUCCESS;
8442 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8443 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8445 if (pf->support_multi_driver) {
8446 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8447 return I40E_NOT_SUPPORTED;
8450 memset(&filter_replace, 0,
8451 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8452 memset(&filter_replace_buf, 0,
8453 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8455 /* create L1 filter */
8456 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8457 filter_replace.old_filter_type =
8458 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8459 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8460 filter_replace_buf.data[8] =
8461 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8463 filter_replace.old_filter_type =
8464 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8465 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8466 filter_replace_buf.data[8] =
8467 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8470 filter_replace.tr_bit = 0;
8471 /* Prepare the buffer, 3 entries */
8472 filter_replace_buf.data[0] =
8473 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8474 filter_replace_buf.data[0] |=
8475 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8476 filter_replace_buf.data[2] = 0x00;
8477 filter_replace_buf.data[3] =
8478 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8479 filter_replace_buf.data[4] =
8480 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8481 filter_replace_buf.data[4] |=
8482 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8483 filter_replace_buf.data[5] = 0x00;
8484 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8485 I40E_TR_L4_TYPE_TCP |
8486 I40E_TR_L4_TYPE_SCTP;
8487 filter_replace_buf.data[7] = 0x00;
8488 filter_replace_buf.data[8] |=
8489 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8490 filter_replace_buf.data[9] = 0x00;
8491 filter_replace_buf.data[10] = 0xFF;
8492 filter_replace_buf.data[11] = 0xFF;
8494 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8495 &filter_replace_buf);
8496 if (!status && filter_replace.old_filter_type !=
8497 filter_replace.new_filter_type)
8498 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8499 " original: 0x%x, new: 0x%x",
8501 filter_replace.old_filter_type,
8502 filter_replace.new_filter_type);
8507 static enum i40e_status_code
8508 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8509 enum i40e_l4_port_type l4_port_type)
8511 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8512 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8513 enum i40e_status_code status = I40E_SUCCESS;
8514 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8515 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8517 if (pf->support_multi_driver) {
8518 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8519 return I40E_NOT_SUPPORTED;
8522 memset(&filter_replace, 0,
8523 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8524 memset(&filter_replace_buf, 0,
8525 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8527 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8528 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8529 filter_replace.new_filter_type =
8530 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8531 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8533 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8534 filter_replace.new_filter_type =
8535 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8536 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8539 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8540 filter_replace.tr_bit = 0;
8541 /* Prepare the buffer, 2 entries */
8542 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8543 filter_replace_buf.data[0] |=
8544 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8545 filter_replace_buf.data[4] |=
8546 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8547 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8548 &filter_replace_buf);
8550 if (!status && filter_replace.old_filter_type !=
8551 filter_replace.new_filter_type)
8552 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8553 " original: 0x%x, new: 0x%x",
8555 filter_replace.old_filter_type,
8556 filter_replace.new_filter_type);
8562 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8563 struct i40e_tunnel_filter_conf *tunnel_filter,
8567 uint32_t ipv4_addr, ipv4_addr_le;
8568 uint8_t i, tun_type = 0;
8569 /* internal variable to convert ipv6 byte order */
8570 uint32_t convert_ipv6[4];
8572 struct i40e_pf_vf *vf = NULL;
8573 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8574 struct i40e_vsi *vsi;
8575 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8576 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8577 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8578 struct i40e_tunnel_filter *tunnel, *node;
8579 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8581 bool big_buffer = 0;
8583 cld_filter = rte_zmalloc("tunnel_filter",
8584 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8587 if (cld_filter == NULL) {
8588 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8591 pfilter = cld_filter;
8593 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8594 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8595 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8596 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8598 pfilter->element.inner_vlan =
8599 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8600 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8601 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8602 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8603 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8604 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8606 sizeof(pfilter->element.ipaddr.v4.data));
8608 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8609 for (i = 0; i < 4; i++) {
8611 rte_cpu_to_le_32(rte_be_to_cpu_32(
8612 tunnel_filter->ip_addr.ipv6_addr[i]));
8614 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8616 sizeof(pfilter->element.ipaddr.v6.data));
8619 /* check tunneled type */
8620 switch (tunnel_filter->tunnel_type) {
8621 case I40E_TUNNEL_TYPE_VXLAN:
8622 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8624 case I40E_TUNNEL_TYPE_NVGRE:
8625 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8627 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8628 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8630 case I40E_TUNNEL_TYPE_MPLSoUDP:
8631 if (!pf->mpls_replace_flag) {
8632 i40e_replace_mpls_l1_filter(pf);
8633 i40e_replace_mpls_cloud_filter(pf);
8634 pf->mpls_replace_flag = 1;
8636 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8637 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8639 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8640 (teid_le & 0xF) << 12;
8641 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8644 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8646 case I40E_TUNNEL_TYPE_MPLSoGRE:
8647 if (!pf->mpls_replace_flag) {
8648 i40e_replace_mpls_l1_filter(pf);
8649 i40e_replace_mpls_cloud_filter(pf);
8650 pf->mpls_replace_flag = 1;
8652 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8653 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8655 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8656 (teid_le & 0xF) << 12;
8657 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8660 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8662 case I40E_TUNNEL_TYPE_GTPC:
8663 if (!pf->gtp_replace_flag) {
8664 i40e_replace_gtp_l1_filter(pf);
8665 i40e_replace_gtp_cloud_filter(pf);
8666 pf->gtp_replace_flag = 1;
8668 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8669 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8670 (teid_le >> 16) & 0xFFFF;
8671 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8673 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8677 case I40E_TUNNEL_TYPE_GTPU:
8678 if (!pf->gtp_replace_flag) {
8679 i40e_replace_gtp_l1_filter(pf);
8680 i40e_replace_gtp_cloud_filter(pf);
8681 pf->gtp_replace_flag = 1;
8683 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8684 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8685 (teid_le >> 16) & 0xFFFF;
8686 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8688 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8692 case I40E_TUNNEL_TYPE_QINQ:
8693 if (!pf->qinq_replace_flag) {
8694 ret = i40e_cloud_filter_qinq_create(pf);
8697 "QinQ tunnel filter already created.");
8698 pf->qinq_replace_flag = 1;
8700 /* Add in the General fields the values of
8701 * the Outer and Inner VLAN
8702 * Big Buffer should be set, see changes in
8703 * i40e_aq_add_cloud_filters
8705 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8706 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8709 case I40E_CLOUD_TYPE_UDP:
8710 case I40E_CLOUD_TYPE_TCP:
8711 case I40E_CLOUD_TYPE_SCTP:
8712 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8713 if (!pf->sport_replace_flag) {
8714 i40e_replace_port_l1_filter(pf,
8715 tunnel_filter->l4_port_type);
8716 i40e_replace_port_cloud_filter(pf,
8717 tunnel_filter->l4_port_type);
8718 pf->sport_replace_flag = 1;
8720 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8721 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8722 I40E_DIRECTION_INGRESS_KEY;
8724 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8725 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8726 I40E_TR_L4_TYPE_UDP;
8727 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8728 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8729 I40E_TR_L4_TYPE_TCP;
8731 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8732 I40E_TR_L4_TYPE_SCTP;
8734 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8735 (teid_le >> 16) & 0xFFFF;
8738 if (!pf->dport_replace_flag) {
8739 i40e_replace_port_l1_filter(pf,
8740 tunnel_filter->l4_port_type);
8741 i40e_replace_port_cloud_filter(pf,
8742 tunnel_filter->l4_port_type);
8743 pf->dport_replace_flag = 1;
8745 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8746 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8747 I40E_DIRECTION_INGRESS_KEY;
8749 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8750 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8751 I40E_TR_L4_TYPE_UDP;
8752 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8753 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8754 I40E_TR_L4_TYPE_TCP;
8756 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8757 I40E_TR_L4_TYPE_SCTP;
8759 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8760 (teid_le >> 16) & 0xFFFF;
8766 /* Other tunnel types is not supported. */
8767 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8768 rte_free(cld_filter);
8772 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8773 pfilter->element.flags =
8774 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8775 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8776 pfilter->element.flags =
8777 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8778 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8779 pfilter->element.flags =
8780 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8781 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8782 pfilter->element.flags =
8783 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8784 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8785 pfilter->element.flags |=
8786 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8787 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8788 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8789 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8790 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8791 pfilter->element.flags |=
8792 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8794 pfilter->element.flags |=
8795 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8797 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8798 &pfilter->element.flags);
8800 rte_free(cld_filter);
8805 pfilter->element.flags |= rte_cpu_to_le_16(
8806 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8807 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8808 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8809 pfilter->element.queue_number =
8810 rte_cpu_to_le_16(tunnel_filter->queue_id);
8812 if (!tunnel_filter->is_to_vf)
8815 if (tunnel_filter->vf_id >= pf->vf_num) {
8816 PMD_DRV_LOG(ERR, "Invalid argument.");
8817 rte_free(cld_filter);
8820 vf = &pf->vfs[tunnel_filter->vf_id];
8824 /* Check if there is the filter in SW list */
8825 memset(&check_filter, 0, sizeof(check_filter));
8826 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8827 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8828 check_filter.vf_id = tunnel_filter->vf_id;
8829 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8831 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8832 rte_free(cld_filter);
8836 if (!add && !node) {
8837 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8838 rte_free(cld_filter);
8844 ret = i40e_aq_add_cloud_filters_bb(hw,
8845 vsi->seid, cld_filter, 1);
8847 ret = i40e_aq_add_cloud_filters(hw,
8848 vsi->seid, &cld_filter->element, 1);
8850 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8851 rte_free(cld_filter);
8854 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8855 if (tunnel == NULL) {
8856 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8857 rte_free(cld_filter);
8861 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8862 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8867 ret = i40e_aq_rem_cloud_filters_bb(
8868 hw, vsi->seid, cld_filter, 1);
8870 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8871 &cld_filter->element, 1);
8873 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8874 rte_free(cld_filter);
8877 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8880 rte_free(cld_filter);
8885 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8889 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8890 if (pf->vxlan_ports[i] == port)
8898 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8901 uint8_t filter_idx = 0;
8902 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8904 idx = i40e_get_vxlan_port_idx(pf, port);
8906 /* Check if port already exists */
8908 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8912 /* Now check if there is space to add the new port */
8913 idx = i40e_get_vxlan_port_idx(pf, 0);
8916 "Maximum number of UDP ports reached, not adding port %d",
8921 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8924 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8928 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8931 /* New port: add it and mark its index in the bitmap */
8932 pf->vxlan_ports[idx] = port;
8933 pf->vxlan_bitmap |= (1 << idx);
8935 if (!(pf->flags & I40E_FLAG_VXLAN))
8936 pf->flags |= I40E_FLAG_VXLAN;
8942 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8945 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8947 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8948 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8952 idx = i40e_get_vxlan_port_idx(pf, port);
8955 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8959 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8960 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8964 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8967 pf->vxlan_ports[idx] = 0;
8968 pf->vxlan_bitmap &= ~(1 << idx);
8970 if (!pf->vxlan_bitmap)
8971 pf->flags &= ~I40E_FLAG_VXLAN;
8976 /* Add UDP tunneling port */
8978 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8979 struct rte_eth_udp_tunnel *udp_tunnel)
8982 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8984 if (udp_tunnel == NULL)
8987 switch (udp_tunnel->prot_type) {
8988 case RTE_TUNNEL_TYPE_VXLAN:
8989 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8990 I40E_AQC_TUNNEL_TYPE_VXLAN);
8992 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8993 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8994 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8996 case RTE_TUNNEL_TYPE_GENEVE:
8997 case RTE_TUNNEL_TYPE_TEREDO:
8998 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9003 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9011 /* Remove UDP tunneling port */
9013 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
9014 struct rte_eth_udp_tunnel *udp_tunnel)
9017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9019 if (udp_tunnel == NULL)
9022 switch (udp_tunnel->prot_type) {
9023 case RTE_TUNNEL_TYPE_VXLAN:
9024 case RTE_TUNNEL_TYPE_VXLAN_GPE:
9025 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
9027 case RTE_TUNNEL_TYPE_GENEVE:
9028 case RTE_TUNNEL_TYPE_TEREDO:
9029 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9033 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9041 /* Calculate the maximum number of contiguous PF queues that are configured */
9043 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
9045 struct rte_eth_dev_data *data = pf->dev_data;
9047 struct i40e_rx_queue *rxq;
9050 for (i = 0; i < pf->lan_nb_qps; i++) {
9051 rxq = data->rx_queues[i];
9052 if (rxq && rxq->q_set)
9063 i40e_pf_config_rss(struct i40e_pf *pf)
9065 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9066 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9067 struct rte_eth_rss_conf rss_conf;
9068 uint32_t i, lut = 0;
9072 * If both VMDQ and RSS enabled, not all of PF queues are configured.
9073 * It's necessary to calculate the actual PF queues that are configured.
9075 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9076 num = i40e_pf_calc_configured_queues_num(pf);
9078 num = pf->dev_data->nb_rx_queues;
9080 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9081 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9086 "No PF queues are configured to enable RSS for port %u",
9087 pf->dev_data->port_id);
9091 if (pf->adapter->rss_reta_updated == 0) {
9092 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9095 lut = (lut << 8) | (j & ((0x1 <<
9096 hw->func_caps.rss_table_entry_width) - 1));
9098 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9103 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9104 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
9105 !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
9106 i40e_pf_disable_rss(pf);
9109 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9110 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9111 /* Random default keys */
9112 static uint32_t rss_key_default[] = {0x6b793944,
9113 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9114 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9115 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9117 rss_conf.rss_key = (uint8_t *)rss_key_default;
9118 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9122 return i40e_hw_rss_hash_set(pf, &rss_conf);
9126 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9127 struct rte_eth_tunnel_filter_conf *filter)
9129 if (pf == NULL || filter == NULL) {
9130 PMD_DRV_LOG(ERR, "Invalid parameter");
9134 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9135 PMD_DRV_LOG(ERR, "Invalid queue ID");
9139 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9140 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9144 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9145 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9146 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9150 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9151 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9152 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9159 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9160 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
9162 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9164 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9168 if (pf->support_multi_driver) {
9169 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9173 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9174 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9177 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9178 } else if (len == 4) {
9179 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9181 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9186 ret = i40e_aq_debug_write_global_register(hw,
9187 I40E_GL_PRS_FVBM(2),
9191 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9192 "with value 0x%08x",
9193 I40E_GL_PRS_FVBM(2), reg);
9197 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9198 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9204 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9211 switch (cfg->cfg_type) {
9212 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9213 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9216 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9224 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9225 enum rte_filter_op filter_op,
9228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9229 int ret = I40E_ERR_PARAM;
9231 switch (filter_op) {
9232 case RTE_ETH_FILTER_SET:
9233 ret = i40e_dev_global_config_set(hw,
9234 (struct rte_eth_global_cfg *)arg);
9237 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9245 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9246 enum rte_filter_op filter_op,
9249 struct rte_eth_tunnel_filter_conf *filter;
9250 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9251 int ret = I40E_SUCCESS;
9253 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9255 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9256 return I40E_ERR_PARAM;
9258 switch (filter_op) {
9259 case RTE_ETH_FILTER_NOP:
9260 if (!(pf->flags & I40E_FLAG_VXLAN))
9261 ret = I40E_NOT_SUPPORTED;
9263 case RTE_ETH_FILTER_ADD:
9264 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9266 case RTE_ETH_FILTER_DELETE:
9267 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9270 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9271 ret = I40E_ERR_PARAM;
9278 /* Get the symmetric hash enable configurations per port */
9280 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9282 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9284 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9287 /* Set the symmetric hash enable configurations per port */
9289 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9291 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9294 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9296 "Symmetric hash has already been enabled");
9299 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9301 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9303 "Symmetric hash has already been disabled");
9306 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9308 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9309 I40E_WRITE_FLUSH(hw);
9313 * Get global configurations of hash function type and symmetric hash enable
9314 * per flow type (pctype). Note that global configuration means it affects all
9315 * the ports on the same NIC.
9318 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9319 struct rte_eth_hash_global_conf *g_cfg)
9321 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9325 memset(g_cfg, 0, sizeof(*g_cfg));
9326 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9327 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9328 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9330 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9331 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9332 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9335 * As i40e supports less than 64 flow types, only first 64 bits need to
9338 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9339 g_cfg->valid_bit_mask[i] = 0ULL;
9340 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9343 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9345 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9346 if (!adapter->pctypes_tbl[i])
9348 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9349 j < I40E_FILTER_PCTYPE_MAX; j++) {
9350 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9351 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9352 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9353 g_cfg->sym_hash_enable_mask[0] |=
9364 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9365 const struct rte_eth_hash_global_conf *g_cfg)
9368 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9370 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9371 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9372 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9373 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9379 * As i40e supports less than 64 flow types, only first 64 bits need to
9382 mask0 = g_cfg->valid_bit_mask[0];
9383 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9385 /* Check if any unsupported flow type configured */
9386 if ((mask0 | i40e_mask) ^ i40e_mask)
9389 if (g_cfg->valid_bit_mask[i])
9397 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9403 * Set global configurations of hash function type and symmetric hash enable
9404 * per flow type (pctype). Note any modifying global configuration will affect
9405 * all the ports on the same NIC.
9408 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9409 struct rte_eth_hash_global_conf *g_cfg)
9411 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9412 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9416 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9418 if (pf->support_multi_driver) {
9419 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9423 /* Check the input parameters */
9424 ret = i40e_hash_global_config_check(adapter, g_cfg);
9429 * As i40e supports less than 64 flow types, only first 64 bits need to
9432 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9433 if (mask0 & (1UL << i)) {
9434 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9435 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9437 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9438 j < I40E_FILTER_PCTYPE_MAX; j++) {
9439 if (adapter->pctypes_tbl[i] & (1ULL << j))
9440 i40e_write_global_rx_ctl(hw,
9447 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9448 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9450 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9452 "Hash function already set to Toeplitz");
9455 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9456 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9458 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9460 "Hash function already set to Simple XOR");
9463 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9465 /* Use the default, and keep it as it is */
9468 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9471 I40E_WRITE_FLUSH(hw);
9477 * Valid input sets for hash and flow director filters per PCTYPE
9480 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9481 enum rte_filter_type filter)
9485 static const uint64_t valid_hash_inset_table[] = {
9486 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9487 I40E_INSET_DMAC | I40E_INSET_SMAC |
9488 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9489 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9490 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9491 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9492 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9493 I40E_INSET_FLEX_PAYLOAD,
9494 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9495 I40E_INSET_DMAC | I40E_INSET_SMAC |
9496 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9497 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9498 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9499 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9500 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9501 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9502 I40E_INSET_FLEX_PAYLOAD,
9503 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9504 I40E_INSET_DMAC | I40E_INSET_SMAC |
9505 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9506 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9507 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9508 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9509 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9510 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9511 I40E_INSET_FLEX_PAYLOAD,
9512 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9513 I40E_INSET_DMAC | I40E_INSET_SMAC |
9514 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9515 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9516 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9517 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9518 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9519 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9520 I40E_INSET_FLEX_PAYLOAD,
9521 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9522 I40E_INSET_DMAC | I40E_INSET_SMAC |
9523 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9524 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9525 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9526 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9527 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9528 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9529 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9530 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9531 I40E_INSET_DMAC | I40E_INSET_SMAC |
9532 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9533 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9534 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9535 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9536 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9537 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9538 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9539 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9540 I40E_INSET_DMAC | I40E_INSET_SMAC |
9541 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9542 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9543 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9544 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9545 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9546 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9547 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9548 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9549 I40E_INSET_DMAC | I40E_INSET_SMAC |
9550 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9551 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9552 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9553 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9554 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9555 I40E_INSET_FLEX_PAYLOAD,
9556 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9557 I40E_INSET_DMAC | I40E_INSET_SMAC |
9558 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9559 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9560 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9561 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9562 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9563 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9564 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9565 I40E_INSET_DMAC | I40E_INSET_SMAC |
9566 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9567 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9568 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9569 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9570 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9571 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9572 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9573 I40E_INSET_DMAC | I40E_INSET_SMAC |
9574 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9575 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9576 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9577 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9578 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9579 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9580 I40E_INSET_FLEX_PAYLOAD,
9581 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9582 I40E_INSET_DMAC | I40E_INSET_SMAC |
9583 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9584 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9585 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9586 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9587 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9588 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9589 I40E_INSET_FLEX_PAYLOAD,
9590 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9591 I40E_INSET_DMAC | I40E_INSET_SMAC |
9592 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9593 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9594 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9595 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9596 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9597 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9598 I40E_INSET_FLEX_PAYLOAD,
9599 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9600 I40E_INSET_DMAC | I40E_INSET_SMAC |
9601 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9602 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9603 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9604 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9605 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9606 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9607 I40E_INSET_FLEX_PAYLOAD,
9608 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9609 I40E_INSET_DMAC | I40E_INSET_SMAC |
9610 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9611 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9612 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9613 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9614 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9615 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9616 I40E_INSET_FLEX_PAYLOAD,
9617 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9618 I40E_INSET_DMAC | I40E_INSET_SMAC |
9619 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9620 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9621 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9622 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9623 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9624 I40E_INSET_FLEX_PAYLOAD,
9625 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9626 I40E_INSET_DMAC | I40E_INSET_SMAC |
9627 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9628 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9629 I40E_INSET_FLEX_PAYLOAD,
9633 * Flow director supports only fields defined in
9634 * union rte_eth_fdir_flow.
9636 static const uint64_t valid_fdir_inset_table[] = {
9637 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9638 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9639 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9640 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9641 I40E_INSET_IPV4_TTL,
9642 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9643 I40E_INSET_DMAC | I40E_INSET_SMAC |
9644 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9645 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9646 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9647 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9648 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9649 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9650 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9651 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9652 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9653 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9654 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9655 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9656 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9657 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9658 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9659 I40E_INSET_DMAC | I40E_INSET_SMAC |
9660 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9661 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9662 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9663 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9664 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9665 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9666 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9667 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9668 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9669 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9670 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9671 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9672 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9673 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9675 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9676 I40E_INSET_DMAC | I40E_INSET_SMAC |
9677 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9678 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9679 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9680 I40E_INSET_IPV4_TTL,
9681 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9682 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9683 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9684 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9685 I40E_INSET_IPV6_HOP_LIMIT,
9686 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9687 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9688 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9689 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9690 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9691 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9692 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9693 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9694 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9695 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9696 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9697 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9698 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9699 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9700 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9701 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9702 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9703 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9704 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9705 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9706 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9707 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9708 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9709 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9710 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9711 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9712 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9713 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9714 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9715 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9717 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9718 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9719 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9720 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9721 I40E_INSET_IPV6_HOP_LIMIT,
9722 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9723 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9724 I40E_INSET_LAST_ETHER_TYPE,
9727 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9729 if (filter == RTE_ETH_FILTER_HASH)
9730 valid = valid_hash_inset_table[pctype];
9732 valid = valid_fdir_inset_table[pctype];
9738 * Validate if the input set is allowed for a specific PCTYPE
9741 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9742 enum rte_filter_type filter, uint64_t inset)
9746 valid = i40e_get_valid_input_set(pctype, filter);
9747 if (inset & (~valid))
9753 /* default input set fields combination per pctype */
9755 i40e_get_default_input_set(uint16_t pctype)
9757 static const uint64_t default_inset_table[] = {
9758 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9759 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9760 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9761 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9762 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9763 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9764 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9765 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9766 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9767 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9768 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9769 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9770 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9771 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9772 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9773 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9774 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9775 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9776 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9777 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9779 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9780 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9781 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9782 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9783 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9784 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9785 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9786 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9787 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9788 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9789 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9790 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9791 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9792 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9793 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9794 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9795 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9796 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9797 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9798 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9799 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9800 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9802 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9803 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9804 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9805 I40E_INSET_LAST_ETHER_TYPE,
9808 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9811 return default_inset_table[pctype];
9815 * Parse the input set from index to logical bit masks
9818 i40e_parse_input_set(uint64_t *inset,
9819 enum i40e_filter_pctype pctype,
9820 enum rte_eth_input_set_field *field,
9826 static const struct {
9827 enum rte_eth_input_set_field field;
9829 } inset_convert_table[] = {
9830 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9831 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9832 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9833 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9834 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9835 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9836 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9837 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9838 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9839 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9840 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9841 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9842 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9843 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9844 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9845 I40E_INSET_IPV6_NEXT_HDR},
9846 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9847 I40E_INSET_IPV6_HOP_LIMIT},
9848 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9849 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9850 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9851 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9852 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9853 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9854 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9855 I40E_INSET_SCTP_VT},
9856 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9857 I40E_INSET_TUNNEL_DMAC},
9858 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9859 I40E_INSET_VLAN_TUNNEL},
9860 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9861 I40E_INSET_TUNNEL_ID},
9862 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9863 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9864 I40E_INSET_FLEX_PAYLOAD_W1},
9865 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9866 I40E_INSET_FLEX_PAYLOAD_W2},
9867 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9868 I40E_INSET_FLEX_PAYLOAD_W3},
9869 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9870 I40E_INSET_FLEX_PAYLOAD_W4},
9871 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9872 I40E_INSET_FLEX_PAYLOAD_W5},
9873 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9874 I40E_INSET_FLEX_PAYLOAD_W6},
9875 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9876 I40E_INSET_FLEX_PAYLOAD_W7},
9877 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9878 I40E_INSET_FLEX_PAYLOAD_W8},
9881 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9884 /* Only one item allowed for default or all */
9886 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9887 *inset = i40e_get_default_input_set(pctype);
9889 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9890 *inset = I40E_INSET_NONE;
9895 for (i = 0, *inset = 0; i < size; i++) {
9896 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9897 if (field[i] == inset_convert_table[j].field) {
9898 *inset |= inset_convert_table[j].inset;
9903 /* It contains unsupported input set, return immediately */
9904 if (j == RTE_DIM(inset_convert_table))
9912 * Translate the input set from bit masks to register aware bit masks
9916 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9926 static const struct inset_map inset_map_common[] = {
9927 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9928 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9929 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9930 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9931 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9932 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9933 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9934 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9935 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9936 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9937 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9938 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9939 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9940 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9941 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9942 {I40E_INSET_TUNNEL_DMAC,
9943 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9944 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9945 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9946 {I40E_INSET_TUNNEL_SRC_PORT,
9947 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9948 {I40E_INSET_TUNNEL_DST_PORT,
9949 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9950 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9951 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9952 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9953 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9954 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9955 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9956 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9957 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9958 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9961 /* some different registers map in x722*/
9962 static const struct inset_map inset_map_diff_x722[] = {
9963 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9964 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9965 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9966 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9969 static const struct inset_map inset_map_diff_not_x722[] = {
9970 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9971 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9972 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9973 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9979 /* Translate input set to register aware inset */
9980 if (type == I40E_MAC_X722) {
9981 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9982 if (input & inset_map_diff_x722[i].inset)
9983 val |= inset_map_diff_x722[i].inset_reg;
9986 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9987 if (input & inset_map_diff_not_x722[i].inset)
9988 val |= inset_map_diff_not_x722[i].inset_reg;
9992 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9993 if (input & inset_map_common[i].inset)
9994 val |= inset_map_common[i].inset_reg;
10001 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
10003 uint8_t i, idx = 0;
10004 uint64_t inset_need_mask = inset;
10006 static const struct {
10009 } inset_mask_map[] = {
10010 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
10011 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
10012 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
10013 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
10014 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
10015 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
10016 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
10017 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
10020 if (!inset || !mask || !nb_elem)
10023 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10024 /* Clear the inset bit, if no MASK is required,
10025 * for example proto + ttl
10027 if ((inset & inset_mask_map[i].inset) ==
10028 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
10029 inset_need_mask &= ~inset_mask_map[i].inset;
10030 if (!inset_need_mask)
10033 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10034 if ((inset_need_mask & inset_mask_map[i].inset) ==
10035 inset_mask_map[i].inset) {
10036 if (idx >= nb_elem) {
10037 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
10040 mask[idx] = inset_mask_map[i].mask;
10049 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10051 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10053 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10055 i40e_write_rx_ctl(hw, addr, val);
10056 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10057 (uint32_t)i40e_read_rx_ctl(hw, addr));
10061 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10063 uint32_t reg = i40e_read_rx_ctl(hw, addr);
10064 struct rte_eth_dev *dev;
10066 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10068 i40e_write_rx_ctl(hw, addr, val);
10069 PMD_DRV_LOG(WARNING,
10070 "i40e device %s changed global register [0x%08x]."
10071 " original: 0x%08x, new: 0x%08x",
10072 dev->device->name, addr, reg,
10073 (uint32_t)i40e_read_rx_ctl(hw, addr));
10078 i40e_filter_input_set_init(struct i40e_pf *pf)
10080 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10081 enum i40e_filter_pctype pctype;
10082 uint64_t input_set, inset_reg;
10083 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10085 uint16_t flow_type;
10087 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10088 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10089 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10091 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10094 input_set = i40e_get_default_input_set(pctype);
10096 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10097 I40E_INSET_MASK_NUM_REG);
10100 if (pf->support_multi_driver && num > 0) {
10101 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10104 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10107 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10108 (uint32_t)(inset_reg & UINT32_MAX));
10109 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10110 (uint32_t)((inset_reg >>
10111 I40E_32_BIT_WIDTH) & UINT32_MAX));
10112 if (!pf->support_multi_driver) {
10113 i40e_check_write_global_reg(hw,
10114 I40E_GLQF_HASH_INSET(0, pctype),
10115 (uint32_t)(inset_reg & UINT32_MAX));
10116 i40e_check_write_global_reg(hw,
10117 I40E_GLQF_HASH_INSET(1, pctype),
10118 (uint32_t)((inset_reg >>
10119 I40E_32_BIT_WIDTH) & UINT32_MAX));
10121 for (i = 0; i < num; i++) {
10122 i40e_check_write_global_reg(hw,
10123 I40E_GLQF_FD_MSK(i, pctype),
10125 i40e_check_write_global_reg(hw,
10126 I40E_GLQF_HASH_MSK(i, pctype),
10129 /*clear unused mask registers of the pctype */
10130 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10131 i40e_check_write_global_reg(hw,
10132 I40E_GLQF_FD_MSK(i, pctype),
10134 i40e_check_write_global_reg(hw,
10135 I40E_GLQF_HASH_MSK(i, pctype),
10139 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10141 I40E_WRITE_FLUSH(hw);
10143 /* store the default input set */
10144 if (!pf->support_multi_driver)
10145 pf->hash_input_set[pctype] = input_set;
10146 pf->fdir.input_set[pctype] = input_set;
10151 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10152 struct rte_eth_input_set_conf *conf)
10154 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10155 enum i40e_filter_pctype pctype;
10156 uint64_t input_set, inset_reg = 0;
10157 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10161 PMD_DRV_LOG(ERR, "Invalid pointer");
10164 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10165 conf->op != RTE_ETH_INPUT_SET_ADD) {
10166 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10170 if (pf->support_multi_driver) {
10171 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10175 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10176 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10177 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10181 if (hw->mac.type == I40E_MAC_X722) {
10182 /* get translated pctype value in fd pctype register */
10183 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10184 I40E_GLQF_FD_PCTYPES((int)pctype));
10187 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10190 PMD_DRV_LOG(ERR, "Failed to parse input set");
10194 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10195 /* get inset value in register */
10196 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10197 inset_reg <<= I40E_32_BIT_WIDTH;
10198 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10199 input_set |= pf->hash_input_set[pctype];
10201 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10202 I40E_INSET_MASK_NUM_REG);
10206 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10208 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10209 (uint32_t)(inset_reg & UINT32_MAX));
10210 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10211 (uint32_t)((inset_reg >>
10212 I40E_32_BIT_WIDTH) & UINT32_MAX));
10214 for (i = 0; i < num; i++)
10215 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10217 /*clear unused mask registers of the pctype */
10218 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10219 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10221 I40E_WRITE_FLUSH(hw);
10223 pf->hash_input_set[pctype] = input_set;
10228 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10229 struct rte_eth_input_set_conf *conf)
10231 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10232 enum i40e_filter_pctype pctype;
10233 uint64_t input_set, inset_reg = 0;
10234 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10237 if (!hw || !conf) {
10238 PMD_DRV_LOG(ERR, "Invalid pointer");
10241 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10242 conf->op != RTE_ETH_INPUT_SET_ADD) {
10243 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10247 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10249 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10250 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10254 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10257 PMD_DRV_LOG(ERR, "Failed to parse input set");
10261 /* get inset value in register */
10262 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10263 inset_reg <<= I40E_32_BIT_WIDTH;
10264 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10266 /* Can not change the inset reg for flex payload for fdir,
10267 * it is done by writing I40E_PRTQF_FD_FLXINSET
10268 * in i40e_set_flex_mask_on_pctype.
10270 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10271 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10273 input_set |= pf->fdir.input_set[pctype];
10274 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10275 I40E_INSET_MASK_NUM_REG);
10278 if (pf->support_multi_driver && num > 0) {
10279 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10283 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10285 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10286 (uint32_t)(inset_reg & UINT32_MAX));
10287 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10288 (uint32_t)((inset_reg >>
10289 I40E_32_BIT_WIDTH) & UINT32_MAX));
10291 if (!pf->support_multi_driver) {
10292 for (i = 0; i < num; i++)
10293 i40e_check_write_global_reg(hw,
10294 I40E_GLQF_FD_MSK(i, pctype),
10296 /*clear unused mask registers of the pctype */
10297 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10298 i40e_check_write_global_reg(hw,
10299 I40E_GLQF_FD_MSK(i, pctype),
10302 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10304 I40E_WRITE_FLUSH(hw);
10306 pf->fdir.input_set[pctype] = input_set;
10311 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10315 if (!hw || !info) {
10316 PMD_DRV_LOG(ERR, "Invalid pointer");
10320 switch (info->info_type) {
10321 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10322 i40e_get_symmetric_hash_enable_per_port(hw,
10323 &(info->info.enable));
10325 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10326 ret = i40e_get_hash_filter_global_config(hw,
10327 &(info->info.global_conf));
10330 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10340 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10344 if (!hw || !info) {
10345 PMD_DRV_LOG(ERR, "Invalid pointer");
10349 switch (info->info_type) {
10350 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10351 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10353 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10354 ret = i40e_set_hash_filter_global_config(hw,
10355 &(info->info.global_conf));
10357 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10358 ret = i40e_hash_filter_inset_select(hw,
10359 &(info->info.input_set_conf));
10363 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10372 /* Operations for hash function */
10374 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10375 enum rte_filter_op filter_op,
10378 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10381 switch (filter_op) {
10382 case RTE_ETH_FILTER_NOP:
10384 case RTE_ETH_FILTER_GET:
10385 ret = i40e_hash_filter_get(hw,
10386 (struct rte_eth_hash_filter_info *)arg);
10388 case RTE_ETH_FILTER_SET:
10389 ret = i40e_hash_filter_set(hw,
10390 (struct rte_eth_hash_filter_info *)arg);
10393 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10402 /* Convert ethertype filter structure */
10404 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10405 struct i40e_ethertype_filter *filter)
10407 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10408 RTE_ETHER_ADDR_LEN);
10409 filter->input.ether_type = input->ether_type;
10410 filter->flags = input->flags;
10411 filter->queue = input->queue;
10416 /* Check if there exists the ehtertype filter */
10417 struct i40e_ethertype_filter *
10418 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10419 const struct i40e_ethertype_filter_input *input)
10423 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10427 return ethertype_rule->hash_map[ret];
10430 /* Add ethertype filter in SW list */
10432 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10433 struct i40e_ethertype_filter *filter)
10435 struct i40e_ethertype_rule *rule = &pf->ethertype;
10438 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10441 "Failed to insert ethertype filter"
10442 " to hash table %d!",
10446 rule->hash_map[ret] = filter;
10448 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10453 /* Delete ethertype filter in SW list */
10455 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10456 struct i40e_ethertype_filter_input *input)
10458 struct i40e_ethertype_rule *rule = &pf->ethertype;
10459 struct i40e_ethertype_filter *filter;
10462 ret = rte_hash_del_key(rule->hash_table, input);
10465 "Failed to delete ethertype filter"
10466 " to hash table %d!",
10470 filter = rule->hash_map[ret];
10471 rule->hash_map[ret] = NULL;
10473 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10480 * Configure ethertype filter, which can director packet by filtering
10481 * with mac address and ether_type or only ether_type
10484 i40e_ethertype_filter_set(struct i40e_pf *pf,
10485 struct rte_eth_ethertype_filter *filter,
10488 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10489 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10490 struct i40e_ethertype_filter *ethertype_filter, *node;
10491 struct i40e_ethertype_filter check_filter;
10492 struct i40e_control_filter_stats stats;
10493 uint16_t flags = 0;
10496 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10497 PMD_DRV_LOG(ERR, "Invalid queue ID");
10500 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10501 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10503 "unsupported ether_type(0x%04x) in control packet filter.",
10504 filter->ether_type);
10507 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10508 PMD_DRV_LOG(WARNING,
10509 "filter vlan ether_type in first tag is not supported.");
10511 /* Check if there is the filter in SW list */
10512 memset(&check_filter, 0, sizeof(check_filter));
10513 i40e_ethertype_filter_convert(filter, &check_filter);
10514 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10515 &check_filter.input);
10517 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10521 if (!add && !node) {
10522 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10526 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10527 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10528 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10529 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10530 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10532 memset(&stats, 0, sizeof(stats));
10533 ret = i40e_aq_add_rem_control_packet_filter(hw,
10534 filter->mac_addr.addr_bytes,
10535 filter->ether_type, flags,
10536 pf->main_vsi->seid,
10537 filter->queue, add, &stats, NULL);
10540 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10541 ret, stats.mac_etype_used, stats.etype_used,
10542 stats.mac_etype_free, stats.etype_free);
10546 /* Add or delete a filter in SW list */
10548 ethertype_filter = rte_zmalloc("ethertype_filter",
10549 sizeof(*ethertype_filter), 0);
10550 if (ethertype_filter == NULL) {
10551 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10555 rte_memcpy(ethertype_filter, &check_filter,
10556 sizeof(check_filter));
10557 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10559 rte_free(ethertype_filter);
10561 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10568 * Handle operations for ethertype filter.
10571 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10572 enum rte_filter_op filter_op,
10575 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10578 if (filter_op == RTE_ETH_FILTER_NOP)
10582 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10587 switch (filter_op) {
10588 case RTE_ETH_FILTER_ADD:
10589 ret = i40e_ethertype_filter_set(pf,
10590 (struct rte_eth_ethertype_filter *)arg,
10593 case RTE_ETH_FILTER_DELETE:
10594 ret = i40e_ethertype_filter_set(pf,
10595 (struct rte_eth_ethertype_filter *)arg,
10599 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10607 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10608 enum rte_filter_type filter_type,
10609 enum rte_filter_op filter_op,
10617 switch (filter_type) {
10618 case RTE_ETH_FILTER_NONE:
10619 /* For global configuration */
10620 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10622 case RTE_ETH_FILTER_HASH:
10623 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10625 case RTE_ETH_FILTER_MACVLAN:
10626 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10628 case RTE_ETH_FILTER_ETHERTYPE:
10629 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10631 case RTE_ETH_FILTER_TUNNEL:
10632 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10634 case RTE_ETH_FILTER_FDIR:
10635 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10637 case RTE_ETH_FILTER_GENERIC:
10638 if (filter_op != RTE_ETH_FILTER_GET)
10640 *(const void **)arg = &i40e_flow_ops;
10643 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10653 * Check and enable Extended Tag.
10654 * Enabling Extended Tag is important for 40G performance.
10657 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10659 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10663 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10666 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10670 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10671 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10676 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10679 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10683 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10684 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10687 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10688 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10691 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10698 * As some registers wouldn't be reset unless a global hardware reset,
10699 * hardware initialization is needed to put those registers into an
10700 * expected initial state.
10703 i40e_hw_init(struct rte_eth_dev *dev)
10705 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10707 i40e_enable_extended_tag(dev);
10709 /* clear the PF Queue Filter control register */
10710 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10712 /* Disable symmetric hash per port */
10713 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10717 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10718 * however this function will return only one highest pctype index,
10719 * which is not quite correct. This is known problem of i40e driver
10720 * and needs to be fixed later.
10722 enum i40e_filter_pctype
10723 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10726 uint64_t pctype_mask;
10728 if (flow_type < I40E_FLOW_TYPE_MAX) {
10729 pctype_mask = adapter->pctypes_tbl[flow_type];
10730 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10731 if (pctype_mask & (1ULL << i))
10732 return (enum i40e_filter_pctype)i;
10735 return I40E_FILTER_PCTYPE_INVALID;
10739 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10740 enum i40e_filter_pctype pctype)
10743 uint64_t pctype_mask = 1ULL << pctype;
10745 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10747 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10751 return RTE_ETH_FLOW_UNKNOWN;
10755 * On X710, performance number is far from the expectation on recent firmware
10756 * versions; on XL710, performance number is also far from the expectation on
10757 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10758 * mode is enabled and port MAC address is equal to the packet destination MAC
10759 * address. The fix for this issue may not be integrated in the following
10760 * firmware version. So the workaround in software driver is needed. It needs
10761 * to modify the initial values of 3 internal only registers for both X710 and
10762 * XL710. Note that the values for X710 or XL710 could be different, and the
10763 * workaround can be removed when it is fixed in firmware in the future.
10766 /* For both X710 and XL710 */
10767 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10768 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10769 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10771 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10772 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10775 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10776 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10779 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10781 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10782 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10785 * GL_SWR_PM_UP_THR:
10786 * The value is not impacted from the link speed, its value is set according
10787 * to the total number of ports for a better pipe-monitor configuration.
10790 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10792 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10793 .device_id = (dev), \
10794 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10796 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10797 .device_id = (dev), \
10798 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10800 static const struct {
10801 uint16_t device_id;
10803 } swr_pm_table[] = {
10804 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10805 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10806 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10807 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10808 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10810 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10811 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10812 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10813 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10814 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10815 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10816 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10820 if (value == NULL) {
10821 PMD_DRV_LOG(ERR, "value is NULL");
10825 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10826 if (hw->device_id == swr_pm_table[i].device_id) {
10827 *value = swr_pm_table[i].val;
10829 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10831 hw->device_id, *value);
10840 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10842 enum i40e_status_code status;
10843 struct i40e_aq_get_phy_abilities_resp phy_ab;
10844 int ret = -ENOTSUP;
10847 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10851 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10854 rte_delay_us(100000);
10856 status = i40e_aq_get_phy_capabilities(hw, false,
10857 true, &phy_ab, NULL);
10865 i40e_configure_registers(struct i40e_hw *hw)
10871 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10872 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10873 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10879 for (i = 0; i < RTE_DIM(reg_table); i++) {
10880 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10881 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10883 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10884 else /* For X710/XL710/XXV710 */
10885 if (hw->aq.fw_maj_ver < 6)
10887 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10890 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10893 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10894 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10896 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10897 else /* For X710/XL710/XXV710 */
10899 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10902 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10905 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10906 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10907 "GL_SWR_PM_UP_THR value fixup",
10912 reg_table[i].val = cfg_val;
10915 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10918 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10919 reg_table[i].addr);
10922 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10923 reg_table[i].addr, reg);
10924 if (reg == reg_table[i].val)
10927 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10928 reg_table[i].val, NULL);
10931 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10932 reg_table[i].val, reg_table[i].addr);
10935 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10936 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10940 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10941 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10942 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10944 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10949 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10950 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10954 /* Configure for double VLAN RX stripping */
10955 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10956 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10957 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10958 ret = i40e_aq_debug_write_register(hw,
10959 I40E_VSI_TSR(vsi->vsi_id),
10962 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10964 return I40E_ERR_CONFIG;
10968 /* Configure for double VLAN TX insertion */
10969 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10970 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10971 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10972 ret = i40e_aq_debug_write_register(hw,
10973 I40E_VSI_L2TAGSTXVALID(
10974 vsi->vsi_id), reg, NULL);
10977 "Failed to update VSI_L2TAGSTXVALID[%d]",
10979 return I40E_ERR_CONFIG;
10987 * i40e_aq_add_mirror_rule
10988 * @hw: pointer to the hardware structure
10989 * @seid: VEB seid to add mirror rule to
10990 * @dst_id: destination vsi seid
10991 * @entries: Buffer which contains the entities to be mirrored
10992 * @count: number of entities contained in the buffer
10993 * @rule_id:the rule_id of the rule to be added
10995 * Add a mirror rule for a given veb.
10998 static enum i40e_status_code
10999 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
11000 uint16_t seid, uint16_t dst_id,
11001 uint16_t rule_type, uint16_t *entries,
11002 uint16_t count, uint16_t *rule_id)
11004 struct i40e_aq_desc desc;
11005 struct i40e_aqc_add_delete_mirror_rule cmd;
11006 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
11007 (struct i40e_aqc_add_delete_mirror_rule_completion *)
11010 enum i40e_status_code status;
11012 i40e_fill_default_direct_cmd_desc(&desc,
11013 i40e_aqc_opc_add_mirror_rule);
11014 memset(&cmd, 0, sizeof(cmd));
11016 buff_len = sizeof(uint16_t) * count;
11017 desc.datalen = rte_cpu_to_le_16(buff_len);
11019 desc.flags |= rte_cpu_to_le_16(
11020 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
11021 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11022 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11023 cmd.num_entries = rte_cpu_to_le_16(count);
11024 cmd.seid = rte_cpu_to_le_16(seid);
11025 cmd.destination = rte_cpu_to_le_16(dst_id);
11027 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11028 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
11030 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
11031 hw->aq.asq_last_status, resp->rule_id,
11032 resp->mirror_rules_used, resp->mirror_rules_free);
11033 *rule_id = rte_le_to_cpu_16(resp->rule_id);
11039 * i40e_aq_del_mirror_rule
11040 * @hw: pointer to the hardware structure
11041 * @seid: VEB seid to add mirror rule to
11042 * @entries: Buffer which contains the entities to be mirrored
11043 * @count: number of entities contained in the buffer
11044 * @rule_id:the rule_id of the rule to be delete
11046 * Delete a mirror rule for a given veb.
11049 static enum i40e_status_code
11050 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
11051 uint16_t seid, uint16_t rule_type, uint16_t *entries,
11052 uint16_t count, uint16_t rule_id)
11054 struct i40e_aq_desc desc;
11055 struct i40e_aqc_add_delete_mirror_rule cmd;
11056 uint16_t buff_len = 0;
11057 enum i40e_status_code status;
11060 i40e_fill_default_direct_cmd_desc(&desc,
11061 i40e_aqc_opc_delete_mirror_rule);
11062 memset(&cmd, 0, sizeof(cmd));
11063 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11064 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11066 cmd.num_entries = count;
11067 buff_len = sizeof(uint16_t) * count;
11068 desc.datalen = rte_cpu_to_le_16(buff_len);
11069 buff = (void *)entries;
11071 /* rule id is filled in destination field for deleting mirror rule */
11072 cmd.destination = rte_cpu_to_le_16(rule_id);
11074 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11075 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11076 cmd.seid = rte_cpu_to_le_16(seid);
11078 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11079 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11085 * i40e_mirror_rule_set
11086 * @dev: pointer to the hardware structure
11087 * @mirror_conf: mirror rule info
11088 * @sw_id: mirror rule's sw_id
11089 * @on: enable/disable
11091 * set a mirror rule.
11095 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11096 struct rte_eth_mirror_conf *mirror_conf,
11097 uint8_t sw_id, uint8_t on)
11099 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11102 struct i40e_mirror_rule *parent = NULL;
11103 uint16_t seid, dst_seid, rule_id;
11107 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11109 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11111 "mirror rule can not be configured without veb or vfs.");
11114 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11115 PMD_DRV_LOG(ERR, "mirror table is full.");
11118 if (mirror_conf->dst_pool > pf->vf_num) {
11119 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11120 mirror_conf->dst_pool);
11124 seid = pf->main_vsi->veb->seid;
11126 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11127 if (sw_id <= it->index) {
11133 if (mirr_rule && sw_id == mirr_rule->index) {
11135 PMD_DRV_LOG(ERR, "mirror rule exists.");
11138 ret = i40e_aq_del_mirror_rule(hw, seid,
11139 mirr_rule->rule_type,
11140 mirr_rule->entries,
11141 mirr_rule->num_entries, mirr_rule->id);
11144 "failed to remove mirror rule: ret = %d, aq_err = %d.",
11145 ret, hw->aq.asq_last_status);
11148 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11149 rte_free(mirr_rule);
11150 pf->nb_mirror_rule--;
11154 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11158 mirr_rule = rte_zmalloc("i40e_mirror_rule",
11159 sizeof(struct i40e_mirror_rule) , 0);
11161 PMD_DRV_LOG(ERR, "failed to allocate memory");
11162 return I40E_ERR_NO_MEMORY;
11164 switch (mirror_conf->rule_type) {
11165 case ETH_MIRROR_VLAN:
11166 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11167 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11168 mirr_rule->entries[j] =
11169 mirror_conf->vlan.vlan_id[i];
11174 PMD_DRV_LOG(ERR, "vlan is not specified.");
11175 rte_free(mirr_rule);
11178 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11180 case ETH_MIRROR_VIRTUAL_POOL_UP:
11181 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11182 /* check if the specified pool bit is out of range */
11183 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11184 PMD_DRV_LOG(ERR, "pool mask is out of range.");
11185 rte_free(mirr_rule);
11188 for (i = 0, j = 0; i < pf->vf_num; i++) {
11189 if (mirror_conf->pool_mask & (1ULL << i)) {
11190 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11194 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11195 /* add pf vsi to entries */
11196 mirr_rule->entries[j] = pf->main_vsi_seid;
11200 PMD_DRV_LOG(ERR, "pool is not specified.");
11201 rte_free(mirr_rule);
11204 /* egress and ingress in aq commands means from switch but not port */
11205 mirr_rule->rule_type =
11206 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11207 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11208 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11210 case ETH_MIRROR_UPLINK_PORT:
11211 /* egress and ingress in aq commands means from switch but not port*/
11212 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11214 case ETH_MIRROR_DOWNLINK_PORT:
11215 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11218 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11219 mirror_conf->rule_type);
11220 rte_free(mirr_rule);
11224 /* If the dst_pool is equal to vf_num, consider it as PF */
11225 if (mirror_conf->dst_pool == pf->vf_num)
11226 dst_seid = pf->main_vsi_seid;
11228 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11230 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11231 mirr_rule->rule_type, mirr_rule->entries,
11235 "failed to add mirror rule: ret = %d, aq_err = %d.",
11236 ret, hw->aq.asq_last_status);
11237 rte_free(mirr_rule);
11241 mirr_rule->index = sw_id;
11242 mirr_rule->num_entries = j;
11243 mirr_rule->id = rule_id;
11244 mirr_rule->dst_vsi_seid = dst_seid;
11247 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11249 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11251 pf->nb_mirror_rule++;
11256 * i40e_mirror_rule_reset
11257 * @dev: pointer to the device
11258 * @sw_id: mirror rule's sw_id
11260 * reset a mirror rule.
11264 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11268 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11272 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11274 seid = pf->main_vsi->veb->seid;
11276 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11277 if (sw_id == it->index) {
11283 ret = i40e_aq_del_mirror_rule(hw, seid,
11284 mirr_rule->rule_type,
11285 mirr_rule->entries,
11286 mirr_rule->num_entries, mirr_rule->id);
11289 "failed to remove mirror rule: status = %d, aq_err = %d.",
11290 ret, hw->aq.asq_last_status);
11293 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11294 rte_free(mirr_rule);
11295 pf->nb_mirror_rule--;
11297 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11304 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11306 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11307 uint64_t systim_cycles;
11309 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11310 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11313 return systim_cycles;
11317 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11319 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11320 uint64_t rx_tstamp;
11322 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11323 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11330 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11332 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11333 uint64_t tx_tstamp;
11335 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11336 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11343 i40e_start_timecounters(struct rte_eth_dev *dev)
11345 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11346 struct i40e_adapter *adapter = dev->data->dev_private;
11347 struct rte_eth_link link;
11348 uint32_t tsync_inc_l;
11349 uint32_t tsync_inc_h;
11351 /* Get current link speed. */
11352 i40e_dev_link_update(dev, 1);
11353 rte_eth_linkstatus_get(dev, &link);
11355 switch (link.link_speed) {
11356 case ETH_SPEED_NUM_40G:
11357 case ETH_SPEED_NUM_25G:
11358 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11359 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11361 case ETH_SPEED_NUM_10G:
11362 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11363 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11365 case ETH_SPEED_NUM_1G:
11366 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11367 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11374 /* Set the timesync increment value. */
11375 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11376 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11378 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11379 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11380 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11382 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11383 adapter->systime_tc.cc_shift = 0;
11384 adapter->systime_tc.nsec_mask = 0;
11386 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11387 adapter->rx_tstamp_tc.cc_shift = 0;
11388 adapter->rx_tstamp_tc.nsec_mask = 0;
11390 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11391 adapter->tx_tstamp_tc.cc_shift = 0;
11392 adapter->tx_tstamp_tc.nsec_mask = 0;
11396 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11398 struct i40e_adapter *adapter = dev->data->dev_private;
11400 adapter->systime_tc.nsec += delta;
11401 adapter->rx_tstamp_tc.nsec += delta;
11402 adapter->tx_tstamp_tc.nsec += delta;
11408 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11411 struct i40e_adapter *adapter = dev->data->dev_private;
11413 ns = rte_timespec_to_ns(ts);
11415 /* Set the timecounters to a new value. */
11416 adapter->systime_tc.nsec = ns;
11417 adapter->rx_tstamp_tc.nsec = ns;
11418 adapter->tx_tstamp_tc.nsec = ns;
11424 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11426 uint64_t ns, systime_cycles;
11427 struct i40e_adapter *adapter = dev->data->dev_private;
11429 systime_cycles = i40e_read_systime_cyclecounter(dev);
11430 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11431 *ts = rte_ns_to_timespec(ns);
11437 i40e_timesync_enable(struct rte_eth_dev *dev)
11439 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11440 uint32_t tsync_ctl_l;
11441 uint32_t tsync_ctl_h;
11443 /* Stop the timesync system time. */
11444 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11445 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11446 /* Reset the timesync system time value. */
11447 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11448 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11450 i40e_start_timecounters(dev);
11452 /* Clear timesync registers. */
11453 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11454 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11455 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11456 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11457 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11458 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11460 /* Enable timestamping of PTP packets. */
11461 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11462 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11464 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11465 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11466 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11468 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11469 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11475 i40e_timesync_disable(struct rte_eth_dev *dev)
11477 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11478 uint32_t tsync_ctl_l;
11479 uint32_t tsync_ctl_h;
11481 /* Disable timestamping of transmitted PTP packets. */
11482 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11483 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11485 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11486 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11488 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11489 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11491 /* Reset the timesync increment value. */
11492 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11493 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11499 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11500 struct timespec *timestamp, uint32_t flags)
11502 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11503 struct i40e_adapter *adapter = dev->data->dev_private;
11504 uint32_t sync_status;
11505 uint32_t index = flags & 0x03;
11506 uint64_t rx_tstamp_cycles;
11509 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11510 if ((sync_status & (1 << index)) == 0)
11513 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11514 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11515 *timestamp = rte_ns_to_timespec(ns);
11521 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11522 struct timespec *timestamp)
11524 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11525 struct i40e_adapter *adapter = dev->data->dev_private;
11526 uint32_t sync_status;
11527 uint64_t tx_tstamp_cycles;
11530 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11531 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11534 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11535 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11536 *timestamp = rte_ns_to_timespec(ns);
11542 * i40e_parse_dcb_configure - parse dcb configure from user
11543 * @dev: the device being configured
11544 * @dcb_cfg: pointer of the result of parse
11545 * @*tc_map: bit map of enabled traffic classes
11547 * Returns 0 on success, negative value on failure
11550 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11551 struct i40e_dcbx_config *dcb_cfg,
11554 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11555 uint8_t i, tc_bw, bw_lf;
11557 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11559 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11560 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11561 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11565 /* assume each tc has the same bw */
11566 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11567 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11568 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11569 /* to ensure the sum of tcbw is equal to 100 */
11570 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11571 for (i = 0; i < bw_lf; i++)
11572 dcb_cfg->etscfg.tcbwtable[i]++;
11574 /* assume each tc has the same Transmission Selection Algorithm */
11575 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11576 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11578 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11579 dcb_cfg->etscfg.prioritytable[i] =
11580 dcb_rx_conf->dcb_tc[i];
11582 /* FW needs one App to configure HW */
11583 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11584 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11585 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11586 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11588 if (dcb_rx_conf->nb_tcs == 0)
11589 *tc_map = 1; /* tc0 only */
11591 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11593 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11594 dcb_cfg->pfc.willing = 0;
11595 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11596 dcb_cfg->pfc.pfcenable = *tc_map;
11602 static enum i40e_status_code
11603 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11604 struct i40e_aqc_vsi_properties_data *info,
11605 uint8_t enabled_tcmap)
11607 enum i40e_status_code ret;
11608 int i, total_tc = 0;
11609 uint16_t qpnum_per_tc, bsf, qp_idx;
11610 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11611 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11612 uint16_t used_queues;
11614 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11615 if (ret != I40E_SUCCESS)
11618 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11619 if (enabled_tcmap & (1 << i))
11624 vsi->enabled_tc = enabled_tcmap;
11626 /* different VSI has different queues assigned */
11627 if (vsi->type == I40E_VSI_MAIN)
11628 used_queues = dev_data->nb_rx_queues -
11629 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11630 else if (vsi->type == I40E_VSI_VMDQ2)
11631 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11633 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11634 return I40E_ERR_NO_AVAILABLE_VSI;
11637 qpnum_per_tc = used_queues / total_tc;
11638 /* Number of queues per enabled TC */
11639 if (qpnum_per_tc == 0) {
11640 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11641 return I40E_ERR_INVALID_QP_ID;
11643 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11644 I40E_MAX_Q_PER_TC);
11645 bsf = rte_bsf32(qpnum_per_tc);
11648 * Configure TC and queue mapping parameters, for enabled TC,
11649 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11650 * default queue will serve it.
11653 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11654 if (vsi->enabled_tc & (1 << i)) {
11655 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11656 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11657 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11658 qp_idx += qpnum_per_tc;
11660 info->tc_mapping[i] = 0;
11663 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11664 if (vsi->type == I40E_VSI_SRIOV) {
11665 info->mapping_flags |=
11666 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11667 for (i = 0; i < vsi->nb_qps; i++)
11668 info->queue_mapping[i] =
11669 rte_cpu_to_le_16(vsi->base_queue + i);
11671 info->mapping_flags |=
11672 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11673 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11675 info->valid_sections |=
11676 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11678 return I40E_SUCCESS;
11682 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11683 * @veb: VEB to be configured
11684 * @tc_map: enabled TC bitmap
11686 * Returns 0 on success, negative value on failure
11688 static enum i40e_status_code
11689 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11691 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11692 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11693 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11694 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11695 enum i40e_status_code ret = I40E_SUCCESS;
11699 /* Check if enabled_tc is same as existing or new TCs */
11700 if (veb->enabled_tc == tc_map)
11703 /* configure tc bandwidth */
11704 memset(&veb_bw, 0, sizeof(veb_bw));
11705 veb_bw.tc_valid_bits = tc_map;
11706 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11707 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11708 if (tc_map & BIT_ULL(i))
11709 veb_bw.tc_bw_share_credits[i] = 1;
11711 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11715 "AQ command Config switch_comp BW allocation per TC failed = %d",
11716 hw->aq.asq_last_status);
11720 memset(&ets_query, 0, sizeof(ets_query));
11721 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11723 if (ret != I40E_SUCCESS) {
11725 "Failed to get switch_comp ETS configuration %u",
11726 hw->aq.asq_last_status);
11729 memset(&bw_query, 0, sizeof(bw_query));
11730 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11732 if (ret != I40E_SUCCESS) {
11734 "Failed to get switch_comp bandwidth configuration %u",
11735 hw->aq.asq_last_status);
11739 /* store and print out BW info */
11740 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11741 veb->bw_info.bw_max = ets_query.tc_bw_max;
11742 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11743 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11744 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11745 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11746 I40E_16_BIT_WIDTH);
11747 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11748 veb->bw_info.bw_ets_share_credits[i] =
11749 bw_query.tc_bw_share_credits[i];
11750 veb->bw_info.bw_ets_credits[i] =
11751 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11752 /* 4 bits per TC, 4th bit is reserved */
11753 veb->bw_info.bw_ets_max[i] =
11754 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11755 RTE_LEN2MASK(3, uint8_t));
11756 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11757 veb->bw_info.bw_ets_share_credits[i]);
11758 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11759 veb->bw_info.bw_ets_credits[i]);
11760 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11761 veb->bw_info.bw_ets_max[i]);
11764 veb->enabled_tc = tc_map;
11771 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11772 * @vsi: VSI to be configured
11773 * @tc_map: enabled TC bitmap
11775 * Returns 0 on success, negative value on failure
11777 static enum i40e_status_code
11778 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11780 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11781 struct i40e_vsi_context ctxt;
11782 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11783 enum i40e_status_code ret = I40E_SUCCESS;
11786 /* Check if enabled_tc is same as existing or new TCs */
11787 if (vsi->enabled_tc == tc_map)
11790 /* configure tc bandwidth */
11791 memset(&bw_data, 0, sizeof(bw_data));
11792 bw_data.tc_valid_bits = tc_map;
11793 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11794 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11795 if (tc_map & BIT_ULL(i))
11796 bw_data.tc_bw_credits[i] = 1;
11798 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11801 "AQ command Config VSI BW allocation per TC failed = %d",
11802 hw->aq.asq_last_status);
11805 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11806 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11808 /* Update Queue Pairs Mapping for currently enabled UPs */
11809 ctxt.seid = vsi->seid;
11810 ctxt.pf_num = hw->pf_id;
11812 ctxt.uplink_seid = vsi->uplink_seid;
11813 ctxt.info = vsi->info;
11815 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11819 /* Update the VSI after updating the VSI queue-mapping information */
11820 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11822 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11823 hw->aq.asq_last_status);
11826 /* update the local VSI info with updated queue map */
11827 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11828 sizeof(vsi->info.tc_mapping));
11829 rte_memcpy(&vsi->info.queue_mapping,
11830 &ctxt.info.queue_mapping,
11831 sizeof(vsi->info.queue_mapping));
11832 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11833 vsi->info.valid_sections = 0;
11835 /* query and update current VSI BW information */
11836 ret = i40e_vsi_get_bw_config(vsi);
11839 "Failed updating vsi bw info, err %s aq_err %s",
11840 i40e_stat_str(hw, ret),
11841 i40e_aq_str(hw, hw->aq.asq_last_status));
11845 vsi->enabled_tc = tc_map;
11852 * i40e_dcb_hw_configure - program the dcb setting to hw
11853 * @pf: pf the configuration is taken on
11854 * @new_cfg: new configuration
11855 * @tc_map: enabled TC bitmap
11857 * Returns 0 on success, negative value on failure
11859 static enum i40e_status_code
11860 i40e_dcb_hw_configure(struct i40e_pf *pf,
11861 struct i40e_dcbx_config *new_cfg,
11864 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11865 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11866 struct i40e_vsi *main_vsi = pf->main_vsi;
11867 struct i40e_vsi_list *vsi_list;
11868 enum i40e_status_code ret;
11872 /* Use the FW API if FW > v4.4*/
11873 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11874 (hw->aq.fw_maj_ver >= 5))) {
11876 "FW < v4.4, can not use FW LLDP API to configure DCB");
11877 return I40E_ERR_FIRMWARE_API_VERSION;
11880 /* Check if need reconfiguration */
11881 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11882 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11883 return I40E_SUCCESS;
11886 /* Copy the new config to the current config */
11887 *old_cfg = *new_cfg;
11888 old_cfg->etsrec = old_cfg->etscfg;
11889 ret = i40e_set_dcb_config(hw);
11891 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11892 i40e_stat_str(hw, ret),
11893 i40e_aq_str(hw, hw->aq.asq_last_status));
11896 /* set receive Arbiter to RR mode and ETS scheme by default */
11897 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11898 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11899 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11900 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11901 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11902 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11903 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11904 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11905 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11906 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11907 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11908 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11909 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11911 /* get local mib to check whether it is configured correctly */
11913 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11914 /* Get Local DCB Config */
11915 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11916 &hw->local_dcbx_config);
11918 /* if Veb is created, need to update TC of it at first */
11919 if (main_vsi->veb) {
11920 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11922 PMD_INIT_LOG(WARNING,
11923 "Failed configuring TC for VEB seid=%d",
11924 main_vsi->veb->seid);
11926 /* Update each VSI */
11927 i40e_vsi_config_tc(main_vsi, tc_map);
11928 if (main_vsi->veb) {
11929 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11930 /* Beside main VSI and VMDQ VSIs, only enable default
11931 * TC for other VSIs
11933 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11934 ret = i40e_vsi_config_tc(vsi_list->vsi,
11937 ret = i40e_vsi_config_tc(vsi_list->vsi,
11938 I40E_DEFAULT_TCMAP);
11940 PMD_INIT_LOG(WARNING,
11941 "Failed configuring TC for VSI seid=%d",
11942 vsi_list->vsi->seid);
11946 return I40E_SUCCESS;
11950 * i40e_dcb_init_configure - initial dcb config
11951 * @dev: device being configured
11952 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11954 * Returns 0 on success, negative value on failure
11957 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11959 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11963 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11964 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11968 /* DCB initialization:
11969 * Update DCB configuration from the Firmware and configure
11970 * LLDP MIB change event.
11972 if (sw_dcb == TRUE) {
11973 /* Stopping lldp is necessary for DPDK, but it will cause
11974 * DCB init failed. For i40e_init_dcb(), the prerequisite
11975 * for successful initialization of DCB is that LLDP is
11976 * enabled. So it is needed to start lldp before DCB init
11977 * and stop it after initialization.
11979 ret = i40e_aq_start_lldp(hw, true, NULL);
11980 if (ret != I40E_SUCCESS)
11981 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11983 ret = i40e_init_dcb(hw, true);
11984 /* If lldp agent is stopped, the return value from
11985 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11986 * adminq status. Otherwise, it should return success.
11988 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11989 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11990 memset(&hw->local_dcbx_config, 0,
11991 sizeof(struct i40e_dcbx_config));
11992 /* set dcb default configuration */
11993 hw->local_dcbx_config.etscfg.willing = 0;
11994 hw->local_dcbx_config.etscfg.maxtcs = 0;
11995 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11996 hw->local_dcbx_config.etscfg.tsatable[0] =
11998 /* all UPs mapping to TC0 */
11999 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12000 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
12001 hw->local_dcbx_config.etsrec =
12002 hw->local_dcbx_config.etscfg;
12003 hw->local_dcbx_config.pfc.willing = 0;
12004 hw->local_dcbx_config.pfc.pfccap =
12005 I40E_MAX_TRAFFIC_CLASS;
12006 /* FW needs one App to configure HW */
12007 hw->local_dcbx_config.numapps = 1;
12008 hw->local_dcbx_config.app[0].selector =
12009 I40E_APP_SEL_ETHTYPE;
12010 hw->local_dcbx_config.app[0].priority = 3;
12011 hw->local_dcbx_config.app[0].protocolid =
12012 I40E_APP_PROTOID_FCOE;
12013 ret = i40e_set_dcb_config(hw);
12016 "default dcb config fails. err = %d, aq_err = %d.",
12017 ret, hw->aq.asq_last_status);
12022 "DCB initialization in FW fails, err = %d, aq_err = %d.",
12023 ret, hw->aq.asq_last_status);
12027 if (i40e_need_stop_lldp(dev)) {
12028 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
12029 if (ret != I40E_SUCCESS)
12030 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
12033 ret = i40e_aq_start_lldp(hw, true, NULL);
12034 if (ret != I40E_SUCCESS)
12035 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
12037 ret = i40e_init_dcb(hw, true);
12039 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
12041 "HW doesn't support DCBX offload.");
12046 "DCBX configuration failed, err = %d, aq_err = %d.",
12047 ret, hw->aq.asq_last_status);
12055 * i40e_dcb_setup - setup dcb related config
12056 * @dev: device being configured
12058 * Returns 0 on success, negative value on failure
12061 i40e_dcb_setup(struct rte_eth_dev *dev)
12063 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12064 struct i40e_dcbx_config dcb_cfg;
12065 uint8_t tc_map = 0;
12068 if ((pf->flags & I40E_FLAG_DCB) == 0) {
12069 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12073 if (pf->vf_num != 0)
12074 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12076 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12078 PMD_INIT_LOG(ERR, "invalid dcb config");
12081 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12083 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12091 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12092 struct rte_eth_dcb_info *dcb_info)
12094 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12096 struct i40e_vsi *vsi = pf->main_vsi;
12097 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12098 uint16_t bsf, tc_mapping;
12101 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12102 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12104 dcb_info->nb_tcs = 1;
12105 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12106 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12107 for (i = 0; i < dcb_info->nb_tcs; i++)
12108 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12110 /* get queue mapping if vmdq is disabled */
12111 if (!pf->nb_cfg_vmdq_vsi) {
12112 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12113 if (!(vsi->enabled_tc & (1 << i)))
12115 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12116 dcb_info->tc_queue.tc_rxq[j][i].base =
12117 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12118 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12119 dcb_info->tc_queue.tc_txq[j][i].base =
12120 dcb_info->tc_queue.tc_rxq[j][i].base;
12121 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12122 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12123 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12124 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12125 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12130 /* get queue mapping if vmdq is enabled */
12132 vsi = pf->vmdq[j].vsi;
12133 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12134 if (!(vsi->enabled_tc & (1 << i)))
12136 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12137 dcb_info->tc_queue.tc_rxq[j][i].base =
12138 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12139 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12140 dcb_info->tc_queue.tc_txq[j][i].base =
12141 dcb_info->tc_queue.tc_rxq[j][i].base;
12142 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12143 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12144 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12145 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12146 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12149 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12154 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12156 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12157 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12158 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12159 uint16_t msix_intr;
12161 msix_intr = intr_handle->intr_vec[queue_id];
12162 if (msix_intr == I40E_MISC_VEC_ID)
12163 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12164 I40E_PFINT_DYN_CTL0_INTENA_MASK |
12165 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12166 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12169 I40E_PFINT_DYN_CTLN(msix_intr -
12170 I40E_RX_VEC_START),
12171 I40E_PFINT_DYN_CTLN_INTENA_MASK |
12172 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12173 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12175 I40E_WRITE_FLUSH(hw);
12176 rte_intr_ack(&pci_dev->intr_handle);
12182 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12184 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12185 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12187 uint16_t msix_intr;
12189 msix_intr = intr_handle->intr_vec[queue_id];
12190 if (msix_intr == I40E_MISC_VEC_ID)
12191 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12192 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12195 I40E_PFINT_DYN_CTLN(msix_intr -
12196 I40E_RX_VEC_START),
12197 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12198 I40E_WRITE_FLUSH(hw);
12204 * This function is used to check if the register is valid.
12205 * Below is the valid registers list for X722 only:
12209 * 0x208e00--0x209000
12210 * 0x20be00--0x20c000
12211 * 0x263c00--0x264000
12212 * 0x265c00--0x266000
12214 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12216 if ((type != I40E_MAC_X722) &&
12217 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12218 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12219 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12220 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12221 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12222 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12223 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12229 static int i40e_get_regs(struct rte_eth_dev *dev,
12230 struct rte_dev_reg_info *regs)
12232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12233 uint32_t *ptr_data = regs->data;
12234 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12235 const struct i40e_reg_info *reg_info;
12237 if (ptr_data == NULL) {
12238 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12239 regs->width = sizeof(uint32_t);
12243 /* The first few registers have to be read using AQ operations */
12245 while (i40e_regs_adminq[reg_idx].name) {
12246 reg_info = &i40e_regs_adminq[reg_idx++];
12247 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12249 arr_idx2 <= reg_info->count2;
12251 reg_offset = arr_idx * reg_info->stride1 +
12252 arr_idx2 * reg_info->stride2;
12253 reg_offset += reg_info->base_addr;
12254 ptr_data[reg_offset >> 2] =
12255 i40e_read_rx_ctl(hw, reg_offset);
12259 /* The remaining registers can be read using primitives */
12261 while (i40e_regs_others[reg_idx].name) {
12262 reg_info = &i40e_regs_others[reg_idx++];
12263 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12265 arr_idx2 <= reg_info->count2;
12267 reg_offset = arr_idx * reg_info->stride1 +
12268 arr_idx2 * reg_info->stride2;
12269 reg_offset += reg_info->base_addr;
12270 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12271 ptr_data[reg_offset >> 2] = 0;
12273 ptr_data[reg_offset >> 2] =
12274 I40E_READ_REG(hw, reg_offset);
12281 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12283 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12285 /* Convert word count to byte count */
12286 return hw->nvm.sr_size << 1;
12289 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12290 struct rte_dev_eeprom_info *eeprom)
12292 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12293 uint16_t *data = eeprom->data;
12294 uint16_t offset, length, cnt_words;
12297 offset = eeprom->offset >> 1;
12298 length = eeprom->length >> 1;
12299 cnt_words = length;
12301 if (offset > hw->nvm.sr_size ||
12302 offset + length > hw->nvm.sr_size) {
12303 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12307 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12309 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12310 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12311 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12318 static int i40e_get_module_info(struct rte_eth_dev *dev,
12319 struct rte_eth_dev_module_info *modinfo)
12321 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12322 uint32_t sff8472_comp = 0;
12323 uint32_t sff8472_swap = 0;
12324 uint32_t sff8636_rev = 0;
12325 i40e_status status;
12328 /* Check if firmware supports reading module EEPROM. */
12329 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12331 "Module EEPROM memory read not supported. "
12332 "Please update the NVM image.\n");
12336 status = i40e_update_link_info(hw);
12340 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12342 "Cannot read module EEPROM memory. "
12343 "No module connected.\n");
12347 type = hw->phy.link_info.module_type[0];
12350 case I40E_MODULE_TYPE_SFP:
12351 status = i40e_aq_get_phy_register(hw,
12352 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12353 I40E_I2C_EEPROM_DEV_ADDR, 1,
12354 I40E_MODULE_SFF_8472_COMP,
12355 &sff8472_comp, NULL);
12359 status = i40e_aq_get_phy_register(hw,
12360 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12361 I40E_I2C_EEPROM_DEV_ADDR, 1,
12362 I40E_MODULE_SFF_8472_SWAP,
12363 &sff8472_swap, NULL);
12367 /* Check if the module requires address swap to access
12368 * the other EEPROM memory page.
12370 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12371 PMD_DRV_LOG(WARNING,
12372 "Module address swap to access "
12373 "page 0xA2 is not supported.\n");
12374 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12375 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12376 } else if (sff8472_comp == 0x00) {
12377 /* Module is not SFF-8472 compliant */
12378 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12379 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12381 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12382 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12385 case I40E_MODULE_TYPE_QSFP_PLUS:
12386 /* Read from memory page 0. */
12387 status = i40e_aq_get_phy_register(hw,
12388 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12390 I40E_MODULE_REVISION_ADDR,
12391 &sff8636_rev, NULL);
12394 /* Determine revision compliance byte */
12395 if (sff8636_rev > 0x02) {
12396 /* Module is SFF-8636 compliant */
12397 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12398 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12400 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12401 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12404 case I40E_MODULE_TYPE_QSFP28:
12405 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12406 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12409 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12415 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12416 struct rte_dev_eeprom_info *info)
12418 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12419 bool is_sfp = false;
12420 i40e_status status;
12422 uint32_t value = 0;
12425 if (!info || !info->length || !info->data)
12428 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12432 for (i = 0; i < info->length; i++) {
12433 u32 offset = i + info->offset;
12434 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12436 /* Check if we need to access the other memory page */
12438 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12439 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12440 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12443 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12444 /* Compute memory page number and offset. */
12445 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12449 status = i40e_aq_get_phy_register(hw,
12450 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12451 addr, 1, offset, &value, NULL);
12454 data[i] = (uint8_t)value;
12459 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12460 struct rte_ether_addr *mac_addr)
12462 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12464 struct i40e_vsi *vsi = pf->main_vsi;
12465 struct i40e_mac_filter_info mac_filter;
12466 struct i40e_mac_filter *f;
12469 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12470 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12474 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12475 if (rte_is_same_ether_addr(&pf->dev_addr,
12476 &f->mac_info.mac_addr))
12481 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12485 mac_filter = f->mac_info;
12486 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12487 if (ret != I40E_SUCCESS) {
12488 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12491 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12492 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12493 if (ret != I40E_SUCCESS) {
12494 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12497 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12499 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12500 mac_addr->addr_bytes, NULL);
12501 if (ret != I40E_SUCCESS) {
12502 PMD_DRV_LOG(ERR, "Failed to change mac");
12510 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12512 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12513 struct rte_eth_dev_data *dev_data = pf->dev_data;
12514 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12517 /* check if mtu is within the allowed range */
12518 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12521 /* mtu setting is forbidden if port is start */
12522 if (dev_data->dev_started) {
12523 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12524 dev_data->port_id);
12528 if (frame_size > RTE_ETHER_MAX_LEN)
12529 dev_data->dev_conf.rxmode.offloads |=
12530 DEV_RX_OFFLOAD_JUMBO_FRAME;
12532 dev_data->dev_conf.rxmode.offloads &=
12533 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12535 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12540 /* Restore ethertype filter */
12542 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12544 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12545 struct i40e_ethertype_filter_list
12546 *ethertype_list = &pf->ethertype.ethertype_list;
12547 struct i40e_ethertype_filter *f;
12548 struct i40e_control_filter_stats stats;
12551 TAILQ_FOREACH(f, ethertype_list, rules) {
12553 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12554 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12555 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12556 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12557 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12559 memset(&stats, 0, sizeof(stats));
12560 i40e_aq_add_rem_control_packet_filter(hw,
12561 f->input.mac_addr.addr_bytes,
12562 f->input.ether_type,
12563 flags, pf->main_vsi->seid,
12564 f->queue, 1, &stats, NULL);
12566 PMD_DRV_LOG(INFO, "Ethertype filter:"
12567 " mac_etype_used = %u, etype_used = %u,"
12568 " mac_etype_free = %u, etype_free = %u",
12569 stats.mac_etype_used, stats.etype_used,
12570 stats.mac_etype_free, stats.etype_free);
12573 /* Restore tunnel filter */
12575 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12577 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12578 struct i40e_vsi *vsi;
12579 struct i40e_pf_vf *vf;
12580 struct i40e_tunnel_filter_list
12581 *tunnel_list = &pf->tunnel.tunnel_list;
12582 struct i40e_tunnel_filter *f;
12583 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12584 bool big_buffer = 0;
12586 TAILQ_FOREACH(f, tunnel_list, rules) {
12588 vsi = pf->main_vsi;
12590 vf = &pf->vfs[f->vf_id];
12593 memset(&cld_filter, 0, sizeof(cld_filter));
12594 rte_ether_addr_copy((struct rte_ether_addr *)
12595 &f->input.outer_mac,
12596 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12597 rte_ether_addr_copy((struct rte_ether_addr *)
12598 &f->input.inner_mac,
12599 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12600 cld_filter.element.inner_vlan = f->input.inner_vlan;
12601 cld_filter.element.flags = f->input.flags;
12602 cld_filter.element.tenant_id = f->input.tenant_id;
12603 cld_filter.element.queue_number = f->queue;
12604 rte_memcpy(cld_filter.general_fields,
12605 f->input.general_fields,
12606 sizeof(f->input.general_fields));
12608 if (((f->input.flags &
12609 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12610 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12612 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12613 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12615 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12616 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12620 i40e_aq_add_cloud_filters_bb(hw,
12621 vsi->seid, &cld_filter, 1);
12623 i40e_aq_add_cloud_filters(hw, vsi->seid,
12624 &cld_filter.element, 1);
12628 /* Restore RSS filter */
12630 i40e_rss_filter_restore(struct i40e_pf *pf)
12632 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12633 struct i40e_rss_filter *filter;
12635 TAILQ_FOREACH(filter, list, next) {
12636 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12641 i40e_filter_restore(struct i40e_pf *pf)
12643 i40e_ethertype_filter_restore(pf);
12644 i40e_tunnel_filter_restore(pf);
12645 i40e_fdir_filter_restore(pf);
12646 i40e_rss_filter_restore(pf);
12650 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12652 if (strcmp(dev->device->driver->name, drv->driver.name))
12659 is_i40e_supported(struct rte_eth_dev *dev)
12661 return is_device_supported(dev, &rte_i40e_pmd);
12664 struct i40e_customized_pctype*
12665 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12669 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12670 if (pf->customized_pctype[i].index == index)
12671 return &pf->customized_pctype[i];
12677 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12678 uint32_t pkg_size, uint32_t proto_num,
12679 struct rte_pmd_i40e_proto_info *proto,
12680 enum rte_pmd_i40e_package_op op)
12682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12683 uint32_t pctype_num;
12684 struct rte_pmd_i40e_ptype_info *pctype;
12685 uint32_t buff_size;
12686 struct i40e_customized_pctype *new_pctype = NULL;
12688 uint8_t pctype_value;
12693 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12694 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12695 PMD_DRV_LOG(ERR, "Unsupported operation.");
12699 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12700 (uint8_t *)&pctype_num, sizeof(pctype_num),
12701 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12703 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12707 PMD_DRV_LOG(INFO, "No new pctype added");
12711 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12712 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12714 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12717 /* get information about new pctype list */
12718 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12719 (uint8_t *)pctype, buff_size,
12720 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12722 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12727 /* Update customized pctype. */
12728 for (i = 0; i < pctype_num; i++) {
12729 pctype_value = pctype[i].ptype_id;
12730 memset(name, 0, sizeof(name));
12731 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12732 proto_id = pctype[i].protocols[j];
12733 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12735 for (n = 0; n < proto_num; n++) {
12736 if (proto[n].proto_id != proto_id)
12738 strlcat(name, proto[n].name, sizeof(name));
12739 strlcat(name, "_", sizeof(name));
12743 name[strlen(name) - 1] = '\0';
12744 PMD_DRV_LOG(INFO, "name = %s\n", name);
12745 if (!strcmp(name, "GTPC"))
12747 i40e_find_customized_pctype(pf,
12748 I40E_CUSTOMIZED_GTPC);
12749 else if (!strcmp(name, "GTPU_IPV4"))
12751 i40e_find_customized_pctype(pf,
12752 I40E_CUSTOMIZED_GTPU_IPV4);
12753 else if (!strcmp(name, "GTPU_IPV6"))
12755 i40e_find_customized_pctype(pf,
12756 I40E_CUSTOMIZED_GTPU_IPV6);
12757 else if (!strcmp(name, "GTPU"))
12759 i40e_find_customized_pctype(pf,
12760 I40E_CUSTOMIZED_GTPU);
12761 else if (!strcmp(name, "IPV4_L2TPV3"))
12763 i40e_find_customized_pctype(pf,
12764 I40E_CUSTOMIZED_IPV4_L2TPV3);
12765 else if (!strcmp(name, "IPV6_L2TPV3"))
12767 i40e_find_customized_pctype(pf,
12768 I40E_CUSTOMIZED_IPV6_L2TPV3);
12769 else if (!strcmp(name, "IPV4_ESP"))
12771 i40e_find_customized_pctype(pf,
12772 I40E_CUSTOMIZED_ESP_IPV4);
12773 else if (!strcmp(name, "IPV6_ESP"))
12775 i40e_find_customized_pctype(pf,
12776 I40E_CUSTOMIZED_ESP_IPV6);
12777 else if (!strcmp(name, "IPV4_UDP_ESP"))
12779 i40e_find_customized_pctype(pf,
12780 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12781 else if (!strcmp(name, "IPV6_UDP_ESP"))
12783 i40e_find_customized_pctype(pf,
12784 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12785 else if (!strcmp(name, "IPV4_AH"))
12787 i40e_find_customized_pctype(pf,
12788 I40E_CUSTOMIZED_AH_IPV4);
12789 else if (!strcmp(name, "IPV6_AH"))
12791 i40e_find_customized_pctype(pf,
12792 I40E_CUSTOMIZED_AH_IPV6);
12794 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12795 new_pctype->pctype = pctype_value;
12796 new_pctype->valid = true;
12798 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12799 new_pctype->valid = false;
12809 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12810 uint32_t pkg_size, uint32_t proto_num,
12811 struct rte_pmd_i40e_proto_info *proto,
12812 enum rte_pmd_i40e_package_op op)
12814 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12815 uint16_t port_id = dev->data->port_id;
12816 uint32_t ptype_num;
12817 struct rte_pmd_i40e_ptype_info *ptype;
12818 uint32_t buff_size;
12820 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12825 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12826 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12827 PMD_DRV_LOG(ERR, "Unsupported operation.");
12831 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12832 rte_pmd_i40e_ptype_mapping_reset(port_id);
12836 /* get information about new ptype num */
12837 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12838 (uint8_t *)&ptype_num, sizeof(ptype_num),
12839 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12841 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12845 PMD_DRV_LOG(INFO, "No new ptype added");
12849 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12850 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12852 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12856 /* get information about new ptype list */
12857 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12858 (uint8_t *)ptype, buff_size,
12859 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12861 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12866 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12867 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12868 if (!ptype_mapping) {
12869 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12874 /* Update ptype mapping table. */
12875 for (i = 0; i < ptype_num; i++) {
12876 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12877 ptype_mapping[i].sw_ptype = 0;
12879 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12880 proto_id = ptype[i].protocols[j];
12881 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12883 for (n = 0; n < proto_num; n++) {
12884 if (proto[n].proto_id != proto_id)
12886 memset(name, 0, sizeof(name));
12887 strcpy(name, proto[n].name);
12888 PMD_DRV_LOG(INFO, "name = %s\n", name);
12889 if (!strncasecmp(name, "PPPOE", 5))
12890 ptype_mapping[i].sw_ptype |=
12891 RTE_PTYPE_L2_ETHER_PPPOE;
12892 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12894 ptype_mapping[i].sw_ptype |=
12895 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12896 ptype_mapping[i].sw_ptype |=
12898 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12900 ptype_mapping[i].sw_ptype |=
12901 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12902 ptype_mapping[i].sw_ptype |=
12903 RTE_PTYPE_INNER_L4_FRAG;
12904 } else if (!strncasecmp(name, "OIPV4", 5)) {
12905 ptype_mapping[i].sw_ptype |=
12906 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12908 } else if (!strncasecmp(name, "IPV4", 4) &&
12910 ptype_mapping[i].sw_ptype |=
12911 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12912 else if (!strncasecmp(name, "IPV4", 4) &&
12914 ptype_mapping[i].sw_ptype |=
12915 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12916 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12918 ptype_mapping[i].sw_ptype |=
12919 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12920 ptype_mapping[i].sw_ptype |=
12922 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12924 ptype_mapping[i].sw_ptype |=
12925 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12926 ptype_mapping[i].sw_ptype |=
12927 RTE_PTYPE_INNER_L4_FRAG;
12928 } else if (!strncasecmp(name, "OIPV6", 5)) {
12929 ptype_mapping[i].sw_ptype |=
12930 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12932 } else if (!strncasecmp(name, "IPV6", 4) &&
12934 ptype_mapping[i].sw_ptype |=
12935 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12936 else if (!strncasecmp(name, "IPV6", 4) &&
12938 ptype_mapping[i].sw_ptype |=
12939 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12940 else if (!strncasecmp(name, "UDP", 3) &&
12942 ptype_mapping[i].sw_ptype |=
12944 else if (!strncasecmp(name, "UDP", 3) &&
12946 ptype_mapping[i].sw_ptype |=
12947 RTE_PTYPE_INNER_L4_UDP;
12948 else if (!strncasecmp(name, "TCP", 3) &&
12950 ptype_mapping[i].sw_ptype |=
12952 else if (!strncasecmp(name, "TCP", 3) &&
12954 ptype_mapping[i].sw_ptype |=
12955 RTE_PTYPE_INNER_L4_TCP;
12956 else if (!strncasecmp(name, "SCTP", 4) &&
12958 ptype_mapping[i].sw_ptype |=
12960 else if (!strncasecmp(name, "SCTP", 4) &&
12962 ptype_mapping[i].sw_ptype |=
12963 RTE_PTYPE_INNER_L4_SCTP;
12964 else if ((!strncasecmp(name, "ICMP", 4) ||
12965 !strncasecmp(name, "ICMPV6", 6)) &&
12967 ptype_mapping[i].sw_ptype |=
12969 else if ((!strncasecmp(name, "ICMP", 4) ||
12970 !strncasecmp(name, "ICMPV6", 6)) &&
12972 ptype_mapping[i].sw_ptype |=
12973 RTE_PTYPE_INNER_L4_ICMP;
12974 else if (!strncasecmp(name, "GTPC", 4)) {
12975 ptype_mapping[i].sw_ptype |=
12976 RTE_PTYPE_TUNNEL_GTPC;
12978 } else if (!strncasecmp(name, "GTPU", 4)) {
12979 ptype_mapping[i].sw_ptype |=
12980 RTE_PTYPE_TUNNEL_GTPU;
12982 } else if (!strncasecmp(name, "ESP", 3)) {
12983 ptype_mapping[i].sw_ptype |=
12984 RTE_PTYPE_TUNNEL_ESP;
12986 } else if (!strncasecmp(name, "GRENAT", 6)) {
12987 ptype_mapping[i].sw_ptype |=
12988 RTE_PTYPE_TUNNEL_GRENAT;
12990 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12991 !strncasecmp(name, "L2TPV2", 6) ||
12992 !strncasecmp(name, "L2TPV3", 6)) {
12993 ptype_mapping[i].sw_ptype |=
12994 RTE_PTYPE_TUNNEL_L2TP;
13003 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
13006 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
13008 rte_free(ptype_mapping);
13014 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
13015 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
13017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
13018 uint32_t proto_num;
13019 struct rte_pmd_i40e_proto_info *proto;
13020 uint32_t buff_size;
13024 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
13025 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
13026 PMD_DRV_LOG(ERR, "Unsupported operation.");
13030 /* get information about protocol number */
13031 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13032 (uint8_t *)&proto_num, sizeof(proto_num),
13033 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
13035 PMD_DRV_LOG(ERR, "Failed to get protocol number");
13039 PMD_DRV_LOG(INFO, "No new protocol added");
13043 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
13044 proto = rte_zmalloc("new_proto", buff_size, 0);
13046 PMD_DRV_LOG(ERR, "Failed to allocate memory");
13050 /* get information about protocol list */
13051 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13052 (uint8_t *)proto, buff_size,
13053 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13055 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13060 /* Check if GTP is supported. */
13061 for (i = 0; i < proto_num; i++) {
13062 if (!strncmp(proto[i].name, "GTP", 3)) {
13063 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13064 pf->gtp_support = true;
13066 pf->gtp_support = false;
13071 /* Check if ESP is supported. */
13072 for (i = 0; i < proto_num; i++) {
13073 if (!strncmp(proto[i].name, "ESP", 3)) {
13074 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13075 pf->esp_support = true;
13077 pf->esp_support = false;
13082 /* Update customized pctype info */
13083 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13084 proto_num, proto, op);
13086 PMD_DRV_LOG(INFO, "No pctype is updated.");
13088 /* Update customized ptype info */
13089 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13090 proto_num, proto, op);
13092 PMD_DRV_LOG(INFO, "No ptype is updated.");
13097 /* Create a QinQ cloud filter
13099 * The Fortville NIC has limited resources for tunnel filters,
13100 * so we can only reuse existing filters.
13102 * In step 1 we define which Field Vector fields can be used for
13104 * As we do not have the inner tag defined as a field,
13105 * we have to define it first, by reusing one of L1 entries.
13107 * In step 2 we are replacing one of existing filter types with
13108 * a new one for QinQ.
13109 * As we reusing L1 and replacing L2, some of the default filter
13110 * types will disappear,which depends on L1 and L2 entries we reuse.
13112 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13114 * 1. Create L1 filter of outer vlan (12b) which will be in use
13115 * later when we define the cloud filter.
13116 * a. Valid_flags.replace_cloud = 0
13117 * b. Old_filter = 10 (Stag_Inner_Vlan)
13118 * c. New_filter = 0x10
13119 * d. TR bit = 0xff (optional, not used here)
13120 * e. Buffer – 2 entries:
13121 * i. Byte 0 = 8 (outer vlan FV index).
13123 * Byte 2-3 = 0x0fff
13124 * ii. Byte 0 = 37 (inner vlan FV index).
13126 * Byte 2-3 = 0x0fff
13129 * 2. Create cloud filter using two L1 filters entries: stag and
13130 * new filter(outer vlan+ inner vlan)
13131 * a. Valid_flags.replace_cloud = 1
13132 * b. Old_filter = 1 (instead of outer IP)
13133 * c. New_filter = 0x10
13134 * d. Buffer – 2 entries:
13135 * i. Byte 0 = 0x80 | 7 (valid | Stag).
13136 * Byte 1-3 = 0 (rsv)
13137 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13138 * Byte 9-11 = 0 (rsv)
13141 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13143 int ret = -ENOTSUP;
13144 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
13145 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
13146 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13147 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13149 if (pf->support_multi_driver) {
13150 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13155 memset(&filter_replace, 0,
13156 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13157 memset(&filter_replace_buf, 0,
13158 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13160 /* create L1 filter */
13161 filter_replace.old_filter_type =
13162 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13163 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13164 filter_replace.tr_bit = 0;
13166 /* Prepare the buffer, 2 entries */
13167 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13168 filter_replace_buf.data[0] |=
13169 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13170 /* Field Vector 12b mask */
13171 filter_replace_buf.data[2] = 0xff;
13172 filter_replace_buf.data[3] = 0x0f;
13173 filter_replace_buf.data[4] =
13174 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13175 filter_replace_buf.data[4] |=
13176 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13177 /* Field Vector 12b mask */
13178 filter_replace_buf.data[6] = 0xff;
13179 filter_replace_buf.data[7] = 0x0f;
13180 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13181 &filter_replace_buf);
13182 if (ret != I40E_SUCCESS)
13185 if (filter_replace.old_filter_type !=
13186 filter_replace.new_filter_type)
13187 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13188 " original: 0x%x, new: 0x%x",
13190 filter_replace.old_filter_type,
13191 filter_replace.new_filter_type);
13193 /* Apply the second L2 cloud filter */
13194 memset(&filter_replace, 0,
13195 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13196 memset(&filter_replace_buf, 0,
13197 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13199 /* create L2 filter, input for L2 filter will be L1 filter */
13200 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13201 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13202 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13204 /* Prepare the buffer, 2 entries */
13205 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13206 filter_replace_buf.data[0] |=
13207 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13208 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13209 filter_replace_buf.data[4] |=
13210 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13211 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13212 &filter_replace_buf);
13213 if (!ret && (filter_replace.old_filter_type !=
13214 filter_replace.new_filter_type))
13215 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13216 " original: 0x%x, new: 0x%x",
13218 filter_replace.old_filter_type,
13219 filter_replace.new_filter_type);
13225 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13226 const struct rte_flow_action_rss *in)
13228 if (in->key_len > RTE_DIM(out->key) ||
13229 in->queue_num > RTE_DIM(out->queue))
13231 if (!in->key && in->key_len)
13233 out->conf = (struct rte_flow_action_rss){
13235 .level = in->level,
13236 .types = in->types,
13237 .key_len = in->key_len,
13238 .queue_num = in->queue_num,
13239 .queue = memcpy(out->queue, in->queue,
13240 sizeof(*in->queue) * in->queue_num),
13243 out->conf.key = memcpy(out->key, in->key, in->key_len);
13247 /* Write HENA register to enable hash */
13249 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13251 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13252 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13256 ret = i40e_set_rss_key(pf->main_vsi, key,
13257 rss_conf->conf.key_len);
13261 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13262 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13263 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13264 I40E_WRITE_FLUSH(hw);
13269 /* Configure hash input set */
13271 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13273 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13274 struct rte_eth_input_set_conf conf;
13279 static const struct {
13281 enum rte_eth_input_set_field field;
13282 } inset_match_table[] = {
13283 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13284 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13285 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13286 RTE_ETH_INPUT_SET_L3_DST_IP4},
13287 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13288 RTE_ETH_INPUT_SET_UNKNOWN},
13289 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13290 RTE_ETH_INPUT_SET_UNKNOWN},
13292 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13293 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13294 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13295 RTE_ETH_INPUT_SET_L3_DST_IP4},
13296 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13297 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13298 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13299 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13301 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13302 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13303 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13304 RTE_ETH_INPUT_SET_L3_DST_IP4},
13305 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13306 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13307 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13308 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13310 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13311 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13312 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13313 RTE_ETH_INPUT_SET_L3_DST_IP4},
13314 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13315 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13316 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13317 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13319 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13320 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13321 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13322 RTE_ETH_INPUT_SET_L3_DST_IP4},
13323 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13324 RTE_ETH_INPUT_SET_UNKNOWN},
13325 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13326 RTE_ETH_INPUT_SET_UNKNOWN},
13328 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13329 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13330 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13331 RTE_ETH_INPUT_SET_L3_DST_IP6},
13332 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13333 RTE_ETH_INPUT_SET_UNKNOWN},
13334 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13335 RTE_ETH_INPUT_SET_UNKNOWN},
13337 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13338 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13339 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13340 RTE_ETH_INPUT_SET_L3_DST_IP6},
13341 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13342 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13343 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13344 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13346 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13347 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13348 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13349 RTE_ETH_INPUT_SET_L3_DST_IP6},
13350 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13351 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13352 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13353 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13355 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13356 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13357 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13358 RTE_ETH_INPUT_SET_L3_DST_IP6},
13359 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13360 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13361 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13362 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13364 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13365 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13366 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13367 RTE_ETH_INPUT_SET_L3_DST_IP6},
13368 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13369 RTE_ETH_INPUT_SET_UNKNOWN},
13370 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13371 RTE_ETH_INPUT_SET_UNKNOWN},
13374 mask0 = types & pf->adapter->flow_types_mask;
13375 conf.op = RTE_ETH_INPUT_SET_SELECT;
13376 conf.inset_size = 0;
13377 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13378 if (mask0 & (1ULL << i)) {
13379 conf.flow_type = i;
13384 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13385 if ((types & inset_match_table[j].type) ==
13386 inset_match_table[j].type) {
13387 if (inset_match_table[j].field ==
13388 RTE_ETH_INPUT_SET_UNKNOWN)
13391 conf.field[conf.inset_size] =
13392 inset_match_table[j].field;
13397 if (conf.inset_size) {
13398 ret = i40e_hash_filter_inset_select(hw, &conf);
13406 /* Look up the conflicted rule then mark it as invalid */
13408 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13409 struct i40e_rte_flow_rss_conf *conf)
13411 struct i40e_rss_filter *rss_item;
13412 uint64_t rss_inset;
13414 /* Clear input set bits before comparing the pctype */
13415 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13416 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13418 /* Look up the conflicted rule then mark it as invalid */
13419 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13420 if (!rss_item->rss_filter_info.valid)
13423 if (conf->conf.queue_num &&
13424 rss_item->rss_filter_info.conf.queue_num)
13425 rss_item->rss_filter_info.valid = false;
13427 if (conf->conf.types &&
13428 (rss_item->rss_filter_info.conf.types &
13430 (conf->conf.types & rss_inset))
13431 rss_item->rss_filter_info.valid = false;
13433 if (conf->conf.func ==
13434 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13435 rss_item->rss_filter_info.conf.func ==
13436 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13437 rss_item->rss_filter_info.valid = false;
13441 /* Configure RSS hash function */
13443 i40e_rss_config_hash_function(struct i40e_pf *pf,
13444 struct i40e_rte_flow_rss_conf *conf)
13446 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13451 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13452 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13453 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13454 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13455 I40E_WRITE_FLUSH(hw);
13456 i40e_rss_mark_invalid_rule(pf, conf);
13460 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13462 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13463 I40E_WRITE_FLUSH(hw);
13464 i40e_rss_mark_invalid_rule(pf, conf);
13465 } else if (conf->conf.func ==
13466 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13467 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13469 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13470 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13471 if (mask0 & (1UL << i))
13475 if (i == UINT64_BIT)
13478 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13479 j < I40E_FILTER_PCTYPE_MAX; j++) {
13480 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13481 i40e_write_global_rx_ctl(hw,
13483 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13490 /* Enable RSS according to the configuration */
13492 i40e_rss_enable_hash(struct i40e_pf *pf,
13493 struct i40e_rte_flow_rss_conf *conf)
13495 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13496 struct i40e_rte_flow_rss_conf rss_conf;
13498 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13501 memset(&rss_conf, 0, sizeof(rss_conf));
13502 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13504 /* Configure hash input set */
13505 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13508 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13509 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13510 /* Random default keys */
13511 static uint32_t rss_key_default[] = {0x6b793944,
13512 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13513 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13514 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13516 rss_conf.conf.key = (uint8_t *)rss_key_default;
13517 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13520 "No valid RSS key config for i40e, using default\n");
13523 rss_conf.conf.types |= rss_info->conf.types;
13524 i40e_rss_hash_set(pf, &rss_conf);
13526 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13527 i40e_rss_config_hash_function(pf, conf);
13529 i40e_rss_mark_invalid_rule(pf, conf);
13534 /* Configure RSS queue region */
13536 i40e_rss_config_queue_region(struct i40e_pf *pf,
13537 struct i40e_rte_flow_rss_conf *conf)
13539 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13544 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13545 * It's necessary to calculate the actual PF queues that are configured.
13547 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13548 num = i40e_pf_calc_configured_queues_num(pf);
13550 num = pf->dev_data->nb_rx_queues;
13552 num = RTE_MIN(num, conf->conf.queue_num);
13553 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13558 "No PF queues are configured to enable RSS for port %u",
13559 pf->dev_data->port_id);
13563 /* Fill in redirection table */
13564 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13567 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13568 hw->func_caps.rss_table_entry_width) - 1));
13570 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13573 i40e_rss_mark_invalid_rule(pf, conf);
13578 /* Configure RSS hash function to default */
13580 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13581 struct i40e_rte_flow_rss_conf *conf)
13583 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13588 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13589 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13590 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13592 "Hash function already set to Toeplitz");
13593 I40E_WRITE_FLUSH(hw);
13597 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13599 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13600 I40E_WRITE_FLUSH(hw);
13601 } else if (conf->conf.func ==
13602 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13603 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13605 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13606 if (mask0 & (1UL << i))
13610 if (i == UINT64_BIT)
13613 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13614 j < I40E_FILTER_PCTYPE_MAX; j++) {
13615 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13616 i40e_write_global_rx_ctl(hw,
13625 /* Disable RSS hash and configure default input set */
13627 i40e_rss_disable_hash(struct i40e_pf *pf,
13628 struct i40e_rte_flow_rss_conf *conf)
13630 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13631 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13632 struct i40e_rte_flow_rss_conf rss_conf;
13635 memset(&rss_conf, 0, sizeof(rss_conf));
13636 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13638 /* Disable RSS hash */
13639 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13640 i40e_rss_hash_set(pf, &rss_conf);
13642 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13643 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13644 !(conf->conf.types & (1ULL << i)))
13647 /* Configure default input set */
13648 struct rte_eth_input_set_conf input_conf = {
13649 .op = RTE_ETH_INPUT_SET_SELECT,
13653 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13654 i40e_hash_filter_inset_select(hw, &input_conf);
13657 rss_info->conf.types = rss_conf.conf.types;
13659 i40e_rss_clear_hash_function(pf, conf);
13664 /* Configure RSS queue region to default */
13666 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13668 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13669 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13670 uint16_t queue[I40E_MAX_Q_PER_TC];
13671 uint32_t num_rxq, i;
13675 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13677 for (j = 0; j < num_rxq; j++)
13680 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13681 * It's necessary to calculate the actual PF queues that are configured.
13683 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13684 num = i40e_pf_calc_configured_queues_num(pf);
13686 num = pf->dev_data->nb_rx_queues;
13688 num = RTE_MIN(num, num_rxq);
13689 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13694 "No PF queues are configured to enable RSS for port %u",
13695 pf->dev_data->port_id);
13699 /* Fill in redirection table */
13700 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13703 lut = (lut << 8) | (queue[j] & ((0x1 <<
13704 hw->func_caps.rss_table_entry_width) - 1));
13706 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13709 rss_info->conf.queue_num = 0;
13710 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13716 i40e_config_rss_filter(struct i40e_pf *pf,
13717 struct i40e_rte_flow_rss_conf *conf, bool add)
13719 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13720 struct rte_flow_action_rss update_conf = rss_info->conf;
13724 if (conf->conf.queue_num) {
13725 /* Configure RSS queue region */
13726 ret = i40e_rss_config_queue_region(pf, conf);
13730 update_conf.queue_num = conf->conf.queue_num;
13731 update_conf.queue = conf->conf.queue;
13732 } else if (conf->conf.func ==
13733 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13734 /* Configure hash function */
13735 ret = i40e_rss_config_hash_function(pf, conf);
13739 update_conf.func = conf->conf.func;
13741 /* Configure hash enable and input set */
13742 ret = i40e_rss_enable_hash(pf, conf);
13746 update_conf.types |= conf->conf.types;
13747 update_conf.key = conf->conf.key;
13748 update_conf.key_len = conf->conf.key_len;
13751 /* Update RSS info in pf */
13752 if (i40e_rss_conf_init(rss_info, &update_conf))
13758 if (conf->conf.queue_num)
13759 i40e_rss_clear_queue_region(pf);
13760 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13761 i40e_rss_clear_hash_function(pf, conf);
13763 i40e_rss_disable_hash(pf, conf);
13769 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13770 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13771 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13772 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13774 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13775 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13777 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13778 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13781 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13782 ETH_I40E_FLOATING_VEB_ARG "=1"
13783 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13784 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13785 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13786 ETH_I40E_USE_LATEST_VEC "=0|1");